1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/module.h> 33 #include <rdma/ib_verbs.h> 34 #include <rdma/ib_addr.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <linux/netdevice.h> 37 #include <linux/iommu.h> 38 #include <linux/pci.h> 39 #include <net/addrconf.h> 40 41 #include <linux/qed/qed_chain.h> 42 #include <linux/qed/qed_if.h> 43 #include "qedr.h" 44 #include "verbs.h" 45 #include <rdma/qedr-abi.h> 46 47 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver"); 48 MODULE_AUTHOR("QLogic Corporation"); 49 MODULE_LICENSE("Dual BSD/GPL"); 50 51 #define QEDR_WQ_MULTIPLIER_DFT (3) 52 53 void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num, 54 enum ib_event_type type) 55 { 56 struct ib_event ibev; 57 58 ibev.device = &dev->ibdev; 59 ibev.element.port_num = port_num; 60 ibev.event = type; 61 62 ib_dispatch_event(&ibev); 63 } 64 65 static enum rdma_link_layer qedr_link_layer(struct ib_device *device, 66 u8 port_num) 67 { 68 return IB_LINK_LAYER_ETHERNET; 69 } 70 71 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str) 72 { 73 struct qedr_dev *qedr = get_qedr_dev(ibdev); 74 u32 fw_ver = (u32)qedr->attr.fw_ver; 75 76 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d", 77 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF, 78 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); 79 } 80 81 static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num) 82 { 83 struct qedr_dev *qdev; 84 85 qdev = get_qedr_dev(dev); 86 dev_hold(qdev->ndev); 87 88 /* The HW vendor's device driver must guarantee 89 * that this function returns NULL before the net device reaches 90 * NETDEV_UNREGISTER_FINAL state. 91 */ 92 return qdev->ndev; 93 } 94 95 static int qedr_register_device(struct qedr_dev *dev) 96 { 97 strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX); 98 99 dev->ibdev.node_guid = dev->attr.node_guid; 100 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC)); 101 dev->ibdev.owner = THIS_MODULE; 102 dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION; 103 104 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) | 105 QEDR_UVERBS(QUERY_DEVICE) | 106 QEDR_UVERBS(QUERY_PORT) | 107 QEDR_UVERBS(ALLOC_PD) | 108 QEDR_UVERBS(DEALLOC_PD) | 109 QEDR_UVERBS(CREATE_COMP_CHANNEL) | 110 QEDR_UVERBS(CREATE_CQ) | 111 QEDR_UVERBS(RESIZE_CQ) | 112 QEDR_UVERBS(DESTROY_CQ) | 113 QEDR_UVERBS(REQ_NOTIFY_CQ) | 114 QEDR_UVERBS(CREATE_QP) | 115 QEDR_UVERBS(MODIFY_QP) | 116 QEDR_UVERBS(QUERY_QP) | 117 QEDR_UVERBS(DESTROY_QP) | 118 QEDR_UVERBS(REG_MR) | 119 QEDR_UVERBS(DEREG_MR) | 120 QEDR_UVERBS(POLL_CQ) | 121 QEDR_UVERBS(POST_SEND) | 122 QEDR_UVERBS(POST_RECV); 123 124 dev->ibdev.phys_port_cnt = 1; 125 dev->ibdev.num_comp_vectors = dev->num_cnq; 126 dev->ibdev.node_type = RDMA_NODE_IB_CA; 127 128 dev->ibdev.query_device = qedr_query_device; 129 dev->ibdev.query_port = qedr_query_port; 130 dev->ibdev.modify_port = qedr_modify_port; 131 132 dev->ibdev.query_gid = qedr_query_gid; 133 dev->ibdev.add_gid = qedr_add_gid; 134 dev->ibdev.del_gid = qedr_del_gid; 135 136 dev->ibdev.alloc_ucontext = qedr_alloc_ucontext; 137 dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext; 138 dev->ibdev.mmap = qedr_mmap; 139 140 dev->ibdev.alloc_pd = qedr_alloc_pd; 141 dev->ibdev.dealloc_pd = qedr_dealloc_pd; 142 143 dev->ibdev.create_cq = qedr_create_cq; 144 dev->ibdev.destroy_cq = qedr_destroy_cq; 145 dev->ibdev.resize_cq = qedr_resize_cq; 146 dev->ibdev.req_notify_cq = qedr_arm_cq; 147 148 dev->ibdev.create_qp = qedr_create_qp; 149 dev->ibdev.modify_qp = qedr_modify_qp; 150 dev->ibdev.query_qp = qedr_query_qp; 151 dev->ibdev.destroy_qp = qedr_destroy_qp; 152 153 dev->ibdev.query_pkey = qedr_query_pkey; 154 155 dev->ibdev.create_ah = qedr_create_ah; 156 dev->ibdev.destroy_ah = qedr_destroy_ah; 157 158 dev->ibdev.get_dma_mr = qedr_get_dma_mr; 159 dev->ibdev.dereg_mr = qedr_dereg_mr; 160 dev->ibdev.reg_user_mr = qedr_reg_user_mr; 161 dev->ibdev.alloc_mr = qedr_alloc_mr; 162 dev->ibdev.map_mr_sg = qedr_map_mr_sg; 163 164 dev->ibdev.poll_cq = qedr_poll_cq; 165 dev->ibdev.post_send = qedr_post_send; 166 dev->ibdev.post_recv = qedr_post_recv; 167 168 dev->ibdev.process_mad = qedr_process_mad; 169 dev->ibdev.get_port_immutable = qedr_port_immutable; 170 dev->ibdev.get_netdev = qedr_get_netdev; 171 172 dev->ibdev.dev.parent = &dev->pdev->dev; 173 174 dev->ibdev.get_link_layer = qedr_link_layer; 175 dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str; 176 177 return ib_register_device(&dev->ibdev, NULL); 178 } 179 180 /* This function allocates fast-path status block memory */ 181 static int qedr_alloc_mem_sb(struct qedr_dev *dev, 182 struct qed_sb_info *sb_info, u16 sb_id) 183 { 184 struct status_block *sb_virt; 185 dma_addr_t sb_phys; 186 int rc; 187 188 sb_virt = dma_alloc_coherent(&dev->pdev->dev, 189 sizeof(*sb_virt), &sb_phys, GFP_KERNEL); 190 if (!sb_virt) 191 return -ENOMEM; 192 193 rc = dev->ops->common->sb_init(dev->cdev, sb_info, 194 sb_virt, sb_phys, sb_id, 195 QED_SB_TYPE_CNQ); 196 if (rc) { 197 pr_err("Status block initialization failed\n"); 198 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt), 199 sb_virt, sb_phys); 200 return rc; 201 } 202 203 return 0; 204 } 205 206 static void qedr_free_mem_sb(struct qedr_dev *dev, 207 struct qed_sb_info *sb_info, int sb_id) 208 { 209 if (sb_info->sb_virt) { 210 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id); 211 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt), 212 (void *)sb_info->sb_virt, sb_info->sb_phys); 213 } 214 } 215 216 static void qedr_free_resources(struct qedr_dev *dev) 217 { 218 int i; 219 220 for (i = 0; i < dev->num_cnq; i++) { 221 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 222 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 223 } 224 225 kfree(dev->cnq_array); 226 kfree(dev->sb_array); 227 kfree(dev->sgid_tbl); 228 } 229 230 static int qedr_alloc_resources(struct qedr_dev *dev) 231 { 232 struct qedr_cnq *cnq; 233 __le16 *cons_pi; 234 u16 n_entries; 235 int i, rc; 236 237 dev->sgid_tbl = kzalloc(sizeof(union ib_gid) * 238 QEDR_MAX_SGID, GFP_KERNEL); 239 if (!dev->sgid_tbl) 240 return -ENOMEM; 241 242 spin_lock_init(&dev->sgid_lock); 243 244 /* Allocate Status blocks for CNQ */ 245 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array), 246 GFP_KERNEL); 247 if (!dev->sb_array) { 248 rc = -ENOMEM; 249 goto err1; 250 } 251 252 dev->cnq_array = kcalloc(dev->num_cnq, 253 sizeof(*dev->cnq_array), GFP_KERNEL); 254 if (!dev->cnq_array) { 255 rc = -ENOMEM; 256 goto err2; 257 } 258 259 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev); 260 261 /* Allocate CNQ PBLs */ 262 n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE); 263 for (i = 0; i < dev->num_cnq; i++) { 264 cnq = &dev->cnq_array[i]; 265 266 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i], 267 dev->sb_start + i); 268 if (rc) 269 goto err3; 270 271 rc = dev->ops->common->chain_alloc(dev->cdev, 272 QED_CHAIN_USE_TO_CONSUME, 273 QED_CHAIN_MODE_PBL, 274 QED_CHAIN_CNT_TYPE_U16, 275 n_entries, 276 sizeof(struct regpair *), 277 &cnq->pbl, NULL); 278 if (rc) 279 goto err4; 280 281 cnq->dev = dev; 282 cnq->sb = &dev->sb_array[i]; 283 cons_pi = dev->sb_array[i].sb_virt->pi_array; 284 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX]; 285 cnq->index = i; 286 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev)); 287 288 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n", 289 i, qed_chain_get_cons_idx(&cnq->pbl)); 290 } 291 292 return 0; 293 err4: 294 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 295 err3: 296 for (--i; i >= 0; i--) { 297 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 298 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 299 } 300 kfree(dev->cnq_array); 301 err2: 302 kfree(dev->sb_array); 303 err1: 304 kfree(dev->sgid_tbl); 305 return rc; 306 } 307 308 /* QEDR sysfs interface */ 309 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 310 char *buf) 311 { 312 struct qedr_dev *dev = dev_get_drvdata(device); 313 314 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor); 315 } 316 317 static ssize_t show_hca_type(struct device *device, 318 struct device_attribute *attr, char *buf) 319 { 320 return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET"); 321 } 322 323 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 324 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL); 325 326 static struct device_attribute *qedr_attributes[] = { 327 &dev_attr_hw_rev, 328 &dev_attr_hca_type 329 }; 330 331 static void qedr_remove_sysfiles(struct qedr_dev *dev) 332 { 333 int i; 334 335 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++) 336 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]); 337 } 338 339 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev) 340 { 341 struct pci_dev *bridge; 342 u32 ctl2, cap2; 343 u16 flags; 344 int rc; 345 346 bridge = pdev->bus->self; 347 if (!bridge) 348 goto disable; 349 350 /* Check atomic routing support all the way to root complex */ 351 while (bridge->bus->parent) { 352 rc = pcie_capability_read_word(bridge, PCI_EXP_FLAGS, &flags); 353 if (rc || ((flags & PCI_EXP_FLAGS_VERS) < 2)) 354 goto disable; 355 356 rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap2); 357 if (rc) 358 goto disable; 359 360 rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl2); 361 if (rc) 362 goto disable; 363 364 if (!(cap2 & PCI_EXP_DEVCAP2_ATOMIC_ROUTE) || 365 (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)) 366 goto disable; 367 bridge = bridge->bus->parent->self; 368 } 369 370 rc = pcie_capability_read_word(bridge, PCI_EXP_FLAGS, &flags); 371 if (rc || ((flags & PCI_EXP_FLAGS_VERS) < 2)) 372 goto disable; 373 374 rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap2); 375 if (rc || !(cap2 & PCI_EXP_DEVCAP2_ATOMIC_COMP64)) 376 goto disable; 377 378 /* Set atomic operations */ 379 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 380 PCI_EXP_DEVCTL2_ATOMIC_REQ); 381 dev->atomic_cap = IB_ATOMIC_GLOB; 382 383 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n"); 384 385 return; 386 387 disable: 388 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2, 389 PCI_EXP_DEVCTL2_ATOMIC_REQ); 390 dev->atomic_cap = IB_ATOMIC_NONE; 391 392 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n"); 393 394 } 395 396 static const struct qed_rdma_ops *qed_ops; 397 398 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 399 400 static irqreturn_t qedr_irq_handler(int irq, void *handle) 401 { 402 u16 hw_comp_cons, sw_comp_cons; 403 struct qedr_cnq *cnq = handle; 404 struct regpair *cq_handle; 405 struct qedr_cq *cq; 406 407 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0); 408 409 qed_sb_update_sb_idx(cnq->sb); 410 411 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 412 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 413 414 /* Align protocol-index and chain reads */ 415 rmb(); 416 417 while (sw_comp_cons != hw_comp_cons) { 418 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl); 419 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 420 cq_handle->lo); 421 422 if (cq == NULL) { 423 DP_ERR(cnq->dev, 424 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n", 425 cq_handle->hi, cq_handle->lo, sw_comp_cons, 426 hw_comp_cons); 427 428 break; 429 } 430 431 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) { 432 DP_ERR(cnq->dev, 433 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n", 434 cq_handle->hi, cq_handle->lo, cq); 435 break; 436 } 437 438 cq->arm_flags = 0; 439 440 if (!cq->destroyed && cq->ibcq.comp_handler) 441 (*cq->ibcq.comp_handler) 442 (&cq->ibcq, cq->ibcq.cq_context); 443 444 /* The CQ's CNQ notification counter is checked before 445 * destroying the CQ in a busy-wait loop that waits for all of 446 * the CQ's CNQ interrupts to be processed. It is increased 447 * here, only after the completion handler, to ensure that the 448 * the handler is not running when the CQ is destroyed. 449 */ 450 cq->cnq_notif++; 451 452 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 453 454 cnq->n_comp++; 455 } 456 457 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, 458 sw_comp_cons); 459 460 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1); 461 462 return IRQ_HANDLED; 463 } 464 465 static void qedr_sync_free_irqs(struct qedr_dev *dev) 466 { 467 u32 vector; 468 int i; 469 470 for (i = 0; i < dev->int_info.used_cnt; i++) { 471 if (dev->int_info.msix_cnt) { 472 vector = dev->int_info.msix[i * dev->num_hwfns].vector; 473 synchronize_irq(vector); 474 free_irq(vector, &dev->cnq_array[i]); 475 } 476 } 477 478 dev->int_info.used_cnt = 0; 479 } 480 481 static int qedr_req_msix_irqs(struct qedr_dev *dev) 482 { 483 int i, rc = 0; 484 485 if (dev->num_cnq > dev->int_info.msix_cnt) { 486 DP_ERR(dev, 487 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n", 488 dev->num_cnq, dev->int_info.msix_cnt); 489 return -EINVAL; 490 } 491 492 for (i = 0; i < dev->num_cnq; i++) { 493 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector, 494 qedr_irq_handler, 0, dev->cnq_array[i].name, 495 &dev->cnq_array[i]); 496 if (rc) { 497 DP_ERR(dev, "Request cnq %d irq failed\n", i); 498 qedr_sync_free_irqs(dev); 499 } else { 500 DP_DEBUG(dev, QEDR_MSG_INIT, 501 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n", 502 dev->cnq_array[i].name, i, 503 &dev->cnq_array[i]); 504 dev->int_info.used_cnt++; 505 } 506 } 507 508 return rc; 509 } 510 511 static int qedr_setup_irqs(struct qedr_dev *dev) 512 { 513 int rc; 514 515 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n"); 516 517 /* Learn Interrupt configuration */ 518 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq); 519 if (rc < 0) 520 return rc; 521 522 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info); 523 if (rc) { 524 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n"); 525 return rc; 526 } 527 528 if (dev->int_info.msix_cnt) { 529 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n", 530 dev->int_info.msix_cnt); 531 rc = qedr_req_msix_irqs(dev); 532 if (rc) 533 return rc; 534 } 535 536 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n"); 537 538 return 0; 539 } 540 541 static int qedr_set_device_attr(struct qedr_dev *dev) 542 { 543 struct qed_rdma_device *qed_attr; 544 struct qedr_device_attr *attr; 545 u32 page_size; 546 547 /* Part 1 - query core capabilities */ 548 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx); 549 550 /* Part 2 - check capabilities */ 551 page_size = ~dev->attr.page_size_caps + 1; 552 if (page_size > PAGE_SIZE) { 553 DP_ERR(dev, 554 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n", 555 PAGE_SIZE, page_size); 556 return -ENODEV; 557 } 558 559 /* Part 3 - copy and update capabilities */ 560 attr = &dev->attr; 561 attr->vendor_id = qed_attr->vendor_id; 562 attr->vendor_part_id = qed_attr->vendor_part_id; 563 attr->hw_ver = qed_attr->hw_ver; 564 attr->fw_ver = qed_attr->fw_ver; 565 attr->node_guid = qed_attr->node_guid; 566 attr->sys_image_guid = qed_attr->sys_image_guid; 567 attr->max_cnq = qed_attr->max_cnq; 568 attr->max_sge = qed_attr->max_sge; 569 attr->max_inline = qed_attr->max_inline; 570 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE); 571 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE); 572 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc; 573 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc; 574 attr->max_dev_resp_rd_atomic_resc = 575 qed_attr->max_dev_resp_rd_atomic_resc; 576 attr->max_cq = qed_attr->max_cq; 577 attr->max_qp = qed_attr->max_qp; 578 attr->max_mr = qed_attr->max_mr; 579 attr->max_mr_size = qed_attr->max_mr_size; 580 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES); 581 attr->max_mw = qed_attr->max_mw; 582 attr->max_fmr = qed_attr->max_fmr; 583 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl; 584 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size; 585 attr->max_pd = qed_attr->max_pd; 586 attr->max_ah = qed_attr->max_ah; 587 attr->max_pkey = qed_attr->max_pkey; 588 attr->max_srq = qed_attr->max_srq; 589 attr->max_srq_wr = qed_attr->max_srq_wr; 590 attr->dev_caps = qed_attr->dev_caps; 591 attr->page_size_caps = qed_attr->page_size_caps; 592 attr->dev_ack_delay = qed_attr->dev_ack_delay; 593 attr->reserved_lkey = qed_attr->reserved_lkey; 594 attr->bad_pkey_counter = qed_attr->bad_pkey_counter; 595 attr->max_stats_queues = qed_attr->max_stats_queues; 596 597 return 0; 598 } 599 600 void qedr_unaffiliated_event(void *context, u8 event_code) 601 { 602 pr_err("unaffiliated event not implemented yet\n"); 603 } 604 605 void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle) 606 { 607 #define EVENT_TYPE_NOT_DEFINED 0 608 #define EVENT_TYPE_CQ 1 609 #define EVENT_TYPE_QP 2 610 struct qedr_dev *dev = (struct qedr_dev *)context; 611 struct regpair *async_handle = (struct regpair *)fw_handle; 612 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo; 613 u8 event_type = EVENT_TYPE_NOT_DEFINED; 614 struct ib_event event; 615 struct ib_cq *ibcq; 616 struct ib_qp *ibqp; 617 struct qedr_cq *cq; 618 struct qedr_qp *qp; 619 620 switch (e_code) { 621 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 622 event.event = IB_EVENT_CQ_ERR; 623 event_type = EVENT_TYPE_CQ; 624 break; 625 case ROCE_ASYNC_EVENT_SQ_DRAINED: 626 event.event = IB_EVENT_SQ_DRAINED; 627 event_type = EVENT_TYPE_QP; 628 break; 629 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 630 event.event = IB_EVENT_QP_FATAL; 631 event_type = EVENT_TYPE_QP; 632 break; 633 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 634 event.event = IB_EVENT_QP_REQ_ERR; 635 event_type = EVENT_TYPE_QP; 636 break; 637 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 638 event.event = IB_EVENT_QP_ACCESS_ERR; 639 event_type = EVENT_TYPE_QP; 640 break; 641 default: 642 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code, 643 roce_handle64); 644 } 645 646 switch (event_type) { 647 case EVENT_TYPE_CQ: 648 cq = (struct qedr_cq *)(uintptr_t)roce_handle64; 649 if (cq) { 650 ibcq = &cq->ibcq; 651 if (ibcq->event_handler) { 652 event.device = ibcq->device; 653 event.element.cq = ibcq; 654 ibcq->event_handler(&event, ibcq->cq_context); 655 } 656 } else { 657 WARN(1, 658 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n", 659 roce_handle64); 660 } 661 DP_ERR(dev, "CQ event %d on hanlde %p\n", e_code, cq); 662 break; 663 case EVENT_TYPE_QP: 664 qp = (struct qedr_qp *)(uintptr_t)roce_handle64; 665 if (qp) { 666 ibqp = &qp->ibqp; 667 if (ibqp->event_handler) { 668 event.device = ibqp->device; 669 event.element.qp = ibqp; 670 ibqp->event_handler(&event, ibqp->qp_context); 671 } 672 } else { 673 WARN(1, 674 "Error: QP event with NULL pointer ibqp. Handle=%llx\n", 675 roce_handle64); 676 } 677 DP_ERR(dev, "QP event %d on hanlde %p\n", e_code, qp); 678 break; 679 default: 680 break; 681 } 682 } 683 684 static int qedr_init_hw(struct qedr_dev *dev) 685 { 686 struct qed_rdma_add_user_out_params out_params; 687 struct qed_rdma_start_in_params *in_params; 688 struct qed_rdma_cnq_params *cur_pbl; 689 struct qed_rdma_events events; 690 dma_addr_t p_phys_table; 691 u32 page_cnt; 692 int rc = 0; 693 int i; 694 695 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 696 if (!in_params) { 697 rc = -ENOMEM; 698 goto out; 699 } 700 701 in_params->desired_cnq = dev->num_cnq; 702 for (i = 0; i < dev->num_cnq; i++) { 703 cur_pbl = &in_params->cnq_pbl_list[i]; 704 705 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl); 706 cur_pbl->num_pbl_pages = page_cnt; 707 708 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 709 cur_pbl->pbl_ptr = (u64)p_phys_table; 710 } 711 712 events.affiliated_event = qedr_affiliated_event; 713 events.unaffiliated_event = qedr_unaffiliated_event; 714 events.context = dev; 715 716 in_params->events = &events; 717 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS; 718 in_params->max_mtu = dev->ndev->mtu; 719 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr); 720 721 rc = dev->ops->rdma_init(dev->cdev, in_params); 722 if (rc) 723 goto out; 724 725 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params); 726 if (rc) 727 goto out; 728 729 dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr; 730 dev->db_phys_addr = out_params.dpi_phys_addr; 731 dev->db_size = out_params.dpi_size; 732 dev->dpi = out_params.dpi; 733 734 rc = qedr_set_device_attr(dev); 735 out: 736 kfree(in_params); 737 if (rc) 738 DP_ERR(dev, "Init HW Failed rc = %d\n", rc); 739 740 return rc; 741 } 742 743 void qedr_stop_hw(struct qedr_dev *dev) 744 { 745 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi); 746 dev->ops->rdma_stop(dev->rdma_ctx); 747 } 748 749 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev, 750 struct net_device *ndev) 751 { 752 struct qed_dev_rdma_info dev_info; 753 struct qedr_dev *dev; 754 int rc = 0, i; 755 756 dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev)); 757 if (!dev) { 758 pr_err("Unable to allocate ib device\n"); 759 return NULL; 760 } 761 762 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n"); 763 764 dev->pdev = pdev; 765 dev->ndev = ndev; 766 dev->cdev = cdev; 767 768 qed_ops = qed_get_rdma_ops(); 769 if (!qed_ops) { 770 DP_ERR(dev, "Failed to get qed roce operations\n"); 771 goto init_err; 772 } 773 774 dev->ops = qed_ops; 775 rc = qed_ops->fill_dev_info(cdev, &dev_info); 776 if (rc) 777 goto init_err; 778 779 dev->user_dpm_enabled = dev_info.user_dpm_enabled; 780 dev->num_hwfns = dev_info.common.num_hwfns; 781 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev); 782 783 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev); 784 if (!dev->num_cnq) { 785 DP_ERR(dev, "not enough CNQ resources.\n"); 786 goto init_err; 787 } 788 789 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT; 790 791 qedr_pci_set_atomic(dev, pdev); 792 793 rc = qedr_alloc_resources(dev); 794 if (rc) 795 goto init_err; 796 797 rc = qedr_init_hw(dev); 798 if (rc) 799 goto alloc_err; 800 801 rc = qedr_setup_irqs(dev); 802 if (rc) 803 goto irq_err; 804 805 rc = qedr_register_device(dev); 806 if (rc) { 807 DP_ERR(dev, "Unable to allocate register device\n"); 808 goto reg_err; 809 } 810 811 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++) 812 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i])) 813 goto sysfs_err; 814 815 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 816 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 817 818 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n"); 819 return dev; 820 821 sysfs_err: 822 ib_unregister_device(&dev->ibdev); 823 reg_err: 824 qedr_sync_free_irqs(dev); 825 irq_err: 826 qedr_stop_hw(dev); 827 alloc_err: 828 qedr_free_resources(dev); 829 init_err: 830 ib_dealloc_device(&dev->ibdev); 831 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc); 832 833 return NULL; 834 } 835 836 static void qedr_remove(struct qedr_dev *dev) 837 { 838 /* First unregister with stack to stop all the active traffic 839 * of the registered clients. 840 */ 841 qedr_remove_sysfiles(dev); 842 ib_unregister_device(&dev->ibdev); 843 844 qedr_stop_hw(dev); 845 qedr_sync_free_irqs(dev); 846 qedr_free_resources(dev); 847 ib_dealloc_device(&dev->ibdev); 848 } 849 850 static void qedr_close(struct qedr_dev *dev) 851 { 852 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 853 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR); 854 } 855 856 static void qedr_shutdown(struct qedr_dev *dev) 857 { 858 qedr_close(dev); 859 qedr_remove(dev); 860 } 861 862 static void qedr_open(struct qedr_dev *dev) 863 { 864 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 865 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 866 } 867 868 static void qedr_mac_address_change(struct qedr_dev *dev) 869 { 870 union ib_gid *sgid = &dev->sgid_tbl[0]; 871 u8 guid[8], mac_addr[6]; 872 int rc; 873 874 /* Update SGID */ 875 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr); 876 guid[0] = mac_addr[0] ^ 2; 877 guid[1] = mac_addr[1]; 878 guid[2] = mac_addr[2]; 879 guid[3] = 0xff; 880 guid[4] = 0xfe; 881 guid[5] = mac_addr[3]; 882 guid[6] = mac_addr[4]; 883 guid[7] = mac_addr[5]; 884 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL); 885 memcpy(&sgid->raw[8], guid, sizeof(guid)); 886 887 /* Update LL2 */ 888 rc = dev->ops->ll2_set_mac_filter(dev->cdev, 889 dev->gsi_ll2_mac_address, 890 dev->ndev->dev_addr); 891 892 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr); 893 894 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE); 895 896 if (rc) 897 DP_ERR(dev, "Error updating mac filter\n"); 898 } 899 900 /* event handling via NIC driver ensures that all the NIC specific 901 * initialization done before RoCE driver notifies 902 * event to stack. 903 */ 904 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event) 905 { 906 switch (event) { 907 case QEDE_UP: 908 qedr_open(dev); 909 break; 910 case QEDE_DOWN: 911 qedr_close(dev); 912 break; 913 case QEDE_CLOSE: 914 qedr_shutdown(dev); 915 break; 916 case QEDE_CHANGE_ADDR: 917 qedr_mac_address_change(dev); 918 break; 919 default: 920 pr_err("Event not supported\n"); 921 } 922 } 923 924 static struct qedr_driver qedr_drv = { 925 .name = "qedr_driver", 926 .add = qedr_add, 927 .remove = qedr_remove, 928 .notify = qedr_notify, 929 }; 930 931 static int __init qedr_init_module(void) 932 { 933 return qede_rdma_register_driver(&qedr_drv); 934 } 935 936 static void __exit qedr_exit_module(void) 937 { 938 qede_rdma_unregister_driver(&qedr_drv); 939 } 940 941 module_init(qedr_init_module); 942 module_exit(qedr_exit_module); 943