1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/module.h> 33 #include <rdma/ib_verbs.h> 34 #include <rdma/ib_addr.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/iw_cm.h> 37 #include <rdma/ib_mad.h> 38 #include <linux/netdevice.h> 39 #include <linux/iommu.h> 40 #include <linux/pci.h> 41 #include <net/addrconf.h> 42 #include <linux/idr.h> 43 44 #include <linux/qed/qed_chain.h> 45 #include <linux/qed/qed_if.h> 46 #include "qedr.h" 47 #include "verbs.h" 48 #include <rdma/qedr-abi.h> 49 #include "qedr_iw_cm.h" 50 51 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver"); 52 MODULE_AUTHOR("QLogic Corporation"); 53 MODULE_LICENSE("Dual BSD/GPL"); 54 55 #define QEDR_WQ_MULTIPLIER_DFT (3) 56 57 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num, 58 enum ib_event_type type) 59 { 60 struct ib_event ibev; 61 62 ibev.device = &dev->ibdev; 63 ibev.element.port_num = port_num; 64 ibev.event = type; 65 66 ib_dispatch_event(&ibev); 67 } 68 69 static enum rdma_link_layer qedr_link_layer(struct ib_device *device, 70 u8 port_num) 71 { 72 return IB_LINK_LAYER_ETHERNET; 73 } 74 75 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str) 76 { 77 struct qedr_dev *qedr = get_qedr_dev(ibdev); 78 u32 fw_ver = (u32)qedr->attr.fw_ver; 79 80 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d", 81 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF, 82 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); 83 } 84 85 static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num) 86 { 87 struct qedr_dev *qdev; 88 89 qdev = get_qedr_dev(dev); 90 dev_hold(qdev->ndev); 91 92 /* The HW vendor's device driver must guarantee 93 * that this function returns NULL before the net device has finished 94 * NETDEV_UNREGISTER state. 95 */ 96 return qdev->ndev; 97 } 98 99 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num, 100 struct ib_port_immutable *immutable) 101 { 102 struct ib_port_attr attr; 103 int err; 104 105 err = qedr_query_port(ibdev, port_num, &attr); 106 if (err) 107 return err; 108 109 immutable->pkey_tbl_len = attr.pkey_tbl_len; 110 immutable->gid_tbl_len = attr.gid_tbl_len; 111 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 112 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 113 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 114 115 return 0; 116 } 117 118 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num, 119 struct ib_port_immutable *immutable) 120 { 121 struct ib_port_attr attr; 122 int err; 123 124 err = qedr_query_port(ibdev, port_num, &attr); 125 if (err) 126 return err; 127 128 immutable->pkey_tbl_len = 1; 129 immutable->gid_tbl_len = 1; 130 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 131 immutable->max_mad_size = 0; 132 133 return 0; 134 } 135 136 /* QEDR sysfs interface */ 137 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 138 char *buf) 139 { 140 struct qedr_dev *dev = dev_get_drvdata(device); 141 142 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor); 143 } 144 static DEVICE_ATTR_RO(hw_rev); 145 146 static ssize_t hca_type_show(struct device *device, 147 struct device_attribute *attr, char *buf) 148 { 149 return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET"); 150 } 151 static DEVICE_ATTR_RO(hca_type); 152 153 static struct attribute *qedr_attributes[] = { 154 &dev_attr_hw_rev.attr, 155 &dev_attr_hca_type.attr, 156 NULL 157 }; 158 159 static const struct attribute_group qedr_attr_group = { 160 .attrs = qedr_attributes, 161 }; 162 163 static int qedr_iw_register_device(struct qedr_dev *dev) 164 { 165 dev->ibdev.node_type = RDMA_NODE_RNIC; 166 dev->ibdev.query_gid = qedr_iw_query_gid; 167 168 dev->ibdev.get_port_immutable = qedr_iw_port_immutable; 169 170 dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL); 171 if (!dev->ibdev.iwcm) 172 return -ENOMEM; 173 174 dev->ibdev.iwcm->connect = qedr_iw_connect; 175 dev->ibdev.iwcm->accept = qedr_iw_accept; 176 dev->ibdev.iwcm->reject = qedr_iw_reject; 177 dev->ibdev.iwcm->create_listen = qedr_iw_create_listen; 178 dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen; 179 dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref; 180 dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref; 181 dev->ibdev.iwcm->get_qp = qedr_iw_get_qp; 182 183 memcpy(dev->ibdev.iwcm->ifname, 184 dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname)); 185 186 return 0; 187 } 188 189 static void qedr_roce_register_device(struct qedr_dev *dev) 190 { 191 dev->ibdev.node_type = RDMA_NODE_IB_CA; 192 193 dev->ibdev.get_port_immutable = qedr_roce_port_immutable; 194 } 195 196 static int qedr_register_device(struct qedr_dev *dev) 197 { 198 int rc; 199 200 dev->ibdev.node_guid = dev->attr.node_guid; 201 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC)); 202 dev->ibdev.owner = THIS_MODULE; 203 dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION; 204 205 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) | 206 QEDR_UVERBS(QUERY_DEVICE) | 207 QEDR_UVERBS(QUERY_PORT) | 208 QEDR_UVERBS(ALLOC_PD) | 209 QEDR_UVERBS(DEALLOC_PD) | 210 QEDR_UVERBS(CREATE_COMP_CHANNEL) | 211 QEDR_UVERBS(CREATE_CQ) | 212 QEDR_UVERBS(RESIZE_CQ) | 213 QEDR_UVERBS(DESTROY_CQ) | 214 QEDR_UVERBS(REQ_NOTIFY_CQ) | 215 QEDR_UVERBS(CREATE_QP) | 216 QEDR_UVERBS(MODIFY_QP) | 217 QEDR_UVERBS(QUERY_QP) | 218 QEDR_UVERBS(DESTROY_QP) | 219 QEDR_UVERBS(CREATE_SRQ) | 220 QEDR_UVERBS(DESTROY_SRQ) | 221 QEDR_UVERBS(QUERY_SRQ) | 222 QEDR_UVERBS(MODIFY_SRQ) | 223 QEDR_UVERBS(POST_SRQ_RECV) | 224 QEDR_UVERBS(REG_MR) | 225 QEDR_UVERBS(DEREG_MR) | 226 QEDR_UVERBS(POLL_CQ) | 227 QEDR_UVERBS(POST_SEND) | 228 QEDR_UVERBS(POST_RECV); 229 230 if (IS_IWARP(dev)) { 231 rc = qedr_iw_register_device(dev); 232 if (rc) 233 return rc; 234 } else { 235 qedr_roce_register_device(dev); 236 } 237 238 dev->ibdev.phys_port_cnt = 1; 239 dev->ibdev.num_comp_vectors = dev->num_cnq; 240 241 dev->ibdev.query_device = qedr_query_device; 242 dev->ibdev.query_port = qedr_query_port; 243 dev->ibdev.modify_port = qedr_modify_port; 244 245 dev->ibdev.alloc_ucontext = qedr_alloc_ucontext; 246 dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext; 247 dev->ibdev.mmap = qedr_mmap; 248 249 dev->ibdev.alloc_pd = qedr_alloc_pd; 250 dev->ibdev.dealloc_pd = qedr_dealloc_pd; 251 252 dev->ibdev.create_cq = qedr_create_cq; 253 dev->ibdev.destroy_cq = qedr_destroy_cq; 254 dev->ibdev.resize_cq = qedr_resize_cq; 255 dev->ibdev.req_notify_cq = qedr_arm_cq; 256 257 dev->ibdev.create_qp = qedr_create_qp; 258 dev->ibdev.modify_qp = qedr_modify_qp; 259 dev->ibdev.query_qp = qedr_query_qp; 260 dev->ibdev.destroy_qp = qedr_destroy_qp; 261 262 dev->ibdev.create_srq = qedr_create_srq; 263 dev->ibdev.destroy_srq = qedr_destroy_srq; 264 dev->ibdev.modify_srq = qedr_modify_srq; 265 dev->ibdev.query_srq = qedr_query_srq; 266 dev->ibdev.post_srq_recv = qedr_post_srq_recv; 267 dev->ibdev.query_pkey = qedr_query_pkey; 268 269 dev->ibdev.create_ah = qedr_create_ah; 270 dev->ibdev.destroy_ah = qedr_destroy_ah; 271 272 dev->ibdev.get_dma_mr = qedr_get_dma_mr; 273 dev->ibdev.dereg_mr = qedr_dereg_mr; 274 dev->ibdev.reg_user_mr = qedr_reg_user_mr; 275 dev->ibdev.alloc_mr = qedr_alloc_mr; 276 dev->ibdev.map_mr_sg = qedr_map_mr_sg; 277 278 dev->ibdev.poll_cq = qedr_poll_cq; 279 dev->ibdev.post_send = qedr_post_send; 280 dev->ibdev.post_recv = qedr_post_recv; 281 282 dev->ibdev.process_mad = qedr_process_mad; 283 284 dev->ibdev.get_netdev = qedr_get_netdev; 285 286 dev->ibdev.dev.parent = &dev->pdev->dev; 287 288 dev->ibdev.get_link_layer = qedr_link_layer; 289 dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str; 290 rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group); 291 dev->ibdev.driver_id = RDMA_DRIVER_QEDR; 292 return ib_register_device(&dev->ibdev, "qedr%d", NULL); 293 } 294 295 /* This function allocates fast-path status block memory */ 296 static int qedr_alloc_mem_sb(struct qedr_dev *dev, 297 struct qed_sb_info *sb_info, u16 sb_id) 298 { 299 struct status_block_e4 *sb_virt; 300 dma_addr_t sb_phys; 301 int rc; 302 303 sb_virt = dma_alloc_coherent(&dev->pdev->dev, 304 sizeof(*sb_virt), &sb_phys, GFP_KERNEL); 305 if (!sb_virt) 306 return -ENOMEM; 307 308 rc = dev->ops->common->sb_init(dev->cdev, sb_info, 309 sb_virt, sb_phys, sb_id, 310 QED_SB_TYPE_CNQ); 311 if (rc) { 312 pr_err("Status block initialization failed\n"); 313 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt), 314 sb_virt, sb_phys); 315 return rc; 316 } 317 318 return 0; 319 } 320 321 static void qedr_free_mem_sb(struct qedr_dev *dev, 322 struct qed_sb_info *sb_info, int sb_id) 323 { 324 if (sb_info->sb_virt) { 325 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id); 326 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt), 327 (void *)sb_info->sb_virt, sb_info->sb_phys); 328 } 329 } 330 331 static void qedr_free_resources(struct qedr_dev *dev) 332 { 333 int i; 334 335 if (IS_IWARP(dev)) 336 destroy_workqueue(dev->iwarp_wq); 337 338 for (i = 0; i < dev->num_cnq; i++) { 339 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 340 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 341 } 342 343 kfree(dev->cnq_array); 344 kfree(dev->sb_array); 345 kfree(dev->sgid_tbl); 346 } 347 348 static int qedr_alloc_resources(struct qedr_dev *dev) 349 { 350 struct qedr_cnq *cnq; 351 __le16 *cons_pi; 352 u16 n_entries; 353 int i, rc; 354 355 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid), 356 GFP_KERNEL); 357 if (!dev->sgid_tbl) 358 return -ENOMEM; 359 360 spin_lock_init(&dev->sgid_lock); 361 362 if (IS_IWARP(dev)) { 363 spin_lock_init(&dev->qpidr.idr_lock); 364 idr_init(&dev->qpidr.idr); 365 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq"); 366 } 367 368 /* Allocate Status blocks for CNQ */ 369 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array), 370 GFP_KERNEL); 371 if (!dev->sb_array) { 372 rc = -ENOMEM; 373 goto err1; 374 } 375 376 dev->cnq_array = kcalloc(dev->num_cnq, 377 sizeof(*dev->cnq_array), GFP_KERNEL); 378 if (!dev->cnq_array) { 379 rc = -ENOMEM; 380 goto err2; 381 } 382 383 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev); 384 385 /* Allocate CNQ PBLs */ 386 n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE); 387 for (i = 0; i < dev->num_cnq; i++) { 388 cnq = &dev->cnq_array[i]; 389 390 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i], 391 dev->sb_start + i); 392 if (rc) 393 goto err3; 394 395 rc = dev->ops->common->chain_alloc(dev->cdev, 396 QED_CHAIN_USE_TO_CONSUME, 397 QED_CHAIN_MODE_PBL, 398 QED_CHAIN_CNT_TYPE_U16, 399 n_entries, 400 sizeof(struct regpair *), 401 &cnq->pbl, NULL); 402 if (rc) 403 goto err4; 404 405 cnq->dev = dev; 406 cnq->sb = &dev->sb_array[i]; 407 cons_pi = dev->sb_array[i].sb_virt->pi_array; 408 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX]; 409 cnq->index = i; 410 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev)); 411 412 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n", 413 i, qed_chain_get_cons_idx(&cnq->pbl)); 414 } 415 416 return 0; 417 err4: 418 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 419 err3: 420 for (--i; i >= 0; i--) { 421 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 422 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 423 } 424 kfree(dev->cnq_array); 425 err2: 426 kfree(dev->sb_array); 427 err1: 428 kfree(dev->sgid_tbl); 429 return rc; 430 } 431 432 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev) 433 { 434 int rc = pci_enable_atomic_ops_to_root(pdev, 435 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 436 437 if (rc) { 438 dev->atomic_cap = IB_ATOMIC_NONE; 439 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n"); 440 } else { 441 dev->atomic_cap = IB_ATOMIC_GLOB; 442 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n"); 443 } 444 } 445 446 static const struct qed_rdma_ops *qed_ops; 447 448 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 449 450 static irqreturn_t qedr_irq_handler(int irq, void *handle) 451 { 452 u16 hw_comp_cons, sw_comp_cons; 453 struct qedr_cnq *cnq = handle; 454 struct regpair *cq_handle; 455 struct qedr_cq *cq; 456 457 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0); 458 459 qed_sb_update_sb_idx(cnq->sb); 460 461 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 462 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 463 464 /* Align protocol-index and chain reads */ 465 rmb(); 466 467 while (sw_comp_cons != hw_comp_cons) { 468 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl); 469 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 470 cq_handle->lo); 471 472 if (cq == NULL) { 473 DP_ERR(cnq->dev, 474 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n", 475 cq_handle->hi, cq_handle->lo, sw_comp_cons, 476 hw_comp_cons); 477 478 break; 479 } 480 481 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) { 482 DP_ERR(cnq->dev, 483 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n", 484 cq_handle->hi, cq_handle->lo, cq); 485 break; 486 } 487 488 cq->arm_flags = 0; 489 490 if (!cq->destroyed && cq->ibcq.comp_handler) 491 (*cq->ibcq.comp_handler) 492 (&cq->ibcq, cq->ibcq.cq_context); 493 494 /* The CQ's CNQ notification counter is checked before 495 * destroying the CQ in a busy-wait loop that waits for all of 496 * the CQ's CNQ interrupts to be processed. It is increased 497 * here, only after the completion handler, to ensure that the 498 * the handler is not running when the CQ is destroyed. 499 */ 500 cq->cnq_notif++; 501 502 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 503 504 cnq->n_comp++; 505 } 506 507 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, 508 sw_comp_cons); 509 510 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1); 511 512 return IRQ_HANDLED; 513 } 514 515 static void qedr_sync_free_irqs(struct qedr_dev *dev) 516 { 517 u32 vector; 518 int i; 519 520 for (i = 0; i < dev->int_info.used_cnt; i++) { 521 if (dev->int_info.msix_cnt) { 522 vector = dev->int_info.msix[i * dev->num_hwfns].vector; 523 synchronize_irq(vector); 524 free_irq(vector, &dev->cnq_array[i]); 525 } 526 } 527 528 dev->int_info.used_cnt = 0; 529 } 530 531 static int qedr_req_msix_irqs(struct qedr_dev *dev) 532 { 533 int i, rc = 0; 534 535 if (dev->num_cnq > dev->int_info.msix_cnt) { 536 DP_ERR(dev, 537 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n", 538 dev->num_cnq, dev->int_info.msix_cnt); 539 return -EINVAL; 540 } 541 542 for (i = 0; i < dev->num_cnq; i++) { 543 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector, 544 qedr_irq_handler, 0, dev->cnq_array[i].name, 545 &dev->cnq_array[i]); 546 if (rc) { 547 DP_ERR(dev, "Request cnq %d irq failed\n", i); 548 qedr_sync_free_irqs(dev); 549 } else { 550 DP_DEBUG(dev, QEDR_MSG_INIT, 551 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n", 552 dev->cnq_array[i].name, i, 553 &dev->cnq_array[i]); 554 dev->int_info.used_cnt++; 555 } 556 } 557 558 return rc; 559 } 560 561 static int qedr_setup_irqs(struct qedr_dev *dev) 562 { 563 int rc; 564 565 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n"); 566 567 /* Learn Interrupt configuration */ 568 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq); 569 if (rc < 0) 570 return rc; 571 572 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info); 573 if (rc) { 574 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n"); 575 return rc; 576 } 577 578 if (dev->int_info.msix_cnt) { 579 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n", 580 dev->int_info.msix_cnt); 581 rc = qedr_req_msix_irqs(dev); 582 if (rc) 583 return rc; 584 } 585 586 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n"); 587 588 return 0; 589 } 590 591 static int qedr_set_device_attr(struct qedr_dev *dev) 592 { 593 struct qed_rdma_device *qed_attr; 594 struct qedr_device_attr *attr; 595 u32 page_size; 596 597 /* Part 1 - query core capabilities */ 598 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx); 599 600 /* Part 2 - check capabilities */ 601 page_size = ~dev->attr.page_size_caps + 1; 602 if (page_size > PAGE_SIZE) { 603 DP_ERR(dev, 604 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n", 605 PAGE_SIZE, page_size); 606 return -ENODEV; 607 } 608 609 /* Part 3 - copy and update capabilities */ 610 attr = &dev->attr; 611 attr->vendor_id = qed_attr->vendor_id; 612 attr->vendor_part_id = qed_attr->vendor_part_id; 613 attr->hw_ver = qed_attr->hw_ver; 614 attr->fw_ver = qed_attr->fw_ver; 615 attr->node_guid = qed_attr->node_guid; 616 attr->sys_image_guid = qed_attr->sys_image_guid; 617 attr->max_cnq = qed_attr->max_cnq; 618 attr->max_sge = qed_attr->max_sge; 619 attr->max_inline = qed_attr->max_inline; 620 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE); 621 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE); 622 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc; 623 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc; 624 attr->max_dev_resp_rd_atomic_resc = 625 qed_attr->max_dev_resp_rd_atomic_resc; 626 attr->max_cq = qed_attr->max_cq; 627 attr->max_qp = qed_attr->max_qp; 628 attr->max_mr = qed_attr->max_mr; 629 attr->max_mr_size = qed_attr->max_mr_size; 630 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES); 631 attr->max_mw = qed_attr->max_mw; 632 attr->max_fmr = qed_attr->max_fmr; 633 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl; 634 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size; 635 attr->max_pd = qed_attr->max_pd; 636 attr->max_ah = qed_attr->max_ah; 637 attr->max_pkey = qed_attr->max_pkey; 638 attr->max_srq = qed_attr->max_srq; 639 attr->max_srq_wr = qed_attr->max_srq_wr; 640 attr->dev_caps = qed_attr->dev_caps; 641 attr->page_size_caps = qed_attr->page_size_caps; 642 attr->dev_ack_delay = qed_attr->dev_ack_delay; 643 attr->reserved_lkey = qed_attr->reserved_lkey; 644 attr->bad_pkey_counter = qed_attr->bad_pkey_counter; 645 attr->max_stats_queues = qed_attr->max_stats_queues; 646 647 return 0; 648 } 649 650 static void qedr_unaffiliated_event(void *context, u8 event_code) 651 { 652 pr_err("unaffiliated event not implemented yet\n"); 653 } 654 655 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle) 656 { 657 #define EVENT_TYPE_NOT_DEFINED 0 658 #define EVENT_TYPE_CQ 1 659 #define EVENT_TYPE_QP 2 660 #define EVENT_TYPE_SRQ 3 661 struct qedr_dev *dev = (struct qedr_dev *)context; 662 struct regpair *async_handle = (struct regpair *)fw_handle; 663 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo; 664 u8 event_type = EVENT_TYPE_NOT_DEFINED; 665 struct ib_event event; 666 struct ib_srq *ibsrq; 667 struct qedr_srq *srq; 668 unsigned long flags; 669 struct ib_cq *ibcq; 670 struct ib_qp *ibqp; 671 struct qedr_cq *cq; 672 struct qedr_qp *qp; 673 u16 srq_id; 674 675 if (IS_ROCE(dev)) { 676 switch (e_code) { 677 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 678 event.event = IB_EVENT_CQ_ERR; 679 event_type = EVENT_TYPE_CQ; 680 break; 681 case ROCE_ASYNC_EVENT_SQ_DRAINED: 682 event.event = IB_EVENT_SQ_DRAINED; 683 event_type = EVENT_TYPE_QP; 684 break; 685 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 686 event.event = IB_EVENT_QP_FATAL; 687 event_type = EVENT_TYPE_QP; 688 break; 689 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 690 event.event = IB_EVENT_QP_REQ_ERR; 691 event_type = EVENT_TYPE_QP; 692 break; 693 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 694 event.event = IB_EVENT_QP_ACCESS_ERR; 695 event_type = EVENT_TYPE_QP; 696 break; 697 case ROCE_ASYNC_EVENT_SRQ_LIMIT: 698 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 699 event_type = EVENT_TYPE_SRQ; 700 break; 701 case ROCE_ASYNC_EVENT_SRQ_EMPTY: 702 event.event = IB_EVENT_SRQ_ERR; 703 event_type = EVENT_TYPE_SRQ; 704 break; 705 default: 706 DP_ERR(dev, "unsupported event %d on handle=%llx\n", 707 e_code, roce_handle64); 708 } 709 } else { 710 switch (e_code) { 711 case QED_IWARP_EVENT_SRQ_LIMIT: 712 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 713 event_type = EVENT_TYPE_SRQ; 714 break; 715 case QED_IWARP_EVENT_SRQ_EMPTY: 716 event.event = IB_EVENT_SRQ_ERR; 717 event_type = EVENT_TYPE_SRQ; 718 break; 719 default: 720 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code, 721 roce_handle64); 722 } 723 } 724 switch (event_type) { 725 case EVENT_TYPE_CQ: 726 cq = (struct qedr_cq *)(uintptr_t)roce_handle64; 727 if (cq) { 728 ibcq = &cq->ibcq; 729 if (ibcq->event_handler) { 730 event.device = ibcq->device; 731 event.element.cq = ibcq; 732 ibcq->event_handler(&event, ibcq->cq_context); 733 } 734 } else { 735 WARN(1, 736 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n", 737 roce_handle64); 738 } 739 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq); 740 break; 741 case EVENT_TYPE_QP: 742 qp = (struct qedr_qp *)(uintptr_t)roce_handle64; 743 if (qp) { 744 ibqp = &qp->ibqp; 745 if (ibqp->event_handler) { 746 event.device = ibqp->device; 747 event.element.qp = ibqp; 748 ibqp->event_handler(&event, ibqp->qp_context); 749 } 750 } else { 751 WARN(1, 752 "Error: QP event with NULL pointer ibqp. Handle=%llx\n", 753 roce_handle64); 754 } 755 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp); 756 break; 757 case EVENT_TYPE_SRQ: 758 srq_id = (u16)roce_handle64; 759 spin_lock_irqsave(&dev->srqidr.idr_lock, flags); 760 srq = idr_find(&dev->srqidr.idr, srq_id); 761 if (srq) { 762 ibsrq = &srq->ibsrq; 763 if (ibsrq->event_handler) { 764 event.device = ibsrq->device; 765 event.element.srq = ibsrq; 766 ibsrq->event_handler(&event, 767 ibsrq->srq_context); 768 } 769 } else { 770 DP_NOTICE(dev, 771 "SRQ event with NULL pointer ibsrq. Handle=%llx\n", 772 roce_handle64); 773 } 774 spin_unlock_irqrestore(&dev->srqidr.idr_lock, flags); 775 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq); 776 default: 777 break; 778 } 779 } 780 781 static int qedr_init_hw(struct qedr_dev *dev) 782 { 783 struct qed_rdma_add_user_out_params out_params; 784 struct qed_rdma_start_in_params *in_params; 785 struct qed_rdma_cnq_params *cur_pbl; 786 struct qed_rdma_events events; 787 dma_addr_t p_phys_table; 788 u32 page_cnt; 789 int rc = 0; 790 int i; 791 792 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 793 if (!in_params) { 794 rc = -ENOMEM; 795 goto out; 796 } 797 798 in_params->desired_cnq = dev->num_cnq; 799 for (i = 0; i < dev->num_cnq; i++) { 800 cur_pbl = &in_params->cnq_pbl_list[i]; 801 802 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl); 803 cur_pbl->num_pbl_pages = page_cnt; 804 805 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 806 cur_pbl->pbl_ptr = (u64)p_phys_table; 807 } 808 809 events.affiliated_event = qedr_affiliated_event; 810 events.unaffiliated_event = qedr_unaffiliated_event; 811 events.context = dev; 812 813 in_params->events = &events; 814 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS; 815 in_params->max_mtu = dev->ndev->mtu; 816 dev->iwarp_max_mtu = dev->ndev->mtu; 817 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr); 818 819 rc = dev->ops->rdma_init(dev->cdev, in_params); 820 if (rc) 821 goto out; 822 823 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params); 824 if (rc) 825 goto out; 826 827 dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr; 828 dev->db_phys_addr = out_params.dpi_phys_addr; 829 dev->db_size = out_params.dpi_size; 830 dev->dpi = out_params.dpi; 831 832 rc = qedr_set_device_attr(dev); 833 out: 834 kfree(in_params); 835 if (rc) 836 DP_ERR(dev, "Init HW Failed rc = %d\n", rc); 837 838 return rc; 839 } 840 841 static void qedr_stop_hw(struct qedr_dev *dev) 842 { 843 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi); 844 dev->ops->rdma_stop(dev->rdma_ctx); 845 } 846 847 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev, 848 struct net_device *ndev) 849 { 850 struct qed_dev_rdma_info dev_info; 851 struct qedr_dev *dev; 852 int rc = 0; 853 854 dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev)); 855 if (!dev) { 856 pr_err("Unable to allocate ib device\n"); 857 return NULL; 858 } 859 860 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n"); 861 862 dev->pdev = pdev; 863 dev->ndev = ndev; 864 dev->cdev = cdev; 865 866 qed_ops = qed_get_rdma_ops(); 867 if (!qed_ops) { 868 DP_ERR(dev, "Failed to get qed roce operations\n"); 869 goto init_err; 870 } 871 872 dev->ops = qed_ops; 873 rc = qed_ops->fill_dev_info(cdev, &dev_info); 874 if (rc) 875 goto init_err; 876 877 dev->user_dpm_enabled = dev_info.user_dpm_enabled; 878 dev->rdma_type = dev_info.rdma_type; 879 dev->num_hwfns = dev_info.common.num_hwfns; 880 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev); 881 882 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev); 883 if (!dev->num_cnq) { 884 DP_ERR(dev, "Failed. At least one CNQ is required.\n"); 885 rc = -ENOMEM; 886 goto init_err; 887 } 888 889 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT; 890 891 qedr_pci_set_atomic(dev, pdev); 892 893 rc = qedr_alloc_resources(dev); 894 if (rc) 895 goto init_err; 896 897 rc = qedr_init_hw(dev); 898 if (rc) 899 goto alloc_err; 900 901 rc = qedr_setup_irqs(dev); 902 if (rc) 903 goto irq_err; 904 905 rc = qedr_register_device(dev); 906 if (rc) { 907 DP_ERR(dev, "Unable to allocate register device\n"); 908 goto reg_err; 909 } 910 911 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 912 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 913 914 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n"); 915 return dev; 916 917 reg_err: 918 qedr_sync_free_irqs(dev); 919 irq_err: 920 qedr_stop_hw(dev); 921 alloc_err: 922 qedr_free_resources(dev); 923 init_err: 924 ib_dealloc_device(&dev->ibdev); 925 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc); 926 927 return NULL; 928 } 929 930 static void qedr_remove(struct qedr_dev *dev) 931 { 932 /* First unregister with stack to stop all the active traffic 933 * of the registered clients. 934 */ 935 ib_unregister_device(&dev->ibdev); 936 937 qedr_stop_hw(dev); 938 qedr_sync_free_irqs(dev); 939 qedr_free_resources(dev); 940 ib_dealloc_device(&dev->ibdev); 941 } 942 943 static void qedr_close(struct qedr_dev *dev) 944 { 945 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 946 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR); 947 } 948 949 static void qedr_shutdown(struct qedr_dev *dev) 950 { 951 qedr_close(dev); 952 qedr_remove(dev); 953 } 954 955 static void qedr_open(struct qedr_dev *dev) 956 { 957 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 958 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 959 } 960 961 static void qedr_mac_address_change(struct qedr_dev *dev) 962 { 963 union ib_gid *sgid = &dev->sgid_tbl[0]; 964 u8 guid[8], mac_addr[6]; 965 int rc; 966 967 /* Update SGID */ 968 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr); 969 guid[0] = mac_addr[0] ^ 2; 970 guid[1] = mac_addr[1]; 971 guid[2] = mac_addr[2]; 972 guid[3] = 0xff; 973 guid[4] = 0xfe; 974 guid[5] = mac_addr[3]; 975 guid[6] = mac_addr[4]; 976 guid[7] = mac_addr[5]; 977 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL); 978 memcpy(&sgid->raw[8], guid, sizeof(guid)); 979 980 /* Update LL2 */ 981 rc = dev->ops->ll2_set_mac_filter(dev->cdev, 982 dev->gsi_ll2_mac_address, 983 dev->ndev->dev_addr); 984 985 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr); 986 987 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE); 988 989 if (rc) 990 DP_ERR(dev, "Error updating mac filter\n"); 991 } 992 993 /* event handling via NIC driver ensures that all the NIC specific 994 * initialization done before RoCE driver notifies 995 * event to stack. 996 */ 997 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event) 998 { 999 switch (event) { 1000 case QEDE_UP: 1001 qedr_open(dev); 1002 break; 1003 case QEDE_DOWN: 1004 qedr_close(dev); 1005 break; 1006 case QEDE_CLOSE: 1007 qedr_shutdown(dev); 1008 break; 1009 case QEDE_CHANGE_ADDR: 1010 qedr_mac_address_change(dev); 1011 break; 1012 default: 1013 pr_err("Event not supported\n"); 1014 } 1015 } 1016 1017 static struct qedr_driver qedr_drv = { 1018 .name = "qedr_driver", 1019 .add = qedr_add, 1020 .remove = qedr_remove, 1021 .notify = qedr_notify, 1022 }; 1023 1024 static int __init qedr_init_module(void) 1025 { 1026 return qede_rdma_register_driver(&qedr_drv); 1027 } 1028 1029 static void __exit qedr_exit_module(void) 1030 { 1031 qede_rdma_unregister_driver(&qedr_drv); 1032 } 1033 1034 module_init(qedr_init_module); 1035 module_exit(qedr_exit_module); 1036