1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/module.h> 33 #include <rdma/ib_verbs.h> 34 #include <rdma/ib_addr.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/iw_cm.h> 37 #include <rdma/ib_mad.h> 38 #include <linux/netdevice.h> 39 #include <linux/iommu.h> 40 #include <linux/pci.h> 41 #include <net/addrconf.h> 42 #include <linux/idr.h> 43 44 #include <linux/qed/qed_chain.h> 45 #include <linux/qed/qed_if.h> 46 #include "qedr.h" 47 #include "verbs.h" 48 #include <rdma/qedr-abi.h> 49 #include "qedr_iw_cm.h" 50 51 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver"); 52 MODULE_AUTHOR("QLogic Corporation"); 53 MODULE_LICENSE("Dual BSD/GPL"); 54 55 #define QEDR_WQ_MULTIPLIER_DFT (3) 56 57 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num, 58 enum ib_event_type type) 59 { 60 struct ib_event ibev; 61 62 ibev.device = &dev->ibdev; 63 ibev.element.port_num = port_num; 64 ibev.event = type; 65 66 ib_dispatch_event(&ibev); 67 } 68 69 static enum rdma_link_layer qedr_link_layer(struct ib_device *device, 70 u8 port_num) 71 { 72 return IB_LINK_LAYER_ETHERNET; 73 } 74 75 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str) 76 { 77 struct qedr_dev *qedr = get_qedr_dev(ibdev); 78 u32 fw_ver = (u32)qedr->attr.fw_ver; 79 80 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d", 81 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF, 82 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); 83 } 84 85 static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num) 86 { 87 struct qedr_dev *qdev; 88 89 qdev = get_qedr_dev(dev); 90 dev_hold(qdev->ndev); 91 92 /* The HW vendor's device driver must guarantee 93 * that this function returns NULL before the net device has finished 94 * NETDEV_UNREGISTER state. 95 */ 96 return qdev->ndev; 97 } 98 99 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num, 100 struct ib_port_immutable *immutable) 101 { 102 struct ib_port_attr attr; 103 int err; 104 105 err = qedr_query_port(ibdev, port_num, &attr); 106 if (err) 107 return err; 108 109 immutable->pkey_tbl_len = attr.pkey_tbl_len; 110 immutable->gid_tbl_len = attr.gid_tbl_len; 111 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 112 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 113 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 114 115 return 0; 116 } 117 118 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num, 119 struct ib_port_immutable *immutable) 120 { 121 struct ib_port_attr attr; 122 int err; 123 124 err = qedr_query_port(ibdev, port_num, &attr); 125 if (err) 126 return err; 127 128 immutable->pkey_tbl_len = 1; 129 immutable->gid_tbl_len = 1; 130 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 131 immutable->max_mad_size = 0; 132 133 return 0; 134 } 135 136 static int qedr_iw_register_device(struct qedr_dev *dev) 137 { 138 dev->ibdev.node_type = RDMA_NODE_RNIC; 139 dev->ibdev.query_gid = qedr_iw_query_gid; 140 141 dev->ibdev.get_port_immutable = qedr_iw_port_immutable; 142 143 dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL); 144 if (!dev->ibdev.iwcm) 145 return -ENOMEM; 146 147 dev->ibdev.iwcm->connect = qedr_iw_connect; 148 dev->ibdev.iwcm->accept = qedr_iw_accept; 149 dev->ibdev.iwcm->reject = qedr_iw_reject; 150 dev->ibdev.iwcm->create_listen = qedr_iw_create_listen; 151 dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen; 152 dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref; 153 dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref; 154 dev->ibdev.iwcm->get_qp = qedr_iw_get_qp; 155 156 memcpy(dev->ibdev.iwcm->ifname, 157 dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname)); 158 159 return 0; 160 } 161 162 static void qedr_roce_register_device(struct qedr_dev *dev) 163 { 164 dev->ibdev.node_type = RDMA_NODE_IB_CA; 165 166 dev->ibdev.get_port_immutable = qedr_roce_port_immutable; 167 } 168 169 static int qedr_register_device(struct qedr_dev *dev) 170 { 171 int rc; 172 173 strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX); 174 175 dev->ibdev.node_guid = dev->attr.node_guid; 176 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC)); 177 dev->ibdev.owner = THIS_MODULE; 178 dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION; 179 180 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) | 181 QEDR_UVERBS(QUERY_DEVICE) | 182 QEDR_UVERBS(QUERY_PORT) | 183 QEDR_UVERBS(ALLOC_PD) | 184 QEDR_UVERBS(DEALLOC_PD) | 185 QEDR_UVERBS(CREATE_COMP_CHANNEL) | 186 QEDR_UVERBS(CREATE_CQ) | 187 QEDR_UVERBS(RESIZE_CQ) | 188 QEDR_UVERBS(DESTROY_CQ) | 189 QEDR_UVERBS(REQ_NOTIFY_CQ) | 190 QEDR_UVERBS(CREATE_QP) | 191 QEDR_UVERBS(MODIFY_QP) | 192 QEDR_UVERBS(QUERY_QP) | 193 QEDR_UVERBS(DESTROY_QP) | 194 QEDR_UVERBS(CREATE_SRQ) | 195 QEDR_UVERBS(DESTROY_SRQ) | 196 QEDR_UVERBS(QUERY_SRQ) | 197 QEDR_UVERBS(MODIFY_SRQ) | 198 QEDR_UVERBS(POST_SRQ_RECV) | 199 QEDR_UVERBS(REG_MR) | 200 QEDR_UVERBS(DEREG_MR) | 201 QEDR_UVERBS(POLL_CQ) | 202 QEDR_UVERBS(POST_SEND) | 203 QEDR_UVERBS(POST_RECV); 204 205 if (IS_IWARP(dev)) { 206 rc = qedr_iw_register_device(dev); 207 if (rc) 208 return rc; 209 } else { 210 qedr_roce_register_device(dev); 211 } 212 213 dev->ibdev.phys_port_cnt = 1; 214 dev->ibdev.num_comp_vectors = dev->num_cnq; 215 216 dev->ibdev.query_device = qedr_query_device; 217 dev->ibdev.query_port = qedr_query_port; 218 dev->ibdev.modify_port = qedr_modify_port; 219 220 dev->ibdev.alloc_ucontext = qedr_alloc_ucontext; 221 dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext; 222 dev->ibdev.mmap = qedr_mmap; 223 224 dev->ibdev.alloc_pd = qedr_alloc_pd; 225 dev->ibdev.dealloc_pd = qedr_dealloc_pd; 226 227 dev->ibdev.create_cq = qedr_create_cq; 228 dev->ibdev.destroy_cq = qedr_destroy_cq; 229 dev->ibdev.resize_cq = qedr_resize_cq; 230 dev->ibdev.req_notify_cq = qedr_arm_cq; 231 232 dev->ibdev.create_qp = qedr_create_qp; 233 dev->ibdev.modify_qp = qedr_modify_qp; 234 dev->ibdev.query_qp = qedr_query_qp; 235 dev->ibdev.destroy_qp = qedr_destroy_qp; 236 237 dev->ibdev.create_srq = qedr_create_srq; 238 dev->ibdev.destroy_srq = qedr_destroy_srq; 239 dev->ibdev.modify_srq = qedr_modify_srq; 240 dev->ibdev.query_srq = qedr_query_srq; 241 dev->ibdev.post_srq_recv = qedr_post_srq_recv; 242 dev->ibdev.query_pkey = qedr_query_pkey; 243 244 dev->ibdev.create_ah = qedr_create_ah; 245 dev->ibdev.destroy_ah = qedr_destroy_ah; 246 247 dev->ibdev.get_dma_mr = qedr_get_dma_mr; 248 dev->ibdev.dereg_mr = qedr_dereg_mr; 249 dev->ibdev.reg_user_mr = qedr_reg_user_mr; 250 dev->ibdev.alloc_mr = qedr_alloc_mr; 251 dev->ibdev.map_mr_sg = qedr_map_mr_sg; 252 253 dev->ibdev.poll_cq = qedr_poll_cq; 254 dev->ibdev.post_send = qedr_post_send; 255 dev->ibdev.post_recv = qedr_post_recv; 256 257 dev->ibdev.process_mad = qedr_process_mad; 258 259 dev->ibdev.get_netdev = qedr_get_netdev; 260 261 dev->ibdev.dev.parent = &dev->pdev->dev; 262 263 dev->ibdev.get_link_layer = qedr_link_layer; 264 dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str; 265 266 dev->ibdev.driver_id = RDMA_DRIVER_QEDR; 267 return ib_register_device(&dev->ibdev, NULL); 268 } 269 270 /* This function allocates fast-path status block memory */ 271 static int qedr_alloc_mem_sb(struct qedr_dev *dev, 272 struct qed_sb_info *sb_info, u16 sb_id) 273 { 274 struct status_block_e4 *sb_virt; 275 dma_addr_t sb_phys; 276 int rc; 277 278 sb_virt = dma_alloc_coherent(&dev->pdev->dev, 279 sizeof(*sb_virt), &sb_phys, GFP_KERNEL); 280 if (!sb_virt) 281 return -ENOMEM; 282 283 rc = dev->ops->common->sb_init(dev->cdev, sb_info, 284 sb_virt, sb_phys, sb_id, 285 QED_SB_TYPE_CNQ); 286 if (rc) { 287 pr_err("Status block initialization failed\n"); 288 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt), 289 sb_virt, sb_phys); 290 return rc; 291 } 292 293 return 0; 294 } 295 296 static void qedr_free_mem_sb(struct qedr_dev *dev, 297 struct qed_sb_info *sb_info, int sb_id) 298 { 299 if (sb_info->sb_virt) { 300 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id); 301 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt), 302 (void *)sb_info->sb_virt, sb_info->sb_phys); 303 } 304 } 305 306 static void qedr_free_resources(struct qedr_dev *dev) 307 { 308 int i; 309 310 if (IS_IWARP(dev)) 311 destroy_workqueue(dev->iwarp_wq); 312 313 for (i = 0; i < dev->num_cnq; i++) { 314 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 315 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 316 } 317 318 kfree(dev->cnq_array); 319 kfree(dev->sb_array); 320 kfree(dev->sgid_tbl); 321 } 322 323 static int qedr_alloc_resources(struct qedr_dev *dev) 324 { 325 struct qedr_cnq *cnq; 326 __le16 *cons_pi; 327 u16 n_entries; 328 int i, rc; 329 330 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid), 331 GFP_KERNEL); 332 if (!dev->sgid_tbl) 333 return -ENOMEM; 334 335 spin_lock_init(&dev->sgid_lock); 336 337 if (IS_IWARP(dev)) { 338 spin_lock_init(&dev->qpidr.idr_lock); 339 idr_init(&dev->qpidr.idr); 340 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq"); 341 } 342 343 /* Allocate Status blocks for CNQ */ 344 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array), 345 GFP_KERNEL); 346 if (!dev->sb_array) { 347 rc = -ENOMEM; 348 goto err1; 349 } 350 351 dev->cnq_array = kcalloc(dev->num_cnq, 352 sizeof(*dev->cnq_array), GFP_KERNEL); 353 if (!dev->cnq_array) { 354 rc = -ENOMEM; 355 goto err2; 356 } 357 358 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev); 359 360 /* Allocate CNQ PBLs */ 361 n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE); 362 for (i = 0; i < dev->num_cnq; i++) { 363 cnq = &dev->cnq_array[i]; 364 365 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i], 366 dev->sb_start + i); 367 if (rc) 368 goto err3; 369 370 rc = dev->ops->common->chain_alloc(dev->cdev, 371 QED_CHAIN_USE_TO_CONSUME, 372 QED_CHAIN_MODE_PBL, 373 QED_CHAIN_CNT_TYPE_U16, 374 n_entries, 375 sizeof(struct regpair *), 376 &cnq->pbl, NULL); 377 if (rc) 378 goto err4; 379 380 cnq->dev = dev; 381 cnq->sb = &dev->sb_array[i]; 382 cons_pi = dev->sb_array[i].sb_virt->pi_array; 383 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX]; 384 cnq->index = i; 385 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev)); 386 387 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n", 388 i, qed_chain_get_cons_idx(&cnq->pbl)); 389 } 390 391 return 0; 392 err4: 393 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 394 err3: 395 for (--i; i >= 0; i--) { 396 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 397 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 398 } 399 kfree(dev->cnq_array); 400 err2: 401 kfree(dev->sb_array); 402 err1: 403 kfree(dev->sgid_tbl); 404 return rc; 405 } 406 407 /* QEDR sysfs interface */ 408 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 409 char *buf) 410 { 411 struct qedr_dev *dev = dev_get_drvdata(device); 412 413 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor); 414 } 415 416 static ssize_t show_hca_type(struct device *device, 417 struct device_attribute *attr, char *buf) 418 { 419 return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET"); 420 } 421 422 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 423 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL); 424 425 static struct device_attribute *qedr_attributes[] = { 426 &dev_attr_hw_rev, 427 &dev_attr_hca_type 428 }; 429 430 static void qedr_remove_sysfiles(struct qedr_dev *dev) 431 { 432 int i; 433 434 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++) 435 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]); 436 } 437 438 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev) 439 { 440 int rc = pci_enable_atomic_ops_to_root(pdev, 441 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 442 443 if (rc) { 444 dev->atomic_cap = IB_ATOMIC_NONE; 445 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n"); 446 } else { 447 dev->atomic_cap = IB_ATOMIC_GLOB; 448 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n"); 449 } 450 } 451 452 static const struct qed_rdma_ops *qed_ops; 453 454 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 455 456 static irqreturn_t qedr_irq_handler(int irq, void *handle) 457 { 458 u16 hw_comp_cons, sw_comp_cons; 459 struct qedr_cnq *cnq = handle; 460 struct regpair *cq_handle; 461 struct qedr_cq *cq; 462 463 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0); 464 465 qed_sb_update_sb_idx(cnq->sb); 466 467 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 468 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 469 470 /* Align protocol-index and chain reads */ 471 rmb(); 472 473 while (sw_comp_cons != hw_comp_cons) { 474 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl); 475 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 476 cq_handle->lo); 477 478 if (cq == NULL) { 479 DP_ERR(cnq->dev, 480 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n", 481 cq_handle->hi, cq_handle->lo, sw_comp_cons, 482 hw_comp_cons); 483 484 break; 485 } 486 487 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) { 488 DP_ERR(cnq->dev, 489 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n", 490 cq_handle->hi, cq_handle->lo, cq); 491 break; 492 } 493 494 cq->arm_flags = 0; 495 496 if (!cq->destroyed && cq->ibcq.comp_handler) 497 (*cq->ibcq.comp_handler) 498 (&cq->ibcq, cq->ibcq.cq_context); 499 500 /* The CQ's CNQ notification counter is checked before 501 * destroying the CQ in a busy-wait loop that waits for all of 502 * the CQ's CNQ interrupts to be processed. It is increased 503 * here, only after the completion handler, to ensure that the 504 * the handler is not running when the CQ is destroyed. 505 */ 506 cq->cnq_notif++; 507 508 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 509 510 cnq->n_comp++; 511 } 512 513 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, 514 sw_comp_cons); 515 516 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1); 517 518 return IRQ_HANDLED; 519 } 520 521 static void qedr_sync_free_irqs(struct qedr_dev *dev) 522 { 523 u32 vector; 524 int i; 525 526 for (i = 0; i < dev->int_info.used_cnt; i++) { 527 if (dev->int_info.msix_cnt) { 528 vector = dev->int_info.msix[i * dev->num_hwfns].vector; 529 synchronize_irq(vector); 530 free_irq(vector, &dev->cnq_array[i]); 531 } 532 } 533 534 dev->int_info.used_cnt = 0; 535 } 536 537 static int qedr_req_msix_irqs(struct qedr_dev *dev) 538 { 539 int i, rc = 0; 540 541 if (dev->num_cnq > dev->int_info.msix_cnt) { 542 DP_ERR(dev, 543 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n", 544 dev->num_cnq, dev->int_info.msix_cnt); 545 return -EINVAL; 546 } 547 548 for (i = 0; i < dev->num_cnq; i++) { 549 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector, 550 qedr_irq_handler, 0, dev->cnq_array[i].name, 551 &dev->cnq_array[i]); 552 if (rc) { 553 DP_ERR(dev, "Request cnq %d irq failed\n", i); 554 qedr_sync_free_irqs(dev); 555 } else { 556 DP_DEBUG(dev, QEDR_MSG_INIT, 557 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n", 558 dev->cnq_array[i].name, i, 559 &dev->cnq_array[i]); 560 dev->int_info.used_cnt++; 561 } 562 } 563 564 return rc; 565 } 566 567 static int qedr_setup_irqs(struct qedr_dev *dev) 568 { 569 int rc; 570 571 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n"); 572 573 /* Learn Interrupt configuration */ 574 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq); 575 if (rc < 0) 576 return rc; 577 578 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info); 579 if (rc) { 580 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n"); 581 return rc; 582 } 583 584 if (dev->int_info.msix_cnt) { 585 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n", 586 dev->int_info.msix_cnt); 587 rc = qedr_req_msix_irqs(dev); 588 if (rc) 589 return rc; 590 } 591 592 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n"); 593 594 return 0; 595 } 596 597 static int qedr_set_device_attr(struct qedr_dev *dev) 598 { 599 struct qed_rdma_device *qed_attr; 600 struct qedr_device_attr *attr; 601 u32 page_size; 602 603 /* Part 1 - query core capabilities */ 604 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx); 605 606 /* Part 2 - check capabilities */ 607 page_size = ~dev->attr.page_size_caps + 1; 608 if (page_size > PAGE_SIZE) { 609 DP_ERR(dev, 610 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n", 611 PAGE_SIZE, page_size); 612 return -ENODEV; 613 } 614 615 /* Part 3 - copy and update capabilities */ 616 attr = &dev->attr; 617 attr->vendor_id = qed_attr->vendor_id; 618 attr->vendor_part_id = qed_attr->vendor_part_id; 619 attr->hw_ver = qed_attr->hw_ver; 620 attr->fw_ver = qed_attr->fw_ver; 621 attr->node_guid = qed_attr->node_guid; 622 attr->sys_image_guid = qed_attr->sys_image_guid; 623 attr->max_cnq = qed_attr->max_cnq; 624 attr->max_sge = qed_attr->max_sge; 625 attr->max_inline = qed_attr->max_inline; 626 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE); 627 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE); 628 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc; 629 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc; 630 attr->max_dev_resp_rd_atomic_resc = 631 qed_attr->max_dev_resp_rd_atomic_resc; 632 attr->max_cq = qed_attr->max_cq; 633 attr->max_qp = qed_attr->max_qp; 634 attr->max_mr = qed_attr->max_mr; 635 attr->max_mr_size = qed_attr->max_mr_size; 636 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES); 637 attr->max_mw = qed_attr->max_mw; 638 attr->max_fmr = qed_attr->max_fmr; 639 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl; 640 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size; 641 attr->max_pd = qed_attr->max_pd; 642 attr->max_ah = qed_attr->max_ah; 643 attr->max_pkey = qed_attr->max_pkey; 644 attr->max_srq = qed_attr->max_srq; 645 attr->max_srq_wr = qed_attr->max_srq_wr; 646 attr->dev_caps = qed_attr->dev_caps; 647 attr->page_size_caps = qed_attr->page_size_caps; 648 attr->dev_ack_delay = qed_attr->dev_ack_delay; 649 attr->reserved_lkey = qed_attr->reserved_lkey; 650 attr->bad_pkey_counter = qed_attr->bad_pkey_counter; 651 attr->max_stats_queues = qed_attr->max_stats_queues; 652 653 return 0; 654 } 655 656 static void qedr_unaffiliated_event(void *context, u8 event_code) 657 { 658 pr_err("unaffiliated event not implemented yet\n"); 659 } 660 661 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle) 662 { 663 #define EVENT_TYPE_NOT_DEFINED 0 664 #define EVENT_TYPE_CQ 1 665 #define EVENT_TYPE_QP 2 666 #define EVENT_TYPE_SRQ 3 667 struct qedr_dev *dev = (struct qedr_dev *)context; 668 struct regpair *async_handle = (struct regpair *)fw_handle; 669 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo; 670 u8 event_type = EVENT_TYPE_NOT_DEFINED; 671 struct ib_event event; 672 struct ib_srq *ibsrq; 673 struct qedr_srq *srq; 674 unsigned long flags; 675 struct ib_cq *ibcq; 676 struct ib_qp *ibqp; 677 struct qedr_cq *cq; 678 struct qedr_qp *qp; 679 u16 srq_id; 680 681 if (IS_ROCE(dev)) { 682 switch (e_code) { 683 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 684 event.event = IB_EVENT_CQ_ERR; 685 event_type = EVENT_TYPE_CQ; 686 break; 687 case ROCE_ASYNC_EVENT_SQ_DRAINED: 688 event.event = IB_EVENT_SQ_DRAINED; 689 event_type = EVENT_TYPE_QP; 690 break; 691 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 692 event.event = IB_EVENT_QP_FATAL; 693 event_type = EVENT_TYPE_QP; 694 break; 695 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 696 event.event = IB_EVENT_QP_REQ_ERR; 697 event_type = EVENT_TYPE_QP; 698 break; 699 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 700 event.event = IB_EVENT_QP_ACCESS_ERR; 701 event_type = EVENT_TYPE_QP; 702 break; 703 case ROCE_ASYNC_EVENT_SRQ_LIMIT: 704 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 705 event_type = EVENT_TYPE_SRQ; 706 break; 707 case ROCE_ASYNC_EVENT_SRQ_EMPTY: 708 event.event = IB_EVENT_SRQ_ERR; 709 event_type = EVENT_TYPE_SRQ; 710 break; 711 default: 712 DP_ERR(dev, "unsupported event %d on handle=%llx\n", 713 e_code, roce_handle64); 714 } 715 } else { 716 switch (e_code) { 717 case QED_IWARP_EVENT_SRQ_LIMIT: 718 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 719 event_type = EVENT_TYPE_SRQ; 720 break; 721 case QED_IWARP_EVENT_SRQ_EMPTY: 722 event.event = IB_EVENT_SRQ_ERR; 723 event_type = EVENT_TYPE_SRQ; 724 break; 725 default: 726 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code, 727 roce_handle64); 728 } 729 } 730 switch (event_type) { 731 case EVENT_TYPE_CQ: 732 cq = (struct qedr_cq *)(uintptr_t)roce_handle64; 733 if (cq) { 734 ibcq = &cq->ibcq; 735 if (ibcq->event_handler) { 736 event.device = ibcq->device; 737 event.element.cq = ibcq; 738 ibcq->event_handler(&event, ibcq->cq_context); 739 } 740 } else { 741 WARN(1, 742 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n", 743 roce_handle64); 744 } 745 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq); 746 break; 747 case EVENT_TYPE_QP: 748 qp = (struct qedr_qp *)(uintptr_t)roce_handle64; 749 if (qp) { 750 ibqp = &qp->ibqp; 751 if (ibqp->event_handler) { 752 event.device = ibqp->device; 753 event.element.qp = ibqp; 754 ibqp->event_handler(&event, ibqp->qp_context); 755 } 756 } else { 757 WARN(1, 758 "Error: QP event with NULL pointer ibqp. Handle=%llx\n", 759 roce_handle64); 760 } 761 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp); 762 break; 763 case EVENT_TYPE_SRQ: 764 srq_id = (u16)roce_handle64; 765 spin_lock_irqsave(&dev->srqidr.idr_lock, flags); 766 srq = idr_find(&dev->srqidr.idr, srq_id); 767 if (srq) { 768 ibsrq = &srq->ibsrq; 769 if (ibsrq->event_handler) { 770 event.device = ibsrq->device; 771 event.element.srq = ibsrq; 772 ibsrq->event_handler(&event, 773 ibsrq->srq_context); 774 } 775 } else { 776 DP_NOTICE(dev, 777 "SRQ event with NULL pointer ibsrq. Handle=%llx\n", 778 roce_handle64); 779 } 780 spin_unlock_irqrestore(&dev->srqidr.idr_lock, flags); 781 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq); 782 default: 783 break; 784 } 785 } 786 787 static int qedr_init_hw(struct qedr_dev *dev) 788 { 789 struct qed_rdma_add_user_out_params out_params; 790 struct qed_rdma_start_in_params *in_params; 791 struct qed_rdma_cnq_params *cur_pbl; 792 struct qed_rdma_events events; 793 dma_addr_t p_phys_table; 794 u32 page_cnt; 795 int rc = 0; 796 int i; 797 798 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 799 if (!in_params) { 800 rc = -ENOMEM; 801 goto out; 802 } 803 804 in_params->desired_cnq = dev->num_cnq; 805 for (i = 0; i < dev->num_cnq; i++) { 806 cur_pbl = &in_params->cnq_pbl_list[i]; 807 808 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl); 809 cur_pbl->num_pbl_pages = page_cnt; 810 811 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 812 cur_pbl->pbl_ptr = (u64)p_phys_table; 813 } 814 815 events.affiliated_event = qedr_affiliated_event; 816 events.unaffiliated_event = qedr_unaffiliated_event; 817 events.context = dev; 818 819 in_params->events = &events; 820 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS; 821 in_params->max_mtu = dev->ndev->mtu; 822 dev->iwarp_max_mtu = dev->ndev->mtu; 823 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr); 824 825 rc = dev->ops->rdma_init(dev->cdev, in_params); 826 if (rc) 827 goto out; 828 829 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params); 830 if (rc) 831 goto out; 832 833 dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr; 834 dev->db_phys_addr = out_params.dpi_phys_addr; 835 dev->db_size = out_params.dpi_size; 836 dev->dpi = out_params.dpi; 837 838 rc = qedr_set_device_attr(dev); 839 out: 840 kfree(in_params); 841 if (rc) 842 DP_ERR(dev, "Init HW Failed rc = %d\n", rc); 843 844 return rc; 845 } 846 847 static void qedr_stop_hw(struct qedr_dev *dev) 848 { 849 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi); 850 dev->ops->rdma_stop(dev->rdma_ctx); 851 } 852 853 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev, 854 struct net_device *ndev) 855 { 856 struct qed_dev_rdma_info dev_info; 857 struct qedr_dev *dev; 858 int rc = 0, i; 859 860 dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev)); 861 if (!dev) { 862 pr_err("Unable to allocate ib device\n"); 863 return NULL; 864 } 865 866 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n"); 867 868 dev->pdev = pdev; 869 dev->ndev = ndev; 870 dev->cdev = cdev; 871 872 qed_ops = qed_get_rdma_ops(); 873 if (!qed_ops) { 874 DP_ERR(dev, "Failed to get qed roce operations\n"); 875 goto init_err; 876 } 877 878 dev->ops = qed_ops; 879 rc = qed_ops->fill_dev_info(cdev, &dev_info); 880 if (rc) 881 goto init_err; 882 883 dev->user_dpm_enabled = dev_info.user_dpm_enabled; 884 dev->rdma_type = dev_info.rdma_type; 885 dev->num_hwfns = dev_info.common.num_hwfns; 886 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev); 887 888 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev); 889 if (!dev->num_cnq) { 890 DP_ERR(dev, "Failed. At least one CNQ is required.\n"); 891 rc = -ENOMEM; 892 goto init_err; 893 } 894 895 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT; 896 897 qedr_pci_set_atomic(dev, pdev); 898 899 rc = qedr_alloc_resources(dev); 900 if (rc) 901 goto init_err; 902 903 rc = qedr_init_hw(dev); 904 if (rc) 905 goto alloc_err; 906 907 rc = qedr_setup_irqs(dev); 908 if (rc) 909 goto irq_err; 910 911 rc = qedr_register_device(dev); 912 if (rc) { 913 DP_ERR(dev, "Unable to allocate register device\n"); 914 goto reg_err; 915 } 916 917 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++) 918 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i])) 919 goto sysfs_err; 920 921 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 922 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 923 924 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n"); 925 return dev; 926 927 sysfs_err: 928 ib_unregister_device(&dev->ibdev); 929 reg_err: 930 qedr_sync_free_irqs(dev); 931 irq_err: 932 qedr_stop_hw(dev); 933 alloc_err: 934 qedr_free_resources(dev); 935 init_err: 936 ib_dealloc_device(&dev->ibdev); 937 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc); 938 939 return NULL; 940 } 941 942 static void qedr_remove(struct qedr_dev *dev) 943 { 944 /* First unregister with stack to stop all the active traffic 945 * of the registered clients. 946 */ 947 qedr_remove_sysfiles(dev); 948 ib_unregister_device(&dev->ibdev); 949 950 qedr_stop_hw(dev); 951 qedr_sync_free_irqs(dev); 952 qedr_free_resources(dev); 953 ib_dealloc_device(&dev->ibdev); 954 } 955 956 static void qedr_close(struct qedr_dev *dev) 957 { 958 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 959 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR); 960 } 961 962 static void qedr_shutdown(struct qedr_dev *dev) 963 { 964 qedr_close(dev); 965 qedr_remove(dev); 966 } 967 968 static void qedr_open(struct qedr_dev *dev) 969 { 970 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 971 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 972 } 973 974 static void qedr_mac_address_change(struct qedr_dev *dev) 975 { 976 union ib_gid *sgid = &dev->sgid_tbl[0]; 977 u8 guid[8], mac_addr[6]; 978 int rc; 979 980 /* Update SGID */ 981 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr); 982 guid[0] = mac_addr[0] ^ 2; 983 guid[1] = mac_addr[1]; 984 guid[2] = mac_addr[2]; 985 guid[3] = 0xff; 986 guid[4] = 0xfe; 987 guid[5] = mac_addr[3]; 988 guid[6] = mac_addr[4]; 989 guid[7] = mac_addr[5]; 990 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL); 991 memcpy(&sgid->raw[8], guid, sizeof(guid)); 992 993 /* Update LL2 */ 994 rc = dev->ops->ll2_set_mac_filter(dev->cdev, 995 dev->gsi_ll2_mac_address, 996 dev->ndev->dev_addr); 997 998 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr); 999 1000 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE); 1001 1002 if (rc) 1003 DP_ERR(dev, "Error updating mac filter\n"); 1004 } 1005 1006 /* event handling via NIC driver ensures that all the NIC specific 1007 * initialization done before RoCE driver notifies 1008 * event to stack. 1009 */ 1010 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event) 1011 { 1012 switch (event) { 1013 case QEDE_UP: 1014 qedr_open(dev); 1015 break; 1016 case QEDE_DOWN: 1017 qedr_close(dev); 1018 break; 1019 case QEDE_CLOSE: 1020 qedr_shutdown(dev); 1021 break; 1022 case QEDE_CHANGE_ADDR: 1023 qedr_mac_address_change(dev); 1024 break; 1025 default: 1026 pr_err("Event not supported\n"); 1027 } 1028 } 1029 1030 static struct qedr_driver qedr_drv = { 1031 .name = "qedr_driver", 1032 .add = qedr_add, 1033 .remove = qedr_remove, 1034 .notify = qedr_notify, 1035 }; 1036 1037 static int __init qedr_init_module(void) 1038 { 1039 return qede_rdma_register_driver(&qedr_drv); 1040 } 1041 1042 static void __exit qedr_exit_module(void) 1043 { 1044 qede_rdma_unregister_driver(&qedr_drv); 1045 } 1046 1047 module_init(qedr_init_module); 1048 module_exit(qedr_exit_module); 1049