1 /******************************************************************* 2 * This file is part of the Emulex RoCE Device Driver for * 3 * RoCE (RDMA over Converged Ethernet) adapters. * 4 * Copyright (C) 2008-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 * 20 * Contact Information: 21 * linux-drivers@emulex.com 22 * 23 * Emulex 24 * 3333 Susan Street 25 * Costa Mesa, CA 92626 26 *******************************************************************/ 27 28 #ifndef __OCRDMA_SLI_H__ 29 #define __OCRDMA_SLI_H__ 30 31 #define Bit(_b) (1 << (_b)) 32 33 #define OCRDMA_GEN1_FAMILY 0xB 34 #define OCRDMA_GEN2_FAMILY 0x2 35 36 #define OCRDMA_SUBSYS_ROCE 10 37 enum { 38 OCRDMA_CMD_QUERY_CONFIG = 1, 39 OCRDMA_CMD_ALLOC_PD, 40 OCRDMA_CMD_DEALLOC_PD, 41 42 OCRDMA_CMD_CREATE_AH_TBL, 43 OCRDMA_CMD_DELETE_AH_TBL, 44 45 OCRDMA_CMD_CREATE_QP, 46 OCRDMA_CMD_QUERY_QP, 47 OCRDMA_CMD_MODIFY_QP, 48 OCRDMA_CMD_DELETE_QP, 49 50 OCRDMA_CMD_RSVD1, 51 OCRDMA_CMD_ALLOC_LKEY, 52 OCRDMA_CMD_DEALLOC_LKEY, 53 OCRDMA_CMD_REGISTER_NSMR, 54 OCRDMA_CMD_REREGISTER_NSMR, 55 OCRDMA_CMD_REGISTER_NSMR_CONT, 56 OCRDMA_CMD_QUERY_NSMR, 57 OCRDMA_CMD_ALLOC_MW, 58 OCRDMA_CMD_QUERY_MW, 59 60 OCRDMA_CMD_CREATE_SRQ, 61 OCRDMA_CMD_QUERY_SRQ, 62 OCRDMA_CMD_MODIFY_SRQ, 63 OCRDMA_CMD_DELETE_SRQ, 64 65 OCRDMA_CMD_ATTACH_MCAST, 66 OCRDMA_CMD_DETACH_MCAST, 67 68 OCRDMA_CMD_MAX 69 }; 70 71 #define OCRDMA_SUBSYS_COMMON 1 72 enum { 73 OCRDMA_CMD_CREATE_CQ = 12, 74 OCRDMA_CMD_CREATE_EQ = 13, 75 OCRDMA_CMD_CREATE_MQ = 21, 76 OCRDMA_CMD_GET_FW_VER = 35, 77 OCRDMA_CMD_DELETE_MQ = 53, 78 OCRDMA_CMD_DELETE_CQ = 54, 79 OCRDMA_CMD_DELETE_EQ = 55, 80 OCRDMA_CMD_GET_FW_CONFIG = 58, 81 OCRDMA_CMD_CREATE_MQ_EXT = 90 82 }; 83 84 enum { 85 QTYPE_EQ = 1, 86 QTYPE_CQ = 2, 87 QTYPE_MCCQ = 3 88 }; 89 90 #define OCRDMA_MAX_SGID (8) 91 92 #define OCRDMA_MAX_QP 2048 93 #define OCRDMA_MAX_CQ 2048 94 #define OCRDMA_MAX_STAG 8192 95 96 enum { 97 OCRDMA_DB_RQ_OFFSET = 0xE0, 98 OCRDMA_DB_GEN2_RQ_OFFSET = 0x100, 99 OCRDMA_DB_SQ_OFFSET = 0x60, 100 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0, 101 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET, 102 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ_OFFSET, 103 OCRDMA_DB_CQ_OFFSET = 0x120, 104 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET, 105 OCRDMA_DB_MQ_OFFSET = 0x140 106 }; 107 108 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 109 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */ 110 /* qid #2 msbits at 12-11 */ 111 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1 112 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 113 /* Rearm bit */ 114 #define OCRDMA_DB_CQ_REARM_SHIFT (29) /* bit 29 */ 115 /* solicited bit */ 116 #define OCRDMA_DB_CQ_SOLICIT_SHIFT (31) /* bit 31 */ 117 118 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */ 119 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 120 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 at 11-15 */ 121 122 /* Clear the interrupt for this eq */ 123 #define OCRDMA_EQ_CLR_SHIFT (9) /* bit 9 */ 124 /* Must be 1 */ 125 #define OCRDMA_EQ_TYPE_SHIFT (10) /* bit 10 */ 126 /* Number of event entries processed */ 127 #define OCRDMA_NUM_EQE_SHIFT (16) /* bits 16 - 28 */ 128 /* Rearm bit */ 129 #define OCRDMA_REARM_SHIFT (29) /* bit 29 */ 130 131 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */ 132 /* Number of entries posted */ 133 #define OCRDMA_MQ_NUM_MQE_SHIFT (16) /* bits 16 - 29 */ 134 135 #define OCRDMA_MIN_HPAGE_SIZE (4096) 136 137 #define OCRDMA_MIN_Q_PAGE_SIZE (4096) 138 #define OCRDMA_MAX_Q_PAGES (8) 139 140 /* 141 # 0: 4K Bytes 142 # 1: 8K Bytes 143 # 2: 16K Bytes 144 # 3: 32K Bytes 145 # 4: 64K Bytes 146 # 5: 128K Bytes 147 # 6: 256K Bytes 148 # 7: 512K Bytes 149 */ 150 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8) 151 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES) 152 153 #define MAX_OCRDMA_QP_PAGES (8) 154 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE) 155 156 #define OCRDMA_CREATE_CQ_MAX_PAGES (4) 157 #define OCRDMA_DPP_CQE_SIZE (4) 158 159 #define OCRDMA_GEN2_MAX_CQE 1024 160 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096 161 #define OCRDMA_GEN2_WQE_SIZE 256 162 #define OCRDMA_MAX_CQE 4095 163 #define OCRDMA_CQ_PAGE_SIZE 16384 164 #define OCRDMA_WQE_SIZE 128 165 #define OCRDMA_WQE_STRIDE 8 166 #define OCRDMA_WQE_ALIGN_BYTES 16 167 168 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES 169 170 enum { 171 OCRDMA_MCH_OPCODE_SHIFT = 0, 172 OCRDMA_MCH_OPCODE_MASK = 0xFF, 173 OCRDMA_MCH_SUBSYS_SHIFT = 8, 174 OCRDMA_MCH_SUBSYS_MASK = 0xFF00 175 }; 176 177 /* mailbox cmd header */ 178 struct ocrdma_mbx_hdr { 179 u32 subsys_op; 180 u32 timeout; /* in seconds */ 181 u32 cmd_len; 182 u32 rsvd_version; 183 }; 184 185 enum { 186 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0, 187 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF, 188 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8, 189 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT, 190 191 OCRDMA_MBX_RSP_STATUS_SHIFT = 0, 192 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF, 193 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8, 194 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT 195 }; 196 197 /* mailbox cmd response */ 198 struct ocrdma_mbx_rsp { 199 u32 subsys_op; 200 u32 status; 201 u32 rsp_len; 202 u32 add_rsp_len; 203 }; 204 205 enum { 206 OCRDMA_MQE_EMBEDDED = 1, 207 OCRDMA_MQE_NONEMBEDDED = 0 208 }; 209 210 struct ocrdma_mqe_sge { 211 u32 pa_lo; 212 u32 pa_hi; 213 u32 len; 214 }; 215 216 enum { 217 OCRDMA_MQE_HDR_EMB_SHIFT = 0, 218 OCRDMA_MQE_HDR_EMB_MASK = Bit(0), 219 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3, 220 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT, 221 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24, 222 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT 223 }; 224 225 struct ocrdma_mqe_hdr { 226 u32 spcl_sge_cnt_emb; 227 u32 pyld_len; 228 u32 tag_lo; 229 u32 tag_hi; 230 u32 rsvd3; 231 }; 232 233 struct ocrdma_mqe_emb_cmd { 234 struct ocrdma_mbx_hdr mch; 235 u8 pyld[220]; 236 }; 237 238 struct ocrdma_mqe { 239 struct ocrdma_mqe_hdr hdr; 240 union { 241 struct ocrdma_mqe_emb_cmd emb_req; 242 struct { 243 struct ocrdma_mqe_sge sge[19]; 244 } nonemb_req; 245 u8 cmd[236]; 246 struct ocrdma_mbx_rsp rsp; 247 } u; 248 }; 249 250 #define OCRDMA_EQ_LEN 4096 251 #define OCRDMA_MQ_CQ_LEN 256 252 #define OCRDMA_MQ_LEN 128 253 254 #define PAGE_SHIFT_4K 12 255 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 256 257 /* Returns number of pages spanned by the data starting at the given addr */ 258 #define PAGES_4K_SPANNED(_address, size) \ 259 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 260 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 261 262 struct ocrdma_delete_q_req { 263 struct ocrdma_mbx_hdr req; 264 u32 id; 265 }; 266 267 struct ocrdma_pa { 268 u32 lo; 269 u32 hi; 270 }; 271 272 #define MAX_OCRDMA_EQ_PAGES (8) 273 struct ocrdma_create_eq_req { 274 struct ocrdma_mbx_hdr req; 275 u32 num_pages; 276 u32 valid; 277 u32 cnt; 278 u32 delay; 279 u32 rsvd; 280 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES]; 281 }; 282 283 enum { 284 OCRDMA_CREATE_EQ_VALID = Bit(29), 285 OCRDMA_CREATE_EQ_CNT_SHIFT = 26, 286 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13, 287 }; 288 289 struct ocrdma_create_eq_rsp { 290 struct ocrdma_mbx_rsp rsp; 291 u32 vector_eqid; 292 }; 293 294 #define OCRDMA_EQ_MINOR_OTHER (0x1) 295 296 enum { 297 OCRDMA_MCQE_STATUS_SHIFT = 0, 298 OCRDMA_MCQE_STATUS_MASK = 0xFFFF, 299 OCRDMA_MCQE_ESTATUS_SHIFT = 16, 300 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT, 301 OCRDMA_MCQE_CONS_SHIFT = 27, 302 OCRDMA_MCQE_CONS_MASK = Bit(27), 303 OCRDMA_MCQE_CMPL_SHIFT = 28, 304 OCRDMA_MCQE_CMPL_MASK = Bit(28), 305 OCRDMA_MCQE_AE_SHIFT = 30, 306 OCRDMA_MCQE_AE_MASK = Bit(30), 307 OCRDMA_MCQE_VALID_SHIFT = 31, 308 OCRDMA_MCQE_VALID_MASK = Bit(31) 309 }; 310 311 struct ocrdma_mcqe { 312 u32 status; 313 u32 tag_lo; 314 u32 tag_hi; 315 u32 valid_ae_cmpl_cons; 316 }; 317 318 enum { 319 OCRDMA_AE_MCQE_QPVALID = Bit(31), 320 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF, 321 322 OCRDMA_AE_MCQE_CQVALID = Bit(31), 323 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF, 324 OCRDMA_AE_MCQE_VALID = Bit(31), 325 OCRDMA_AE_MCQE_AE = Bit(30), 326 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16, 327 OCRDMA_AE_MCQE_EVENT_TYPE_MASK = 328 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT, 329 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8, 330 OCRDMA_AE_MCQE_EVENT_CODE_MASK = 331 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT 332 }; 333 struct ocrdma_ae_mcqe { 334 u32 qpvalid_qpid; 335 u32 cqvalid_cqid; 336 u32 evt_tag; 337 u32 valid_ae_event; 338 }; 339 340 enum { 341 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16, 342 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF << 343 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT, 344 345 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8, 346 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF << 347 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT, 348 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16, 349 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF << 350 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT, 351 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30, 352 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30), 353 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31, 354 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31) 355 }; 356 357 struct ocrdma_ae_mpa_mcqe { 358 u32 req_id; 359 u32 w1; 360 u32 w2; 361 u32 valid_ae_event; 362 }; 363 364 enum { 365 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0, 366 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF, 367 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16, 368 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF << 369 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT, 370 371 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8, 372 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF << 373 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT, 374 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16, 375 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF << 376 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT, 377 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30, 378 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30), 379 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31, 380 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31) 381 }; 382 383 struct ocrdma_ae_qp_mcqe { 384 u32 qp_id_state; 385 u32 w1; 386 u32 w2; 387 u32 valid_ae_event; 388 }; 389 390 #define OCRDMA_ASYNC_EVE_CODE 0x14 391 392 enum OCRDMA_ASYNC_EVENT_TYPE { 393 OCRDMA_CQ_ERROR = 0x00, 394 OCRDMA_CQ_OVERRUN_ERROR = 0x01, 395 OCRDMA_CQ_QPCAT_ERROR = 0x02, 396 OCRDMA_QP_ACCESS_ERROR = 0x03, 397 OCRDMA_QP_COMM_EST_EVENT = 0x04, 398 OCRDMA_SQ_DRAINED_EVENT = 0x05, 399 OCRDMA_DEVICE_FATAL_EVENT = 0x08, 400 OCRDMA_SRQCAT_ERROR = 0x0E, 401 OCRDMA_SRQ_LIMIT_EVENT = 0x0F, 402 OCRDMA_QP_LAST_WQE_EVENT = 0x10 403 }; 404 405 /* mailbox command request and responses */ 406 enum { 407 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2, 408 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2), 409 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3, 410 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3), 411 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8, 412 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF << 413 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT, 414 415 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16, 416 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF << 417 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT, 418 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8, 419 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF << 420 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT, 421 422 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0, 423 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF, 424 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16, 425 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF << 426 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT, 427 428 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0, 429 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF, 430 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16, 431 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF << 432 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT, 433 434 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24, 435 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF << 436 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET, 437 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16, 438 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF << 439 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET, 440 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0, 441 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF << 442 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET, 443 444 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16, 445 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF << 446 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET, 447 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0, 448 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF << 449 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET, 450 451 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16, 452 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF << 453 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET, 454 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0, 455 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF << 456 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET, 457 458 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0, 459 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF << 460 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET, 461 462 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16, 463 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF << 464 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET, 465 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0, 466 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF << 467 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET, 468 469 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16, 470 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF << 471 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET, 472 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0, 473 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF << 474 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET, 475 476 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16, 477 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF << 478 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET, 479 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0, 480 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF << 481 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET, 482 }; 483 484 struct ocrdma_mbx_query_config { 485 struct ocrdma_mqe_hdr hdr; 486 struct ocrdma_mbx_rsp rsp; 487 u32 qp_srq_cq_ird_ord; 488 u32 max_pd_ca_ack_delay; 489 u32 max_write_send_sge; 490 u32 max_ird_ord_per_qp; 491 u32 max_shared_ird_ord; 492 u32 max_mr; 493 u32 max_mr_size_lo; 494 u32 max_mr_size_hi; 495 u32 max_num_mr_pbl; 496 u32 max_mw; 497 u32 max_fmr; 498 u32 max_pages_per_frmr; 499 u32 max_mcast_group; 500 u32 max_mcast_qp_attach; 501 u32 max_total_mcast_qp_attach; 502 u32 wqe_rqe_stride_max_dpp_cqs; 503 u32 max_srq_rpir_qps; 504 u32 max_dpp_pds_credits; 505 u32 max_dpp_credits_pds_per_pd; 506 u32 max_wqes_rqes_per_q; 507 u32 max_cq_cqes_per_cq; 508 u32 max_srq_rqe_sge; 509 }; 510 511 struct ocrdma_fw_ver_rsp { 512 struct ocrdma_mqe_hdr hdr; 513 struct ocrdma_mbx_rsp rsp; 514 515 u8 running_ver[32]; 516 }; 517 518 struct ocrdma_fw_conf_rsp { 519 struct ocrdma_mqe_hdr hdr; 520 struct ocrdma_mbx_rsp rsp; 521 522 u32 config_num; 523 u32 asic_revision; 524 u32 phy_port; 525 u32 fn_mode; 526 struct { 527 u32 mode; 528 u32 nic_wqid_base; 529 u32 nic_wq_tot; 530 u32 prot_wqid_base; 531 u32 prot_wq_tot; 532 u32 prot_rqid_base; 533 u32 prot_rqid_tot; 534 u32 rsvd[6]; 535 } ulp[2]; 536 u32 fn_capabilities; 537 u32 rsvd1; 538 u32 rsvd2; 539 u32 base_eqid; 540 u32 max_eq; 541 542 }; 543 544 enum { 545 OCRDMA_FN_MODE_RDMA = 0x4 546 }; 547 548 enum { 549 OCRDMA_CREATE_CQ_VER2 = 2, 550 OCRDMA_CREATE_CQ_VER3 = 3, 551 552 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF, 553 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16, 554 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF, 555 556 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12, 557 OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12), 558 OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14), 559 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15), 560 561 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF, 562 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF 563 }; 564 565 enum { 566 OCRDMA_CREATE_CQ_VER0 = 0, 567 OCRDMA_CREATE_CQ_DPP = 1, 568 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24, 569 OCRDMA_CREATE_CQ_EQID_SHIFT = 22, 570 571 OCRDMA_CREATE_CQ_CNT_SHIFT = 27, 572 OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29), 573 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31), 574 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID | 575 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE | 576 OCRDMA_CREATE_CQ_FLAGS_NODELAY 577 }; 578 579 struct ocrdma_create_cq_cmd { 580 struct ocrdma_mbx_hdr req; 581 u32 pgsz_pgcnt; 582 u32 ev_cnt_flags; 583 u32 eqn; 584 u16 cqe_count; 585 u16 pd_id; 586 u32 rsvd6; 587 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES]; 588 }; 589 590 struct ocrdma_create_cq { 591 struct ocrdma_mqe_hdr hdr; 592 struct ocrdma_create_cq_cmd cmd; 593 }; 594 595 enum { 596 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF 597 }; 598 599 struct ocrdma_create_cq_cmd_rsp { 600 struct ocrdma_mbx_rsp rsp; 601 u32 cq_id; 602 }; 603 604 struct ocrdma_create_cq_rsp { 605 struct ocrdma_mqe_hdr hdr; 606 struct ocrdma_create_cq_cmd_rsp rsp; 607 }; 608 609 enum { 610 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22, 611 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16, 612 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16, 613 OCRDMA_CREATE_MQ_VALID = Bit(31), 614 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0) 615 }; 616 617 struct ocrdma_create_mq_req { 618 struct ocrdma_mbx_hdr req; 619 u32 cqid_pages; 620 u32 async_event_bitmap; 621 u32 async_cqid_ringsize; 622 u32 valid; 623 u32 async_cqid_valid; 624 u32 rsvd; 625 struct ocrdma_pa pa[8]; 626 }; 627 628 struct ocrdma_create_mq_rsp { 629 struct ocrdma_mbx_rsp rsp; 630 u32 id; 631 }; 632 633 enum { 634 OCRDMA_DESTROY_CQ_QID_SHIFT = 0, 635 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF, 636 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16, 637 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF << 638 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT 639 }; 640 641 struct ocrdma_destroy_cq { 642 struct ocrdma_mqe_hdr hdr; 643 struct ocrdma_mbx_hdr req; 644 645 u32 bypass_flush_qid; 646 }; 647 648 struct ocrdma_destroy_cq_rsp { 649 struct ocrdma_mqe_hdr hdr; 650 struct ocrdma_mbx_rsp rsp; 651 }; 652 653 enum { 654 OCRDMA_QPT_GSI = 1, 655 OCRDMA_QPT_RC = 2, 656 OCRDMA_QPT_UD = 4, 657 }; 658 659 enum { 660 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0, 661 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF, 662 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16, 663 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19, 664 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29, 665 OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29), 666 667 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0, 668 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF, 669 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16, 670 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF << 671 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT, 672 673 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0, 674 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF, 675 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16, 676 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF << 677 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT, 678 679 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0, 680 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0), 681 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1, 682 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1), 683 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2, 684 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2), 685 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3, 686 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3), 687 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4, 688 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4), 689 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5, 690 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5), 691 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6, 692 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6), 693 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7, 694 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7), 695 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8, 696 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8), 697 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16, 698 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF << 699 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT, 700 701 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0, 702 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF, 703 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16, 704 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF << 705 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT, 706 707 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0, 708 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF, 709 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16, 710 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF << 711 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT, 712 713 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0, 714 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF, 715 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16, 716 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF << 717 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT, 718 719 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0, 720 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF, 721 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16, 722 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF << 723 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT, 724 725 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0, 726 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF, 727 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16, 728 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF << 729 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT 730 }; 731 732 enum { 733 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16, 734 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1 735 }; 736 737 #define MAX_OCRDMA_IRD_PAGES 4 738 739 enum ocrdma_qp_flags { 740 OCRDMA_QP_MW_BIND = 1, 741 OCRDMA_QP_LKEY0 = (1 << 1), 742 OCRDMA_QP_FAST_REG = (1 << 2), 743 OCRDMA_QP_INB_RD = (1 << 6), 744 OCRDMA_QP_INB_WR = (1 << 7), 745 }; 746 747 enum ocrdma_qp_state { 748 OCRDMA_QPS_RST = 0, 749 OCRDMA_QPS_INIT = 1, 750 OCRDMA_QPS_RTR = 2, 751 OCRDMA_QPS_RTS = 3, 752 OCRDMA_QPS_SQE = 4, 753 OCRDMA_QPS_SQ_DRAINING = 5, 754 OCRDMA_QPS_ERR = 6, 755 OCRDMA_QPS_SQD = 7 756 }; 757 758 struct ocrdma_create_qp_req { 759 struct ocrdma_mqe_hdr hdr; 760 struct ocrdma_mbx_hdr req; 761 762 u32 type_pgsz_pdn; 763 u32 max_wqe_rqe; 764 u32 max_sge_send_write; 765 u32 max_sge_recv_flags; 766 u32 max_ord_ird; 767 u32 num_wq_rq_pages; 768 u32 wqe_rqe_size; 769 u32 wq_rq_cqid; 770 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES]; 771 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES]; 772 u32 dpp_credits_cqid; 773 u32 rpir_lkey; 774 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES]; 775 }; 776 777 enum { 778 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0, 779 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF, 780 781 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0, 782 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF, 783 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16, 784 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF << 785 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT, 786 787 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0, 788 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF, 789 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16, 790 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF << 791 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT, 792 793 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16, 794 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF << 795 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT, 796 797 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0, 798 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF, 799 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16, 800 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF << 801 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT, 802 803 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0, 804 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF, 805 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16, 806 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF << 807 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT, 808 809 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0), 810 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1, 811 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF << 812 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT, 813 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16, 814 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF << 815 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT, 816 }; 817 818 struct ocrdma_create_qp_rsp { 819 struct ocrdma_mqe_hdr hdr; 820 struct ocrdma_mbx_rsp rsp; 821 822 u32 qp_id; 823 u32 max_wqe_rqe; 824 u32 max_sge_send_write; 825 u32 max_sge_recv; 826 u32 max_ord_ird; 827 u32 sq_rq_id; 828 u32 dpp_response; 829 }; 830 831 struct ocrdma_destroy_qp { 832 struct ocrdma_mqe_hdr hdr; 833 struct ocrdma_mbx_hdr req; 834 u32 qp_id; 835 }; 836 837 struct ocrdma_destroy_qp_rsp { 838 struct ocrdma_mqe_hdr hdr; 839 struct ocrdma_mbx_rsp rsp; 840 }; 841 842 enum { 843 OCRDMA_MODIFY_QP_ID_SHIFT = 0, 844 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF, 845 846 OCRDMA_QP_PARA_QPS_VALID = Bit(0), 847 OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1), 848 OCRDMA_QP_PARA_PKEY_VALID = Bit(2), 849 OCRDMA_QP_PARA_QKEY_VALID = Bit(3), 850 OCRDMA_QP_PARA_PMTU_VALID = Bit(4), 851 OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5), 852 OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6), 853 OCRDMA_QP_PARA_RRC_VALID = Bit(7), 854 OCRDMA_QP_PARA_RQPSN_VALID = Bit(8), 855 OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9), 856 OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10), 857 OCRDMA_QP_PARA_RNT_VALID = Bit(11), 858 OCRDMA_QP_PARA_SQPSN_VALID = Bit(12), 859 OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13), 860 OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14), 861 OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15), 862 OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16), 863 OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17), 864 OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18), 865 OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19), 866 OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20), 867 OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21), 868 OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22), 869 OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23), 870 OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24), 871 OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25), 872 OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26), 873 874 OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0), 875 OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1), 876 OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2), 877 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3) 878 }; 879 880 enum { 881 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0, 882 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF, 883 884 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0, 885 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF, 886 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16, 887 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF << 888 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT, 889 890 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0, 891 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF, 892 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16, 893 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF << 894 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT, 895 896 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0), 897 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1), 898 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2), 899 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3), 900 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4), 901 OCRDMA_QP_PARAMS_STATE_SHIFT = 5, 902 OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7), 903 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8), 904 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9), 905 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16, 906 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF << 907 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT, 908 909 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0, 910 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF, 911 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16, 912 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF << 913 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT, 914 915 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0, 916 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF, 917 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16, 918 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF << 919 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT, 920 921 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0, 922 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF, 923 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24, 924 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF << 925 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT, 926 927 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0, 928 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF, 929 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24, 930 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF << 931 OCRDMA_QP_PARAMS_TCLASS_SHIFT, 932 933 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0, 934 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF, 935 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24, 936 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 << 937 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT, 938 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27, 939 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F << 940 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT, 941 942 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0, 943 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF, 944 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18, 945 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF << 946 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT, 947 948 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0, 949 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF, 950 OCRDMA_QP_PARAMS_SL_SHIFT = 20, 951 OCRDMA_QP_PARAMS_SL_MASK = 0xF << 952 OCRDMA_QP_PARAMS_SL_SHIFT, 953 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24, 954 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 << 955 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT, 956 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27, 957 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F << 958 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT, 959 960 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0, 961 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF, 962 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16, 963 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF << 964 OCRDMA_QP_PARAMS_VLAN_SHIFT 965 }; 966 967 struct ocrdma_qp_params { 968 u32 id; 969 u32 max_wqe_rqe; 970 u32 max_sge_send_write; 971 u32 max_sge_recv_flags; 972 u32 max_ord_ird; 973 u32 wq_rq_cqid; 974 u32 hop_lmt_rq_psn; 975 u32 tclass_sq_psn; 976 u32 ack_to_rnr_rtc_dest_qpn; 977 u32 path_mtu_pkey_indx; 978 u32 rnt_rc_sl_fl; 979 u8 sgid[16]; 980 u8 dgid[16]; 981 u32 dmac_b0_to_b3; 982 u32 vlan_dmac_b4_to_b5; 983 u32 qkey; 984 }; 985 986 987 struct ocrdma_modify_qp { 988 struct ocrdma_mqe_hdr hdr; 989 struct ocrdma_mbx_hdr req; 990 991 struct ocrdma_qp_params params; 992 u32 flags; 993 u32 rdma_flags; 994 u32 num_outstanding_atomic_rd; 995 }; 996 997 enum { 998 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0, 999 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF, 1000 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16, 1001 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF << 1002 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT, 1003 1004 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0, 1005 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF, 1006 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16, 1007 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF << 1008 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT 1009 }; 1010 struct ocrdma_modify_qp_rsp { 1011 struct ocrdma_mqe_hdr hdr; 1012 struct ocrdma_mbx_rsp rsp; 1013 1014 u32 max_wqe_rqe; 1015 u32 max_ord_ird; 1016 }; 1017 1018 struct ocrdma_query_qp { 1019 struct ocrdma_mqe_hdr hdr; 1020 struct ocrdma_mbx_hdr req; 1021 1022 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0 1023 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF 1024 u32 qp_id; 1025 }; 1026 1027 struct ocrdma_query_qp_rsp { 1028 struct ocrdma_mqe_hdr hdr; 1029 struct ocrdma_mbx_rsp rsp; 1030 struct ocrdma_qp_params params; 1031 }; 1032 1033 enum { 1034 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0, 1035 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF, 1036 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16, 1037 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 << 1038 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT, 1039 1040 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0, 1041 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16, 1042 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF << 1043 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT, 1044 1045 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0, 1046 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF, 1047 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16, 1048 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF << 1049 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT 1050 }; 1051 1052 struct ocrdma_create_srq { 1053 struct ocrdma_mqe_hdr hdr; 1054 struct ocrdma_mbx_hdr req; 1055 1056 u32 pgsz_pdid; 1057 u32 max_sge_rqe; 1058 u32 pages_rqe_sz; 1059 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES]; 1060 }; 1061 1062 enum { 1063 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0, 1064 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF, 1065 1066 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0, 1067 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF, 1068 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16, 1069 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF << 1070 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT 1071 }; 1072 1073 struct ocrdma_create_srq_rsp { 1074 struct ocrdma_mqe_hdr hdr; 1075 struct ocrdma_mbx_rsp rsp; 1076 1077 u32 id; 1078 u32 max_sge_rqe_allocated; 1079 }; 1080 1081 enum { 1082 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0, 1083 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF, 1084 1085 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0, 1086 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF, 1087 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16, 1088 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF << 1089 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT 1090 }; 1091 1092 struct ocrdma_modify_srq { 1093 struct ocrdma_mqe_hdr hdr; 1094 struct ocrdma_mbx_rsp rep; 1095 1096 u32 id; 1097 u32 limit_max_rqe; 1098 }; 1099 1100 enum { 1101 OCRDMA_QUERY_SRQ_ID_SHIFT = 0, 1102 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF 1103 }; 1104 1105 struct ocrdma_query_srq { 1106 struct ocrdma_mqe_hdr hdr; 1107 struct ocrdma_mbx_rsp req; 1108 1109 u32 id; 1110 }; 1111 1112 enum { 1113 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0, 1114 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF, 1115 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16, 1116 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF << 1117 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT, 1118 1119 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0, 1120 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF, 1121 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16, 1122 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF << 1123 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT 1124 }; 1125 1126 struct ocrdma_query_srq_rsp { 1127 struct ocrdma_mqe_hdr hdr; 1128 struct ocrdma_mbx_rsp req; 1129 1130 u32 max_rqe_pdid; 1131 u32 srq_lmt_max_sge; 1132 }; 1133 1134 enum { 1135 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0, 1136 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF 1137 }; 1138 1139 struct ocrdma_destroy_srq { 1140 struct ocrdma_mqe_hdr hdr; 1141 struct ocrdma_mbx_rsp req; 1142 1143 u32 id; 1144 }; 1145 1146 enum { 1147 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16), 1148 OCRDMA_PD_MAX_DPP_ENABLED_QP = 8, 1149 OCRDMA_DPP_PAGE_SIZE = 4096 1150 }; 1151 1152 struct ocrdma_alloc_pd { 1153 struct ocrdma_mqe_hdr hdr; 1154 struct ocrdma_mbx_hdr req; 1155 u32 enable_dpp_rsvd; 1156 }; 1157 1158 enum { 1159 OCRDMA_ALLOC_PD_RSP_DPP = Bit(16), 1160 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20, 1161 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF, 1162 }; 1163 1164 struct ocrdma_alloc_pd_rsp { 1165 struct ocrdma_mqe_hdr hdr; 1166 struct ocrdma_mbx_rsp rsp; 1167 u32 dpp_page_pdid; 1168 }; 1169 1170 struct ocrdma_dealloc_pd { 1171 struct ocrdma_mqe_hdr hdr; 1172 struct ocrdma_mbx_hdr req; 1173 u32 id; 1174 }; 1175 1176 struct ocrdma_dealloc_pd_rsp { 1177 struct ocrdma_mqe_hdr hdr; 1178 struct ocrdma_mbx_rsp rsp; 1179 }; 1180 1181 enum { 1182 OCRDMA_ADDR_CHECK_ENABLE = 1, 1183 OCRDMA_ADDR_CHECK_DISABLE = 0 1184 }; 1185 1186 enum { 1187 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0, 1188 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF, 1189 1190 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0, 1191 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0), 1192 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1, 1193 OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1), 1194 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2, 1195 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2), 1196 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3, 1197 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3), 1198 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4, 1199 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4), 1200 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5, 1201 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5), 1202 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6), 1203 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6, 1204 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16, 1205 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF << 1206 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT 1207 }; 1208 1209 struct ocrdma_alloc_lkey { 1210 struct ocrdma_mqe_hdr hdr; 1211 struct ocrdma_mbx_hdr req; 1212 1213 u32 pdid; 1214 u32 pbl_sz_flags; 1215 }; 1216 1217 struct ocrdma_alloc_lkey_rsp { 1218 struct ocrdma_mqe_hdr hdr; 1219 struct ocrdma_mbx_rsp rsp; 1220 1221 u32 lrkey; 1222 u32 num_pbl_rsvd; 1223 }; 1224 1225 struct ocrdma_dealloc_lkey { 1226 struct ocrdma_mqe_hdr hdr; 1227 struct ocrdma_mbx_hdr req; 1228 1229 u32 lkey; 1230 u32 rsvd_frmr; 1231 }; 1232 1233 struct ocrdma_dealloc_lkey_rsp { 1234 struct ocrdma_mqe_hdr hdr; 1235 struct ocrdma_mbx_rsp rsp; 1236 }; 1237 1238 #define MAX_OCRDMA_NSMR_PBL (u32)22 1239 #define MAX_OCRDMA_PBL_SIZE 65536 1240 #define MAX_OCRDMA_PBL_PER_LKEY 32767 1241 1242 enum { 1243 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0, 1244 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF, 1245 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24, 1246 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF << 1247 OCRDMA_REG_NSMR_LRKEY_SHIFT, 1248 1249 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0, 1250 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF, 1251 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16, 1252 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF << 1253 OCRDMA_REG_NSMR_NUM_PBL_SHIFT, 1254 1255 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0, 1256 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF, 1257 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16, 1258 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF << 1259 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT, 1260 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24, 1261 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24), 1262 OCRDMA_REG_NSMR_ZB_SHIFT = 25, 1263 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25), 1264 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26, 1265 OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26), 1266 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27, 1267 OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27), 1268 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28, 1269 OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28), 1270 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29, 1271 OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29), 1272 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30, 1273 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30), 1274 OCRDMA_REG_NSMR_LAST_SHIFT = 31, 1275 OCRDMA_REG_NSMR_LAST_MASK = Bit(31) 1276 }; 1277 1278 struct ocrdma_reg_nsmr { 1279 struct ocrdma_mqe_hdr hdr; 1280 struct ocrdma_mbx_hdr cmd; 1281 1282 u32 fr_mr; 1283 u32 num_pbl_pdid; 1284 u32 flags_hpage_pbe_sz; 1285 u32 totlen_low; 1286 u32 totlen_high; 1287 u32 fbo_low; 1288 u32 fbo_high; 1289 u32 va_loaddr; 1290 u32 va_hiaddr; 1291 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1292 }; 1293 1294 enum { 1295 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0, 1296 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF, 1297 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16, 1298 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF << 1299 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT, 1300 1301 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31, 1302 OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31) 1303 }; 1304 1305 struct ocrdma_reg_nsmr_cont { 1306 struct ocrdma_mqe_hdr hdr; 1307 struct ocrdma_mbx_hdr cmd; 1308 1309 u32 lrkey; 1310 u32 num_pbl_offset; 1311 u32 last; 1312 1313 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1314 }; 1315 1316 struct ocrdma_pbe { 1317 u32 pa_hi; 1318 u32 pa_lo; 1319 }; 1320 1321 enum { 1322 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16, 1323 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000 1324 }; 1325 struct ocrdma_reg_nsmr_rsp { 1326 struct ocrdma_mqe_hdr hdr; 1327 struct ocrdma_mbx_rsp rsp; 1328 1329 u32 lrkey; 1330 u32 num_pbl; 1331 }; 1332 1333 enum { 1334 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0, 1335 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF, 1336 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24, 1337 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF << 1338 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT, 1339 1340 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16, 1341 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF << 1342 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT 1343 }; 1344 1345 struct ocrdma_reg_nsmr_cont_rsp { 1346 struct ocrdma_mqe_hdr hdr; 1347 struct ocrdma_mbx_rsp rsp; 1348 1349 u32 lrkey_key_index; 1350 u32 num_pbl; 1351 }; 1352 1353 enum { 1354 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0, 1355 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF 1356 }; 1357 1358 struct ocrdma_alloc_mw { 1359 struct ocrdma_mqe_hdr hdr; 1360 struct ocrdma_mbx_hdr req; 1361 1362 u32 pdid; 1363 }; 1364 1365 enum { 1366 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0, 1367 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF 1368 }; 1369 1370 struct ocrdma_alloc_mw_rsp { 1371 struct ocrdma_mqe_hdr hdr; 1372 struct ocrdma_mbx_rsp rsp; 1373 1374 u32 lrkey_index; 1375 }; 1376 1377 struct ocrdma_attach_mcast { 1378 struct ocrdma_mqe_hdr hdr; 1379 struct ocrdma_mbx_hdr req; 1380 u32 qp_id; 1381 u8 mgid[16]; 1382 u32 mac_b0_to_b3; 1383 u32 vlan_mac_b4_to_b5; 1384 }; 1385 1386 struct ocrdma_attach_mcast_rsp { 1387 struct ocrdma_mqe_hdr hdr; 1388 struct ocrdma_mbx_rsp rsp; 1389 }; 1390 1391 struct ocrdma_detach_mcast { 1392 struct ocrdma_mqe_hdr hdr; 1393 struct ocrdma_mbx_hdr req; 1394 u32 qp_id; 1395 u8 mgid[16]; 1396 u32 mac_b0_to_b3; 1397 u32 vlan_mac_b4_to_b5; 1398 }; 1399 1400 struct ocrdma_detach_mcast_rsp { 1401 struct ocrdma_mqe_hdr hdr; 1402 struct ocrdma_mbx_rsp rsp; 1403 }; 1404 1405 enum { 1406 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19, 1407 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF << 1408 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT, 1409 1410 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16, 1411 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 << 1412 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT, 1413 1414 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23, 1415 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF << 1416 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT, 1417 }; 1418 1419 #define OCRDMA_AH_TBL_PAGES 8 1420 1421 struct ocrdma_create_ah_tbl { 1422 struct ocrdma_mqe_hdr hdr; 1423 struct ocrdma_mbx_hdr req; 1424 1425 u32 ah_conf; 1426 struct ocrdma_pa tbl_addr[8]; 1427 }; 1428 1429 struct ocrdma_create_ah_tbl_rsp { 1430 struct ocrdma_mqe_hdr hdr; 1431 struct ocrdma_mbx_rsp rsp; 1432 u32 ahid; 1433 }; 1434 1435 struct ocrdma_delete_ah_tbl { 1436 struct ocrdma_mqe_hdr hdr; 1437 struct ocrdma_mbx_hdr req; 1438 u32 ahid; 1439 }; 1440 1441 struct ocrdma_delete_ah_tbl_rsp { 1442 struct ocrdma_mqe_hdr hdr; 1443 struct ocrdma_mbx_rsp rsp; 1444 }; 1445 1446 enum { 1447 OCRDMA_EQE_VALID_SHIFT = 0, 1448 OCRDMA_EQE_VALID_MASK = Bit(0), 1449 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE, 1450 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16, 1451 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF << 1452 OCRDMA_EQE_RESOURCE_ID_SHIFT, 1453 }; 1454 1455 struct ocrdma_eqe { 1456 u32 id_valid; 1457 }; 1458 1459 enum OCRDMA_CQE_STATUS { 1460 OCRDMA_CQE_SUCCESS = 0, 1461 OCRDMA_CQE_LOC_LEN_ERR, 1462 OCRDMA_CQE_LOC_QP_OP_ERR, 1463 OCRDMA_CQE_LOC_EEC_OP_ERR, 1464 OCRDMA_CQE_LOC_PROT_ERR, 1465 OCRDMA_CQE_WR_FLUSH_ERR, 1466 OCRDMA_CQE_MW_BIND_ERR, 1467 OCRDMA_CQE_BAD_RESP_ERR, 1468 OCRDMA_CQE_LOC_ACCESS_ERR, 1469 OCRDMA_CQE_REM_INV_REQ_ERR, 1470 OCRDMA_CQE_REM_ACCESS_ERR, 1471 OCRDMA_CQE_REM_OP_ERR, 1472 OCRDMA_CQE_RETRY_EXC_ERR, 1473 OCRDMA_CQE_RNR_RETRY_EXC_ERR, 1474 OCRDMA_CQE_LOC_RDD_VIOL_ERR, 1475 OCRDMA_CQE_REM_INV_RD_REQ_ERR, 1476 OCRDMA_CQE_REM_ABORT_ERR, 1477 OCRDMA_CQE_INV_EECN_ERR, 1478 OCRDMA_CQE_INV_EEC_STATE_ERR, 1479 OCRDMA_CQE_FATAL_ERR, 1480 OCRDMA_CQE_RESP_TIMEOUT_ERR, 1481 OCRDMA_CQE_GENERAL_ERR 1482 }; 1483 1484 enum { 1485 /* w0 */ 1486 OCRDMA_CQE_WQEIDX_SHIFT = 0, 1487 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF, 1488 1489 /* w1 */ 1490 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16, 1491 OCRDMA_CQE_PKEY_SHIFT = 0, 1492 OCRDMA_CQE_PKEY_MASK = 0xFFFF, 1493 1494 /* w2 */ 1495 OCRDMA_CQE_QPN_SHIFT = 0, 1496 OCRDMA_CQE_QPN_MASK = 0x0000FFFF, 1497 1498 OCRDMA_CQE_BUFTAG_SHIFT = 16, 1499 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT, 1500 1501 /* w3 */ 1502 OCRDMA_CQE_UD_STATUS_SHIFT = 24, 1503 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT, 1504 OCRDMA_CQE_STATUS_SHIFT = 16, 1505 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT, 1506 OCRDMA_CQE_VALID = Bit(31), 1507 OCRDMA_CQE_INVALIDATE = Bit(30), 1508 OCRDMA_CQE_QTYPE = Bit(29), 1509 OCRDMA_CQE_IMM = Bit(28), 1510 OCRDMA_CQE_WRITE_IMM = Bit(27), 1511 OCRDMA_CQE_QTYPE_SQ = 0, 1512 OCRDMA_CQE_QTYPE_RQ = 1, 1513 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF 1514 }; 1515 1516 struct ocrdma_cqe { 1517 union { 1518 /* w0 to w2 */ 1519 struct { 1520 u32 wqeidx; 1521 u32 bytes_xfered; 1522 u32 qpn; 1523 } wq; 1524 struct { 1525 u32 lkey_immdt; 1526 u32 rxlen; 1527 u32 buftag_qpn; 1528 } rq; 1529 struct { 1530 u32 lkey_immdt; 1531 u32 rxlen_pkey; 1532 u32 buftag_qpn; 1533 } ud; 1534 struct { 1535 u32 word_0; 1536 u32 word_1; 1537 u32 qpn; 1538 } cmn; 1539 }; 1540 u32 flags_status_srcqpn; /* w3 */ 1541 }; 1542 1543 struct ocrdma_sge { 1544 u32 addr_hi; 1545 u32 addr_lo; 1546 u32 lrkey; 1547 u32 len; 1548 }; 1549 1550 enum { 1551 OCRDMA_FLAG_SIG = 0x1, 1552 OCRDMA_FLAG_INV = 0x2, 1553 OCRDMA_FLAG_FENCE_L = 0x4, 1554 OCRDMA_FLAG_FENCE_R = 0x8, 1555 OCRDMA_FLAG_SOLICIT = 0x10, 1556 OCRDMA_FLAG_IMM = 0x20, 1557 1558 /* Stag flags */ 1559 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1, 1560 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2, 1561 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4, 1562 OCRDMA_LKEY_FLAG_VATO = 0x8, 1563 }; 1564 1565 enum OCRDMA_WQE_OPCODE { 1566 OCRDMA_WRITE = 0x06, 1567 OCRDMA_READ = 0x0C, 1568 OCRDMA_RESV0 = 0x02, 1569 OCRDMA_SEND = 0x00, 1570 OCRDMA_CMP_SWP = 0x14, 1571 OCRDMA_BIND_MW = 0x10, 1572 OCRDMA_FR_MR = 0x11, 1573 OCRDMA_RESV1 = 0x0A, 1574 OCRDMA_LKEY_INV = 0x15, 1575 OCRDMA_FETCH_ADD = 0x13, 1576 OCRDMA_POST_RQ = 0x12 1577 }; 1578 1579 enum { 1580 OCRDMA_TYPE_INLINE = 0x0, 1581 OCRDMA_TYPE_LKEY = 0x1, 1582 }; 1583 1584 enum { 1585 OCRDMA_WQE_OPCODE_SHIFT = 0, 1586 OCRDMA_WQE_OPCODE_MASK = 0x0000001F, 1587 OCRDMA_WQE_FLAGS_SHIFT = 5, 1588 OCRDMA_WQE_TYPE_SHIFT = 16, 1589 OCRDMA_WQE_TYPE_MASK = 0x00030000, 1590 OCRDMA_WQE_SIZE_SHIFT = 18, 1591 OCRDMA_WQE_SIZE_MASK = 0xFF, 1592 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25, 1593 1594 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0, 1595 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF 1596 }; 1597 1598 /* header WQE for all the SQ and RQ operations */ 1599 struct ocrdma_hdr_wqe { 1600 u32 cw; 1601 union { 1602 u32 rsvd_tag; 1603 u32 rsvd_lkey_flags; 1604 }; 1605 union { 1606 u32 immdt; 1607 u32 lkey; 1608 }; 1609 u32 total_len; 1610 }; 1611 1612 struct ocrdma_ewqe_ud_hdr { 1613 u32 rsvd_dest_qpn; 1614 u32 qkey; 1615 u32 rsvd_ahid; 1616 u32 rsvd; 1617 }; 1618 1619 /* extended wqe followed by hdr_wqe for Fast Memory register */ 1620 struct ocrdma_ewqe_fr { 1621 u32 va_hi; 1622 u32 va_lo; 1623 u32 fbo_hi; 1624 u32 fbo_lo; 1625 u32 size_sge; 1626 u32 num_sges; 1627 u32 rsvd; 1628 u32 rsvd2; 1629 }; 1630 1631 struct ocrdma_eth_basic { 1632 u8 dmac[6]; 1633 u8 smac[6]; 1634 __be16 eth_type; 1635 } __packed; 1636 1637 struct ocrdma_eth_vlan { 1638 u8 dmac[6]; 1639 u8 smac[6]; 1640 __be16 eth_type; 1641 __be16 vlan_tag; 1642 #define OCRDMA_ROCE_ETH_TYPE 0x8915 1643 __be16 roce_eth_type; 1644 } __packed; 1645 1646 struct ocrdma_grh { 1647 __be32 tclass_flow; 1648 __be32 pdid_hoplimit; 1649 u8 sgid[16]; 1650 u8 dgid[16]; 1651 u16 rsvd; 1652 } __packed; 1653 1654 #define OCRDMA_AV_VALID Bit(0) 1655 #define OCRDMA_AV_VLAN_VALID Bit(1) 1656 1657 struct ocrdma_av { 1658 struct ocrdma_eth_vlan eth_hdr; 1659 struct ocrdma_grh grh; 1660 u32 valid; 1661 } __packed; 1662 1663 #endif /* __OCRDMA_SLI_H__ */ 1664