1 /******************************************************************* 2 * This file is part of the Emulex RoCE Device Driver for * 3 * RoCE (RDMA over Converged Ethernet) adapters. * 4 * Copyright (C) 2008-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 * 20 * Contact Information: 21 * linux-drivers@emulex.com 22 * 23 * Emulex 24 * 3333 Susan Street 25 * Costa Mesa, CA 92626 26 *******************************************************************/ 27 28 #ifndef __OCRDMA_SLI_H__ 29 #define __OCRDMA_SLI_H__ 30 31 #define Bit(_b) (1 << (_b)) 32 33 #define OCRDMA_GEN1_FAMILY 0xB 34 #define OCRDMA_GEN2_FAMILY 0x2 35 36 #define OCRDMA_SUBSYS_ROCE 10 37 enum { 38 OCRDMA_CMD_QUERY_CONFIG = 1, 39 OCRDMA_CMD_ALLOC_PD, 40 OCRDMA_CMD_DEALLOC_PD, 41 42 OCRDMA_CMD_CREATE_AH_TBL, 43 OCRDMA_CMD_DELETE_AH_TBL, 44 45 OCRDMA_CMD_CREATE_QP, 46 OCRDMA_CMD_QUERY_QP, 47 OCRDMA_CMD_MODIFY_QP, 48 OCRDMA_CMD_DELETE_QP, 49 50 OCRDMA_CMD_RSVD1, 51 OCRDMA_CMD_ALLOC_LKEY, 52 OCRDMA_CMD_DEALLOC_LKEY, 53 OCRDMA_CMD_REGISTER_NSMR, 54 OCRDMA_CMD_REREGISTER_NSMR, 55 OCRDMA_CMD_REGISTER_NSMR_CONT, 56 OCRDMA_CMD_QUERY_NSMR, 57 OCRDMA_CMD_ALLOC_MW, 58 OCRDMA_CMD_QUERY_MW, 59 60 OCRDMA_CMD_CREATE_SRQ, 61 OCRDMA_CMD_QUERY_SRQ, 62 OCRDMA_CMD_MODIFY_SRQ, 63 OCRDMA_CMD_DELETE_SRQ, 64 65 OCRDMA_CMD_ATTACH_MCAST, 66 OCRDMA_CMD_DETACH_MCAST, 67 68 OCRDMA_CMD_MAX 69 }; 70 71 #define OCRDMA_SUBSYS_COMMON 1 72 enum { 73 OCRDMA_CMD_CREATE_CQ = 12, 74 OCRDMA_CMD_CREATE_EQ = 13, 75 OCRDMA_CMD_CREATE_MQ = 21, 76 OCRDMA_CMD_GET_FW_VER = 35, 77 OCRDMA_CMD_DELETE_MQ = 53, 78 OCRDMA_CMD_DELETE_CQ = 54, 79 OCRDMA_CMD_DELETE_EQ = 55, 80 OCRDMA_CMD_GET_FW_CONFIG = 58, 81 OCRDMA_CMD_CREATE_MQ_EXT = 90 82 }; 83 84 enum { 85 QTYPE_EQ = 1, 86 QTYPE_CQ = 2, 87 QTYPE_MCCQ = 3 88 }; 89 90 #define OCRDMA_MAX_SGID (8) 91 92 #define OCRDMA_MAX_QP 2048 93 #define OCRDMA_MAX_CQ 2048 94 95 enum { 96 OCRDMA_DB_RQ_OFFSET = 0xE0, 97 OCRDMA_DB_GEN2_RQ1_OFFSET = 0x100, 98 OCRDMA_DB_GEN2_RQ2_OFFSET = 0xC0, 99 OCRDMA_DB_SQ_OFFSET = 0x60, 100 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0, 101 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET, 102 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ1_OFFSET, 103 OCRDMA_DB_CQ_OFFSET = 0x120, 104 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET, 105 OCRDMA_DB_MQ_OFFSET = 0x140 106 }; 107 108 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 109 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */ 110 /* qid #2 msbits at 12-11 */ 111 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1 112 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 113 /* Rearm bit */ 114 #define OCRDMA_DB_CQ_REARM_SHIFT (29) /* bit 29 */ 115 /* solicited bit */ 116 #define OCRDMA_DB_CQ_SOLICIT_SHIFT (31) /* bit 31 */ 117 118 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */ 119 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 120 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 at 11-15 */ 121 122 /* Clear the interrupt for this eq */ 123 #define OCRDMA_EQ_CLR_SHIFT (9) /* bit 9 */ 124 /* Must be 1 */ 125 #define OCRDMA_EQ_TYPE_SHIFT (10) /* bit 10 */ 126 /* Number of event entries processed */ 127 #define OCRDMA_NUM_EQE_SHIFT (16) /* bits 16 - 28 */ 128 /* Rearm bit */ 129 #define OCRDMA_REARM_SHIFT (29) /* bit 29 */ 130 131 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */ 132 /* Number of entries posted */ 133 #define OCRDMA_MQ_NUM_MQE_SHIFT (16) /* bits 16 - 29 */ 134 135 #define OCRDMA_MIN_HPAGE_SIZE (4096) 136 137 #define OCRDMA_MIN_Q_PAGE_SIZE (4096) 138 #define OCRDMA_MAX_Q_PAGES (8) 139 140 /* 141 # 0: 4K Bytes 142 # 1: 8K Bytes 143 # 2: 16K Bytes 144 # 3: 32K Bytes 145 # 4: 64K Bytes 146 */ 147 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (5) 148 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES) 149 150 #define MAX_OCRDMA_QP_PAGES (8) 151 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE) 152 153 #define OCRDMA_CREATE_CQ_MAX_PAGES (4) 154 #define OCRDMA_DPP_CQE_SIZE (4) 155 156 #define OCRDMA_GEN2_MAX_CQE 1024 157 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096 158 #define OCRDMA_GEN2_WQE_SIZE 256 159 #define OCRDMA_MAX_CQE 4095 160 #define OCRDMA_CQ_PAGE_SIZE 16384 161 #define OCRDMA_WQE_SIZE 128 162 #define OCRDMA_WQE_STRIDE 8 163 #define OCRDMA_WQE_ALIGN_BYTES 16 164 165 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES 166 167 enum { 168 OCRDMA_MCH_OPCODE_SHIFT = 0, 169 OCRDMA_MCH_OPCODE_MASK = 0xFF, 170 OCRDMA_MCH_SUBSYS_SHIFT = 8, 171 OCRDMA_MCH_SUBSYS_MASK = 0xFF00 172 }; 173 174 /* mailbox cmd header */ 175 struct ocrdma_mbx_hdr { 176 u32 subsys_op; 177 u32 timeout; /* in seconds */ 178 u32 cmd_len; 179 u32 rsvd_version; 180 } __packed; 181 182 enum { 183 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0, 184 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF, 185 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8, 186 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT, 187 188 OCRDMA_MBX_RSP_STATUS_SHIFT = 0, 189 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF, 190 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8, 191 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT 192 }; 193 194 /* mailbox cmd response */ 195 struct ocrdma_mbx_rsp { 196 u32 subsys_op; 197 u32 status; 198 u32 rsp_len; 199 u32 add_rsp_len; 200 } __packed; 201 202 enum { 203 OCRDMA_MQE_EMBEDDED = 1, 204 OCRDMA_MQE_NONEMBEDDED = 0 205 }; 206 207 struct ocrdma_mqe_sge { 208 u32 pa_lo; 209 u32 pa_hi; 210 u32 len; 211 } __packed; 212 213 enum { 214 OCRDMA_MQE_HDR_EMB_SHIFT = 0, 215 OCRDMA_MQE_HDR_EMB_MASK = Bit(0), 216 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3, 217 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT, 218 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24, 219 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT 220 }; 221 222 struct ocrdma_mqe_hdr { 223 u32 spcl_sge_cnt_emb; 224 u32 pyld_len; 225 u32 tag_lo; 226 u32 tag_hi; 227 u32 rsvd3; 228 } __packed; 229 230 struct ocrdma_mqe_emb_cmd { 231 struct ocrdma_mbx_hdr mch; 232 u8 pyld[220]; 233 } __packed; 234 235 struct ocrdma_mqe { 236 struct ocrdma_mqe_hdr hdr; 237 union { 238 struct ocrdma_mqe_emb_cmd emb_req; 239 struct { 240 struct ocrdma_mqe_sge sge[19]; 241 } nonemb_req; 242 u8 cmd[236]; 243 struct ocrdma_mbx_rsp rsp; 244 } u; 245 } __packed; 246 247 #define OCRDMA_EQ_LEN 4096 248 #define OCRDMA_MQ_CQ_LEN 256 249 #define OCRDMA_MQ_LEN 128 250 251 #define PAGE_SHIFT_4K 12 252 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 253 254 /* Returns number of pages spanned by the data starting at the given addr */ 255 #define PAGES_4K_SPANNED(_address, size) \ 256 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 257 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 258 259 struct ocrdma_delete_q_req { 260 struct ocrdma_mbx_hdr req; 261 u32 id; 262 } __packed; 263 264 struct ocrdma_pa { 265 u32 lo; 266 u32 hi; 267 } __packed; 268 269 #define MAX_OCRDMA_EQ_PAGES (8) 270 struct ocrdma_create_eq_req { 271 struct ocrdma_mbx_hdr req; 272 u32 num_pages; 273 u32 valid; 274 u32 cnt; 275 u32 delay; 276 u32 rsvd; 277 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES]; 278 } __packed; 279 280 enum { 281 OCRDMA_CREATE_EQ_VALID = Bit(29), 282 OCRDMA_CREATE_EQ_CNT_SHIFT = 26, 283 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13, 284 }; 285 286 struct ocrdma_create_eq_rsp { 287 struct ocrdma_mbx_rsp rsp; 288 u32 vector_eqid; 289 }; 290 291 #define OCRDMA_EQ_MINOR_OTHER (0x1) 292 293 enum { 294 OCRDMA_MCQE_STATUS_SHIFT = 0, 295 OCRDMA_MCQE_STATUS_MASK = 0xFFFF, 296 OCRDMA_MCQE_ESTATUS_SHIFT = 16, 297 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT, 298 OCRDMA_MCQE_CONS_SHIFT = 27, 299 OCRDMA_MCQE_CONS_MASK = Bit(27), 300 OCRDMA_MCQE_CMPL_SHIFT = 28, 301 OCRDMA_MCQE_CMPL_MASK = Bit(28), 302 OCRDMA_MCQE_AE_SHIFT = 30, 303 OCRDMA_MCQE_AE_MASK = Bit(30), 304 OCRDMA_MCQE_VALID_SHIFT = 31, 305 OCRDMA_MCQE_VALID_MASK = Bit(31) 306 }; 307 308 struct ocrdma_mcqe { 309 u32 status; 310 u32 tag_lo; 311 u32 tag_hi; 312 u32 valid_ae_cmpl_cons; 313 } __packed; 314 315 enum { 316 OCRDMA_AE_MCQE_QPVALID = Bit(31), 317 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF, 318 319 OCRDMA_AE_MCQE_CQVALID = Bit(31), 320 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF, 321 OCRDMA_AE_MCQE_VALID = Bit(31), 322 OCRDMA_AE_MCQE_AE = Bit(30), 323 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16, 324 OCRDMA_AE_MCQE_EVENT_TYPE_MASK = 325 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT, 326 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8, 327 OCRDMA_AE_MCQE_EVENT_CODE_MASK = 328 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT 329 }; 330 struct ocrdma_ae_mcqe { 331 u32 qpvalid_qpid; 332 u32 cqvalid_cqid; 333 u32 evt_tag; 334 u32 valid_ae_event; 335 } __packed; 336 337 enum { 338 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16, 339 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF << 340 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT, 341 342 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8, 343 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF << 344 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT, 345 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16, 346 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF << 347 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT, 348 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30, 349 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30), 350 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31, 351 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31) 352 }; 353 354 struct ocrdma_ae_mpa_mcqe { 355 u32 req_id; 356 u32 w1; 357 u32 w2; 358 u32 valid_ae_event; 359 } __packed; 360 361 enum { 362 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0, 363 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF, 364 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16, 365 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF << 366 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT, 367 368 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8, 369 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF << 370 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT, 371 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16, 372 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF << 373 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT, 374 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30, 375 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30), 376 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31, 377 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31) 378 }; 379 380 struct ocrdma_ae_qp_mcqe { 381 u32 qp_id_state; 382 u32 w1; 383 u32 w2; 384 u32 valid_ae_event; 385 } __packed; 386 387 #define OCRDMA_ASYNC_EVE_CODE 0x14 388 389 enum OCRDMA_ASYNC_EVENT_TYPE { 390 OCRDMA_CQ_ERROR = 0x00, 391 OCRDMA_CQ_OVERRUN_ERROR = 0x01, 392 OCRDMA_CQ_QPCAT_ERROR = 0x02, 393 OCRDMA_QP_ACCESS_ERROR = 0x03, 394 OCRDMA_QP_COMM_EST_EVENT = 0x04, 395 OCRDMA_SQ_DRAINED_EVENT = 0x05, 396 OCRDMA_DEVICE_FATAL_EVENT = 0x08, 397 OCRDMA_SRQCAT_ERROR = 0x0E, 398 OCRDMA_SRQ_LIMIT_EVENT = 0x0F, 399 OCRDMA_QP_LAST_WQE_EVENT = 0x10 400 }; 401 402 /* mailbox command request and responses */ 403 enum { 404 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2, 405 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2), 406 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3, 407 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3), 408 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8, 409 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF << 410 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT, 411 412 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16, 413 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF << 414 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT, 415 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8, 416 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF << 417 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT, 418 419 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0, 420 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF, 421 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16, 422 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF << 423 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT, 424 425 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0, 426 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF, 427 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16, 428 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF << 429 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT, 430 431 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24, 432 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF << 433 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET, 434 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16, 435 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF << 436 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET, 437 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0, 438 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF << 439 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET, 440 441 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16, 442 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF << 443 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET, 444 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0, 445 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF << 446 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET, 447 448 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16, 449 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF << 450 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET, 451 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0, 452 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF << 453 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET, 454 455 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0, 456 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF << 457 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET, 458 459 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16, 460 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF << 461 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET, 462 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0, 463 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF << 464 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET, 465 466 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16, 467 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF << 468 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET, 469 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0, 470 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF << 471 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET, 472 473 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16, 474 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF << 475 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET, 476 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0, 477 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF << 478 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET, 479 }; 480 481 struct ocrdma_mbx_query_config { 482 struct ocrdma_mqe_hdr hdr; 483 struct ocrdma_mbx_rsp rsp; 484 u32 qp_srq_cq_ird_ord; 485 u32 max_pd_ca_ack_delay; 486 u32 max_write_send_sge; 487 u32 max_ird_ord_per_qp; 488 u32 max_shared_ird_ord; 489 u32 max_mr; 490 u64 max_mr_size; 491 u32 max_num_mr_pbl; 492 u32 max_mw; 493 u32 max_fmr; 494 u32 max_pages_per_frmr; 495 u32 max_mcast_group; 496 u32 max_mcast_qp_attach; 497 u32 max_total_mcast_qp_attach; 498 u32 wqe_rqe_stride_max_dpp_cqs; 499 u32 max_srq_rpir_qps; 500 u32 max_dpp_pds_credits; 501 u32 max_dpp_credits_pds_per_pd; 502 u32 max_wqes_rqes_per_q; 503 u32 max_cq_cqes_per_cq; 504 u32 max_srq_rqe_sge; 505 } __packed; 506 507 struct ocrdma_fw_ver_rsp { 508 struct ocrdma_mqe_hdr hdr; 509 struct ocrdma_mbx_rsp rsp; 510 511 u8 running_ver[32]; 512 } __packed; 513 514 struct ocrdma_fw_conf_rsp { 515 struct ocrdma_mqe_hdr hdr; 516 struct ocrdma_mbx_rsp rsp; 517 518 u32 config_num; 519 u32 asic_revision; 520 u32 phy_port; 521 u32 fn_mode; 522 struct { 523 u32 mode; 524 u32 nic_wqid_base; 525 u32 nic_wq_tot; 526 u32 prot_wqid_base; 527 u32 prot_wq_tot; 528 u32 prot_rqid_base; 529 u32 prot_rqid_tot; 530 u32 rsvd[6]; 531 } ulp[2]; 532 u32 fn_capabilities; 533 u32 rsvd1; 534 u32 rsvd2; 535 u32 base_eqid; 536 u32 max_eq; 537 538 } __packed; 539 540 enum { 541 OCRDMA_FN_MODE_RDMA = 0x4 542 }; 543 544 enum { 545 OCRDMA_CREATE_CQ_VER2 = 2, 546 547 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF, 548 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16, 549 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF, 550 551 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12, 552 OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12), 553 OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14), 554 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15), 555 556 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF, 557 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF 558 }; 559 560 enum { 561 OCRDMA_CREATE_CQ_VER0 = 0, 562 OCRDMA_CREATE_CQ_DPP = 1, 563 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24, 564 OCRDMA_CREATE_CQ_EQID_SHIFT = 22, 565 566 OCRDMA_CREATE_CQ_CNT_SHIFT = 27, 567 OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29), 568 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31), 569 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID | 570 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE | 571 OCRDMA_CREATE_CQ_FLAGS_NODELAY 572 }; 573 574 struct ocrdma_create_cq_cmd { 575 struct ocrdma_mbx_hdr req; 576 u32 pgsz_pgcnt; 577 u32 ev_cnt_flags; 578 u32 eqn; 579 u32 cqe_count; 580 u32 rsvd6; 581 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES]; 582 }; 583 584 struct ocrdma_create_cq { 585 struct ocrdma_mqe_hdr hdr; 586 struct ocrdma_create_cq_cmd cmd; 587 } __packed; 588 589 enum { 590 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF 591 }; 592 593 struct ocrdma_create_cq_cmd_rsp { 594 struct ocrdma_mbx_rsp rsp; 595 u32 cq_id; 596 } __packed; 597 598 struct ocrdma_create_cq_rsp { 599 struct ocrdma_mqe_hdr hdr; 600 struct ocrdma_create_cq_cmd_rsp rsp; 601 } __packed; 602 603 enum { 604 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22, 605 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16, 606 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16, 607 OCRDMA_CREATE_MQ_VALID = Bit(31), 608 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0) 609 }; 610 611 struct ocrdma_create_mq_req { 612 struct ocrdma_mbx_hdr req; 613 u32 cqid_pages; 614 u32 async_event_bitmap; 615 u32 async_cqid_ringsize; 616 u32 valid; 617 u32 async_cqid_valid; 618 u32 rsvd; 619 struct ocrdma_pa pa[8]; 620 } __packed; 621 622 struct ocrdma_create_mq_rsp { 623 struct ocrdma_mbx_rsp rsp; 624 u32 id; 625 } __packed; 626 627 enum { 628 OCRDMA_DESTROY_CQ_QID_SHIFT = 0, 629 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF, 630 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16, 631 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF << 632 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT 633 }; 634 635 struct ocrdma_destroy_cq { 636 struct ocrdma_mqe_hdr hdr; 637 struct ocrdma_mbx_hdr req; 638 639 u32 bypass_flush_qid; 640 } __packed; 641 642 struct ocrdma_destroy_cq_rsp { 643 struct ocrdma_mqe_hdr hdr; 644 struct ocrdma_mbx_rsp rsp; 645 } __packed; 646 647 enum { 648 OCRDMA_QPT_GSI = 1, 649 OCRDMA_QPT_RC = 2, 650 OCRDMA_QPT_UD = 4, 651 }; 652 653 enum { 654 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0, 655 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF, 656 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16, 657 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19, 658 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29, 659 OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29), 660 661 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0, 662 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF, 663 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16, 664 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF << 665 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT, 666 667 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0, 668 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF, 669 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16, 670 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF << 671 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT, 672 673 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0, 674 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0), 675 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1, 676 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1), 677 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2, 678 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2), 679 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3, 680 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3), 681 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4, 682 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4), 683 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5, 684 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5), 685 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6, 686 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6), 687 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7, 688 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7), 689 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8, 690 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8), 691 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16, 692 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF << 693 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT, 694 695 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0, 696 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF, 697 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16, 698 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF << 699 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT, 700 701 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0, 702 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF, 703 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16, 704 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF << 705 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT, 706 707 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0, 708 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF, 709 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16, 710 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF << 711 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT, 712 713 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0, 714 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF, 715 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16, 716 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF << 717 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT, 718 719 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0, 720 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF, 721 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16, 722 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF << 723 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT 724 }; 725 726 enum { 727 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16, 728 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1 729 }; 730 731 #define MAX_OCRDMA_IRD_PAGES 4 732 733 enum ocrdma_qp_flags { 734 OCRDMA_QP_MW_BIND = 1, 735 OCRDMA_QP_LKEY0 = (1 << 1), 736 OCRDMA_QP_FAST_REG = (1 << 2), 737 OCRDMA_QP_INB_RD = (1 << 6), 738 OCRDMA_QP_INB_WR = (1 << 7), 739 }; 740 741 enum ocrdma_qp_state { 742 OCRDMA_QPS_RST = 0, 743 OCRDMA_QPS_INIT = 1, 744 OCRDMA_QPS_RTR = 2, 745 OCRDMA_QPS_RTS = 3, 746 OCRDMA_QPS_SQE = 4, 747 OCRDMA_QPS_SQ_DRAINING = 5, 748 OCRDMA_QPS_ERR = 6, 749 OCRDMA_QPS_SQD = 7 750 }; 751 752 struct ocrdma_create_qp_req { 753 struct ocrdma_mqe_hdr hdr; 754 struct ocrdma_mbx_hdr req; 755 756 u32 type_pgsz_pdn; 757 u32 max_wqe_rqe; 758 u32 max_sge_send_write; 759 u32 max_sge_recv_flags; 760 u32 max_ord_ird; 761 u32 num_wq_rq_pages; 762 u32 wqe_rqe_size; 763 u32 wq_rq_cqid; 764 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES]; 765 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES]; 766 u32 dpp_credits_cqid; 767 u32 rpir_lkey; 768 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES]; 769 } __packed; 770 771 enum { 772 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0, 773 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF, 774 775 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0, 776 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF, 777 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16, 778 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF << 779 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT, 780 781 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0, 782 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF, 783 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16, 784 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF << 785 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT, 786 787 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16, 788 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF << 789 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT, 790 791 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0, 792 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF, 793 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16, 794 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF << 795 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT, 796 797 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0, 798 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF, 799 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16, 800 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF << 801 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT, 802 803 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0), 804 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1, 805 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF << 806 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT, 807 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16, 808 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF << 809 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT, 810 }; 811 812 struct ocrdma_create_qp_rsp { 813 struct ocrdma_mqe_hdr hdr; 814 struct ocrdma_mbx_rsp rsp; 815 816 u32 qp_id; 817 u32 max_wqe_rqe; 818 u32 max_sge_send_write; 819 u32 max_sge_recv; 820 u32 max_ord_ird; 821 u32 sq_rq_id; 822 u32 dpp_response; 823 } __packed; 824 825 struct ocrdma_destroy_qp { 826 struct ocrdma_mqe_hdr hdr; 827 struct ocrdma_mbx_hdr req; 828 u32 qp_id; 829 } __packed; 830 831 struct ocrdma_destroy_qp_rsp { 832 struct ocrdma_mqe_hdr hdr; 833 struct ocrdma_mbx_rsp rsp; 834 } __packed; 835 836 enum { 837 OCRDMA_MODIFY_QP_ID_SHIFT = 0, 838 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF, 839 840 OCRDMA_QP_PARA_QPS_VALID = Bit(0), 841 OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1), 842 OCRDMA_QP_PARA_PKEY_VALID = Bit(2), 843 OCRDMA_QP_PARA_QKEY_VALID = Bit(3), 844 OCRDMA_QP_PARA_PMTU_VALID = Bit(4), 845 OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5), 846 OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6), 847 OCRDMA_QP_PARA_RRC_VALID = Bit(7), 848 OCRDMA_QP_PARA_RQPSN_VALID = Bit(8), 849 OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9), 850 OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10), 851 OCRDMA_QP_PARA_RNT_VALID = Bit(11), 852 OCRDMA_QP_PARA_SQPSN_VALID = Bit(12), 853 OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13), 854 OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14), 855 OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15), 856 OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16), 857 OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17), 858 OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18), 859 OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19), 860 OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20), 861 OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21), 862 OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22), 863 OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23), 864 OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24), 865 OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25), 866 OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26), 867 868 OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0), 869 OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1), 870 OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2), 871 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3) 872 }; 873 874 enum { 875 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0, 876 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF, 877 878 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0, 879 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF, 880 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16, 881 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF << 882 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT, 883 884 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0, 885 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF, 886 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16, 887 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF << 888 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT, 889 890 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0), 891 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1), 892 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2), 893 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3), 894 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4), 895 OCRDMA_QP_PARAMS_STATE_SHIFT = 5, 896 OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7), 897 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8), 898 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9), 899 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16, 900 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF << 901 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT, 902 903 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0, 904 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF, 905 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16, 906 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF << 907 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT, 908 909 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0, 910 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF, 911 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16, 912 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF << 913 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT, 914 915 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0, 916 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF, 917 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24, 918 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF << 919 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT, 920 921 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0, 922 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF, 923 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24, 924 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF << 925 OCRDMA_QP_PARAMS_TCLASS_SHIFT, 926 927 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0, 928 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF, 929 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24, 930 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 << 931 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT, 932 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27, 933 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F << 934 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT, 935 936 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0, 937 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF, 938 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18, 939 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF << 940 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT, 941 942 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0, 943 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF, 944 OCRDMA_QP_PARAMS_SL_SHIFT = 20, 945 OCRDMA_QP_PARAMS_SL_MASK = 0xF << 946 OCRDMA_QP_PARAMS_SL_SHIFT, 947 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24, 948 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 << 949 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT, 950 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27, 951 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F << 952 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT, 953 954 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0, 955 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF, 956 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16, 957 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF << 958 OCRDMA_QP_PARAMS_VLAN_SHIFT 959 }; 960 961 struct ocrdma_qp_params { 962 u32 id; 963 u32 max_wqe_rqe; 964 u32 max_sge_send_write; 965 u32 max_sge_recv_flags; 966 u32 max_ord_ird; 967 u32 wq_rq_cqid; 968 u32 hop_lmt_rq_psn; 969 u32 tclass_sq_psn; 970 u32 ack_to_rnr_rtc_dest_qpn; 971 u32 path_mtu_pkey_indx; 972 u32 rnt_rc_sl_fl; 973 u8 sgid[16]; 974 u8 dgid[16]; 975 u32 dmac_b0_to_b3; 976 u32 vlan_dmac_b4_to_b5; 977 u32 qkey; 978 } __packed; 979 980 981 struct ocrdma_modify_qp { 982 struct ocrdma_mqe_hdr hdr; 983 struct ocrdma_mbx_hdr req; 984 985 struct ocrdma_qp_params params; 986 u32 flags; 987 u32 rdma_flags; 988 u32 num_outstanding_atomic_rd; 989 } __packed; 990 991 enum { 992 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0, 993 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF, 994 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16, 995 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF << 996 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT, 997 998 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0, 999 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF, 1000 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16, 1001 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF << 1002 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT 1003 }; 1004 struct ocrdma_modify_qp_rsp { 1005 struct ocrdma_mqe_hdr hdr; 1006 struct ocrdma_mbx_rsp rsp; 1007 1008 u32 max_wqe_rqe; 1009 u32 max_ord_ird; 1010 } __packed; 1011 1012 struct ocrdma_query_qp { 1013 struct ocrdma_mqe_hdr hdr; 1014 struct ocrdma_mbx_hdr req; 1015 1016 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0 1017 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF 1018 u32 qp_id; 1019 } __packed; 1020 1021 struct ocrdma_query_qp_rsp { 1022 struct ocrdma_mqe_hdr hdr; 1023 struct ocrdma_mbx_rsp rsp; 1024 struct ocrdma_qp_params params; 1025 } __packed; 1026 1027 enum { 1028 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0, 1029 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF, 1030 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16, 1031 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 << 1032 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT, 1033 1034 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0, 1035 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16, 1036 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF << 1037 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT, 1038 1039 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0, 1040 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF, 1041 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16, 1042 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF << 1043 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT 1044 }; 1045 1046 struct ocrdma_create_srq { 1047 struct ocrdma_mqe_hdr hdr; 1048 struct ocrdma_mbx_hdr req; 1049 1050 u32 pgsz_pdid; 1051 u32 max_sge_rqe; 1052 u32 pages_rqe_sz; 1053 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES]; 1054 } __packed; 1055 1056 enum { 1057 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0, 1058 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF, 1059 1060 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0, 1061 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF, 1062 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16, 1063 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF << 1064 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT 1065 }; 1066 1067 struct ocrdma_create_srq_rsp { 1068 struct ocrdma_mqe_hdr hdr; 1069 struct ocrdma_mbx_rsp rsp; 1070 1071 u32 id; 1072 u32 max_sge_rqe_allocated; 1073 } __packed; 1074 1075 enum { 1076 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0, 1077 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF, 1078 1079 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0, 1080 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF, 1081 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16, 1082 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF << 1083 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT 1084 }; 1085 1086 struct ocrdma_modify_srq { 1087 struct ocrdma_mqe_hdr hdr; 1088 struct ocrdma_mbx_rsp rep; 1089 1090 u32 id; 1091 u32 limit_max_rqe; 1092 } __packed; 1093 1094 enum { 1095 OCRDMA_QUERY_SRQ_ID_SHIFT = 0, 1096 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF 1097 }; 1098 1099 struct ocrdma_query_srq { 1100 struct ocrdma_mqe_hdr hdr; 1101 struct ocrdma_mbx_rsp req; 1102 1103 u32 id; 1104 } __packed; 1105 1106 enum { 1107 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0, 1108 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF, 1109 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16, 1110 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF << 1111 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT, 1112 1113 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0, 1114 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF, 1115 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16, 1116 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF << 1117 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT 1118 }; 1119 1120 struct ocrdma_query_srq_rsp { 1121 struct ocrdma_mqe_hdr hdr; 1122 struct ocrdma_mbx_rsp req; 1123 1124 u32 max_rqe_pdid; 1125 u32 srq_lmt_max_sge; 1126 } __packed; 1127 1128 enum { 1129 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0, 1130 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF 1131 }; 1132 1133 struct ocrdma_destroy_srq { 1134 struct ocrdma_mqe_hdr hdr; 1135 struct ocrdma_mbx_rsp req; 1136 1137 u32 id; 1138 } __packed; 1139 1140 enum { 1141 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16), 1142 OCRDMA_PD_MAX_DPP_ENABLED_QP = 8, 1143 OCRDMA_DPP_PAGE_SIZE = 4096 1144 }; 1145 1146 struct ocrdma_alloc_pd { 1147 struct ocrdma_mqe_hdr hdr; 1148 struct ocrdma_mbx_hdr req; 1149 u32 enable_dpp_rsvd; 1150 } __packed; 1151 1152 enum { 1153 OCRDMA_ALLOC_PD_RSP_DPP = Bit(16), 1154 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20, 1155 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF, 1156 }; 1157 1158 struct ocrdma_alloc_pd_rsp { 1159 struct ocrdma_mqe_hdr hdr; 1160 struct ocrdma_mbx_rsp rsp; 1161 u32 dpp_page_pdid; 1162 } __packed; 1163 1164 struct ocrdma_dealloc_pd { 1165 struct ocrdma_mqe_hdr hdr; 1166 struct ocrdma_mbx_hdr req; 1167 u32 id; 1168 } __packed; 1169 1170 struct ocrdma_dealloc_pd_rsp { 1171 struct ocrdma_mqe_hdr hdr; 1172 struct ocrdma_mbx_rsp rsp; 1173 } __packed; 1174 1175 enum { 1176 OCRDMA_ADDR_CHECK_ENABLE = 1, 1177 OCRDMA_ADDR_CHECK_DISABLE = 0 1178 }; 1179 1180 enum { 1181 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0, 1182 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF, 1183 1184 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0, 1185 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0), 1186 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1, 1187 OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1), 1188 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2, 1189 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2), 1190 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3, 1191 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3), 1192 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4, 1193 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4), 1194 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5, 1195 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5), 1196 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6), 1197 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6, 1198 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16, 1199 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF << 1200 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT 1201 }; 1202 1203 struct ocrdma_alloc_lkey { 1204 struct ocrdma_mqe_hdr hdr; 1205 struct ocrdma_mbx_hdr req; 1206 1207 u32 pdid; 1208 u32 pbl_sz_flags; 1209 } __packed; 1210 1211 struct ocrdma_alloc_lkey_rsp { 1212 struct ocrdma_mqe_hdr hdr; 1213 struct ocrdma_mbx_rsp rsp; 1214 1215 u32 lrkey; 1216 u32 num_pbl_rsvd; 1217 } __packed; 1218 1219 struct ocrdma_dealloc_lkey { 1220 struct ocrdma_mqe_hdr hdr; 1221 struct ocrdma_mbx_hdr req; 1222 1223 u32 lkey; 1224 u32 rsvd_frmr; 1225 } __packed; 1226 1227 struct ocrdma_dealloc_lkey_rsp { 1228 struct ocrdma_mqe_hdr hdr; 1229 struct ocrdma_mbx_rsp rsp; 1230 } __packed; 1231 1232 #define MAX_OCRDMA_NSMR_PBL (u32)22 1233 #define MAX_OCRDMA_PBL_SIZE 65536 1234 #define MAX_OCRDMA_PBL_PER_LKEY 32767 1235 1236 enum { 1237 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0, 1238 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF, 1239 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24, 1240 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF << 1241 OCRDMA_REG_NSMR_LRKEY_SHIFT, 1242 1243 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0, 1244 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF, 1245 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16, 1246 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF << 1247 OCRDMA_REG_NSMR_NUM_PBL_SHIFT, 1248 1249 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0, 1250 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF, 1251 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16, 1252 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF << 1253 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT, 1254 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24, 1255 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24), 1256 OCRDMA_REG_NSMR_ZB_SHIFT = 25, 1257 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25), 1258 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26, 1259 OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26), 1260 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27, 1261 OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27), 1262 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28, 1263 OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28), 1264 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29, 1265 OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29), 1266 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30, 1267 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30), 1268 OCRDMA_REG_NSMR_LAST_SHIFT = 31, 1269 OCRDMA_REG_NSMR_LAST_MASK = Bit(31) 1270 }; 1271 1272 struct ocrdma_reg_nsmr { 1273 struct ocrdma_mqe_hdr hdr; 1274 struct ocrdma_mbx_hdr cmd; 1275 1276 u32 lrkey_key_index; 1277 u32 num_pbl_pdid; 1278 u32 flags_hpage_pbe_sz; 1279 u32 totlen_low; 1280 u32 totlen_high; 1281 u32 fbo_low; 1282 u32 fbo_high; 1283 u32 va_loaddr; 1284 u32 va_hiaddr; 1285 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1286 } __packed; 1287 1288 enum { 1289 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0, 1290 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF, 1291 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16, 1292 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF << 1293 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT, 1294 1295 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31, 1296 OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31) 1297 }; 1298 1299 struct ocrdma_reg_nsmr_cont { 1300 struct ocrdma_mqe_hdr hdr; 1301 struct ocrdma_mbx_hdr cmd; 1302 1303 u32 lrkey; 1304 u32 num_pbl_offset; 1305 u32 last; 1306 1307 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1308 } __packed; 1309 1310 struct ocrdma_pbe { 1311 u32 pa_hi; 1312 u32 pa_lo; 1313 } __packed; 1314 1315 enum { 1316 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16, 1317 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000 1318 }; 1319 struct ocrdma_reg_nsmr_rsp { 1320 struct ocrdma_mqe_hdr hdr; 1321 struct ocrdma_mbx_rsp rsp; 1322 1323 u32 lrkey; 1324 u32 num_pbl; 1325 } __packed; 1326 1327 enum { 1328 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0, 1329 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF, 1330 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24, 1331 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF << 1332 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT, 1333 1334 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16, 1335 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF << 1336 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT 1337 }; 1338 1339 struct ocrdma_reg_nsmr_cont_rsp { 1340 struct ocrdma_mqe_hdr hdr; 1341 struct ocrdma_mbx_rsp rsp; 1342 1343 u32 lrkey_key_index; 1344 u32 num_pbl; 1345 } __packed; 1346 1347 enum { 1348 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0, 1349 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF 1350 }; 1351 1352 struct ocrdma_alloc_mw { 1353 struct ocrdma_mqe_hdr hdr; 1354 struct ocrdma_mbx_hdr req; 1355 1356 u32 pdid; 1357 } __packed; 1358 1359 enum { 1360 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0, 1361 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF 1362 }; 1363 1364 struct ocrdma_alloc_mw_rsp { 1365 struct ocrdma_mqe_hdr hdr; 1366 struct ocrdma_mbx_rsp rsp; 1367 1368 u32 lrkey_index; 1369 } __packed; 1370 1371 struct ocrdma_attach_mcast { 1372 struct ocrdma_mqe_hdr hdr; 1373 struct ocrdma_mbx_hdr req; 1374 u32 qp_id; 1375 u8 mgid[16]; 1376 u32 mac_b0_to_b3; 1377 u32 vlan_mac_b4_to_b5; 1378 } __packed; 1379 1380 struct ocrdma_attach_mcast_rsp { 1381 struct ocrdma_mqe_hdr hdr; 1382 struct ocrdma_mbx_rsp rsp; 1383 } __packed; 1384 1385 struct ocrdma_detach_mcast { 1386 struct ocrdma_mqe_hdr hdr; 1387 struct ocrdma_mbx_hdr req; 1388 u32 qp_id; 1389 u8 mgid[16]; 1390 u32 mac_b0_to_b3; 1391 u32 vlan_mac_b4_to_b5; 1392 } __packed; 1393 1394 struct ocrdma_detach_mcast_rsp { 1395 struct ocrdma_mqe_hdr hdr; 1396 struct ocrdma_mbx_rsp rsp; 1397 } __packed; 1398 1399 enum { 1400 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19, 1401 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF << 1402 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT, 1403 1404 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16, 1405 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 << 1406 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT, 1407 1408 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23, 1409 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF << 1410 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT, 1411 }; 1412 1413 #define OCRDMA_AH_TBL_PAGES 8 1414 1415 struct ocrdma_create_ah_tbl { 1416 struct ocrdma_mqe_hdr hdr; 1417 struct ocrdma_mbx_hdr req; 1418 1419 u32 ah_conf; 1420 struct ocrdma_pa tbl_addr[8]; 1421 } __packed; 1422 1423 struct ocrdma_create_ah_tbl_rsp { 1424 struct ocrdma_mqe_hdr hdr; 1425 struct ocrdma_mbx_rsp rsp; 1426 u32 ahid; 1427 } __packed; 1428 1429 struct ocrdma_delete_ah_tbl { 1430 struct ocrdma_mqe_hdr hdr; 1431 struct ocrdma_mbx_hdr req; 1432 u32 ahid; 1433 } __packed; 1434 1435 struct ocrdma_delete_ah_tbl_rsp { 1436 struct ocrdma_mqe_hdr hdr; 1437 struct ocrdma_mbx_rsp rsp; 1438 } __packed; 1439 1440 enum { 1441 OCRDMA_EQE_VALID_SHIFT = 0, 1442 OCRDMA_EQE_VALID_MASK = Bit(0), 1443 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE, 1444 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16, 1445 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF << 1446 OCRDMA_EQE_RESOURCE_ID_SHIFT, 1447 }; 1448 1449 struct ocrdma_eqe { 1450 u32 id_valid; 1451 } __packed; 1452 1453 enum OCRDMA_CQE_STATUS { 1454 OCRDMA_CQE_SUCCESS = 0, 1455 OCRDMA_CQE_LOC_LEN_ERR, 1456 OCRDMA_CQE_LOC_QP_OP_ERR, 1457 OCRDMA_CQE_LOC_EEC_OP_ERR, 1458 OCRDMA_CQE_LOC_PROT_ERR, 1459 OCRDMA_CQE_WR_FLUSH_ERR, 1460 OCRDMA_CQE_MW_BIND_ERR, 1461 OCRDMA_CQE_BAD_RESP_ERR, 1462 OCRDMA_CQE_LOC_ACCESS_ERR, 1463 OCRDMA_CQE_REM_INV_REQ_ERR, 1464 OCRDMA_CQE_REM_ACCESS_ERR, 1465 OCRDMA_CQE_REM_OP_ERR, 1466 OCRDMA_CQE_RETRY_EXC_ERR, 1467 OCRDMA_CQE_RNR_RETRY_EXC_ERR, 1468 OCRDMA_CQE_LOC_RDD_VIOL_ERR, 1469 OCRDMA_CQE_REM_INV_RD_REQ_ERR, 1470 OCRDMA_CQE_REM_ABORT_ERR, 1471 OCRDMA_CQE_INV_EECN_ERR, 1472 OCRDMA_CQE_INV_EEC_STATE_ERR, 1473 OCRDMA_CQE_FATAL_ERR, 1474 OCRDMA_CQE_RESP_TIMEOUT_ERR, 1475 OCRDMA_CQE_GENERAL_ERR 1476 }; 1477 1478 enum { 1479 /* w0 */ 1480 OCRDMA_CQE_WQEIDX_SHIFT = 0, 1481 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF, 1482 1483 /* w1 */ 1484 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16, 1485 OCRDMA_CQE_PKEY_SHIFT = 0, 1486 OCRDMA_CQE_PKEY_MASK = 0xFFFF, 1487 1488 /* w2 */ 1489 OCRDMA_CQE_QPN_SHIFT = 0, 1490 OCRDMA_CQE_QPN_MASK = 0x0000FFFF, 1491 1492 OCRDMA_CQE_BUFTAG_SHIFT = 16, 1493 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT, 1494 1495 /* w3 */ 1496 OCRDMA_CQE_UD_STATUS_SHIFT = 24, 1497 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT, 1498 OCRDMA_CQE_STATUS_SHIFT = 16, 1499 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT, 1500 OCRDMA_CQE_VALID = Bit(31), 1501 OCRDMA_CQE_INVALIDATE = Bit(30), 1502 OCRDMA_CQE_QTYPE = Bit(29), 1503 OCRDMA_CQE_IMM = Bit(28), 1504 OCRDMA_CQE_WRITE_IMM = Bit(27), 1505 OCRDMA_CQE_QTYPE_SQ = 0, 1506 OCRDMA_CQE_QTYPE_RQ = 1, 1507 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF 1508 }; 1509 1510 struct ocrdma_cqe { 1511 union { 1512 /* w0 to w2 */ 1513 struct { 1514 u32 wqeidx; 1515 u32 bytes_xfered; 1516 u32 qpn; 1517 } wq; 1518 struct { 1519 u32 lkey_immdt; 1520 u32 rxlen; 1521 u32 buftag_qpn; 1522 } rq; 1523 struct { 1524 u32 lkey_immdt; 1525 u32 rxlen_pkey; 1526 u32 buftag_qpn; 1527 } ud; 1528 struct { 1529 u32 word_0; 1530 u32 word_1; 1531 u32 qpn; 1532 } cmn; 1533 }; 1534 u32 flags_status_srcqpn; /* w3 */ 1535 } __packed; 1536 1537 #define is_cqe_valid(cq, cqe) \ 1538 (((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID)\ 1539 == cq->phase) ? 1 : 0) 1540 #define is_cqe_for_sq(cqe) \ 1541 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 0 : 1) 1542 #define is_cqe_for_rq(cqe) \ 1543 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 1 : 0) 1544 #define is_cqe_invalidated(cqe) \ 1545 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_INVALIDATE) ? \ 1546 1 : 0) 1547 #define is_cqe_imm(cqe) \ 1548 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_IMM) ? 1 : 0) 1549 #define is_cqe_wr_imm(cqe) \ 1550 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_WRITE_IMM) ? 1 : 0) 1551 1552 struct ocrdma_sge { 1553 u32 addr_hi; 1554 u32 addr_lo; 1555 u32 lrkey; 1556 u32 len; 1557 } __packed; 1558 1559 enum { 1560 OCRDMA_FLAG_SIG = 0x1, 1561 OCRDMA_FLAG_INV = 0x2, 1562 OCRDMA_FLAG_FENCE_L = 0x4, 1563 OCRDMA_FLAG_FENCE_R = 0x8, 1564 OCRDMA_FLAG_SOLICIT = 0x10, 1565 OCRDMA_FLAG_IMM = 0x20, 1566 1567 /* Stag flags */ 1568 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1, 1569 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2, 1570 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4, 1571 OCRDMA_LKEY_FLAG_VATO = 0x8, 1572 }; 1573 1574 enum OCRDMA_WQE_OPCODE { 1575 OCRDMA_WRITE = 0x06, 1576 OCRDMA_READ = 0x0C, 1577 OCRDMA_RESV0 = 0x02, 1578 OCRDMA_SEND = 0x00, 1579 OCRDMA_CMP_SWP = 0x14, 1580 OCRDMA_BIND_MW = 0x10, 1581 OCRDMA_RESV1 = 0x0A, 1582 OCRDMA_LKEY_INV = 0x15, 1583 OCRDMA_FETCH_ADD = 0x13, 1584 OCRDMA_POST_RQ = 0x12 1585 }; 1586 1587 enum { 1588 OCRDMA_TYPE_INLINE = 0x0, 1589 OCRDMA_TYPE_LKEY = 0x1, 1590 }; 1591 1592 enum { 1593 OCRDMA_WQE_OPCODE_SHIFT = 0, 1594 OCRDMA_WQE_OPCODE_MASK = 0x0000001F, 1595 OCRDMA_WQE_FLAGS_SHIFT = 5, 1596 OCRDMA_WQE_TYPE_SHIFT = 16, 1597 OCRDMA_WQE_TYPE_MASK = 0x00030000, 1598 OCRDMA_WQE_SIZE_SHIFT = 18, 1599 OCRDMA_WQE_SIZE_MASK = 0xFF, 1600 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25, 1601 1602 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0, 1603 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF 1604 }; 1605 1606 /* header WQE for all the SQ and RQ operations */ 1607 struct ocrdma_hdr_wqe { 1608 u32 cw; 1609 union { 1610 u32 rsvd_tag; 1611 u32 rsvd_lkey_flags; 1612 }; 1613 union { 1614 u32 immdt; 1615 u32 lkey; 1616 }; 1617 u32 total_len; 1618 } __packed; 1619 1620 struct ocrdma_ewqe_ud_hdr { 1621 u32 rsvd_dest_qpn; 1622 u32 qkey; 1623 u32 rsvd_ahid; 1624 u32 rsvd; 1625 } __packed; 1626 1627 struct ocrdma_eth_basic { 1628 u8 dmac[6]; 1629 u8 smac[6]; 1630 __be16 eth_type; 1631 } __packed; 1632 1633 struct ocrdma_eth_vlan { 1634 u8 dmac[6]; 1635 u8 smac[6]; 1636 __be16 eth_type; 1637 __be16 vlan_tag; 1638 #define OCRDMA_ROCE_ETH_TYPE 0x8915 1639 __be16 roce_eth_type; 1640 } __packed; 1641 1642 struct ocrdma_grh { 1643 __be32 tclass_flow; 1644 __be32 pdid_hoplimit; 1645 u8 sgid[16]; 1646 u8 dgid[16]; 1647 u16 rsvd; 1648 } __packed; 1649 1650 #define OCRDMA_AV_VALID Bit(0) 1651 #define OCRDMA_AV_VLAN_VALID Bit(1) 1652 1653 struct ocrdma_av { 1654 struct ocrdma_eth_vlan eth_hdr; 1655 struct ocrdma_grh grh; 1656 u32 valid; 1657 } __packed; 1658 1659 #endif /* __OCRDMA_SLI_H__ */ 1660