1 /******************************************************************* 2 * This file is part of the Emulex RoCE Device Driver for * 3 * RoCE (RDMA over Converged Ethernet) adapters. * 4 * Copyright (C) 2008-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 * 20 * Contact Information: 21 * linux-drivers@emulex.com 22 * 23 * Emulex 24 * 3333 Susan Street 25 * Costa Mesa, CA 92626 26 *******************************************************************/ 27 28 #ifndef __OCRDMA_SLI_H__ 29 #define __OCRDMA_SLI_H__ 30 31 #define Bit(_b) (1 << (_b)) 32 33 #define OCRDMA_GEN1_FAMILY 0xB 34 #define OCRDMA_GEN2_FAMILY 0x2 35 36 #define OCRDMA_SUBSYS_ROCE 10 37 enum { 38 OCRDMA_CMD_QUERY_CONFIG = 1, 39 OCRDMA_CMD_ALLOC_PD, 40 OCRDMA_CMD_DEALLOC_PD, 41 42 OCRDMA_CMD_CREATE_AH_TBL, 43 OCRDMA_CMD_DELETE_AH_TBL, 44 45 OCRDMA_CMD_CREATE_QP, 46 OCRDMA_CMD_QUERY_QP, 47 OCRDMA_CMD_MODIFY_QP, 48 OCRDMA_CMD_DELETE_QP, 49 50 OCRDMA_CMD_RSVD1, 51 OCRDMA_CMD_ALLOC_LKEY, 52 OCRDMA_CMD_DEALLOC_LKEY, 53 OCRDMA_CMD_REGISTER_NSMR, 54 OCRDMA_CMD_REREGISTER_NSMR, 55 OCRDMA_CMD_REGISTER_NSMR_CONT, 56 OCRDMA_CMD_QUERY_NSMR, 57 OCRDMA_CMD_ALLOC_MW, 58 OCRDMA_CMD_QUERY_MW, 59 60 OCRDMA_CMD_CREATE_SRQ, 61 OCRDMA_CMD_QUERY_SRQ, 62 OCRDMA_CMD_MODIFY_SRQ, 63 OCRDMA_CMD_DELETE_SRQ, 64 65 OCRDMA_CMD_ATTACH_MCAST, 66 OCRDMA_CMD_DETACH_MCAST, 67 68 OCRDMA_CMD_MAX 69 }; 70 71 #define OCRDMA_SUBSYS_COMMON 1 72 enum { 73 OCRDMA_CMD_CREATE_CQ = 12, 74 OCRDMA_CMD_CREATE_EQ = 13, 75 OCRDMA_CMD_CREATE_MQ = 21, 76 OCRDMA_CMD_GET_FW_VER = 35, 77 OCRDMA_CMD_DELETE_MQ = 53, 78 OCRDMA_CMD_DELETE_CQ = 54, 79 OCRDMA_CMD_DELETE_EQ = 55, 80 OCRDMA_CMD_GET_FW_CONFIG = 58, 81 OCRDMA_CMD_CREATE_MQ_EXT = 90 82 }; 83 84 enum { 85 QTYPE_EQ = 1, 86 QTYPE_CQ = 2, 87 QTYPE_MCCQ = 3 88 }; 89 90 #define OCRDMA_MAX_SGID (8) 91 92 #define OCRDMA_MAX_QP 2048 93 #define OCRDMA_MAX_CQ 2048 94 #define OCRDMA_MAX_STAG 2048 95 96 enum { 97 OCRDMA_DB_RQ_OFFSET = 0xE0, 98 OCRDMA_DB_GEN2_RQ1_OFFSET = 0x100, 99 OCRDMA_DB_GEN2_RQ2_OFFSET = 0xC0, 100 OCRDMA_DB_SQ_OFFSET = 0x60, 101 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0, 102 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET, 103 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ1_OFFSET, 104 OCRDMA_DB_CQ_OFFSET = 0x120, 105 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET, 106 OCRDMA_DB_MQ_OFFSET = 0x140 107 }; 108 109 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 110 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */ 111 /* qid #2 msbits at 12-11 */ 112 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1 113 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 114 /* Rearm bit */ 115 #define OCRDMA_DB_CQ_REARM_SHIFT (29) /* bit 29 */ 116 /* solicited bit */ 117 #define OCRDMA_DB_CQ_SOLICIT_SHIFT (31) /* bit 31 */ 118 119 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */ 120 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 121 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 at 11-15 */ 122 123 /* Clear the interrupt for this eq */ 124 #define OCRDMA_EQ_CLR_SHIFT (9) /* bit 9 */ 125 /* Must be 1 */ 126 #define OCRDMA_EQ_TYPE_SHIFT (10) /* bit 10 */ 127 /* Number of event entries processed */ 128 #define OCRDMA_NUM_EQE_SHIFT (16) /* bits 16 - 28 */ 129 /* Rearm bit */ 130 #define OCRDMA_REARM_SHIFT (29) /* bit 29 */ 131 132 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */ 133 /* Number of entries posted */ 134 #define OCRDMA_MQ_NUM_MQE_SHIFT (16) /* bits 16 - 29 */ 135 136 #define OCRDMA_MIN_HPAGE_SIZE (4096) 137 138 #define OCRDMA_MIN_Q_PAGE_SIZE (4096) 139 #define OCRDMA_MAX_Q_PAGES (8) 140 141 /* 142 # 0: 4K Bytes 143 # 1: 8K Bytes 144 # 2: 16K Bytes 145 # 3: 32K Bytes 146 # 4: 64K Bytes 147 */ 148 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (5) 149 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES) 150 151 #define MAX_OCRDMA_QP_PAGES (8) 152 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE) 153 154 #define OCRDMA_CREATE_CQ_MAX_PAGES (4) 155 #define OCRDMA_DPP_CQE_SIZE (4) 156 157 #define OCRDMA_GEN2_MAX_CQE 1024 158 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096 159 #define OCRDMA_GEN2_WQE_SIZE 256 160 #define OCRDMA_MAX_CQE 4095 161 #define OCRDMA_CQ_PAGE_SIZE 16384 162 #define OCRDMA_WQE_SIZE 128 163 #define OCRDMA_WQE_STRIDE 8 164 #define OCRDMA_WQE_ALIGN_BYTES 16 165 166 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES 167 168 enum { 169 OCRDMA_MCH_OPCODE_SHIFT = 0, 170 OCRDMA_MCH_OPCODE_MASK = 0xFF, 171 OCRDMA_MCH_SUBSYS_SHIFT = 8, 172 OCRDMA_MCH_SUBSYS_MASK = 0xFF00 173 }; 174 175 /* mailbox cmd header */ 176 struct ocrdma_mbx_hdr { 177 u32 subsys_op; 178 u32 timeout; /* in seconds */ 179 u32 cmd_len; 180 u32 rsvd_version; 181 }; 182 183 enum { 184 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0, 185 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF, 186 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8, 187 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT, 188 189 OCRDMA_MBX_RSP_STATUS_SHIFT = 0, 190 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF, 191 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8, 192 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT 193 }; 194 195 /* mailbox cmd response */ 196 struct ocrdma_mbx_rsp { 197 u32 subsys_op; 198 u32 status; 199 u32 rsp_len; 200 u32 add_rsp_len; 201 }; 202 203 enum { 204 OCRDMA_MQE_EMBEDDED = 1, 205 OCRDMA_MQE_NONEMBEDDED = 0 206 }; 207 208 struct ocrdma_mqe_sge { 209 u32 pa_lo; 210 u32 pa_hi; 211 u32 len; 212 }; 213 214 enum { 215 OCRDMA_MQE_HDR_EMB_SHIFT = 0, 216 OCRDMA_MQE_HDR_EMB_MASK = Bit(0), 217 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3, 218 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT, 219 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24, 220 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT 221 }; 222 223 struct ocrdma_mqe_hdr { 224 u32 spcl_sge_cnt_emb; 225 u32 pyld_len; 226 u32 tag_lo; 227 u32 tag_hi; 228 u32 rsvd3; 229 }; 230 231 struct ocrdma_mqe_emb_cmd { 232 struct ocrdma_mbx_hdr mch; 233 u8 pyld[220]; 234 }; 235 236 struct ocrdma_mqe { 237 struct ocrdma_mqe_hdr hdr; 238 union { 239 struct ocrdma_mqe_emb_cmd emb_req; 240 struct { 241 struct ocrdma_mqe_sge sge[19]; 242 } nonemb_req; 243 u8 cmd[236]; 244 struct ocrdma_mbx_rsp rsp; 245 } u; 246 }; 247 248 #define OCRDMA_EQ_LEN 4096 249 #define OCRDMA_MQ_CQ_LEN 256 250 #define OCRDMA_MQ_LEN 128 251 252 #define PAGE_SHIFT_4K 12 253 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 254 255 /* Returns number of pages spanned by the data starting at the given addr */ 256 #define PAGES_4K_SPANNED(_address, size) \ 257 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 258 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 259 260 struct ocrdma_delete_q_req { 261 struct ocrdma_mbx_hdr req; 262 u32 id; 263 }; 264 265 struct ocrdma_pa { 266 u32 lo; 267 u32 hi; 268 }; 269 270 #define MAX_OCRDMA_EQ_PAGES (8) 271 struct ocrdma_create_eq_req { 272 struct ocrdma_mbx_hdr req; 273 u32 num_pages; 274 u32 valid; 275 u32 cnt; 276 u32 delay; 277 u32 rsvd; 278 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES]; 279 }; 280 281 enum { 282 OCRDMA_CREATE_EQ_VALID = Bit(29), 283 OCRDMA_CREATE_EQ_CNT_SHIFT = 26, 284 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13, 285 }; 286 287 struct ocrdma_create_eq_rsp { 288 struct ocrdma_mbx_rsp rsp; 289 u32 vector_eqid; 290 }; 291 292 #define OCRDMA_EQ_MINOR_OTHER (0x1) 293 294 enum { 295 OCRDMA_MCQE_STATUS_SHIFT = 0, 296 OCRDMA_MCQE_STATUS_MASK = 0xFFFF, 297 OCRDMA_MCQE_ESTATUS_SHIFT = 16, 298 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT, 299 OCRDMA_MCQE_CONS_SHIFT = 27, 300 OCRDMA_MCQE_CONS_MASK = Bit(27), 301 OCRDMA_MCQE_CMPL_SHIFT = 28, 302 OCRDMA_MCQE_CMPL_MASK = Bit(28), 303 OCRDMA_MCQE_AE_SHIFT = 30, 304 OCRDMA_MCQE_AE_MASK = Bit(30), 305 OCRDMA_MCQE_VALID_SHIFT = 31, 306 OCRDMA_MCQE_VALID_MASK = Bit(31) 307 }; 308 309 struct ocrdma_mcqe { 310 u32 status; 311 u32 tag_lo; 312 u32 tag_hi; 313 u32 valid_ae_cmpl_cons; 314 }; 315 316 enum { 317 OCRDMA_AE_MCQE_QPVALID = Bit(31), 318 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF, 319 320 OCRDMA_AE_MCQE_CQVALID = Bit(31), 321 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF, 322 OCRDMA_AE_MCQE_VALID = Bit(31), 323 OCRDMA_AE_MCQE_AE = Bit(30), 324 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16, 325 OCRDMA_AE_MCQE_EVENT_TYPE_MASK = 326 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT, 327 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8, 328 OCRDMA_AE_MCQE_EVENT_CODE_MASK = 329 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT 330 }; 331 struct ocrdma_ae_mcqe { 332 u32 qpvalid_qpid; 333 u32 cqvalid_cqid; 334 u32 evt_tag; 335 u32 valid_ae_event; 336 }; 337 338 enum { 339 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16, 340 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF << 341 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT, 342 343 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8, 344 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF << 345 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT, 346 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16, 347 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF << 348 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT, 349 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30, 350 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30), 351 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31, 352 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31) 353 }; 354 355 struct ocrdma_ae_mpa_mcqe { 356 u32 req_id; 357 u32 w1; 358 u32 w2; 359 u32 valid_ae_event; 360 }; 361 362 enum { 363 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0, 364 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF, 365 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16, 366 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF << 367 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT, 368 369 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8, 370 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF << 371 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT, 372 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16, 373 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF << 374 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT, 375 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30, 376 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30), 377 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31, 378 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31) 379 }; 380 381 struct ocrdma_ae_qp_mcqe { 382 u32 qp_id_state; 383 u32 w1; 384 u32 w2; 385 u32 valid_ae_event; 386 }; 387 388 #define OCRDMA_ASYNC_EVE_CODE 0x14 389 390 enum OCRDMA_ASYNC_EVENT_TYPE { 391 OCRDMA_CQ_ERROR = 0x00, 392 OCRDMA_CQ_OVERRUN_ERROR = 0x01, 393 OCRDMA_CQ_QPCAT_ERROR = 0x02, 394 OCRDMA_QP_ACCESS_ERROR = 0x03, 395 OCRDMA_QP_COMM_EST_EVENT = 0x04, 396 OCRDMA_SQ_DRAINED_EVENT = 0x05, 397 OCRDMA_DEVICE_FATAL_EVENT = 0x08, 398 OCRDMA_SRQCAT_ERROR = 0x0E, 399 OCRDMA_SRQ_LIMIT_EVENT = 0x0F, 400 OCRDMA_QP_LAST_WQE_EVENT = 0x10 401 }; 402 403 /* mailbox command request and responses */ 404 enum { 405 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2, 406 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2), 407 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3, 408 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3), 409 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8, 410 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF << 411 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT, 412 413 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16, 414 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF << 415 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT, 416 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8, 417 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF << 418 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT, 419 420 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0, 421 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF, 422 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16, 423 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF << 424 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT, 425 426 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0, 427 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF, 428 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16, 429 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF << 430 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT, 431 432 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24, 433 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF << 434 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET, 435 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16, 436 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF << 437 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET, 438 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0, 439 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF << 440 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET, 441 442 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16, 443 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF << 444 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET, 445 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0, 446 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF << 447 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET, 448 449 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16, 450 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF << 451 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET, 452 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0, 453 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF << 454 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET, 455 456 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0, 457 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF << 458 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET, 459 460 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16, 461 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF << 462 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET, 463 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0, 464 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF << 465 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET, 466 467 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16, 468 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF << 469 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET, 470 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0, 471 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF << 472 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET, 473 474 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16, 475 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF << 476 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET, 477 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0, 478 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF << 479 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET, 480 }; 481 482 struct ocrdma_mbx_query_config { 483 struct ocrdma_mqe_hdr hdr; 484 struct ocrdma_mbx_rsp rsp; 485 u32 qp_srq_cq_ird_ord; 486 u32 max_pd_ca_ack_delay; 487 u32 max_write_send_sge; 488 u32 max_ird_ord_per_qp; 489 u32 max_shared_ird_ord; 490 u32 max_mr; 491 u32 max_mr_size_lo; 492 u32 max_mr_size_hi; 493 u32 max_num_mr_pbl; 494 u32 max_mw; 495 u32 max_fmr; 496 u32 max_pages_per_frmr; 497 u32 max_mcast_group; 498 u32 max_mcast_qp_attach; 499 u32 max_total_mcast_qp_attach; 500 u32 wqe_rqe_stride_max_dpp_cqs; 501 u32 max_srq_rpir_qps; 502 u32 max_dpp_pds_credits; 503 u32 max_dpp_credits_pds_per_pd; 504 u32 max_wqes_rqes_per_q; 505 u32 max_cq_cqes_per_cq; 506 u32 max_srq_rqe_sge; 507 }; 508 509 struct ocrdma_fw_ver_rsp { 510 struct ocrdma_mqe_hdr hdr; 511 struct ocrdma_mbx_rsp rsp; 512 513 u8 running_ver[32]; 514 }; 515 516 struct ocrdma_fw_conf_rsp { 517 struct ocrdma_mqe_hdr hdr; 518 struct ocrdma_mbx_rsp rsp; 519 520 u32 config_num; 521 u32 asic_revision; 522 u32 phy_port; 523 u32 fn_mode; 524 struct { 525 u32 mode; 526 u32 nic_wqid_base; 527 u32 nic_wq_tot; 528 u32 prot_wqid_base; 529 u32 prot_wq_tot; 530 u32 prot_rqid_base; 531 u32 prot_rqid_tot; 532 u32 rsvd[6]; 533 } ulp[2]; 534 u32 fn_capabilities; 535 u32 rsvd1; 536 u32 rsvd2; 537 u32 base_eqid; 538 u32 max_eq; 539 540 }; 541 542 enum { 543 OCRDMA_FN_MODE_RDMA = 0x4 544 }; 545 546 enum { 547 OCRDMA_CREATE_CQ_VER2 = 2, 548 549 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF, 550 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16, 551 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF, 552 553 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12, 554 OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12), 555 OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14), 556 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15), 557 558 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF, 559 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF 560 }; 561 562 enum { 563 OCRDMA_CREATE_CQ_VER0 = 0, 564 OCRDMA_CREATE_CQ_DPP = 1, 565 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24, 566 OCRDMA_CREATE_CQ_EQID_SHIFT = 22, 567 568 OCRDMA_CREATE_CQ_CNT_SHIFT = 27, 569 OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29), 570 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31), 571 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID | 572 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE | 573 OCRDMA_CREATE_CQ_FLAGS_NODELAY 574 }; 575 576 struct ocrdma_create_cq_cmd { 577 struct ocrdma_mbx_hdr req; 578 u32 pgsz_pgcnt; 579 u32 ev_cnt_flags; 580 u32 eqn; 581 u32 cqe_count; 582 u32 rsvd6; 583 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES]; 584 }; 585 586 struct ocrdma_create_cq { 587 struct ocrdma_mqe_hdr hdr; 588 struct ocrdma_create_cq_cmd cmd; 589 }; 590 591 enum { 592 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF 593 }; 594 595 struct ocrdma_create_cq_cmd_rsp { 596 struct ocrdma_mbx_rsp rsp; 597 u32 cq_id; 598 }; 599 600 struct ocrdma_create_cq_rsp { 601 struct ocrdma_mqe_hdr hdr; 602 struct ocrdma_create_cq_cmd_rsp rsp; 603 }; 604 605 enum { 606 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22, 607 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16, 608 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16, 609 OCRDMA_CREATE_MQ_VALID = Bit(31), 610 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0) 611 }; 612 613 struct ocrdma_create_mq_req { 614 struct ocrdma_mbx_hdr req; 615 u32 cqid_pages; 616 u32 async_event_bitmap; 617 u32 async_cqid_ringsize; 618 u32 valid; 619 u32 async_cqid_valid; 620 u32 rsvd; 621 struct ocrdma_pa pa[8]; 622 }; 623 624 struct ocrdma_create_mq_rsp { 625 struct ocrdma_mbx_rsp rsp; 626 u32 id; 627 }; 628 629 enum { 630 OCRDMA_DESTROY_CQ_QID_SHIFT = 0, 631 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF, 632 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16, 633 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF << 634 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT 635 }; 636 637 struct ocrdma_destroy_cq { 638 struct ocrdma_mqe_hdr hdr; 639 struct ocrdma_mbx_hdr req; 640 641 u32 bypass_flush_qid; 642 }; 643 644 struct ocrdma_destroy_cq_rsp { 645 struct ocrdma_mqe_hdr hdr; 646 struct ocrdma_mbx_rsp rsp; 647 }; 648 649 enum { 650 OCRDMA_QPT_GSI = 1, 651 OCRDMA_QPT_RC = 2, 652 OCRDMA_QPT_UD = 4, 653 }; 654 655 enum { 656 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0, 657 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF, 658 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16, 659 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19, 660 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29, 661 OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29), 662 663 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0, 664 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF, 665 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16, 666 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF << 667 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT, 668 669 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0, 670 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF, 671 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16, 672 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF << 673 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT, 674 675 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0, 676 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0), 677 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1, 678 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1), 679 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2, 680 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2), 681 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3, 682 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3), 683 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4, 684 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4), 685 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5, 686 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5), 687 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6, 688 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6), 689 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7, 690 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7), 691 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8, 692 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8), 693 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16, 694 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF << 695 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT, 696 697 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0, 698 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF, 699 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16, 700 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF << 701 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT, 702 703 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0, 704 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF, 705 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16, 706 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF << 707 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT, 708 709 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0, 710 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF, 711 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16, 712 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF << 713 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT, 714 715 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0, 716 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF, 717 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16, 718 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF << 719 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT, 720 721 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0, 722 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF, 723 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16, 724 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF << 725 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT 726 }; 727 728 enum { 729 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16, 730 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1 731 }; 732 733 #define MAX_OCRDMA_IRD_PAGES 4 734 735 enum ocrdma_qp_flags { 736 OCRDMA_QP_MW_BIND = 1, 737 OCRDMA_QP_LKEY0 = (1 << 1), 738 OCRDMA_QP_FAST_REG = (1 << 2), 739 OCRDMA_QP_INB_RD = (1 << 6), 740 OCRDMA_QP_INB_WR = (1 << 7), 741 }; 742 743 enum ocrdma_qp_state { 744 OCRDMA_QPS_RST = 0, 745 OCRDMA_QPS_INIT = 1, 746 OCRDMA_QPS_RTR = 2, 747 OCRDMA_QPS_RTS = 3, 748 OCRDMA_QPS_SQE = 4, 749 OCRDMA_QPS_SQ_DRAINING = 5, 750 OCRDMA_QPS_ERR = 6, 751 OCRDMA_QPS_SQD = 7 752 }; 753 754 struct ocrdma_create_qp_req { 755 struct ocrdma_mqe_hdr hdr; 756 struct ocrdma_mbx_hdr req; 757 758 u32 type_pgsz_pdn; 759 u32 max_wqe_rqe; 760 u32 max_sge_send_write; 761 u32 max_sge_recv_flags; 762 u32 max_ord_ird; 763 u32 num_wq_rq_pages; 764 u32 wqe_rqe_size; 765 u32 wq_rq_cqid; 766 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES]; 767 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES]; 768 u32 dpp_credits_cqid; 769 u32 rpir_lkey; 770 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES]; 771 }; 772 773 enum { 774 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0, 775 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF, 776 777 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0, 778 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF, 779 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16, 780 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF << 781 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT, 782 783 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0, 784 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF, 785 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16, 786 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF << 787 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT, 788 789 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16, 790 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF << 791 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT, 792 793 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0, 794 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF, 795 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16, 796 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF << 797 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT, 798 799 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0, 800 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF, 801 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16, 802 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF << 803 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT, 804 805 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0), 806 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1, 807 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF << 808 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT, 809 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16, 810 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF << 811 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT, 812 }; 813 814 struct ocrdma_create_qp_rsp { 815 struct ocrdma_mqe_hdr hdr; 816 struct ocrdma_mbx_rsp rsp; 817 818 u32 qp_id; 819 u32 max_wqe_rqe; 820 u32 max_sge_send_write; 821 u32 max_sge_recv; 822 u32 max_ord_ird; 823 u32 sq_rq_id; 824 u32 dpp_response; 825 }; 826 827 struct ocrdma_destroy_qp { 828 struct ocrdma_mqe_hdr hdr; 829 struct ocrdma_mbx_hdr req; 830 u32 qp_id; 831 }; 832 833 struct ocrdma_destroy_qp_rsp { 834 struct ocrdma_mqe_hdr hdr; 835 struct ocrdma_mbx_rsp rsp; 836 }; 837 838 enum { 839 OCRDMA_MODIFY_QP_ID_SHIFT = 0, 840 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF, 841 842 OCRDMA_QP_PARA_QPS_VALID = Bit(0), 843 OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1), 844 OCRDMA_QP_PARA_PKEY_VALID = Bit(2), 845 OCRDMA_QP_PARA_QKEY_VALID = Bit(3), 846 OCRDMA_QP_PARA_PMTU_VALID = Bit(4), 847 OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5), 848 OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6), 849 OCRDMA_QP_PARA_RRC_VALID = Bit(7), 850 OCRDMA_QP_PARA_RQPSN_VALID = Bit(8), 851 OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9), 852 OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10), 853 OCRDMA_QP_PARA_RNT_VALID = Bit(11), 854 OCRDMA_QP_PARA_SQPSN_VALID = Bit(12), 855 OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13), 856 OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14), 857 OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15), 858 OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16), 859 OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17), 860 OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18), 861 OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19), 862 OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20), 863 OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21), 864 OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22), 865 OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23), 866 OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24), 867 OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25), 868 OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26), 869 870 OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0), 871 OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1), 872 OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2), 873 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3) 874 }; 875 876 enum { 877 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0, 878 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF, 879 880 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0, 881 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF, 882 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16, 883 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF << 884 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT, 885 886 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0, 887 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF, 888 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16, 889 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF << 890 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT, 891 892 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0), 893 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1), 894 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2), 895 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3), 896 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4), 897 OCRDMA_QP_PARAMS_STATE_SHIFT = 5, 898 OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7), 899 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8), 900 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9), 901 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16, 902 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF << 903 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT, 904 905 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0, 906 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF, 907 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16, 908 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF << 909 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT, 910 911 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0, 912 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF, 913 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16, 914 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF << 915 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT, 916 917 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0, 918 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF, 919 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24, 920 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF << 921 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT, 922 923 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0, 924 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF, 925 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24, 926 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF << 927 OCRDMA_QP_PARAMS_TCLASS_SHIFT, 928 929 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0, 930 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF, 931 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24, 932 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 << 933 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT, 934 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27, 935 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F << 936 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT, 937 938 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0, 939 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF, 940 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18, 941 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF << 942 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT, 943 944 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0, 945 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF, 946 OCRDMA_QP_PARAMS_SL_SHIFT = 20, 947 OCRDMA_QP_PARAMS_SL_MASK = 0xF << 948 OCRDMA_QP_PARAMS_SL_SHIFT, 949 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24, 950 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 << 951 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT, 952 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27, 953 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F << 954 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT, 955 956 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0, 957 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF, 958 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16, 959 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF << 960 OCRDMA_QP_PARAMS_VLAN_SHIFT 961 }; 962 963 struct ocrdma_qp_params { 964 u32 id; 965 u32 max_wqe_rqe; 966 u32 max_sge_send_write; 967 u32 max_sge_recv_flags; 968 u32 max_ord_ird; 969 u32 wq_rq_cqid; 970 u32 hop_lmt_rq_psn; 971 u32 tclass_sq_psn; 972 u32 ack_to_rnr_rtc_dest_qpn; 973 u32 path_mtu_pkey_indx; 974 u32 rnt_rc_sl_fl; 975 u8 sgid[16]; 976 u8 dgid[16]; 977 u32 dmac_b0_to_b3; 978 u32 vlan_dmac_b4_to_b5; 979 u32 qkey; 980 }; 981 982 983 struct ocrdma_modify_qp { 984 struct ocrdma_mqe_hdr hdr; 985 struct ocrdma_mbx_hdr req; 986 987 struct ocrdma_qp_params params; 988 u32 flags; 989 u32 rdma_flags; 990 u32 num_outstanding_atomic_rd; 991 }; 992 993 enum { 994 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0, 995 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF, 996 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16, 997 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF << 998 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT, 999 1000 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0, 1001 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF, 1002 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16, 1003 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF << 1004 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT 1005 }; 1006 struct ocrdma_modify_qp_rsp { 1007 struct ocrdma_mqe_hdr hdr; 1008 struct ocrdma_mbx_rsp rsp; 1009 1010 u32 max_wqe_rqe; 1011 u32 max_ord_ird; 1012 }; 1013 1014 struct ocrdma_query_qp { 1015 struct ocrdma_mqe_hdr hdr; 1016 struct ocrdma_mbx_hdr req; 1017 1018 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0 1019 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF 1020 u32 qp_id; 1021 }; 1022 1023 struct ocrdma_query_qp_rsp { 1024 struct ocrdma_mqe_hdr hdr; 1025 struct ocrdma_mbx_rsp rsp; 1026 struct ocrdma_qp_params params; 1027 }; 1028 1029 enum { 1030 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0, 1031 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF, 1032 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16, 1033 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 << 1034 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT, 1035 1036 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0, 1037 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16, 1038 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF << 1039 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT, 1040 1041 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0, 1042 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF, 1043 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16, 1044 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF << 1045 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT 1046 }; 1047 1048 struct ocrdma_create_srq { 1049 struct ocrdma_mqe_hdr hdr; 1050 struct ocrdma_mbx_hdr req; 1051 1052 u32 pgsz_pdid; 1053 u32 max_sge_rqe; 1054 u32 pages_rqe_sz; 1055 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES]; 1056 }; 1057 1058 enum { 1059 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0, 1060 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF, 1061 1062 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0, 1063 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF, 1064 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16, 1065 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF << 1066 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT 1067 }; 1068 1069 struct ocrdma_create_srq_rsp { 1070 struct ocrdma_mqe_hdr hdr; 1071 struct ocrdma_mbx_rsp rsp; 1072 1073 u32 id; 1074 u32 max_sge_rqe_allocated; 1075 }; 1076 1077 enum { 1078 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0, 1079 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF, 1080 1081 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0, 1082 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF, 1083 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16, 1084 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF << 1085 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT 1086 }; 1087 1088 struct ocrdma_modify_srq { 1089 struct ocrdma_mqe_hdr hdr; 1090 struct ocrdma_mbx_rsp rep; 1091 1092 u32 id; 1093 u32 limit_max_rqe; 1094 }; 1095 1096 enum { 1097 OCRDMA_QUERY_SRQ_ID_SHIFT = 0, 1098 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF 1099 }; 1100 1101 struct ocrdma_query_srq { 1102 struct ocrdma_mqe_hdr hdr; 1103 struct ocrdma_mbx_rsp req; 1104 1105 u32 id; 1106 }; 1107 1108 enum { 1109 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0, 1110 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF, 1111 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16, 1112 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF << 1113 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT, 1114 1115 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0, 1116 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF, 1117 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16, 1118 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF << 1119 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT 1120 }; 1121 1122 struct ocrdma_query_srq_rsp { 1123 struct ocrdma_mqe_hdr hdr; 1124 struct ocrdma_mbx_rsp req; 1125 1126 u32 max_rqe_pdid; 1127 u32 srq_lmt_max_sge; 1128 }; 1129 1130 enum { 1131 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0, 1132 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF 1133 }; 1134 1135 struct ocrdma_destroy_srq { 1136 struct ocrdma_mqe_hdr hdr; 1137 struct ocrdma_mbx_rsp req; 1138 1139 u32 id; 1140 }; 1141 1142 enum { 1143 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16), 1144 OCRDMA_PD_MAX_DPP_ENABLED_QP = 8, 1145 OCRDMA_DPP_PAGE_SIZE = 4096 1146 }; 1147 1148 struct ocrdma_alloc_pd { 1149 struct ocrdma_mqe_hdr hdr; 1150 struct ocrdma_mbx_hdr req; 1151 u32 enable_dpp_rsvd; 1152 }; 1153 1154 enum { 1155 OCRDMA_ALLOC_PD_RSP_DPP = Bit(16), 1156 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20, 1157 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF, 1158 }; 1159 1160 struct ocrdma_alloc_pd_rsp { 1161 struct ocrdma_mqe_hdr hdr; 1162 struct ocrdma_mbx_rsp rsp; 1163 u32 dpp_page_pdid; 1164 }; 1165 1166 struct ocrdma_dealloc_pd { 1167 struct ocrdma_mqe_hdr hdr; 1168 struct ocrdma_mbx_hdr req; 1169 u32 id; 1170 }; 1171 1172 struct ocrdma_dealloc_pd_rsp { 1173 struct ocrdma_mqe_hdr hdr; 1174 struct ocrdma_mbx_rsp rsp; 1175 }; 1176 1177 enum { 1178 OCRDMA_ADDR_CHECK_ENABLE = 1, 1179 OCRDMA_ADDR_CHECK_DISABLE = 0 1180 }; 1181 1182 enum { 1183 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0, 1184 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF, 1185 1186 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0, 1187 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0), 1188 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1, 1189 OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1), 1190 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2, 1191 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2), 1192 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3, 1193 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3), 1194 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4, 1195 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4), 1196 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5, 1197 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5), 1198 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6), 1199 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6, 1200 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16, 1201 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF << 1202 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT 1203 }; 1204 1205 struct ocrdma_alloc_lkey { 1206 struct ocrdma_mqe_hdr hdr; 1207 struct ocrdma_mbx_hdr req; 1208 1209 u32 pdid; 1210 u32 pbl_sz_flags; 1211 }; 1212 1213 struct ocrdma_alloc_lkey_rsp { 1214 struct ocrdma_mqe_hdr hdr; 1215 struct ocrdma_mbx_rsp rsp; 1216 1217 u32 lrkey; 1218 u32 num_pbl_rsvd; 1219 }; 1220 1221 struct ocrdma_dealloc_lkey { 1222 struct ocrdma_mqe_hdr hdr; 1223 struct ocrdma_mbx_hdr req; 1224 1225 u32 lkey; 1226 u32 rsvd_frmr; 1227 }; 1228 1229 struct ocrdma_dealloc_lkey_rsp { 1230 struct ocrdma_mqe_hdr hdr; 1231 struct ocrdma_mbx_rsp rsp; 1232 }; 1233 1234 #define MAX_OCRDMA_NSMR_PBL (u32)22 1235 #define MAX_OCRDMA_PBL_SIZE 65536 1236 #define MAX_OCRDMA_PBL_PER_LKEY 32767 1237 1238 enum { 1239 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0, 1240 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF, 1241 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24, 1242 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF << 1243 OCRDMA_REG_NSMR_LRKEY_SHIFT, 1244 1245 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0, 1246 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF, 1247 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16, 1248 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF << 1249 OCRDMA_REG_NSMR_NUM_PBL_SHIFT, 1250 1251 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0, 1252 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF, 1253 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16, 1254 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF << 1255 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT, 1256 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24, 1257 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24), 1258 OCRDMA_REG_NSMR_ZB_SHIFT = 25, 1259 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25), 1260 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26, 1261 OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26), 1262 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27, 1263 OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27), 1264 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28, 1265 OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28), 1266 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29, 1267 OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29), 1268 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30, 1269 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30), 1270 OCRDMA_REG_NSMR_LAST_SHIFT = 31, 1271 OCRDMA_REG_NSMR_LAST_MASK = Bit(31) 1272 }; 1273 1274 struct ocrdma_reg_nsmr { 1275 struct ocrdma_mqe_hdr hdr; 1276 struct ocrdma_mbx_hdr cmd; 1277 1278 u32 lrkey_key_index; 1279 u32 num_pbl_pdid; 1280 u32 flags_hpage_pbe_sz; 1281 u32 totlen_low; 1282 u32 totlen_high; 1283 u32 fbo_low; 1284 u32 fbo_high; 1285 u32 va_loaddr; 1286 u32 va_hiaddr; 1287 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1288 }; 1289 1290 enum { 1291 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0, 1292 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF, 1293 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16, 1294 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF << 1295 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT, 1296 1297 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31, 1298 OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31) 1299 }; 1300 1301 struct ocrdma_reg_nsmr_cont { 1302 struct ocrdma_mqe_hdr hdr; 1303 struct ocrdma_mbx_hdr cmd; 1304 1305 u32 lrkey; 1306 u32 num_pbl_offset; 1307 u32 last; 1308 1309 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1310 }; 1311 1312 struct ocrdma_pbe { 1313 u32 pa_hi; 1314 u32 pa_lo; 1315 }; 1316 1317 enum { 1318 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16, 1319 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000 1320 }; 1321 struct ocrdma_reg_nsmr_rsp { 1322 struct ocrdma_mqe_hdr hdr; 1323 struct ocrdma_mbx_rsp rsp; 1324 1325 u32 lrkey; 1326 u32 num_pbl; 1327 }; 1328 1329 enum { 1330 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0, 1331 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF, 1332 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24, 1333 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF << 1334 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT, 1335 1336 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16, 1337 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF << 1338 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT 1339 }; 1340 1341 struct ocrdma_reg_nsmr_cont_rsp { 1342 struct ocrdma_mqe_hdr hdr; 1343 struct ocrdma_mbx_rsp rsp; 1344 1345 u32 lrkey_key_index; 1346 u32 num_pbl; 1347 }; 1348 1349 enum { 1350 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0, 1351 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF 1352 }; 1353 1354 struct ocrdma_alloc_mw { 1355 struct ocrdma_mqe_hdr hdr; 1356 struct ocrdma_mbx_hdr req; 1357 1358 u32 pdid; 1359 }; 1360 1361 enum { 1362 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0, 1363 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF 1364 }; 1365 1366 struct ocrdma_alloc_mw_rsp { 1367 struct ocrdma_mqe_hdr hdr; 1368 struct ocrdma_mbx_rsp rsp; 1369 1370 u32 lrkey_index; 1371 }; 1372 1373 struct ocrdma_attach_mcast { 1374 struct ocrdma_mqe_hdr hdr; 1375 struct ocrdma_mbx_hdr req; 1376 u32 qp_id; 1377 u8 mgid[16]; 1378 u32 mac_b0_to_b3; 1379 u32 vlan_mac_b4_to_b5; 1380 }; 1381 1382 struct ocrdma_attach_mcast_rsp { 1383 struct ocrdma_mqe_hdr hdr; 1384 struct ocrdma_mbx_rsp rsp; 1385 }; 1386 1387 struct ocrdma_detach_mcast { 1388 struct ocrdma_mqe_hdr hdr; 1389 struct ocrdma_mbx_hdr req; 1390 u32 qp_id; 1391 u8 mgid[16]; 1392 u32 mac_b0_to_b3; 1393 u32 vlan_mac_b4_to_b5; 1394 }; 1395 1396 struct ocrdma_detach_mcast_rsp { 1397 struct ocrdma_mqe_hdr hdr; 1398 struct ocrdma_mbx_rsp rsp; 1399 }; 1400 1401 enum { 1402 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19, 1403 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF << 1404 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT, 1405 1406 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16, 1407 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 << 1408 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT, 1409 1410 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23, 1411 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF << 1412 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT, 1413 }; 1414 1415 #define OCRDMA_AH_TBL_PAGES 8 1416 1417 struct ocrdma_create_ah_tbl { 1418 struct ocrdma_mqe_hdr hdr; 1419 struct ocrdma_mbx_hdr req; 1420 1421 u32 ah_conf; 1422 struct ocrdma_pa tbl_addr[8]; 1423 }; 1424 1425 struct ocrdma_create_ah_tbl_rsp { 1426 struct ocrdma_mqe_hdr hdr; 1427 struct ocrdma_mbx_rsp rsp; 1428 u32 ahid; 1429 }; 1430 1431 struct ocrdma_delete_ah_tbl { 1432 struct ocrdma_mqe_hdr hdr; 1433 struct ocrdma_mbx_hdr req; 1434 u32 ahid; 1435 }; 1436 1437 struct ocrdma_delete_ah_tbl_rsp { 1438 struct ocrdma_mqe_hdr hdr; 1439 struct ocrdma_mbx_rsp rsp; 1440 }; 1441 1442 enum { 1443 OCRDMA_EQE_VALID_SHIFT = 0, 1444 OCRDMA_EQE_VALID_MASK = Bit(0), 1445 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE, 1446 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16, 1447 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF << 1448 OCRDMA_EQE_RESOURCE_ID_SHIFT, 1449 }; 1450 1451 struct ocrdma_eqe { 1452 u32 id_valid; 1453 }; 1454 1455 enum OCRDMA_CQE_STATUS { 1456 OCRDMA_CQE_SUCCESS = 0, 1457 OCRDMA_CQE_LOC_LEN_ERR, 1458 OCRDMA_CQE_LOC_QP_OP_ERR, 1459 OCRDMA_CQE_LOC_EEC_OP_ERR, 1460 OCRDMA_CQE_LOC_PROT_ERR, 1461 OCRDMA_CQE_WR_FLUSH_ERR, 1462 OCRDMA_CQE_MW_BIND_ERR, 1463 OCRDMA_CQE_BAD_RESP_ERR, 1464 OCRDMA_CQE_LOC_ACCESS_ERR, 1465 OCRDMA_CQE_REM_INV_REQ_ERR, 1466 OCRDMA_CQE_REM_ACCESS_ERR, 1467 OCRDMA_CQE_REM_OP_ERR, 1468 OCRDMA_CQE_RETRY_EXC_ERR, 1469 OCRDMA_CQE_RNR_RETRY_EXC_ERR, 1470 OCRDMA_CQE_LOC_RDD_VIOL_ERR, 1471 OCRDMA_CQE_REM_INV_RD_REQ_ERR, 1472 OCRDMA_CQE_REM_ABORT_ERR, 1473 OCRDMA_CQE_INV_EECN_ERR, 1474 OCRDMA_CQE_INV_EEC_STATE_ERR, 1475 OCRDMA_CQE_FATAL_ERR, 1476 OCRDMA_CQE_RESP_TIMEOUT_ERR, 1477 OCRDMA_CQE_GENERAL_ERR 1478 }; 1479 1480 enum { 1481 /* w0 */ 1482 OCRDMA_CQE_WQEIDX_SHIFT = 0, 1483 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF, 1484 1485 /* w1 */ 1486 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16, 1487 OCRDMA_CQE_PKEY_SHIFT = 0, 1488 OCRDMA_CQE_PKEY_MASK = 0xFFFF, 1489 1490 /* w2 */ 1491 OCRDMA_CQE_QPN_SHIFT = 0, 1492 OCRDMA_CQE_QPN_MASK = 0x0000FFFF, 1493 1494 OCRDMA_CQE_BUFTAG_SHIFT = 16, 1495 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT, 1496 1497 /* w3 */ 1498 OCRDMA_CQE_UD_STATUS_SHIFT = 24, 1499 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT, 1500 OCRDMA_CQE_STATUS_SHIFT = 16, 1501 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT, 1502 OCRDMA_CQE_VALID = Bit(31), 1503 OCRDMA_CQE_INVALIDATE = Bit(30), 1504 OCRDMA_CQE_QTYPE = Bit(29), 1505 OCRDMA_CQE_IMM = Bit(28), 1506 OCRDMA_CQE_WRITE_IMM = Bit(27), 1507 OCRDMA_CQE_QTYPE_SQ = 0, 1508 OCRDMA_CQE_QTYPE_RQ = 1, 1509 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF 1510 }; 1511 1512 struct ocrdma_cqe { 1513 union { 1514 /* w0 to w2 */ 1515 struct { 1516 u32 wqeidx; 1517 u32 bytes_xfered; 1518 u32 qpn; 1519 } wq; 1520 struct { 1521 u32 lkey_immdt; 1522 u32 rxlen; 1523 u32 buftag_qpn; 1524 } rq; 1525 struct { 1526 u32 lkey_immdt; 1527 u32 rxlen_pkey; 1528 u32 buftag_qpn; 1529 } ud; 1530 struct { 1531 u32 word_0; 1532 u32 word_1; 1533 u32 qpn; 1534 } cmn; 1535 }; 1536 u32 flags_status_srcqpn; /* w3 */ 1537 }; 1538 1539 struct ocrdma_sge { 1540 u32 addr_hi; 1541 u32 addr_lo; 1542 u32 lrkey; 1543 u32 len; 1544 }; 1545 1546 enum { 1547 OCRDMA_FLAG_SIG = 0x1, 1548 OCRDMA_FLAG_INV = 0x2, 1549 OCRDMA_FLAG_FENCE_L = 0x4, 1550 OCRDMA_FLAG_FENCE_R = 0x8, 1551 OCRDMA_FLAG_SOLICIT = 0x10, 1552 OCRDMA_FLAG_IMM = 0x20, 1553 1554 /* Stag flags */ 1555 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1, 1556 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2, 1557 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4, 1558 OCRDMA_LKEY_FLAG_VATO = 0x8, 1559 }; 1560 1561 enum OCRDMA_WQE_OPCODE { 1562 OCRDMA_WRITE = 0x06, 1563 OCRDMA_READ = 0x0C, 1564 OCRDMA_RESV0 = 0x02, 1565 OCRDMA_SEND = 0x00, 1566 OCRDMA_CMP_SWP = 0x14, 1567 OCRDMA_BIND_MW = 0x10, 1568 OCRDMA_FR_MR = 0x11, 1569 OCRDMA_RESV1 = 0x0A, 1570 OCRDMA_LKEY_INV = 0x15, 1571 OCRDMA_FETCH_ADD = 0x13, 1572 OCRDMA_POST_RQ = 0x12 1573 }; 1574 1575 enum { 1576 OCRDMA_TYPE_INLINE = 0x0, 1577 OCRDMA_TYPE_LKEY = 0x1, 1578 }; 1579 1580 enum { 1581 OCRDMA_WQE_OPCODE_SHIFT = 0, 1582 OCRDMA_WQE_OPCODE_MASK = 0x0000001F, 1583 OCRDMA_WQE_FLAGS_SHIFT = 5, 1584 OCRDMA_WQE_TYPE_SHIFT = 16, 1585 OCRDMA_WQE_TYPE_MASK = 0x00030000, 1586 OCRDMA_WQE_SIZE_SHIFT = 18, 1587 OCRDMA_WQE_SIZE_MASK = 0xFF, 1588 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25, 1589 1590 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0, 1591 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF 1592 }; 1593 1594 /* header WQE for all the SQ and RQ operations */ 1595 struct ocrdma_hdr_wqe { 1596 u32 cw; 1597 union { 1598 u32 rsvd_tag; 1599 u32 rsvd_lkey_flags; 1600 }; 1601 union { 1602 u32 immdt; 1603 u32 lkey; 1604 }; 1605 u32 total_len; 1606 }; 1607 1608 struct ocrdma_ewqe_ud_hdr { 1609 u32 rsvd_dest_qpn; 1610 u32 qkey; 1611 u32 rsvd_ahid; 1612 u32 rsvd; 1613 }; 1614 1615 #define OCRDMA_MAX_FR_PBES 11 1616 struct ocrdma_fr_pbe { 1617 u32 pa_hi; 1618 u32 pa_lo; 1619 }; 1620 1621 /* extended wqe followed by hdr_wqe for Fast Memory register */ 1622 struct ocrdma_ewqe_fr { 1623 u32 va_hi; 1624 u32 va_lo; 1625 u32 fbo_hi; 1626 u32 fbo_lo; 1627 u32 size_sge; 1628 u32 num_sges; 1629 struct ocrdma_fr_pbe pbe[0]; 1630 }; 1631 1632 struct ocrdma_eth_basic { 1633 u8 dmac[6]; 1634 u8 smac[6]; 1635 __be16 eth_type; 1636 } __packed; 1637 1638 struct ocrdma_eth_vlan { 1639 u8 dmac[6]; 1640 u8 smac[6]; 1641 __be16 eth_type; 1642 __be16 vlan_tag; 1643 #define OCRDMA_ROCE_ETH_TYPE 0x8915 1644 __be16 roce_eth_type; 1645 } __packed; 1646 1647 struct ocrdma_grh { 1648 __be32 tclass_flow; 1649 __be32 pdid_hoplimit; 1650 u8 sgid[16]; 1651 u8 dgid[16]; 1652 u16 rsvd; 1653 } __packed; 1654 1655 #define OCRDMA_AV_VALID Bit(0) 1656 #define OCRDMA_AV_VLAN_VALID Bit(1) 1657 1658 struct ocrdma_av { 1659 struct ocrdma_eth_vlan eth_hdr; 1660 struct ocrdma_grh grh; 1661 u32 valid; 1662 } __packed; 1663 1664 #endif /* __OCRDMA_SLI_H__ */ 1665