1fe2caefcSParav Pandit /******************************************************************* 2fe2caefcSParav Pandit * This file is part of the Emulex RoCE Device Driver for * 3fe2caefcSParav Pandit * RoCE (RDMA over Converged Ethernet) adapters. * 4fe2caefcSParav Pandit * Copyright (C) 2008-2012 Emulex. All rights reserved. * 5fe2caefcSParav Pandit * EMULEX and SLI are trademarks of Emulex. * 6fe2caefcSParav Pandit * www.emulex.com * 7fe2caefcSParav Pandit * * 8fe2caefcSParav Pandit * This program is free software; you can redistribute it and/or * 9fe2caefcSParav Pandit * modify it under the terms of version 2 of the GNU General * 10fe2caefcSParav Pandit * Public License as published by the Free Software Foundation. * 11fe2caefcSParav Pandit * This program is distributed in the hope that it will be useful. * 12fe2caefcSParav Pandit * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13fe2caefcSParav Pandit * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14fe2caefcSParav Pandit * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15fe2caefcSParav Pandit * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16fe2caefcSParav Pandit * TO BE LEGALLY INVALID. See the GNU General Public License for * 17fe2caefcSParav Pandit * more details, a copy of which can be found in the file COPYING * 18fe2caefcSParav Pandit * included with this package. * 19fe2caefcSParav Pandit * 20fe2caefcSParav Pandit * Contact Information: 21fe2caefcSParav Pandit * linux-drivers@emulex.com 22fe2caefcSParav Pandit * 23fe2caefcSParav Pandit * Emulex 24fe2caefcSParav Pandit * 3333 Susan Street 25fe2caefcSParav Pandit * Costa Mesa, CA 92626 26fe2caefcSParav Pandit *******************************************************************/ 27fe2caefcSParav Pandit 28fe2caefcSParav Pandit #ifndef __OCRDMA_SLI_H__ 29fe2caefcSParav Pandit #define __OCRDMA_SLI_H__ 30fe2caefcSParav Pandit 31fe2caefcSParav Pandit #define Bit(_b) (1 << (_b)) 32fe2caefcSParav Pandit 33fe2caefcSParav Pandit #define OCRDMA_GEN1_FAMILY 0xB 34fe2caefcSParav Pandit #define OCRDMA_GEN2_FAMILY 0x2 35fe2caefcSParav Pandit 36fe2caefcSParav Pandit #define OCRDMA_SUBSYS_ROCE 10 37fe2caefcSParav Pandit enum { 38fe2caefcSParav Pandit OCRDMA_CMD_QUERY_CONFIG = 1, 39fe2caefcSParav Pandit OCRDMA_CMD_ALLOC_PD, 40fe2caefcSParav Pandit OCRDMA_CMD_DEALLOC_PD, 41fe2caefcSParav Pandit 42fe2caefcSParav Pandit OCRDMA_CMD_CREATE_AH_TBL, 43fe2caefcSParav Pandit OCRDMA_CMD_DELETE_AH_TBL, 44fe2caefcSParav Pandit 45fe2caefcSParav Pandit OCRDMA_CMD_CREATE_QP, 46fe2caefcSParav Pandit OCRDMA_CMD_QUERY_QP, 47fe2caefcSParav Pandit OCRDMA_CMD_MODIFY_QP, 48fe2caefcSParav Pandit OCRDMA_CMD_DELETE_QP, 49fe2caefcSParav Pandit 50fe2caefcSParav Pandit OCRDMA_CMD_RSVD1, 51fe2caefcSParav Pandit OCRDMA_CMD_ALLOC_LKEY, 52fe2caefcSParav Pandit OCRDMA_CMD_DEALLOC_LKEY, 53fe2caefcSParav Pandit OCRDMA_CMD_REGISTER_NSMR, 54fe2caefcSParav Pandit OCRDMA_CMD_REREGISTER_NSMR, 55fe2caefcSParav Pandit OCRDMA_CMD_REGISTER_NSMR_CONT, 56fe2caefcSParav Pandit OCRDMA_CMD_QUERY_NSMR, 57fe2caefcSParav Pandit OCRDMA_CMD_ALLOC_MW, 58fe2caefcSParav Pandit OCRDMA_CMD_QUERY_MW, 59fe2caefcSParav Pandit 60fe2caefcSParav Pandit OCRDMA_CMD_CREATE_SRQ, 61fe2caefcSParav Pandit OCRDMA_CMD_QUERY_SRQ, 62fe2caefcSParav Pandit OCRDMA_CMD_MODIFY_SRQ, 63fe2caefcSParav Pandit OCRDMA_CMD_DELETE_SRQ, 64fe2caefcSParav Pandit 65fe2caefcSParav Pandit OCRDMA_CMD_ATTACH_MCAST, 66fe2caefcSParav Pandit OCRDMA_CMD_DETACH_MCAST, 67fe2caefcSParav Pandit 68fe2caefcSParav Pandit OCRDMA_CMD_MAX 69fe2caefcSParav Pandit }; 70fe2caefcSParav Pandit 71fe2caefcSParav Pandit #define OCRDMA_SUBSYS_COMMON 1 72fe2caefcSParav Pandit enum { 73fe2caefcSParav Pandit OCRDMA_CMD_CREATE_CQ = 12, 74fe2caefcSParav Pandit OCRDMA_CMD_CREATE_EQ = 13, 75fe2caefcSParav Pandit OCRDMA_CMD_CREATE_MQ = 21, 76fe2caefcSParav Pandit OCRDMA_CMD_GET_FW_VER = 35, 77fe2caefcSParav Pandit OCRDMA_CMD_DELETE_MQ = 53, 78fe2caefcSParav Pandit OCRDMA_CMD_DELETE_CQ = 54, 79fe2caefcSParav Pandit OCRDMA_CMD_DELETE_EQ = 55, 80fe2caefcSParav Pandit OCRDMA_CMD_GET_FW_CONFIG = 58, 81fe2caefcSParav Pandit OCRDMA_CMD_CREATE_MQ_EXT = 90 82fe2caefcSParav Pandit }; 83fe2caefcSParav Pandit 84fe2caefcSParav Pandit enum { 85fe2caefcSParav Pandit QTYPE_EQ = 1, 86fe2caefcSParav Pandit QTYPE_CQ = 2, 87fe2caefcSParav Pandit QTYPE_MCCQ = 3 88fe2caefcSParav Pandit }; 89fe2caefcSParav Pandit 90fe2caefcSParav Pandit #define OCRDMA_MAX_SGID (8) 91fe2caefcSParav Pandit 92fe2caefcSParav Pandit #define OCRDMA_MAX_QP 2048 93fe2caefcSParav Pandit #define OCRDMA_MAX_CQ 2048 94fe2caefcSParav Pandit 95fe2caefcSParav Pandit enum { 96fe2caefcSParav Pandit OCRDMA_DB_RQ_OFFSET = 0xE0, 97fe2caefcSParav Pandit OCRDMA_DB_GEN2_RQ1_OFFSET = 0x100, 98fe2caefcSParav Pandit OCRDMA_DB_GEN2_RQ2_OFFSET = 0xC0, 99fe2caefcSParav Pandit OCRDMA_DB_SQ_OFFSET = 0x60, 100fe2caefcSParav Pandit OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0, 101fe2caefcSParav Pandit OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET, 102fe2caefcSParav Pandit OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ1_OFFSET, 103fe2caefcSParav Pandit OCRDMA_DB_CQ_OFFSET = 0x120, 104fe2caefcSParav Pandit OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET, 105fe2caefcSParav Pandit OCRDMA_DB_MQ_OFFSET = 0x140 106fe2caefcSParav Pandit }; 107fe2caefcSParav Pandit 108fe2caefcSParav Pandit #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 109fe2caefcSParav Pandit #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */ 110fe2caefcSParav Pandit /* qid #2 msbits at 12-11 */ 111fe2caefcSParav Pandit #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1 112fe2caefcSParav Pandit #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 113fe2caefcSParav Pandit /* Rearm bit */ 114fe2caefcSParav Pandit #define OCRDMA_DB_CQ_REARM_SHIFT (29) /* bit 29 */ 115fe2caefcSParav Pandit /* solicited bit */ 116fe2caefcSParav Pandit #define OCRDMA_DB_CQ_SOLICIT_SHIFT (31) /* bit 31 */ 117fe2caefcSParav Pandit 118fe2caefcSParav Pandit #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */ 119fe2caefcSParav Pandit #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 120fe2caefcSParav Pandit #define OCRDMA_EQ_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 at 11-15 */ 121fe2caefcSParav Pandit 122fe2caefcSParav Pandit /* Clear the interrupt for this eq */ 123fe2caefcSParav Pandit #define OCRDMA_EQ_CLR_SHIFT (9) /* bit 9 */ 124fe2caefcSParav Pandit /* Must be 1 */ 125fe2caefcSParav Pandit #define OCRDMA_EQ_TYPE_SHIFT (10) /* bit 10 */ 126fe2caefcSParav Pandit /* Number of event entries processed */ 127fe2caefcSParav Pandit #define OCRDMA_NUM_EQE_SHIFT (16) /* bits 16 - 28 */ 128fe2caefcSParav Pandit /* Rearm bit */ 129fe2caefcSParav Pandit #define OCRDMA_REARM_SHIFT (29) /* bit 29 */ 130fe2caefcSParav Pandit 131fe2caefcSParav Pandit #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */ 132fe2caefcSParav Pandit /* Number of entries posted */ 133fe2caefcSParav Pandit #define OCRDMA_MQ_NUM_MQE_SHIFT (16) /* bits 16 - 29 */ 134fe2caefcSParav Pandit 135fe2caefcSParav Pandit #define OCRDMA_MIN_HPAGE_SIZE (4096) 136fe2caefcSParav Pandit 137fe2caefcSParav Pandit #define OCRDMA_MIN_Q_PAGE_SIZE (4096) 138fe2caefcSParav Pandit #define OCRDMA_MAX_Q_PAGES (8) 139fe2caefcSParav Pandit 140fe2caefcSParav Pandit /* 141fe2caefcSParav Pandit # 0: 4K Bytes 142fe2caefcSParav Pandit # 1: 8K Bytes 143fe2caefcSParav Pandit # 2: 16K Bytes 144fe2caefcSParav Pandit # 3: 32K Bytes 145fe2caefcSParav Pandit # 4: 64K Bytes 146fe2caefcSParav Pandit */ 147fe2caefcSParav Pandit #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (5) 148fe2caefcSParav Pandit #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES) 149fe2caefcSParav Pandit 150fe2caefcSParav Pandit #define MAX_OCRDMA_QP_PAGES (8) 151fe2caefcSParav Pandit #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE) 152fe2caefcSParav Pandit 153fe2caefcSParav Pandit #define OCRDMA_CREATE_CQ_MAX_PAGES (4) 154fe2caefcSParav Pandit #define OCRDMA_DPP_CQE_SIZE (4) 155fe2caefcSParav Pandit 156fe2caefcSParav Pandit #define OCRDMA_GEN2_MAX_CQE 1024 157fe2caefcSParav Pandit #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096 158fe2caefcSParav Pandit #define OCRDMA_GEN2_WQE_SIZE 256 159fe2caefcSParav Pandit #define OCRDMA_MAX_CQE 4095 160fe2caefcSParav Pandit #define OCRDMA_CQ_PAGE_SIZE 16384 161fe2caefcSParav Pandit #define OCRDMA_WQE_SIZE 128 162fe2caefcSParav Pandit #define OCRDMA_WQE_STRIDE 8 163fe2caefcSParav Pandit #define OCRDMA_WQE_ALIGN_BYTES 16 164fe2caefcSParav Pandit 165fe2caefcSParav Pandit #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES 166fe2caefcSParav Pandit 167fe2caefcSParav Pandit enum { 168fe2caefcSParav Pandit OCRDMA_MCH_OPCODE_SHIFT = 0, 169fe2caefcSParav Pandit OCRDMA_MCH_OPCODE_MASK = 0xFF, 170fe2caefcSParav Pandit OCRDMA_MCH_SUBSYS_SHIFT = 8, 171fe2caefcSParav Pandit OCRDMA_MCH_SUBSYS_MASK = 0xFF00 172fe2caefcSParav Pandit }; 173fe2caefcSParav Pandit 174fe2caefcSParav Pandit /* mailbox cmd header */ 175fe2caefcSParav Pandit struct ocrdma_mbx_hdr { 176fe2caefcSParav Pandit u32 subsys_op; 177fe2caefcSParav Pandit u32 timeout; /* in seconds */ 178fe2caefcSParav Pandit u32 cmd_len; 179fe2caefcSParav Pandit u32 rsvd_version; 180fe2caefcSParav Pandit } __packed; 181fe2caefcSParav Pandit 182fe2caefcSParav Pandit enum { 183fe2caefcSParav Pandit OCRDMA_MBX_RSP_OPCODE_SHIFT = 0, 184fe2caefcSParav Pandit OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF, 185fe2caefcSParav Pandit OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8, 186fe2caefcSParav Pandit OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT, 187fe2caefcSParav Pandit 188fe2caefcSParav Pandit OCRDMA_MBX_RSP_STATUS_SHIFT = 0, 189fe2caefcSParav Pandit OCRDMA_MBX_RSP_STATUS_MASK = 0xFF, 190fe2caefcSParav Pandit OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8, 191fe2caefcSParav Pandit OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT 192fe2caefcSParav Pandit }; 193fe2caefcSParav Pandit 194fe2caefcSParav Pandit /* mailbox cmd response */ 195fe2caefcSParav Pandit struct ocrdma_mbx_rsp { 196fe2caefcSParav Pandit u32 subsys_op; 197fe2caefcSParav Pandit u32 status; 198fe2caefcSParav Pandit u32 rsp_len; 199fe2caefcSParav Pandit u32 add_rsp_len; 200fe2caefcSParav Pandit } __packed; 201fe2caefcSParav Pandit 202fe2caefcSParav Pandit enum { 203fe2caefcSParav Pandit OCRDMA_MQE_EMBEDDED = 1, 204fe2caefcSParav Pandit OCRDMA_MQE_NONEMBEDDED = 0 205fe2caefcSParav Pandit }; 206fe2caefcSParav Pandit 207fe2caefcSParav Pandit struct ocrdma_mqe_sge { 208fe2caefcSParav Pandit u32 pa_lo; 209fe2caefcSParav Pandit u32 pa_hi; 210fe2caefcSParav Pandit u32 len; 211fe2caefcSParav Pandit } __packed; 212fe2caefcSParav Pandit 213fe2caefcSParav Pandit enum { 214fe2caefcSParav Pandit OCRDMA_MQE_HDR_EMB_SHIFT = 0, 215fe2caefcSParav Pandit OCRDMA_MQE_HDR_EMB_MASK = Bit(0), 216fe2caefcSParav Pandit OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3, 217fe2caefcSParav Pandit OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT, 218fe2caefcSParav Pandit OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24, 219fe2caefcSParav Pandit OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT 220fe2caefcSParav Pandit }; 221fe2caefcSParav Pandit 222fe2caefcSParav Pandit struct ocrdma_mqe_hdr { 223fe2caefcSParav Pandit u32 spcl_sge_cnt_emb; 224fe2caefcSParav Pandit u32 pyld_len; 225fe2caefcSParav Pandit u32 tag_lo; 226fe2caefcSParav Pandit u32 tag_hi; 227fe2caefcSParav Pandit u32 rsvd3; 228fe2caefcSParav Pandit } __packed; 229fe2caefcSParav Pandit 230fe2caefcSParav Pandit struct ocrdma_mqe_emb_cmd { 231fe2caefcSParav Pandit struct ocrdma_mbx_hdr mch; 232fe2caefcSParav Pandit u8 pyld[220]; 233fe2caefcSParav Pandit } __packed; 234fe2caefcSParav Pandit 235fe2caefcSParav Pandit struct ocrdma_mqe { 236fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 237fe2caefcSParav Pandit union { 238fe2caefcSParav Pandit struct ocrdma_mqe_emb_cmd emb_req; 239fe2caefcSParav Pandit struct { 240fe2caefcSParav Pandit struct ocrdma_mqe_sge sge[19]; 241fe2caefcSParav Pandit } nonemb_req; 242fe2caefcSParav Pandit u8 cmd[236]; 243fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 244fe2caefcSParav Pandit } u; 245fe2caefcSParav Pandit } __packed; 246fe2caefcSParav Pandit 247fe2caefcSParav Pandit #define OCRDMA_EQ_LEN 4096 248fe2caefcSParav Pandit #define OCRDMA_MQ_CQ_LEN 256 249fe2caefcSParav Pandit #define OCRDMA_MQ_LEN 128 250fe2caefcSParav Pandit 251fe2caefcSParav Pandit #define PAGE_SHIFT_4K 12 252fe2caefcSParav Pandit #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 253fe2caefcSParav Pandit 254fe2caefcSParav Pandit /* Returns number of pages spanned by the data starting at the given addr */ 255fe2caefcSParav Pandit #define PAGES_4K_SPANNED(_address, size) \ 256fe2caefcSParav Pandit ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 257fe2caefcSParav Pandit (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 258fe2caefcSParav Pandit 259fe2caefcSParav Pandit struct ocrdma_delete_q_req { 260fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 261fe2caefcSParav Pandit u32 id; 262fe2caefcSParav Pandit } __packed; 263fe2caefcSParav Pandit 264fe2caefcSParav Pandit struct ocrdma_pa { 265fe2caefcSParav Pandit u32 lo; 266fe2caefcSParav Pandit u32 hi; 267fe2caefcSParav Pandit } __packed; 268fe2caefcSParav Pandit 269fe2caefcSParav Pandit #define MAX_OCRDMA_EQ_PAGES (8) 270fe2caefcSParav Pandit struct ocrdma_create_eq_req { 271fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 272fe2caefcSParav Pandit u32 num_pages; 273fe2caefcSParav Pandit u32 valid; 274fe2caefcSParav Pandit u32 cnt; 275fe2caefcSParav Pandit u32 delay; 276fe2caefcSParav Pandit u32 rsvd; 277fe2caefcSParav Pandit struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES]; 278fe2caefcSParav Pandit } __packed; 279fe2caefcSParav Pandit 280fe2caefcSParav Pandit enum { 281fe2caefcSParav Pandit OCRDMA_CREATE_EQ_VALID = Bit(29), 282fe2caefcSParav Pandit OCRDMA_CREATE_EQ_CNT_SHIFT = 26, 283fe2caefcSParav Pandit OCRDMA_CREATE_CQ_DELAY_SHIFT = 13, 284fe2caefcSParav Pandit }; 285fe2caefcSParav Pandit 286fe2caefcSParav Pandit struct ocrdma_create_eq_rsp { 287fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 288fe2caefcSParav Pandit u32 vector_eqid; 289fe2caefcSParav Pandit }; 290fe2caefcSParav Pandit 291fe2caefcSParav Pandit #define OCRDMA_EQ_MINOR_OTHER (0x1) 292fe2caefcSParav Pandit 293fe2caefcSParav Pandit enum { 294fe2caefcSParav Pandit OCRDMA_MCQE_STATUS_SHIFT = 0, 295fe2caefcSParav Pandit OCRDMA_MCQE_STATUS_MASK = 0xFFFF, 296fe2caefcSParav Pandit OCRDMA_MCQE_ESTATUS_SHIFT = 16, 297fe2caefcSParav Pandit OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT, 298fe2caefcSParav Pandit OCRDMA_MCQE_CONS_SHIFT = 27, 299fe2caefcSParav Pandit OCRDMA_MCQE_CONS_MASK = Bit(27), 300fe2caefcSParav Pandit OCRDMA_MCQE_CMPL_SHIFT = 28, 301fe2caefcSParav Pandit OCRDMA_MCQE_CMPL_MASK = Bit(28), 302fe2caefcSParav Pandit OCRDMA_MCQE_AE_SHIFT = 30, 303fe2caefcSParav Pandit OCRDMA_MCQE_AE_MASK = Bit(30), 304fe2caefcSParav Pandit OCRDMA_MCQE_VALID_SHIFT = 31, 305fe2caefcSParav Pandit OCRDMA_MCQE_VALID_MASK = Bit(31) 306fe2caefcSParav Pandit }; 307fe2caefcSParav Pandit 308fe2caefcSParav Pandit struct ocrdma_mcqe { 309fe2caefcSParav Pandit u32 status; 310fe2caefcSParav Pandit u32 tag_lo; 311fe2caefcSParav Pandit u32 tag_hi; 312fe2caefcSParav Pandit u32 valid_ae_cmpl_cons; 313fe2caefcSParav Pandit } __packed; 314fe2caefcSParav Pandit 315fe2caefcSParav Pandit enum { 316fe2caefcSParav Pandit OCRDMA_AE_MCQE_QPVALID = Bit(31), 317fe2caefcSParav Pandit OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF, 318fe2caefcSParav Pandit 319fe2caefcSParav Pandit OCRDMA_AE_MCQE_CQVALID = Bit(31), 320fe2caefcSParav Pandit OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF, 321fe2caefcSParav Pandit OCRDMA_AE_MCQE_VALID = Bit(31), 322fe2caefcSParav Pandit OCRDMA_AE_MCQE_AE = Bit(30), 323fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16, 324fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_TYPE_MASK = 325fe2caefcSParav Pandit 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT, 326fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8, 327fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_CODE_MASK = 328fe2caefcSParav Pandit 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT 329fe2caefcSParav Pandit }; 330fe2caefcSParav Pandit struct ocrdma_ae_mcqe { 331fe2caefcSParav Pandit u32 qpvalid_qpid; 332fe2caefcSParav Pandit u32 cqvalid_cqid; 333fe2caefcSParav Pandit u32 evt_tag; 334fe2caefcSParav Pandit u32 valid_ae_event; 335fe2caefcSParav Pandit } __packed; 336fe2caefcSParav Pandit 337fe2caefcSParav Pandit enum { 338fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16, 339fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF << 340fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT, 341fe2caefcSParav Pandit 342fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8, 343fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF << 344fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT, 345fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16, 346fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF << 347fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT, 348fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30, 349fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30), 350fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31, 351fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31) 352fe2caefcSParav Pandit }; 353fe2caefcSParav Pandit 354fe2caefcSParav Pandit struct ocrdma_ae_mpa_mcqe { 355fe2caefcSParav Pandit u32 req_id; 356fe2caefcSParav Pandit u32 w1; 357fe2caefcSParav Pandit u32 w2; 358fe2caefcSParav Pandit u32 valid_ae_event; 359fe2caefcSParav Pandit } __packed; 360fe2caefcSParav Pandit 361fe2caefcSParav Pandit enum { 362fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0, 363fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF, 364fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16, 365fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF << 366fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_QP_ID_SHIFT, 367fe2caefcSParav Pandit 368fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8, 369fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF << 370fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT, 371fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16, 372fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF << 373fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT, 374fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30, 375fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30), 376fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31, 377fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31) 378fe2caefcSParav Pandit }; 379fe2caefcSParav Pandit 380fe2caefcSParav Pandit struct ocrdma_ae_qp_mcqe { 381fe2caefcSParav Pandit u32 qp_id_state; 382fe2caefcSParav Pandit u32 w1; 383fe2caefcSParav Pandit u32 w2; 384fe2caefcSParav Pandit u32 valid_ae_event; 385fe2caefcSParav Pandit } __packed; 386fe2caefcSParav Pandit 387fe2caefcSParav Pandit #define OCRDMA_ASYNC_EVE_CODE 0x14 388fe2caefcSParav Pandit 389fe2caefcSParav Pandit enum OCRDMA_ASYNC_EVENT_TYPE { 390fe2caefcSParav Pandit OCRDMA_CQ_ERROR = 0x00, 391fe2caefcSParav Pandit OCRDMA_CQ_OVERRUN_ERROR = 0x01, 392fe2caefcSParav Pandit OCRDMA_CQ_QPCAT_ERROR = 0x02, 393fe2caefcSParav Pandit OCRDMA_QP_ACCESS_ERROR = 0x03, 394fe2caefcSParav Pandit OCRDMA_QP_COMM_EST_EVENT = 0x04, 395fe2caefcSParav Pandit OCRDMA_SQ_DRAINED_EVENT = 0x05, 396fe2caefcSParav Pandit OCRDMA_DEVICE_FATAL_EVENT = 0x08, 397fe2caefcSParav Pandit OCRDMA_SRQCAT_ERROR = 0x0E, 398fe2caefcSParav Pandit OCRDMA_SRQ_LIMIT_EVENT = 0x0F, 399fe2caefcSParav Pandit OCRDMA_QP_LAST_WQE_EVENT = 0x10 400fe2caefcSParav Pandit }; 401fe2caefcSParav Pandit 402fe2caefcSParav Pandit /* mailbox command request and responses */ 403fe2caefcSParav Pandit enum { 404fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2, 405fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2), 406fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3, 407fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3), 408fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8, 409fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF << 410fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT, 411fe2caefcSParav Pandit 412fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16, 413fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF << 414fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT, 415fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8, 416fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF << 417fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT, 418fe2caefcSParav Pandit 419fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0, 420fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF, 421634c5796SMahesh Vardhamanaiah OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16, 422634c5796SMahesh Vardhamanaiah OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF << 423634c5796SMahesh Vardhamanaiah OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT, 424fe2caefcSParav Pandit 425fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0, 426fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF, 427fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16, 428fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF << 429fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT, 430fe2caefcSParav Pandit 431fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24, 432fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF << 433fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET, 434fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16, 435fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF << 436fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET, 437fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0, 438fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF << 439fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET, 440fe2caefcSParav Pandit 441fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16, 442fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF << 443fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET, 444fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0, 445fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF << 446fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET, 447fe2caefcSParav Pandit 448fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16, 449fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF << 450fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET, 451fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0, 452fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF << 453fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET, 454fe2caefcSParav Pandit 455fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0, 456fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF << 457fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET, 458fe2caefcSParav Pandit 459fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16, 460fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF << 461fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET, 462fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0, 463fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF << 46407bb5424SMahesh Vardhamanaiah OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET, 465fe2caefcSParav Pandit 466fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16, 467fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF << 468fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET, 469fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0, 470fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF << 471fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET, 472fe2caefcSParav Pandit 473fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16, 474fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF << 475fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET, 476fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0, 477fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF << 478fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET, 479fe2caefcSParav Pandit }; 480fe2caefcSParav Pandit 481fe2caefcSParav Pandit struct ocrdma_mbx_query_config { 482fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 483fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 484fe2caefcSParav Pandit u32 qp_srq_cq_ird_ord; 485fe2caefcSParav Pandit u32 max_pd_ca_ack_delay; 486fe2caefcSParav Pandit u32 max_write_send_sge; 487fe2caefcSParav Pandit u32 max_ird_ord_per_qp; 488fe2caefcSParav Pandit u32 max_shared_ird_ord; 489fe2caefcSParav Pandit u32 max_mr; 490fe2caefcSParav Pandit u64 max_mr_size; 491fe2caefcSParav Pandit u32 max_num_mr_pbl; 492fe2caefcSParav Pandit u32 max_mw; 493fe2caefcSParav Pandit u32 max_fmr; 494fe2caefcSParav Pandit u32 max_pages_per_frmr; 495fe2caefcSParav Pandit u32 max_mcast_group; 496fe2caefcSParav Pandit u32 max_mcast_qp_attach; 497fe2caefcSParav Pandit u32 max_total_mcast_qp_attach; 498fe2caefcSParav Pandit u32 wqe_rqe_stride_max_dpp_cqs; 499fe2caefcSParav Pandit u32 max_srq_rpir_qps; 500fe2caefcSParav Pandit u32 max_dpp_pds_credits; 501fe2caefcSParav Pandit u32 max_dpp_credits_pds_per_pd; 502fe2caefcSParav Pandit u32 max_wqes_rqes_per_q; 503fe2caefcSParav Pandit u32 max_cq_cqes_per_cq; 504fe2caefcSParav Pandit u32 max_srq_rqe_sge; 505fe2caefcSParav Pandit } __packed; 506fe2caefcSParav Pandit 507fe2caefcSParav Pandit struct ocrdma_fw_ver_rsp { 508fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 509fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 510fe2caefcSParav Pandit 511fe2caefcSParav Pandit u8 running_ver[32]; 512fe2caefcSParav Pandit } __packed; 513fe2caefcSParav Pandit 514fe2caefcSParav Pandit struct ocrdma_fw_conf_rsp { 515fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 516fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 517fe2caefcSParav Pandit 518fe2caefcSParav Pandit u32 config_num; 519fe2caefcSParav Pandit u32 asic_revision; 520fe2caefcSParav Pandit u32 phy_port; 521fe2caefcSParav Pandit u32 fn_mode; 522fe2caefcSParav Pandit struct { 523fe2caefcSParav Pandit u32 mode; 524fe2caefcSParav Pandit u32 nic_wqid_base; 525fe2caefcSParav Pandit u32 nic_wq_tot; 526fe2caefcSParav Pandit u32 prot_wqid_base; 527fe2caefcSParav Pandit u32 prot_wq_tot; 528fe2caefcSParav Pandit u32 prot_rqid_base; 529fe2caefcSParav Pandit u32 prot_rqid_tot; 530fe2caefcSParav Pandit u32 rsvd[6]; 531fe2caefcSParav Pandit } ulp[2]; 532fe2caefcSParav Pandit u32 fn_capabilities; 533fe2caefcSParav Pandit u32 rsvd1; 534fe2caefcSParav Pandit u32 rsvd2; 535fe2caefcSParav Pandit u32 base_eqid; 536fe2caefcSParav Pandit u32 max_eq; 537fe2caefcSParav Pandit 538fe2caefcSParav Pandit } __packed; 539fe2caefcSParav Pandit 540fe2caefcSParav Pandit enum { 541fe2caefcSParav Pandit OCRDMA_FN_MODE_RDMA = 0x4 542fe2caefcSParav Pandit }; 543fe2caefcSParav Pandit 544fe2caefcSParav Pandit enum { 545fe2caefcSParav Pandit OCRDMA_CREATE_CQ_VER2 = 2, 546fe2caefcSParav Pandit 547fe2caefcSParav Pandit OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF, 548fe2caefcSParav Pandit OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16, 549fe2caefcSParav Pandit OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF, 550fe2caefcSParav Pandit 551fe2caefcSParav Pandit OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12, 552fe2caefcSParav Pandit OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12), 553fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14), 554fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15), 555fe2caefcSParav Pandit 556fe2caefcSParav Pandit OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF, 557fe2caefcSParav Pandit OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF 558fe2caefcSParav Pandit }; 559fe2caefcSParav Pandit 560fe2caefcSParav Pandit enum { 561fe2caefcSParav Pandit OCRDMA_CREATE_CQ_VER0 = 0, 562fe2caefcSParav Pandit OCRDMA_CREATE_CQ_DPP = 1, 563fe2caefcSParav Pandit OCRDMA_CREATE_CQ_TYPE_SHIFT = 24, 564fe2caefcSParav Pandit OCRDMA_CREATE_CQ_EQID_SHIFT = 22, 565fe2caefcSParav Pandit 566fe2caefcSParav Pandit OCRDMA_CREATE_CQ_CNT_SHIFT = 27, 567fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29), 568fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31), 569fe2caefcSParav Pandit OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID | 570fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_EVENTABLE | 571fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_NODELAY 572fe2caefcSParav Pandit }; 573fe2caefcSParav Pandit 574fe2caefcSParav Pandit struct ocrdma_create_cq_cmd { 575fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 576fe2caefcSParav Pandit u32 pgsz_pgcnt; 577fe2caefcSParav Pandit u32 ev_cnt_flags; 578fe2caefcSParav Pandit u32 eqn; 579fe2caefcSParav Pandit u32 cqe_count; 580fe2caefcSParav Pandit u32 rsvd6; 581fe2caefcSParav Pandit struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES]; 582fe2caefcSParav Pandit }; 583fe2caefcSParav Pandit 584fe2caefcSParav Pandit struct ocrdma_create_cq { 585fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 586fe2caefcSParav Pandit struct ocrdma_create_cq_cmd cmd; 587fe2caefcSParav Pandit } __packed; 588fe2caefcSParav Pandit 589fe2caefcSParav Pandit enum { 590fe2caefcSParav Pandit OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF 591fe2caefcSParav Pandit }; 592fe2caefcSParav Pandit 593fe2caefcSParav Pandit struct ocrdma_create_cq_cmd_rsp { 594fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 595fe2caefcSParav Pandit u32 cq_id; 596fe2caefcSParav Pandit } __packed; 597fe2caefcSParav Pandit 598fe2caefcSParav Pandit struct ocrdma_create_cq_rsp { 599fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 600fe2caefcSParav Pandit struct ocrdma_create_cq_cmd_rsp rsp; 601fe2caefcSParav Pandit } __packed; 602fe2caefcSParav Pandit 603fe2caefcSParav Pandit enum { 604fe2caefcSParav Pandit OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22, 605fe2caefcSParav Pandit OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16, 606fe2caefcSParav Pandit OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16, 607fe2caefcSParav Pandit OCRDMA_CREATE_MQ_VALID = Bit(31), 608fe2caefcSParav Pandit OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0) 609fe2caefcSParav Pandit }; 610fe2caefcSParav Pandit 611fe2caefcSParav Pandit struct ocrdma_create_mq_v0 { 612fe2caefcSParav Pandit u32 pages; 613fe2caefcSParav Pandit u32 cqid_ringsize; 614fe2caefcSParav Pandit u32 valid; 615fe2caefcSParav Pandit u32 async_cqid_valid; 616fe2caefcSParav Pandit u32 rsvd; 617fe2caefcSParav Pandit struct ocrdma_pa pa[8]; 618fe2caefcSParav Pandit } __packed; 619fe2caefcSParav Pandit 620fe2caefcSParav Pandit struct ocrdma_create_mq_v1 { 621fe2caefcSParav Pandit u32 cqid_pages; 622fe2caefcSParav Pandit u32 async_event_bitmap; 623fe2caefcSParav Pandit u32 async_cqid_ringsize; 624fe2caefcSParav Pandit u32 valid; 625fe2caefcSParav Pandit u32 async_cqid_valid; 626fe2caefcSParav Pandit u32 rsvd; 627fe2caefcSParav Pandit struct ocrdma_pa pa[8]; 628fe2caefcSParav Pandit } __packed; 629fe2caefcSParav Pandit 630fe2caefcSParav Pandit struct ocrdma_create_mq_req { 631fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 632fe2caefcSParav Pandit union { 633fe2caefcSParav Pandit struct ocrdma_create_mq_v0 v0; 634fe2caefcSParav Pandit struct ocrdma_create_mq_v1 v1; 635fe2caefcSParav Pandit }; 636fe2caefcSParav Pandit } __packed; 637fe2caefcSParav Pandit 638fe2caefcSParav Pandit struct ocrdma_create_mq_rsp { 639fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 640fe2caefcSParav Pandit u32 id; 641fe2caefcSParav Pandit } __packed; 642fe2caefcSParav Pandit 643fe2caefcSParav Pandit enum { 644fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_SHIFT = 0, 645fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF, 646fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16, 647fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF << 648fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT 649fe2caefcSParav Pandit }; 650fe2caefcSParav Pandit 651fe2caefcSParav Pandit struct ocrdma_destroy_cq { 652fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 653fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 654fe2caefcSParav Pandit 655fe2caefcSParav Pandit u32 bypass_flush_qid; 656fe2caefcSParav Pandit } __packed; 657fe2caefcSParav Pandit 658fe2caefcSParav Pandit struct ocrdma_destroy_cq_rsp { 659fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 660fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 661fe2caefcSParav Pandit } __packed; 662fe2caefcSParav Pandit 663fe2caefcSParav Pandit enum { 664fe2caefcSParav Pandit OCRDMA_QPT_GSI = 1, 665fe2caefcSParav Pandit OCRDMA_QPT_RC = 2, 666fe2caefcSParav Pandit OCRDMA_QPT_UD = 4, 667fe2caefcSParav Pandit }; 668fe2caefcSParav Pandit 669fe2caefcSParav Pandit enum { 670fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0, 671fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF, 672fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16, 673fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19, 674fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29, 675fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29), 676fe2caefcSParav Pandit 677fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0, 678fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF, 679fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16, 680fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF << 681fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT, 682fe2caefcSParav Pandit 683fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0, 684fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF, 685fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16, 686fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF << 687fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT, 688fe2caefcSParav Pandit 689fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0, 690fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0), 691fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1, 692fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1), 693fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2, 694fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2), 695fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3, 696fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3), 697fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4, 698fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4), 699fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5, 700fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5), 701fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6, 702fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6), 703fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7, 704fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7), 705fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8, 706fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8), 707fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16, 708fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF << 709fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT, 710fe2caefcSParav Pandit 711fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0, 712fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF, 713fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16, 714fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF << 715fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT, 716fe2caefcSParav Pandit 717fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0, 718fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF, 719fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16, 720fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF << 721fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT, 722fe2caefcSParav Pandit 723fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0, 724fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF, 725fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16, 726fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF << 727fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT, 728fe2caefcSParav Pandit 729fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0, 730fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF, 731fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16, 732fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF << 733fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT, 734fe2caefcSParav Pandit 735fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0, 736fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF, 737fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16, 738fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF << 739fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT 740fe2caefcSParav Pandit }; 741fe2caefcSParav Pandit 742fe2caefcSParav Pandit enum { 743fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16, 744fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1 745fe2caefcSParav Pandit }; 746fe2caefcSParav Pandit 747fe2caefcSParav Pandit #define MAX_OCRDMA_IRD_PAGES 4 748fe2caefcSParav Pandit 749fe2caefcSParav Pandit enum ocrdma_qp_flags { 750fe2caefcSParav Pandit OCRDMA_QP_MW_BIND = 1, 751fe2caefcSParav Pandit OCRDMA_QP_LKEY0 = (1 << 1), 752fe2caefcSParav Pandit OCRDMA_QP_FAST_REG = (1 << 2), 753fe2caefcSParav Pandit OCRDMA_QP_INB_RD = (1 << 6), 754fe2caefcSParav Pandit OCRDMA_QP_INB_WR = (1 << 7), 755fe2caefcSParav Pandit }; 756fe2caefcSParav Pandit 757fe2caefcSParav Pandit enum ocrdma_qp_state { 758fe2caefcSParav Pandit OCRDMA_QPS_RST = 0, 759fe2caefcSParav Pandit OCRDMA_QPS_INIT = 1, 760fe2caefcSParav Pandit OCRDMA_QPS_RTR = 2, 761fe2caefcSParav Pandit OCRDMA_QPS_RTS = 3, 762fe2caefcSParav Pandit OCRDMA_QPS_SQE = 4, 763fe2caefcSParav Pandit OCRDMA_QPS_SQ_DRAINING = 5, 764fe2caefcSParav Pandit OCRDMA_QPS_ERR = 6, 765fe2caefcSParav Pandit OCRDMA_QPS_SQD = 7 766fe2caefcSParav Pandit }; 767fe2caefcSParav Pandit 768fe2caefcSParav Pandit struct ocrdma_create_qp_req { 769fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 770fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 771fe2caefcSParav Pandit 772fe2caefcSParav Pandit u32 type_pgsz_pdn; 773fe2caefcSParav Pandit u32 max_wqe_rqe; 774fe2caefcSParav Pandit u32 max_sge_send_write; 775fe2caefcSParav Pandit u32 max_sge_recv_flags; 776fe2caefcSParav Pandit u32 max_ord_ird; 777fe2caefcSParav Pandit u32 num_wq_rq_pages; 778fe2caefcSParav Pandit u32 wqe_rqe_size; 779fe2caefcSParav Pandit u32 wq_rq_cqid; 780fe2caefcSParav Pandit struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES]; 781fe2caefcSParav Pandit struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES]; 782fe2caefcSParav Pandit u32 dpp_credits_cqid; 783fe2caefcSParav Pandit u32 rpir_lkey; 784fe2caefcSParav Pandit struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES]; 785fe2caefcSParav Pandit } __packed; 786fe2caefcSParav Pandit 787fe2caefcSParav Pandit enum { 788fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0, 789fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF, 790fe2caefcSParav Pandit 791fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0, 792fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF, 793fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16, 794fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF << 795fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT, 796fe2caefcSParav Pandit 797fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0, 798fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF, 799fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16, 800fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF << 801fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT, 802fe2caefcSParav Pandit 803fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16, 804fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF << 805fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT, 806fe2caefcSParav Pandit 807fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0, 808fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF, 809fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16, 810fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF << 811fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT, 812fe2caefcSParav Pandit 813fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0, 814fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF, 815fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16, 816fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF << 817fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT, 818fe2caefcSParav Pandit 819fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0), 820fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1, 821fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF << 822fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT, 823fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16, 824fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF << 825fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT, 826fe2caefcSParav Pandit }; 827fe2caefcSParav Pandit 828fe2caefcSParav Pandit struct ocrdma_create_qp_rsp { 829fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 830fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 831fe2caefcSParav Pandit 832fe2caefcSParav Pandit u32 qp_id; 833fe2caefcSParav Pandit u32 max_wqe_rqe; 834fe2caefcSParav Pandit u32 max_sge_send_write; 835fe2caefcSParav Pandit u32 max_sge_recv; 836fe2caefcSParav Pandit u32 max_ord_ird; 837fe2caefcSParav Pandit u32 sq_rq_id; 838fe2caefcSParav Pandit u32 dpp_response; 839fe2caefcSParav Pandit } __packed; 840fe2caefcSParav Pandit 841fe2caefcSParav Pandit struct ocrdma_destroy_qp { 842fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 843fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 844fe2caefcSParav Pandit u32 qp_id; 845fe2caefcSParav Pandit } __packed; 846fe2caefcSParav Pandit 847fe2caefcSParav Pandit struct ocrdma_destroy_qp_rsp { 848fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 849fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 850fe2caefcSParav Pandit } __packed; 851fe2caefcSParav Pandit 852fe2caefcSParav Pandit enum { 853fe2caefcSParav Pandit OCRDMA_MODIFY_QP_ID_SHIFT = 0, 854fe2caefcSParav Pandit OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF, 855fe2caefcSParav Pandit 856fe2caefcSParav Pandit OCRDMA_QP_PARA_QPS_VALID = Bit(0), 857fe2caefcSParav Pandit OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1), 858fe2caefcSParav Pandit OCRDMA_QP_PARA_PKEY_VALID = Bit(2), 859fe2caefcSParav Pandit OCRDMA_QP_PARA_QKEY_VALID = Bit(3), 860fe2caefcSParav Pandit OCRDMA_QP_PARA_PMTU_VALID = Bit(4), 861fe2caefcSParav Pandit OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5), 862fe2caefcSParav Pandit OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6), 863fe2caefcSParav Pandit OCRDMA_QP_PARA_RRC_VALID = Bit(7), 864fe2caefcSParav Pandit OCRDMA_QP_PARA_RQPSN_VALID = Bit(8), 865fe2caefcSParav Pandit OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9), 866fe2caefcSParav Pandit OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10), 867fe2caefcSParav Pandit OCRDMA_QP_PARA_RNT_VALID = Bit(11), 868fe2caefcSParav Pandit OCRDMA_QP_PARA_SQPSN_VALID = Bit(12), 869fe2caefcSParav Pandit OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13), 870fe2caefcSParav Pandit OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14), 871fe2caefcSParav Pandit OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15), 872fe2caefcSParav Pandit OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16), 873fe2caefcSParav Pandit OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17), 874fe2caefcSParav Pandit OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18), 875fe2caefcSParav Pandit OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19), 876fe2caefcSParav Pandit OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20), 877fe2caefcSParav Pandit OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21), 878fe2caefcSParav Pandit OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22), 879fe2caefcSParav Pandit OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23), 880fe2caefcSParav Pandit OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24), 881fe2caefcSParav Pandit OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25), 882fe2caefcSParav Pandit OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26), 883fe2caefcSParav Pandit 884fe2caefcSParav Pandit OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0), 885fe2caefcSParav Pandit OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1), 886fe2caefcSParav Pandit OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2), 887fe2caefcSParav Pandit OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3) 888fe2caefcSParav Pandit }; 889fe2caefcSParav Pandit 890fe2caefcSParav Pandit enum { 891fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0, 892fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF, 893fe2caefcSParav Pandit 894fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0, 895fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF, 896fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16, 897fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF << 898fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_WQE_SHIFT, 899fe2caefcSParav Pandit 900fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0, 901fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF, 902fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16, 903fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF << 904fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT, 905fe2caefcSParav Pandit 906fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0), 907fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1), 908fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2), 909fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3), 910fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4), 911fe2caefcSParav Pandit OCRDMA_QP_PARAMS_STATE_SHIFT = 5, 912fe2caefcSParav Pandit OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7), 913fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8), 914fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9), 915fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16, 916fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF << 917fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT, 918fe2caefcSParav Pandit 919fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0, 920fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF, 921fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16, 922fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF << 923fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_ORD_SHIFT, 924fe2caefcSParav Pandit 925fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0, 926fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF, 927fe2caefcSParav Pandit OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16, 928fe2caefcSParav Pandit OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF << 929fe2caefcSParav Pandit OCRDMA_QP_PARAMS_WQ_CQID_SHIFT, 930fe2caefcSParav Pandit 931fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0, 932fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF, 933fe2caefcSParav Pandit OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24, 934fe2caefcSParav Pandit OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF << 935fe2caefcSParav Pandit OCRDMA_QP_PARAMS_HOP_LMT_SHIFT, 936fe2caefcSParav Pandit 937fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0, 938fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF, 939fe2caefcSParav Pandit OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24, 940fe2caefcSParav Pandit OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF << 941fe2caefcSParav Pandit OCRDMA_QP_PARAMS_TCLASS_SHIFT, 942fe2caefcSParav Pandit 943fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0, 944fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF, 945fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24, 946fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 << 947fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT, 948fe2caefcSParav Pandit OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27, 949fe2caefcSParav Pandit OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F << 950fe2caefcSParav Pandit OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT, 951fe2caefcSParav Pandit 952fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0, 953fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF, 954fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18, 955fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF << 956fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PATH_MTU_SHIFT, 957fe2caefcSParav Pandit 958fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0, 959fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF, 960fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SL_SHIFT = 20, 961fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SL_MASK = 0xF << 962fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SL_SHIFT, 963fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24, 964fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 << 965fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT, 966fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27, 967fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F << 968fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT, 969fe2caefcSParav Pandit 970fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0, 971fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF, 972fe2caefcSParav Pandit OCRDMA_QP_PARAMS_VLAN_SHIFT = 16, 973fe2caefcSParav Pandit OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF << 974fe2caefcSParav Pandit OCRDMA_QP_PARAMS_VLAN_SHIFT 975fe2caefcSParav Pandit }; 976fe2caefcSParav Pandit 977fe2caefcSParav Pandit struct ocrdma_qp_params { 978fe2caefcSParav Pandit u32 id; 979fe2caefcSParav Pandit u32 max_wqe_rqe; 980fe2caefcSParav Pandit u32 max_sge_send_write; 981fe2caefcSParav Pandit u32 max_sge_recv_flags; 982fe2caefcSParav Pandit u32 max_ord_ird; 983fe2caefcSParav Pandit u32 wq_rq_cqid; 984fe2caefcSParav Pandit u32 hop_lmt_rq_psn; 985fe2caefcSParav Pandit u32 tclass_sq_psn; 986fe2caefcSParav Pandit u32 ack_to_rnr_rtc_dest_qpn; 987fe2caefcSParav Pandit u32 path_mtu_pkey_indx; 988fe2caefcSParav Pandit u32 rnt_rc_sl_fl; 989fe2caefcSParav Pandit u8 sgid[16]; 990fe2caefcSParav Pandit u8 dgid[16]; 991fe2caefcSParav Pandit u32 dmac_b0_to_b3; 992fe2caefcSParav Pandit u32 vlan_dmac_b4_to_b5; 993fe2caefcSParav Pandit u32 qkey; 994fe2caefcSParav Pandit } __packed; 995fe2caefcSParav Pandit 996fe2caefcSParav Pandit 997fe2caefcSParav Pandit struct ocrdma_modify_qp { 998fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 999fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1000fe2caefcSParav Pandit 1001fe2caefcSParav Pandit struct ocrdma_qp_params params; 1002fe2caefcSParav Pandit u32 flags; 1003fe2caefcSParav Pandit u32 rdma_flags; 1004fe2caefcSParav Pandit u32 num_outstanding_atomic_rd; 1005fe2caefcSParav Pandit } __packed; 1006fe2caefcSParav Pandit 1007fe2caefcSParav Pandit enum { 1008fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0, 1009fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF, 1010fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16, 1011fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF << 1012fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT, 1013fe2caefcSParav Pandit 1014fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0, 1015fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF, 1016fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16, 1017fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF << 1018fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT 1019fe2caefcSParav Pandit }; 1020fe2caefcSParav Pandit struct ocrdma_modify_qp_rsp { 1021fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1022fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1023fe2caefcSParav Pandit 1024fe2caefcSParav Pandit u32 max_wqe_rqe; 1025fe2caefcSParav Pandit u32 max_ord_ird; 1026fe2caefcSParav Pandit } __packed; 1027fe2caefcSParav Pandit 1028fe2caefcSParav Pandit struct ocrdma_query_qp { 1029fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1030fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1031fe2caefcSParav Pandit 1032fe2caefcSParav Pandit #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0 1033fe2caefcSParav Pandit #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF 1034fe2caefcSParav Pandit u32 qp_id; 1035fe2caefcSParav Pandit } __packed; 1036fe2caefcSParav Pandit 1037fe2caefcSParav Pandit struct ocrdma_query_qp_rsp { 1038fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1039fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1040fe2caefcSParav Pandit struct ocrdma_qp_params params; 1041fe2caefcSParav Pandit } __packed; 1042fe2caefcSParav Pandit 1043fe2caefcSParav Pandit enum { 1044fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0, 1045fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF, 1046fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16, 1047fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 << 1048fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PG_SZ_SHIFT, 1049fe2caefcSParav Pandit 1050fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0, 1051fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16, 1052fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF << 1053fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT, 1054fe2caefcSParav Pandit 1055fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0, 1056fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF, 1057fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16, 1058fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF << 1059fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT 1060fe2caefcSParav Pandit }; 1061fe2caefcSParav Pandit 1062fe2caefcSParav Pandit struct ocrdma_create_srq { 1063fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1064fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1065fe2caefcSParav Pandit 1066fe2caefcSParav Pandit u32 pgsz_pdid; 1067fe2caefcSParav Pandit u32 max_sge_rqe; 1068fe2caefcSParav Pandit u32 pages_rqe_sz; 1069fe2caefcSParav Pandit struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES]; 1070fe2caefcSParav Pandit } __packed; 1071fe2caefcSParav Pandit 1072fe2caefcSParav Pandit enum { 1073fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0, 1074fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF, 1075fe2caefcSParav Pandit 1076fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0, 1077fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF, 1078fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16, 1079fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF << 1080fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT 1081fe2caefcSParav Pandit }; 1082fe2caefcSParav Pandit 1083fe2caefcSParav Pandit struct ocrdma_create_srq_rsp { 1084fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1085fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1086fe2caefcSParav Pandit 1087fe2caefcSParav Pandit u32 id; 1088fe2caefcSParav Pandit u32 max_sge_rqe_allocated; 1089fe2caefcSParav Pandit } __packed; 1090fe2caefcSParav Pandit 1091fe2caefcSParav Pandit enum { 1092fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_ID_SHIFT = 0, 1093fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF, 1094fe2caefcSParav Pandit 1095fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0, 1096fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF, 1097fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16, 1098fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF << 1099fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_LIMIT_SHIFT 1100fe2caefcSParav Pandit }; 1101fe2caefcSParav Pandit 1102fe2caefcSParav Pandit struct ocrdma_modify_srq { 1103fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1104fe2caefcSParav Pandit struct ocrdma_mbx_rsp rep; 1105fe2caefcSParav Pandit 1106fe2caefcSParav Pandit u32 id; 1107fe2caefcSParav Pandit u32 limit_max_rqe; 1108fe2caefcSParav Pandit } __packed; 1109fe2caefcSParav Pandit 1110fe2caefcSParav Pandit enum { 1111fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_ID_SHIFT = 0, 1112fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF 1113fe2caefcSParav Pandit }; 1114fe2caefcSParav Pandit 1115fe2caefcSParav Pandit struct ocrdma_query_srq { 1116fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1117fe2caefcSParav Pandit struct ocrdma_mbx_rsp req; 1118fe2caefcSParav Pandit 1119fe2caefcSParav Pandit u32 id; 1120fe2caefcSParav Pandit } __packed; 1121fe2caefcSParav Pandit 1122fe2caefcSParav Pandit enum { 1123fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0, 1124fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF, 1125fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16, 1126fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF << 1127fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT, 1128fe2caefcSParav Pandit 1129fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0, 1130fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF, 1131fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16, 1132fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF << 1133fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT 1134fe2caefcSParav Pandit }; 1135fe2caefcSParav Pandit 1136fe2caefcSParav Pandit struct ocrdma_query_srq_rsp { 1137fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1138fe2caefcSParav Pandit struct ocrdma_mbx_rsp req; 1139fe2caefcSParav Pandit 1140fe2caefcSParav Pandit u32 max_rqe_pdid; 1141fe2caefcSParav Pandit u32 srq_lmt_max_sge; 1142fe2caefcSParav Pandit } __packed; 1143fe2caefcSParav Pandit 1144fe2caefcSParav Pandit enum { 1145fe2caefcSParav Pandit OCRDMA_DESTROY_SRQ_ID_SHIFT = 0, 1146fe2caefcSParav Pandit OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF 1147fe2caefcSParav Pandit }; 1148fe2caefcSParav Pandit 1149fe2caefcSParav Pandit struct ocrdma_destroy_srq { 1150fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1151fe2caefcSParav Pandit struct ocrdma_mbx_rsp req; 1152fe2caefcSParav Pandit 1153fe2caefcSParav Pandit u32 id; 1154fe2caefcSParav Pandit } __packed; 1155fe2caefcSParav Pandit 1156fe2caefcSParav Pandit enum { 1157fe2caefcSParav Pandit OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16), 1158fe2caefcSParav Pandit OCRDMA_PD_MAX_DPP_ENABLED_QP = 8, 1159fe2caefcSParav Pandit OCRDMA_DPP_PAGE_SIZE = 4096 1160fe2caefcSParav Pandit }; 1161fe2caefcSParav Pandit 1162fe2caefcSParav Pandit struct ocrdma_alloc_pd { 1163fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1164fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1165fe2caefcSParav Pandit u32 enable_dpp_rsvd; 1166fe2caefcSParav Pandit } __packed; 1167fe2caefcSParav Pandit 1168fe2caefcSParav Pandit enum { 1169fe2caefcSParav Pandit OCRDMA_ALLOC_PD_RSP_DPP = Bit(16), 1170fe2caefcSParav Pandit OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20, 1171fe2caefcSParav Pandit OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF, 1172fe2caefcSParav Pandit }; 1173fe2caefcSParav Pandit 1174fe2caefcSParav Pandit struct ocrdma_alloc_pd_rsp { 1175fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1176fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1177fe2caefcSParav Pandit u32 dpp_page_pdid; 1178fe2caefcSParav Pandit } __packed; 1179fe2caefcSParav Pandit 1180fe2caefcSParav Pandit struct ocrdma_dealloc_pd { 1181fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1182fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1183fe2caefcSParav Pandit u32 id; 1184fe2caefcSParav Pandit } __packed; 1185fe2caefcSParav Pandit 1186fe2caefcSParav Pandit struct ocrdma_dealloc_pd_rsp { 1187fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1188fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1189fe2caefcSParav Pandit } __packed; 1190fe2caefcSParav Pandit 1191fe2caefcSParav Pandit enum { 1192fe2caefcSParav Pandit OCRDMA_ADDR_CHECK_ENABLE = 1, 1193fe2caefcSParav Pandit OCRDMA_ADDR_CHECK_DISABLE = 0 1194fe2caefcSParav Pandit }; 1195fe2caefcSParav Pandit 1196fe2caefcSParav Pandit enum { 1197fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0, 1198fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF, 1199fe2caefcSParav Pandit 1200fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0, 1201fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0), 1202fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1, 1203fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1), 1204fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2, 1205fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2), 1206fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3, 1207fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3), 1208fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4, 1209fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4), 1210fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5, 1211fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5), 1212fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6), 1213fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6, 1214fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16, 1215fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF << 1216fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT 1217fe2caefcSParav Pandit }; 1218fe2caefcSParav Pandit 1219fe2caefcSParav Pandit struct ocrdma_alloc_lkey { 1220fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1221fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1222fe2caefcSParav Pandit 1223fe2caefcSParav Pandit u32 pdid; 1224fe2caefcSParav Pandit u32 pbl_sz_flags; 1225fe2caefcSParav Pandit } __packed; 1226fe2caefcSParav Pandit 1227fe2caefcSParav Pandit struct ocrdma_alloc_lkey_rsp { 1228fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1229fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1230fe2caefcSParav Pandit 1231fe2caefcSParav Pandit u32 lrkey; 1232fe2caefcSParav Pandit u32 num_pbl_rsvd; 1233fe2caefcSParav Pandit } __packed; 1234fe2caefcSParav Pandit 1235fe2caefcSParav Pandit struct ocrdma_dealloc_lkey { 1236fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1237fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1238fe2caefcSParav Pandit 1239fe2caefcSParav Pandit u32 lkey; 1240fe2caefcSParav Pandit u32 rsvd_frmr; 1241fe2caefcSParav Pandit } __packed; 1242fe2caefcSParav Pandit 1243fe2caefcSParav Pandit struct ocrdma_dealloc_lkey_rsp { 1244fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1245fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1246fe2caefcSParav Pandit } __packed; 1247fe2caefcSParav Pandit 1248fe2caefcSParav Pandit #define MAX_OCRDMA_NSMR_PBL (u32)22 1249fe2caefcSParav Pandit #define MAX_OCRDMA_PBL_SIZE 65536 1250fe2caefcSParav Pandit #define MAX_OCRDMA_PBL_PER_LKEY 32767 1251fe2caefcSParav Pandit 1252fe2caefcSParav Pandit enum { 1253fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0, 1254fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF, 1255fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_SHIFT = 24, 1256fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF << 1257fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_SHIFT, 1258fe2caefcSParav Pandit 1259fe2caefcSParav Pandit OCRDMA_REG_NSMR_PD_ID_SHIFT = 0, 1260fe2caefcSParav Pandit OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF, 1261fe2caefcSParav Pandit OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16, 1262fe2caefcSParav Pandit OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF << 1263fe2caefcSParav Pandit OCRDMA_REG_NSMR_NUM_PBL_SHIFT, 1264fe2caefcSParav Pandit 1265fe2caefcSParav Pandit OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0, 1266fe2caefcSParav Pandit OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF, 1267fe2caefcSParav Pandit OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16, 1268fe2caefcSParav Pandit OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF << 1269fe2caefcSParav Pandit OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT, 1270fe2caefcSParav Pandit OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24, 1271fe2caefcSParav Pandit OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24), 1272fe2caefcSParav Pandit OCRDMA_REG_NSMR_ZB_SHIFT = 25, 1273fe2caefcSParav Pandit OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25), 1274fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26, 1275fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26), 1276fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27, 1277fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27), 1278fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28, 1279fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28), 1280fe2caefcSParav Pandit OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29, 1281fe2caefcSParav Pandit OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29), 1282fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30, 1283fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30), 1284fe2caefcSParav Pandit OCRDMA_REG_NSMR_LAST_SHIFT = 31, 1285fe2caefcSParav Pandit OCRDMA_REG_NSMR_LAST_MASK = Bit(31) 1286fe2caefcSParav Pandit }; 1287fe2caefcSParav Pandit 1288fe2caefcSParav Pandit struct ocrdma_reg_nsmr { 1289fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1290fe2caefcSParav Pandit struct ocrdma_mbx_hdr cmd; 1291fe2caefcSParav Pandit 1292fe2caefcSParav Pandit u32 lrkey_key_index; 1293fe2caefcSParav Pandit u32 num_pbl_pdid; 1294fe2caefcSParav Pandit u32 flags_hpage_pbe_sz; 1295fe2caefcSParav Pandit u32 totlen_low; 1296fe2caefcSParav Pandit u32 totlen_high; 1297fe2caefcSParav Pandit u32 fbo_low; 1298fe2caefcSParav Pandit u32 fbo_high; 1299fe2caefcSParav Pandit u32 va_loaddr; 1300fe2caefcSParav Pandit u32 va_hiaddr; 1301fe2caefcSParav Pandit struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1302fe2caefcSParav Pandit } __packed; 1303fe2caefcSParav Pandit 1304fe2caefcSParav Pandit enum { 1305fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0, 1306fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF, 1307fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16, 1308fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF << 1309fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT, 1310fe2caefcSParav Pandit 1311fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31, 1312fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31) 1313fe2caefcSParav Pandit }; 1314fe2caefcSParav Pandit 1315fe2caefcSParav Pandit struct ocrdma_reg_nsmr_cont { 1316fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1317fe2caefcSParav Pandit struct ocrdma_mbx_hdr cmd; 1318fe2caefcSParav Pandit 1319fe2caefcSParav Pandit u32 lrkey; 1320fe2caefcSParav Pandit u32 num_pbl_offset; 1321fe2caefcSParav Pandit u32 last; 1322fe2caefcSParav Pandit 1323fe2caefcSParav Pandit struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 1324fe2caefcSParav Pandit } __packed; 1325fe2caefcSParav Pandit 1326fe2caefcSParav Pandit struct ocrdma_pbe { 1327fe2caefcSParav Pandit u32 pa_hi; 1328fe2caefcSParav Pandit u32 pa_lo; 1329fe2caefcSParav Pandit } __packed; 1330fe2caefcSParav Pandit 1331fe2caefcSParav Pandit enum { 1332fe2caefcSParav Pandit OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16, 1333fe2caefcSParav Pandit OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000 1334fe2caefcSParav Pandit }; 1335fe2caefcSParav Pandit struct ocrdma_reg_nsmr_rsp { 1336fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1337fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1338fe2caefcSParav Pandit 1339fe2caefcSParav Pandit u32 lrkey; 1340fe2caefcSParav Pandit u32 num_pbl; 1341fe2caefcSParav Pandit } __packed; 1342fe2caefcSParav Pandit 1343fe2caefcSParav Pandit enum { 1344fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0, 1345fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF, 1346fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24, 1347fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF << 1348fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT, 1349fe2caefcSParav Pandit 1350fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16, 1351fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF << 1352fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT 1353fe2caefcSParav Pandit }; 1354fe2caefcSParav Pandit 1355fe2caefcSParav Pandit struct ocrdma_reg_nsmr_cont_rsp { 1356fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1357fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1358fe2caefcSParav Pandit 1359fe2caefcSParav Pandit u32 lrkey_key_index; 1360fe2caefcSParav Pandit u32 num_pbl; 1361fe2caefcSParav Pandit } __packed; 1362fe2caefcSParav Pandit 1363fe2caefcSParav Pandit enum { 1364fe2caefcSParav Pandit OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0, 1365fe2caefcSParav Pandit OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF 1366fe2caefcSParav Pandit }; 1367fe2caefcSParav Pandit 1368fe2caefcSParav Pandit struct ocrdma_alloc_mw { 1369fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1370fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1371fe2caefcSParav Pandit 1372fe2caefcSParav Pandit u32 pdid; 1373fe2caefcSParav Pandit } __packed; 1374fe2caefcSParav Pandit 1375fe2caefcSParav Pandit enum { 1376fe2caefcSParav Pandit OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0, 1377fe2caefcSParav Pandit OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF 1378fe2caefcSParav Pandit }; 1379fe2caefcSParav Pandit 1380fe2caefcSParav Pandit struct ocrdma_alloc_mw_rsp { 1381fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1382fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1383fe2caefcSParav Pandit 1384fe2caefcSParav Pandit u32 lrkey_index; 1385fe2caefcSParav Pandit } __packed; 1386fe2caefcSParav Pandit 1387fe2caefcSParav Pandit struct ocrdma_attach_mcast { 1388fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1389fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1390fe2caefcSParav Pandit u32 qp_id; 1391fe2caefcSParav Pandit u8 mgid[16]; 1392fe2caefcSParav Pandit u32 mac_b0_to_b3; 1393fe2caefcSParav Pandit u32 vlan_mac_b4_to_b5; 1394fe2caefcSParav Pandit } __packed; 1395fe2caefcSParav Pandit 1396fe2caefcSParav Pandit struct ocrdma_attach_mcast_rsp { 1397fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1398fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1399fe2caefcSParav Pandit } __packed; 1400fe2caefcSParav Pandit 1401fe2caefcSParav Pandit struct ocrdma_detach_mcast { 1402fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1403fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1404fe2caefcSParav Pandit u32 qp_id; 1405fe2caefcSParav Pandit u8 mgid[16]; 1406fe2caefcSParav Pandit u32 mac_b0_to_b3; 1407fe2caefcSParav Pandit u32 vlan_mac_b4_to_b5; 1408fe2caefcSParav Pandit } __packed; 1409fe2caefcSParav Pandit 1410fe2caefcSParav Pandit struct ocrdma_detach_mcast_rsp { 1411fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1412fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1413fe2caefcSParav Pandit } __packed; 1414fe2caefcSParav Pandit 1415fe2caefcSParav Pandit enum { 1416fe2caefcSParav Pandit OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19, 1417fe2caefcSParav Pandit OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF << 1418fe2caefcSParav Pandit OCRDMA_CREATE_AH_NUM_PAGES_SHIFT, 1419fe2caefcSParav Pandit 1420fe2caefcSParav Pandit OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16, 1421fe2caefcSParav Pandit OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 << 1422fe2caefcSParav Pandit OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT, 1423fe2caefcSParav Pandit 1424fe2caefcSParav Pandit OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23, 1425fe2caefcSParav Pandit OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF << 1426fe2caefcSParav Pandit OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT, 1427fe2caefcSParav Pandit }; 1428fe2caefcSParav Pandit 1429fe2caefcSParav Pandit #define OCRDMA_AH_TBL_PAGES 8 1430fe2caefcSParav Pandit 1431fe2caefcSParav Pandit struct ocrdma_create_ah_tbl { 1432fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1433fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1434fe2caefcSParav Pandit 1435fe2caefcSParav Pandit u32 ah_conf; 1436fe2caefcSParav Pandit struct ocrdma_pa tbl_addr[8]; 1437fe2caefcSParav Pandit } __packed; 1438fe2caefcSParav Pandit 1439fe2caefcSParav Pandit struct ocrdma_create_ah_tbl_rsp { 1440fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1441fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1442fe2caefcSParav Pandit u32 ahid; 1443fe2caefcSParav Pandit } __packed; 1444fe2caefcSParav Pandit 1445fe2caefcSParav Pandit struct ocrdma_delete_ah_tbl { 1446fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1447fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1448fe2caefcSParav Pandit u32 ahid; 1449fe2caefcSParav Pandit } __packed; 1450fe2caefcSParav Pandit 1451fe2caefcSParav Pandit struct ocrdma_delete_ah_tbl_rsp { 1452fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1453fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1454fe2caefcSParav Pandit } __packed; 1455fe2caefcSParav Pandit 1456fe2caefcSParav Pandit enum { 1457fe2caefcSParav Pandit OCRDMA_EQE_VALID_SHIFT = 0, 1458fe2caefcSParav Pandit OCRDMA_EQE_VALID_MASK = Bit(0), 1459fe2caefcSParav Pandit OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE, 1460fe2caefcSParav Pandit OCRDMA_EQE_RESOURCE_ID_SHIFT = 16, 1461fe2caefcSParav Pandit OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF << 1462fe2caefcSParav Pandit OCRDMA_EQE_RESOURCE_ID_SHIFT, 1463fe2caefcSParav Pandit }; 1464fe2caefcSParav Pandit 1465fe2caefcSParav Pandit struct ocrdma_eqe { 1466fe2caefcSParav Pandit u32 id_valid; 1467fe2caefcSParav Pandit } __packed; 1468fe2caefcSParav Pandit 1469fe2caefcSParav Pandit enum OCRDMA_CQE_STATUS { 1470fe2caefcSParav Pandit OCRDMA_CQE_SUCCESS = 0, 1471fe2caefcSParav Pandit OCRDMA_CQE_LOC_LEN_ERR, 1472fe2caefcSParav Pandit OCRDMA_CQE_LOC_QP_OP_ERR, 1473fe2caefcSParav Pandit OCRDMA_CQE_LOC_EEC_OP_ERR, 1474fe2caefcSParav Pandit OCRDMA_CQE_LOC_PROT_ERR, 1475fe2caefcSParav Pandit OCRDMA_CQE_WR_FLUSH_ERR, 1476fe2caefcSParav Pandit OCRDMA_CQE_MW_BIND_ERR, 1477fe2caefcSParav Pandit OCRDMA_CQE_BAD_RESP_ERR, 1478fe2caefcSParav Pandit OCRDMA_CQE_LOC_ACCESS_ERR, 1479fe2caefcSParav Pandit OCRDMA_CQE_REM_INV_REQ_ERR, 1480fe2caefcSParav Pandit OCRDMA_CQE_REM_ACCESS_ERR, 1481fe2caefcSParav Pandit OCRDMA_CQE_REM_OP_ERR, 1482fe2caefcSParav Pandit OCRDMA_CQE_RETRY_EXC_ERR, 1483fe2caefcSParav Pandit OCRDMA_CQE_RNR_RETRY_EXC_ERR, 1484fe2caefcSParav Pandit OCRDMA_CQE_LOC_RDD_VIOL_ERR, 1485fe2caefcSParav Pandit OCRDMA_CQE_REM_INV_RD_REQ_ERR, 1486fe2caefcSParav Pandit OCRDMA_CQE_REM_ABORT_ERR, 1487fe2caefcSParav Pandit OCRDMA_CQE_INV_EECN_ERR, 1488fe2caefcSParav Pandit OCRDMA_CQE_INV_EEC_STATE_ERR, 1489fe2caefcSParav Pandit OCRDMA_CQE_FATAL_ERR, 1490fe2caefcSParav Pandit OCRDMA_CQE_RESP_TIMEOUT_ERR, 1491fe2caefcSParav Pandit OCRDMA_CQE_GENERAL_ERR 1492fe2caefcSParav Pandit }; 1493fe2caefcSParav Pandit 1494fe2caefcSParav Pandit enum { 1495fe2caefcSParav Pandit /* w0 */ 1496fe2caefcSParav Pandit OCRDMA_CQE_WQEIDX_SHIFT = 0, 1497fe2caefcSParav Pandit OCRDMA_CQE_WQEIDX_MASK = 0xFFFF, 1498fe2caefcSParav Pandit 1499fe2caefcSParav Pandit /* w1 */ 1500fe2caefcSParav Pandit OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16, 1501fe2caefcSParav Pandit OCRDMA_CQE_PKEY_SHIFT = 0, 1502fe2caefcSParav Pandit OCRDMA_CQE_PKEY_MASK = 0xFFFF, 1503fe2caefcSParav Pandit 1504fe2caefcSParav Pandit /* w2 */ 1505fe2caefcSParav Pandit OCRDMA_CQE_QPN_SHIFT = 0, 1506fe2caefcSParav Pandit OCRDMA_CQE_QPN_MASK = 0x0000FFFF, 1507fe2caefcSParav Pandit 1508fe2caefcSParav Pandit OCRDMA_CQE_BUFTAG_SHIFT = 16, 1509fe2caefcSParav Pandit OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT, 1510fe2caefcSParav Pandit 1511fe2caefcSParav Pandit /* w3 */ 1512fe2caefcSParav Pandit OCRDMA_CQE_UD_STATUS_SHIFT = 24, 1513fe2caefcSParav Pandit OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT, 1514fe2caefcSParav Pandit OCRDMA_CQE_STATUS_SHIFT = 16, 1515fe2caefcSParav Pandit OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT, 1516fe2caefcSParav Pandit OCRDMA_CQE_VALID = Bit(31), 1517fe2caefcSParav Pandit OCRDMA_CQE_INVALIDATE = Bit(30), 1518fe2caefcSParav Pandit OCRDMA_CQE_QTYPE = Bit(29), 1519fe2caefcSParav Pandit OCRDMA_CQE_IMM = Bit(28), 1520fe2caefcSParav Pandit OCRDMA_CQE_WRITE_IMM = Bit(27), 1521fe2caefcSParav Pandit OCRDMA_CQE_QTYPE_SQ = 0, 1522fe2caefcSParav Pandit OCRDMA_CQE_QTYPE_RQ = 1, 1523fe2caefcSParav Pandit OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF 1524fe2caefcSParav Pandit }; 1525fe2caefcSParav Pandit 1526fe2caefcSParav Pandit struct ocrdma_cqe { 1527fe2caefcSParav Pandit union { 1528fe2caefcSParav Pandit /* w0 to w2 */ 1529fe2caefcSParav Pandit struct { 1530fe2caefcSParav Pandit u32 wqeidx; 1531fe2caefcSParav Pandit u32 bytes_xfered; 1532fe2caefcSParav Pandit u32 qpn; 1533fe2caefcSParav Pandit } wq; 1534fe2caefcSParav Pandit struct { 1535fe2caefcSParav Pandit u32 lkey_immdt; 1536fe2caefcSParav Pandit u32 rxlen; 1537fe2caefcSParav Pandit u32 buftag_qpn; 1538fe2caefcSParav Pandit } rq; 1539fe2caefcSParav Pandit struct { 1540fe2caefcSParav Pandit u32 lkey_immdt; 1541fe2caefcSParav Pandit u32 rxlen_pkey; 1542fe2caefcSParav Pandit u32 buftag_qpn; 1543fe2caefcSParav Pandit } ud; 1544fe2caefcSParav Pandit struct { 1545fe2caefcSParav Pandit u32 word_0; 1546fe2caefcSParav Pandit u32 word_1; 1547fe2caefcSParav Pandit u32 qpn; 1548fe2caefcSParav Pandit } cmn; 1549fe2caefcSParav Pandit }; 1550fe2caefcSParav Pandit u32 flags_status_srcqpn; /* w3 */ 1551fe2caefcSParav Pandit } __packed; 1552fe2caefcSParav Pandit 1553fe2caefcSParav Pandit #define is_cqe_valid(cq, cqe) \ 1554fe2caefcSParav Pandit (((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID)\ 1555fe2caefcSParav Pandit == cq->phase) ? 1 : 0) 1556fe2caefcSParav Pandit #define is_cqe_for_sq(cqe) \ 1557fe2caefcSParav Pandit ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 0 : 1) 1558fe2caefcSParav Pandit #define is_cqe_for_rq(cqe) \ 1559fe2caefcSParav Pandit ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 1 : 0) 1560fe2caefcSParav Pandit #define is_cqe_invalidated(cqe) \ 1561fe2caefcSParav Pandit ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_INVALIDATE) ? \ 1562fe2caefcSParav Pandit 1 : 0) 1563fe2caefcSParav Pandit #define is_cqe_imm(cqe) \ 1564fe2caefcSParav Pandit ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_IMM) ? 1 : 0) 1565fe2caefcSParav Pandit #define is_cqe_wr_imm(cqe) \ 1566fe2caefcSParav Pandit ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_WRITE_IMM) ? 1 : 0) 1567fe2caefcSParav Pandit 1568fe2caefcSParav Pandit struct ocrdma_sge { 1569fe2caefcSParav Pandit u32 addr_hi; 1570fe2caefcSParav Pandit u32 addr_lo; 1571fe2caefcSParav Pandit u32 lrkey; 1572fe2caefcSParav Pandit u32 len; 1573fe2caefcSParav Pandit } __packed; 1574fe2caefcSParav Pandit 1575fe2caefcSParav Pandit enum { 1576fe2caefcSParav Pandit OCRDMA_FLAG_SIG = 0x1, 1577fe2caefcSParav Pandit OCRDMA_FLAG_INV = 0x2, 1578fe2caefcSParav Pandit OCRDMA_FLAG_FENCE_L = 0x4, 1579fe2caefcSParav Pandit OCRDMA_FLAG_FENCE_R = 0x8, 1580fe2caefcSParav Pandit OCRDMA_FLAG_SOLICIT = 0x10, 1581fe2caefcSParav Pandit OCRDMA_FLAG_IMM = 0x20, 1582fe2caefcSParav Pandit 1583fe2caefcSParav Pandit /* Stag flags */ 1584fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1, 1585fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2, 1586fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4, 1587fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_VATO = 0x8, 1588fe2caefcSParav Pandit }; 1589fe2caefcSParav Pandit 1590fe2caefcSParav Pandit enum OCRDMA_WQE_OPCODE { 1591fe2caefcSParav Pandit OCRDMA_WRITE = 0x06, 1592fe2caefcSParav Pandit OCRDMA_READ = 0x0C, 1593fe2caefcSParav Pandit OCRDMA_RESV0 = 0x02, 1594fe2caefcSParav Pandit OCRDMA_SEND = 0x00, 1595fe2caefcSParav Pandit OCRDMA_CMP_SWP = 0x14, 1596fe2caefcSParav Pandit OCRDMA_BIND_MW = 0x10, 1597fe2caefcSParav Pandit OCRDMA_RESV1 = 0x0A, 1598fe2caefcSParav Pandit OCRDMA_LKEY_INV = 0x15, 1599fe2caefcSParav Pandit OCRDMA_FETCH_ADD = 0x13, 1600fe2caefcSParav Pandit OCRDMA_POST_RQ = 0x12 1601fe2caefcSParav Pandit }; 1602fe2caefcSParav Pandit 1603fe2caefcSParav Pandit enum { 1604fe2caefcSParav Pandit OCRDMA_TYPE_INLINE = 0x0, 1605fe2caefcSParav Pandit OCRDMA_TYPE_LKEY = 0x1, 1606fe2caefcSParav Pandit }; 1607fe2caefcSParav Pandit 1608fe2caefcSParav Pandit enum { 1609fe2caefcSParav Pandit OCRDMA_WQE_OPCODE_SHIFT = 0, 1610fe2caefcSParav Pandit OCRDMA_WQE_OPCODE_MASK = 0x0000001F, 1611fe2caefcSParav Pandit OCRDMA_WQE_FLAGS_SHIFT = 5, 1612fe2caefcSParav Pandit OCRDMA_WQE_TYPE_SHIFT = 16, 1613fe2caefcSParav Pandit OCRDMA_WQE_TYPE_MASK = 0x00030000, 1614fe2caefcSParav Pandit OCRDMA_WQE_SIZE_SHIFT = 18, 1615fe2caefcSParav Pandit OCRDMA_WQE_SIZE_MASK = 0xFF, 1616fe2caefcSParav Pandit OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25, 1617fe2caefcSParav Pandit 1618fe2caefcSParav Pandit OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0, 1619fe2caefcSParav Pandit OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF 1620fe2caefcSParav Pandit }; 1621fe2caefcSParav Pandit 1622fe2caefcSParav Pandit /* header WQE for all the SQ and RQ operations */ 1623fe2caefcSParav Pandit struct ocrdma_hdr_wqe { 1624fe2caefcSParav Pandit u32 cw; 1625fe2caefcSParav Pandit union { 1626fe2caefcSParav Pandit u32 rsvd_tag; 1627fe2caefcSParav Pandit u32 rsvd_lkey_flags; 1628fe2caefcSParav Pandit }; 1629fe2caefcSParav Pandit union { 1630fe2caefcSParav Pandit u32 immdt; 1631fe2caefcSParav Pandit u32 lkey; 1632fe2caefcSParav Pandit }; 1633fe2caefcSParav Pandit u32 total_len; 1634fe2caefcSParav Pandit } __packed; 1635fe2caefcSParav Pandit 1636fe2caefcSParav Pandit struct ocrdma_ewqe_ud_hdr { 1637fe2caefcSParav Pandit u32 rsvd_dest_qpn; 1638fe2caefcSParav Pandit u32 qkey; 1639fe2caefcSParav Pandit u32 rsvd_ahid; 1640fe2caefcSParav Pandit u32 rsvd; 1641fe2caefcSParav Pandit } __packed; 1642fe2caefcSParav Pandit 1643fe2caefcSParav Pandit struct ocrdma_eth_basic { 1644fe2caefcSParav Pandit u8 dmac[6]; 1645fe2caefcSParav Pandit u8 smac[6]; 1646fe2caefcSParav Pandit __be16 eth_type; 1647fe2caefcSParav Pandit } __packed; 1648fe2caefcSParav Pandit 1649fe2caefcSParav Pandit struct ocrdma_eth_vlan { 1650fe2caefcSParav Pandit u8 dmac[6]; 1651fe2caefcSParav Pandit u8 smac[6]; 1652fe2caefcSParav Pandit __be16 eth_type; 1653fe2caefcSParav Pandit __be16 vlan_tag; 1654fe2caefcSParav Pandit #define OCRDMA_ROCE_ETH_TYPE 0x8915 1655fe2caefcSParav Pandit __be16 roce_eth_type; 1656fe2caefcSParav Pandit } __packed; 1657fe2caefcSParav Pandit 1658fe2caefcSParav Pandit struct ocrdma_grh { 1659fe2caefcSParav Pandit __be32 tclass_flow; 1660fe2caefcSParav Pandit __be32 pdid_hoplimit; 1661fe2caefcSParav Pandit u8 sgid[16]; 1662fe2caefcSParav Pandit u8 dgid[16]; 1663fe2caefcSParav Pandit u16 rsvd; 1664fe2caefcSParav Pandit } __packed; 1665fe2caefcSParav Pandit 1666fe2caefcSParav Pandit #define OCRDMA_AV_VALID Bit(0) 1667fe2caefcSParav Pandit #define OCRDMA_AV_VLAN_VALID Bit(1) 1668fe2caefcSParav Pandit 1669fe2caefcSParav Pandit struct ocrdma_av { 1670fe2caefcSParav Pandit struct ocrdma_eth_vlan eth_hdr; 1671fe2caefcSParav Pandit struct ocrdma_grh grh; 1672fe2caefcSParav Pandit u32 valid; 1673fe2caefcSParav Pandit } __packed; 1674fe2caefcSParav Pandit 1675fe2caefcSParav Pandit #endif /* __OCRDMA_SLI_H__ */ 1676