171ee6730SDevesh Sharma /* This file is part of the Emulex RoCE Device Driver for 271ee6730SDevesh Sharma * RoCE (RDMA over Converged Ethernet) adapters. 371ee6730SDevesh Sharma * Copyright (C) 2012-2015 Emulex. All rights reserved. 471ee6730SDevesh Sharma * EMULEX and SLI are trademarks of Emulex. 571ee6730SDevesh Sharma * www.emulex.com 671ee6730SDevesh Sharma * 771ee6730SDevesh Sharma * This software is available to you under a choice of one of two licenses. 871ee6730SDevesh Sharma * You may choose to be licensed under the terms of the GNU General Public 971ee6730SDevesh Sharma * License (GPL) Version 2, available from the file COPYING in the main 1071ee6730SDevesh Sharma * directory of this source tree, or the BSD license below: 1171ee6730SDevesh Sharma * 1271ee6730SDevesh Sharma * Redistribution and use in source and binary forms, with or without 1371ee6730SDevesh Sharma * modification, are permitted provided that the following conditions 1471ee6730SDevesh Sharma * are met: 1571ee6730SDevesh Sharma * 1671ee6730SDevesh Sharma * - Redistributions of source code must retain the above copyright notice, 1771ee6730SDevesh Sharma * this list of conditions and the following disclaimer. 1871ee6730SDevesh Sharma * 1971ee6730SDevesh Sharma * - Redistributions in binary form must reproduce the above copyright 2071ee6730SDevesh Sharma * notice, this list of conditions and the following disclaimer in 2171ee6730SDevesh Sharma * the documentation and/or other materials provided with the distribution. 2271ee6730SDevesh Sharma * 2371ee6730SDevesh Sharma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2471ee6730SDevesh Sharma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE 2571ee6730SDevesh Sharma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2671ee6730SDevesh Sharma * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2771ee6730SDevesh Sharma * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2871ee6730SDevesh Sharma * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2971ee6730SDevesh Sharma * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 3071ee6730SDevesh Sharma * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 3171ee6730SDevesh Sharma * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 3271ee6730SDevesh Sharma * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 3371ee6730SDevesh Sharma * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34fe2caefcSParav Pandit * 35fe2caefcSParav Pandit * Contact Information: 36fe2caefcSParav Pandit * linux-drivers@emulex.com 37fe2caefcSParav Pandit * 38fe2caefcSParav Pandit * Emulex 39fe2caefcSParav Pandit * 3333 Susan Street 40fe2caefcSParav Pandit * Costa Mesa, CA 92626 4171ee6730SDevesh Sharma */ 42fe2caefcSParav Pandit 43fe2caefcSParav Pandit #ifndef __OCRDMA_SLI_H__ 44fe2caefcSParav Pandit #define __OCRDMA_SLI_H__ 45fe2caefcSParav Pandit 4621c3391aSDevesh Sharma enum { 4721c3391aSDevesh Sharma OCRDMA_ASIC_GEN_SKH_R = 0x04, 4821c3391aSDevesh Sharma OCRDMA_ASIC_GEN_LANCER = 0x0B 4921c3391aSDevesh Sharma }; 5021c3391aSDevesh Sharma 5121c3391aSDevesh Sharma enum { 5221c3391aSDevesh Sharma OCRDMA_ASIC_REV_A0 = 0x00, 5321c3391aSDevesh Sharma OCRDMA_ASIC_REV_B0 = 0x10, 5421c3391aSDevesh Sharma OCRDMA_ASIC_REV_C0 = 0x20 5521c3391aSDevesh Sharma }; 56fe2caefcSParav Pandit 57fe2caefcSParav Pandit #define OCRDMA_SUBSYS_ROCE 10 58fe2caefcSParav Pandit enum { 59fe2caefcSParav Pandit OCRDMA_CMD_QUERY_CONFIG = 1, 60920de55dSSelvin Xavier OCRDMA_CMD_ALLOC_PD = 2, 61920de55dSSelvin Xavier OCRDMA_CMD_DEALLOC_PD = 3, 62fe2caefcSParav Pandit 63920de55dSSelvin Xavier OCRDMA_CMD_CREATE_AH_TBL = 4, 64920de55dSSelvin Xavier OCRDMA_CMD_DELETE_AH_TBL = 5, 65fe2caefcSParav Pandit 66920de55dSSelvin Xavier OCRDMA_CMD_CREATE_QP = 6, 67920de55dSSelvin Xavier OCRDMA_CMD_QUERY_QP = 7, 68920de55dSSelvin Xavier OCRDMA_CMD_MODIFY_QP = 8 , 69920de55dSSelvin Xavier OCRDMA_CMD_DELETE_QP = 9, 70fe2caefcSParav Pandit 71920de55dSSelvin Xavier OCRDMA_CMD_RSVD1 = 10, 72920de55dSSelvin Xavier OCRDMA_CMD_ALLOC_LKEY = 11, 73920de55dSSelvin Xavier OCRDMA_CMD_DEALLOC_LKEY = 12, 74920de55dSSelvin Xavier OCRDMA_CMD_REGISTER_NSMR = 13, 75920de55dSSelvin Xavier OCRDMA_CMD_REREGISTER_NSMR = 14, 76920de55dSSelvin Xavier OCRDMA_CMD_REGISTER_NSMR_CONT = 15, 77920de55dSSelvin Xavier OCRDMA_CMD_QUERY_NSMR = 16, 78920de55dSSelvin Xavier OCRDMA_CMD_ALLOC_MW = 17, 79920de55dSSelvin Xavier OCRDMA_CMD_QUERY_MW = 18, 80fe2caefcSParav Pandit 81920de55dSSelvin Xavier OCRDMA_CMD_CREATE_SRQ = 19, 82920de55dSSelvin Xavier OCRDMA_CMD_QUERY_SRQ = 20, 83920de55dSSelvin Xavier OCRDMA_CMD_MODIFY_SRQ = 21, 84920de55dSSelvin Xavier OCRDMA_CMD_DELETE_SRQ = 22, 85fe2caefcSParav Pandit 86920de55dSSelvin Xavier OCRDMA_CMD_ATTACH_MCAST = 23, 87920de55dSSelvin Xavier OCRDMA_CMD_DETACH_MCAST = 24, 88920de55dSSelvin Xavier 89920de55dSSelvin Xavier OCRDMA_CMD_CREATE_RBQ = 25, 90920de55dSSelvin Xavier OCRDMA_CMD_DESTROY_RBQ = 26, 91920de55dSSelvin Xavier 92920de55dSSelvin Xavier OCRDMA_CMD_GET_RDMA_STATS = 27, 939ba1377dSMitesh Ahuja OCRDMA_CMD_ALLOC_PD_RANGE = 28, 949ba1377dSMitesh Ahuja OCRDMA_CMD_DEALLOC_PD_RANGE = 29, 95fe2caefcSParav Pandit 96fe2caefcSParav Pandit OCRDMA_CMD_MAX 97fe2caefcSParav Pandit }; 98fe2caefcSParav Pandit 99fe2caefcSParav Pandit #define OCRDMA_SUBSYS_COMMON 1 100fe2caefcSParav Pandit enum { 101f24ceba6SNaresh Gottumukkala OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5, 102fe2caefcSParav Pandit OCRDMA_CMD_CREATE_CQ = 12, 103fe2caefcSParav Pandit OCRDMA_CMD_CREATE_EQ = 13, 104fe2caefcSParav Pandit OCRDMA_CMD_CREATE_MQ = 21, 105a51f06e1SSelvin Xavier OCRDMA_CMD_GET_CTRL_ATTRIBUTES = 32, 106fe2caefcSParav Pandit OCRDMA_CMD_GET_FW_VER = 35, 107b4dbe8d5SMitesh Ahuja OCRDMA_CMD_MODIFY_EQ_DELAY = 41, 108fe2caefcSParav Pandit OCRDMA_CMD_DELETE_MQ = 53, 109fe2caefcSParav Pandit OCRDMA_CMD_DELETE_CQ = 54, 110fe2caefcSParav Pandit OCRDMA_CMD_DELETE_EQ = 55, 111fe2caefcSParav Pandit OCRDMA_CMD_GET_FW_CONFIG = 58, 112a51f06e1SSelvin Xavier OCRDMA_CMD_CREATE_MQ_EXT = 90, 113a51f06e1SSelvin Xavier OCRDMA_CMD_PHY_DETAILS = 102 114fe2caefcSParav Pandit }; 115fe2caefcSParav Pandit 116fe2caefcSParav Pandit enum { 117fe2caefcSParav Pandit QTYPE_EQ = 1, 118fe2caefcSParav Pandit QTYPE_CQ = 2, 119fe2caefcSParav Pandit QTYPE_MCCQ = 3 120fe2caefcSParav Pandit }; 121fe2caefcSParav Pandit 122978cb6a4SMitesh Ahuja #define OCRDMA_MAX_SGID 16 123fe2caefcSParav Pandit 124fe2caefcSParav Pandit #define OCRDMA_MAX_QP 2048 125fe2caefcSParav Pandit #define OCRDMA_MAX_CQ 2048 1264f1df844SSelvin Xavier #define OCRDMA_MAX_STAG 16384 127fe2caefcSParav Pandit 128fe2caefcSParav Pandit enum { 129fe2caefcSParav Pandit OCRDMA_DB_RQ_OFFSET = 0xE0, 130f11220eeSNaresh Gottumukkala OCRDMA_DB_GEN2_RQ_OFFSET = 0x100, 131fe2caefcSParav Pandit OCRDMA_DB_SQ_OFFSET = 0x60, 132fe2caefcSParav Pandit OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0, 133fe2caefcSParav Pandit OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET, 134f11220eeSNaresh Gottumukkala OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ_OFFSET, 135fe2caefcSParav Pandit OCRDMA_DB_CQ_OFFSET = 0x120, 136fe2caefcSParav Pandit OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET, 1372df84fa8SDevesh Sharma OCRDMA_DB_MQ_OFFSET = 0x140, 1382df84fa8SDevesh Sharma 1392df84fa8SDevesh Sharma OCRDMA_DB_SQ_SHIFT = 16, 1402df84fa8SDevesh Sharma OCRDMA_DB_RQ_SHIFT = 24 141fe2caefcSParav Pandit }; 142fe2caefcSParav Pandit 143e1614869SSomnath Kotur enum { 144e1614869SSomnath Kotur OCRDMA_L3_TYPE_IB_GRH = 0x00, 145e1614869SSomnath Kotur OCRDMA_L3_TYPE_IPV4 = 0x01, 146e1614869SSomnath Kotur OCRDMA_L3_TYPE_IPV6 = 0x02 147e1614869SSomnath Kotur }; 148cc36929eSSomnath Kotur 149fe2caefcSParav Pandit #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 150fe2caefcSParav Pandit #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */ 151fe2caefcSParav Pandit /* qid #2 msbits at 12-11 */ 152fe2caefcSParav Pandit #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1 15305df7805SJes Sorensen #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */ 154fe2caefcSParav Pandit /* Rearm bit */ 15505df7805SJes Sorensen #define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */ 156fe2caefcSParav Pandit /* solicited bit */ 15705df7805SJes Sorensen #define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */ 158fe2caefcSParav Pandit 159fe2caefcSParav Pandit #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */ 160fe2caefcSParav Pandit #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */ 16105df7805SJes Sorensen #define OCRDMA_EQ_ID_EXT_MASK_SHIFT 2 /* qid bits 9-13 at 11-15 */ 162fe2caefcSParav Pandit 163fe2caefcSParav Pandit /* Clear the interrupt for this eq */ 16405df7805SJes Sorensen #define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */ 165fe2caefcSParav Pandit /* Must be 1 */ 16605df7805SJes Sorensen #define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */ 167fe2caefcSParav Pandit /* Number of event entries processed */ 16805df7805SJes Sorensen #define OCRDMA_NUM_EQE_SHIFT 16 /* bits 16 - 28 */ 169fe2caefcSParav Pandit /* Rearm bit */ 17005df7805SJes Sorensen #define OCRDMA_REARM_SHIFT 29 /* bit 29 */ 171fe2caefcSParav Pandit 172fe2caefcSParav Pandit #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */ 173fe2caefcSParav Pandit /* Number of entries posted */ 17405df7805SJes Sorensen #define OCRDMA_MQ_NUM_MQE_SHIFT 16 /* bits 16 - 29 */ 175fe2caefcSParav Pandit 17605df7805SJes Sorensen #define OCRDMA_MIN_HPAGE_SIZE 4096 177fe2caefcSParav Pandit 17805df7805SJes Sorensen #define OCRDMA_MIN_Q_PAGE_SIZE 4096 17905df7805SJes Sorensen #define OCRDMA_MAX_Q_PAGES 8 180fe2caefcSParav Pandit 18121c3391aSDevesh Sharma #define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C 18221c3391aSDevesh Sharma #define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF 18321c3391aSDevesh Sharma #define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00 18421c3391aSDevesh Sharma #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08 185fe2caefcSParav Pandit /* 186fe2caefcSParav Pandit # 0: 4K Bytes 187fe2caefcSParav Pandit # 1: 8K Bytes 188fe2caefcSParav Pandit # 2: 16K Bytes 189fe2caefcSParav Pandit # 3: 32K Bytes 190fe2caefcSParav Pandit # 4: 64K Bytes 1912b51a9b9SNaresh Gottumukkala # 5: 128K Bytes 1922b51a9b9SNaresh Gottumukkala # 6: 256K Bytes 1932b51a9b9SNaresh Gottumukkala # 7: 512K Bytes 194fe2caefcSParav Pandit */ 19505df7805SJes Sorensen #define OCRDMA_MAX_Q_PAGE_SIZE_CNT 8 196fe2caefcSParav Pandit #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES) 197fe2caefcSParav Pandit 19805df7805SJes Sorensen #define MAX_OCRDMA_QP_PAGES 8 199fe2caefcSParav Pandit #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE) 200fe2caefcSParav Pandit 20105df7805SJes Sorensen #define OCRDMA_CREATE_CQ_MAX_PAGES 4 20205df7805SJes Sorensen #define OCRDMA_DPP_CQE_SIZE 4 203fe2caefcSParav Pandit 204fe2caefcSParav Pandit #define OCRDMA_GEN2_MAX_CQE 1024 205fe2caefcSParav Pandit #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096 206fe2caefcSParav Pandit #define OCRDMA_GEN2_WQE_SIZE 256 207fe2caefcSParav Pandit #define OCRDMA_MAX_CQE 4095 208fe2caefcSParav Pandit #define OCRDMA_CQ_PAGE_SIZE 16384 209fe2caefcSParav Pandit #define OCRDMA_WQE_SIZE 128 210fe2caefcSParav Pandit #define OCRDMA_WQE_STRIDE 8 211fe2caefcSParav Pandit #define OCRDMA_WQE_ALIGN_BYTES 16 212fe2caefcSParav Pandit 213fe2caefcSParav Pandit #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES 214fe2caefcSParav Pandit 215fe2caefcSParav Pandit enum { 216fe2caefcSParav Pandit OCRDMA_MCH_OPCODE_SHIFT = 0, 217fe2caefcSParav Pandit OCRDMA_MCH_OPCODE_MASK = 0xFF, 218fe2caefcSParav Pandit OCRDMA_MCH_SUBSYS_SHIFT = 8, 219fe2caefcSParav Pandit OCRDMA_MCH_SUBSYS_MASK = 0xFF00 220fe2caefcSParav Pandit }; 221fe2caefcSParav Pandit 222fe2caefcSParav Pandit /* mailbox cmd header */ 223fe2caefcSParav Pandit struct ocrdma_mbx_hdr { 224fe2caefcSParav Pandit u32 subsys_op; 225fe2caefcSParav Pandit u32 timeout; /* in seconds */ 226fe2caefcSParav Pandit u32 cmd_len; 227fe2caefcSParav Pandit u32 rsvd_version; 2287b9b1a59SNaresh Gottumukkala }; 229fe2caefcSParav Pandit 230fe2caefcSParav Pandit enum { 231fe2caefcSParav Pandit OCRDMA_MBX_RSP_OPCODE_SHIFT = 0, 232fe2caefcSParav Pandit OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF, 233fe2caefcSParav Pandit OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8, 234fe2caefcSParav Pandit OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT, 235fe2caefcSParav Pandit 236fe2caefcSParav Pandit OCRDMA_MBX_RSP_STATUS_SHIFT = 0, 237fe2caefcSParav Pandit OCRDMA_MBX_RSP_STATUS_MASK = 0xFF, 238fe2caefcSParav Pandit OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8, 239fe2caefcSParav Pandit OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT 240fe2caefcSParav Pandit }; 241fe2caefcSParav Pandit 242fe2caefcSParav Pandit /* mailbox cmd response */ 243fe2caefcSParav Pandit struct ocrdma_mbx_rsp { 244fe2caefcSParav Pandit u32 subsys_op; 245fe2caefcSParav Pandit u32 status; 246fe2caefcSParav Pandit u32 rsp_len; 247fe2caefcSParav Pandit u32 add_rsp_len; 2487b9b1a59SNaresh Gottumukkala }; 249fe2caefcSParav Pandit 250fe2caefcSParav Pandit enum { 251fe2caefcSParav Pandit OCRDMA_MQE_EMBEDDED = 1, 252fe2caefcSParav Pandit OCRDMA_MQE_NONEMBEDDED = 0 253fe2caefcSParav Pandit }; 254fe2caefcSParav Pandit 255fe2caefcSParav Pandit struct ocrdma_mqe_sge { 256fe2caefcSParav Pandit u32 pa_lo; 257fe2caefcSParav Pandit u32 pa_hi; 258fe2caefcSParav Pandit u32 len; 2597b9b1a59SNaresh Gottumukkala }; 260fe2caefcSParav Pandit 261fe2caefcSParav Pandit enum { 262fe2caefcSParav Pandit OCRDMA_MQE_HDR_EMB_SHIFT = 0, 263de123485SJes Sorensen OCRDMA_MQE_HDR_EMB_MASK = BIT(0), 264fe2caefcSParav Pandit OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3, 265fe2caefcSParav Pandit OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT, 266fe2caefcSParav Pandit OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24, 267fe2caefcSParav Pandit OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT 268fe2caefcSParav Pandit }; 269fe2caefcSParav Pandit 270fe2caefcSParav Pandit struct ocrdma_mqe_hdr { 271fe2caefcSParav Pandit u32 spcl_sge_cnt_emb; 272fe2caefcSParav Pandit u32 pyld_len; 273fe2caefcSParav Pandit u32 tag_lo; 274fe2caefcSParav Pandit u32 tag_hi; 275fe2caefcSParav Pandit u32 rsvd3; 2767b9b1a59SNaresh Gottumukkala }; 277fe2caefcSParav Pandit 278fe2caefcSParav Pandit struct ocrdma_mqe_emb_cmd { 279fe2caefcSParav Pandit struct ocrdma_mbx_hdr mch; 280fe2caefcSParav Pandit u8 pyld[220]; 2817b9b1a59SNaresh Gottumukkala }; 282fe2caefcSParav Pandit 283fe2caefcSParav Pandit struct ocrdma_mqe { 284fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 285fe2caefcSParav Pandit union { 286fe2caefcSParav Pandit struct ocrdma_mqe_emb_cmd emb_req; 287fe2caefcSParav Pandit struct { 288fe2caefcSParav Pandit struct ocrdma_mqe_sge sge[19]; 289fe2caefcSParav Pandit } nonemb_req; 290fe2caefcSParav Pandit u8 cmd[236]; 291fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 292fe2caefcSParav Pandit } u; 2937b9b1a59SNaresh Gottumukkala }; 294fe2caefcSParav Pandit 295fe2caefcSParav Pandit #define OCRDMA_EQ_LEN 4096 296fe2caefcSParav Pandit #define OCRDMA_MQ_CQ_LEN 256 297fe2caefcSParav Pandit #define OCRDMA_MQ_LEN 128 298fe2caefcSParav Pandit 299fe2caefcSParav Pandit #define PAGE_SHIFT_4K 12 300fe2caefcSParav Pandit #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 301fe2caefcSParav Pandit 302fe2caefcSParav Pandit /* Returns number of pages spanned by the data starting at the given addr */ 303fe2caefcSParav Pandit #define PAGES_4K_SPANNED(_address, size) \ 304fe2caefcSParav Pandit ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 305fe2caefcSParav Pandit (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 306fe2caefcSParav Pandit 307fe2caefcSParav Pandit struct ocrdma_delete_q_req { 308fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 309fe2caefcSParav Pandit u32 id; 3107b9b1a59SNaresh Gottumukkala }; 311fe2caefcSParav Pandit 312fe2caefcSParav Pandit struct ocrdma_pa { 313fe2caefcSParav Pandit u32 lo; 314fe2caefcSParav Pandit u32 hi; 3157b9b1a59SNaresh Gottumukkala }; 316fe2caefcSParav Pandit 31705df7805SJes Sorensen #define MAX_OCRDMA_EQ_PAGES 8 318fe2caefcSParav Pandit struct ocrdma_create_eq_req { 319fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 320fe2caefcSParav Pandit u32 num_pages; 321fe2caefcSParav Pandit u32 valid; 322fe2caefcSParav Pandit u32 cnt; 323fe2caefcSParav Pandit u32 delay; 324fe2caefcSParav Pandit u32 rsvd; 325fe2caefcSParav Pandit struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES]; 3267b9b1a59SNaresh Gottumukkala }; 327fe2caefcSParav Pandit 328fe2caefcSParav Pandit enum { 329de123485SJes Sorensen OCRDMA_CREATE_EQ_VALID = BIT(29), 330fe2caefcSParav Pandit OCRDMA_CREATE_EQ_CNT_SHIFT = 26, 331fe2caefcSParav Pandit OCRDMA_CREATE_CQ_DELAY_SHIFT = 13, 332fe2caefcSParav Pandit }; 333fe2caefcSParav Pandit 334fe2caefcSParav Pandit struct ocrdma_create_eq_rsp { 335fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 336fe2caefcSParav Pandit u32 vector_eqid; 337fe2caefcSParav Pandit }; 338fe2caefcSParav Pandit 33905df7805SJes Sorensen #define OCRDMA_EQ_MINOR_OTHER 0x1 340fe2caefcSParav Pandit 341b4dbe8d5SMitesh Ahuja struct ocrmda_set_eqd { 342b4dbe8d5SMitesh Ahuja u32 eq_id; 343b4dbe8d5SMitesh Ahuja u32 phase; 344b4dbe8d5SMitesh Ahuja u32 delay_multiplier; 345b4dbe8d5SMitesh Ahuja }; 346b4dbe8d5SMitesh Ahuja 347b4dbe8d5SMitesh Ahuja struct ocrdma_modify_eqd_cmd { 348b4dbe8d5SMitesh Ahuja struct ocrdma_mbx_hdr req; 349b4dbe8d5SMitesh Ahuja u32 num_eq; 350b4dbe8d5SMitesh Ahuja struct ocrmda_set_eqd set_eqd[8]; 351b4dbe8d5SMitesh Ahuja } __packed; 352b4dbe8d5SMitesh Ahuja 353b4dbe8d5SMitesh Ahuja struct ocrdma_modify_eqd_req { 354b4dbe8d5SMitesh Ahuja struct ocrdma_mqe_hdr hdr; 355b4dbe8d5SMitesh Ahuja struct ocrdma_modify_eqd_cmd cmd; 356b4dbe8d5SMitesh Ahuja }; 357b4dbe8d5SMitesh Ahuja 358b4dbe8d5SMitesh Ahuja 359b4dbe8d5SMitesh Ahuja struct ocrdma_modify_eq_delay_rsp { 360b4dbe8d5SMitesh Ahuja struct ocrdma_mbx_rsp hdr; 361b4dbe8d5SMitesh Ahuja u32 rsvd0; 362b4dbe8d5SMitesh Ahuja } __packed; 363b4dbe8d5SMitesh Ahuja 364fe2caefcSParav Pandit enum { 365fe2caefcSParav Pandit OCRDMA_MCQE_STATUS_SHIFT = 0, 366fe2caefcSParav Pandit OCRDMA_MCQE_STATUS_MASK = 0xFFFF, 367fe2caefcSParav Pandit OCRDMA_MCQE_ESTATUS_SHIFT = 16, 368fe2caefcSParav Pandit OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT, 369fe2caefcSParav Pandit OCRDMA_MCQE_CONS_SHIFT = 27, 370de123485SJes Sorensen OCRDMA_MCQE_CONS_MASK = BIT(27), 371fe2caefcSParav Pandit OCRDMA_MCQE_CMPL_SHIFT = 28, 372de123485SJes Sorensen OCRDMA_MCQE_CMPL_MASK = BIT(28), 373fe2caefcSParav Pandit OCRDMA_MCQE_AE_SHIFT = 30, 374de123485SJes Sorensen OCRDMA_MCQE_AE_MASK = BIT(30), 375fe2caefcSParav Pandit OCRDMA_MCQE_VALID_SHIFT = 31, 376de123485SJes Sorensen OCRDMA_MCQE_VALID_MASK = BIT(31) 377fe2caefcSParav Pandit }; 378fe2caefcSParav Pandit 379fe2caefcSParav Pandit struct ocrdma_mcqe { 380fe2caefcSParav Pandit u32 status; 381fe2caefcSParav Pandit u32 tag_lo; 382fe2caefcSParav Pandit u32 tag_hi; 383fe2caefcSParav Pandit u32 valid_ae_cmpl_cons; 3847b9b1a59SNaresh Gottumukkala }; 385fe2caefcSParav Pandit 386fe2caefcSParav Pandit enum { 387de123485SJes Sorensen OCRDMA_AE_MCQE_QPVALID = BIT(31), 388fe2caefcSParav Pandit OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF, 389fe2caefcSParav Pandit 390de123485SJes Sorensen OCRDMA_AE_MCQE_CQVALID = BIT(31), 391fe2caefcSParav Pandit OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF, 392de123485SJes Sorensen OCRDMA_AE_MCQE_VALID = BIT(31), 393de123485SJes Sorensen OCRDMA_AE_MCQE_AE = BIT(30), 394fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16, 395fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_TYPE_MASK = 396fe2caefcSParav Pandit 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT, 397fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8, 398fe2caefcSParav Pandit OCRDMA_AE_MCQE_EVENT_CODE_MASK = 399fe2caefcSParav Pandit 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT 400fe2caefcSParav Pandit }; 401fe2caefcSParav Pandit struct ocrdma_ae_mcqe { 402fe2caefcSParav Pandit u32 qpvalid_qpid; 403fe2caefcSParav Pandit u32 cqvalid_cqid; 404fe2caefcSParav Pandit u32 evt_tag; 405fe2caefcSParav Pandit u32 valid_ae_event; 4067b9b1a59SNaresh Gottumukkala }; 407fe2caefcSParav Pandit 408fe2caefcSParav Pandit enum { 40984b105dbSNaresh Gottumukkala OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0, 41084b105dbSNaresh Gottumukkala OCRDMA_AE_PVID_MCQE_ENABLED_MASK = 0xFF, 41184b105dbSNaresh Gottumukkala OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16, 41284b105dbSNaresh Gottumukkala OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT 41384b105dbSNaresh Gottumukkala }; 41484b105dbSNaresh Gottumukkala 41584b105dbSNaresh Gottumukkala struct ocrdma_ae_pvid_mcqe { 41684b105dbSNaresh Gottumukkala u32 tag_enabled; 41784b105dbSNaresh Gottumukkala u32 event_tag; 41884b105dbSNaresh Gottumukkala u32 rsvd1; 41984b105dbSNaresh Gottumukkala u32 rsvd2; 42084b105dbSNaresh Gottumukkala }; 42184b105dbSNaresh Gottumukkala 42284b105dbSNaresh Gottumukkala enum { 423fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16, 424fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF << 425fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT, 426fe2caefcSParav Pandit 427fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8, 428fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF << 429fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT, 430fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16, 431fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF << 432fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT, 433fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30, 434de123485SJes Sorensen OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = BIT(30), 435fe2caefcSParav Pandit OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31, 436de123485SJes Sorensen OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = BIT(31) 437fe2caefcSParav Pandit }; 438fe2caefcSParav Pandit 439fe2caefcSParav Pandit struct ocrdma_ae_mpa_mcqe { 440fe2caefcSParav Pandit u32 req_id; 441fe2caefcSParav Pandit u32 w1; 442fe2caefcSParav Pandit u32 w2; 443fe2caefcSParav Pandit u32 valid_ae_event; 4447b9b1a59SNaresh Gottumukkala }; 445fe2caefcSParav Pandit 446fe2caefcSParav Pandit enum { 447fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0, 448fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF, 449fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16, 450fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF << 451fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_QP_ID_SHIFT, 452fe2caefcSParav Pandit 453fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8, 454fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF << 455fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT, 456fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16, 457fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF << 458fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT, 459fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30, 460de123485SJes Sorensen OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = BIT(30), 461fe2caefcSParav Pandit OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31, 462de123485SJes Sorensen OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = BIT(31) 463fe2caefcSParav Pandit }; 464fe2caefcSParav Pandit 465fe2caefcSParav Pandit struct ocrdma_ae_qp_mcqe { 466fe2caefcSParav Pandit u32 qp_id_state; 467fe2caefcSParav Pandit u32 w1; 468fe2caefcSParav Pandit u32 w2; 469fe2caefcSParav Pandit u32 valid_ae_event; 4707b9b1a59SNaresh Gottumukkala }; 471fe2caefcSParav Pandit 47210a214dcSDevesh Sharma enum ocrdma_async_event_code { 47310a214dcSDevesh Sharma OCRDMA_ASYNC_LINK_EVE_CODE = 0x01, 47410a214dcSDevesh Sharma OCRDMA_ASYNC_GRP5_EVE_CODE = 0x05, 47510a214dcSDevesh Sharma OCRDMA_ASYNC_RDMA_EVE_CODE = 0x14 47610a214dcSDevesh Sharma }; 47731dbdd9aSSelvin Xavier 47831dbdd9aSSelvin Xavier enum ocrdma_async_grp5_events { 47931dbdd9aSSelvin Xavier OCRDMA_ASYNC_EVENT_QOS_VALUE = 0x01, 48031dbdd9aSSelvin Xavier OCRDMA_ASYNC_EVENT_COS_VALUE = 0x02, 48131dbdd9aSSelvin Xavier OCRDMA_ASYNC_EVENT_PVID_STATE = 0x03 48231dbdd9aSSelvin Xavier }; 483fe2caefcSParav Pandit 484fe2caefcSParav Pandit enum OCRDMA_ASYNC_EVENT_TYPE { 485fe2caefcSParav Pandit OCRDMA_CQ_ERROR = 0x00, 486fe2caefcSParav Pandit OCRDMA_CQ_OVERRUN_ERROR = 0x01, 487fe2caefcSParav Pandit OCRDMA_CQ_QPCAT_ERROR = 0x02, 488fe2caefcSParav Pandit OCRDMA_QP_ACCESS_ERROR = 0x03, 489fe2caefcSParav Pandit OCRDMA_QP_COMM_EST_EVENT = 0x04, 490fe2caefcSParav Pandit OCRDMA_SQ_DRAINED_EVENT = 0x05, 491fe2caefcSParav Pandit OCRDMA_DEVICE_FATAL_EVENT = 0x08, 492fe2caefcSParav Pandit OCRDMA_SRQCAT_ERROR = 0x0E, 493fe2caefcSParav Pandit OCRDMA_SRQ_LIMIT_EVENT = 0x0F, 494ad56ebb4SSelvin Xavier OCRDMA_QP_LAST_WQE_EVENT = 0x10, 495ad56ebb4SSelvin Xavier 496ad56ebb4SSelvin Xavier OCRDMA_MAX_ASYNC_ERRORS 497fe2caefcSParav Pandit }; 498fe2caefcSParav Pandit 49910a214dcSDevesh Sharma struct ocrdma_ae_lnkst_mcqe { 50010a214dcSDevesh Sharma u32 speed_state_ptn; 50110a214dcSDevesh Sharma u32 qos_reason_falut; 50210a214dcSDevesh Sharma u32 evt_tag; 50310a214dcSDevesh Sharma u32 valid_ae_event; 50410a214dcSDevesh Sharma }; 50510a214dcSDevesh Sharma 50610a214dcSDevesh Sharma enum { 50710a214dcSDevesh Sharma OCRDMA_AE_LSC_PORT_NUM_MASK = 0x3F, 50810a214dcSDevesh Sharma OCRDMA_AE_LSC_PT_SHIFT = 0x06, 50910a214dcSDevesh Sharma OCRDMA_AE_LSC_PT_MASK = (0x03 << 51010a214dcSDevesh Sharma OCRDMA_AE_LSC_PT_SHIFT), 51110a214dcSDevesh Sharma OCRDMA_AE_LSC_LS_SHIFT = 0x08, 51210a214dcSDevesh Sharma OCRDMA_AE_LSC_LS_MASK = (0xFF << 51310a214dcSDevesh Sharma OCRDMA_AE_LSC_LS_SHIFT), 51410a214dcSDevesh Sharma OCRDMA_AE_LSC_LD_SHIFT = 0x10, 51510a214dcSDevesh Sharma OCRDMA_AE_LSC_LD_MASK = (0xFF << 51610a214dcSDevesh Sharma OCRDMA_AE_LSC_LD_SHIFT), 51710a214dcSDevesh Sharma OCRDMA_AE_LSC_PPS_SHIFT = 0x18, 51810a214dcSDevesh Sharma OCRDMA_AE_LSC_PPS_MASK = (0xFF << 51910a214dcSDevesh Sharma OCRDMA_AE_LSC_PPS_SHIFT), 52010a214dcSDevesh Sharma OCRDMA_AE_LSC_PPF_MASK = 0xFF, 52110a214dcSDevesh Sharma OCRDMA_AE_LSC_ER_SHIFT = 0x08, 52210a214dcSDevesh Sharma OCRDMA_AE_LSC_ER_MASK = (0xFF << 52310a214dcSDevesh Sharma OCRDMA_AE_LSC_ER_SHIFT), 52410a214dcSDevesh Sharma OCRDMA_AE_LSC_QOS_SHIFT = 0x10, 52510a214dcSDevesh Sharma OCRDMA_AE_LSC_QOS_MASK = (0xFFFF << 52610a214dcSDevesh Sharma OCRDMA_AE_LSC_QOS_SHIFT) 52710a214dcSDevesh Sharma }; 52810a214dcSDevesh Sharma 52910a214dcSDevesh Sharma enum { 53010a214dcSDevesh Sharma OCRDMA_AE_LSC_PLINK_DOWN = 0x00, 53110a214dcSDevesh Sharma OCRDMA_AE_LSC_PLINK_UP = 0x01, 53210a214dcSDevesh Sharma OCRDMA_AE_LSC_LLINK_DOWN = 0x02, 53310a214dcSDevesh Sharma OCRDMA_AE_LSC_LLINK_MASK = 0x02, 53410a214dcSDevesh Sharma OCRDMA_AE_LSC_LLINK_UP = 0x03 53510a214dcSDevesh Sharma }; 53610a214dcSDevesh Sharma 537fe2caefcSParav Pandit /* mailbox command request and responses */ 538fe2caefcSParav Pandit enum { 539fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2, 540de123485SJes Sorensen OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = BIT(2), 541fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3, 542de123485SJes Sorensen OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = BIT(3), 543fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8, 544fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF << 545fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT, 546fe2caefcSParav Pandit 547fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16, 548fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF << 549fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT, 550fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8, 551fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF << 552fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT, 553e1614869SSomnath Kotur OCRDMA_MBX_QUERY_CFG_L3_TYPE_SHIFT = 3, 554e1614869SSomnath Kotur OCRDMA_MBX_QUERY_CFG_L3_TYPE_MASK = 0x18, 555fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0, 556fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF, 5573c199b45SSelvin Xavier OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT = 16, 5583c199b45SSelvin Xavier OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_MASK = 0xFFFF << 5593c199b45SSelvin Xavier OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT, 560fe2caefcSParav Pandit 561fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0, 562fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF, 563fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16, 564fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF << 565fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT, 566fe2caefcSParav Pandit 567fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24, 568fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF << 569fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET, 570fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16, 571fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF << 572fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET, 573fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0, 574fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF << 575fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET, 576fe2caefcSParav Pandit 577fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16, 578fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF << 579fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET, 580fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0, 581fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF << 582fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET, 583fe2caefcSParav Pandit 584fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16, 585fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF << 586fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET, 587fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0, 588fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF << 589fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET, 590fe2caefcSParav Pandit 591fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0, 592fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF << 593fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET, 594fe2caefcSParav Pandit 595fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16, 596fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF << 597fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET, 598fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0, 599fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF << 60007bb5424SMahesh Vardhamanaiah OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET, 601fe2caefcSParav Pandit 602fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16, 603fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF << 604fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET, 605fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0, 606fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF << 607fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET, 608fe2caefcSParav Pandit 609fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16, 610fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF << 611fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET, 612fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0, 613fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF << 614fe2caefcSParav Pandit OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET, 6153c199b45SSelvin Xavier OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_SHIFT = 0, 6163c199b45SSelvin Xavier OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_MASK = 0xFFFF, 617fe2caefcSParav Pandit }; 618fe2caefcSParav Pandit 619fe2caefcSParav Pandit struct ocrdma_mbx_query_config { 620fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 621fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 622fe2caefcSParav Pandit u32 qp_srq_cq_ird_ord; 623fe2caefcSParav Pandit u32 max_pd_ca_ack_delay; 6243c199b45SSelvin Xavier u32 max_recv_send_sge; 625fe2caefcSParav Pandit u32 max_ird_ord_per_qp; 626fe2caefcSParav Pandit u32 max_shared_ird_ord; 627fe2caefcSParav Pandit u32 max_mr; 6287b9b1a59SNaresh Gottumukkala u32 max_mr_size_hi; 629033edd4dSMitesh Ahuja u32 max_mr_size_lo; 630fe2caefcSParav Pandit u32 max_num_mr_pbl; 631fe2caefcSParav Pandit u32 max_mw; 632fe2caefcSParav Pandit u32 max_fmr; 633fe2caefcSParav Pandit u32 max_pages_per_frmr; 634fe2caefcSParav Pandit u32 max_mcast_group; 635fe2caefcSParav Pandit u32 max_mcast_qp_attach; 636fe2caefcSParav Pandit u32 max_total_mcast_qp_attach; 637fe2caefcSParav Pandit u32 wqe_rqe_stride_max_dpp_cqs; 638fe2caefcSParav Pandit u32 max_srq_rpir_qps; 639fe2caefcSParav Pandit u32 max_dpp_pds_credits; 640fe2caefcSParav Pandit u32 max_dpp_credits_pds_per_pd; 641fe2caefcSParav Pandit u32 max_wqes_rqes_per_q; 642fe2caefcSParav Pandit u32 max_cq_cqes_per_cq; 643fe2caefcSParav Pandit u32 max_srq_rqe_sge; 6443c199b45SSelvin Xavier u32 max_wr_rd_sge; 6453c199b45SSelvin Xavier u32 ird_pgsz_num_pages; 6467b9b1a59SNaresh Gottumukkala }; 647fe2caefcSParav Pandit 648fe2caefcSParav Pandit struct ocrdma_fw_ver_rsp { 649fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 650fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 651fe2caefcSParav Pandit 652fe2caefcSParav Pandit u8 running_ver[32]; 6537b9b1a59SNaresh Gottumukkala }; 654fe2caefcSParav Pandit 655fe2caefcSParav Pandit struct ocrdma_fw_conf_rsp { 656fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 657fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 658fe2caefcSParav Pandit 659fe2caefcSParav Pandit u32 config_num; 660fe2caefcSParav Pandit u32 asic_revision; 661fe2caefcSParav Pandit u32 phy_port; 662fe2caefcSParav Pandit u32 fn_mode; 663fe2caefcSParav Pandit struct { 664fe2caefcSParav Pandit u32 mode; 665fe2caefcSParav Pandit u32 nic_wqid_base; 666fe2caefcSParav Pandit u32 nic_wq_tot; 667fe2caefcSParav Pandit u32 prot_wqid_base; 668fe2caefcSParav Pandit u32 prot_wq_tot; 669fe2caefcSParav Pandit u32 prot_rqid_base; 670fe2caefcSParav Pandit u32 prot_rqid_tot; 671fe2caefcSParav Pandit u32 rsvd[6]; 672fe2caefcSParav Pandit } ulp[2]; 673fe2caefcSParav Pandit u32 fn_capabilities; 674fe2caefcSParav Pandit u32 rsvd1; 675fe2caefcSParav Pandit u32 rsvd2; 676fe2caefcSParav Pandit u32 base_eqid; 677fe2caefcSParav Pandit u32 max_eq; 678fe2caefcSParav Pandit 6797b9b1a59SNaresh Gottumukkala }; 680fe2caefcSParav Pandit 681fe2caefcSParav Pandit enum { 682fe2caefcSParav Pandit OCRDMA_FN_MODE_RDMA = 0x4 683fe2caefcSParav Pandit }; 684fe2caefcSParav Pandit 6858ac0c7c7SDevesh Sharma enum { 6868ac0c7c7SDevesh Sharma OCRDMA_IF_TYPE_MASK = 0xFFFF0000, 6878ac0c7c7SDevesh Sharma OCRDMA_IF_TYPE_SHIFT = 0x10, 6888ac0c7c7SDevesh Sharma OCRDMA_PHY_TYPE_MASK = 0x0000FFFF, 6898ac0c7c7SDevesh Sharma OCRDMA_FUTURE_DETAILS_MASK = 0xFFFF0000, 6908ac0c7c7SDevesh Sharma OCRDMA_FUTURE_DETAILS_SHIFT = 0x10, 6918ac0c7c7SDevesh Sharma OCRDMA_EX_PHY_DETAILS_MASK = 0x0000FFFF, 6928ac0c7c7SDevesh Sharma OCRDMA_FSPEED_SUPP_MASK = 0xFFFF0000, 6938ac0c7c7SDevesh Sharma OCRDMA_FSPEED_SUPP_SHIFT = 0x10, 6948ac0c7c7SDevesh Sharma OCRDMA_ASPEED_SUPP_MASK = 0x0000FFFF 6958ac0c7c7SDevesh Sharma }; 6968ac0c7c7SDevesh Sharma 697a51f06e1SSelvin Xavier struct ocrdma_get_phy_info_rsp { 698a51f06e1SSelvin Xavier struct ocrdma_mqe_hdr hdr; 699a51f06e1SSelvin Xavier struct ocrdma_mbx_rsp rsp; 700a51f06e1SSelvin Xavier 7018ac0c7c7SDevesh Sharma u32 ityp_ptyp; 702a51f06e1SSelvin Xavier u32 misc_params; 7038ac0c7c7SDevesh Sharma u32 ftrdtl_exphydtl; 7048ac0c7c7SDevesh Sharma u32 fspeed_aspeed; 705a51f06e1SSelvin Xavier u32 future_use[2]; 706a51f06e1SSelvin Xavier }; 707a51f06e1SSelvin Xavier 708a51f06e1SSelvin Xavier enum { 709a51f06e1SSelvin Xavier OCRDMA_PHY_SPEED_ZERO = 0x0, 710a51f06e1SSelvin Xavier OCRDMA_PHY_SPEED_10MBPS = 0x1, 711a51f06e1SSelvin Xavier OCRDMA_PHY_SPEED_100MBPS = 0x2, 712a51f06e1SSelvin Xavier OCRDMA_PHY_SPEED_1GBPS = 0x4, 713a51f06e1SSelvin Xavier OCRDMA_PHY_SPEED_10GBPS = 0x8, 714a51f06e1SSelvin Xavier OCRDMA_PHY_SPEED_40GBPS = 0x20 715a51f06e1SSelvin Xavier }; 716a51f06e1SSelvin Xavier 7178ac0c7c7SDevesh Sharma enum { 7188ac0c7c7SDevesh Sharma OCRDMA_PORT_NUM_MASK = 0x3F, 7198ac0c7c7SDevesh Sharma OCRDMA_PT_MASK = 0xC0, 7208ac0c7c7SDevesh Sharma OCRDMA_PT_SHIFT = 0x6, 7218ac0c7c7SDevesh Sharma OCRDMA_LINK_DUP_MASK = 0x0000FF00, 7228ac0c7c7SDevesh Sharma OCRDMA_LINK_DUP_SHIFT = 0x8, 7238ac0c7c7SDevesh Sharma OCRDMA_PHY_PS_MASK = 0x00FF0000, 7248ac0c7c7SDevesh Sharma OCRDMA_PHY_PS_SHIFT = 0x10, 7258ac0c7c7SDevesh Sharma OCRDMA_PHY_PFLT_MASK = 0xFF000000, 7268ac0c7c7SDevesh Sharma OCRDMA_PHY_PFLT_SHIFT = 0x18, 7278ac0c7c7SDevesh Sharma OCRDMA_QOS_LNKSP_MASK = 0xFFFF0000, 7288ac0c7c7SDevesh Sharma OCRDMA_QOS_LNKSP_SHIFT = 0x10, 72910a214dcSDevesh Sharma OCRDMA_LINK_ST_MASK = 0x01, 7308ac0c7c7SDevesh Sharma OCRDMA_PLFC_MASK = 0x00000400, 7318ac0c7c7SDevesh Sharma OCRDMA_PLFC_SHIFT = 0x8, 7328ac0c7c7SDevesh Sharma OCRDMA_PLRFC_MASK = 0x00000200, 7338ac0c7c7SDevesh Sharma OCRDMA_PLRFC_SHIFT = 0x8, 7348ac0c7c7SDevesh Sharma OCRDMA_PLTFC_MASK = 0x00000100, 7358ac0c7c7SDevesh Sharma OCRDMA_PLTFC_SHIFT = 0x8 7368ac0c7c7SDevesh Sharma }; 737a51f06e1SSelvin Xavier 738f24ceba6SNaresh Gottumukkala struct ocrdma_get_link_speed_rsp { 739f24ceba6SNaresh Gottumukkala struct ocrdma_mqe_hdr hdr; 740f24ceba6SNaresh Gottumukkala struct ocrdma_mbx_rsp rsp; 741f24ceba6SNaresh Gottumukkala 7428ac0c7c7SDevesh Sharma u32 pflt_pps_ld_pnum; 7438ac0c7c7SDevesh Sharma u32 qos_lsp; 74410a214dcSDevesh Sharma u32 res_lnk_st; 745f24ceba6SNaresh Gottumukkala }; 746f24ceba6SNaresh Gottumukkala 747f24ceba6SNaresh Gottumukkala enum { 748f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0, 749f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1, 750f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2, 751f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3, 752f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4, 753f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5, 754f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6, 755f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7, 756f24ceba6SNaresh Gottumukkala OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8 757f24ceba6SNaresh Gottumukkala }; 758f24ceba6SNaresh Gottumukkala 759fe2caefcSParav Pandit enum { 760fe2caefcSParav Pandit OCRDMA_CREATE_CQ_VER2 = 2, 761cffce990SNaresh Gottumukkala OCRDMA_CREATE_CQ_VER3 = 3, 762fe2caefcSParav Pandit 763fe2caefcSParav Pandit OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF, 764fe2caefcSParav Pandit OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16, 765fe2caefcSParav Pandit OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF, 766fe2caefcSParav Pandit 767fe2caefcSParav Pandit OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12, 768de123485SJes Sorensen OCRDMA_CREATE_CQ_COALESCWM_MASK = BIT(13) | BIT(12), 769de123485SJes Sorensen OCRDMA_CREATE_CQ_FLAGS_NODELAY = BIT(14), 770de123485SJes Sorensen OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = BIT(15), 771fe2caefcSParav Pandit 772fe2caefcSParav Pandit OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF, 773fe2caefcSParav Pandit OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF 774fe2caefcSParav Pandit }; 775fe2caefcSParav Pandit 776fe2caefcSParav Pandit enum { 777fe2caefcSParav Pandit OCRDMA_CREATE_CQ_VER0 = 0, 778fe2caefcSParav Pandit OCRDMA_CREATE_CQ_DPP = 1, 779fe2caefcSParav Pandit OCRDMA_CREATE_CQ_TYPE_SHIFT = 24, 780fe2caefcSParav Pandit OCRDMA_CREATE_CQ_EQID_SHIFT = 22, 781fe2caefcSParav Pandit 782fe2caefcSParav Pandit OCRDMA_CREATE_CQ_CNT_SHIFT = 27, 783de123485SJes Sorensen OCRDMA_CREATE_CQ_FLAGS_VALID = BIT(29), 784de123485SJes Sorensen OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = BIT(31), 785fe2caefcSParav Pandit OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID | 786fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_EVENTABLE | 787fe2caefcSParav Pandit OCRDMA_CREATE_CQ_FLAGS_NODELAY 788fe2caefcSParav Pandit }; 789fe2caefcSParav Pandit 790fe2caefcSParav Pandit struct ocrdma_create_cq_cmd { 791fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 792fe2caefcSParav Pandit u32 pgsz_pgcnt; 793fe2caefcSParav Pandit u32 ev_cnt_flags; 794fe2caefcSParav Pandit u32 eqn; 7958ac0c7c7SDevesh Sharma u32 pdid_cqecnt; 796fe2caefcSParav Pandit u32 rsvd6; 797fe2caefcSParav Pandit struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES]; 798fe2caefcSParav Pandit }; 799fe2caefcSParav Pandit 800fe2caefcSParav Pandit struct ocrdma_create_cq { 801fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 802fe2caefcSParav Pandit struct ocrdma_create_cq_cmd cmd; 8037b9b1a59SNaresh Gottumukkala }; 804fe2caefcSParav Pandit 805fe2caefcSParav Pandit enum { 8068ac0c7c7SDevesh Sharma OCRDMA_CREATE_CQ_CMD_PDID_SHIFT = 0x10 8078ac0c7c7SDevesh Sharma }; 8088ac0c7c7SDevesh Sharma 8098ac0c7c7SDevesh Sharma enum { 810fe2caefcSParav Pandit OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF 811fe2caefcSParav Pandit }; 812fe2caefcSParav Pandit 813fe2caefcSParav Pandit struct ocrdma_create_cq_cmd_rsp { 814fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 815fe2caefcSParav Pandit u32 cq_id; 8167b9b1a59SNaresh Gottumukkala }; 817fe2caefcSParav Pandit 818fe2caefcSParav Pandit struct ocrdma_create_cq_rsp { 819fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 820fe2caefcSParav Pandit struct ocrdma_create_cq_cmd_rsp rsp; 8217b9b1a59SNaresh Gottumukkala }; 822fe2caefcSParav Pandit 823fe2caefcSParav Pandit enum { 824fe2caefcSParav Pandit OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22, 825fe2caefcSParav Pandit OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16, 826fe2caefcSParav Pandit OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16, 827de123485SJes Sorensen OCRDMA_CREATE_MQ_VALID = BIT(31), 828de123485SJes Sorensen OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = BIT(0) 829fe2caefcSParav Pandit }; 830fe2caefcSParav Pandit 831b1d58b99SNaresh Gottumukkala struct ocrdma_create_mq_req { 832b1d58b99SNaresh Gottumukkala struct ocrdma_mbx_hdr req; 833fe2caefcSParav Pandit u32 cqid_pages; 834fe2caefcSParav Pandit u32 async_event_bitmap; 835fe2caefcSParav Pandit u32 async_cqid_ringsize; 836fe2caefcSParav Pandit u32 valid; 837fe2caefcSParav Pandit u32 async_cqid_valid; 838fe2caefcSParav Pandit u32 rsvd; 839fe2caefcSParav Pandit struct ocrdma_pa pa[8]; 8407b9b1a59SNaresh Gottumukkala }; 841fe2caefcSParav Pandit 842fe2caefcSParav Pandit struct ocrdma_create_mq_rsp { 843fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 844fe2caefcSParav Pandit u32 id; 8457b9b1a59SNaresh Gottumukkala }; 846fe2caefcSParav Pandit 847fe2caefcSParav Pandit enum { 848fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_SHIFT = 0, 849fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF, 850fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16, 851fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF << 852fe2caefcSParav Pandit OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT 853fe2caefcSParav Pandit }; 854fe2caefcSParav Pandit 855fe2caefcSParav Pandit struct ocrdma_destroy_cq { 856fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 857fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 858fe2caefcSParav Pandit 859fe2caefcSParav Pandit u32 bypass_flush_qid; 8607b9b1a59SNaresh Gottumukkala }; 861fe2caefcSParav Pandit 862fe2caefcSParav Pandit struct ocrdma_destroy_cq_rsp { 863fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 864fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 8657b9b1a59SNaresh Gottumukkala }; 866fe2caefcSParav Pandit 867fe2caefcSParav Pandit enum { 868fe2caefcSParav Pandit OCRDMA_QPT_GSI = 1, 869fe2caefcSParav Pandit OCRDMA_QPT_RC = 2, 870fe2caefcSParav Pandit OCRDMA_QPT_UD = 4, 871fe2caefcSParav Pandit }; 872fe2caefcSParav Pandit 873fe2caefcSParav Pandit enum { 874fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0, 875fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF, 876fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16, 877fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19, 878fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29, 879de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_QPT_MASK = BIT(31) | BIT(30) | BIT(29), 880fe2caefcSParav Pandit 881fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0, 882fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF, 883fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16, 884fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF << 885fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT, 886fe2caefcSParav Pandit 887fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0, 888fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF, 889fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16, 890fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF << 891fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT, 892fe2caefcSParav Pandit 893fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0, 894de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = BIT(0), 895fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1, 896de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = BIT(1), 897fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2, 898de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = BIT(2), 899fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3, 900de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = BIT(3), 901fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4, 902de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = BIT(4), 903fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5, 904de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = BIT(5), 905fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6, 906de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = BIT(6), 907fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7, 908de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = BIT(7), 909fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8, 910de123485SJes Sorensen OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = BIT(8), 911fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16, 912fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF << 913fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT, 914fe2caefcSParav Pandit 915fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0, 916fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF, 917fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16, 918fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF << 919fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT, 920fe2caefcSParav Pandit 921fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0, 922fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF, 923fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16, 924fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF << 925fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT, 926fe2caefcSParav Pandit 927fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0, 928fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF, 929fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16, 930fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF << 931fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT, 932fe2caefcSParav Pandit 933fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0, 934fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF, 935fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16, 936fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF << 937fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT, 938fe2caefcSParav Pandit 939fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0, 940fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF, 941fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16, 942fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF << 943fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT 944fe2caefcSParav Pandit }; 945fe2caefcSParav Pandit 946fe2caefcSParav Pandit enum { 947fe2caefcSParav Pandit OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16, 948fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1 949fe2caefcSParav Pandit }; 950fe2caefcSParav Pandit 951fe2caefcSParav Pandit #define MAX_OCRDMA_IRD_PAGES 4 952fe2caefcSParav Pandit 953fe2caefcSParav Pandit enum ocrdma_qp_flags { 954fe2caefcSParav Pandit OCRDMA_QP_MW_BIND = 1, 955fe2caefcSParav Pandit OCRDMA_QP_LKEY0 = (1 << 1), 956fe2caefcSParav Pandit OCRDMA_QP_FAST_REG = (1 << 2), 957fe2caefcSParav Pandit OCRDMA_QP_INB_RD = (1 << 6), 958fe2caefcSParav Pandit OCRDMA_QP_INB_WR = (1 << 7), 959fe2caefcSParav Pandit }; 960fe2caefcSParav Pandit 961fe2caefcSParav Pandit enum ocrdma_qp_state { 962fe2caefcSParav Pandit OCRDMA_QPS_RST = 0, 963fe2caefcSParav Pandit OCRDMA_QPS_INIT = 1, 964fe2caefcSParav Pandit OCRDMA_QPS_RTR = 2, 965fe2caefcSParav Pandit OCRDMA_QPS_RTS = 3, 966fe2caefcSParav Pandit OCRDMA_QPS_SQE = 4, 967fe2caefcSParav Pandit OCRDMA_QPS_SQ_DRAINING = 5, 968fe2caefcSParav Pandit OCRDMA_QPS_ERR = 6, 969fe2caefcSParav Pandit OCRDMA_QPS_SQD = 7 970fe2caefcSParav Pandit }; 971fe2caefcSParav Pandit 972fe2caefcSParav Pandit struct ocrdma_create_qp_req { 973fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 974fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 975fe2caefcSParav Pandit 976fe2caefcSParav Pandit u32 type_pgsz_pdn; 977fe2caefcSParav Pandit u32 max_wqe_rqe; 978fe2caefcSParav Pandit u32 max_sge_send_write; 979fe2caefcSParav Pandit u32 max_sge_recv_flags; 980fe2caefcSParav Pandit u32 max_ord_ird; 981fe2caefcSParav Pandit u32 num_wq_rq_pages; 982fe2caefcSParav Pandit u32 wqe_rqe_size; 983fe2caefcSParav Pandit u32 wq_rq_cqid; 984fe2caefcSParav Pandit struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES]; 985fe2caefcSParav Pandit struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES]; 986fe2caefcSParav Pandit u32 dpp_credits_cqid; 987fe2caefcSParav Pandit u32 rpir_lkey; 988fe2caefcSParav Pandit struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES]; 9897b9b1a59SNaresh Gottumukkala }; 990fe2caefcSParav Pandit 991fe2caefcSParav Pandit enum { 992fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0, 993fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF, 994fe2caefcSParav Pandit 995fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0, 996fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF, 997fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16, 998fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF << 999fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT, 1000fe2caefcSParav Pandit 1001fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0, 1002fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF, 1003fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16, 1004fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF << 1005fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT, 1006fe2caefcSParav Pandit 1007fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16, 1008fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF << 1009fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT, 1010fe2caefcSParav Pandit 1011fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0, 1012fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF, 1013fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16, 1014fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF << 1015fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT, 1016fe2caefcSParav Pandit 1017fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0, 1018fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF, 1019fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16, 1020fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF << 1021fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT, 1022fe2caefcSParav Pandit 1023de123485SJes Sorensen OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = BIT(0), 1024fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1, 1025fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF << 1026fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT, 1027fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16, 1028fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF << 1029fe2caefcSParav Pandit OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT, 1030fe2caefcSParav Pandit }; 1031fe2caefcSParav Pandit 1032fe2caefcSParav Pandit struct ocrdma_create_qp_rsp { 1033fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1034fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1035fe2caefcSParav Pandit 1036fe2caefcSParav Pandit u32 qp_id; 1037fe2caefcSParav Pandit u32 max_wqe_rqe; 1038fe2caefcSParav Pandit u32 max_sge_send_write; 1039fe2caefcSParav Pandit u32 max_sge_recv; 1040fe2caefcSParav Pandit u32 max_ord_ird; 1041fe2caefcSParav Pandit u32 sq_rq_id; 1042fe2caefcSParav Pandit u32 dpp_response; 10437b9b1a59SNaresh Gottumukkala }; 1044fe2caefcSParav Pandit 1045fe2caefcSParav Pandit struct ocrdma_destroy_qp { 1046fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1047fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1048fe2caefcSParav Pandit u32 qp_id; 10497b9b1a59SNaresh Gottumukkala }; 1050fe2caefcSParav Pandit 1051fe2caefcSParav Pandit struct ocrdma_destroy_qp_rsp { 1052fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1053fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 10547b9b1a59SNaresh Gottumukkala }; 1055fe2caefcSParav Pandit 1056fe2caefcSParav Pandit enum { 1057fe2caefcSParav Pandit OCRDMA_MODIFY_QP_ID_SHIFT = 0, 1058fe2caefcSParav Pandit OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF, 1059fe2caefcSParav Pandit 1060de123485SJes Sorensen OCRDMA_QP_PARA_QPS_VALID = BIT(0), 1061de123485SJes Sorensen OCRDMA_QP_PARA_SQD_ASYNC_VALID = BIT(1), 1062de123485SJes Sorensen OCRDMA_QP_PARA_PKEY_VALID = BIT(2), 1063de123485SJes Sorensen OCRDMA_QP_PARA_QKEY_VALID = BIT(3), 1064de123485SJes Sorensen OCRDMA_QP_PARA_PMTU_VALID = BIT(4), 1065de123485SJes Sorensen OCRDMA_QP_PARA_ACK_TO_VALID = BIT(5), 1066de123485SJes Sorensen OCRDMA_QP_PARA_RETRY_CNT_VALID = BIT(6), 1067de123485SJes Sorensen OCRDMA_QP_PARA_RRC_VALID = BIT(7), 1068de123485SJes Sorensen OCRDMA_QP_PARA_RQPSN_VALID = BIT(8), 1069de123485SJes Sorensen OCRDMA_QP_PARA_MAX_IRD_VALID = BIT(9), 1070de123485SJes Sorensen OCRDMA_QP_PARA_MAX_ORD_VALID = BIT(10), 1071de123485SJes Sorensen OCRDMA_QP_PARA_RNT_VALID = BIT(11), 1072de123485SJes Sorensen OCRDMA_QP_PARA_SQPSN_VALID = BIT(12), 1073de123485SJes Sorensen OCRDMA_QP_PARA_DST_QPN_VALID = BIT(13), 1074de123485SJes Sorensen OCRDMA_QP_PARA_MAX_WQE_VALID = BIT(14), 1075de123485SJes Sorensen OCRDMA_QP_PARA_MAX_RQE_VALID = BIT(15), 1076de123485SJes Sorensen OCRDMA_QP_PARA_SGE_SEND_VALID = BIT(16), 1077de123485SJes Sorensen OCRDMA_QP_PARA_SGE_RECV_VALID = BIT(17), 1078de123485SJes Sorensen OCRDMA_QP_PARA_SGE_WR_VALID = BIT(18), 1079de123485SJes Sorensen OCRDMA_QP_PARA_INB_RDEN_VALID = BIT(19), 1080de123485SJes Sorensen OCRDMA_QP_PARA_INB_WREN_VALID = BIT(20), 1081de123485SJes Sorensen OCRDMA_QP_PARA_FLOW_LBL_VALID = BIT(21), 1082de123485SJes Sorensen OCRDMA_QP_PARA_BIND_EN_VALID = BIT(22), 1083de123485SJes Sorensen OCRDMA_QP_PARA_ZLKEY_EN_VALID = BIT(23), 1084de123485SJes Sorensen OCRDMA_QP_PARA_FMR_EN_VALID = BIT(24), 1085de123485SJes Sorensen OCRDMA_QP_PARA_INBAT_EN_VALID = BIT(25), 1086de123485SJes Sorensen OCRDMA_QP_PARA_VLAN_EN_VALID = BIT(26), 1087fe2caefcSParav Pandit 1088de123485SJes Sorensen OCRDMA_MODIFY_QP_FLAGS_RD = BIT(0), 1089de123485SJes Sorensen OCRDMA_MODIFY_QP_FLAGS_WR = BIT(1), 1090de123485SJes Sorensen OCRDMA_MODIFY_QP_FLAGS_SEND = BIT(2), 1091de123485SJes Sorensen OCRDMA_MODIFY_QP_FLAGS_ATOMIC = BIT(3) 1092fe2caefcSParav Pandit }; 1093fe2caefcSParav Pandit 1094fe2caefcSParav Pandit enum { 1095fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0, 1096fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF, 1097fe2caefcSParav Pandit 1098fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0, 1099fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF, 1100fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16, 1101fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF << 1102fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_WQE_SHIFT, 1103fe2caefcSParav Pandit 1104fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0, 1105fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF, 1106fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16, 1107fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF << 1108fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT, 1109fe2caefcSParav Pandit 1110de123485SJes Sorensen OCRDMA_QP_PARAMS_FLAGS_FMR_EN = BIT(0), 1111de123485SJes Sorensen OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = BIT(1), 1112de123485SJes Sorensen OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = BIT(2), 1113de123485SJes Sorensen OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = BIT(3), 1114de123485SJes Sorensen OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = BIT(4), 1115fe2caefcSParav Pandit OCRDMA_QP_PARAMS_STATE_SHIFT = 5, 1116de123485SJes Sorensen OCRDMA_QP_PARAMS_STATE_MASK = BIT(5) | BIT(6) | BIT(7), 1117de123485SJes Sorensen OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = BIT(8), 1118de123485SJes Sorensen OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = BIT(9), 1119bcf117e2SDevesh Sharma OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_SHIFT = 11, 1120bcf117e2SDevesh Sharma OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK = BIT(11) | BIT(12) | BIT(13), 1121fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16, 1122fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF << 1123fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT, 1124fe2caefcSParav Pandit 1125fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0, 1126fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF, 1127fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16, 1128fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF << 1129fe2caefcSParav Pandit OCRDMA_QP_PARAMS_MAX_ORD_SHIFT, 1130fe2caefcSParav Pandit 1131fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0, 1132fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF, 1133fe2caefcSParav Pandit OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16, 1134fe2caefcSParav Pandit OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF << 1135fe2caefcSParav Pandit OCRDMA_QP_PARAMS_WQ_CQID_SHIFT, 1136fe2caefcSParav Pandit 1137fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0, 1138fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF, 1139fe2caefcSParav Pandit OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24, 1140fe2caefcSParav Pandit OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF << 1141fe2caefcSParav Pandit OCRDMA_QP_PARAMS_HOP_LMT_SHIFT, 1142fe2caefcSParav Pandit 1143fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0, 1144fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF, 1145fe2caefcSParav Pandit OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24, 1146fe2caefcSParav Pandit OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF << 1147fe2caefcSParav Pandit OCRDMA_QP_PARAMS_TCLASS_SHIFT, 1148fe2caefcSParav Pandit 1149fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0, 1150fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF, 1151fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24, 1152fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 << 1153fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT, 1154fe2caefcSParav Pandit OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27, 1155fe2caefcSParav Pandit OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F << 1156fe2caefcSParav Pandit OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT, 1157fe2caefcSParav Pandit 1158fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0, 1159fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF, 1160fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18, 1161fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF << 1162fe2caefcSParav Pandit OCRDMA_QP_PARAMS_PATH_MTU_SHIFT, 1163fe2caefcSParav Pandit 1164fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0, 1165fe2caefcSParav Pandit OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF, 1166fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SL_SHIFT = 20, 1167fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SL_MASK = 0xF << 1168fe2caefcSParav Pandit OCRDMA_QP_PARAMS_SL_SHIFT, 1169fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24, 1170fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 << 1171fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT, 1172fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27, 1173fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F << 1174fe2caefcSParav Pandit OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT, 1175fe2caefcSParav Pandit 1176fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0, 1177fe2caefcSParav Pandit OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF, 1178fe2caefcSParav Pandit OCRDMA_QP_PARAMS_VLAN_SHIFT = 16, 1179fe2caefcSParav Pandit OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF << 1180fe2caefcSParav Pandit OCRDMA_QP_PARAMS_VLAN_SHIFT 1181fe2caefcSParav Pandit }; 1182fe2caefcSParav Pandit 1183fe2caefcSParav Pandit struct ocrdma_qp_params { 1184fe2caefcSParav Pandit u32 id; 1185fe2caefcSParav Pandit u32 max_wqe_rqe; 1186fe2caefcSParav Pandit u32 max_sge_send_write; 1187fe2caefcSParav Pandit u32 max_sge_recv_flags; 1188fe2caefcSParav Pandit u32 max_ord_ird; 1189fe2caefcSParav Pandit u32 wq_rq_cqid; 1190fe2caefcSParav Pandit u32 hop_lmt_rq_psn; 1191fe2caefcSParav Pandit u32 tclass_sq_psn; 1192fe2caefcSParav Pandit u32 ack_to_rnr_rtc_dest_qpn; 1193fe2caefcSParav Pandit u32 path_mtu_pkey_indx; 1194fe2caefcSParav Pandit u32 rnt_rc_sl_fl; 1195fe2caefcSParav Pandit u8 sgid[16]; 1196fe2caefcSParav Pandit u8 dgid[16]; 1197fe2caefcSParav Pandit u32 dmac_b0_to_b3; 1198fe2caefcSParav Pandit u32 vlan_dmac_b4_to_b5; 1199fe2caefcSParav Pandit u32 qkey; 12007b9b1a59SNaresh Gottumukkala }; 1201fe2caefcSParav Pandit 1202fe2caefcSParav Pandit 1203fe2caefcSParav Pandit struct ocrdma_modify_qp { 1204fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1205fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1206fe2caefcSParav Pandit 1207fe2caefcSParav Pandit struct ocrdma_qp_params params; 1208fe2caefcSParav Pandit u32 flags; 1209fe2caefcSParav Pandit u32 rdma_flags; 1210fe2caefcSParav Pandit u32 num_outstanding_atomic_rd; 12117b9b1a59SNaresh Gottumukkala }; 1212fe2caefcSParav Pandit 1213fe2caefcSParav Pandit enum { 1214fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0, 1215fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF, 1216fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16, 1217fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF << 1218fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT, 1219fe2caefcSParav Pandit 1220fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0, 1221fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF, 1222fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16, 1223fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF << 1224fe2caefcSParav Pandit OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT 1225fe2caefcSParav Pandit }; 1226fad51b7dSDevesh Sharma 1227fe2caefcSParav Pandit struct ocrdma_modify_qp_rsp { 1228fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1229fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1230fe2caefcSParav Pandit 1231fe2caefcSParav Pandit u32 max_wqe_rqe; 1232fe2caefcSParav Pandit u32 max_ord_ird; 12337b9b1a59SNaresh Gottumukkala }; 1234fe2caefcSParav Pandit 1235fe2caefcSParav Pandit struct ocrdma_query_qp { 1236fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1237fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1238fe2caefcSParav Pandit 1239fe2caefcSParav Pandit #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0 1240fe2caefcSParav Pandit #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF 1241fe2caefcSParav Pandit u32 qp_id; 12427b9b1a59SNaresh Gottumukkala }; 1243fe2caefcSParav Pandit 1244fe2caefcSParav Pandit struct ocrdma_query_qp_rsp { 1245fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1246fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1247fe2caefcSParav Pandit struct ocrdma_qp_params params; 1248038ab8b7SMitesh Ahuja u32 dpp_credits_cqid; 1249038ab8b7SMitesh Ahuja u32 rbq_id; 12507b9b1a59SNaresh Gottumukkala }; 1251fe2caefcSParav Pandit 1252fe2caefcSParav Pandit enum { 1253fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0, 1254fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF, 1255fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16, 1256fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 << 1257fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_PG_SZ_SHIFT, 1258fe2caefcSParav Pandit 1259fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0, 1260fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16, 1261fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF << 1262fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT, 1263fe2caefcSParav Pandit 1264fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0, 1265fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF, 1266fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16, 1267fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF << 1268fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT 1269fe2caefcSParav Pandit }; 1270fe2caefcSParav Pandit 1271fe2caefcSParav Pandit struct ocrdma_create_srq { 1272fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1273fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1274fe2caefcSParav Pandit 1275fe2caefcSParav Pandit u32 pgsz_pdid; 1276fe2caefcSParav Pandit u32 max_sge_rqe; 1277fe2caefcSParav Pandit u32 pages_rqe_sz; 1278fe2caefcSParav Pandit struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES]; 12797b9b1a59SNaresh Gottumukkala }; 1280fe2caefcSParav Pandit 1281fe2caefcSParav Pandit enum { 1282fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0, 1283fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF, 1284fe2caefcSParav Pandit 1285fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0, 1286fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF, 1287fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16, 1288fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF << 1289fe2caefcSParav Pandit OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT 1290fe2caefcSParav Pandit }; 1291fe2caefcSParav Pandit 1292fe2caefcSParav Pandit struct ocrdma_create_srq_rsp { 1293fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1294fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1295fe2caefcSParav Pandit 1296fe2caefcSParav Pandit u32 id; 1297fe2caefcSParav Pandit u32 max_sge_rqe_allocated; 12987b9b1a59SNaresh Gottumukkala }; 1299fe2caefcSParav Pandit 1300fe2caefcSParav Pandit enum { 1301fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_ID_SHIFT = 0, 1302fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF, 1303fe2caefcSParav Pandit 1304fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0, 1305fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF, 1306fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16, 1307fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF << 1308fe2caefcSParav Pandit OCRDMA_MODIFY_SRQ_LIMIT_SHIFT 1309fe2caefcSParav Pandit }; 1310fe2caefcSParav Pandit 1311fe2caefcSParav Pandit struct ocrdma_modify_srq { 1312fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1313fe2caefcSParav Pandit struct ocrdma_mbx_rsp rep; 1314fe2caefcSParav Pandit 1315fe2caefcSParav Pandit u32 id; 1316fe2caefcSParav Pandit u32 limit_max_rqe; 13177b9b1a59SNaresh Gottumukkala }; 1318fe2caefcSParav Pandit 1319fe2caefcSParav Pandit enum { 1320fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_ID_SHIFT = 0, 1321fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF 1322fe2caefcSParav Pandit }; 1323fe2caefcSParav Pandit 1324fe2caefcSParav Pandit struct ocrdma_query_srq { 1325fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1326fe2caefcSParav Pandit struct ocrdma_mbx_rsp req; 1327fe2caefcSParav Pandit 1328fe2caefcSParav Pandit u32 id; 13297b9b1a59SNaresh Gottumukkala }; 1330fe2caefcSParav Pandit 1331fe2caefcSParav Pandit enum { 1332fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0, 1333fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF, 1334fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16, 1335fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF << 1336fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT, 1337fe2caefcSParav Pandit 1338fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0, 1339fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF, 1340fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16, 1341fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF << 1342fe2caefcSParav Pandit OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT 1343fe2caefcSParav Pandit }; 1344fe2caefcSParav Pandit 1345fe2caefcSParav Pandit struct ocrdma_query_srq_rsp { 1346fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1347fe2caefcSParav Pandit struct ocrdma_mbx_rsp req; 1348fe2caefcSParav Pandit 1349fe2caefcSParav Pandit u32 max_rqe_pdid; 1350fe2caefcSParav Pandit u32 srq_lmt_max_sge; 13517b9b1a59SNaresh Gottumukkala }; 1352fe2caefcSParav Pandit 1353fe2caefcSParav Pandit enum { 1354fe2caefcSParav Pandit OCRDMA_DESTROY_SRQ_ID_SHIFT = 0, 1355fe2caefcSParav Pandit OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF 1356fe2caefcSParav Pandit }; 1357fe2caefcSParav Pandit 1358fe2caefcSParav Pandit struct ocrdma_destroy_srq { 1359fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1360fe2caefcSParav Pandit struct ocrdma_mbx_rsp req; 1361fe2caefcSParav Pandit 1362fe2caefcSParav Pandit u32 id; 13637b9b1a59SNaresh Gottumukkala }; 1364fe2caefcSParav Pandit 1365fe2caefcSParav Pandit enum { 1366fe2caefcSParav Pandit OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16), 1367fe2caefcSParav Pandit OCRDMA_DPP_PAGE_SIZE = 4096 1368fe2caefcSParav Pandit }; 1369fe2caefcSParav Pandit 1370fe2caefcSParav Pandit struct ocrdma_alloc_pd { 1371fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1372fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1373fe2caefcSParav Pandit u32 enable_dpp_rsvd; 13747b9b1a59SNaresh Gottumukkala }; 1375fe2caefcSParav Pandit 1376fe2caefcSParav Pandit enum { 1377de123485SJes Sorensen OCRDMA_ALLOC_PD_RSP_DPP = BIT(16), 1378fe2caefcSParav Pandit OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20, 1379fe2caefcSParav Pandit OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF, 1380fe2caefcSParav Pandit }; 1381fe2caefcSParav Pandit 1382fe2caefcSParav Pandit struct ocrdma_alloc_pd_rsp { 1383fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1384fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1385fe2caefcSParav Pandit u32 dpp_page_pdid; 13867b9b1a59SNaresh Gottumukkala }; 1387fe2caefcSParav Pandit 1388fe2caefcSParav Pandit struct ocrdma_dealloc_pd { 1389fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1390fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1391fe2caefcSParav Pandit u32 id; 13927b9b1a59SNaresh Gottumukkala }; 1393fe2caefcSParav Pandit 1394fe2caefcSParav Pandit struct ocrdma_dealloc_pd_rsp { 1395fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1396fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 13977b9b1a59SNaresh Gottumukkala }; 1398fe2caefcSParav Pandit 13999ba1377dSMitesh Ahuja struct ocrdma_alloc_pd_range { 14009ba1377dSMitesh Ahuja struct ocrdma_mqe_hdr hdr; 14019ba1377dSMitesh Ahuja struct ocrdma_mbx_hdr req; 14029ba1377dSMitesh Ahuja u32 enable_dpp_rsvd; 14039ba1377dSMitesh Ahuja u32 pd_count; 14049ba1377dSMitesh Ahuja }; 14059ba1377dSMitesh Ahuja 14069ba1377dSMitesh Ahuja struct ocrdma_alloc_pd_range_rsp { 14079ba1377dSMitesh Ahuja struct ocrdma_mqe_hdr hdr; 14089ba1377dSMitesh Ahuja struct ocrdma_mbx_rsp rsp; 14099ba1377dSMitesh Ahuja u32 dpp_page_pdid; 14109ba1377dSMitesh Ahuja u32 pd_count; 14119ba1377dSMitesh Ahuja }; 14129ba1377dSMitesh Ahuja 14139ba1377dSMitesh Ahuja enum { 14149ba1377dSMitesh Ahuja OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK = 0xFFFF, 14159ba1377dSMitesh Ahuja }; 14169ba1377dSMitesh Ahuja 14179ba1377dSMitesh Ahuja struct ocrdma_dealloc_pd_range { 14189ba1377dSMitesh Ahuja struct ocrdma_mqe_hdr hdr; 14199ba1377dSMitesh Ahuja struct ocrdma_mbx_hdr req; 14209ba1377dSMitesh Ahuja u32 start_pd_id; 14219ba1377dSMitesh Ahuja u32 pd_count; 14229ba1377dSMitesh Ahuja }; 14239ba1377dSMitesh Ahuja 14249ba1377dSMitesh Ahuja struct ocrdma_dealloc_pd_range_rsp { 14259ba1377dSMitesh Ahuja struct ocrdma_mqe_hdr hdr; 14269ba1377dSMitesh Ahuja struct ocrdma_mbx_hdr req; 14279ba1377dSMitesh Ahuja u32 rsvd; 14289ba1377dSMitesh Ahuja }; 14299ba1377dSMitesh Ahuja 1430fe2caefcSParav Pandit enum { 1431fe2caefcSParav Pandit OCRDMA_ADDR_CHECK_ENABLE = 1, 1432fe2caefcSParav Pandit OCRDMA_ADDR_CHECK_DISABLE = 0 1433fe2caefcSParav Pandit }; 1434fe2caefcSParav Pandit 1435fe2caefcSParav Pandit enum { 1436fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0, 1437fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF, 1438fe2caefcSParav Pandit 1439fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0, 1440de123485SJes Sorensen OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = BIT(0), 1441fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1, 1442de123485SJes Sorensen OCRDMA_ALLOC_LKEY_FMR_MASK = BIT(1), 1443fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2, 1444de123485SJes Sorensen OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = BIT(2), 1445fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3, 1446de123485SJes Sorensen OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = BIT(3), 1447fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4, 1448de123485SJes Sorensen OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = BIT(4), 1449fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5, 1450de123485SJes Sorensen OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = BIT(5), 1451de123485SJes Sorensen OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = BIT(6), 1452fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6, 1453fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16, 1454fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF << 1455fe2caefcSParav Pandit OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT 1456fe2caefcSParav Pandit }; 1457fe2caefcSParav Pandit 1458fe2caefcSParav Pandit struct ocrdma_alloc_lkey { 1459fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1460fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1461fe2caefcSParav Pandit 1462fe2caefcSParav Pandit u32 pdid; 1463fe2caefcSParav Pandit u32 pbl_sz_flags; 14647b9b1a59SNaresh Gottumukkala }; 1465fe2caefcSParav Pandit 1466fe2caefcSParav Pandit struct ocrdma_alloc_lkey_rsp { 1467fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1468fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1469fe2caefcSParav Pandit 1470fe2caefcSParav Pandit u32 lrkey; 1471fe2caefcSParav Pandit u32 num_pbl_rsvd; 14727b9b1a59SNaresh Gottumukkala }; 1473fe2caefcSParav Pandit 1474fe2caefcSParav Pandit struct ocrdma_dealloc_lkey { 1475fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1476fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1477fe2caefcSParav Pandit 1478fe2caefcSParav Pandit u32 lkey; 1479fe2caefcSParav Pandit u32 rsvd_frmr; 14807b9b1a59SNaresh Gottumukkala }; 1481fe2caefcSParav Pandit 1482fe2caefcSParav Pandit struct ocrdma_dealloc_lkey_rsp { 1483fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1484fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 14857b9b1a59SNaresh Gottumukkala }; 1486fe2caefcSParav Pandit 1487fe2caefcSParav Pandit #define MAX_OCRDMA_NSMR_PBL (u32)22 1488fe2caefcSParav Pandit #define MAX_OCRDMA_PBL_SIZE 65536 1489fe2caefcSParav Pandit #define MAX_OCRDMA_PBL_PER_LKEY 32767 1490fe2caefcSParav Pandit 1491fe2caefcSParav Pandit enum { 1492fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0, 1493fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF, 1494fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_SHIFT = 24, 1495fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF << 1496fe2caefcSParav Pandit OCRDMA_REG_NSMR_LRKEY_SHIFT, 1497fe2caefcSParav Pandit 1498fe2caefcSParav Pandit OCRDMA_REG_NSMR_PD_ID_SHIFT = 0, 1499fe2caefcSParav Pandit OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF, 1500fe2caefcSParav Pandit OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16, 1501fe2caefcSParav Pandit OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF << 1502fe2caefcSParav Pandit OCRDMA_REG_NSMR_NUM_PBL_SHIFT, 1503fe2caefcSParav Pandit 1504fe2caefcSParav Pandit OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0, 1505fe2caefcSParav Pandit OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF, 1506fe2caefcSParav Pandit OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16, 1507fe2caefcSParav Pandit OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF << 1508fe2caefcSParav Pandit OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT, 1509fe2caefcSParav Pandit OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24, 1510de123485SJes Sorensen OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = BIT(24), 1511fe2caefcSParav Pandit OCRDMA_REG_NSMR_ZB_SHIFT = 25, 1512de123485SJes Sorensen OCRDMA_REG_NSMR_ZB_SHIFT_MASK = BIT(25), 1513fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26, 1514de123485SJes Sorensen OCRDMA_REG_NSMR_REMOTE_INV_MASK = BIT(26), 1515fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27, 1516de123485SJes Sorensen OCRDMA_REG_NSMR_REMOTE_WR_MASK = BIT(27), 1517fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28, 1518de123485SJes Sorensen OCRDMA_REG_NSMR_REMOTE_RD_MASK = BIT(28), 1519fe2caefcSParav Pandit OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29, 1520de123485SJes Sorensen OCRDMA_REG_NSMR_LOCAL_WR_MASK = BIT(29), 1521fe2caefcSParav Pandit OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30, 1522de123485SJes Sorensen OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = BIT(30), 1523fe2caefcSParav Pandit OCRDMA_REG_NSMR_LAST_SHIFT = 31, 1524de123485SJes Sorensen OCRDMA_REG_NSMR_LAST_MASK = BIT(31) 1525fe2caefcSParav Pandit }; 1526fe2caefcSParav Pandit 1527fe2caefcSParav Pandit struct ocrdma_reg_nsmr { 1528fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1529fe2caefcSParav Pandit struct ocrdma_mbx_hdr cmd; 1530fe2caefcSParav Pandit 15312b51a9b9SNaresh Gottumukkala u32 fr_mr; 1532fe2caefcSParav Pandit u32 num_pbl_pdid; 1533fe2caefcSParav Pandit u32 flags_hpage_pbe_sz; 1534fe2caefcSParav Pandit u32 totlen_low; 1535fe2caefcSParav Pandit u32 totlen_high; 1536fe2caefcSParav Pandit u32 fbo_low; 1537fe2caefcSParav Pandit u32 fbo_high; 1538fe2caefcSParav Pandit u32 va_loaddr; 1539fe2caefcSParav Pandit u32 va_hiaddr; 1540fe2caefcSParav Pandit struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 15417b9b1a59SNaresh Gottumukkala }; 1542fe2caefcSParav Pandit 1543fe2caefcSParav Pandit enum { 1544fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0, 1545fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF, 1546fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16, 1547fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF << 1548fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT, 1549fe2caefcSParav Pandit 1550fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31, 1551de123485SJes Sorensen OCRDMA_REG_NSMR_CONT_LAST_MASK = BIT(31) 1552fe2caefcSParav Pandit }; 1553fe2caefcSParav Pandit 1554fe2caefcSParav Pandit struct ocrdma_reg_nsmr_cont { 1555fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1556fe2caefcSParav Pandit struct ocrdma_mbx_hdr cmd; 1557fe2caefcSParav Pandit 1558fe2caefcSParav Pandit u32 lrkey; 1559fe2caefcSParav Pandit u32 num_pbl_offset; 1560fe2caefcSParav Pandit u32 last; 1561fe2caefcSParav Pandit 1562fe2caefcSParav Pandit struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL]; 156345e86b33SNaresh Gottumukkala }; 1564fe2caefcSParav Pandit 1565fe2caefcSParav Pandit struct ocrdma_pbe { 1566fe2caefcSParav Pandit u32 pa_hi; 1567fe2caefcSParav Pandit u32 pa_lo; 15687b9b1a59SNaresh Gottumukkala }; 1569fe2caefcSParav Pandit 1570fe2caefcSParav Pandit enum { 1571fe2caefcSParav Pandit OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16, 1572fe2caefcSParav Pandit OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000 1573fe2caefcSParav Pandit }; 1574fe2caefcSParav Pandit struct ocrdma_reg_nsmr_rsp { 1575fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1576fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1577fe2caefcSParav Pandit 1578fe2caefcSParav Pandit u32 lrkey; 1579fe2caefcSParav Pandit u32 num_pbl; 15807b9b1a59SNaresh Gottumukkala }; 1581fe2caefcSParav Pandit 1582fe2caefcSParav Pandit enum { 1583fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0, 1584fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF, 1585fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24, 1586fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF << 1587fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT, 1588fe2caefcSParav Pandit 1589fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16, 1590fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF << 1591fe2caefcSParav Pandit OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT 1592fe2caefcSParav Pandit }; 1593fe2caefcSParav Pandit 1594fe2caefcSParav Pandit struct ocrdma_reg_nsmr_cont_rsp { 1595fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1596fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1597fe2caefcSParav Pandit 1598fe2caefcSParav Pandit u32 lrkey_key_index; 1599fe2caefcSParav Pandit u32 num_pbl; 16007b9b1a59SNaresh Gottumukkala }; 1601fe2caefcSParav Pandit 1602fe2caefcSParav Pandit enum { 1603fe2caefcSParav Pandit OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0, 1604fe2caefcSParav Pandit OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF 1605fe2caefcSParav Pandit }; 1606fe2caefcSParav Pandit 1607fe2caefcSParav Pandit struct ocrdma_alloc_mw { 1608fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1609fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1610fe2caefcSParav Pandit 1611fe2caefcSParav Pandit u32 pdid; 16127b9b1a59SNaresh Gottumukkala }; 1613fe2caefcSParav Pandit 1614fe2caefcSParav Pandit enum { 1615fe2caefcSParav Pandit OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0, 1616fe2caefcSParav Pandit OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF 1617fe2caefcSParav Pandit }; 1618fe2caefcSParav Pandit 1619fe2caefcSParav Pandit struct ocrdma_alloc_mw_rsp { 1620fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1621fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1622fe2caefcSParav Pandit 1623fe2caefcSParav Pandit u32 lrkey_index; 16247b9b1a59SNaresh Gottumukkala }; 1625fe2caefcSParav Pandit 1626fe2caefcSParav Pandit struct ocrdma_attach_mcast { 1627fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1628fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1629fe2caefcSParav Pandit u32 qp_id; 1630fe2caefcSParav Pandit u8 mgid[16]; 1631fe2caefcSParav Pandit u32 mac_b0_to_b3; 1632fe2caefcSParav Pandit u32 vlan_mac_b4_to_b5; 16337b9b1a59SNaresh Gottumukkala }; 1634fe2caefcSParav Pandit 1635fe2caefcSParav Pandit struct ocrdma_attach_mcast_rsp { 1636fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1637fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 16387b9b1a59SNaresh Gottumukkala }; 1639fe2caefcSParav Pandit 1640fe2caefcSParav Pandit struct ocrdma_detach_mcast { 1641fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1642fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1643fe2caefcSParav Pandit u32 qp_id; 1644fe2caefcSParav Pandit u8 mgid[16]; 1645fe2caefcSParav Pandit u32 mac_b0_to_b3; 1646fe2caefcSParav Pandit u32 vlan_mac_b4_to_b5; 16477b9b1a59SNaresh Gottumukkala }; 1648fe2caefcSParav Pandit 1649fe2caefcSParav Pandit struct ocrdma_detach_mcast_rsp { 1650fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1651fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 16527b9b1a59SNaresh Gottumukkala }; 1653fe2caefcSParav Pandit 1654fe2caefcSParav Pandit enum { 1655fe2caefcSParav Pandit OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19, 1656fe2caefcSParav Pandit OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF << 1657fe2caefcSParav Pandit OCRDMA_CREATE_AH_NUM_PAGES_SHIFT, 1658fe2caefcSParav Pandit 1659fe2caefcSParav Pandit OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16, 1660fe2caefcSParav Pandit OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 << 1661fe2caefcSParav Pandit OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT, 1662fe2caefcSParav Pandit 1663fe2caefcSParav Pandit OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23, 1664fe2caefcSParav Pandit OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF << 1665fe2caefcSParav Pandit OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT, 1666fe2caefcSParav Pandit }; 1667fe2caefcSParav Pandit 1668fe2caefcSParav Pandit #define OCRDMA_AH_TBL_PAGES 8 1669fe2caefcSParav Pandit 1670fe2caefcSParav Pandit struct ocrdma_create_ah_tbl { 1671fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1672fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1673fe2caefcSParav Pandit 1674fe2caefcSParav Pandit u32 ah_conf; 1675fe2caefcSParav Pandit struct ocrdma_pa tbl_addr[8]; 16767b9b1a59SNaresh Gottumukkala }; 1677fe2caefcSParav Pandit 1678fe2caefcSParav Pandit struct ocrdma_create_ah_tbl_rsp { 1679fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1680fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 1681fe2caefcSParav Pandit u32 ahid; 16827b9b1a59SNaresh Gottumukkala }; 1683fe2caefcSParav Pandit 1684fe2caefcSParav Pandit struct ocrdma_delete_ah_tbl { 1685fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1686fe2caefcSParav Pandit struct ocrdma_mbx_hdr req; 1687fe2caefcSParav Pandit u32 ahid; 16887b9b1a59SNaresh Gottumukkala }; 1689fe2caefcSParav Pandit 1690fe2caefcSParav Pandit struct ocrdma_delete_ah_tbl_rsp { 1691fe2caefcSParav Pandit struct ocrdma_mqe_hdr hdr; 1692fe2caefcSParav Pandit struct ocrdma_mbx_rsp rsp; 16937b9b1a59SNaresh Gottumukkala }; 1694fe2caefcSParav Pandit 1695fe2caefcSParav Pandit enum { 1696fe2caefcSParav Pandit OCRDMA_EQE_VALID_SHIFT = 0, 1697de123485SJes Sorensen OCRDMA_EQE_VALID_MASK = BIT(0), 16985e6f9237SDevesh Sharma OCRDMA_EQE_MAJOR_CODE_MASK = 0x0E, 16995e6f9237SDevesh Sharma OCRDMA_EQE_MAJOR_CODE_SHIFT = 0x01, 1700fe2caefcSParav Pandit OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE, 1701fe2caefcSParav Pandit OCRDMA_EQE_RESOURCE_ID_SHIFT = 16, 1702fe2caefcSParav Pandit OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF << 1703fe2caefcSParav Pandit OCRDMA_EQE_RESOURCE_ID_SHIFT, 1704fe2caefcSParav Pandit }; 1705fe2caefcSParav Pandit 17065e6f9237SDevesh Sharma enum major_code { 17075e6f9237SDevesh Sharma OCRDMA_MAJOR_CODE_COMPLETION = 0x00, 17085e6f9237SDevesh Sharma OCRDMA_MAJOR_CODE_SENTINAL = 0x01 17095e6f9237SDevesh Sharma }; 17105e6f9237SDevesh Sharma 1711fe2caefcSParav Pandit struct ocrdma_eqe { 1712fe2caefcSParav Pandit u32 id_valid; 17137b9b1a59SNaresh Gottumukkala }; 1714fe2caefcSParav Pandit 1715fe2caefcSParav Pandit enum OCRDMA_CQE_STATUS { 1716fe2caefcSParav Pandit OCRDMA_CQE_SUCCESS = 0, 1717fe2caefcSParav Pandit OCRDMA_CQE_LOC_LEN_ERR, 1718fe2caefcSParav Pandit OCRDMA_CQE_LOC_QP_OP_ERR, 1719fe2caefcSParav Pandit OCRDMA_CQE_LOC_EEC_OP_ERR, 1720fe2caefcSParav Pandit OCRDMA_CQE_LOC_PROT_ERR, 1721fe2caefcSParav Pandit OCRDMA_CQE_WR_FLUSH_ERR, 1722fe2caefcSParav Pandit OCRDMA_CQE_MW_BIND_ERR, 1723fe2caefcSParav Pandit OCRDMA_CQE_BAD_RESP_ERR, 1724fe2caefcSParav Pandit OCRDMA_CQE_LOC_ACCESS_ERR, 1725fe2caefcSParav Pandit OCRDMA_CQE_REM_INV_REQ_ERR, 1726fe2caefcSParav Pandit OCRDMA_CQE_REM_ACCESS_ERR, 1727fe2caefcSParav Pandit OCRDMA_CQE_REM_OP_ERR, 1728fe2caefcSParav Pandit OCRDMA_CQE_RETRY_EXC_ERR, 1729fe2caefcSParav Pandit OCRDMA_CQE_RNR_RETRY_EXC_ERR, 1730fe2caefcSParav Pandit OCRDMA_CQE_LOC_RDD_VIOL_ERR, 1731fe2caefcSParav Pandit OCRDMA_CQE_REM_INV_RD_REQ_ERR, 1732fe2caefcSParav Pandit OCRDMA_CQE_REM_ABORT_ERR, 1733fe2caefcSParav Pandit OCRDMA_CQE_INV_EECN_ERR, 1734fe2caefcSParav Pandit OCRDMA_CQE_INV_EEC_STATE_ERR, 1735fe2caefcSParav Pandit OCRDMA_CQE_FATAL_ERR, 1736fe2caefcSParav Pandit OCRDMA_CQE_RESP_TIMEOUT_ERR, 1737ad56ebb4SSelvin Xavier OCRDMA_CQE_GENERAL_ERR, 1738ad56ebb4SSelvin Xavier 1739ad56ebb4SSelvin Xavier OCRDMA_MAX_CQE_ERR 1740fe2caefcSParav Pandit }; 1741fe2caefcSParav Pandit 1742fe2caefcSParav Pandit enum { 1743fe2caefcSParav Pandit /* w0 */ 1744fe2caefcSParav Pandit OCRDMA_CQE_WQEIDX_SHIFT = 0, 1745fe2caefcSParav Pandit OCRDMA_CQE_WQEIDX_MASK = 0xFFFF, 1746fe2caefcSParav Pandit 1747fe2caefcSParav Pandit /* w1 */ 1748fe2caefcSParav Pandit OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16, 17496b062667SDevesh Sharma OCRDMA_CQE_UD_XFER_LEN_MASK = 0x1FFF, 1750fe2caefcSParav Pandit OCRDMA_CQE_PKEY_SHIFT = 0, 1751fe2caefcSParav Pandit OCRDMA_CQE_PKEY_MASK = 0xFFFF, 17526b062667SDevesh Sharma OCRDMA_CQE_UD_L3TYPE_SHIFT = 29, 17536b062667SDevesh Sharma OCRDMA_CQE_UD_L3TYPE_MASK = 0x07, 1754fe2caefcSParav Pandit 1755fe2caefcSParav Pandit /* w2 */ 1756fe2caefcSParav Pandit OCRDMA_CQE_QPN_SHIFT = 0, 1757fe2caefcSParav Pandit OCRDMA_CQE_QPN_MASK = 0x0000FFFF, 1758fe2caefcSParav Pandit 1759fe2caefcSParav Pandit OCRDMA_CQE_BUFTAG_SHIFT = 16, 1760fe2caefcSParav Pandit OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT, 1761fe2caefcSParav Pandit 1762fe2caefcSParav Pandit /* w3 */ 1763fe2caefcSParav Pandit OCRDMA_CQE_UD_STATUS_SHIFT = 24, 1764fe2caefcSParav Pandit OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT, 1765fe2caefcSParav Pandit OCRDMA_CQE_STATUS_SHIFT = 16, 1766fe2caefcSParav Pandit OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT, 1767de123485SJes Sorensen OCRDMA_CQE_VALID = BIT(31), 1768de123485SJes Sorensen OCRDMA_CQE_INVALIDATE = BIT(30), 1769de123485SJes Sorensen OCRDMA_CQE_QTYPE = BIT(29), 1770de123485SJes Sorensen OCRDMA_CQE_IMM = BIT(28), 1771de123485SJes Sorensen OCRDMA_CQE_WRITE_IMM = BIT(27), 1772fe2caefcSParav Pandit OCRDMA_CQE_QTYPE_SQ = 0, 1773fe2caefcSParav Pandit OCRDMA_CQE_QTYPE_RQ = 1, 1774fe2caefcSParav Pandit OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF 1775fe2caefcSParav Pandit }; 1776fe2caefcSParav Pandit 1777fe2caefcSParav Pandit struct ocrdma_cqe { 1778fe2caefcSParav Pandit union { 1779fe2caefcSParav Pandit /* w0 to w2 */ 1780fe2caefcSParav Pandit struct { 1781fe2caefcSParav Pandit u32 wqeidx; 1782fe2caefcSParav Pandit u32 bytes_xfered; 1783fe2caefcSParav Pandit u32 qpn; 1784fe2caefcSParav Pandit } wq; 1785fe2caefcSParav Pandit struct { 1786fe2caefcSParav Pandit u32 lkey_immdt; 1787fe2caefcSParav Pandit u32 rxlen; 1788fe2caefcSParav Pandit u32 buftag_qpn; 1789fe2caefcSParav Pandit } rq; 1790fe2caefcSParav Pandit struct { 1791fe2caefcSParav Pandit u32 lkey_immdt; 1792fe2caefcSParav Pandit u32 rxlen_pkey; 1793fe2caefcSParav Pandit u32 buftag_qpn; 1794fe2caefcSParav Pandit } ud; 1795fe2caefcSParav Pandit struct { 1796fe2caefcSParav Pandit u32 word_0; 1797fe2caefcSParav Pandit u32 word_1; 1798fe2caefcSParav Pandit u32 qpn; 1799fe2caefcSParav Pandit } cmn; 1800fe2caefcSParav Pandit }; 1801fe2caefcSParav Pandit u32 flags_status_srcqpn; /* w3 */ 18027b9b1a59SNaresh Gottumukkala }; 1803fe2caefcSParav Pandit 1804fe2caefcSParav Pandit struct ocrdma_sge { 1805fe2caefcSParav Pandit u32 addr_hi; 1806fe2caefcSParav Pandit u32 addr_lo; 1807fe2caefcSParav Pandit u32 lrkey; 1808fe2caefcSParav Pandit u32 len; 18097b9b1a59SNaresh Gottumukkala }; 1810fe2caefcSParav Pandit 1811fe2caefcSParav Pandit enum { 1812fe2caefcSParav Pandit OCRDMA_FLAG_SIG = 0x1, 1813fe2caefcSParav Pandit OCRDMA_FLAG_INV = 0x2, 1814fe2caefcSParav Pandit OCRDMA_FLAG_FENCE_L = 0x4, 1815fe2caefcSParav Pandit OCRDMA_FLAG_FENCE_R = 0x8, 1816fe2caefcSParav Pandit OCRDMA_FLAG_SOLICIT = 0x10, 1817fe2caefcSParav Pandit OCRDMA_FLAG_IMM = 0x20, 181829565f2fSDevesh Sharma OCRDMA_FLAG_AH_VLAN_PR = 0x40, 1819fe2caefcSParav Pandit 1820fe2caefcSParav Pandit /* Stag flags */ 1821fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1, 1822fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2, 1823fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4, 1824fe2caefcSParav Pandit OCRDMA_LKEY_FLAG_VATO = 0x8, 1825fe2caefcSParav Pandit }; 1826fe2caefcSParav Pandit 1827fe2caefcSParav Pandit enum OCRDMA_WQE_OPCODE { 1828fe2caefcSParav Pandit OCRDMA_WRITE = 0x06, 1829fe2caefcSParav Pandit OCRDMA_READ = 0x0C, 1830fe2caefcSParav Pandit OCRDMA_RESV0 = 0x02, 1831fe2caefcSParav Pandit OCRDMA_SEND = 0x00, 1832fe2caefcSParav Pandit OCRDMA_CMP_SWP = 0x14, 1833fe2caefcSParav Pandit OCRDMA_BIND_MW = 0x10, 18347c33880cSNaresh Gottumukkala OCRDMA_FR_MR = 0x11, 1835fe2caefcSParav Pandit OCRDMA_RESV1 = 0x0A, 1836fe2caefcSParav Pandit OCRDMA_LKEY_INV = 0x15, 1837fe2caefcSParav Pandit OCRDMA_FETCH_ADD = 0x13, 1838fe2caefcSParav Pandit OCRDMA_POST_RQ = 0x12 1839fe2caefcSParav Pandit }; 1840fe2caefcSParav Pandit 1841fe2caefcSParav Pandit enum { 1842fe2caefcSParav Pandit OCRDMA_TYPE_INLINE = 0x0, 1843fe2caefcSParav Pandit OCRDMA_TYPE_LKEY = 0x1, 1844fe2caefcSParav Pandit }; 1845fe2caefcSParav Pandit 1846fe2caefcSParav Pandit enum { 1847fe2caefcSParav Pandit OCRDMA_WQE_OPCODE_SHIFT = 0, 1848fe2caefcSParav Pandit OCRDMA_WQE_OPCODE_MASK = 0x0000001F, 1849fe2caefcSParav Pandit OCRDMA_WQE_FLAGS_SHIFT = 5, 1850fe2caefcSParav Pandit OCRDMA_WQE_TYPE_SHIFT = 16, 1851fe2caefcSParav Pandit OCRDMA_WQE_TYPE_MASK = 0x00030000, 1852fe2caefcSParav Pandit OCRDMA_WQE_SIZE_SHIFT = 18, 1853fe2caefcSParav Pandit OCRDMA_WQE_SIZE_MASK = 0xFF, 1854fe2caefcSParav Pandit OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25, 1855fe2caefcSParav Pandit 1856fe2caefcSParav Pandit OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0, 1857fe2caefcSParav Pandit OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF 1858fe2caefcSParav Pandit }; 1859fe2caefcSParav Pandit 1860fe2caefcSParav Pandit /* header WQE for all the SQ and RQ operations */ 1861fe2caefcSParav Pandit struct ocrdma_hdr_wqe { 1862fe2caefcSParav Pandit u32 cw; 1863fe2caefcSParav Pandit union { 1864fe2caefcSParav Pandit u32 rsvd_tag; 1865fe2caefcSParav Pandit u32 rsvd_lkey_flags; 1866fe2caefcSParav Pandit }; 1867fe2caefcSParav Pandit union { 1868fe2caefcSParav Pandit u32 immdt; 1869fe2caefcSParav Pandit u32 lkey; 1870fe2caefcSParav Pandit }; 1871fe2caefcSParav Pandit u32 total_len; 18727b9b1a59SNaresh Gottumukkala }; 1873fe2caefcSParav Pandit 1874fe2caefcSParav Pandit struct ocrdma_ewqe_ud_hdr { 1875fe2caefcSParav Pandit u32 rsvd_dest_qpn; 1876fe2caefcSParav Pandit u32 qkey; 1877fe2caefcSParav Pandit u32 rsvd_ahid; 18786b062667SDevesh Sharma u32 hdr_type; 18797b9b1a59SNaresh Gottumukkala }; 1880fe2caefcSParav Pandit 18817c33880cSNaresh Gottumukkala /* extended wqe followed by hdr_wqe for Fast Memory register */ 18827c33880cSNaresh Gottumukkala struct ocrdma_ewqe_fr { 18837c33880cSNaresh Gottumukkala u32 va_hi; 18847c33880cSNaresh Gottumukkala u32 va_lo; 18857c33880cSNaresh Gottumukkala u32 fbo_hi; 18867c33880cSNaresh Gottumukkala u32 fbo_lo; 18877c33880cSNaresh Gottumukkala u32 size_sge; 18887c33880cSNaresh Gottumukkala u32 num_sges; 18892b51a9b9SNaresh Gottumukkala u32 rsvd; 18902b51a9b9SNaresh Gottumukkala u32 rsvd2; 18917c33880cSNaresh Gottumukkala }; 18927c33880cSNaresh Gottumukkala 1893fe2caefcSParav Pandit struct ocrdma_eth_basic { 1894fe2caefcSParav Pandit u8 dmac[6]; 1895fe2caefcSParav Pandit u8 smac[6]; 1896fe2caefcSParav Pandit __be16 eth_type; 1897fe2caefcSParav Pandit } __packed; 1898fe2caefcSParav Pandit 1899fe2caefcSParav Pandit struct ocrdma_eth_vlan { 1900fe2caefcSParav Pandit u8 dmac[6]; 1901fe2caefcSParav Pandit u8 smac[6]; 1902fe2caefcSParav Pandit __be16 eth_type; 1903fe2caefcSParav Pandit __be16 vlan_tag; 1904fe2caefcSParav Pandit __be16 roce_eth_type; 1905fe2caefcSParav Pandit } __packed; 1906fe2caefcSParav Pandit 1907fe2caefcSParav Pandit struct ocrdma_grh { 1908fe2caefcSParav Pandit __be32 tclass_flow; 1909fe2caefcSParav Pandit __be32 pdid_hoplimit; 1910fe2caefcSParav Pandit u8 sgid[16]; 1911fe2caefcSParav Pandit u8 dgid[16]; 1912fe2caefcSParav Pandit u16 rsvd; 1913fe2caefcSParav Pandit } __packed; 1914fe2caefcSParav Pandit 1915de123485SJes Sorensen #define OCRDMA_AV_VALID BIT(7) 1916de123485SJes Sorensen #define OCRDMA_AV_VLAN_VALID BIT(1) 1917fe2caefcSParav Pandit 1918fe2caefcSParav Pandit struct ocrdma_av { 1919fe2caefcSParav Pandit struct ocrdma_eth_vlan eth_hdr; 1920fe2caefcSParav Pandit struct ocrdma_grh grh; 1921fe2caefcSParav Pandit u32 valid; 1922fe2caefcSParav Pandit } __packed; 1923fe2caefcSParav Pandit 1924a51f06e1SSelvin Xavier struct ocrdma_rsrc_stats { 1925a51f06e1SSelvin Xavier u32 dpp_pds; 1926a51f06e1SSelvin Xavier u32 non_dpp_pds; 1927a51f06e1SSelvin Xavier u32 rc_dpp_qps; 1928a51f06e1SSelvin Xavier u32 uc_dpp_qps; 1929a51f06e1SSelvin Xavier u32 ud_dpp_qps; 1930a51f06e1SSelvin Xavier u32 rc_non_dpp_qps; 1931a51f06e1SSelvin Xavier u32 rsvd; 1932a51f06e1SSelvin Xavier u32 uc_non_dpp_qps; 1933a51f06e1SSelvin Xavier u32 ud_non_dpp_qps; 1934a51f06e1SSelvin Xavier u32 rsvd1; 1935a51f06e1SSelvin Xavier u32 srqs; 1936a51f06e1SSelvin Xavier u32 rbqs; 1937a51f06e1SSelvin Xavier u32 r64K_nsmr; 1938a51f06e1SSelvin Xavier u32 r64K_to_2M_nsmr; 1939a51f06e1SSelvin Xavier u32 r2M_to_44M_nsmr; 1940a51f06e1SSelvin Xavier u32 r44M_to_1G_nsmr; 1941a51f06e1SSelvin Xavier u32 r1G_to_4G_nsmr; 1942a51f06e1SSelvin Xavier u32 nsmr_count_4G_to_32G; 1943a51f06e1SSelvin Xavier u32 r32G_to_64G_nsmr; 1944a51f06e1SSelvin Xavier u32 r64G_to_128G_nsmr; 1945a51f06e1SSelvin Xavier u32 r128G_to_higher_nsmr; 1946a51f06e1SSelvin Xavier u32 embedded_nsmr; 1947a51f06e1SSelvin Xavier u32 frmr; 1948a51f06e1SSelvin Xavier u32 prefetch_qps; 1949a51f06e1SSelvin Xavier u32 ondemand_qps; 1950a51f06e1SSelvin Xavier u32 phy_mr; 1951a51f06e1SSelvin Xavier u32 mw; 1952a51f06e1SSelvin Xavier u32 rsvd2[7]; 1953a51f06e1SSelvin Xavier }; 1954a51f06e1SSelvin Xavier 1955a51f06e1SSelvin Xavier struct ocrdma_db_err_stats { 1956a51f06e1SSelvin Xavier u32 sq_doorbell_errors; 1957a51f06e1SSelvin Xavier u32 cq_doorbell_errors; 1958a51f06e1SSelvin Xavier u32 rq_srq_doorbell_errors; 1959a51f06e1SSelvin Xavier u32 cq_overflow_errors; 1960a51f06e1SSelvin Xavier u32 rsvd[4]; 1961a51f06e1SSelvin Xavier }; 1962a51f06e1SSelvin Xavier 1963a51f06e1SSelvin Xavier struct ocrdma_wqe_stats { 1964a51f06e1SSelvin Xavier u32 large_send_rc_wqes_lo; 1965a51f06e1SSelvin Xavier u32 large_send_rc_wqes_hi; 1966a51f06e1SSelvin Xavier u32 large_write_rc_wqes_lo; 1967a51f06e1SSelvin Xavier u32 large_write_rc_wqes_hi; 1968a51f06e1SSelvin Xavier u32 rsvd[4]; 1969a51f06e1SSelvin Xavier u32 read_wqes_lo; 1970a51f06e1SSelvin Xavier u32 read_wqes_hi; 1971a51f06e1SSelvin Xavier u32 frmr_wqes_lo; 1972a51f06e1SSelvin Xavier u32 frmr_wqes_hi; 1973a51f06e1SSelvin Xavier u32 mw_bind_wqes_lo; 1974a51f06e1SSelvin Xavier u32 mw_bind_wqes_hi; 1975a51f06e1SSelvin Xavier u32 invalidate_wqes_lo; 1976a51f06e1SSelvin Xavier u32 invalidate_wqes_hi; 1977a51f06e1SSelvin Xavier u32 rsvd1[2]; 1978a51f06e1SSelvin Xavier u32 dpp_wqe_drops; 1979a51f06e1SSelvin Xavier u32 rsvd2[5]; 1980a51f06e1SSelvin Xavier }; 1981a51f06e1SSelvin Xavier 1982a51f06e1SSelvin Xavier struct ocrdma_tx_stats { 1983a51f06e1SSelvin Xavier u32 send_pkts_lo; 1984a51f06e1SSelvin Xavier u32 send_pkts_hi; 1985a51f06e1SSelvin Xavier u32 write_pkts_lo; 1986a51f06e1SSelvin Xavier u32 write_pkts_hi; 1987a51f06e1SSelvin Xavier u32 read_pkts_lo; 1988a51f06e1SSelvin Xavier u32 read_pkts_hi; 1989a51f06e1SSelvin Xavier u32 read_rsp_pkts_lo; 1990a51f06e1SSelvin Xavier u32 read_rsp_pkts_hi; 1991a51f06e1SSelvin Xavier u32 ack_pkts_lo; 1992a51f06e1SSelvin Xavier u32 ack_pkts_hi; 1993a51f06e1SSelvin Xavier u32 send_bytes_lo; 1994a51f06e1SSelvin Xavier u32 send_bytes_hi; 1995a51f06e1SSelvin Xavier u32 write_bytes_lo; 1996a51f06e1SSelvin Xavier u32 write_bytes_hi; 1997a51f06e1SSelvin Xavier u32 read_req_bytes_lo; 1998a51f06e1SSelvin Xavier u32 read_req_bytes_hi; 1999a51f06e1SSelvin Xavier u32 read_rsp_bytes_lo; 2000a51f06e1SSelvin Xavier u32 read_rsp_bytes_hi; 2001a51f06e1SSelvin Xavier u32 ack_timeouts; 2002a51f06e1SSelvin Xavier u32 rsvd[5]; 2003a51f06e1SSelvin Xavier }; 2004a51f06e1SSelvin Xavier 2005a51f06e1SSelvin Xavier 2006a51f06e1SSelvin Xavier struct ocrdma_tx_qp_err_stats { 2007a51f06e1SSelvin Xavier u32 local_length_errors; 2008a51f06e1SSelvin Xavier u32 local_protection_errors; 2009a51f06e1SSelvin Xavier u32 local_qp_operation_errors; 2010a51f06e1SSelvin Xavier u32 retry_count_exceeded_errors; 2011a51f06e1SSelvin Xavier u32 rnr_retry_count_exceeded_errors; 2012a51f06e1SSelvin Xavier u32 rsvd[3]; 2013a51f06e1SSelvin Xavier }; 2014a51f06e1SSelvin Xavier 2015a51f06e1SSelvin Xavier struct ocrdma_rx_stats { 2016a51f06e1SSelvin Xavier u32 roce_frame_bytes_lo; 2017a51f06e1SSelvin Xavier u32 roce_frame_bytes_hi; 2018a51f06e1SSelvin Xavier u32 roce_frame_icrc_drops; 2019a51f06e1SSelvin Xavier u32 roce_frame_payload_len_drops; 2020a51f06e1SSelvin Xavier u32 ud_drops; 2021a51f06e1SSelvin Xavier u32 qp1_drops; 2022a51f06e1SSelvin Xavier u32 psn_error_request_packets; 2023a51f06e1SSelvin Xavier u32 psn_error_resp_packets; 2024a51f06e1SSelvin Xavier u32 rnr_nak_timeouts; 2025a51f06e1SSelvin Xavier u32 rnr_nak_receives; 2026a51f06e1SSelvin Xavier u32 roce_frame_rxmt_drops; 2027a51f06e1SSelvin Xavier u32 nak_count_psn_sequence_errors; 2028a51f06e1SSelvin Xavier u32 rc_drop_count_lookup_errors; 2029a51f06e1SSelvin Xavier u32 rq_rnr_naks; 2030a51f06e1SSelvin Xavier u32 srq_rnr_naks; 2031a51f06e1SSelvin Xavier u32 roce_frames_lo; 2032a51f06e1SSelvin Xavier u32 roce_frames_hi; 2033a51f06e1SSelvin Xavier u32 rsvd; 2034a51f06e1SSelvin Xavier }; 2035a51f06e1SSelvin Xavier 2036a51f06e1SSelvin Xavier struct ocrdma_rx_qp_err_stats { 20376296665cSColin Ian King u32 nak_invalid_request_errors; 2038a51f06e1SSelvin Xavier u32 nak_remote_operation_errors; 2039a51f06e1SSelvin Xavier u32 nak_count_remote_access_errors; 2040a51f06e1SSelvin Xavier u32 local_length_errors; 2041a51f06e1SSelvin Xavier u32 local_protection_errors; 2042a51f06e1SSelvin Xavier u32 local_qp_operation_errors; 2043a51f06e1SSelvin Xavier u32 rsvd[2]; 2044a51f06e1SSelvin Xavier }; 2045a51f06e1SSelvin Xavier 2046a51f06e1SSelvin Xavier struct ocrdma_tx_dbg_stats { 2047a51f06e1SSelvin Xavier u32 data[100]; 2048a51f06e1SSelvin Xavier }; 2049a51f06e1SSelvin Xavier 2050a51f06e1SSelvin Xavier struct ocrdma_rx_dbg_stats { 2051a51f06e1SSelvin Xavier u32 data[200]; 2052a51f06e1SSelvin Xavier }; 2053a51f06e1SSelvin Xavier 2054a51f06e1SSelvin Xavier struct ocrdma_rdma_stats_req { 2055a51f06e1SSelvin Xavier struct ocrdma_mbx_hdr hdr; 2056a51f06e1SSelvin Xavier u8 reset_stats; 2057a51f06e1SSelvin Xavier u8 rsvd[3]; 2058a51f06e1SSelvin Xavier } __packed; 2059a51f06e1SSelvin Xavier 2060a51f06e1SSelvin Xavier struct ocrdma_rdma_stats_resp { 2061a51f06e1SSelvin Xavier struct ocrdma_mbx_hdr hdr; 2062a51f06e1SSelvin Xavier struct ocrdma_rsrc_stats act_rsrc_stats; 2063a51f06e1SSelvin Xavier struct ocrdma_rsrc_stats th_rsrc_stats; 2064a51f06e1SSelvin Xavier struct ocrdma_db_err_stats db_err_stats; 2065a51f06e1SSelvin Xavier struct ocrdma_wqe_stats wqe_stats; 2066a51f06e1SSelvin Xavier struct ocrdma_tx_stats tx_stats; 2067a51f06e1SSelvin Xavier struct ocrdma_tx_qp_err_stats tx_qp_err_stats; 2068a51f06e1SSelvin Xavier struct ocrdma_rx_stats rx_stats; 2069a51f06e1SSelvin Xavier struct ocrdma_rx_qp_err_stats rx_qp_err_stats; 2070a51f06e1SSelvin Xavier struct ocrdma_tx_dbg_stats tx_dbg_stats; 2071a51f06e1SSelvin Xavier struct ocrdma_rx_dbg_stats rx_dbg_stats; 2072a51f06e1SSelvin Xavier } __packed; 2073a51f06e1SSelvin Xavier 20748ac0c7c7SDevesh Sharma enum { 20758ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK = 0xFF, 20768ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK = 0xFF00, 20778ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT = 0x08, 20788ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_CDBLEN_MASK = 0xFFFF, 20798ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_ASIC_REV_MASK = 0xFF0000, 20808ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT = 0x10, 20818ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_GUID0_MASK = 0xFF000000, 20828ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_GUID0_SHIFT = 0x18, 20838ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_GUID13_MASK = 0xFF, 20848ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_GUID14_MASK = 0xFF00, 20858ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_GUID14_SHIFT = 0x08, 20868ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_GUID15_MASK = 0xFF0000, 20878ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_GUID15_SHIFT = 0x10, 20888ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCNT_MASK = 0xFF000000, 20898ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCNT_SHIFT = 0x18, 20908ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_LDTOUT_MASK = 0xFFFF, 20918ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_ISCSI_VER_MASK = 0xFF0000, 20928ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT = 0x10, 20938ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK = 0xFF000000, 20948ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT = 0x18, 20958ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_CV_MASK = 0xFF, 20968ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_HBA_ST_MASK = 0xFF00, 20978ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_HBA_ST_SHIFT = 0x08, 20988ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_MAX_DOMS_MASK = 0xFF0000, 20998ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT = 0x10, 21008ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PTNUM_MASK = 0x3F000000, 21018ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PTNUM_SHIFT = 0x18, 21028ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PT_MASK = 0xC0000000, 21038ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PT_SHIFT = 0x1E, 21048ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_ISCSI_FET_MASK = 0xFF, 21058ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_ASIC_GEN_MASK = 0xFF00, 21068ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT = 0x08, 21078ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_VID_MASK = 0xFFFF, 21088ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_DID_MASK = 0xFFFF0000, 21098ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_DID_SHIFT = 0x10, 21108ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_SVID_MASK = 0xFFFF, 21118ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_SSID_MASK = 0xFFFF0000, 21128ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT = 0x10, 21138ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK = 0xFF, 21148ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK = 0xFF00, 21158ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT = 0x08, 21168ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK = 0xFF0000, 21178ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT = 0x10, 21188ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_IF_TYPE_MASK = 0xFF000000, 21198ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT = 0x18, 21208ac0c7c7SDevesh Sharma OCRDMA_HBA_ATTRB_NETFIL_MASK =0xFF 21218ac0c7c7SDevesh Sharma }; 2122a51f06e1SSelvin Xavier 2123a51f06e1SSelvin Xavier struct mgmt_hba_attribs { 2124a51f06e1SSelvin Xavier u8 flashrom_version_string[32]; 2125a51f06e1SSelvin Xavier u8 manufacturer_name[32]; 2126a51f06e1SSelvin Xavier u32 supported_modes; 21278ac0c7c7SDevesh Sharma u32 rsvd_eprom_verhi_verlo; 21288ac0c7c7SDevesh Sharma u32 mbx_ds_ver; 21298ac0c7c7SDevesh Sharma u32 epfw_ds_ver; 2130a51f06e1SSelvin Xavier u8 ncsi_ver_string[12]; 2131a51f06e1SSelvin Xavier u32 default_extended_timeout; 2132a51f06e1SSelvin Xavier u8 controller_model_number[32]; 2133a51f06e1SSelvin Xavier u8 controller_description[64]; 2134a51f06e1SSelvin Xavier u8 controller_serial_number[32]; 2135a51f06e1SSelvin Xavier u8 ip_version_string[32]; 2136a51f06e1SSelvin Xavier u8 firmware_version_string[32]; 2137a51f06e1SSelvin Xavier u8 bios_version_string[32]; 2138a51f06e1SSelvin Xavier u8 redboot_version_string[32]; 2139a51f06e1SSelvin Xavier u8 driver_version_string[32]; 2140a51f06e1SSelvin Xavier u8 fw_on_flash_version_string[32]; 2141a51f06e1SSelvin Xavier u32 functionalities_supported; 21428ac0c7c7SDevesh Sharma u32 guid0_asicrev_cdblen; 21438ac0c7c7SDevesh Sharma u8 generational_guid[12]; 21448ac0c7c7SDevesh Sharma u32 portcnt_guid15; 21458ac0c7c7SDevesh Sharma u32 mfuncdev_iscsi_ldtout; 21468ac0c7c7SDevesh Sharma u32 ptpnum_maxdoms_hbast_cv; 2147a51f06e1SSelvin Xavier u32 firmware_post_status; 2148a51f06e1SSelvin Xavier u32 hba_mtu[8]; 21498ac0c7c7SDevesh Sharma u32 res_asicgen_iscsi_feaures; 21508ac0c7c7SDevesh Sharma u32 rsvd1[3]; 2151a51f06e1SSelvin Xavier }; 2152a51f06e1SSelvin Xavier 2153a51f06e1SSelvin Xavier struct mgmt_controller_attrib { 2154a51f06e1SSelvin Xavier struct mgmt_hba_attribs hba_attribs; 21558ac0c7c7SDevesh Sharma u32 pci_did_vid; 21568ac0c7c7SDevesh Sharma u32 pci_ssid_svid; 21578ac0c7c7SDevesh Sharma u32 ityp_fnum_devnum_bnum; 21588ac0c7c7SDevesh Sharma u32 uid_hi; 21598ac0c7c7SDevesh Sharma u32 uid_lo; 21608ac0c7c7SDevesh Sharma u32 res_nnetfil; 21618ac0c7c7SDevesh Sharma u32 rsvd0[4]; 2162a51f06e1SSelvin Xavier }; 2163a51f06e1SSelvin Xavier 2164a51f06e1SSelvin Xavier struct ocrdma_get_ctrl_attribs_rsp { 2165a51f06e1SSelvin Xavier struct ocrdma_mbx_hdr hdr; 2166a51f06e1SSelvin Xavier struct mgmt_controller_attrib ctrl_attribs; 2167a51f06e1SSelvin Xavier }; 2168a51f06e1SSelvin Xavier 216931dbdd9aSSelvin Xavier #define OCRDMA_SUBSYS_DCBX 0x10 217031dbdd9aSSelvin Xavier 217131dbdd9aSSelvin Xavier enum OCRDMA_DCBX_OPCODE { 217231dbdd9aSSelvin Xavier OCRDMA_CMD_GET_DCBX_CONFIG = 0x01 217331dbdd9aSSelvin Xavier }; 217431dbdd9aSSelvin Xavier 217531dbdd9aSSelvin Xavier enum OCRDMA_DCBX_PARAM_TYPE { 217631dbdd9aSSelvin Xavier OCRDMA_PARAMETER_TYPE_ADMIN = 0x00, 217731dbdd9aSSelvin Xavier OCRDMA_PARAMETER_TYPE_OPER = 0x01, 217831dbdd9aSSelvin Xavier OCRDMA_PARAMETER_TYPE_PEER = 0x02 217931dbdd9aSSelvin Xavier }; 218031dbdd9aSSelvin Xavier 218131dbdd9aSSelvin Xavier enum OCRDMA_DCBX_PROTO { 218231dbdd9aSSelvin Xavier OCRDMA_PROTO_SELECT_L2 = 0x00, 218331dbdd9aSSelvin Xavier OCRDMA_PROTO_SELECT_L4 = 0x01 218431dbdd9aSSelvin Xavier }; 218531dbdd9aSSelvin Xavier 218631dbdd9aSSelvin Xavier enum OCRDMA_DCBX_APP_PARAM { 218731dbdd9aSSelvin Xavier OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF, 218831dbdd9aSSelvin Xavier OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF, 218931dbdd9aSSelvin Xavier OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10, 219031dbdd9aSSelvin Xavier OCRDMA_APP_PARAM_VALID_MASK = 0xFF, 219131dbdd9aSSelvin Xavier OCRDMA_APP_PARAM_VALID_SHIFT = 0x18 219231dbdd9aSSelvin Xavier }; 219331dbdd9aSSelvin Xavier 219431dbdd9aSSelvin Xavier enum OCRDMA_DCBX_STATE_FLAGS { 219531dbdd9aSSelvin Xavier OCRDMA_STATE_FLAG_ENABLED = 0x01, 219631dbdd9aSSelvin Xavier OCRDMA_STATE_FLAG_ADDVERTISED = 0x02, 219731dbdd9aSSelvin Xavier OCRDMA_STATE_FLAG_WILLING = 0x04, 219831dbdd9aSSelvin Xavier OCRDMA_STATE_FLAG_SYNC = 0x08, 219931dbdd9aSSelvin Xavier OCRDMA_STATE_FLAG_UNSUPPORTED = 0x40000000, 220031dbdd9aSSelvin Xavier OCRDMA_STATE_FLAG_NEG_FAILD = 0x80000000 220131dbdd9aSSelvin Xavier }; 220231dbdd9aSSelvin Xavier 220331dbdd9aSSelvin Xavier enum OCRDMA_TCV_AEV_OPV_ST { 220431dbdd9aSSelvin Xavier OCRDMA_DCBX_TC_SUPPORT_MASK = 0xFF, 220531dbdd9aSSelvin Xavier OCRDMA_DCBX_TC_SUPPORT_SHIFT = 0x18, 220631dbdd9aSSelvin Xavier OCRDMA_DCBX_APP_ENTRY_SHIFT = 0x10, 220731dbdd9aSSelvin Xavier OCRDMA_DCBX_OP_PARAM_SHIFT = 0x08, 220831dbdd9aSSelvin Xavier OCRDMA_DCBX_STATE_MASK = 0xFF 220931dbdd9aSSelvin Xavier }; 221031dbdd9aSSelvin Xavier 221131dbdd9aSSelvin Xavier struct ocrdma_app_parameter { 221231dbdd9aSSelvin Xavier u32 valid_proto_app; 221331dbdd9aSSelvin Xavier u32 oui; 221431dbdd9aSSelvin Xavier u32 app_prio[2]; 221531dbdd9aSSelvin Xavier }; 221631dbdd9aSSelvin Xavier 221731dbdd9aSSelvin Xavier struct ocrdma_dcbx_cfg { 221831dbdd9aSSelvin Xavier u32 tcv_aev_opv_st; 221931dbdd9aSSelvin Xavier u32 tc_state; 222031dbdd9aSSelvin Xavier u32 pfc_state; 222131dbdd9aSSelvin Xavier u32 qcn_state; 222231dbdd9aSSelvin Xavier u32 appl_state; 222331dbdd9aSSelvin Xavier u32 ll_state; 222431dbdd9aSSelvin Xavier u32 tc_bw[2]; 222531dbdd9aSSelvin Xavier u32 tc_prio[8]; 222631dbdd9aSSelvin Xavier u32 pfc_prio[2]; 222731dbdd9aSSelvin Xavier struct ocrdma_app_parameter app_param[15]; 222831dbdd9aSSelvin Xavier }; 222931dbdd9aSSelvin Xavier 223031dbdd9aSSelvin Xavier struct ocrdma_get_dcbx_cfg_req { 223131dbdd9aSSelvin Xavier struct ocrdma_mbx_hdr hdr; 223231dbdd9aSSelvin Xavier u32 param_type; 223331dbdd9aSSelvin Xavier } __packed; 223431dbdd9aSSelvin Xavier 223531dbdd9aSSelvin Xavier struct ocrdma_get_dcbx_cfg_rsp { 223631dbdd9aSSelvin Xavier struct ocrdma_mbx_rsp hdr; 223731dbdd9aSSelvin Xavier struct ocrdma_dcbx_cfg cfg; 223831dbdd9aSSelvin Xavier } __packed; 2239a51f06e1SSelvin Xavier 2240fe2caefcSParav Pandit #endif /* __OCRDMA_SLI_H__ */ 2241