1 /*******************************************************************
2  * This file is part of the Emulex RoCE Device Driver for          *
3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
5  * EMULEX and SLI are trademarks of Emulex.                        *
6  * www.emulex.com                                                  *
7  *                                                                 *
8  * This program is free software; you can redistribute it and/or   *
9  * modify it under the terms of version 2 of the GNU General       *
10  * Public License as published by the Free Software Foundation.    *
11  * This program is distributed in the hope that it will be useful. *
12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
17  * more details, a copy of which can be found in the file COPYING  *
18  * included with this package.                                     *
19  *
20  * Contact Information:
21  * linux-drivers@emulex.com
22  *
23  * Emulex
24  * 3333 Susan Street
25  * Costa Mesa, CA 92626
26  *******************************************************************/
27 
28 #include <linux/sched.h>
29 #include <linux/interrupt.h>
30 #include <linux/log2.h>
31 #include <linux/dma-mapping.h>
32 
33 #include <rdma/ib_verbs.h>
34 #include <rdma/ib_user_verbs.h>
35 
36 #include "ocrdma.h"
37 #include "ocrdma_hw.h"
38 #include "ocrdma_verbs.h"
39 #include "ocrdma_ah.h"
40 
41 enum mbx_status {
42 	OCRDMA_MBX_STATUS_FAILED		= 1,
43 	OCRDMA_MBX_STATUS_ILLEGAL_FIELD		= 3,
44 	OCRDMA_MBX_STATUS_OOR			= 100,
45 	OCRDMA_MBX_STATUS_INVALID_PD		= 101,
46 	OCRDMA_MBX_STATUS_PD_INUSE		= 102,
47 	OCRDMA_MBX_STATUS_INVALID_CQ		= 103,
48 	OCRDMA_MBX_STATUS_INVALID_QP		= 104,
49 	OCRDMA_MBX_STATUS_INVALID_LKEY		= 105,
50 	OCRDMA_MBX_STATUS_ORD_EXCEEDS		= 106,
51 	OCRDMA_MBX_STATUS_IRD_EXCEEDS		= 107,
52 	OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS	= 108,
53 	OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS	= 109,
54 	OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS	= 110,
55 	OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS	= 111,
56 	OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS	= 112,
57 	OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE	= 113,
58 	OCRDMA_MBX_STATUS_MW_BOUND		= 114,
59 	OCRDMA_MBX_STATUS_INVALID_VA		= 115,
60 	OCRDMA_MBX_STATUS_INVALID_LENGTH	= 116,
61 	OCRDMA_MBX_STATUS_INVALID_FBO		= 117,
62 	OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS	= 118,
63 	OCRDMA_MBX_STATUS_INVALID_PBE_SIZE	= 119,
64 	OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY	= 120,
65 	OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT	= 121,
66 	OCRDMA_MBX_STATUS_INVALID_SRQ_ID	= 129,
67 	OCRDMA_MBX_STATUS_SRQ_ERROR		= 133,
68 	OCRDMA_MBX_STATUS_RQE_EXCEEDS		= 134,
69 	OCRDMA_MBX_STATUS_MTU_EXCEEDS		= 135,
70 	OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS	= 136,
71 	OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS	= 137,
72 	OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS	= 138,
73 	OCRDMA_MBX_STATUS_QP_BOUND		= 130,
74 	OCRDMA_MBX_STATUS_INVALID_CHANGE	= 139,
75 	OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP	= 140,
76 	OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER	= 141,
77 	OCRDMA_MBX_STATUS_MW_STILL_BOUND	= 142,
78 	OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID	= 143,
79 	OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS	= 144
80 };
81 
82 enum additional_status {
83 	OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
84 };
85 
86 enum cqe_status {
87 	OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES	= 1,
88 	OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER		= 2,
89 	OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES	= 3,
90 	OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING		= 4,
91 	OCRDMA_MBX_CQE_STATUS_DMA_FAILED		= 5
92 };
93 
94 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
95 {
96 	return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
97 }
98 
99 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
100 {
101 	eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
102 }
103 
104 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
105 {
106 	struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
107 	    (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
108 
109 	if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
110 		return NULL;
111 	return cqe;
112 }
113 
114 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
115 {
116 	dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
117 }
118 
119 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
120 {
121 	return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
122 }
123 
124 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
125 {
126 	dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
127 }
128 
129 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
130 {
131 	return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
132 }
133 
134 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
135 {
136 	switch (qps) {
137 	case OCRDMA_QPS_RST:
138 		return IB_QPS_RESET;
139 	case OCRDMA_QPS_INIT:
140 		return IB_QPS_INIT;
141 	case OCRDMA_QPS_RTR:
142 		return IB_QPS_RTR;
143 	case OCRDMA_QPS_RTS:
144 		return IB_QPS_RTS;
145 	case OCRDMA_QPS_SQD:
146 	case OCRDMA_QPS_SQ_DRAINING:
147 		return IB_QPS_SQD;
148 	case OCRDMA_QPS_SQE:
149 		return IB_QPS_SQE;
150 	case OCRDMA_QPS_ERR:
151 		return IB_QPS_ERR;
152 	}
153 	return IB_QPS_ERR;
154 }
155 
156 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
157 {
158 	switch (qps) {
159 	case IB_QPS_RESET:
160 		return OCRDMA_QPS_RST;
161 	case IB_QPS_INIT:
162 		return OCRDMA_QPS_INIT;
163 	case IB_QPS_RTR:
164 		return OCRDMA_QPS_RTR;
165 	case IB_QPS_RTS:
166 		return OCRDMA_QPS_RTS;
167 	case IB_QPS_SQD:
168 		return OCRDMA_QPS_SQD;
169 	case IB_QPS_SQE:
170 		return OCRDMA_QPS_SQE;
171 	case IB_QPS_ERR:
172 		return OCRDMA_QPS_ERR;
173 	}
174 	return OCRDMA_QPS_ERR;
175 }
176 
177 static int ocrdma_get_mbx_errno(u32 status)
178 {
179 	int err_num;
180 	u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
181 					OCRDMA_MBX_RSP_STATUS_SHIFT;
182 	u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
183 					OCRDMA_MBX_RSP_ASTATUS_SHIFT;
184 
185 	switch (mbox_status) {
186 	case OCRDMA_MBX_STATUS_OOR:
187 	case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
188 		err_num = -EAGAIN;
189 		break;
190 
191 	case OCRDMA_MBX_STATUS_INVALID_PD:
192 	case OCRDMA_MBX_STATUS_INVALID_CQ:
193 	case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
194 	case OCRDMA_MBX_STATUS_INVALID_QP:
195 	case OCRDMA_MBX_STATUS_INVALID_CHANGE:
196 	case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
197 	case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
198 	case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
199 	case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
200 	case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
201 	case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
202 	case OCRDMA_MBX_STATUS_INVALID_LKEY:
203 	case OCRDMA_MBX_STATUS_INVALID_VA:
204 	case OCRDMA_MBX_STATUS_INVALID_LENGTH:
205 	case OCRDMA_MBX_STATUS_INVALID_FBO:
206 	case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
207 	case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
208 	case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
209 	case OCRDMA_MBX_STATUS_SRQ_ERROR:
210 	case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
211 		err_num = -EINVAL;
212 		break;
213 
214 	case OCRDMA_MBX_STATUS_PD_INUSE:
215 	case OCRDMA_MBX_STATUS_QP_BOUND:
216 	case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
217 	case OCRDMA_MBX_STATUS_MW_BOUND:
218 		err_num = -EBUSY;
219 		break;
220 
221 	case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
222 	case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
223 	case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
224 	case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
225 	case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
226 	case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
227 	case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
228 	case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
229 	case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
230 		err_num = -ENOBUFS;
231 		break;
232 
233 	case OCRDMA_MBX_STATUS_FAILED:
234 		switch (add_status) {
235 		case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
236 			err_num = -EAGAIN;
237 			break;
238 		}
239 	default:
240 		err_num = -EFAULT;
241 	}
242 	return err_num;
243 }
244 
245 char *port_speed_string(struct ocrdma_dev *dev)
246 {
247 	char *str = "";
248 	u16 speeds_supported;
249 
250 	speeds_supported = dev->phy.fixed_speeds_supported |
251 				dev->phy.auto_speeds_supported;
252 	if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
253 		str = "40Gbps ";
254 	else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
255 		str = "10Gbps ";
256 	else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
257 		str = "1Gbps ";
258 
259 	return str;
260 }
261 
262 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
263 {
264 	int err_num = -EINVAL;
265 
266 	switch (cqe_status) {
267 	case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
268 		err_num = -EPERM;
269 		break;
270 	case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
271 		err_num = -EINVAL;
272 		break;
273 	case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
274 	case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
275 		err_num = -EINVAL;
276 		break;
277 	case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
278 	default:
279 		err_num = -EINVAL;
280 		break;
281 	}
282 	return err_num;
283 }
284 
285 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
286 		       bool solicited, u16 cqe_popped)
287 {
288 	u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
289 
290 	val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
291 	     OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
292 
293 	if (armed)
294 		val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
295 	if (solicited)
296 		val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
297 	val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
298 	iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
299 }
300 
301 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
302 {
303 	u32 val = 0;
304 
305 	val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
306 	val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
307 	iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
308 }
309 
310 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
311 			      bool arm, bool clear_int, u16 num_eqe)
312 {
313 	u32 val = 0;
314 
315 	val |= eq_id & OCRDMA_EQ_ID_MASK;
316 	val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
317 	if (arm)
318 		val |= (1 << OCRDMA_REARM_SHIFT);
319 	if (clear_int)
320 		val |= (1 << OCRDMA_EQ_CLR_SHIFT);
321 	val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
322 	val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
323 	iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
324 }
325 
326 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
327 			    u8 opcode, u8 subsys, u32 cmd_len)
328 {
329 	cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
330 	cmd_hdr->timeout = 20; /* seconds */
331 	cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
332 }
333 
334 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
335 {
336 	struct ocrdma_mqe *mqe;
337 
338 	mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
339 	if (!mqe)
340 		return NULL;
341 	mqe->hdr.spcl_sge_cnt_emb |=
342 		(OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
343 					OCRDMA_MQE_HDR_EMB_MASK;
344 	mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
345 
346 	ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
347 			mqe->hdr.pyld_len);
348 	return mqe;
349 }
350 
351 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
352 {
353 	dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
354 }
355 
356 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
357 			  struct ocrdma_queue_info *q, u16 len, u16 entry_size)
358 {
359 	memset(q, 0, sizeof(*q));
360 	q->len = len;
361 	q->entry_size = entry_size;
362 	q->size = len * entry_size;
363 	q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
364 				   &q->dma, GFP_KERNEL);
365 	if (!q->va)
366 		return -ENOMEM;
367 	memset(q->va, 0, q->size);
368 	return 0;
369 }
370 
371 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
372 					dma_addr_t host_pa, int hw_page_size)
373 {
374 	int i;
375 
376 	for (i = 0; i < cnt; i++) {
377 		q_pa[i].lo = (u32) (host_pa & 0xffffffff);
378 		q_pa[i].hi = (u32) upper_32_bits(host_pa);
379 		host_pa += hw_page_size;
380 	}
381 }
382 
383 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
384 			       struct ocrdma_queue_info *q, int queue_type)
385 {
386 	u8 opcode = 0;
387 	int status;
388 	struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
389 
390 	switch (queue_type) {
391 	case QTYPE_MCCQ:
392 		opcode = OCRDMA_CMD_DELETE_MQ;
393 		break;
394 	case QTYPE_CQ:
395 		opcode = OCRDMA_CMD_DELETE_CQ;
396 		break;
397 	case QTYPE_EQ:
398 		opcode = OCRDMA_CMD_DELETE_EQ;
399 		break;
400 	default:
401 		BUG();
402 	}
403 	memset(cmd, 0, sizeof(*cmd));
404 	ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
405 	cmd->id = q->id;
406 
407 	status = be_roce_mcc_cmd(dev->nic_info.netdev,
408 				 cmd, sizeof(*cmd), NULL, NULL);
409 	if (!status)
410 		q->created = false;
411 	return status;
412 }
413 
414 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
415 {
416 	int status;
417 	struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
418 	struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
419 
420 	memset(cmd, 0, sizeof(*cmd));
421 	ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
422 			sizeof(*cmd));
423 
424 	cmd->req.rsvd_version = 2;
425 	cmd->num_pages = 4;
426 	cmd->valid = OCRDMA_CREATE_EQ_VALID;
427 	cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
428 
429 	ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
430 			     PAGE_SIZE_4K);
431 	status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
432 				 NULL);
433 	if (!status) {
434 		eq->q.id = rsp->vector_eqid & 0xffff;
435 		eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
436 		eq->q.created = true;
437 	}
438 	return status;
439 }
440 
441 static int ocrdma_create_eq(struct ocrdma_dev *dev,
442 			    struct ocrdma_eq *eq, u16 q_len)
443 {
444 	int status;
445 
446 	status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
447 				sizeof(struct ocrdma_eqe));
448 	if (status)
449 		return status;
450 
451 	status = ocrdma_mbx_create_eq(dev, eq);
452 	if (status)
453 		goto mbx_err;
454 	eq->dev = dev;
455 	ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
456 
457 	return 0;
458 mbx_err:
459 	ocrdma_free_q(dev, &eq->q);
460 	return status;
461 }
462 
463 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
464 {
465 	int irq;
466 
467 	if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
468 		irq = dev->nic_info.pdev->irq;
469 	else
470 		irq = dev->nic_info.msix.vector_list[eq->vector];
471 	return irq;
472 }
473 
474 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
475 {
476 	if (eq->q.created) {
477 		ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
478 		ocrdma_free_q(dev, &eq->q);
479 	}
480 }
481 
482 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
483 {
484 	int irq;
485 
486 	/* disarm EQ so that interrupts are not generated
487 	 * during freeing and EQ delete is in progress.
488 	 */
489 	ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
490 
491 	irq = ocrdma_get_irq(dev, eq);
492 	free_irq(irq, eq);
493 	_ocrdma_destroy_eq(dev, eq);
494 }
495 
496 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
497 {
498 	int i;
499 
500 	for (i = 0; i < dev->eq_cnt; i++)
501 		ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
502 }
503 
504 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
505 				   struct ocrdma_queue_info *cq,
506 				   struct ocrdma_queue_info *eq)
507 {
508 	struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
509 	struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
510 	int status;
511 
512 	memset(cmd, 0, sizeof(*cmd));
513 	ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
514 			OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
515 
516 	cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
517 	cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
518 		OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
519 	cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
520 
521 	cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
522 	cmd->eqn = eq->id;
523 	cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
524 
525 	ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
526 			     cq->dma, PAGE_SIZE_4K);
527 	status = be_roce_mcc_cmd(dev->nic_info.netdev,
528 				 cmd, sizeof(*cmd), NULL, NULL);
529 	if (!status) {
530 		cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
531 		cq->created = true;
532 	}
533 	return status;
534 }
535 
536 static u32 ocrdma_encoded_q_len(int q_len)
537 {
538 	u32 len_encoded = fls(q_len);	/* log2(len) + 1 */
539 
540 	if (len_encoded == 16)
541 		len_encoded = 0;
542 	return len_encoded;
543 }
544 
545 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
546 				struct ocrdma_queue_info *mq,
547 				struct ocrdma_queue_info *cq)
548 {
549 	int num_pages, status;
550 	struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
551 	struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
552 	struct ocrdma_pa *pa;
553 
554 	memset(cmd, 0, sizeof(*cmd));
555 	num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
556 
557 	ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
558 			OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
559 	cmd->req.rsvd_version = 1;
560 	cmd->cqid_pages = num_pages;
561 	cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
562 	cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
563 
564 	cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
565 	cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
566 
567 	cmd->async_cqid_ringsize = cq->id;
568 	cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
569 				OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
570 	cmd->valid = OCRDMA_CREATE_MQ_VALID;
571 	pa = &cmd->pa[0];
572 
573 	ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
574 	status = be_roce_mcc_cmd(dev->nic_info.netdev,
575 				 cmd, sizeof(*cmd), NULL, NULL);
576 	if (!status) {
577 		mq->id = rsp->id;
578 		mq->created = true;
579 	}
580 	return status;
581 }
582 
583 static int ocrdma_create_mq(struct ocrdma_dev *dev)
584 {
585 	int status;
586 
587 	/* Alloc completion queue for Mailbox queue */
588 	status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
589 				sizeof(struct ocrdma_mcqe));
590 	if (status)
591 		goto alloc_err;
592 
593 	dev->eq_tbl[0].cq_cnt++;
594 	status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
595 	if (status)
596 		goto mbx_cq_free;
597 
598 	memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
599 	init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
600 	mutex_init(&dev->mqe_ctx.lock);
601 
602 	/* Alloc Mailbox queue */
603 	status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
604 				sizeof(struct ocrdma_mqe));
605 	if (status)
606 		goto mbx_cq_destroy;
607 	status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
608 	if (status)
609 		goto mbx_q_free;
610 	ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
611 	return 0;
612 
613 mbx_q_free:
614 	ocrdma_free_q(dev, &dev->mq.sq);
615 mbx_cq_destroy:
616 	ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
617 mbx_cq_free:
618 	ocrdma_free_q(dev, &dev->mq.cq);
619 alloc_err:
620 	return status;
621 }
622 
623 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
624 {
625 	struct ocrdma_queue_info *mbxq, *cq;
626 
627 	/* mqe_ctx lock synchronizes with any other pending cmds. */
628 	mutex_lock(&dev->mqe_ctx.lock);
629 	mbxq = &dev->mq.sq;
630 	if (mbxq->created) {
631 		ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
632 		ocrdma_free_q(dev, mbxq);
633 	}
634 	mutex_unlock(&dev->mqe_ctx.lock);
635 
636 	cq = &dev->mq.cq;
637 	if (cq->created) {
638 		ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
639 		ocrdma_free_q(dev, cq);
640 	}
641 }
642 
643 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
644 				       struct ocrdma_qp *qp)
645 {
646 	enum ib_qp_state new_ib_qps = IB_QPS_ERR;
647 	enum ib_qp_state old_ib_qps;
648 
649 	if (qp == NULL)
650 		BUG();
651 	ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
652 }
653 
654 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
655 				    struct ocrdma_ae_mcqe *cqe)
656 {
657 	struct ocrdma_qp *qp = NULL;
658 	struct ocrdma_cq *cq = NULL;
659 	struct ib_event ib_evt;
660 	int cq_event = 0;
661 	int qp_event = 1;
662 	int srq_event = 0;
663 	int dev_event = 0;
664 	int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
665 	    OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
666 
667 	if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
668 		qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
669 	if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
670 		cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
671 
672 	memset(&ib_evt, 0, sizeof(ib_evt));
673 
674 	ib_evt.device = &dev->ibdev;
675 
676 	switch (type) {
677 	case OCRDMA_CQ_ERROR:
678 		ib_evt.element.cq = &cq->ibcq;
679 		ib_evt.event = IB_EVENT_CQ_ERR;
680 		cq_event = 1;
681 		qp_event = 0;
682 		break;
683 	case OCRDMA_CQ_OVERRUN_ERROR:
684 		ib_evt.element.cq = &cq->ibcq;
685 		ib_evt.event = IB_EVENT_CQ_ERR;
686 		cq_event = 1;
687 		qp_event = 0;
688 		break;
689 	case OCRDMA_CQ_QPCAT_ERROR:
690 		ib_evt.element.qp = &qp->ibqp;
691 		ib_evt.event = IB_EVENT_QP_FATAL;
692 		ocrdma_process_qpcat_error(dev, qp);
693 		break;
694 	case OCRDMA_QP_ACCESS_ERROR:
695 		ib_evt.element.qp = &qp->ibqp;
696 		ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
697 		break;
698 	case OCRDMA_QP_COMM_EST_EVENT:
699 		ib_evt.element.qp = &qp->ibqp;
700 		ib_evt.event = IB_EVENT_COMM_EST;
701 		break;
702 	case OCRDMA_SQ_DRAINED_EVENT:
703 		ib_evt.element.qp = &qp->ibqp;
704 		ib_evt.event = IB_EVENT_SQ_DRAINED;
705 		break;
706 	case OCRDMA_DEVICE_FATAL_EVENT:
707 		ib_evt.element.port_num = 1;
708 		ib_evt.event = IB_EVENT_DEVICE_FATAL;
709 		qp_event = 0;
710 		dev_event = 1;
711 		break;
712 	case OCRDMA_SRQCAT_ERROR:
713 		ib_evt.element.srq = &qp->srq->ibsrq;
714 		ib_evt.event = IB_EVENT_SRQ_ERR;
715 		srq_event = 1;
716 		qp_event = 0;
717 		break;
718 	case OCRDMA_SRQ_LIMIT_EVENT:
719 		ib_evt.element.srq = &qp->srq->ibsrq;
720 		ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
721 		srq_event = 1;
722 		qp_event = 0;
723 		break;
724 	case OCRDMA_QP_LAST_WQE_EVENT:
725 		ib_evt.element.qp = &qp->ibqp;
726 		ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
727 		break;
728 	default:
729 		cq_event = 0;
730 		qp_event = 0;
731 		srq_event = 0;
732 		dev_event = 0;
733 		pr_err("%s() unknown type=0x%x\n", __func__, type);
734 		break;
735 	}
736 
737 	if (qp_event) {
738 		if (qp->ibqp.event_handler)
739 			qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
740 	} else if (cq_event) {
741 		if (cq->ibcq.event_handler)
742 			cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
743 	} else if (srq_event) {
744 		if (qp->srq->ibsrq.event_handler)
745 			qp->srq->ibsrq.event_handler(&ib_evt,
746 						     qp->srq->ibsrq.
747 						     srq_context);
748 	} else if (dev_event) {
749 		pr_err("%s: Fatal event received\n", dev->ibdev.name);
750 		ib_dispatch_event(&ib_evt);
751 	}
752 
753 }
754 
755 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
756 					struct ocrdma_ae_mcqe *cqe)
757 {
758 	struct ocrdma_ae_pvid_mcqe *evt;
759 	int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
760 			OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
761 
762 	switch (type) {
763 	case OCRDMA_ASYNC_EVENT_PVID_STATE:
764 		evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
765 		if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
766 			OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
767 			dev->pvid = ((evt->tag_enabled &
768 					OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
769 					OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
770 		break;
771 
772 	case OCRDMA_ASYNC_EVENT_COS_VALUE:
773 		atomic_set(&dev->update_sl, 1);
774 		break;
775 	default:
776 		/* Not interested evts. */
777 		break;
778 	}
779 }
780 
781 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
782 {
783 	/* async CQE processing */
784 	struct ocrdma_ae_mcqe *cqe = ae_cqe;
785 	u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
786 			OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
787 
788 	if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
789 		ocrdma_dispatch_ibevent(dev, cqe);
790 	else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
791 		ocrdma_process_grp5_aync(dev, cqe);
792 	else
793 		pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
794 		       dev->id, evt_code);
795 }
796 
797 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
798 {
799 	if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
800 		dev->mqe_ctx.cqe_status = (cqe->status &
801 		     OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
802 		dev->mqe_ctx.ext_status =
803 		    (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
804 		    >> OCRDMA_MCQE_ESTATUS_SHIFT;
805 		dev->mqe_ctx.cmd_done = true;
806 		wake_up(&dev->mqe_ctx.cmd_wait);
807 	} else
808 		pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
809 		       __func__, cqe->tag_lo, dev->mqe_ctx.tag);
810 }
811 
812 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
813 {
814 	u16 cqe_popped = 0;
815 	struct ocrdma_mcqe *cqe;
816 
817 	while (1) {
818 		cqe = ocrdma_get_mcqe(dev);
819 		if (cqe == NULL)
820 			break;
821 		ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
822 		cqe_popped += 1;
823 		if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
824 			ocrdma_process_acqe(dev, cqe);
825 		else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
826 			ocrdma_process_mcqe(dev, cqe);
827 		memset(cqe, 0, sizeof(struct ocrdma_mcqe));
828 		ocrdma_mcq_inc_tail(dev);
829 	}
830 	ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
831 	return 0;
832 }
833 
834 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
835 				       struct ocrdma_cq *cq)
836 {
837 	unsigned long flags;
838 	struct ocrdma_qp *qp;
839 	bool buddy_cq_found = false;
840 	/* Go through list of QPs in error state which are using this CQ
841 	 * and invoke its callback handler to trigger CQE processing for
842 	 * error/flushed CQE. It is rare to find more than few entries in
843 	 * this list as most consumers stops after getting error CQE.
844 	 * List is traversed only once when a matching buddy cq found for a QP.
845 	 */
846 	spin_lock_irqsave(&dev->flush_q_lock, flags);
847 	list_for_each_entry(qp, &cq->sq_head, sq_entry) {
848 		if (qp->srq)
849 			continue;
850 		/* if wq and rq share the same cq, than comp_handler
851 		 * is already invoked.
852 		 */
853 		if (qp->sq_cq == qp->rq_cq)
854 			continue;
855 		/* if completion came on sq, rq's cq is buddy cq.
856 		 * if completion came on rq, sq's cq is buddy cq.
857 		 */
858 		if (qp->sq_cq == cq)
859 			cq = qp->rq_cq;
860 		else
861 			cq = qp->sq_cq;
862 		buddy_cq_found = true;
863 		break;
864 	}
865 	spin_unlock_irqrestore(&dev->flush_q_lock, flags);
866 	if (buddy_cq_found == false)
867 		return;
868 	if (cq->ibcq.comp_handler) {
869 		spin_lock_irqsave(&cq->comp_handler_lock, flags);
870 		(*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
871 		spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
872 	}
873 }
874 
875 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
876 {
877 	unsigned long flags;
878 	struct ocrdma_cq *cq;
879 
880 	if (cq_idx >= OCRDMA_MAX_CQ)
881 		BUG();
882 
883 	cq = dev->cq_tbl[cq_idx];
884 	if (cq == NULL)
885 		return;
886 
887 	if (cq->ibcq.comp_handler) {
888 		spin_lock_irqsave(&cq->comp_handler_lock, flags);
889 		(*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
890 		spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
891 	}
892 	ocrdma_qp_buddy_cq_handler(dev, cq);
893 }
894 
895 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
896 {
897 	/* process the MQ-CQE. */
898 	if (cq_id == dev->mq.cq.id)
899 		ocrdma_mq_cq_handler(dev, cq_id);
900 	else
901 		ocrdma_qp_cq_handler(dev, cq_id);
902 }
903 
904 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
905 {
906 	struct ocrdma_eq *eq = handle;
907 	struct ocrdma_dev *dev = eq->dev;
908 	struct ocrdma_eqe eqe;
909 	struct ocrdma_eqe *ptr;
910 	u16 cq_id;
911 	int budget = eq->cq_cnt;
912 
913 	do {
914 		ptr = ocrdma_get_eqe(eq);
915 		eqe = *ptr;
916 		ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
917 		if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
918 			break;
919 
920 		ptr->id_valid = 0;
921 		/* ring eq doorbell as soon as its consumed. */
922 		ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
923 		/* check whether its CQE or not. */
924 		if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
925 			cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
926 			ocrdma_cq_handler(dev, cq_id);
927 		}
928 		ocrdma_eq_inc_tail(eq);
929 
930 		/* There can be a stale EQE after the last bound CQ is
931 		 * destroyed. EQE valid and budget == 0 implies this.
932 		 */
933 		if (budget)
934 			budget--;
935 
936 	} while (budget);
937 
938 	ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
939 	return IRQ_HANDLED;
940 }
941 
942 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
943 {
944 	struct ocrdma_mqe *mqe;
945 
946 	dev->mqe_ctx.tag = dev->mq.sq.head;
947 	dev->mqe_ctx.cmd_done = false;
948 	mqe = ocrdma_get_mqe(dev);
949 	cmd->hdr.tag_lo = dev->mq.sq.head;
950 	ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
951 	/* make sure descriptor is written before ringing doorbell */
952 	wmb();
953 	ocrdma_mq_inc_head(dev);
954 	ocrdma_ring_mq_db(dev);
955 }
956 
957 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
958 {
959 	long status;
960 	/* 30 sec timeout */
961 	status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
962 				    (dev->mqe_ctx.cmd_done != false),
963 				    msecs_to_jiffies(30000));
964 	if (status)
965 		return 0;
966 	else {
967 		dev->mqe_ctx.fw_error_state = true;
968 		pr_err("%s(%d) mailbox timeout: fw not responding\n",
969 		       __func__, dev->id);
970 		return -1;
971 	}
972 }
973 
974 /* issue a mailbox command on the MQ */
975 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
976 {
977 	int status = 0;
978 	u16 cqe_status, ext_status;
979 	struct ocrdma_mqe *rsp_mqe;
980 	struct ocrdma_mbx_rsp *rsp = NULL;
981 
982 	mutex_lock(&dev->mqe_ctx.lock);
983 	if (dev->mqe_ctx.fw_error_state)
984 		goto mbx_err;
985 	ocrdma_post_mqe(dev, mqe);
986 	status = ocrdma_wait_mqe_cmpl(dev);
987 	if (status)
988 		goto mbx_err;
989 	cqe_status = dev->mqe_ctx.cqe_status;
990 	ext_status = dev->mqe_ctx.ext_status;
991 	rsp_mqe = ocrdma_get_mqe_rsp(dev);
992 	ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
993 	if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
994 				OCRDMA_MQE_HDR_EMB_SHIFT)
995 		rsp = &mqe->u.rsp;
996 
997 	if (cqe_status || ext_status) {
998 		pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
999 		       __func__, cqe_status, ext_status);
1000 		if (rsp) {
1001 			/* This is for embedded cmds. */
1002 			pr_err("opcode=0x%x, subsystem=0x%x\n",
1003 			       (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1004 				OCRDMA_MBX_RSP_OPCODE_SHIFT,
1005 				(rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1006 				OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1007 		}
1008 		status = ocrdma_get_mbx_cqe_errno(cqe_status);
1009 		goto mbx_err;
1010 	}
1011 	/* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1012 	if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1013 		status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1014 mbx_err:
1015 	mutex_unlock(&dev->mqe_ctx.lock);
1016 	return status;
1017 }
1018 
1019 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1020 				 void *payload_va)
1021 {
1022 	int status = 0;
1023 	struct ocrdma_mbx_rsp *rsp = payload_va;
1024 
1025 	if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1026 				OCRDMA_MQE_HDR_EMB_SHIFT)
1027 		BUG();
1028 
1029 	status = ocrdma_mbx_cmd(dev, mqe);
1030 	if (!status)
1031 		/* For non embedded, only CQE failures are handled in
1032 		 * ocrdma_mbx_cmd. We need to check for RSP errors.
1033 		 */
1034 		if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1035 			status = ocrdma_get_mbx_errno(rsp->status);
1036 
1037 	if (status)
1038 		pr_err("opcode=0x%x, subsystem=0x%x\n",
1039 		       (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1040 			OCRDMA_MBX_RSP_OPCODE_SHIFT,
1041 			(rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1042 			OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1043 	return status;
1044 }
1045 
1046 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1047 			      struct ocrdma_dev_attr *attr,
1048 			      struct ocrdma_mbx_query_config *rsp)
1049 {
1050 	attr->max_pd =
1051 	    (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1052 	    OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1053 	attr->max_qp =
1054 	    (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1055 	    OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1056 	attr->max_srq =
1057 		(rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1058 		OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1059 	attr->max_send_sge = ((rsp->max_write_send_sge &
1060 			       OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1061 			      OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1062 	attr->max_recv_sge = (rsp->max_write_send_sge &
1063 			      OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1064 	    OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1065 	attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1066 			      OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1067 	    OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1068 	attr->max_rdma_sge = (rsp->max_write_send_sge &
1069 			      OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1070 	    OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1071 	attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1072 				OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1073 	    OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1074 	attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1075 				OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1076 	    OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1077 	attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1078 				    OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1079 	    OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1080 	attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1081 			       OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1082 	    OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1083 	attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1084 				    OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1085 	    OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1086 	attr->max_mw = rsp->max_mw;
1087 	attr->max_mr = rsp->max_mr;
1088 	attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1089 			      rsp->max_mr_size_lo;
1090 	attr->max_fmr = 0;
1091 	attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1092 	attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1093 	attr->max_cqe = rsp->max_cq_cqes_per_cq &
1094 			OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1095 	attr->max_cq = (rsp->max_cq_cqes_per_cq &
1096 			OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1097 			OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1098 	attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1099 		OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1100 		OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1101 		OCRDMA_WQE_STRIDE;
1102 	attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1103 		OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1104 		OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1105 		OCRDMA_WQE_STRIDE;
1106 	attr->max_inline_data =
1107 	    attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1108 			      sizeof(struct ocrdma_sge));
1109 	if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1110 		attr->ird = 1;
1111 		attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1112 		attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1113 	}
1114 	dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1115 		 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1116 	dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1117 		OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1118 }
1119 
1120 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1121 				   struct ocrdma_fw_conf_rsp *conf)
1122 {
1123 	u32 fn_mode;
1124 
1125 	fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1126 	if (fn_mode != OCRDMA_FN_MODE_RDMA)
1127 		return -EINVAL;
1128 	dev->base_eqid = conf->base_eqid;
1129 	dev->max_eq = conf->max_eq;
1130 	return 0;
1131 }
1132 
1133 /* can be issued only during init time. */
1134 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1135 {
1136 	int status = -ENOMEM;
1137 	struct ocrdma_mqe *cmd;
1138 	struct ocrdma_fw_ver_rsp *rsp;
1139 
1140 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1141 	if (!cmd)
1142 		return -ENOMEM;
1143 	ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1144 			OCRDMA_CMD_GET_FW_VER,
1145 			OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1146 
1147 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1148 	if (status)
1149 		goto mbx_err;
1150 	rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1151 	memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1152 	memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1153 	       sizeof(rsp->running_ver));
1154 	ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1155 mbx_err:
1156 	kfree(cmd);
1157 	return status;
1158 }
1159 
1160 /* can be issued only during init time. */
1161 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1162 {
1163 	int status = -ENOMEM;
1164 	struct ocrdma_mqe *cmd;
1165 	struct ocrdma_fw_conf_rsp *rsp;
1166 
1167 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1168 	if (!cmd)
1169 		return -ENOMEM;
1170 	ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1171 			OCRDMA_CMD_GET_FW_CONFIG,
1172 			OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1173 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1174 	if (status)
1175 		goto mbx_err;
1176 	rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1177 	status = ocrdma_check_fw_config(dev, rsp);
1178 mbx_err:
1179 	kfree(cmd);
1180 	return status;
1181 }
1182 
1183 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1184 {
1185 	struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1186 	struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1187 	struct ocrdma_rdma_stats_resp *old_stats;
1188 	int status;
1189 
1190 	old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1191 	if (old_stats == NULL)
1192 		return -ENOMEM;
1193 
1194 	memset(mqe, 0, sizeof(*mqe));
1195 	mqe->hdr.pyld_len = dev->stats_mem.size;
1196 	mqe->hdr.spcl_sge_cnt_emb |=
1197 			(1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1198 				OCRDMA_MQE_HDR_SGE_CNT_MASK;
1199 	mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1200 	mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1201 	mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1202 
1203 	/* Cache the old stats */
1204 	memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1205 	memset(req, 0, dev->stats_mem.size);
1206 
1207 	ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1208 			OCRDMA_CMD_GET_RDMA_STATS,
1209 			OCRDMA_SUBSYS_ROCE,
1210 			dev->stats_mem.size);
1211 	if (reset)
1212 		req->reset_stats = reset;
1213 
1214 	status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1215 	if (status)
1216 		/* Copy from cache, if mbox fails */
1217 		memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1218 	else
1219 		ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1220 
1221 	kfree(old_stats);
1222 	return status;
1223 }
1224 
1225 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1226 {
1227 	int status = -ENOMEM;
1228 	struct ocrdma_dma_mem dma;
1229 	struct ocrdma_mqe *mqe;
1230 	struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1231 	struct mgmt_hba_attribs *hba_attribs;
1232 
1233 	mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1234 	if (!mqe)
1235 		return status;
1236 
1237 	dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1238 	dma.va	 = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1239 					dma.size, &dma.pa, GFP_KERNEL);
1240 	if (!dma.va)
1241 		goto free_mqe;
1242 
1243 	mqe->hdr.pyld_len = dma.size;
1244 	mqe->hdr.spcl_sge_cnt_emb |=
1245 			(1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1246 			OCRDMA_MQE_HDR_SGE_CNT_MASK;
1247 	mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1248 	mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1249 	mqe->u.nonemb_req.sge[0].len = dma.size;
1250 
1251 	memset(dma.va, 0, dma.size);
1252 	ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1253 			OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1254 			OCRDMA_SUBSYS_COMMON,
1255 			dma.size);
1256 
1257 	status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1258 	if (!status) {
1259 		ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1260 		hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1261 
1262 		dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1263 					OCRDMA_HBA_ATTRB_PTNUM_MASK)
1264 					>> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1265 		strncpy(dev->model_number,
1266 			hba_attribs->controller_model_number, 31);
1267 	}
1268 	dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1269 free_mqe:
1270 	kfree(mqe);
1271 	return status;
1272 }
1273 
1274 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1275 {
1276 	int status = -ENOMEM;
1277 	struct ocrdma_mbx_query_config *rsp;
1278 	struct ocrdma_mqe *cmd;
1279 
1280 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1281 	if (!cmd)
1282 		return status;
1283 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1284 	if (status)
1285 		goto mbx_err;
1286 	rsp = (struct ocrdma_mbx_query_config *)cmd;
1287 	ocrdma_get_attr(dev, &dev->attr, rsp);
1288 mbx_err:
1289 	kfree(cmd);
1290 	return status;
1291 }
1292 
1293 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1294 {
1295 	int status = -ENOMEM;
1296 	struct ocrdma_get_link_speed_rsp *rsp;
1297 	struct ocrdma_mqe *cmd;
1298 
1299 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1300 				  sizeof(*cmd));
1301 	if (!cmd)
1302 		return status;
1303 	ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1304 			OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1305 			OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1306 
1307 	((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1308 
1309 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1310 	if (status)
1311 		goto mbx_err;
1312 
1313 	rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1314 	*lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1315 			>> OCRDMA_PHY_PS_SHIFT;
1316 
1317 mbx_err:
1318 	kfree(cmd);
1319 	return status;
1320 }
1321 
1322 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1323 {
1324 	int status = -ENOMEM;
1325 	struct ocrdma_mqe *cmd;
1326 	struct ocrdma_get_phy_info_rsp *rsp;
1327 
1328 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1329 	if (!cmd)
1330 		return status;
1331 
1332 	ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1333 			OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1334 			sizeof(*cmd));
1335 
1336 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1337 	if (status)
1338 		goto mbx_err;
1339 
1340 	rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1341 	dev->phy.phy_type =
1342 			(rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1343 	dev->phy.interface_type =
1344 			(rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1345 				>> OCRDMA_IF_TYPE_SHIFT;
1346 	dev->phy.auto_speeds_supported  =
1347 			(rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1348 	dev->phy.fixed_speeds_supported =
1349 			(rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1350 				>> OCRDMA_FSPEED_SUPP_SHIFT;
1351 mbx_err:
1352 	kfree(cmd);
1353 	return status;
1354 }
1355 
1356 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1357 {
1358 	int status = -ENOMEM;
1359 	struct ocrdma_alloc_pd *cmd;
1360 	struct ocrdma_alloc_pd_rsp *rsp;
1361 
1362 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1363 	if (!cmd)
1364 		return status;
1365 	if (pd->dpp_enabled)
1366 		cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1367 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1368 	if (status)
1369 		goto mbx_err;
1370 	rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1371 	pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1372 	if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1373 		pd->dpp_enabled = true;
1374 		pd->dpp_page = rsp->dpp_page_pdid >>
1375 				OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1376 	} else {
1377 		pd->dpp_enabled = false;
1378 		pd->num_dpp_qp = 0;
1379 	}
1380 mbx_err:
1381 	kfree(cmd);
1382 	return status;
1383 }
1384 
1385 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1386 {
1387 	int status = -ENOMEM;
1388 	struct ocrdma_dealloc_pd *cmd;
1389 
1390 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1391 	if (!cmd)
1392 		return status;
1393 	cmd->id = pd->id;
1394 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1395 	kfree(cmd);
1396 	return status;
1397 }
1398 
1399 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1400 			       int *num_pages, int *page_size)
1401 {
1402 	int i;
1403 	int mem_size;
1404 
1405 	*num_entries = roundup_pow_of_two(*num_entries);
1406 	mem_size = *num_entries * entry_size;
1407 	/* find the possible lowest possible multiplier */
1408 	for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1409 		if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1410 			break;
1411 	}
1412 	if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1413 		return -EINVAL;
1414 	mem_size = roundup(mem_size,
1415 		       ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1416 	*num_pages =
1417 	    mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1418 	*page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1419 	*num_entries = mem_size / entry_size;
1420 	return 0;
1421 }
1422 
1423 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1424 {
1425 	int i;
1426 	int status = 0;
1427 	int max_ah;
1428 	struct ocrdma_create_ah_tbl *cmd;
1429 	struct ocrdma_create_ah_tbl_rsp *rsp;
1430 	struct pci_dev *pdev = dev->nic_info.pdev;
1431 	dma_addr_t pa;
1432 	struct ocrdma_pbe *pbes;
1433 
1434 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1435 	if (!cmd)
1436 		return status;
1437 
1438 	max_ah = OCRDMA_MAX_AH;
1439 	dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1440 
1441 	/* number of PBEs in PBL */
1442 	cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1443 				OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1444 				OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1445 
1446 	/* page size */
1447 	for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1448 		if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1449 			break;
1450 	}
1451 	cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1452 				OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1453 
1454 	/* ah_entry size */
1455 	cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1456 				OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1457 				OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1458 
1459 	dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1460 						&dev->av_tbl.pbl.pa,
1461 						GFP_KERNEL);
1462 	if (dev->av_tbl.pbl.va == NULL)
1463 		goto mem_err;
1464 
1465 	dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1466 					    &pa, GFP_KERNEL);
1467 	if (dev->av_tbl.va == NULL)
1468 		goto mem_err_ah;
1469 	dev->av_tbl.pa = pa;
1470 	dev->av_tbl.num_ah = max_ah;
1471 	memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1472 
1473 	pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1474 	for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1475 		pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1476 		pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1477 		pa += PAGE_SIZE;
1478 	}
1479 	cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1480 	cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1481 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1482 	if (status)
1483 		goto mbx_err;
1484 	rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1485 	dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1486 	kfree(cmd);
1487 	return 0;
1488 
1489 mbx_err:
1490 	dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1491 			  dev->av_tbl.pa);
1492 	dev->av_tbl.va = NULL;
1493 mem_err_ah:
1494 	dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1495 			  dev->av_tbl.pbl.pa);
1496 	dev->av_tbl.pbl.va = NULL;
1497 	dev->av_tbl.size = 0;
1498 mem_err:
1499 	kfree(cmd);
1500 	return status;
1501 }
1502 
1503 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1504 {
1505 	struct ocrdma_delete_ah_tbl *cmd;
1506 	struct pci_dev *pdev = dev->nic_info.pdev;
1507 
1508 	if (dev->av_tbl.va == NULL)
1509 		return;
1510 
1511 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1512 	if (!cmd)
1513 		return;
1514 	cmd->ahid = dev->av_tbl.ahid;
1515 
1516 	ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1517 	dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1518 			  dev->av_tbl.pa);
1519 	dev->av_tbl.va = NULL;
1520 	dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1521 			  dev->av_tbl.pbl.pa);
1522 	kfree(cmd);
1523 }
1524 
1525 /* Multiple CQs uses the EQ. This routine returns least used
1526  * EQ to associate with CQ. This will distributes the interrupt
1527  * processing and CPU load to associated EQ, vector and so to that CPU.
1528  */
1529 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1530 {
1531 	int i, selected_eq = 0, cq_cnt = 0;
1532 	u16 eq_id;
1533 
1534 	mutex_lock(&dev->dev_lock);
1535 	cq_cnt = dev->eq_tbl[0].cq_cnt;
1536 	eq_id = dev->eq_tbl[0].q.id;
1537 	/* find the EQ which is has the least number of
1538 	 * CQs associated with it.
1539 	 */
1540 	for (i = 0; i < dev->eq_cnt; i++) {
1541 		if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1542 			cq_cnt = dev->eq_tbl[i].cq_cnt;
1543 			eq_id = dev->eq_tbl[i].q.id;
1544 			selected_eq = i;
1545 		}
1546 	}
1547 	dev->eq_tbl[selected_eq].cq_cnt += 1;
1548 	mutex_unlock(&dev->dev_lock);
1549 	return eq_id;
1550 }
1551 
1552 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1553 {
1554 	int i;
1555 
1556 	mutex_lock(&dev->dev_lock);
1557 	i = ocrdma_get_eq_table_index(dev, eq_id);
1558 	if (i == -EINVAL)
1559 		BUG();
1560 	dev->eq_tbl[i].cq_cnt -= 1;
1561 	mutex_unlock(&dev->dev_lock);
1562 }
1563 
1564 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1565 			 int entries, int dpp_cq, u16 pd_id)
1566 {
1567 	int status = -ENOMEM; int max_hw_cqe;
1568 	struct pci_dev *pdev = dev->nic_info.pdev;
1569 	struct ocrdma_create_cq *cmd;
1570 	struct ocrdma_create_cq_rsp *rsp;
1571 	u32 hw_pages, cqe_size, page_size, cqe_count;
1572 
1573 	if (entries > dev->attr.max_cqe) {
1574 		pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1575 		       __func__, dev->id, dev->attr.max_cqe, entries);
1576 		return -EINVAL;
1577 	}
1578 	if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1579 		return -EINVAL;
1580 
1581 	if (dpp_cq) {
1582 		cq->max_hw_cqe = 1;
1583 		max_hw_cqe = 1;
1584 		cqe_size = OCRDMA_DPP_CQE_SIZE;
1585 		hw_pages = 1;
1586 	} else {
1587 		cq->max_hw_cqe = dev->attr.max_cqe;
1588 		max_hw_cqe = dev->attr.max_cqe;
1589 		cqe_size = sizeof(struct ocrdma_cqe);
1590 		hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1591 	}
1592 
1593 	cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1594 
1595 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1596 	if (!cmd)
1597 		return -ENOMEM;
1598 	ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1599 			OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1600 	cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1601 	if (!cq->va) {
1602 		status = -ENOMEM;
1603 		goto mem_err;
1604 	}
1605 	memset(cq->va, 0, cq->len);
1606 	page_size = cq->len / hw_pages;
1607 	cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1608 					OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1609 	cmd->cmd.pgsz_pgcnt |= hw_pages;
1610 	cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1611 
1612 	cq->eqn = ocrdma_bind_eq(dev);
1613 	cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1614 	cqe_count = cq->len / cqe_size;
1615 	cq->cqe_cnt = cqe_count;
1616 	if (cqe_count > 1024) {
1617 		/* Set cnt to 3 to indicate more than 1024 cq entries */
1618 		cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1619 	} else {
1620 		u8 count = 0;
1621 		switch (cqe_count) {
1622 		case 256:
1623 			count = 0;
1624 			break;
1625 		case 512:
1626 			count = 1;
1627 			break;
1628 		case 1024:
1629 			count = 2;
1630 			break;
1631 		default:
1632 			goto mbx_err;
1633 		}
1634 		cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1635 	}
1636 	/* shared eq between all the consumer cqs. */
1637 	cmd->cmd.eqn = cq->eqn;
1638 	if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1639 		if (dpp_cq)
1640 			cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1641 				OCRDMA_CREATE_CQ_TYPE_SHIFT;
1642 		cq->phase_change = false;
1643 		cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1644 	} else {
1645 		cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1646 		cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1647 		cq->phase_change = true;
1648 	}
1649 
1650 	/* pd_id valid only for v3 */
1651 	cmd->cmd.pdid_cqecnt |= (pd_id <<
1652 		OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1653 	ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1654 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1655 	if (status)
1656 		goto mbx_err;
1657 
1658 	rsp = (struct ocrdma_create_cq_rsp *)cmd;
1659 	cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1660 	kfree(cmd);
1661 	return 0;
1662 mbx_err:
1663 	ocrdma_unbind_eq(dev, cq->eqn);
1664 	dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1665 mem_err:
1666 	kfree(cmd);
1667 	return status;
1668 }
1669 
1670 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1671 {
1672 	int status = -ENOMEM;
1673 	struct ocrdma_destroy_cq *cmd;
1674 
1675 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1676 	if (!cmd)
1677 		return status;
1678 	ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1679 			OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1680 
1681 	cmd->bypass_flush_qid |=
1682 	    (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1683 	    OCRDMA_DESTROY_CQ_QID_MASK;
1684 
1685 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1686 	ocrdma_unbind_eq(dev, cq->eqn);
1687 	dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1688 	kfree(cmd);
1689 	return status;
1690 }
1691 
1692 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1693 			  u32 pdid, int addr_check)
1694 {
1695 	int status = -ENOMEM;
1696 	struct ocrdma_alloc_lkey *cmd;
1697 	struct ocrdma_alloc_lkey_rsp *rsp;
1698 
1699 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1700 	if (!cmd)
1701 		return status;
1702 	cmd->pdid = pdid;
1703 	cmd->pbl_sz_flags |= addr_check;
1704 	cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1705 	cmd->pbl_sz_flags |=
1706 	    (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1707 	cmd->pbl_sz_flags |=
1708 	    (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1709 	cmd->pbl_sz_flags |=
1710 	    (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1711 	cmd->pbl_sz_flags |=
1712 	    (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1713 	cmd->pbl_sz_flags |=
1714 	    (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1715 
1716 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1717 	if (status)
1718 		goto mbx_err;
1719 	rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1720 	hwmr->lkey = rsp->lrkey;
1721 mbx_err:
1722 	kfree(cmd);
1723 	return status;
1724 }
1725 
1726 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1727 {
1728 	int status = -ENOMEM;
1729 	struct ocrdma_dealloc_lkey *cmd;
1730 
1731 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1732 	if (!cmd)
1733 		return -ENOMEM;
1734 	cmd->lkey = lkey;
1735 	cmd->rsvd_frmr = fr_mr ? 1 : 0;
1736 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1737 	if (status)
1738 		goto mbx_err;
1739 mbx_err:
1740 	kfree(cmd);
1741 	return status;
1742 }
1743 
1744 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1745 			     u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1746 {
1747 	int status = -ENOMEM;
1748 	int i;
1749 	struct ocrdma_reg_nsmr *cmd;
1750 	struct ocrdma_reg_nsmr_rsp *rsp;
1751 
1752 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1753 	if (!cmd)
1754 		return -ENOMEM;
1755 	cmd->num_pbl_pdid =
1756 	    pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1757 	cmd->fr_mr = hwmr->fr_mr;
1758 
1759 	cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1760 				    OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1761 	cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1762 				    OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1763 	cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1764 				    OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1765 	cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1766 				    OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1767 	cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1768 				    OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1769 	cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1770 
1771 	cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1772 	cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1773 					OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1774 	cmd->totlen_low = hwmr->len;
1775 	cmd->totlen_high = upper_32_bits(hwmr->len);
1776 	cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1777 	cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1778 	cmd->va_loaddr = (u32) hwmr->va;
1779 	cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1780 
1781 	for (i = 0; i < pbl_cnt; i++) {
1782 		cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1783 		cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1784 	}
1785 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1786 	if (status)
1787 		goto mbx_err;
1788 	rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1789 	hwmr->lkey = rsp->lrkey;
1790 mbx_err:
1791 	kfree(cmd);
1792 	return status;
1793 }
1794 
1795 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1796 				  struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1797 				  u32 pbl_offset, u32 last)
1798 {
1799 	int status = -ENOMEM;
1800 	int i;
1801 	struct ocrdma_reg_nsmr_cont *cmd;
1802 
1803 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1804 	if (!cmd)
1805 		return -ENOMEM;
1806 	cmd->lrkey = hwmr->lkey;
1807 	cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1808 	    (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1809 	cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1810 
1811 	for (i = 0; i < pbl_cnt; i++) {
1812 		cmd->pbl[i].lo =
1813 		    (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1814 		cmd->pbl[i].hi =
1815 		    upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1816 	}
1817 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1818 	if (status)
1819 		goto mbx_err;
1820 mbx_err:
1821 	kfree(cmd);
1822 	return status;
1823 }
1824 
1825 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1826 		  struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1827 {
1828 	int status;
1829 	u32 last = 0;
1830 	u32 cur_pbl_cnt, pbl_offset;
1831 	u32 pending_pbl_cnt = hwmr->num_pbls;
1832 
1833 	pbl_offset = 0;
1834 	cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1835 	if (cur_pbl_cnt == pending_pbl_cnt)
1836 		last = 1;
1837 
1838 	status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1839 				   cur_pbl_cnt, hwmr->pbe_size, last);
1840 	if (status) {
1841 		pr_err("%s() status=%d\n", __func__, status);
1842 		return status;
1843 	}
1844 	/* if there is no more pbls to register then exit. */
1845 	if (last)
1846 		return 0;
1847 
1848 	while (!last) {
1849 		pbl_offset += cur_pbl_cnt;
1850 		pending_pbl_cnt -= cur_pbl_cnt;
1851 		cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1852 		/* if we reach the end of the pbls, then need to set the last
1853 		 * bit, indicating no more pbls to register for this memory key.
1854 		 */
1855 		if (cur_pbl_cnt == pending_pbl_cnt)
1856 			last = 1;
1857 
1858 		status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1859 						pbl_offset, last);
1860 		if (status)
1861 			break;
1862 	}
1863 	if (status)
1864 		pr_err("%s() err. status=%d\n", __func__, status);
1865 
1866 	return status;
1867 }
1868 
1869 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1870 {
1871 	struct ocrdma_qp *tmp;
1872 	bool found = false;
1873 	list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1874 		if (qp == tmp) {
1875 			found = true;
1876 			break;
1877 		}
1878 	}
1879 	return found;
1880 }
1881 
1882 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1883 {
1884 	struct ocrdma_qp *tmp;
1885 	bool found = false;
1886 	list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1887 		if (qp == tmp) {
1888 			found = true;
1889 			break;
1890 		}
1891 	}
1892 	return found;
1893 }
1894 
1895 void ocrdma_flush_qp(struct ocrdma_qp *qp)
1896 {
1897 	bool found;
1898 	unsigned long flags;
1899 
1900 	spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1901 	found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1902 	if (!found)
1903 		list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1904 	if (!qp->srq) {
1905 		found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1906 		if (!found)
1907 			list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1908 	}
1909 	spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1910 }
1911 
1912 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1913 {
1914 	qp->sq.head = 0;
1915 	qp->sq.tail = 0;
1916 	qp->rq.head = 0;
1917 	qp->rq.tail = 0;
1918 }
1919 
1920 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1921 			   enum ib_qp_state *old_ib_state)
1922 {
1923 	unsigned long flags;
1924 	int status = 0;
1925 	enum ocrdma_qp_state new_state;
1926 	new_state = get_ocrdma_qp_state(new_ib_state);
1927 
1928 	/* sync with wqe and rqe posting */
1929 	spin_lock_irqsave(&qp->q_lock, flags);
1930 
1931 	if (old_ib_state)
1932 		*old_ib_state = get_ibqp_state(qp->state);
1933 	if (new_state == qp->state) {
1934 		spin_unlock_irqrestore(&qp->q_lock, flags);
1935 		return 1;
1936 	}
1937 
1938 
1939 	if (new_state == OCRDMA_QPS_INIT) {
1940 		ocrdma_init_hwq_ptr(qp);
1941 		ocrdma_del_flush_qp(qp);
1942 	} else if (new_state == OCRDMA_QPS_ERR) {
1943 		ocrdma_flush_qp(qp);
1944 	}
1945 
1946 	qp->state = new_state;
1947 
1948 	spin_unlock_irqrestore(&qp->q_lock, flags);
1949 	return status;
1950 }
1951 
1952 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1953 {
1954 	u32 flags = 0;
1955 	if (qp->cap_flags & OCRDMA_QP_INB_RD)
1956 		flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1957 	if (qp->cap_flags & OCRDMA_QP_INB_WR)
1958 		flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1959 	if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1960 		flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1961 	if (qp->cap_flags & OCRDMA_QP_LKEY0)
1962 		flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1963 	if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1964 		flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1965 	return flags;
1966 }
1967 
1968 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1969 					struct ib_qp_init_attr *attrs,
1970 					struct ocrdma_qp *qp)
1971 {
1972 	int status;
1973 	u32 len, hw_pages, hw_page_size;
1974 	dma_addr_t pa;
1975 	struct ocrdma_dev *dev = qp->dev;
1976 	struct pci_dev *pdev = dev->nic_info.pdev;
1977 	u32 max_wqe_allocated;
1978 	u32 max_sges = attrs->cap.max_send_sge;
1979 
1980 	/* QP1 may exceed 127 */
1981 	max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
1982 				dev->attr.max_wqe);
1983 
1984 	status = ocrdma_build_q_conf(&max_wqe_allocated,
1985 		dev->attr.wqe_size, &hw_pages, &hw_page_size);
1986 	if (status) {
1987 		pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1988 		       max_wqe_allocated);
1989 		return -EINVAL;
1990 	}
1991 	qp->sq.max_cnt = max_wqe_allocated;
1992 	len = (hw_pages * hw_page_size);
1993 
1994 	qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1995 	if (!qp->sq.va)
1996 		return -EINVAL;
1997 	memset(qp->sq.va, 0, len);
1998 	qp->sq.len = len;
1999 	qp->sq.pa = pa;
2000 	qp->sq.entry_size = dev->attr.wqe_size;
2001 	ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2002 
2003 	cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2004 				<< OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2005 	cmd->num_wq_rq_pages |= (hw_pages <<
2006 				 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2007 	    OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2008 	cmd->max_sge_send_write |= (max_sges <<
2009 				    OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2010 	    OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2011 	cmd->max_sge_send_write |= (max_sges <<
2012 				    OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2013 					OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2014 	cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2015 			     OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2016 				OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2017 	cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2018 			      OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2019 				OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2020 	return 0;
2021 }
2022 
2023 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2024 					struct ib_qp_init_attr *attrs,
2025 					struct ocrdma_qp *qp)
2026 {
2027 	int status;
2028 	u32 len, hw_pages, hw_page_size;
2029 	dma_addr_t pa = 0;
2030 	struct ocrdma_dev *dev = qp->dev;
2031 	struct pci_dev *pdev = dev->nic_info.pdev;
2032 	u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2033 
2034 	status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2035 				     &hw_pages, &hw_page_size);
2036 	if (status) {
2037 		pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2038 		       attrs->cap.max_recv_wr + 1);
2039 		return status;
2040 	}
2041 	qp->rq.max_cnt = max_rqe_allocated;
2042 	len = (hw_pages * hw_page_size);
2043 
2044 	qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2045 	if (!qp->rq.va)
2046 		return -ENOMEM;
2047 	memset(qp->rq.va, 0, len);
2048 	qp->rq.pa = pa;
2049 	qp->rq.len = len;
2050 	qp->rq.entry_size = dev->attr.rqe_size;
2051 
2052 	ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2053 	cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2054 		OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2055 	cmd->num_wq_rq_pages |=
2056 	    (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2057 	    OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2058 	cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2059 				OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2060 				OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2061 	cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2062 				OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2063 				OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2064 	cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2065 			OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2066 			OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2067 	return 0;
2068 }
2069 
2070 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2071 					 struct ocrdma_pd *pd,
2072 					 struct ocrdma_qp *qp,
2073 					 u8 enable_dpp_cq, u16 dpp_cq_id)
2074 {
2075 	pd->num_dpp_qp--;
2076 	qp->dpp_enabled = true;
2077 	cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2078 	if (!enable_dpp_cq)
2079 		return;
2080 	cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2081 	cmd->dpp_credits_cqid = dpp_cq_id;
2082 	cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2083 					OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2084 }
2085 
2086 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2087 					struct ocrdma_qp *qp)
2088 {
2089 	struct ocrdma_dev *dev = qp->dev;
2090 	struct pci_dev *pdev = dev->nic_info.pdev;
2091 	dma_addr_t pa = 0;
2092 	int ird_page_size = dev->attr.ird_page_size;
2093 	int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2094 	struct ocrdma_hdr_wqe *rqe;
2095 	int i  = 0;
2096 
2097 	if (dev->attr.ird == 0)
2098 		return 0;
2099 
2100 	qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2101 					&pa, GFP_KERNEL);
2102 	if (!qp->ird_q_va)
2103 		return -ENOMEM;
2104 	memset(qp->ird_q_va, 0, ird_q_len);
2105 	ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2106 			     pa, ird_page_size);
2107 	for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2108 		rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2109 			(i * dev->attr.rqe_size));
2110 		rqe->cw = 0;
2111 		rqe->cw |= 2;
2112 		rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2113 		rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2114 		rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2115 	}
2116 	return 0;
2117 }
2118 
2119 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2120 				     struct ocrdma_qp *qp,
2121 				     struct ib_qp_init_attr *attrs,
2122 				     u16 *dpp_offset, u16 *dpp_credit_lmt)
2123 {
2124 	u32 max_wqe_allocated, max_rqe_allocated;
2125 	qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2126 	qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2127 	qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2128 	qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2129 	qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2130 	qp->dpp_enabled = false;
2131 	if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2132 		qp->dpp_enabled = true;
2133 		*dpp_credit_lmt = (rsp->dpp_response &
2134 				OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2135 				OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2136 		*dpp_offset = (rsp->dpp_response &
2137 				OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2138 				OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2139 	}
2140 	max_wqe_allocated =
2141 		rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2142 	max_wqe_allocated = 1 << max_wqe_allocated;
2143 	max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2144 
2145 	qp->sq.max_cnt = max_wqe_allocated;
2146 	qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2147 
2148 	if (!attrs->srq) {
2149 		qp->rq.max_cnt = max_rqe_allocated;
2150 		qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2151 	}
2152 }
2153 
2154 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2155 			 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2156 			 u16 *dpp_credit_lmt)
2157 {
2158 	int status = -ENOMEM;
2159 	u32 flags = 0;
2160 	struct ocrdma_dev *dev = qp->dev;
2161 	struct ocrdma_pd *pd = qp->pd;
2162 	struct pci_dev *pdev = dev->nic_info.pdev;
2163 	struct ocrdma_cq *cq;
2164 	struct ocrdma_create_qp_req *cmd;
2165 	struct ocrdma_create_qp_rsp *rsp;
2166 	int qptype;
2167 
2168 	switch (attrs->qp_type) {
2169 	case IB_QPT_GSI:
2170 		qptype = OCRDMA_QPT_GSI;
2171 		break;
2172 	case IB_QPT_RC:
2173 		qptype = OCRDMA_QPT_RC;
2174 		break;
2175 	case IB_QPT_UD:
2176 		qptype = OCRDMA_QPT_UD;
2177 		break;
2178 	default:
2179 		return -EINVAL;
2180 	}
2181 
2182 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2183 	if (!cmd)
2184 		return status;
2185 	cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2186 						OCRDMA_CREATE_QP_REQ_QPT_MASK;
2187 	status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2188 	if (status)
2189 		goto sq_err;
2190 
2191 	if (attrs->srq) {
2192 		struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2193 		cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2194 		cmd->rq_addr[0].lo = srq->id;
2195 		qp->srq = srq;
2196 	} else {
2197 		status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2198 		if (status)
2199 			goto rq_err;
2200 	}
2201 
2202 	status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2203 	if (status)
2204 		goto mbx_err;
2205 
2206 	cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2207 				OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2208 
2209 	flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2210 
2211 	cmd->max_sge_recv_flags |= flags;
2212 	cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2213 			     OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2214 				OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2215 	cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2216 			     OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2217 				OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2218 	cq = get_ocrdma_cq(attrs->send_cq);
2219 	cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2220 				OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2221 	qp->sq_cq = cq;
2222 	cq = get_ocrdma_cq(attrs->recv_cq);
2223 	cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2224 				OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2225 	qp->rq_cq = cq;
2226 
2227 	if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2228 	    (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2229 		ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2230 					     dpp_cq_id);
2231 	}
2232 
2233 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2234 	if (status)
2235 		goto mbx_err;
2236 	rsp = (struct ocrdma_create_qp_rsp *)cmd;
2237 	ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2238 	qp->state = OCRDMA_QPS_RST;
2239 	kfree(cmd);
2240 	return 0;
2241 mbx_err:
2242 	if (qp->rq.va)
2243 		dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2244 rq_err:
2245 	pr_err("%s(%d) rq_err\n", __func__, dev->id);
2246 	dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2247 sq_err:
2248 	pr_err("%s(%d) sq_err\n", __func__, dev->id);
2249 	kfree(cmd);
2250 	return status;
2251 }
2252 
2253 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2254 			struct ocrdma_qp_params *param)
2255 {
2256 	int status = -ENOMEM;
2257 	struct ocrdma_query_qp *cmd;
2258 	struct ocrdma_query_qp_rsp *rsp;
2259 
2260 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2261 	if (!cmd)
2262 		return status;
2263 	cmd->qp_id = qp->id;
2264 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2265 	if (status)
2266 		goto mbx_err;
2267 	rsp = (struct ocrdma_query_qp_rsp *)cmd;
2268 	memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2269 mbx_err:
2270 	kfree(cmd);
2271 	return status;
2272 }
2273 
2274 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2275 				struct ocrdma_modify_qp *cmd,
2276 				struct ib_qp_attr *attrs,
2277 				int attr_mask)
2278 {
2279 	int status;
2280 	struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2281 	union ib_gid sgid, zgid;
2282 	u32 vlan_id;
2283 	u8 mac_addr[6];
2284 
2285 	if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2286 		return -EINVAL;
2287 	if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
2288 		ocrdma_init_service_level(qp->dev);
2289 	cmd->params.tclass_sq_psn |=
2290 	    (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2291 	cmd->params.rnt_rc_sl_fl |=
2292 	    (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2293 	cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2294 	cmd->params.hop_lmt_rq_psn |=
2295 	    (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2296 	cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2297 	memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2298 	       sizeof(cmd->params.dgid));
2299 	status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2300 			ah_attr->grh.sgid_index, &sgid);
2301 	if (status)
2302 		return status;
2303 
2304 	memset(&zgid, 0, sizeof(zgid));
2305 	if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2306 		return -EINVAL;
2307 
2308 	qp->sgid_idx = ah_attr->grh.sgid_index;
2309 	memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2310 	ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2311 	cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2312 				(mac_addr[2] << 16) | (mac_addr[3] << 24);
2313 	/* convert them to LE format. */
2314 	ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2315 	ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2316 	cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2317 	if (attr_mask & IB_QP_VID) {
2318 		vlan_id = attrs->vlan_id;
2319 		cmd->params.vlan_dmac_b4_to_b5 |=
2320 		    vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2321 		cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2322 		cmd->params.rnt_rc_sl_fl |=
2323 			(qp->dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2324 	}
2325 	return 0;
2326 }
2327 
2328 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2329 				struct ocrdma_modify_qp *cmd,
2330 				struct ib_qp_attr *attrs, int attr_mask)
2331 {
2332 	int status = 0;
2333 
2334 	if (attr_mask & IB_QP_PKEY_INDEX) {
2335 		cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2336 					    OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2337 		cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2338 	}
2339 	if (attr_mask & IB_QP_QKEY) {
2340 		qp->qkey = attrs->qkey;
2341 		cmd->params.qkey = attrs->qkey;
2342 		cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2343 	}
2344 	if (attr_mask & IB_QP_AV) {
2345 		status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2346 		if (status)
2347 			return status;
2348 	} else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2349 		/* set the default mac address for UD, GSI QPs */
2350 		cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2351 			(qp->dev->nic_info.mac_addr[1] << 8) |
2352 			(qp->dev->nic_info.mac_addr[2] << 16) |
2353 			(qp->dev->nic_info.mac_addr[3] << 24);
2354 		cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2355 					(qp->dev->nic_info.mac_addr[5] << 8);
2356 	}
2357 	if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2358 	    attrs->en_sqd_async_notify) {
2359 		cmd->params.max_sge_recv_flags |=
2360 			OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2361 		cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2362 	}
2363 	if (attr_mask & IB_QP_DEST_QPN) {
2364 		cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2365 				OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2366 		cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2367 	}
2368 	if (attr_mask & IB_QP_PATH_MTU) {
2369 		if (attrs->path_mtu < IB_MTU_256 ||
2370 		    attrs->path_mtu > IB_MTU_4096) {
2371 			status = -EINVAL;
2372 			goto pmtu_err;
2373 		}
2374 		cmd->params.path_mtu_pkey_indx |=
2375 		    (ib_mtu_enum_to_int(attrs->path_mtu) <<
2376 		     OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2377 		    OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2378 		cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2379 	}
2380 	if (attr_mask & IB_QP_TIMEOUT) {
2381 		cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2382 		    OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2383 		cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2384 	}
2385 	if (attr_mask & IB_QP_RETRY_CNT) {
2386 		cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2387 				      OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2388 		    OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2389 		cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2390 	}
2391 	if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2392 		cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2393 				      OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2394 		    OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2395 		cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2396 	}
2397 	if (attr_mask & IB_QP_RNR_RETRY) {
2398 		cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2399 			OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2400 			& OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2401 		cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2402 	}
2403 	if (attr_mask & IB_QP_SQ_PSN) {
2404 		cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2405 		cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2406 	}
2407 	if (attr_mask & IB_QP_RQ_PSN) {
2408 		cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2409 		cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2410 	}
2411 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2412 		if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2413 			status = -EINVAL;
2414 			goto pmtu_err;
2415 		}
2416 		qp->max_ord = attrs->max_rd_atomic;
2417 		cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2418 	}
2419 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2420 		if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2421 			status = -EINVAL;
2422 			goto pmtu_err;
2423 		}
2424 		qp->max_ird = attrs->max_dest_rd_atomic;
2425 		cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2426 	}
2427 	cmd->params.max_ord_ird = (qp->max_ord <<
2428 				OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2429 				(qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2430 pmtu_err:
2431 	return status;
2432 }
2433 
2434 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2435 			 struct ib_qp_attr *attrs, int attr_mask)
2436 {
2437 	int status = -ENOMEM;
2438 	struct ocrdma_modify_qp *cmd;
2439 
2440 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2441 	if (!cmd)
2442 		return status;
2443 
2444 	cmd->params.id = qp->id;
2445 	cmd->flags = 0;
2446 	if (attr_mask & IB_QP_STATE) {
2447 		cmd->params.max_sge_recv_flags |=
2448 		    (get_ocrdma_qp_state(attrs->qp_state) <<
2449 		     OCRDMA_QP_PARAMS_STATE_SHIFT) &
2450 		    OCRDMA_QP_PARAMS_STATE_MASK;
2451 		cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2452 	} else {
2453 		cmd->params.max_sge_recv_flags |=
2454 		    (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2455 		    OCRDMA_QP_PARAMS_STATE_MASK;
2456 	}
2457 
2458 	status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2459 	if (status)
2460 		goto mbx_err;
2461 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2462 	if (status)
2463 		goto mbx_err;
2464 
2465 mbx_err:
2466 	kfree(cmd);
2467 	return status;
2468 }
2469 
2470 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2471 {
2472 	int status = -ENOMEM;
2473 	struct ocrdma_destroy_qp *cmd;
2474 	struct pci_dev *pdev = dev->nic_info.pdev;
2475 
2476 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2477 	if (!cmd)
2478 		return status;
2479 	cmd->qp_id = qp->id;
2480 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2481 	if (status)
2482 		goto mbx_err;
2483 
2484 mbx_err:
2485 	kfree(cmd);
2486 	if (qp->sq.va)
2487 		dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2488 	if (!qp->srq && qp->rq.va)
2489 		dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2490 	if (qp->dpp_enabled)
2491 		qp->pd->num_dpp_qp++;
2492 	return status;
2493 }
2494 
2495 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2496 			  struct ib_srq_init_attr *srq_attr,
2497 			  struct ocrdma_pd *pd)
2498 {
2499 	int status = -ENOMEM;
2500 	int hw_pages, hw_page_size;
2501 	int len;
2502 	struct ocrdma_create_srq_rsp *rsp;
2503 	struct ocrdma_create_srq *cmd;
2504 	dma_addr_t pa;
2505 	struct pci_dev *pdev = dev->nic_info.pdev;
2506 	u32 max_rqe_allocated;
2507 
2508 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2509 	if (!cmd)
2510 		return status;
2511 
2512 	cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2513 	max_rqe_allocated = srq_attr->attr.max_wr + 1;
2514 	status = ocrdma_build_q_conf(&max_rqe_allocated,
2515 				dev->attr.rqe_size,
2516 				&hw_pages, &hw_page_size);
2517 	if (status) {
2518 		pr_err("%s() req. max_wr=0x%x\n", __func__,
2519 		       srq_attr->attr.max_wr);
2520 		status = -EINVAL;
2521 		goto ret;
2522 	}
2523 	len = hw_pages * hw_page_size;
2524 	srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2525 	if (!srq->rq.va) {
2526 		status = -ENOMEM;
2527 		goto ret;
2528 	}
2529 	ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2530 
2531 	srq->rq.entry_size = dev->attr.rqe_size;
2532 	srq->rq.pa = pa;
2533 	srq->rq.len = len;
2534 	srq->rq.max_cnt = max_rqe_allocated;
2535 
2536 	cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2537 	cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2538 				OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2539 
2540 	cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2541 		<< OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2542 	cmd->pages_rqe_sz |= (dev->attr.rqe_size
2543 		<< OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2544 		& OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2545 	cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2546 
2547 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2548 	if (status)
2549 		goto mbx_err;
2550 	rsp = (struct ocrdma_create_srq_rsp *)cmd;
2551 	srq->id = rsp->id;
2552 	srq->rq.dbid = rsp->id;
2553 	max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2554 		OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2555 		OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2556 	max_rqe_allocated = (1 << max_rqe_allocated);
2557 	srq->rq.max_cnt = max_rqe_allocated;
2558 	srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2559 	srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2560 		OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2561 		OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2562 	goto ret;
2563 mbx_err:
2564 	dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2565 ret:
2566 	kfree(cmd);
2567 	return status;
2568 }
2569 
2570 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2571 {
2572 	int status = -ENOMEM;
2573 	struct ocrdma_modify_srq *cmd;
2574 	struct ocrdma_pd *pd = srq->pd;
2575 	struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2576 
2577 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2578 	if (!cmd)
2579 		return status;
2580 	cmd->id = srq->id;
2581 	cmd->limit_max_rqe |= srq_attr->srq_limit <<
2582 	    OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2583 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2584 	kfree(cmd);
2585 	return status;
2586 }
2587 
2588 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2589 {
2590 	int status = -ENOMEM;
2591 	struct ocrdma_query_srq *cmd;
2592 	struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2593 
2594 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2595 	if (!cmd)
2596 		return status;
2597 	cmd->id = srq->rq.dbid;
2598 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2599 	if (status == 0) {
2600 		struct ocrdma_query_srq_rsp *rsp =
2601 		    (struct ocrdma_query_srq_rsp *)cmd;
2602 		srq_attr->max_sge =
2603 		    rsp->srq_lmt_max_sge &
2604 		    OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2605 		srq_attr->max_wr =
2606 		    rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2607 		srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2608 		    OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2609 	}
2610 	kfree(cmd);
2611 	return status;
2612 }
2613 
2614 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2615 {
2616 	int status = -ENOMEM;
2617 	struct ocrdma_destroy_srq *cmd;
2618 	struct pci_dev *pdev = dev->nic_info.pdev;
2619 	cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2620 	if (!cmd)
2621 		return status;
2622 	cmd->id = srq->id;
2623 	status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2624 	if (srq->rq.va)
2625 		dma_free_coherent(&pdev->dev, srq->rq.len,
2626 				  srq->rq.va, srq->rq.pa);
2627 	kfree(cmd);
2628 	return status;
2629 }
2630 
2631 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2632 				      struct ocrdma_dcbx_cfg *dcbxcfg)
2633 {
2634 	int status = 0;
2635 	dma_addr_t pa;
2636 	struct ocrdma_mqe cmd;
2637 
2638 	struct ocrdma_get_dcbx_cfg_req *req = NULL;
2639 	struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2640 	struct pci_dev *pdev = dev->nic_info.pdev;
2641 	struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2642 
2643 	memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2644 	cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2645 					sizeof(struct ocrdma_get_dcbx_cfg_req));
2646 	req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2647 	if (!req) {
2648 		status = -ENOMEM;
2649 		goto mem_err;
2650 	}
2651 
2652 	cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2653 					OCRDMA_MQE_HDR_SGE_CNT_MASK;
2654 	mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2655 	mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2656 	mqe_sge->len = cmd.hdr.pyld_len;
2657 
2658 	memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2659 	ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2660 			OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2661 	req->param_type = ptype;
2662 
2663 	status = ocrdma_mbx_cmd(dev, &cmd);
2664 	if (status)
2665 		goto mbx_err;
2666 
2667 	rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2668 	ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2669 	memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2670 
2671 mbx_err:
2672 	dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2673 mem_err:
2674 	return status;
2675 }
2676 
2677 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX	0x08
2678 #define OCRDMA_DEFAULT_SERVICE_LEVEL	0x05
2679 
2680 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2681 				    struct ocrdma_dcbx_cfg *dcbxcfg,
2682 				    u8 *srvc_lvl)
2683 {
2684 	int status = -EINVAL, indx, slindx;
2685 	int ventry_cnt;
2686 	struct ocrdma_app_parameter *app_param;
2687 	u8 valid, proto_sel;
2688 	u8 app_prio, pfc_prio;
2689 	u16 proto;
2690 
2691 	if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2692 		pr_info("%s ocrdma%d DCBX is disabled\n",
2693 			dev_name(&dev->nic_info.pdev->dev), dev->id);
2694 		goto out;
2695 	}
2696 
2697 	if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2698 		pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2699 			dev_name(&dev->nic_info.pdev->dev), dev->id,
2700 			(ptype > 0 ? "operational" : "admin"),
2701 			(dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2702 			"enabled" : "disabled",
2703 			(dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2704 			"" : ", not sync'ed");
2705 		goto out;
2706 	} else {
2707 		pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2708 			dev_name(&dev->nic_info.pdev->dev), dev->id);
2709 	}
2710 
2711 	ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2712 				OCRDMA_DCBX_APP_ENTRY_SHIFT)
2713 				& OCRDMA_DCBX_STATE_MASK;
2714 
2715 	for (indx = 0; indx < ventry_cnt; indx++) {
2716 		app_param = &dcbxcfg->app_param[indx];
2717 		valid = (app_param->valid_proto_app >>
2718 				OCRDMA_APP_PARAM_VALID_SHIFT)
2719 				& OCRDMA_APP_PARAM_VALID_MASK;
2720 		proto_sel = (app_param->valid_proto_app
2721 				>>  OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2722 				& OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2723 		proto = app_param->valid_proto_app &
2724 				OCRDMA_APP_PARAM_APP_PROTO_MASK;
2725 
2726 		if (
2727 			valid && proto == OCRDMA_APP_PROTO_ROCE &&
2728 			proto_sel == OCRDMA_PROTO_SELECT_L2) {
2729 			for (slindx = 0; slindx <
2730 				OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2731 				app_prio = ocrdma_get_app_prio(
2732 						(u8 *)app_param->app_prio,
2733 						slindx);
2734 				pfc_prio = ocrdma_get_pfc_prio(
2735 						(u8 *)dcbxcfg->pfc_prio,
2736 						slindx);
2737 
2738 				if (app_prio && pfc_prio) {
2739 					*srvc_lvl = slindx;
2740 					status = 0;
2741 					goto out;
2742 				}
2743 			}
2744 			if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2745 				pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2746 					dev_name(&dev->nic_info.pdev->dev),
2747 					dev->id, proto);
2748 			}
2749 		}
2750 	}
2751 
2752 out:
2753 	return status;
2754 }
2755 
2756 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2757 {
2758 	int status = 0, indx;
2759 	struct ocrdma_dcbx_cfg dcbxcfg;
2760 	u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2761 	int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2762 
2763 	for (indx = 0; indx < 2; indx++) {
2764 		status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2765 		if (status) {
2766 			pr_err("%s(): status=%d\n", __func__, status);
2767 			ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2768 			continue;
2769 		}
2770 
2771 		status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2772 						  &dcbxcfg, &srvc_lvl);
2773 		if (status) {
2774 			ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2775 			continue;
2776 		}
2777 
2778 		break;
2779 	}
2780 
2781 	if (status)
2782 		pr_info("%s ocrdma%d service level default\n",
2783 			dev_name(&dev->nic_info.pdev->dev), dev->id);
2784 	else
2785 		pr_info("%s ocrdma%d service level %d\n",
2786 			dev_name(&dev->nic_info.pdev->dev), dev->id,
2787 			srvc_lvl);
2788 
2789 	dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2790 	dev->sl = srvc_lvl;
2791 }
2792 
2793 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2794 {
2795 	int i;
2796 	int status = -EINVAL;
2797 	struct ocrdma_av *av;
2798 	unsigned long flags;
2799 
2800 	av = dev->av_tbl.va;
2801 	spin_lock_irqsave(&dev->av_tbl.lock, flags);
2802 	for (i = 0; i < dev->av_tbl.num_ah; i++) {
2803 		if (av->valid == 0) {
2804 			av->valid = OCRDMA_AV_VALID;
2805 			ah->av = av;
2806 			ah->id = i;
2807 			status = 0;
2808 			break;
2809 		}
2810 		av++;
2811 	}
2812 	if (i == dev->av_tbl.num_ah)
2813 		status = -EAGAIN;
2814 	spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2815 	return status;
2816 }
2817 
2818 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2819 {
2820 	unsigned long flags;
2821 	spin_lock_irqsave(&dev->av_tbl.lock, flags);
2822 	ah->av->valid = 0;
2823 	spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2824 	return 0;
2825 }
2826 
2827 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2828 {
2829 	int num_eq, i, status = 0;
2830 	int irq;
2831 	unsigned long flags = 0;
2832 
2833 	num_eq = dev->nic_info.msix.num_vectors -
2834 			dev->nic_info.msix.start_vector;
2835 	if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2836 		num_eq = 1;
2837 		flags = IRQF_SHARED;
2838 	} else {
2839 		num_eq = min_t(u32, num_eq, num_online_cpus());
2840 	}
2841 
2842 	if (!num_eq)
2843 		return -EINVAL;
2844 
2845 	dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2846 	if (!dev->eq_tbl)
2847 		return -ENOMEM;
2848 
2849 	for (i = 0; i < num_eq; i++) {
2850 		status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2851 					OCRDMA_EQ_LEN);
2852 		if (status) {
2853 			status = -EINVAL;
2854 			break;
2855 		}
2856 		sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
2857 			dev->id, i);
2858 		irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
2859 		status = request_irq(irq, ocrdma_irq_handler, flags,
2860 				     dev->eq_tbl[i].irq_name,
2861 				     &dev->eq_tbl[i]);
2862 		if (status)
2863 			goto done;
2864 		dev->eq_cnt += 1;
2865 	}
2866 	/* one eq is sufficient for data path to work */
2867 	return 0;
2868 done:
2869 	ocrdma_destroy_eqs(dev);
2870 	return status;
2871 }
2872 
2873 int ocrdma_init_hw(struct ocrdma_dev *dev)
2874 {
2875 	int status;
2876 
2877 	/* create the eqs  */
2878 	status = ocrdma_create_eqs(dev);
2879 	if (status)
2880 		goto qpeq_err;
2881 	status = ocrdma_create_mq(dev);
2882 	if (status)
2883 		goto mq_err;
2884 	status = ocrdma_mbx_query_fw_config(dev);
2885 	if (status)
2886 		goto conf_err;
2887 	status = ocrdma_mbx_query_dev(dev);
2888 	if (status)
2889 		goto conf_err;
2890 	status = ocrdma_mbx_query_fw_ver(dev);
2891 	if (status)
2892 		goto conf_err;
2893 	status = ocrdma_mbx_create_ah_tbl(dev);
2894 	if (status)
2895 		goto conf_err;
2896 	status = ocrdma_mbx_get_phy_info(dev);
2897 	if (status)
2898 		goto info_attrb_err;
2899 	status = ocrdma_mbx_get_ctrl_attribs(dev);
2900 	if (status)
2901 		goto info_attrb_err;
2902 
2903 	return 0;
2904 
2905 info_attrb_err:
2906 	ocrdma_mbx_delete_ah_tbl(dev);
2907 conf_err:
2908 	ocrdma_destroy_mq(dev);
2909 mq_err:
2910 	ocrdma_destroy_eqs(dev);
2911 qpeq_err:
2912 	pr_err("%s() status=%d\n", __func__, status);
2913 	return status;
2914 }
2915 
2916 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2917 {
2918 	ocrdma_mbx_delete_ah_tbl(dev);
2919 
2920 	/* cleanup the eqs */
2921 	ocrdma_destroy_eqs(dev);
2922 
2923 	/* cleanup the control path */
2924 	ocrdma_destroy_mq(dev);
2925 }
2926