1 /* This file is part of the Emulex RoCE Device Driver for 2 * RoCE (RDMA over Converged Ethernet) adapters. 3 * Copyright (C) 2012-2015 Emulex. All rights reserved. 4 * EMULEX and SLI are trademarks of Emulex. 5 * www.emulex.com 6 * 7 * This software is available to you under a choice of one of two licenses. 8 * You may choose to be licensed under the terms of the GNU General Public 9 * License (GPL) Version 2, available from the file COPYING in the main 10 * directory of this source tree, or the BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 16 * - Redistributions of source code must retain the above copyright notice, 17 * this list of conditions and the following disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * Contact Information: 36 * linux-drivers@emulex.com 37 * 38 * Emulex 39 * 3333 Susan Street 40 * Costa Mesa, CA 92626 41 */ 42 43 #ifndef __OCRDMA_H__ 44 #define __OCRDMA_H__ 45 46 #include <linux/mutex.h> 47 #include <linux/list.h> 48 #include <linux/spinlock.h> 49 #include <linux/pci.h> 50 51 #include <rdma/ib_verbs.h> 52 #include <rdma/ib_user_verbs.h> 53 #include <rdma/ib_addr.h> 54 55 #include <be_roce.h> 56 #include "ocrdma_sli.h" 57 58 #define OCRDMA_ROCE_DRV_VERSION "10.6.0.0" 59 60 #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver" 61 #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA" 62 63 #define OC_NAME_SH OCRDMA_NODE_DESC "(Skyhawk)" 64 #define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)" 65 66 #define OC_SKH_DEVICE_PF 0x720 67 #define OC_SKH_DEVICE_VF 0x728 68 #define OCRDMA_MAX_AH 512 69 70 #define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 71 72 #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo) 73 #define EQ_INTR_PER_SEC_THRSH_HI 150000 74 #define EQ_INTR_PER_SEC_THRSH_LOW 100000 75 #define EQ_AIC_MAX_EQD 20 76 #define EQ_AIC_MIN_EQD 0 77 78 void ocrdma_eqd_set_task(struct work_struct *work); 79 80 struct ocrdma_dev_attr { 81 u8 fw_ver[32]; 82 u32 vendor_id; 83 u32 device_id; 84 u16 max_pd; 85 u16 max_dpp_pds; 86 u16 max_cq; 87 u16 max_cqe; 88 u16 max_qp; 89 u16 max_wqe; 90 u16 max_rqe; 91 u16 max_srq; 92 u32 max_inline_data; 93 int max_send_sge; 94 int max_recv_sge; 95 int max_srq_sge; 96 int max_rdma_sge; 97 int max_mr; 98 u64 max_mr_size; 99 u32 max_num_mr_pbl; 100 int max_mw; 101 int max_fmr; 102 int max_map_per_fmr; 103 int max_pages_per_frmr; 104 u16 max_ord_per_qp; 105 u16 max_ird_per_qp; 106 107 int device_cap_flags; 108 u8 cq_overflow_detect; 109 u8 srq_supported; 110 111 u32 wqe_size; 112 u32 rqe_size; 113 u32 ird_page_size; 114 u8 local_ca_ack_delay; 115 u8 ird; 116 u8 num_ird_pages; 117 }; 118 119 struct ocrdma_dma_mem { 120 void *va; 121 dma_addr_t pa; 122 u32 size; 123 }; 124 125 struct ocrdma_pbl { 126 void *va; 127 dma_addr_t pa; 128 }; 129 130 struct ocrdma_queue_info { 131 void *va; 132 dma_addr_t dma; 133 u32 size; 134 u16 len; 135 u16 entry_size; /* Size of an element in the queue */ 136 u16 id; /* qid, where to ring the doorbell. */ 137 u16 head, tail; 138 bool created; 139 }; 140 141 struct ocrdma_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 142 u32 prev_eqd; 143 u64 eq_intr_cnt; 144 u64 prev_eq_intr_cnt; 145 }; 146 147 struct ocrdma_eq { 148 struct ocrdma_queue_info q; 149 u32 vector; 150 int cq_cnt; 151 struct ocrdma_dev *dev; 152 char irq_name[32]; 153 struct ocrdma_aic_obj aic_obj; 154 }; 155 156 struct ocrdma_mq { 157 struct ocrdma_queue_info sq; 158 struct ocrdma_queue_info cq; 159 bool rearm_cq; 160 }; 161 162 struct mqe_ctx { 163 struct mutex lock; /* for serializing mailbox commands on MQ */ 164 wait_queue_head_t cmd_wait; 165 u32 tag; 166 u16 cqe_status; 167 u16 ext_status; 168 bool cmd_done; 169 bool fw_error_state; 170 }; 171 172 struct ocrdma_hw_mr { 173 u32 lkey; 174 u8 fr_mr; 175 u8 remote_atomic; 176 u8 remote_rd; 177 u8 remote_wr; 178 u8 local_rd; 179 u8 local_wr; 180 u8 mw_bind; 181 u8 rsvd; 182 u64 len; 183 struct ocrdma_pbl *pbl_table; 184 u32 num_pbls; 185 u32 num_pbes; 186 u32 pbl_size; 187 u32 pbe_size; 188 u64 fbo; 189 u64 va; 190 }; 191 192 struct ocrdma_mr { 193 struct ib_mr ibmr; 194 struct ib_umem *umem; 195 struct ocrdma_hw_mr hwmr; 196 }; 197 198 struct ocrdma_stats { 199 u8 type; 200 struct ocrdma_dev *dev; 201 }; 202 203 struct ocrdma_pd_resource_mgr { 204 u32 pd_norm_start; 205 u16 pd_norm_count; 206 u16 pd_norm_thrsh; 207 u16 max_normal_pd; 208 u32 pd_dpp_start; 209 u16 pd_dpp_count; 210 u16 pd_dpp_thrsh; 211 u16 max_dpp_pd; 212 u16 dpp_page_index; 213 unsigned long *pd_norm_bitmap; 214 unsigned long *pd_dpp_bitmap; 215 bool pd_prealloc_valid; 216 }; 217 218 struct stats_mem { 219 struct ocrdma_mqe mqe; 220 void *va; 221 dma_addr_t pa; 222 u32 size; 223 char *debugfs_mem; 224 }; 225 226 struct phy_info { 227 u16 auto_speeds_supported; 228 u16 fixed_speeds_supported; 229 u16 phy_type; 230 u16 interface_type; 231 }; 232 233 struct ocrdma_dev { 234 struct ib_device ibdev; 235 struct ocrdma_dev_attr attr; 236 237 struct mutex dev_lock; /* provides syncronise access to device data */ 238 spinlock_t flush_q_lock ____cacheline_aligned; 239 240 struct ocrdma_cq **cq_tbl; 241 struct ocrdma_qp **qp_tbl; 242 243 struct ocrdma_eq *eq_tbl; 244 int eq_cnt; 245 struct delayed_work eqd_work; 246 u16 base_eqid; 247 u16 max_eq; 248 249 /* provided synchronization to sgid table for 250 * updating gid entries triggered by notifier. 251 */ 252 spinlock_t sgid_lock; 253 254 int gsi_qp_created; 255 struct ocrdma_cq *gsi_sqcq; 256 struct ocrdma_cq *gsi_rqcq; 257 258 struct { 259 struct ocrdma_av *va; 260 dma_addr_t pa; 261 u32 size; 262 u32 num_ah; 263 /* provide synchronization for av 264 * entry allocations. 265 */ 266 spinlock_t lock; 267 u32 ahid; 268 struct ocrdma_pbl pbl; 269 } av_tbl; 270 271 void *mbx_cmd; 272 struct ocrdma_mq mq; 273 struct mqe_ctx mqe_ctx; 274 275 struct be_dev_info nic_info; 276 struct phy_info phy; 277 char model_number[32]; 278 u32 hba_port_num; 279 280 struct list_head entry; 281 struct rcu_head rcu; 282 int id; 283 u64 *stag_arr; 284 u8 sl; /* service level */ 285 bool pfc_state; 286 atomic_t update_sl; 287 u16 pvid; 288 u32 asic_id; 289 290 ulong last_stats_time; 291 struct mutex stats_lock; /* provide synch for debugfs operations */ 292 struct stats_mem stats_mem; 293 struct ocrdma_stats rsrc_stats; 294 struct ocrdma_stats rx_stats; 295 struct ocrdma_stats wqe_stats; 296 struct ocrdma_stats tx_stats; 297 struct ocrdma_stats db_err_stats; 298 struct ocrdma_stats tx_qp_err_stats; 299 struct ocrdma_stats rx_qp_err_stats; 300 struct ocrdma_stats tx_dbg_stats; 301 struct ocrdma_stats rx_dbg_stats; 302 struct ocrdma_stats driver_stats; 303 struct ocrdma_stats reset_stats; 304 struct dentry *dir; 305 atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS]; 306 atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR]; 307 struct ocrdma_pd_resource_mgr *pd_mgr; 308 }; 309 310 struct ocrdma_cq { 311 struct ib_cq ibcq; 312 struct ocrdma_cqe *va; 313 u32 phase; 314 u32 getp; /* pointer to pending wrs to 315 * return to stack, wrap arounds 316 * at max_hw_cqe 317 */ 318 u32 max_hw_cqe; 319 bool phase_change; 320 bool deferred_arm, deferred_sol; 321 bool first_arm; 322 323 spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization 324 * to cq polling 325 */ 326 /* syncronizes cq completion handler invoked from multiple context */ 327 spinlock_t comp_handler_lock ____cacheline_aligned; 328 u16 id; 329 u16 eqn; 330 331 struct ocrdma_ucontext *ucontext; 332 dma_addr_t pa; 333 u32 len; 334 u32 cqe_cnt; 335 336 /* head of all qp's sq and rq for which cqes need to be flushed 337 * by the software. 338 */ 339 struct list_head sq_head, rq_head; 340 }; 341 342 struct ocrdma_pd { 343 struct ib_pd ibpd; 344 struct ocrdma_ucontext *uctx; 345 u32 id; 346 int num_dpp_qp; 347 u32 dpp_page; 348 bool dpp_enabled; 349 }; 350 351 struct ocrdma_ah { 352 struct ib_ah ibah; 353 struct ocrdma_av *av; 354 u16 sgid_index; 355 u32 id; 356 }; 357 358 struct ocrdma_qp_hwq_info { 359 u8 *va; /* virtual address */ 360 u32 max_sges; 361 u32 head, tail; 362 u32 entry_size; 363 u32 max_cnt; 364 u32 max_wqe_idx; 365 u16 dbid; /* qid, where to ring the doorbell. */ 366 u32 len; 367 dma_addr_t pa; 368 }; 369 370 struct ocrdma_srq { 371 struct ib_srq ibsrq; 372 u8 __iomem *db; 373 struct ocrdma_qp_hwq_info rq; 374 u64 *rqe_wr_id_tbl; 375 u32 *idx_bit_fields; 376 u32 bit_fields_len; 377 378 /* provide synchronization to multiple context(s) posting rqe */ 379 spinlock_t q_lock ____cacheline_aligned; 380 381 struct ocrdma_pd *pd; 382 u32 id; 383 }; 384 385 struct ocrdma_qp { 386 struct ib_qp ibqp; 387 388 u8 __iomem *sq_db; 389 struct ocrdma_qp_hwq_info sq; 390 struct { 391 uint64_t wrid; 392 uint16_t dpp_wqe_idx; 393 uint16_t dpp_wqe; 394 uint8_t signaled; 395 uint8_t rsvd[3]; 396 } *wqe_wr_id_tbl; 397 u32 max_inline_data; 398 399 /* provide synchronization to multiple context(s) posting wqe, rqe */ 400 spinlock_t q_lock ____cacheline_aligned; 401 struct ocrdma_cq *sq_cq; 402 /* list maintained per CQ to flush SQ errors */ 403 struct list_head sq_entry; 404 405 u8 __iomem *rq_db; 406 struct ocrdma_qp_hwq_info rq; 407 u64 *rqe_wr_id_tbl; 408 struct ocrdma_cq *rq_cq; 409 struct ocrdma_srq *srq; 410 /* list maintained per CQ to flush RQ errors */ 411 struct list_head rq_entry; 412 413 enum ocrdma_qp_state state; /* QP state */ 414 int cap_flags; 415 u32 max_ord, max_ird; 416 417 u32 id; 418 struct ocrdma_pd *pd; 419 420 enum ib_qp_type qp_type; 421 422 int sgid_idx; 423 u32 qkey; 424 bool dpp_enabled; 425 u8 *ird_q_va; 426 bool signaled; 427 }; 428 429 struct ocrdma_ucontext { 430 struct ib_ucontext ibucontext; 431 432 struct list_head mm_head; 433 struct mutex mm_list_lock; /* protects list entries of mm type */ 434 struct ocrdma_pd *cntxt_pd; 435 int pd_in_use; 436 437 struct { 438 u32 *va; 439 dma_addr_t pa; 440 u32 len; 441 } ah_tbl; 442 }; 443 444 struct ocrdma_mm { 445 struct { 446 u64 phy_addr; 447 unsigned long len; 448 } key; 449 struct list_head entry; 450 }; 451 452 static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev) 453 { 454 return container_of(ibdev, struct ocrdma_dev, ibdev); 455 } 456 457 static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext 458 *ibucontext) 459 { 460 return container_of(ibucontext, struct ocrdma_ucontext, ibucontext); 461 } 462 463 static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd) 464 { 465 return container_of(ibpd, struct ocrdma_pd, ibpd); 466 } 467 468 static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq) 469 { 470 return container_of(ibcq, struct ocrdma_cq, ibcq); 471 } 472 473 static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp) 474 { 475 return container_of(ibqp, struct ocrdma_qp, ibqp); 476 } 477 478 static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr) 479 { 480 return container_of(ibmr, struct ocrdma_mr, ibmr); 481 } 482 483 static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah) 484 { 485 return container_of(ibah, struct ocrdma_ah, ibah); 486 } 487 488 static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq) 489 { 490 return container_of(ibsrq, struct ocrdma_srq, ibsrq); 491 } 492 493 static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe) 494 { 495 int cqe_valid; 496 cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID; 497 return (cqe_valid == cq->phase); 498 } 499 500 static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe) 501 { 502 return (le32_to_cpu(cqe->flags_status_srcqpn) & 503 OCRDMA_CQE_QTYPE) ? 0 : 1; 504 } 505 506 static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe) 507 { 508 return (le32_to_cpu(cqe->flags_status_srcqpn) & 509 OCRDMA_CQE_INVALIDATE) ? 1 : 0; 510 } 511 512 static inline int is_cqe_imm(struct ocrdma_cqe *cqe) 513 { 514 return (le32_to_cpu(cqe->flags_status_srcqpn) & 515 OCRDMA_CQE_IMM) ? 1 : 0; 516 } 517 518 static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe) 519 { 520 return (le32_to_cpu(cqe->flags_status_srcqpn) & 521 OCRDMA_CQE_WRITE_IMM) ? 1 : 0; 522 } 523 524 static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev, 525 struct ib_ah_attr *ah_attr, u8 *mac_addr) 526 { 527 struct in6_addr in6; 528 529 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6)); 530 if (rdma_is_multicast_addr(&in6)) 531 rdma_get_mcast_mac(&in6, mac_addr); 532 else if (rdma_link_local_addr(&in6)) 533 rdma_get_ll_mac(&in6, mac_addr); 534 else 535 memcpy(mac_addr, ah_attr->dmac, ETH_ALEN); 536 return 0; 537 } 538 539 static inline char *hca_name(struct ocrdma_dev *dev) 540 { 541 switch (dev->nic_info.pdev->device) { 542 case OC_SKH_DEVICE_PF: 543 case OC_SKH_DEVICE_VF: 544 return OC_NAME_SH; 545 default: 546 return OC_NAME_UNKNOWN; 547 } 548 } 549 550 static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev, 551 int eqid) 552 { 553 int indx; 554 555 for (indx = 0; indx < dev->eq_cnt; indx++) { 556 if (dev->eq_tbl[indx].q.id == eqid) 557 return indx; 558 } 559 560 return -EINVAL; 561 } 562 563 static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev) 564 { 565 if (dev->nic_info.dev_family == 0xF && !dev->asic_id) { 566 pci_read_config_dword( 567 dev->nic_info.pdev, 568 OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id); 569 } 570 571 return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >> 572 OCRDMA_SLI_ASIC_GEN_NUM_SHIFT; 573 } 574 575 static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio) 576 { 577 return *(pfc + prio); 578 } 579 580 static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio) 581 { 582 return *(app_prio + prio); 583 } 584 585 static inline u8 ocrdma_is_enabled_and_synced(u32 state) 586 { /* May also be used to interpret TC-state, QCN-state 587 * Appl-state and Logical-link-state in future. 588 */ 589 return (state & OCRDMA_STATE_FLAG_ENABLED) && 590 (state & OCRDMA_STATE_FLAG_SYNC); 591 } 592 593 #endif 594