1 /*
2  * Copyright (c) 2005 Cisco Systems. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  * $Id: mthca_wqe.h 3047 2005-08-10 03:59:35Z roland $
33  */
34 
35 #ifndef MTHCA_WQE_H
36 #define MTHCA_WQE_H
37 
38 #include <linux/types.h>
39 
40 enum {
41 	MTHCA_NEXT_DBD		= 1 << 7,
42 	MTHCA_NEXT_FENCE	= 1 << 6,
43 	MTHCA_NEXT_CQ_UPDATE	= 1 << 3,
44 	MTHCA_NEXT_EVENT_GEN	= 1 << 2,
45 	MTHCA_NEXT_SOLICIT	= 1 << 1,
46 	MTHCA_NEXT_IP_CSUM	= 1 << 4,
47 	MTHCA_NEXT_TCP_UDP_CSUM = 1 << 5,
48 
49 	MTHCA_MLX_VL15		= 1 << 17,
50 	MTHCA_MLX_SLR		= 1 << 16
51 };
52 
53 enum {
54 	MTHCA_INVAL_LKEY			= 0x100,
55 	MTHCA_TAVOR_MAX_WQES_PER_RECV_DB	= 256,
56 	MTHCA_ARBEL_MAX_WQES_PER_SEND_DB	= 255
57 };
58 
59 struct mthca_next_seg {
60 	__be32 nda_op;		/* [31:6] next WQE [4:0] next opcode */
61 	__be32 ee_nds;		/* [31:8] next EE  [7] DBD [6] F [5:0] next WQE size */
62 	__be32 flags;		/* [3] CQ [2] Event [1] Solicit */
63 	__be32 imm;		/* immediate data */
64 };
65 
66 struct mthca_tavor_ud_seg {
67 	u32    reserved1;
68 	__be32 lkey;
69 	__be64 av_addr;
70 	u32    reserved2[4];
71 	__be32 dqpn;
72 	__be32 qkey;
73 	u32    reserved3[2];
74 };
75 
76 struct mthca_arbel_ud_seg {
77 	__be32 av[8];
78 	__be32 dqpn;
79 	__be32 qkey;
80 	u32    reserved[2];
81 };
82 
83 struct mthca_bind_seg {
84 	__be32 flags;		/* [31] Atomic [30] rem write [29] rem read */
85 	u32    reserved;
86 	__be32 new_rkey;
87 	__be32 lkey;
88 	__be64 addr;
89 	__be64 length;
90 };
91 
92 struct mthca_raddr_seg {
93 	__be64 raddr;
94 	__be32 rkey;
95 	u32    reserved;
96 };
97 
98 struct mthca_atomic_seg {
99 	__be64 swap_add;
100 	__be64 compare;
101 };
102 
103 struct mthca_data_seg {
104 	__be32 byte_count;
105 	__be32 lkey;
106 	__be64 addr;
107 };
108 
109 struct mthca_mlx_seg {
110 	__be32 nda_op;
111 	__be32 nds;
112 	__be32 flags;		/* [17] VL15 [16] SLR [14:12] static rate
113 				   [11:8] SL [3] C [2] E */
114 	__be16 rlid;
115 	__be16 vcrc;
116 };
117 
118 static __always_inline void mthca_set_data_seg(struct mthca_data_seg *dseg,
119 					       struct ib_sge *sg)
120 {
121 	dseg->byte_count = cpu_to_be32(sg->length);
122 	dseg->lkey       = cpu_to_be32(sg->lkey);
123 	dseg->addr       = cpu_to_be64(sg->addr);
124 }
125 
126 static __always_inline void mthca_set_data_seg_inval(struct mthca_data_seg *dseg)
127 {
128 	dseg->byte_count = 0;
129 	dseg->lkey       = cpu_to_be32(MTHCA_INVAL_LKEY);
130 	dseg->addr       = 0;
131 }
132 
133 #endif /* MTHCA_WQE_H */
134