1 /* 2 * Copyright (c) 2004 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Cisco Systems. All rights reserved. 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 * 35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $ 36 */ 37 38 #include <linux/string.h> 39 #include <linux/slab.h> 40 #include <linux/sched.h> 41 42 #include <asm/io.h> 43 44 #include <rdma/ib_verbs.h> 45 #include <rdma/ib_cache.h> 46 #include <rdma/ib_pack.h> 47 48 #include "mthca_dev.h" 49 #include "mthca_cmd.h" 50 #include "mthca_memfree.h" 51 #include "mthca_wqe.h" 52 53 enum { 54 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE, 55 MTHCA_ACK_REQ_FREQ = 10, 56 MTHCA_FLIGHT_LIMIT = 9, 57 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */ 58 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */ 59 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */ 60 }; 61 62 enum { 63 MTHCA_QP_STATE_RST = 0, 64 MTHCA_QP_STATE_INIT = 1, 65 MTHCA_QP_STATE_RTR = 2, 66 MTHCA_QP_STATE_RTS = 3, 67 MTHCA_QP_STATE_SQE = 4, 68 MTHCA_QP_STATE_SQD = 5, 69 MTHCA_QP_STATE_ERR = 6, 70 MTHCA_QP_STATE_DRAINING = 7 71 }; 72 73 enum { 74 MTHCA_QP_ST_RC = 0x0, 75 MTHCA_QP_ST_UC = 0x1, 76 MTHCA_QP_ST_RD = 0x2, 77 MTHCA_QP_ST_UD = 0x3, 78 MTHCA_QP_ST_MLX = 0x7 79 }; 80 81 enum { 82 MTHCA_QP_PM_MIGRATED = 0x3, 83 MTHCA_QP_PM_ARMED = 0x0, 84 MTHCA_QP_PM_REARM = 0x1 85 }; 86 87 enum { 88 /* qp_context flags */ 89 MTHCA_QP_BIT_DE = 1 << 8, 90 /* params1 */ 91 MTHCA_QP_BIT_SRE = 1 << 15, 92 MTHCA_QP_BIT_SWE = 1 << 14, 93 MTHCA_QP_BIT_SAE = 1 << 13, 94 MTHCA_QP_BIT_SIC = 1 << 4, 95 MTHCA_QP_BIT_SSC = 1 << 3, 96 /* params2 */ 97 MTHCA_QP_BIT_RRE = 1 << 15, 98 MTHCA_QP_BIT_RWE = 1 << 14, 99 MTHCA_QP_BIT_RAE = 1 << 13, 100 MTHCA_QP_BIT_RIC = 1 << 4, 101 MTHCA_QP_BIT_RSC = 1 << 3 102 }; 103 104 enum { 105 MTHCA_SEND_DOORBELL_FENCE = 1 << 5 106 }; 107 108 struct mthca_qp_path { 109 __be32 port_pkey; 110 u8 rnr_retry; 111 u8 g_mylmc; 112 __be16 rlid; 113 u8 ackto; 114 u8 mgid_index; 115 u8 static_rate; 116 u8 hop_limit; 117 __be32 sl_tclass_flowlabel; 118 u8 rgid[16]; 119 } __attribute__((packed)); 120 121 struct mthca_qp_context { 122 __be32 flags; 123 __be32 tavor_sched_queue; /* Reserved on Arbel */ 124 u8 mtu_msgmax; 125 u8 rq_size_stride; /* Reserved on Tavor */ 126 u8 sq_size_stride; /* Reserved on Tavor */ 127 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */ 128 __be32 usr_page; 129 __be32 local_qpn; 130 __be32 remote_qpn; 131 u32 reserved1[2]; 132 struct mthca_qp_path pri_path; 133 struct mthca_qp_path alt_path; 134 __be32 rdd; 135 __be32 pd; 136 __be32 wqe_base; 137 __be32 wqe_lkey; 138 __be32 params1; 139 __be32 reserved2; 140 __be32 next_send_psn; 141 __be32 cqn_snd; 142 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */ 143 __be32 snd_db_index; /* (debugging only entries) */ 144 __be32 last_acked_psn; 145 __be32 ssn; 146 __be32 params2; 147 __be32 rnr_nextrecvpsn; 148 __be32 ra_buff_indx; 149 __be32 cqn_rcv; 150 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */ 151 __be32 rcv_db_index; /* (debugging only entries) */ 152 __be32 qkey; 153 __be32 srqn; 154 __be32 rmsn; 155 __be16 rq_wqe_counter; /* reserved on Tavor */ 156 __be16 sq_wqe_counter; /* reserved on Tavor */ 157 u32 reserved3[18]; 158 } __attribute__((packed)); 159 160 struct mthca_qp_param { 161 __be32 opt_param_mask; 162 u32 reserved1; 163 struct mthca_qp_context context; 164 u32 reserved2[62]; 165 } __attribute__((packed)); 166 167 enum { 168 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 169 MTHCA_QP_OPTPAR_RRE = 1 << 1, 170 MTHCA_QP_OPTPAR_RAE = 1 << 2, 171 MTHCA_QP_OPTPAR_RWE = 1 << 3, 172 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4, 173 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5, 174 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 175 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 176 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8, 177 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9, 178 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10, 179 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11, 180 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12, 181 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13, 182 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 183 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15, 184 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16 185 }; 186 187 static const u8 mthca_opcode[] = { 188 [IB_WR_SEND] = MTHCA_OPCODE_SEND, 189 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM, 190 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE, 191 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM, 192 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ, 193 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS, 194 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA, 195 }; 196 197 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp) 198 { 199 return qp->qpn >= dev->qp_table.sqp_start && 200 qp->qpn <= dev->qp_table.sqp_start + 3; 201 } 202 203 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp) 204 { 205 return qp->qpn >= dev->qp_table.sqp_start && 206 qp->qpn <= dev->qp_table.sqp_start + 1; 207 } 208 209 static void *get_recv_wqe(struct mthca_qp *qp, int n) 210 { 211 if (qp->is_direct) 212 return qp->queue.direct.buf + (n << qp->rq.wqe_shift); 213 else 214 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf + 215 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1)); 216 } 217 218 static void *get_send_wqe(struct mthca_qp *qp, int n) 219 { 220 if (qp->is_direct) 221 return qp->queue.direct.buf + qp->send_wqe_offset + 222 (n << qp->sq.wqe_shift); 223 else 224 return qp->queue.page_list[(qp->send_wqe_offset + 225 (n << qp->sq.wqe_shift)) >> 226 PAGE_SHIFT].buf + 227 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) & 228 (PAGE_SIZE - 1)); 229 } 230 231 static void mthca_wq_reset(struct mthca_wq *wq) 232 { 233 wq->next_ind = 0; 234 wq->last_comp = wq->max - 1; 235 wq->head = 0; 236 wq->tail = 0; 237 } 238 239 void mthca_qp_event(struct mthca_dev *dev, u32 qpn, 240 enum ib_event_type event_type) 241 { 242 struct mthca_qp *qp; 243 struct ib_event event; 244 245 spin_lock(&dev->qp_table.lock); 246 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1)); 247 if (qp) 248 ++qp->refcount; 249 spin_unlock(&dev->qp_table.lock); 250 251 if (!qp) { 252 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn); 253 return; 254 } 255 256 if (event_type == IB_EVENT_PATH_MIG) 257 qp->port = qp->alt_port; 258 259 event.device = &dev->ib_dev; 260 event.event = event_type; 261 event.element.qp = &qp->ibqp; 262 if (qp->ibqp.event_handler) 263 qp->ibqp.event_handler(&event, qp->ibqp.qp_context); 264 265 spin_lock(&dev->qp_table.lock); 266 if (!--qp->refcount) 267 wake_up(&qp->wait); 268 spin_unlock(&dev->qp_table.lock); 269 } 270 271 static int to_mthca_state(enum ib_qp_state ib_state) 272 { 273 switch (ib_state) { 274 case IB_QPS_RESET: return MTHCA_QP_STATE_RST; 275 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT; 276 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR; 277 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS; 278 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD; 279 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE; 280 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR; 281 default: return -1; 282 } 283 } 284 285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS }; 286 287 static int to_mthca_st(int transport) 288 { 289 switch (transport) { 290 case RC: return MTHCA_QP_ST_RC; 291 case UC: return MTHCA_QP_ST_UC; 292 case UD: return MTHCA_QP_ST_UD; 293 case RD: return MTHCA_QP_ST_RD; 294 case MLX: return MTHCA_QP_ST_MLX; 295 default: return -1; 296 } 297 } 298 299 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr, 300 int attr_mask) 301 { 302 if (attr_mask & IB_QP_PKEY_INDEX) 303 sqp->pkey_index = attr->pkey_index; 304 if (attr_mask & IB_QP_QKEY) 305 sqp->qkey = attr->qkey; 306 if (attr_mask & IB_QP_SQ_PSN) 307 sqp->send_psn = attr->sq_psn; 308 } 309 310 static void init_port(struct mthca_dev *dev, int port) 311 { 312 int err; 313 u8 status; 314 struct mthca_init_ib_param param; 315 316 memset(¶m, 0, sizeof param); 317 318 param.port_width = dev->limits.port_width_cap; 319 param.vl_cap = dev->limits.vl_cap; 320 param.mtu_cap = dev->limits.mtu_cap; 321 param.gid_cap = dev->limits.gid_table_len; 322 param.pkey_cap = dev->limits.pkey_table_len; 323 324 err = mthca_INIT_IB(dev, ¶m, port, &status); 325 if (err) 326 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err); 327 if (status) 328 mthca_warn(dev, "INIT_IB returned status %02x.\n", status); 329 } 330 331 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr, 332 int attr_mask) 333 { 334 u8 dest_rd_atomic; 335 u32 access_flags; 336 u32 hw_access_flags = 0; 337 338 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 339 dest_rd_atomic = attr->max_dest_rd_atomic; 340 else 341 dest_rd_atomic = qp->resp_depth; 342 343 if (attr_mask & IB_QP_ACCESS_FLAGS) 344 access_flags = attr->qp_access_flags; 345 else 346 access_flags = qp->atomic_rd_en; 347 348 if (!dest_rd_atomic) 349 access_flags &= IB_ACCESS_REMOTE_WRITE; 350 351 if (access_flags & IB_ACCESS_REMOTE_READ) 352 hw_access_flags |= MTHCA_QP_BIT_RRE; 353 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 354 hw_access_flags |= MTHCA_QP_BIT_RAE; 355 if (access_flags & IB_ACCESS_REMOTE_WRITE) 356 hw_access_flags |= MTHCA_QP_BIT_RWE; 357 358 return cpu_to_be32(hw_access_flags); 359 } 360 361 static inline enum ib_qp_state to_ib_qp_state(int mthca_state) 362 { 363 switch (mthca_state) { 364 case MTHCA_QP_STATE_RST: return IB_QPS_RESET; 365 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT; 366 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR; 367 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS; 368 case MTHCA_QP_STATE_DRAINING: 369 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD; 370 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE; 371 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR; 372 default: return -1; 373 } 374 } 375 376 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state) 377 { 378 switch (mthca_mig_state) { 379 case 0: return IB_MIG_ARMED; 380 case 1: return IB_MIG_REARM; 381 case 3: return IB_MIG_MIGRATED; 382 default: return -1; 383 } 384 } 385 386 static int to_ib_qp_access_flags(int mthca_flags) 387 { 388 int ib_flags = 0; 389 390 if (mthca_flags & MTHCA_QP_BIT_RRE) 391 ib_flags |= IB_ACCESS_REMOTE_READ; 392 if (mthca_flags & MTHCA_QP_BIT_RWE) 393 ib_flags |= IB_ACCESS_REMOTE_WRITE; 394 if (mthca_flags & MTHCA_QP_BIT_RAE) 395 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 396 397 return ib_flags; 398 } 399 400 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr, 401 struct mthca_qp_path *path) 402 { 403 memset(ib_ah_attr, 0, sizeof *ib_ah_attr); 404 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3; 405 406 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports) 407 return; 408 409 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 410 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28; 411 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f; 412 ib_ah_attr->static_rate = mthca_rate_to_ib(dev, 413 path->static_rate & 0xf, 414 ib_ah_attr->port_num); 415 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0; 416 if (ib_ah_attr->ah_flags) { 417 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1); 418 ib_ah_attr->grh.hop_limit = path->hop_limit; 419 ib_ah_attr->grh.traffic_class = 420 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff; 421 ib_ah_attr->grh.flow_label = 422 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff; 423 memcpy(ib_ah_attr->grh.dgid.raw, 424 path->rgid, sizeof ib_ah_attr->grh.dgid.raw); 425 } 426 } 427 428 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 429 struct ib_qp_init_attr *qp_init_attr) 430 { 431 struct mthca_dev *dev = to_mdev(ibqp->device); 432 struct mthca_qp *qp = to_mqp(ibqp); 433 int err = 0; 434 struct mthca_mailbox *mailbox = NULL; 435 struct mthca_qp_param *qp_param; 436 struct mthca_qp_context *context; 437 int mthca_state; 438 u8 status; 439 440 mutex_lock(&qp->mutex); 441 442 if (qp->state == IB_QPS_RESET) { 443 qp_attr->qp_state = IB_QPS_RESET; 444 goto done; 445 } 446 447 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 448 if (IS_ERR(mailbox)) { 449 err = PTR_ERR(mailbox); 450 goto out; 451 } 452 453 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status); 454 if (err) 455 goto out_mailbox; 456 if (status) { 457 mthca_warn(dev, "QUERY_QP returned status %02x\n", status); 458 err = -EINVAL; 459 goto out_mailbox; 460 } 461 462 qp_param = mailbox->buf; 463 context = &qp_param->context; 464 mthca_state = be32_to_cpu(context->flags) >> 28; 465 466 qp->state = to_ib_qp_state(mthca_state); 467 qp_attr->qp_state = qp->state; 468 qp_attr->path_mtu = context->mtu_msgmax >> 5; 469 qp_attr->path_mig_state = 470 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 471 qp_attr->qkey = be32_to_cpu(context->qkey); 472 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 473 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 474 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff; 475 qp_attr->qp_access_flags = 476 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 477 478 if (qp->transport == RC || qp->transport == UC) { 479 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 480 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 481 qp_attr->alt_pkey_index = 482 be32_to_cpu(context->alt_path.port_pkey) & 0x7f; 483 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 484 } 485 486 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f; 487 qp_attr->port_num = 488 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3; 489 490 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 491 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING; 492 493 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 494 495 qp_attr->max_dest_rd_atomic = 496 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 497 qp_attr->min_rnr_timer = 498 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 499 qp_attr->timeout = context->pri_path.ackto >> 3; 500 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 501 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5; 502 qp_attr->alt_timeout = context->alt_path.ackto >> 3; 503 504 done: 505 qp_attr->cur_qp_state = qp_attr->qp_state; 506 qp_attr->cap.max_send_wr = qp->sq.max; 507 qp_attr->cap.max_recv_wr = qp->rq.max; 508 qp_attr->cap.max_send_sge = qp->sq.max_gs; 509 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 510 qp_attr->cap.max_inline_data = qp->max_inline_data; 511 512 qp_init_attr->cap = qp_attr->cap; 513 514 out_mailbox: 515 mthca_free_mailbox(dev, mailbox); 516 517 out: 518 mutex_unlock(&qp->mutex); 519 return err; 520 } 521 522 static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah, 523 struct mthca_qp_path *path, u8 port) 524 { 525 path->g_mylmc = ah->src_path_bits & 0x7f; 526 path->rlid = cpu_to_be16(ah->dlid); 527 path->static_rate = mthca_get_rate(dev, ah->static_rate, port); 528 529 if (ah->ah_flags & IB_AH_GRH) { 530 if (ah->grh.sgid_index >= dev->limits.gid_table_len) { 531 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n", 532 ah->grh.sgid_index, dev->limits.gid_table_len-1); 533 return -1; 534 } 535 536 path->g_mylmc |= 1 << 7; 537 path->mgid_index = ah->grh.sgid_index; 538 path->hop_limit = ah->grh.hop_limit; 539 path->sl_tclass_flowlabel = 540 cpu_to_be32((ah->sl << 28) | 541 (ah->grh.traffic_class << 20) | 542 (ah->grh.flow_label)); 543 memcpy(path->rgid, ah->grh.dgid.raw, 16); 544 } else 545 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28); 546 547 return 0; 548 } 549 550 static int __mthca_modify_qp(struct ib_qp *ibqp, 551 const struct ib_qp_attr *attr, int attr_mask, 552 enum ib_qp_state cur_state, enum ib_qp_state new_state) 553 { 554 struct mthca_dev *dev = to_mdev(ibqp->device); 555 struct mthca_qp *qp = to_mqp(ibqp); 556 struct mthca_mailbox *mailbox; 557 struct mthca_qp_param *qp_param; 558 struct mthca_qp_context *qp_context; 559 u32 sqd_event = 0; 560 u8 status; 561 int err = -EINVAL; 562 563 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 564 if (IS_ERR(mailbox)) { 565 err = PTR_ERR(mailbox); 566 goto out; 567 } 568 qp_param = mailbox->buf; 569 qp_context = &qp_param->context; 570 memset(qp_param, 0, sizeof *qp_param); 571 572 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) | 573 (to_mthca_st(qp->transport) << 16)); 574 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE); 575 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 576 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11); 577 else { 578 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE); 579 switch (attr->path_mig_state) { 580 case IB_MIG_MIGRATED: 581 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11); 582 break; 583 case IB_MIG_REARM: 584 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11); 585 break; 586 case IB_MIG_ARMED: 587 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11); 588 break; 589 } 590 } 591 592 /* leave tavor_sched_queue as 0 */ 593 594 if (qp->transport == MLX || qp->transport == UD) 595 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11; 596 else if (attr_mask & IB_QP_PATH_MTU) { 597 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) { 598 mthca_dbg(dev, "path MTU (%u) is invalid\n", 599 attr->path_mtu); 600 goto out_mailbox; 601 } 602 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31; 603 } 604 605 if (mthca_is_memfree(dev)) { 606 if (qp->rq.max) 607 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3; 608 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4; 609 610 if (qp->sq.max) 611 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3; 612 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4; 613 } 614 615 /* leave arbel_sched_queue as 0 */ 616 617 if (qp->ibqp.uobject) 618 qp_context->usr_page = 619 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index); 620 else 621 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index); 622 qp_context->local_qpn = cpu_to_be32(qp->qpn); 623 if (attr_mask & IB_QP_DEST_QPN) { 624 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 625 } 626 627 if (qp->transport == MLX) 628 qp_context->pri_path.port_pkey |= 629 cpu_to_be32(qp->port << 24); 630 else { 631 if (attr_mask & IB_QP_PORT) { 632 qp_context->pri_path.port_pkey |= 633 cpu_to_be32(attr->port_num << 24); 634 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM); 635 } 636 } 637 638 if (attr_mask & IB_QP_PKEY_INDEX) { 639 qp_context->pri_path.port_pkey |= 640 cpu_to_be32(attr->pkey_index); 641 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX); 642 } 643 644 if (attr_mask & IB_QP_RNR_RETRY) { 645 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry = 646 attr->rnr_retry << 5; 647 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY | 648 MTHCA_QP_OPTPAR_ALT_RNR_RETRY); 649 } 650 651 if (attr_mask & IB_QP_AV) { 652 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path, 653 attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) 654 goto out_mailbox; 655 656 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH); 657 } 658 659 if (ibqp->qp_type == IB_QPT_RC && 660 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 661 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1; 662 663 if (mthca_is_memfree(dev)) 664 qp_context->rlkey_arbel_sched_queue |= sched_queue; 665 else 666 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue); 667 668 qp_param->opt_param_mask |= 669 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE); 670 } 671 672 if (attr_mask & IB_QP_TIMEOUT) { 673 qp_context->pri_path.ackto = attr->timeout << 3; 674 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT); 675 } 676 677 if (attr_mask & IB_QP_ALT_PATH) { 678 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) { 679 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n", 680 attr->alt_pkey_index, dev->limits.pkey_table_len-1); 681 goto out_mailbox; 682 } 683 684 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) { 685 mthca_dbg(dev, "Alternate port number (%u) is invalid\n", 686 attr->alt_port_num); 687 goto out_mailbox; 688 } 689 690 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path, 691 attr->alt_ah_attr.port_num)) 692 goto out_mailbox; 693 694 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index | 695 attr->alt_port_num << 24); 696 qp_context->alt_path.ackto = attr->alt_timeout << 3; 697 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH); 698 } 699 700 /* leave rdd as 0 */ 701 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num); 702 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */ 703 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey); 704 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) | 705 (MTHCA_FLIGHT_LIMIT << 24) | 706 MTHCA_QP_BIT_SWE); 707 if (qp->sq_policy == IB_SIGNAL_ALL_WR) 708 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC); 709 if (attr_mask & IB_QP_RETRY_CNT) { 710 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 711 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT); 712 } 713 714 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 715 if (attr->max_rd_atomic) { 716 qp_context->params1 |= 717 cpu_to_be32(MTHCA_QP_BIT_SRE | 718 MTHCA_QP_BIT_SAE); 719 qp_context->params1 |= 720 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 721 } 722 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX); 723 } 724 725 if (attr_mask & IB_QP_SQ_PSN) 726 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn); 727 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn); 728 729 if (mthca_is_memfree(dev)) { 730 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset); 731 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index); 732 } 733 734 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 735 if (attr->max_dest_rd_atomic) 736 qp_context->params2 |= 737 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 738 739 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX); 740 } 741 742 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 743 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask); 744 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE | 745 MTHCA_QP_OPTPAR_RRE | 746 MTHCA_QP_OPTPAR_RAE); 747 } 748 749 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC); 750 751 if (ibqp->srq) 752 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC); 753 754 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 755 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 756 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT); 757 } 758 if (attr_mask & IB_QP_RQ_PSN) 759 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 760 761 qp_context->ra_buff_indx = 762 cpu_to_be32(dev->qp_table.rdb_base + 763 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE << 764 dev->qp_table.rdb_shift)); 765 766 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn); 767 768 if (mthca_is_memfree(dev)) 769 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index); 770 771 if (attr_mask & IB_QP_QKEY) { 772 qp_context->qkey = cpu_to_be32(attr->qkey); 773 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY); 774 } 775 776 if (ibqp->srq) 777 qp_context->srqn = cpu_to_be32(1 << 24 | 778 to_msrq(ibqp->srq)->srqn); 779 780 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 781 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && 782 attr->en_sqd_async_notify) 783 sqd_event = 1 << 31; 784 785 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0, 786 mailbox, sqd_event, &status); 787 if (err) 788 goto out_mailbox; 789 if (status) { 790 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n", 791 cur_state, new_state, status); 792 err = -EINVAL; 793 goto out_mailbox; 794 } 795 796 qp->state = new_state; 797 if (attr_mask & IB_QP_ACCESS_FLAGS) 798 qp->atomic_rd_en = attr->qp_access_flags; 799 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 800 qp->resp_depth = attr->max_dest_rd_atomic; 801 if (attr_mask & IB_QP_PORT) 802 qp->port = attr->port_num; 803 if (attr_mask & IB_QP_ALT_PATH) 804 qp->alt_port = attr->alt_port_num; 805 806 if (is_sqp(dev, qp)) 807 store_attrs(to_msqp(qp), attr, attr_mask); 808 809 /* 810 * If we moved QP0 to RTR, bring the IB link up; if we moved 811 * QP0 to RESET or ERROR, bring the link back down. 812 */ 813 if (is_qp0(dev, qp)) { 814 if (cur_state != IB_QPS_RTR && 815 new_state == IB_QPS_RTR) 816 init_port(dev, qp->port); 817 818 if (cur_state != IB_QPS_RESET && 819 cur_state != IB_QPS_ERR && 820 (new_state == IB_QPS_RESET || 821 new_state == IB_QPS_ERR)) 822 mthca_CLOSE_IB(dev, qp->port, &status); 823 } 824 825 /* 826 * If we moved a kernel QP to RESET, clean up all old CQ 827 * entries and reinitialize the QP. 828 */ 829 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) { 830 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn, 831 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 832 if (qp->ibqp.send_cq != qp->ibqp.recv_cq) 833 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL); 834 835 mthca_wq_reset(&qp->sq); 836 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1); 837 838 mthca_wq_reset(&qp->rq); 839 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1); 840 841 if (mthca_is_memfree(dev)) { 842 *qp->sq.db = 0; 843 *qp->rq.db = 0; 844 } 845 } 846 847 out_mailbox: 848 mthca_free_mailbox(dev, mailbox); 849 out: 850 return err; 851 } 852 853 static const struct ib_qp_attr dummy_init_attr = { .port_num = 1 }; 854 static const int dummy_init_attr_mask[] = { 855 [IB_QPT_UD] = (IB_QP_PKEY_INDEX | 856 IB_QP_PORT | 857 IB_QP_QKEY), 858 [IB_QPT_UC] = (IB_QP_PKEY_INDEX | 859 IB_QP_PORT | 860 IB_QP_ACCESS_FLAGS), 861 [IB_QPT_RC] = (IB_QP_PKEY_INDEX | 862 IB_QP_PORT | 863 IB_QP_ACCESS_FLAGS), 864 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX | 865 IB_QP_QKEY), 866 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX | 867 IB_QP_QKEY), 868 }; 869 870 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, 871 struct ib_udata *udata) 872 { 873 struct mthca_dev *dev = to_mdev(ibqp->device); 874 struct mthca_qp *qp = to_mqp(ibqp); 875 enum ib_qp_state cur_state, new_state; 876 int err = -EINVAL; 877 878 mutex_lock(&qp->mutex); 879 if (attr_mask & IB_QP_CUR_STATE) { 880 cur_state = attr->cur_qp_state; 881 } else { 882 spin_lock_irq(&qp->sq.lock); 883 spin_lock(&qp->rq.lock); 884 cur_state = qp->state; 885 spin_unlock(&qp->rq.lock); 886 spin_unlock_irq(&qp->sq.lock); 887 } 888 889 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 890 891 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) { 892 mthca_dbg(dev, "Bad QP transition (transport %d) " 893 "%d->%d with attr 0x%08x\n", 894 qp->transport, cur_state, new_state, 895 attr_mask); 896 goto out; 897 } 898 899 if ((attr_mask & IB_QP_PKEY_INDEX) && 900 attr->pkey_index >= dev->limits.pkey_table_len) { 901 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n", 902 attr->pkey_index, dev->limits.pkey_table_len-1); 903 goto out; 904 } 905 906 if ((attr_mask & IB_QP_PORT) && 907 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) { 908 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num); 909 goto out; 910 } 911 912 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 913 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) { 914 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n", 915 attr->max_rd_atomic, dev->limits.max_qp_init_rdma); 916 goto out; 917 } 918 919 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 920 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) { 921 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n", 922 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift); 923 goto out; 924 } 925 926 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 927 err = 0; 928 goto out; 929 } 930 931 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) { 932 err = __mthca_modify_qp(ibqp, &dummy_init_attr, 933 dummy_init_attr_mask[ibqp->qp_type], 934 IB_QPS_RESET, IB_QPS_INIT); 935 if (err) 936 goto out; 937 cur_state = IB_QPS_INIT; 938 } 939 940 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 941 942 out: 943 mutex_unlock(&qp->mutex); 944 return err; 945 } 946 947 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz) 948 { 949 /* 950 * Calculate the maximum size of WQE s/g segments, excluding 951 * the next segment and other non-data segments. 952 */ 953 int max_data_size = desc_sz - sizeof (struct mthca_next_seg); 954 955 switch (qp->transport) { 956 case MLX: 957 max_data_size -= 2 * sizeof (struct mthca_data_seg); 958 break; 959 960 case UD: 961 if (mthca_is_memfree(dev)) 962 max_data_size -= sizeof (struct mthca_arbel_ud_seg); 963 else 964 max_data_size -= sizeof (struct mthca_tavor_ud_seg); 965 break; 966 967 default: 968 max_data_size -= sizeof (struct mthca_raddr_seg); 969 break; 970 } 971 972 return max_data_size; 973 } 974 975 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size) 976 { 977 /* We don't support inline data for kernel QPs (yet). */ 978 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0; 979 } 980 981 static void mthca_adjust_qp_caps(struct mthca_dev *dev, 982 struct mthca_pd *pd, 983 struct mthca_qp *qp) 984 { 985 int max_data_size = mthca_max_data_size(dev, qp, 986 min(dev->limits.max_desc_sz, 987 1 << qp->sq.wqe_shift)); 988 989 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size); 990 991 qp->sq.max_gs = min_t(int, dev->limits.max_sg, 992 max_data_size / sizeof (struct mthca_data_seg)); 993 qp->rq.max_gs = min_t(int, dev->limits.max_sg, 994 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) - 995 sizeof (struct mthca_next_seg)) / 996 sizeof (struct mthca_data_seg)); 997 } 998 999 /* 1000 * Allocate and register buffer for WQEs. qp->rq.max, sq.max, 1001 * rq.max_gs and sq.max_gs must all be assigned. 1002 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and 1003 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and 1004 * queue) 1005 */ 1006 static int mthca_alloc_wqe_buf(struct mthca_dev *dev, 1007 struct mthca_pd *pd, 1008 struct mthca_qp *qp) 1009 { 1010 int size; 1011 int err = -ENOMEM; 1012 1013 size = sizeof (struct mthca_next_seg) + 1014 qp->rq.max_gs * sizeof (struct mthca_data_seg); 1015 1016 if (size > dev->limits.max_desc_sz) 1017 return -EINVAL; 1018 1019 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size; 1020 qp->rq.wqe_shift++) 1021 ; /* nothing */ 1022 1023 size = qp->sq.max_gs * sizeof (struct mthca_data_seg); 1024 switch (qp->transport) { 1025 case MLX: 1026 size += 2 * sizeof (struct mthca_data_seg); 1027 break; 1028 1029 case UD: 1030 size += mthca_is_memfree(dev) ? 1031 sizeof (struct mthca_arbel_ud_seg) : 1032 sizeof (struct mthca_tavor_ud_seg); 1033 break; 1034 1035 case UC: 1036 size += sizeof (struct mthca_raddr_seg); 1037 break; 1038 1039 case RC: 1040 size += sizeof (struct mthca_raddr_seg); 1041 /* 1042 * An atomic op will require an atomic segment, a 1043 * remote address segment and one scatter entry. 1044 */ 1045 size = max_t(int, size, 1046 sizeof (struct mthca_atomic_seg) + 1047 sizeof (struct mthca_raddr_seg) + 1048 sizeof (struct mthca_data_seg)); 1049 break; 1050 1051 default: 1052 break; 1053 } 1054 1055 /* Make sure that we have enough space for a bind request */ 1056 size = max_t(int, size, sizeof (struct mthca_bind_seg)); 1057 1058 size += sizeof (struct mthca_next_seg); 1059 1060 if (size > dev->limits.max_desc_sz) 1061 return -EINVAL; 1062 1063 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size; 1064 qp->sq.wqe_shift++) 1065 ; /* nothing */ 1066 1067 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift, 1068 1 << qp->sq.wqe_shift); 1069 1070 /* 1071 * If this is a userspace QP, we don't actually have to 1072 * allocate anything. All we need is to calculate the WQE 1073 * sizes and the send_wqe_offset, so we're done now. 1074 */ 1075 if (pd->ibpd.uobject) 1076 return 0; 1077 1078 size = PAGE_ALIGN(qp->send_wqe_offset + 1079 (qp->sq.max << qp->sq.wqe_shift)); 1080 1081 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64), 1082 GFP_KERNEL); 1083 if (!qp->wrid) 1084 goto err_out; 1085 1086 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE, 1087 &qp->queue, &qp->is_direct, pd, 0, &qp->mr); 1088 if (err) 1089 goto err_out; 1090 1091 return 0; 1092 1093 err_out: 1094 kfree(qp->wrid); 1095 return err; 1096 } 1097 1098 static void mthca_free_wqe_buf(struct mthca_dev *dev, 1099 struct mthca_qp *qp) 1100 { 1101 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset + 1102 (qp->sq.max << qp->sq.wqe_shift)), 1103 &qp->queue, qp->is_direct, &qp->mr); 1104 kfree(qp->wrid); 1105 } 1106 1107 static int mthca_map_memfree(struct mthca_dev *dev, 1108 struct mthca_qp *qp) 1109 { 1110 int ret; 1111 1112 if (mthca_is_memfree(dev)) { 1113 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn); 1114 if (ret) 1115 return ret; 1116 1117 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn); 1118 if (ret) 1119 goto err_qpc; 1120 1121 ret = mthca_table_get(dev, dev->qp_table.rdb_table, 1122 qp->qpn << dev->qp_table.rdb_shift); 1123 if (ret) 1124 goto err_eqpc; 1125 1126 } 1127 1128 return 0; 1129 1130 err_eqpc: 1131 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn); 1132 1133 err_qpc: 1134 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn); 1135 1136 return ret; 1137 } 1138 1139 static void mthca_unmap_memfree(struct mthca_dev *dev, 1140 struct mthca_qp *qp) 1141 { 1142 mthca_table_put(dev, dev->qp_table.rdb_table, 1143 qp->qpn << dev->qp_table.rdb_shift); 1144 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn); 1145 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn); 1146 } 1147 1148 static int mthca_alloc_memfree(struct mthca_dev *dev, 1149 struct mthca_qp *qp) 1150 { 1151 if (mthca_is_memfree(dev)) { 1152 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ, 1153 qp->qpn, &qp->rq.db); 1154 if (qp->rq.db_index < 0) 1155 return -ENOMEM; 1156 1157 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ, 1158 qp->qpn, &qp->sq.db); 1159 if (qp->sq.db_index < 0) { 1160 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index); 1161 return -ENOMEM; 1162 } 1163 } 1164 1165 return 0; 1166 } 1167 1168 static void mthca_free_memfree(struct mthca_dev *dev, 1169 struct mthca_qp *qp) 1170 { 1171 if (mthca_is_memfree(dev)) { 1172 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index); 1173 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index); 1174 } 1175 } 1176 1177 static int mthca_alloc_qp_common(struct mthca_dev *dev, 1178 struct mthca_pd *pd, 1179 struct mthca_cq *send_cq, 1180 struct mthca_cq *recv_cq, 1181 enum ib_sig_type send_policy, 1182 struct mthca_qp *qp) 1183 { 1184 int ret; 1185 int i; 1186 struct mthca_next_seg *next; 1187 1188 qp->refcount = 1; 1189 init_waitqueue_head(&qp->wait); 1190 mutex_init(&qp->mutex); 1191 qp->state = IB_QPS_RESET; 1192 qp->atomic_rd_en = 0; 1193 qp->resp_depth = 0; 1194 qp->sq_policy = send_policy; 1195 mthca_wq_reset(&qp->sq); 1196 mthca_wq_reset(&qp->rq); 1197 1198 spin_lock_init(&qp->sq.lock); 1199 spin_lock_init(&qp->rq.lock); 1200 1201 ret = mthca_map_memfree(dev, qp); 1202 if (ret) 1203 return ret; 1204 1205 ret = mthca_alloc_wqe_buf(dev, pd, qp); 1206 if (ret) { 1207 mthca_unmap_memfree(dev, qp); 1208 return ret; 1209 } 1210 1211 mthca_adjust_qp_caps(dev, pd, qp); 1212 1213 /* 1214 * If this is a userspace QP, we're done now. The doorbells 1215 * will be allocated and buffers will be initialized in 1216 * userspace. 1217 */ 1218 if (pd->ibpd.uobject) 1219 return 0; 1220 1221 ret = mthca_alloc_memfree(dev, qp); 1222 if (ret) { 1223 mthca_free_wqe_buf(dev, qp); 1224 mthca_unmap_memfree(dev, qp); 1225 return ret; 1226 } 1227 1228 if (mthca_is_memfree(dev)) { 1229 struct mthca_data_seg *scatter; 1230 int size = (sizeof (struct mthca_next_seg) + 1231 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16; 1232 1233 for (i = 0; i < qp->rq.max; ++i) { 1234 next = get_recv_wqe(qp, i); 1235 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) << 1236 qp->rq.wqe_shift); 1237 next->ee_nds = cpu_to_be32(size); 1238 1239 for (scatter = (void *) (next + 1); 1240 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift); 1241 ++scatter) 1242 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); 1243 } 1244 1245 for (i = 0; i < qp->sq.max; ++i) { 1246 next = get_send_wqe(qp, i); 1247 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) << 1248 qp->sq.wqe_shift) + 1249 qp->send_wqe_offset); 1250 } 1251 } else { 1252 for (i = 0; i < qp->rq.max; ++i) { 1253 next = get_recv_wqe(qp, i); 1254 next->nda_op = htonl((((i + 1) % qp->rq.max) << 1255 qp->rq.wqe_shift) | 1); 1256 } 1257 1258 } 1259 1260 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1); 1261 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1); 1262 1263 return 0; 1264 } 1265 1266 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap, 1267 struct mthca_pd *pd, struct mthca_qp *qp) 1268 { 1269 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz); 1270 1271 /* Sanity check QP size before proceeding */ 1272 if (cap->max_send_wr > dev->limits.max_wqes || 1273 cap->max_recv_wr > dev->limits.max_wqes || 1274 cap->max_send_sge > dev->limits.max_sg || 1275 cap->max_recv_sge > dev->limits.max_sg || 1276 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size)) 1277 return -EINVAL; 1278 1279 /* 1280 * For MLX transport we need 2 extra S/G entries: 1281 * one for the header and one for the checksum at the end 1282 */ 1283 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg) 1284 return -EINVAL; 1285 1286 if (mthca_is_memfree(dev)) { 1287 qp->rq.max = cap->max_recv_wr ? 1288 roundup_pow_of_two(cap->max_recv_wr) : 0; 1289 qp->sq.max = cap->max_send_wr ? 1290 roundup_pow_of_two(cap->max_send_wr) : 0; 1291 } else { 1292 qp->rq.max = cap->max_recv_wr; 1293 qp->sq.max = cap->max_send_wr; 1294 } 1295 1296 qp->rq.max_gs = cap->max_recv_sge; 1297 qp->sq.max_gs = max_t(int, cap->max_send_sge, 1298 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE, 1299 MTHCA_INLINE_CHUNK_SIZE) / 1300 sizeof (struct mthca_data_seg)); 1301 1302 return 0; 1303 } 1304 1305 int mthca_alloc_qp(struct mthca_dev *dev, 1306 struct mthca_pd *pd, 1307 struct mthca_cq *send_cq, 1308 struct mthca_cq *recv_cq, 1309 enum ib_qp_type type, 1310 enum ib_sig_type send_policy, 1311 struct ib_qp_cap *cap, 1312 struct mthca_qp *qp) 1313 { 1314 int err; 1315 1316 switch (type) { 1317 case IB_QPT_RC: qp->transport = RC; break; 1318 case IB_QPT_UC: qp->transport = UC; break; 1319 case IB_QPT_UD: qp->transport = UD; break; 1320 default: return -EINVAL; 1321 } 1322 1323 err = mthca_set_qp_size(dev, cap, pd, qp); 1324 if (err) 1325 return err; 1326 1327 qp->qpn = mthca_alloc(&dev->qp_table.alloc); 1328 if (qp->qpn == -1) 1329 return -ENOMEM; 1330 1331 /* initialize port to zero for error-catching. */ 1332 qp->port = 0; 1333 1334 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq, 1335 send_policy, qp); 1336 if (err) { 1337 mthca_free(&dev->qp_table.alloc, qp->qpn); 1338 return err; 1339 } 1340 1341 spin_lock_irq(&dev->qp_table.lock); 1342 mthca_array_set(&dev->qp_table.qp, 1343 qp->qpn & (dev->limits.num_qps - 1), qp); 1344 spin_unlock_irq(&dev->qp_table.lock); 1345 1346 return 0; 1347 } 1348 1349 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq) 1350 { 1351 if (send_cq == recv_cq) 1352 spin_lock_irq(&send_cq->lock); 1353 else if (send_cq->cqn < recv_cq->cqn) { 1354 spin_lock_irq(&send_cq->lock); 1355 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1356 } else { 1357 spin_lock_irq(&recv_cq->lock); 1358 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1359 } 1360 } 1361 1362 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq) 1363 { 1364 if (send_cq == recv_cq) 1365 spin_unlock_irq(&send_cq->lock); 1366 else if (send_cq->cqn < recv_cq->cqn) { 1367 spin_unlock(&recv_cq->lock); 1368 spin_unlock_irq(&send_cq->lock); 1369 } else { 1370 spin_unlock(&send_cq->lock); 1371 spin_unlock_irq(&recv_cq->lock); 1372 } 1373 } 1374 1375 int mthca_alloc_sqp(struct mthca_dev *dev, 1376 struct mthca_pd *pd, 1377 struct mthca_cq *send_cq, 1378 struct mthca_cq *recv_cq, 1379 enum ib_sig_type send_policy, 1380 struct ib_qp_cap *cap, 1381 int qpn, 1382 int port, 1383 struct mthca_sqp *sqp) 1384 { 1385 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1; 1386 int err; 1387 1388 sqp->qp.transport = MLX; 1389 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp); 1390 if (err) 1391 return err; 1392 1393 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE; 1394 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size, 1395 &sqp->header_dma, GFP_KERNEL); 1396 if (!sqp->header_buf) 1397 return -ENOMEM; 1398 1399 spin_lock_irq(&dev->qp_table.lock); 1400 if (mthca_array_get(&dev->qp_table.qp, mqpn)) 1401 err = -EBUSY; 1402 else 1403 mthca_array_set(&dev->qp_table.qp, mqpn, sqp); 1404 spin_unlock_irq(&dev->qp_table.lock); 1405 1406 if (err) 1407 goto err_out; 1408 1409 sqp->qp.port = port; 1410 sqp->qp.qpn = mqpn; 1411 sqp->qp.transport = MLX; 1412 1413 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq, 1414 send_policy, &sqp->qp); 1415 if (err) 1416 goto err_out_free; 1417 1418 atomic_inc(&pd->sqp_count); 1419 1420 return 0; 1421 1422 err_out_free: 1423 /* 1424 * Lock CQs here, so that CQ polling code can do QP lookup 1425 * without taking a lock. 1426 */ 1427 mthca_lock_cqs(send_cq, recv_cq); 1428 1429 spin_lock(&dev->qp_table.lock); 1430 mthca_array_clear(&dev->qp_table.qp, mqpn); 1431 spin_unlock(&dev->qp_table.lock); 1432 1433 mthca_unlock_cqs(send_cq, recv_cq); 1434 1435 err_out: 1436 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size, 1437 sqp->header_buf, sqp->header_dma); 1438 1439 return err; 1440 } 1441 1442 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp) 1443 { 1444 int c; 1445 1446 spin_lock_irq(&dev->qp_table.lock); 1447 c = qp->refcount; 1448 spin_unlock_irq(&dev->qp_table.lock); 1449 1450 return c; 1451 } 1452 1453 void mthca_free_qp(struct mthca_dev *dev, 1454 struct mthca_qp *qp) 1455 { 1456 u8 status; 1457 struct mthca_cq *send_cq; 1458 struct mthca_cq *recv_cq; 1459 1460 send_cq = to_mcq(qp->ibqp.send_cq); 1461 recv_cq = to_mcq(qp->ibqp.recv_cq); 1462 1463 /* 1464 * Lock CQs here, so that CQ polling code can do QP lookup 1465 * without taking a lock. 1466 */ 1467 mthca_lock_cqs(send_cq, recv_cq); 1468 1469 spin_lock(&dev->qp_table.lock); 1470 mthca_array_clear(&dev->qp_table.qp, 1471 qp->qpn & (dev->limits.num_qps - 1)); 1472 --qp->refcount; 1473 spin_unlock(&dev->qp_table.lock); 1474 1475 mthca_unlock_cqs(send_cq, recv_cq); 1476 1477 wait_event(qp->wait, !get_qp_refcount(dev, qp)); 1478 1479 if (qp->state != IB_QPS_RESET) 1480 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0, 1481 NULL, 0, &status); 1482 1483 /* 1484 * If this is a userspace QP, the buffers, MR, CQs and so on 1485 * will be cleaned up in userspace, so all we have to do is 1486 * unref the mem-free tables and free the QPN in our table. 1487 */ 1488 if (!qp->ibqp.uobject) { 1489 mthca_cq_clean(dev, recv_cq, qp->qpn, 1490 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1491 if (send_cq != recv_cq) 1492 mthca_cq_clean(dev, send_cq, qp->qpn, NULL); 1493 1494 mthca_free_memfree(dev, qp); 1495 mthca_free_wqe_buf(dev, qp); 1496 } 1497 1498 mthca_unmap_memfree(dev, qp); 1499 1500 if (is_sqp(dev, qp)) { 1501 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count)); 1502 dma_free_coherent(&dev->pdev->dev, 1503 to_msqp(qp)->header_buf_size, 1504 to_msqp(qp)->header_buf, 1505 to_msqp(qp)->header_dma); 1506 } else 1507 mthca_free(&dev->qp_table.alloc, qp->qpn); 1508 } 1509 1510 /* Create UD header for an MLX send and build a data segment for it */ 1511 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp, 1512 int ind, struct ib_send_wr *wr, 1513 struct mthca_mlx_seg *mlx, 1514 struct mthca_data_seg *data) 1515 { 1516 int header_size; 1517 int err; 1518 u16 pkey; 1519 1520 ib_ud_header_init(256, /* assume a MAD */ 1521 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)), 1522 &sqp->ud_header); 1523 1524 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header); 1525 if (err) 1526 return err; 1527 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1); 1528 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) | 1529 (sqp->ud_header.lrh.destination_lid == 1530 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) | 1531 (sqp->ud_header.lrh.service_level << 8)); 1532 mlx->rlid = sqp->ud_header.lrh.destination_lid; 1533 mlx->vcrc = 0; 1534 1535 switch (wr->opcode) { 1536 case IB_WR_SEND: 1537 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1538 sqp->ud_header.immediate_present = 0; 1539 break; 1540 case IB_WR_SEND_WITH_IMM: 1541 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1542 sqp->ud_header.immediate_present = 1; 1543 sqp->ud_header.immediate_data = wr->ex.imm_data; 1544 break; 1545 default: 1546 return -EINVAL; 1547 } 1548 1549 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; 1550 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 1551 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 1552 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 1553 if (!sqp->qp.ibqp.qp_num) 1554 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port, 1555 sqp->pkey_index, &pkey); 1556 else 1557 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port, 1558 wr->wr.ud.pkey_index, &pkey); 1559 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 1560 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1561 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 1562 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? 1563 sqp->qkey : wr->wr.ud.remote_qkey); 1564 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 1565 1566 header_size = ib_ud_header_pack(&sqp->ud_header, 1567 sqp->header_buf + 1568 ind * MTHCA_UD_HEADER_SIZE); 1569 1570 data->byte_count = cpu_to_be32(header_size); 1571 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey); 1572 data->addr = cpu_to_be64(sqp->header_dma + 1573 ind * MTHCA_UD_HEADER_SIZE); 1574 1575 return 0; 1576 } 1577 1578 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq, 1579 struct ib_cq *ib_cq) 1580 { 1581 unsigned cur; 1582 struct mthca_cq *cq; 1583 1584 cur = wq->head - wq->tail; 1585 if (likely(cur + nreq < wq->max)) 1586 return 0; 1587 1588 cq = to_mcq(ib_cq); 1589 spin_lock(&cq->lock); 1590 cur = wq->head - wq->tail; 1591 spin_unlock(&cq->lock); 1592 1593 return cur + nreq >= wq->max; 1594 } 1595 1596 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg, 1597 u64 remote_addr, u32 rkey) 1598 { 1599 rseg->raddr = cpu_to_be64(remote_addr); 1600 rseg->rkey = cpu_to_be32(rkey); 1601 rseg->reserved = 0; 1602 } 1603 1604 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg, 1605 struct ib_send_wr *wr) 1606 { 1607 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 1608 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 1609 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 1610 } else { 1611 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 1612 aseg->compare = 0; 1613 } 1614 1615 } 1616 1617 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg, 1618 struct ib_send_wr *wr) 1619 { 1620 useg->lkey = cpu_to_be32(to_mah(wr->wr.ud.ah)->key); 1621 useg->av_addr = cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma); 1622 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1623 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1624 1625 } 1626 1627 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg, 1628 struct ib_send_wr *wr) 1629 { 1630 memcpy(useg->av, to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE); 1631 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1632 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1633 } 1634 1635 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 1636 struct ib_send_wr **bad_wr) 1637 { 1638 struct mthca_dev *dev = to_mdev(ibqp->device); 1639 struct mthca_qp *qp = to_mqp(ibqp); 1640 void *wqe; 1641 void *prev_wqe; 1642 unsigned long flags; 1643 int err = 0; 1644 int nreq; 1645 int i; 1646 int size; 1647 /* 1648 * f0 and size0 are only used if nreq != 0, and they will 1649 * always be initialized the first time through the main loop 1650 * before nreq is incremented. So nreq cannot become non-zero 1651 * without initializing f0 and size0, and they are in fact 1652 * never used uninitialized. 1653 */ 1654 int uninitialized_var(size0); 1655 u32 uninitialized_var(f0); 1656 int ind; 1657 u8 op0 = 0; 1658 1659 spin_lock_irqsave(&qp->sq.lock, flags); 1660 1661 /* XXX check that state is OK to post send */ 1662 1663 ind = qp->sq.next_ind; 1664 1665 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1666 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 1667 mthca_err(dev, "SQ %06x full (%u head, %u tail," 1668 " %d max, %d nreq)\n", qp->qpn, 1669 qp->sq.head, qp->sq.tail, 1670 qp->sq.max, nreq); 1671 err = -ENOMEM; 1672 *bad_wr = wr; 1673 goto out; 1674 } 1675 1676 wqe = get_send_wqe(qp, ind); 1677 prev_wqe = qp->sq.last; 1678 qp->sq.last = wqe; 1679 1680 ((struct mthca_next_seg *) wqe)->nda_op = 0; 1681 ((struct mthca_next_seg *) wqe)->ee_nds = 0; 1682 ((struct mthca_next_seg *) wqe)->flags = 1683 ((wr->send_flags & IB_SEND_SIGNALED) ? 1684 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) | 1685 ((wr->send_flags & IB_SEND_SOLICITED) ? 1686 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) | 1687 cpu_to_be32(1); 1688 if (wr->opcode == IB_WR_SEND_WITH_IMM || 1689 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) 1690 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data; 1691 1692 wqe += sizeof (struct mthca_next_seg); 1693 size = sizeof (struct mthca_next_seg) / 16; 1694 1695 switch (qp->transport) { 1696 case RC: 1697 switch (wr->opcode) { 1698 case IB_WR_ATOMIC_CMP_AND_SWP: 1699 case IB_WR_ATOMIC_FETCH_AND_ADD: 1700 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 1701 wr->wr.atomic.rkey); 1702 wqe += sizeof (struct mthca_raddr_seg); 1703 1704 set_atomic_seg(wqe, wr); 1705 wqe += sizeof (struct mthca_atomic_seg); 1706 size += (sizeof (struct mthca_raddr_seg) + 1707 sizeof (struct mthca_atomic_seg)) / 16; 1708 break; 1709 1710 case IB_WR_RDMA_WRITE: 1711 case IB_WR_RDMA_WRITE_WITH_IMM: 1712 case IB_WR_RDMA_READ: 1713 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 1714 wr->wr.rdma.rkey); 1715 wqe += sizeof (struct mthca_raddr_seg); 1716 size += sizeof (struct mthca_raddr_seg) / 16; 1717 break; 1718 1719 default: 1720 /* No extra segments required for sends */ 1721 break; 1722 } 1723 1724 break; 1725 1726 case UC: 1727 switch (wr->opcode) { 1728 case IB_WR_RDMA_WRITE: 1729 case IB_WR_RDMA_WRITE_WITH_IMM: 1730 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 1731 wr->wr.rdma.rkey); 1732 wqe += sizeof (struct mthca_raddr_seg); 1733 size += sizeof (struct mthca_raddr_seg) / 16; 1734 break; 1735 1736 default: 1737 /* No extra segments required for sends */ 1738 break; 1739 } 1740 1741 break; 1742 1743 case UD: 1744 set_tavor_ud_seg(wqe, wr); 1745 wqe += sizeof (struct mthca_tavor_ud_seg); 1746 size += sizeof (struct mthca_tavor_ud_seg) / 16; 1747 break; 1748 1749 case MLX: 1750 err = build_mlx_header(dev, to_msqp(qp), ind, wr, 1751 wqe - sizeof (struct mthca_next_seg), 1752 wqe); 1753 if (err) { 1754 *bad_wr = wr; 1755 goto out; 1756 } 1757 wqe += sizeof (struct mthca_data_seg); 1758 size += sizeof (struct mthca_data_seg) / 16; 1759 break; 1760 } 1761 1762 if (wr->num_sge > qp->sq.max_gs) { 1763 mthca_err(dev, "too many gathers\n"); 1764 err = -EINVAL; 1765 *bad_wr = wr; 1766 goto out; 1767 } 1768 1769 for (i = 0; i < wr->num_sge; ++i) { 1770 mthca_set_data_seg(wqe, wr->sg_list + i); 1771 wqe += sizeof (struct mthca_data_seg); 1772 size += sizeof (struct mthca_data_seg) / 16; 1773 } 1774 1775 /* Add one more inline data segment for ICRC */ 1776 if (qp->transport == MLX) { 1777 ((struct mthca_data_seg *) wqe)->byte_count = 1778 cpu_to_be32((1 << 31) | 4); 1779 ((u32 *) wqe)[1] = 0; 1780 wqe += sizeof (struct mthca_data_seg); 1781 size += sizeof (struct mthca_data_seg) / 16; 1782 } 1783 1784 qp->wrid[ind + qp->rq.max] = wr->wr_id; 1785 1786 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) { 1787 mthca_err(dev, "opcode invalid\n"); 1788 err = -EINVAL; 1789 *bad_wr = wr; 1790 goto out; 1791 } 1792 1793 ((struct mthca_next_seg *) prev_wqe)->nda_op = 1794 cpu_to_be32(((ind << qp->sq.wqe_shift) + 1795 qp->send_wqe_offset) | 1796 mthca_opcode[wr->opcode]); 1797 wmb(); 1798 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 1799 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size | 1800 ((wr->send_flags & IB_SEND_FENCE) ? 1801 MTHCA_NEXT_FENCE : 0)); 1802 1803 if (!nreq) { 1804 size0 = size; 1805 op0 = mthca_opcode[wr->opcode]; 1806 f0 = wr->send_flags & IB_SEND_FENCE ? 1807 MTHCA_SEND_DOORBELL_FENCE : 0; 1808 } 1809 1810 ++ind; 1811 if (unlikely(ind >= qp->sq.max)) 1812 ind -= qp->sq.max; 1813 } 1814 1815 out: 1816 if (likely(nreq)) { 1817 wmb(); 1818 1819 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) + 1820 qp->send_wqe_offset) | f0 | op0, 1821 (qp->qpn << 8) | size0, 1822 dev->kar + MTHCA_SEND_DOORBELL, 1823 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1824 /* 1825 * Make sure doorbells don't leak out of SQ spinlock 1826 * and reach the HCA out of order: 1827 */ 1828 mmiowb(); 1829 } 1830 1831 qp->sq.next_ind = ind; 1832 qp->sq.head += nreq; 1833 1834 spin_unlock_irqrestore(&qp->sq.lock, flags); 1835 return err; 1836 } 1837 1838 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 1839 struct ib_recv_wr **bad_wr) 1840 { 1841 struct mthca_dev *dev = to_mdev(ibqp->device); 1842 struct mthca_qp *qp = to_mqp(ibqp); 1843 unsigned long flags; 1844 int err = 0; 1845 int nreq; 1846 int i; 1847 int size; 1848 /* 1849 * size0 is only used if nreq != 0, and it will always be 1850 * initialized the first time through the main loop before 1851 * nreq is incremented. So nreq cannot become non-zero 1852 * without initializing size0, and it is in fact never used 1853 * uninitialized. 1854 */ 1855 int uninitialized_var(size0); 1856 int ind; 1857 void *wqe; 1858 void *prev_wqe; 1859 1860 spin_lock_irqsave(&qp->rq.lock, flags); 1861 1862 /* XXX check that state is OK to post receive */ 1863 1864 ind = qp->rq.next_ind; 1865 1866 for (nreq = 0; wr; wr = wr->next) { 1867 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 1868 mthca_err(dev, "RQ %06x full (%u head, %u tail," 1869 " %d max, %d nreq)\n", qp->qpn, 1870 qp->rq.head, qp->rq.tail, 1871 qp->rq.max, nreq); 1872 err = -ENOMEM; 1873 *bad_wr = wr; 1874 goto out; 1875 } 1876 1877 wqe = get_recv_wqe(qp, ind); 1878 prev_wqe = qp->rq.last; 1879 qp->rq.last = wqe; 1880 1881 ((struct mthca_next_seg *) wqe)->ee_nds = 1882 cpu_to_be32(MTHCA_NEXT_DBD); 1883 ((struct mthca_next_seg *) wqe)->flags = 0; 1884 1885 wqe += sizeof (struct mthca_next_seg); 1886 size = sizeof (struct mthca_next_seg) / 16; 1887 1888 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 1889 err = -EINVAL; 1890 *bad_wr = wr; 1891 goto out; 1892 } 1893 1894 for (i = 0; i < wr->num_sge; ++i) { 1895 mthca_set_data_seg(wqe, wr->sg_list + i); 1896 wqe += sizeof (struct mthca_data_seg); 1897 size += sizeof (struct mthca_data_seg) / 16; 1898 } 1899 1900 qp->wrid[ind] = wr->wr_id; 1901 1902 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 1903 cpu_to_be32(MTHCA_NEXT_DBD | size); 1904 1905 if (!nreq) 1906 size0 = size; 1907 1908 ++ind; 1909 if (unlikely(ind >= qp->rq.max)) 1910 ind -= qp->rq.max; 1911 1912 ++nreq; 1913 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 1914 nreq = 0; 1915 1916 wmb(); 1917 1918 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0, 1919 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL, 1920 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1921 1922 qp->rq.next_ind = ind; 1923 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB; 1924 } 1925 } 1926 1927 out: 1928 if (likely(nreq)) { 1929 wmb(); 1930 1931 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0, 1932 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL, 1933 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1934 } 1935 1936 qp->rq.next_ind = ind; 1937 qp->rq.head += nreq; 1938 1939 /* 1940 * Make sure doorbells don't leak out of RQ spinlock and reach 1941 * the HCA out of order: 1942 */ 1943 mmiowb(); 1944 1945 spin_unlock_irqrestore(&qp->rq.lock, flags); 1946 return err; 1947 } 1948 1949 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 1950 struct ib_send_wr **bad_wr) 1951 { 1952 struct mthca_dev *dev = to_mdev(ibqp->device); 1953 struct mthca_qp *qp = to_mqp(ibqp); 1954 u32 dbhi; 1955 void *wqe; 1956 void *prev_wqe; 1957 unsigned long flags; 1958 int err = 0; 1959 int nreq; 1960 int i; 1961 int size; 1962 /* 1963 * f0 and size0 are only used if nreq != 0, and they will 1964 * always be initialized the first time through the main loop 1965 * before nreq is incremented. So nreq cannot become non-zero 1966 * without initializing f0 and size0, and they are in fact 1967 * never used uninitialized. 1968 */ 1969 int uninitialized_var(size0); 1970 u32 uninitialized_var(f0); 1971 int ind; 1972 u8 op0 = 0; 1973 1974 spin_lock_irqsave(&qp->sq.lock, flags); 1975 1976 /* XXX check that state is OK to post send */ 1977 1978 ind = qp->sq.head & (qp->sq.max - 1); 1979 1980 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1981 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) { 1982 nreq = 0; 1983 1984 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) | 1985 ((qp->sq.head & 0xffff) << 8) | f0 | op0; 1986 1987 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB; 1988 1989 /* 1990 * Make sure that descriptors are written before 1991 * doorbell record. 1992 */ 1993 wmb(); 1994 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff); 1995 1996 /* 1997 * Make sure doorbell record is written before we 1998 * write MMIO send doorbell. 1999 */ 2000 wmb(); 2001 2002 mthca_write64(dbhi, (qp->qpn << 8) | size0, 2003 dev->kar + MTHCA_SEND_DOORBELL, 2004 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 2005 } 2006 2007 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 2008 mthca_err(dev, "SQ %06x full (%u head, %u tail," 2009 " %d max, %d nreq)\n", qp->qpn, 2010 qp->sq.head, qp->sq.tail, 2011 qp->sq.max, nreq); 2012 err = -ENOMEM; 2013 *bad_wr = wr; 2014 goto out; 2015 } 2016 2017 wqe = get_send_wqe(qp, ind); 2018 prev_wqe = qp->sq.last; 2019 qp->sq.last = wqe; 2020 2021 ((struct mthca_next_seg *) wqe)->flags = 2022 ((wr->send_flags & IB_SEND_SIGNALED) ? 2023 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) | 2024 ((wr->send_flags & IB_SEND_SOLICITED) ? 2025 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) | 2026 ((wr->send_flags & IB_SEND_IP_CSUM) ? 2027 cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) | 2028 cpu_to_be32(1); 2029 if (wr->opcode == IB_WR_SEND_WITH_IMM || 2030 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) 2031 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data; 2032 2033 wqe += sizeof (struct mthca_next_seg); 2034 size = sizeof (struct mthca_next_seg) / 16; 2035 2036 switch (qp->transport) { 2037 case RC: 2038 switch (wr->opcode) { 2039 case IB_WR_ATOMIC_CMP_AND_SWP: 2040 case IB_WR_ATOMIC_FETCH_AND_ADD: 2041 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 2042 wr->wr.atomic.rkey); 2043 wqe += sizeof (struct mthca_raddr_seg); 2044 2045 set_atomic_seg(wqe, wr); 2046 wqe += sizeof (struct mthca_atomic_seg); 2047 size += (sizeof (struct mthca_raddr_seg) + 2048 sizeof (struct mthca_atomic_seg)) / 16; 2049 break; 2050 2051 case IB_WR_RDMA_READ: 2052 case IB_WR_RDMA_WRITE: 2053 case IB_WR_RDMA_WRITE_WITH_IMM: 2054 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 2055 wr->wr.rdma.rkey); 2056 wqe += sizeof (struct mthca_raddr_seg); 2057 size += sizeof (struct mthca_raddr_seg) / 16; 2058 break; 2059 2060 default: 2061 /* No extra segments required for sends */ 2062 break; 2063 } 2064 2065 break; 2066 2067 case UC: 2068 switch (wr->opcode) { 2069 case IB_WR_RDMA_WRITE: 2070 case IB_WR_RDMA_WRITE_WITH_IMM: 2071 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 2072 wr->wr.rdma.rkey); 2073 wqe += sizeof (struct mthca_raddr_seg); 2074 size += sizeof (struct mthca_raddr_seg) / 16; 2075 break; 2076 2077 default: 2078 /* No extra segments required for sends */ 2079 break; 2080 } 2081 2082 break; 2083 2084 case UD: 2085 set_arbel_ud_seg(wqe, wr); 2086 wqe += sizeof (struct mthca_arbel_ud_seg); 2087 size += sizeof (struct mthca_arbel_ud_seg) / 16; 2088 break; 2089 2090 case MLX: 2091 err = build_mlx_header(dev, to_msqp(qp), ind, wr, 2092 wqe - sizeof (struct mthca_next_seg), 2093 wqe); 2094 if (err) { 2095 *bad_wr = wr; 2096 goto out; 2097 } 2098 wqe += sizeof (struct mthca_data_seg); 2099 size += sizeof (struct mthca_data_seg) / 16; 2100 break; 2101 } 2102 2103 if (wr->num_sge > qp->sq.max_gs) { 2104 mthca_err(dev, "too many gathers\n"); 2105 err = -EINVAL; 2106 *bad_wr = wr; 2107 goto out; 2108 } 2109 2110 for (i = 0; i < wr->num_sge; ++i) { 2111 mthca_set_data_seg(wqe, wr->sg_list + i); 2112 wqe += sizeof (struct mthca_data_seg); 2113 size += sizeof (struct mthca_data_seg) / 16; 2114 } 2115 2116 /* Add one more inline data segment for ICRC */ 2117 if (qp->transport == MLX) { 2118 ((struct mthca_data_seg *) wqe)->byte_count = 2119 cpu_to_be32((1 << 31) | 4); 2120 ((u32 *) wqe)[1] = 0; 2121 wqe += sizeof (struct mthca_data_seg); 2122 size += sizeof (struct mthca_data_seg) / 16; 2123 } 2124 2125 qp->wrid[ind + qp->rq.max] = wr->wr_id; 2126 2127 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) { 2128 mthca_err(dev, "opcode invalid\n"); 2129 err = -EINVAL; 2130 *bad_wr = wr; 2131 goto out; 2132 } 2133 2134 ((struct mthca_next_seg *) prev_wqe)->nda_op = 2135 cpu_to_be32(((ind << qp->sq.wqe_shift) + 2136 qp->send_wqe_offset) | 2137 mthca_opcode[wr->opcode]); 2138 wmb(); 2139 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 2140 cpu_to_be32(MTHCA_NEXT_DBD | size | 2141 ((wr->send_flags & IB_SEND_FENCE) ? 2142 MTHCA_NEXT_FENCE : 0)); 2143 2144 if (!nreq) { 2145 size0 = size; 2146 op0 = mthca_opcode[wr->opcode]; 2147 f0 = wr->send_flags & IB_SEND_FENCE ? 2148 MTHCA_SEND_DOORBELL_FENCE : 0; 2149 } 2150 2151 ++ind; 2152 if (unlikely(ind >= qp->sq.max)) 2153 ind -= qp->sq.max; 2154 } 2155 2156 out: 2157 if (likely(nreq)) { 2158 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0; 2159 2160 qp->sq.head += nreq; 2161 2162 /* 2163 * Make sure that descriptors are written before 2164 * doorbell record. 2165 */ 2166 wmb(); 2167 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff); 2168 2169 /* 2170 * Make sure doorbell record is written before we 2171 * write MMIO send doorbell. 2172 */ 2173 wmb(); 2174 2175 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL, 2176 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 2177 } 2178 2179 /* 2180 * Make sure doorbells don't leak out of SQ spinlock and reach 2181 * the HCA out of order: 2182 */ 2183 mmiowb(); 2184 2185 spin_unlock_irqrestore(&qp->sq.lock, flags); 2186 return err; 2187 } 2188 2189 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 2190 struct ib_recv_wr **bad_wr) 2191 { 2192 struct mthca_dev *dev = to_mdev(ibqp->device); 2193 struct mthca_qp *qp = to_mqp(ibqp); 2194 unsigned long flags; 2195 int err = 0; 2196 int nreq; 2197 int ind; 2198 int i; 2199 void *wqe; 2200 2201 spin_lock_irqsave(&qp->rq.lock, flags); 2202 2203 /* XXX check that state is OK to post receive */ 2204 2205 ind = qp->rq.head & (qp->rq.max - 1); 2206 2207 for (nreq = 0; wr; ++nreq, wr = wr->next) { 2208 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 2209 mthca_err(dev, "RQ %06x full (%u head, %u tail," 2210 " %d max, %d nreq)\n", qp->qpn, 2211 qp->rq.head, qp->rq.tail, 2212 qp->rq.max, nreq); 2213 err = -ENOMEM; 2214 *bad_wr = wr; 2215 goto out; 2216 } 2217 2218 wqe = get_recv_wqe(qp, ind); 2219 2220 ((struct mthca_next_seg *) wqe)->flags = 0; 2221 2222 wqe += sizeof (struct mthca_next_seg); 2223 2224 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 2225 err = -EINVAL; 2226 *bad_wr = wr; 2227 goto out; 2228 } 2229 2230 for (i = 0; i < wr->num_sge; ++i) { 2231 mthca_set_data_seg(wqe, wr->sg_list + i); 2232 wqe += sizeof (struct mthca_data_seg); 2233 } 2234 2235 if (i < qp->rq.max_gs) 2236 mthca_set_data_seg_inval(wqe); 2237 2238 qp->wrid[ind] = wr->wr_id; 2239 2240 ++ind; 2241 if (unlikely(ind >= qp->rq.max)) 2242 ind -= qp->rq.max; 2243 } 2244 out: 2245 if (likely(nreq)) { 2246 qp->rq.head += nreq; 2247 2248 /* 2249 * Make sure that descriptors are written before 2250 * doorbell record. 2251 */ 2252 wmb(); 2253 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff); 2254 } 2255 2256 spin_unlock_irqrestore(&qp->rq.lock, flags); 2257 return err; 2258 } 2259 2260 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, 2261 int index, int *dbd, __be32 *new_wqe) 2262 { 2263 struct mthca_next_seg *next; 2264 2265 /* 2266 * For SRQs, all receive WQEs generate a CQE, so we're always 2267 * at the end of the doorbell chain. 2268 */ 2269 if (qp->ibqp.srq && !is_send) { 2270 *new_wqe = 0; 2271 return; 2272 } 2273 2274 if (is_send) 2275 next = get_send_wqe(qp, index); 2276 else 2277 next = get_recv_wqe(qp, index); 2278 2279 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD)); 2280 if (next->ee_nds & cpu_to_be32(0x3f)) 2281 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) | 2282 (next->ee_nds & cpu_to_be32(0x3f)); 2283 else 2284 *new_wqe = 0; 2285 } 2286 2287 int mthca_init_qp_table(struct mthca_dev *dev) 2288 { 2289 int err; 2290 u8 status; 2291 int i; 2292 2293 spin_lock_init(&dev->qp_table.lock); 2294 2295 /* 2296 * We reserve 2 extra QPs per port for the special QPs. The 2297 * special QP for port 1 has to be even, so round up. 2298 */ 2299 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL; 2300 err = mthca_alloc_init(&dev->qp_table.alloc, 2301 dev->limits.num_qps, 2302 (1 << 24) - 1, 2303 dev->qp_table.sqp_start + 2304 MTHCA_MAX_PORTS * 2); 2305 if (err) 2306 return err; 2307 2308 err = mthca_array_init(&dev->qp_table.qp, 2309 dev->limits.num_qps); 2310 if (err) { 2311 mthca_alloc_cleanup(&dev->qp_table.alloc); 2312 return err; 2313 } 2314 2315 for (i = 0; i < 2; ++i) { 2316 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI, 2317 dev->qp_table.sqp_start + i * 2, 2318 &status); 2319 if (err) 2320 goto err_out; 2321 if (status) { 2322 mthca_warn(dev, "CONF_SPECIAL_QP returned " 2323 "status %02x, aborting.\n", 2324 status); 2325 err = -EINVAL; 2326 goto err_out; 2327 } 2328 } 2329 return 0; 2330 2331 err_out: 2332 for (i = 0; i < 2; ++i) 2333 mthca_CONF_SPECIAL_QP(dev, i, 0, &status); 2334 2335 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps); 2336 mthca_alloc_cleanup(&dev->qp_table.alloc); 2337 2338 return err; 2339 } 2340 2341 void mthca_cleanup_qp_table(struct mthca_dev *dev) 2342 { 2343 int i; 2344 u8 status; 2345 2346 for (i = 0; i < 2; ++i) 2347 mthca_CONF_SPECIAL_QP(dev, i, 0, &status); 2348 2349 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps); 2350 mthca_alloc_cleanup(&dev->qp_table.alloc); 2351 } 2352