1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved. 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #include <linux/hardirq.h> 38 #include <linux/sched.h> 39 40 #include <asm/io.h> 41 42 #include <rdma/ib_pack.h> 43 44 #include "mthca_dev.h" 45 #include "mthca_cmd.h" 46 #include "mthca_memfree.h" 47 48 enum { 49 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE 50 }; 51 52 enum { 53 MTHCA_CQ_ENTRY_SIZE = 0x20 54 }; 55 56 enum { 57 MTHCA_ATOMIC_BYTE_LEN = 8 58 }; 59 60 /* 61 * Must be packed because start is 64 bits but only aligned to 32 bits. 62 */ 63 struct mthca_cq_context { 64 __be32 flags; 65 __be64 start; 66 __be32 logsize_usrpage; 67 __be32 error_eqn; /* Tavor only */ 68 __be32 comp_eqn; 69 __be32 pd; 70 __be32 lkey; 71 __be32 last_notified_index; 72 __be32 solicit_producer_index; 73 __be32 consumer_index; 74 __be32 producer_index; 75 __be32 cqn; 76 __be32 ci_db; /* Arbel only */ 77 __be32 state_db; /* Arbel only */ 78 u32 reserved; 79 } __attribute__((packed)); 80 81 #define MTHCA_CQ_STATUS_OK ( 0 << 28) 82 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28) 83 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28) 84 #define MTHCA_CQ_FLAG_TR ( 1 << 18) 85 #define MTHCA_CQ_FLAG_OI ( 1 << 17) 86 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8) 87 #define MTHCA_CQ_STATE_ARMED ( 1 << 8) 88 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8) 89 #define MTHCA_EQ_STATE_FIRED (10 << 8) 90 91 enum { 92 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe 93 }; 94 95 enum { 96 SYNDROME_LOCAL_LENGTH_ERR = 0x01, 97 SYNDROME_LOCAL_QP_OP_ERR = 0x02, 98 SYNDROME_LOCAL_EEC_OP_ERR = 0x03, 99 SYNDROME_LOCAL_PROT_ERR = 0x04, 100 SYNDROME_WR_FLUSH_ERR = 0x05, 101 SYNDROME_MW_BIND_ERR = 0x06, 102 SYNDROME_BAD_RESP_ERR = 0x10, 103 SYNDROME_LOCAL_ACCESS_ERR = 0x11, 104 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, 105 SYNDROME_REMOTE_ACCESS_ERR = 0x13, 106 SYNDROME_REMOTE_OP_ERR = 0x14, 107 SYNDROME_RETRY_EXC_ERR = 0x15, 108 SYNDROME_RNR_RETRY_EXC_ERR = 0x16, 109 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20, 110 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21, 111 SYNDROME_REMOTE_ABORTED_ERR = 0x22, 112 SYNDROME_INVAL_EECN_ERR = 0x23, 113 SYNDROME_INVAL_EEC_STATE_ERR = 0x24 114 }; 115 116 struct mthca_cqe { 117 __be32 my_qpn; 118 __be32 my_ee; 119 __be32 rqpn; 120 u8 sl_ipok; 121 u8 g_mlpath; 122 __be16 rlid; 123 __be32 imm_etype_pkey_eec; 124 __be32 byte_cnt; 125 __be32 wqe; 126 u8 opcode; 127 u8 is_send; 128 u8 reserved; 129 u8 owner; 130 }; 131 132 struct mthca_err_cqe { 133 __be32 my_qpn; 134 u32 reserved1[3]; 135 u8 syndrome; 136 u8 vendor_err; 137 __be16 db_cnt; 138 u32 reserved2; 139 __be32 wqe; 140 u8 opcode; 141 u8 reserved3[2]; 142 u8 owner; 143 }; 144 145 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7) 146 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7) 147 148 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24) 149 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24) 150 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24) 151 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24) 152 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24) 153 154 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24) 155 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24) 156 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24) 157 158 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf, 159 int entry) 160 { 161 if (buf->is_direct) 162 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE); 163 else 164 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf 165 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE; 166 } 167 168 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry) 169 { 170 return get_cqe_from_buf(&cq->buf, entry); 171 } 172 173 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe) 174 { 175 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe; 176 } 177 178 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq) 179 { 180 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe)); 181 } 182 183 static inline void set_cqe_hw(struct mthca_cqe *cqe) 184 { 185 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW; 186 } 187 188 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr) 189 { 190 __be32 *cqe = cqe_ptr; 191 192 (void) cqe; /* avoid warning if mthca_dbg compiled away... */ 193 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 194 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]), 195 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]), 196 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7])); 197 } 198 199 /* 200 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index 201 * should be correct before calling update_cons_index(). 202 */ 203 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 204 int incr) 205 { 206 if (mthca_is_memfree(dev)) { 207 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 208 wmb(); 209 } else { 210 mthca_write64(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn, incr - 1, 211 dev->kar + MTHCA_CQ_DOORBELL, 212 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 213 /* 214 * Make sure doorbells don't leak out of CQ spinlock 215 * and reach the HCA out of order: 216 */ 217 mmiowb(); 218 } 219 } 220 221 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn) 222 { 223 struct mthca_cq *cq; 224 225 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 226 227 if (!cq) { 228 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn); 229 return; 230 } 231 232 ++cq->arm_sn; 233 234 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 235 } 236 237 void mthca_cq_event(struct mthca_dev *dev, u32 cqn, 238 enum ib_event_type event_type) 239 { 240 struct mthca_cq *cq; 241 struct ib_event event; 242 243 spin_lock(&dev->cq_table.lock); 244 245 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 246 if (cq) 247 ++cq->refcount; 248 249 spin_unlock(&dev->cq_table.lock); 250 251 if (!cq) { 252 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn); 253 return; 254 } 255 256 event.device = &dev->ib_dev; 257 event.event = event_type; 258 event.element.cq = &cq->ibcq; 259 if (cq->ibcq.event_handler) 260 cq->ibcq.event_handler(&event, cq->ibcq.cq_context); 261 262 spin_lock(&dev->cq_table.lock); 263 if (!--cq->refcount) 264 wake_up(&cq->wait); 265 spin_unlock(&dev->cq_table.lock); 266 } 267 268 static inline int is_recv_cqe(struct mthca_cqe *cqe) 269 { 270 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 271 MTHCA_ERROR_CQE_OPCODE_MASK) 272 return !(cqe->opcode & 0x01); 273 else 274 return !(cqe->is_send & 0x80); 275 } 276 277 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn, 278 struct mthca_srq *srq) 279 { 280 struct mthca_cqe *cqe; 281 u32 prod_index; 282 int i, nfreed = 0; 283 284 spin_lock_irq(&cq->lock); 285 286 /* 287 * First we need to find the current producer index, so we 288 * know where to start cleaning from. It doesn't matter if HW 289 * adds new entries after this loop -- the QP we're worried 290 * about is already in RESET, so the new entries won't come 291 * from our QP and therefore don't need to be checked. 292 */ 293 for (prod_index = cq->cons_index; 294 cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe)); 295 ++prod_index) 296 if (prod_index == cq->cons_index + cq->ibcq.cqe) 297 break; 298 299 if (0) 300 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n", 301 qpn, cq->cqn, cq->cons_index, prod_index); 302 303 /* 304 * Now sweep backwards through the CQ, removing CQ entries 305 * that match our QP by copying older entries on top of them. 306 */ 307 while ((int) --prod_index - (int) cq->cons_index >= 0) { 308 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 309 if (cqe->my_qpn == cpu_to_be32(qpn)) { 310 if (srq && is_recv_cqe(cqe)) 311 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe)); 312 ++nfreed; 313 } else if (nfreed) 314 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe), 315 cqe, MTHCA_CQ_ENTRY_SIZE); 316 } 317 318 if (nfreed) { 319 for (i = 0; i < nfreed; ++i) 320 set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibcq.cqe)); 321 wmb(); 322 cq->cons_index += nfreed; 323 update_cons_index(dev, cq, nfreed); 324 } 325 326 spin_unlock_irq(&cq->lock); 327 } 328 329 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq) 330 { 331 int i; 332 333 /* 334 * In Tavor mode, the hardware keeps the consumer and producer 335 * indices mod the CQ size. Since we might be making the CQ 336 * bigger, we need to deal with the case where the producer 337 * index wrapped around before the CQ was resized. 338 */ 339 if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) && 340 cq->ibcq.cqe < cq->resize_buf->cqe) { 341 cq->cons_index &= cq->ibcq.cqe; 342 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe))) 343 cq->cons_index -= cq->ibcq.cqe + 1; 344 } 345 346 for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i) 347 memcpy(get_cqe_from_buf(&cq->resize_buf->buf, 348 i & cq->resize_buf->cqe), 349 get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE); 350 } 351 352 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent) 353 { 354 int ret; 355 int i; 356 357 ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE, 358 MTHCA_MAX_DIRECT_CQ_SIZE, 359 &buf->queue, &buf->is_direct, 360 &dev->driver_pd, 1, &buf->mr); 361 if (ret) 362 return ret; 363 364 for (i = 0; i < nent; ++i) 365 set_cqe_hw(get_cqe_from_buf(buf, i)); 366 367 return 0; 368 } 369 370 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe) 371 { 372 mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue, 373 buf->is_direct, &buf->mr); 374 } 375 376 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq, 377 struct mthca_qp *qp, int wqe_index, int is_send, 378 struct mthca_err_cqe *cqe, 379 struct ib_wc *entry, int *free_cqe) 380 { 381 int dbd; 382 __be32 new_wqe; 383 384 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { 385 mthca_dbg(dev, "local QP operation err " 386 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n", 387 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe), 388 cq->cqn, cq->cons_index); 389 dump_cqe(dev, cqe); 390 } 391 392 /* 393 * For completions in error, only work request ID, status, vendor error 394 * (and freed resource count for RD) have to be set. 395 */ 396 switch (cqe->syndrome) { 397 case SYNDROME_LOCAL_LENGTH_ERR: 398 entry->status = IB_WC_LOC_LEN_ERR; 399 break; 400 case SYNDROME_LOCAL_QP_OP_ERR: 401 entry->status = IB_WC_LOC_QP_OP_ERR; 402 break; 403 case SYNDROME_LOCAL_EEC_OP_ERR: 404 entry->status = IB_WC_LOC_EEC_OP_ERR; 405 break; 406 case SYNDROME_LOCAL_PROT_ERR: 407 entry->status = IB_WC_LOC_PROT_ERR; 408 break; 409 case SYNDROME_WR_FLUSH_ERR: 410 entry->status = IB_WC_WR_FLUSH_ERR; 411 break; 412 case SYNDROME_MW_BIND_ERR: 413 entry->status = IB_WC_MW_BIND_ERR; 414 break; 415 case SYNDROME_BAD_RESP_ERR: 416 entry->status = IB_WC_BAD_RESP_ERR; 417 break; 418 case SYNDROME_LOCAL_ACCESS_ERR: 419 entry->status = IB_WC_LOC_ACCESS_ERR; 420 break; 421 case SYNDROME_REMOTE_INVAL_REQ_ERR: 422 entry->status = IB_WC_REM_INV_REQ_ERR; 423 break; 424 case SYNDROME_REMOTE_ACCESS_ERR: 425 entry->status = IB_WC_REM_ACCESS_ERR; 426 break; 427 case SYNDROME_REMOTE_OP_ERR: 428 entry->status = IB_WC_REM_OP_ERR; 429 break; 430 case SYNDROME_RETRY_EXC_ERR: 431 entry->status = IB_WC_RETRY_EXC_ERR; 432 break; 433 case SYNDROME_RNR_RETRY_EXC_ERR: 434 entry->status = IB_WC_RNR_RETRY_EXC_ERR; 435 break; 436 case SYNDROME_LOCAL_RDD_VIOL_ERR: 437 entry->status = IB_WC_LOC_RDD_VIOL_ERR; 438 break; 439 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR: 440 entry->status = IB_WC_REM_INV_RD_REQ_ERR; 441 break; 442 case SYNDROME_REMOTE_ABORTED_ERR: 443 entry->status = IB_WC_REM_ABORT_ERR; 444 break; 445 case SYNDROME_INVAL_EECN_ERR: 446 entry->status = IB_WC_INV_EECN_ERR; 447 break; 448 case SYNDROME_INVAL_EEC_STATE_ERR: 449 entry->status = IB_WC_INV_EEC_STATE_ERR; 450 break; 451 default: 452 entry->status = IB_WC_GENERAL_ERR; 453 break; 454 } 455 456 entry->vendor_err = cqe->vendor_err; 457 458 /* 459 * Mem-free HCAs always generate one CQE per WQE, even in the 460 * error case, so we don't have to check the doorbell count, etc. 461 */ 462 if (mthca_is_memfree(dev)) 463 return; 464 465 mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe); 466 467 /* 468 * If we're at the end of the WQE chain, or we've used up our 469 * doorbell count, free the CQE. Otherwise just update it for 470 * the next poll operation. 471 */ 472 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd)) 473 return; 474 475 be16_add_cpu(&cqe->db_cnt, -dbd); 476 cqe->wqe = new_wqe; 477 cqe->syndrome = SYNDROME_WR_FLUSH_ERR; 478 479 *free_cqe = 0; 480 } 481 482 static inline int mthca_poll_one(struct mthca_dev *dev, 483 struct mthca_cq *cq, 484 struct mthca_qp **cur_qp, 485 int *freed, 486 struct ib_wc *entry) 487 { 488 struct mthca_wq *wq; 489 struct mthca_cqe *cqe; 490 int wqe_index; 491 int is_error; 492 int is_send; 493 int free_cqe = 1; 494 int err = 0; 495 u16 checksum; 496 497 cqe = next_cqe_sw(cq); 498 if (!cqe) 499 return -EAGAIN; 500 501 /* 502 * Make sure we read CQ entry contents after we've checked the 503 * ownership bit. 504 */ 505 rmb(); 506 507 if (0) { 508 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n", 509 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn), 510 be32_to_cpu(cqe->wqe)); 511 dump_cqe(dev, cqe); 512 } 513 514 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 515 MTHCA_ERROR_CQE_OPCODE_MASK; 516 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80; 517 518 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) { 519 /* 520 * We do not have to take the QP table lock here, 521 * because CQs will be locked while QPs are removed 522 * from the table. 523 */ 524 *cur_qp = mthca_array_get(&dev->qp_table.qp, 525 be32_to_cpu(cqe->my_qpn) & 526 (dev->limits.num_qps - 1)); 527 if (!*cur_qp) { 528 mthca_warn(dev, "CQ entry for unknown QP %06x\n", 529 be32_to_cpu(cqe->my_qpn) & 0xffffff); 530 err = -EINVAL; 531 goto out; 532 } 533 } 534 535 entry->qp = &(*cur_qp)->ibqp; 536 537 if (is_send) { 538 wq = &(*cur_qp)->sq; 539 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset) 540 >> wq->wqe_shift); 541 entry->wr_id = (*cur_qp)->wrid[wqe_index + 542 (*cur_qp)->rq.max]; 543 } else if ((*cur_qp)->ibqp.srq) { 544 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq); 545 u32 wqe = be32_to_cpu(cqe->wqe); 546 wq = NULL; 547 wqe_index = wqe >> srq->wqe_shift; 548 entry->wr_id = srq->wrid[wqe_index]; 549 mthca_free_srq_wqe(srq, wqe); 550 } else { 551 s32 wqe; 552 wq = &(*cur_qp)->rq; 553 wqe = be32_to_cpu(cqe->wqe); 554 wqe_index = wqe >> wq->wqe_shift; 555 /* 556 * WQE addr == base - 1 might be reported in receive completion 557 * with error instead of (rq size - 1) by Sinai FW 1.0.800 and 558 * Arbel FW 5.1.400. This bug should be fixed in later FW revs. 559 */ 560 if (unlikely(wqe_index < 0)) 561 wqe_index = wq->max - 1; 562 entry->wr_id = (*cur_qp)->wrid[wqe_index]; 563 } 564 565 if (wq) { 566 if (wq->last_comp < wqe_index) 567 wq->tail += wqe_index - wq->last_comp; 568 else 569 wq->tail += wqe_index + wq->max - wq->last_comp; 570 571 wq->last_comp = wqe_index; 572 } 573 574 if (is_error) { 575 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send, 576 (struct mthca_err_cqe *) cqe, 577 entry, &free_cqe); 578 goto out; 579 } 580 581 if (is_send) { 582 entry->wc_flags = 0; 583 switch (cqe->opcode) { 584 case MTHCA_OPCODE_RDMA_WRITE: 585 entry->opcode = IB_WC_RDMA_WRITE; 586 break; 587 case MTHCA_OPCODE_RDMA_WRITE_IMM: 588 entry->opcode = IB_WC_RDMA_WRITE; 589 entry->wc_flags |= IB_WC_WITH_IMM; 590 break; 591 case MTHCA_OPCODE_SEND: 592 entry->opcode = IB_WC_SEND; 593 break; 594 case MTHCA_OPCODE_SEND_IMM: 595 entry->opcode = IB_WC_SEND; 596 entry->wc_flags |= IB_WC_WITH_IMM; 597 break; 598 case MTHCA_OPCODE_RDMA_READ: 599 entry->opcode = IB_WC_RDMA_READ; 600 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 601 break; 602 case MTHCA_OPCODE_ATOMIC_CS: 603 entry->opcode = IB_WC_COMP_SWAP; 604 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 605 break; 606 case MTHCA_OPCODE_ATOMIC_FA: 607 entry->opcode = IB_WC_FETCH_ADD; 608 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 609 break; 610 case MTHCA_OPCODE_BIND_MW: 611 entry->opcode = IB_WC_BIND_MW; 612 break; 613 default: 614 entry->opcode = MTHCA_OPCODE_INVALID; 615 break; 616 } 617 } else { 618 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 619 switch (cqe->opcode & 0x1f) { 620 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE: 621 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE: 622 entry->wc_flags = IB_WC_WITH_IMM; 623 entry->ex.imm_data = cqe->imm_etype_pkey_eec; 624 entry->opcode = IB_WC_RECV; 625 break; 626 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: 627 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: 628 entry->wc_flags = IB_WC_WITH_IMM; 629 entry->ex.imm_data = cqe->imm_etype_pkey_eec; 630 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; 631 break; 632 default: 633 entry->wc_flags = 0; 634 entry->opcode = IB_WC_RECV; 635 break; 636 } 637 entry->slid = be16_to_cpu(cqe->rlid); 638 entry->sl = cqe->sl_ipok >> 4; 639 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff; 640 entry->dlid_path_bits = cqe->g_mlpath & 0x7f; 641 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16; 642 entry->wc_flags |= cqe->g_mlpath & 0x80 ? IB_WC_GRH : 0; 643 checksum = (be32_to_cpu(cqe->rqpn) >> 24) | 644 ((be32_to_cpu(cqe->my_ee) >> 16) & 0xff00); 645 entry->csum_ok = (cqe->sl_ipok & 1 && checksum == 0xffff); 646 } 647 648 entry->status = IB_WC_SUCCESS; 649 650 out: 651 if (likely(free_cqe)) { 652 set_cqe_hw(cqe); 653 ++(*freed); 654 ++cq->cons_index; 655 } 656 657 return err; 658 } 659 660 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 661 struct ib_wc *entry) 662 { 663 struct mthca_dev *dev = to_mdev(ibcq->device); 664 struct mthca_cq *cq = to_mcq(ibcq); 665 struct mthca_qp *qp = NULL; 666 unsigned long flags; 667 int err = 0; 668 int freed = 0; 669 int npolled; 670 671 spin_lock_irqsave(&cq->lock, flags); 672 673 npolled = 0; 674 repoll: 675 while (npolled < num_entries) { 676 err = mthca_poll_one(dev, cq, &qp, 677 &freed, entry + npolled); 678 if (err) 679 break; 680 ++npolled; 681 } 682 683 if (freed) { 684 wmb(); 685 update_cons_index(dev, cq, freed); 686 } 687 688 /* 689 * If a CQ resize is in progress and we discovered that the 690 * old buffer is empty, then peek in the new buffer, and if 691 * it's not empty, switch to the new buffer and continue 692 * polling there. 693 */ 694 if (unlikely(err == -EAGAIN && cq->resize_buf && 695 cq->resize_buf->state == CQ_RESIZE_READY)) { 696 /* 697 * In Tavor mode, the hardware keeps the producer 698 * index modulo the CQ size. Since we might be making 699 * the CQ bigger, we need to mask our consumer index 700 * using the size of the old CQ buffer before looking 701 * in the new CQ buffer. 702 */ 703 if (!mthca_is_memfree(dev)) 704 cq->cons_index &= cq->ibcq.cqe; 705 706 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf, 707 cq->cons_index & cq->resize_buf->cqe))) { 708 struct mthca_cq_buf tbuf; 709 int tcqe; 710 711 tbuf = cq->buf; 712 tcqe = cq->ibcq.cqe; 713 cq->buf = cq->resize_buf->buf; 714 cq->ibcq.cqe = cq->resize_buf->cqe; 715 716 cq->resize_buf->buf = tbuf; 717 cq->resize_buf->cqe = tcqe; 718 cq->resize_buf->state = CQ_RESIZE_SWAPPED; 719 720 goto repoll; 721 } 722 } 723 724 spin_unlock_irqrestore(&cq->lock, flags); 725 726 return err == 0 || err == -EAGAIN ? npolled : err; 727 } 728 729 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags) 730 { 731 u32 dbhi = ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 732 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 733 MTHCA_TAVOR_CQ_DB_REQ_NOT) | 734 to_mcq(cq)->cqn; 735 736 mthca_write64(dbhi, 0xffffffff, to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 737 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock)); 738 739 return 0; 740 } 741 742 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 743 { 744 struct mthca_cq *cq = to_mcq(ibcq); 745 __be32 db_rec[2]; 746 u32 dbhi; 747 u32 sn = cq->arm_sn & 3; 748 749 db_rec[0] = cpu_to_be32(cq->cons_index); 750 db_rec[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) | 751 ((flags & IB_CQ_SOLICITED_MASK) == 752 IB_CQ_SOLICITED ? 1 : 2)); 753 754 mthca_write_db_rec(db_rec, cq->arm_db); 755 756 /* 757 * Make sure that the doorbell record in host memory is 758 * written before ringing the doorbell via PCI MMIO. 759 */ 760 wmb(); 761 762 dbhi = (sn << 28) | 763 ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 764 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL : 765 MTHCA_ARBEL_CQ_DB_REQ_NOT) | cq->cqn; 766 767 mthca_write64(dbhi, cq->cons_index, 768 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL, 769 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock)); 770 771 return 0; 772 } 773 774 int mthca_init_cq(struct mthca_dev *dev, int nent, 775 struct mthca_ucontext *ctx, u32 pdn, 776 struct mthca_cq *cq) 777 { 778 struct mthca_mailbox *mailbox; 779 struct mthca_cq_context *cq_context; 780 int err = -ENOMEM; 781 u8 status; 782 783 cq->ibcq.cqe = nent - 1; 784 cq->is_kernel = !ctx; 785 786 cq->cqn = mthca_alloc(&dev->cq_table.alloc); 787 if (cq->cqn == -1) 788 return -ENOMEM; 789 790 if (mthca_is_memfree(dev)) { 791 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn); 792 if (err) 793 goto err_out; 794 795 if (cq->is_kernel) { 796 cq->arm_sn = 1; 797 798 err = -ENOMEM; 799 800 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, 801 cq->cqn, &cq->set_ci_db); 802 if (cq->set_ci_db_index < 0) 803 goto err_out_icm; 804 805 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM, 806 cq->cqn, &cq->arm_db); 807 if (cq->arm_db_index < 0) 808 goto err_out_ci; 809 } 810 } 811 812 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 813 if (IS_ERR(mailbox)) 814 goto err_out_arm; 815 816 cq_context = mailbox->buf; 817 818 if (cq->is_kernel) { 819 err = mthca_alloc_cq_buf(dev, &cq->buf, nent); 820 if (err) 821 goto err_out_mailbox; 822 } 823 824 spin_lock_init(&cq->lock); 825 cq->refcount = 1; 826 init_waitqueue_head(&cq->wait); 827 mutex_init(&cq->mutex); 828 829 memset(cq_context, 0, sizeof *cq_context); 830 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK | 831 MTHCA_CQ_STATE_DISARMED | 832 MTHCA_CQ_FLAG_TR); 833 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24); 834 if (ctx) 835 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index); 836 else 837 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); 838 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn); 839 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn); 840 cq_context->pd = cpu_to_be32(pdn); 841 cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey); 842 cq_context->cqn = cpu_to_be32(cq->cqn); 843 844 if (mthca_is_memfree(dev)) { 845 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index); 846 cq_context->state_db = cpu_to_be32(cq->arm_db_index); 847 } 848 849 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status); 850 if (err) { 851 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err); 852 goto err_out_free_mr; 853 } 854 855 if (status) { 856 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n", 857 status); 858 err = -EINVAL; 859 goto err_out_free_mr; 860 } 861 862 spin_lock_irq(&dev->cq_table.lock); 863 if (mthca_array_set(&dev->cq_table.cq, 864 cq->cqn & (dev->limits.num_cqs - 1), 865 cq)) { 866 spin_unlock_irq(&dev->cq_table.lock); 867 goto err_out_free_mr; 868 } 869 spin_unlock_irq(&dev->cq_table.lock); 870 871 cq->cons_index = 0; 872 873 mthca_free_mailbox(dev, mailbox); 874 875 return 0; 876 877 err_out_free_mr: 878 if (cq->is_kernel) 879 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 880 881 err_out_mailbox: 882 mthca_free_mailbox(dev, mailbox); 883 884 err_out_arm: 885 if (cq->is_kernel && mthca_is_memfree(dev)) 886 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 887 888 err_out_ci: 889 if (cq->is_kernel && mthca_is_memfree(dev)) 890 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 891 892 err_out_icm: 893 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 894 895 err_out: 896 mthca_free(&dev->cq_table.alloc, cq->cqn); 897 898 return err; 899 } 900 901 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq) 902 { 903 int c; 904 905 spin_lock_irq(&dev->cq_table.lock); 906 c = cq->refcount; 907 spin_unlock_irq(&dev->cq_table.lock); 908 909 return c; 910 } 911 912 void mthca_free_cq(struct mthca_dev *dev, 913 struct mthca_cq *cq) 914 { 915 struct mthca_mailbox *mailbox; 916 int err; 917 u8 status; 918 919 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 920 if (IS_ERR(mailbox)) { 921 mthca_warn(dev, "No memory for mailbox to free CQ.\n"); 922 return; 923 } 924 925 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status); 926 if (err) 927 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err); 928 else if (status) 929 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status); 930 931 if (0) { 932 __be32 *ctx = mailbox->buf; 933 int j; 934 935 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n", 936 cq->cqn, cq->cons_index, 937 cq->is_kernel ? !!next_cqe_sw(cq) : 0); 938 for (j = 0; j < 16; ++j) 939 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j])); 940 } 941 942 spin_lock_irq(&dev->cq_table.lock); 943 mthca_array_clear(&dev->cq_table.cq, 944 cq->cqn & (dev->limits.num_cqs - 1)); 945 --cq->refcount; 946 spin_unlock_irq(&dev->cq_table.lock); 947 948 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) 949 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector); 950 else 951 synchronize_irq(dev->pdev->irq); 952 953 wait_event(cq->wait, !get_cq_refcount(dev, cq)); 954 955 if (cq->is_kernel) { 956 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 957 if (mthca_is_memfree(dev)) { 958 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 959 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 960 } 961 } 962 963 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 964 mthca_free(&dev->cq_table.alloc, cq->cqn); 965 mthca_free_mailbox(dev, mailbox); 966 } 967 968 int mthca_init_cq_table(struct mthca_dev *dev) 969 { 970 int err; 971 972 spin_lock_init(&dev->cq_table.lock); 973 974 err = mthca_alloc_init(&dev->cq_table.alloc, 975 dev->limits.num_cqs, 976 (1 << 24) - 1, 977 dev->limits.reserved_cqs); 978 if (err) 979 return err; 980 981 err = mthca_array_init(&dev->cq_table.cq, 982 dev->limits.num_cqs); 983 if (err) 984 mthca_alloc_cleanup(&dev->cq_table.alloc); 985 986 return err; 987 } 988 989 void mthca_cleanup_cq_table(struct mthca_dev *dev) 990 { 991 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs); 992 mthca_alloc_cleanup(&dev->cq_table.alloc); 993 } 994