1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include "mlx5_ib.h" 38 39 /* not supported currently */ 40 static int wq_signature; 41 42 enum { 43 MLX5_IB_ACK_REQ_FREQ = 8, 44 }; 45 46 enum { 47 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 48 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 49 MLX5_IB_LINK_TYPE_IB = 0, 50 MLX5_IB_LINK_TYPE_ETH = 1 51 }; 52 53 enum { 54 MLX5_IB_SQ_STRIDE = 6, 55 }; 56 57 static const u32 mlx5_ib_opcode[] = { 58 [IB_WR_SEND] = MLX5_OPCODE_SEND, 59 [IB_WR_LSO] = MLX5_OPCODE_LSO, 60 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 61 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 62 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 63 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 64 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 65 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 66 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 67 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 68 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 69 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 70 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 71 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 72 }; 73 74 struct mlx5_wqe_eth_pad { 75 u8 rsvd0[16]; 76 }; 77 78 enum raw_qp_set_mask_map { 79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 80 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 81 }; 82 83 struct mlx5_modify_raw_qp_param { 84 u16 operation; 85 86 u32 set_mask; /* raw_qp_set_mask_map */ 87 u32 rate_limit; 88 u8 rq_q_ctr_id; 89 }; 90 91 static void get_cqs(enum ib_qp_type qp_type, 92 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 93 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 94 95 static int is_qp0(enum ib_qp_type qp_type) 96 { 97 return qp_type == IB_QPT_SMI; 98 } 99 100 static int is_sqp(enum ib_qp_type qp_type) 101 { 102 return is_qp0(qp_type) || is_qp1(qp_type); 103 } 104 105 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 106 { 107 return mlx5_buf_offset(&qp->buf, offset); 108 } 109 110 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 111 { 112 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 113 } 114 115 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 116 { 117 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 118 } 119 120 /** 121 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 122 * 123 * @qp: QP to copy from. 124 * @send: copy from the send queue when non-zero, use the receive queue 125 * otherwise. 126 * @wqe_index: index to start copying from. For send work queues, the 127 * wqe_index is in units of MLX5_SEND_WQE_BB. 128 * For receive work queue, it is the number of work queue 129 * element in the queue. 130 * @buffer: destination buffer. 131 * @length: maximum number of bytes to copy. 132 * 133 * Copies at least a single WQE, but may copy more data. 134 * 135 * Return: the number of bytes copied, or an error code. 136 */ 137 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 138 void *buffer, u32 length, 139 struct mlx5_ib_qp_base *base) 140 { 141 struct ib_device *ibdev = qp->ibqp.device; 142 struct mlx5_ib_dev *dev = to_mdev(ibdev); 143 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 144 size_t offset; 145 size_t wq_end; 146 struct ib_umem *umem = base->ubuffer.umem; 147 u32 first_copy_length; 148 int wqe_length; 149 int ret; 150 151 if (wq->wqe_cnt == 0) { 152 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 153 qp->ibqp.qp_type); 154 return -EINVAL; 155 } 156 157 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 158 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 159 160 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 161 return -EINVAL; 162 163 if (offset > umem->length || 164 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 165 return -EINVAL; 166 167 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 168 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 169 if (ret) 170 return ret; 171 172 if (send) { 173 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 174 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 175 176 wqe_length = ds * MLX5_WQE_DS_UNITS; 177 } else { 178 wqe_length = 1 << wq->wqe_shift; 179 } 180 181 if (wqe_length <= first_copy_length) 182 return first_copy_length; 183 184 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 185 wqe_length - first_copy_length); 186 if (ret) 187 return ret; 188 189 return wqe_length; 190 } 191 192 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 193 { 194 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 195 struct ib_event event; 196 197 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 198 /* This event is only valid for trans_qps */ 199 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 200 } 201 202 if (ibqp->event_handler) { 203 event.device = ibqp->device; 204 event.element.qp = ibqp; 205 switch (type) { 206 case MLX5_EVENT_TYPE_PATH_MIG: 207 event.event = IB_EVENT_PATH_MIG; 208 break; 209 case MLX5_EVENT_TYPE_COMM_EST: 210 event.event = IB_EVENT_COMM_EST; 211 break; 212 case MLX5_EVENT_TYPE_SQ_DRAINED: 213 event.event = IB_EVENT_SQ_DRAINED; 214 break; 215 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 216 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 217 break; 218 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 219 event.event = IB_EVENT_QP_FATAL; 220 break; 221 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 222 event.event = IB_EVENT_PATH_MIG_ERR; 223 break; 224 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 225 event.event = IB_EVENT_QP_REQ_ERR; 226 break; 227 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 228 event.event = IB_EVENT_QP_ACCESS_ERR; 229 break; 230 default: 231 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 232 return; 233 } 234 235 ibqp->event_handler(&event, ibqp->qp_context); 236 } 237 } 238 239 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 240 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 241 { 242 int wqe_size; 243 int wq_size; 244 245 /* Sanity check RQ size before proceeding */ 246 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 247 return -EINVAL; 248 249 if (!has_rq) { 250 qp->rq.max_gs = 0; 251 qp->rq.wqe_cnt = 0; 252 qp->rq.wqe_shift = 0; 253 cap->max_recv_wr = 0; 254 cap->max_recv_sge = 0; 255 } else { 256 if (ucmd) { 257 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 258 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 259 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 260 qp->rq.max_post = qp->rq.wqe_cnt; 261 } else { 262 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 263 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 264 wqe_size = roundup_pow_of_two(wqe_size); 265 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 266 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 267 qp->rq.wqe_cnt = wq_size / wqe_size; 268 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 269 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 270 wqe_size, 271 MLX5_CAP_GEN(dev->mdev, 272 max_wqe_sz_rq)); 273 return -EINVAL; 274 } 275 qp->rq.wqe_shift = ilog2(wqe_size); 276 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 277 qp->rq.max_post = qp->rq.wqe_cnt; 278 } 279 } 280 281 return 0; 282 } 283 284 static int sq_overhead(struct ib_qp_init_attr *attr) 285 { 286 int size = 0; 287 288 switch (attr->qp_type) { 289 case IB_QPT_XRC_INI: 290 size += sizeof(struct mlx5_wqe_xrc_seg); 291 /* fall through */ 292 case IB_QPT_RC: 293 size += sizeof(struct mlx5_wqe_ctrl_seg) + 294 max(sizeof(struct mlx5_wqe_atomic_seg) + 295 sizeof(struct mlx5_wqe_raddr_seg), 296 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 297 sizeof(struct mlx5_mkey_seg)); 298 break; 299 300 case IB_QPT_XRC_TGT: 301 return 0; 302 303 case IB_QPT_UC: 304 size += sizeof(struct mlx5_wqe_ctrl_seg) + 305 max(sizeof(struct mlx5_wqe_raddr_seg), 306 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 307 sizeof(struct mlx5_mkey_seg)); 308 break; 309 310 case IB_QPT_UD: 311 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 312 size += sizeof(struct mlx5_wqe_eth_pad) + 313 sizeof(struct mlx5_wqe_eth_seg); 314 /* fall through */ 315 case IB_QPT_SMI: 316 case MLX5_IB_QPT_HW_GSI: 317 size += sizeof(struct mlx5_wqe_ctrl_seg) + 318 sizeof(struct mlx5_wqe_datagram_seg); 319 break; 320 321 case MLX5_IB_QPT_REG_UMR: 322 size += sizeof(struct mlx5_wqe_ctrl_seg) + 323 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 324 sizeof(struct mlx5_mkey_seg); 325 break; 326 327 default: 328 return -EINVAL; 329 } 330 331 return size; 332 } 333 334 static int calc_send_wqe(struct ib_qp_init_attr *attr) 335 { 336 int inl_size = 0; 337 int size; 338 339 size = sq_overhead(attr); 340 if (size < 0) 341 return size; 342 343 if (attr->cap.max_inline_data) { 344 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 345 attr->cap.max_inline_data; 346 } 347 348 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 349 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 350 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 351 return MLX5_SIG_WQE_SIZE; 352 else 353 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 354 } 355 356 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 357 { 358 int max_sge; 359 360 if (attr->qp_type == IB_QPT_RC) 361 max_sge = (min_t(int, wqe_size, 512) - 362 sizeof(struct mlx5_wqe_ctrl_seg) - 363 sizeof(struct mlx5_wqe_raddr_seg)) / 364 sizeof(struct mlx5_wqe_data_seg); 365 else if (attr->qp_type == IB_QPT_XRC_INI) 366 max_sge = (min_t(int, wqe_size, 512) - 367 sizeof(struct mlx5_wqe_ctrl_seg) - 368 sizeof(struct mlx5_wqe_xrc_seg) - 369 sizeof(struct mlx5_wqe_raddr_seg)) / 370 sizeof(struct mlx5_wqe_data_seg); 371 else 372 max_sge = (wqe_size - sq_overhead(attr)) / 373 sizeof(struct mlx5_wqe_data_seg); 374 375 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 376 sizeof(struct mlx5_wqe_data_seg)); 377 } 378 379 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 380 struct mlx5_ib_qp *qp) 381 { 382 int wqe_size; 383 int wq_size; 384 385 if (!attr->cap.max_send_wr) 386 return 0; 387 388 wqe_size = calc_send_wqe(attr); 389 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 390 if (wqe_size < 0) 391 return wqe_size; 392 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 394 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 395 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 396 return -EINVAL; 397 } 398 399 qp->max_inline_data = wqe_size - sq_overhead(attr) - 400 sizeof(struct mlx5_wqe_inline_seg); 401 attr->cap.max_inline_data = qp->max_inline_data; 402 403 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 404 qp->signature_en = true; 405 406 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 407 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 408 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 409 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 410 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 411 qp->sq.wqe_cnt, 412 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 413 return -ENOMEM; 414 } 415 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 416 qp->sq.max_gs = get_send_sge(attr, wqe_size); 417 if (qp->sq.max_gs < attr->cap.max_send_sge) 418 return -ENOMEM; 419 420 attr->cap.max_send_sge = qp->sq.max_gs; 421 qp->sq.max_post = wq_size / wqe_size; 422 attr->cap.max_send_wr = qp->sq.max_post; 423 424 return wq_size; 425 } 426 427 static int set_user_buf_size(struct mlx5_ib_dev *dev, 428 struct mlx5_ib_qp *qp, 429 struct mlx5_ib_create_qp *ucmd, 430 struct mlx5_ib_qp_base *base, 431 struct ib_qp_init_attr *attr) 432 { 433 int desc_sz = 1 << qp->sq.wqe_shift; 434 435 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 436 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 437 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 438 return -EINVAL; 439 } 440 441 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 442 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 443 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 444 return -EINVAL; 445 } 446 447 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 448 449 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 450 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 451 qp->sq.wqe_cnt, 452 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 453 return -EINVAL; 454 } 455 456 if (attr->qp_type == IB_QPT_RAW_PACKET) { 457 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 458 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 459 } else { 460 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 461 (qp->sq.wqe_cnt << 6); 462 } 463 464 return 0; 465 } 466 467 static int qp_has_rq(struct ib_qp_init_attr *attr) 468 { 469 if (attr->qp_type == IB_QPT_XRC_INI || 470 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 471 attr->qp_type == MLX5_IB_QPT_REG_UMR || 472 !attr->cap.max_recv_wr) 473 return 0; 474 475 return 1; 476 } 477 478 static int first_med_uuar(void) 479 { 480 return 1; 481 } 482 483 static int next_uuar(int n) 484 { 485 n++; 486 487 while (((n % 4) & 2)) 488 n++; 489 490 return n; 491 } 492 493 static int num_med_uuar(struct mlx5_uuar_info *uuari) 494 { 495 int n; 496 497 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 498 uuari->num_low_latency_uuars - 1; 499 500 return n >= 0 ? n : 0; 501 } 502 503 static int max_uuari(struct mlx5_uuar_info *uuari) 504 { 505 return uuari->num_uars * 4; 506 } 507 508 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 509 { 510 int med; 511 int i; 512 int t; 513 514 med = num_med_uuar(uuari); 515 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 516 t++; 517 if (t == med) 518 return next_uuar(i); 519 } 520 521 return 0; 522 } 523 524 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 525 { 526 int i; 527 528 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 529 if (!test_bit(i, uuari->bitmap)) { 530 set_bit(i, uuari->bitmap); 531 uuari->count[i]++; 532 return i; 533 } 534 } 535 536 return -ENOMEM; 537 } 538 539 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 540 { 541 int minidx = first_med_uuar(); 542 int i; 543 544 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 545 if (uuari->count[i] < uuari->count[minidx]) 546 minidx = i; 547 } 548 549 uuari->count[minidx]++; 550 return minidx; 551 } 552 553 static int alloc_uuar(struct mlx5_uuar_info *uuari, 554 enum mlx5_ib_latency_class lat) 555 { 556 int uuarn = -EINVAL; 557 558 mutex_lock(&uuari->lock); 559 switch (lat) { 560 case MLX5_IB_LATENCY_CLASS_LOW: 561 uuarn = 0; 562 uuari->count[uuarn]++; 563 break; 564 565 case MLX5_IB_LATENCY_CLASS_MEDIUM: 566 if (uuari->ver < 2) 567 uuarn = -ENOMEM; 568 else 569 uuarn = alloc_med_class_uuar(uuari); 570 break; 571 572 case MLX5_IB_LATENCY_CLASS_HIGH: 573 if (uuari->ver < 2) 574 uuarn = -ENOMEM; 575 else 576 uuarn = alloc_high_class_uuar(uuari); 577 break; 578 579 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 580 uuarn = 2; 581 break; 582 } 583 mutex_unlock(&uuari->lock); 584 585 return uuarn; 586 } 587 588 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 589 { 590 clear_bit(uuarn, uuari->bitmap); 591 --uuari->count[uuarn]; 592 } 593 594 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 595 { 596 clear_bit(uuarn, uuari->bitmap); 597 --uuari->count[uuarn]; 598 } 599 600 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 601 { 602 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 603 int high_uuar = nuuars - uuari->num_low_latency_uuars; 604 605 mutex_lock(&uuari->lock); 606 if (uuarn == 0) { 607 --uuari->count[uuarn]; 608 goto out; 609 } 610 611 if (uuarn < high_uuar) { 612 free_med_class_uuar(uuari, uuarn); 613 goto out; 614 } 615 616 free_high_class_uuar(uuari, uuarn); 617 618 out: 619 mutex_unlock(&uuari->lock); 620 } 621 622 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 623 { 624 switch (state) { 625 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 626 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 627 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 628 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 629 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 630 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 631 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 632 default: return -1; 633 } 634 } 635 636 static int to_mlx5_st(enum ib_qp_type type) 637 { 638 switch (type) { 639 case IB_QPT_RC: return MLX5_QP_ST_RC; 640 case IB_QPT_UC: return MLX5_QP_ST_UC; 641 case IB_QPT_UD: return MLX5_QP_ST_UD; 642 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 643 case IB_QPT_XRC_INI: 644 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 645 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 646 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 647 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 648 case IB_QPT_RAW_PACKET: 649 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 650 case IB_QPT_MAX: 651 default: return -EINVAL; 652 } 653 } 654 655 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 656 struct mlx5_ib_cq *recv_cq); 657 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 658 struct mlx5_ib_cq *recv_cq); 659 660 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 661 { 662 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 663 } 664 665 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 666 struct ib_pd *pd, 667 unsigned long addr, size_t size, 668 struct ib_umem **umem, 669 int *npages, int *page_shift, int *ncont, 670 u32 *offset) 671 { 672 int err; 673 674 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 675 if (IS_ERR(*umem)) { 676 mlx5_ib_dbg(dev, "umem_get failed\n"); 677 return PTR_ERR(*umem); 678 } 679 680 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 681 682 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 683 if (err) { 684 mlx5_ib_warn(dev, "bad offset\n"); 685 goto err_umem; 686 } 687 688 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 689 addr, size, *npages, *page_shift, *ncont, *offset); 690 691 return 0; 692 693 err_umem: 694 ib_umem_release(*umem); 695 *umem = NULL; 696 697 return err; 698 } 699 700 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq) 701 { 702 struct mlx5_ib_ucontext *context; 703 704 context = to_mucontext(pd->uobject->context); 705 mlx5_ib_db_unmap_user(context, &rwq->db); 706 if (rwq->umem) 707 ib_umem_release(rwq->umem); 708 } 709 710 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 711 struct mlx5_ib_rwq *rwq, 712 struct mlx5_ib_create_wq *ucmd) 713 { 714 struct mlx5_ib_ucontext *context; 715 int page_shift = 0; 716 int npages; 717 u32 offset = 0; 718 int ncont = 0; 719 int err; 720 721 if (!ucmd->buf_addr) 722 return -EINVAL; 723 724 context = to_mucontext(pd->uobject->context); 725 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 726 rwq->buf_size, 0, 0); 727 if (IS_ERR(rwq->umem)) { 728 mlx5_ib_dbg(dev, "umem_get failed\n"); 729 err = PTR_ERR(rwq->umem); 730 return err; 731 } 732 733 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 734 &ncont, NULL); 735 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 736 &rwq->rq_page_offset); 737 if (err) { 738 mlx5_ib_warn(dev, "bad offset\n"); 739 goto err_umem; 740 } 741 742 rwq->rq_num_pas = ncont; 743 rwq->page_shift = page_shift; 744 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 745 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 746 747 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 748 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 749 npages, page_shift, ncont, offset); 750 751 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 752 if (err) { 753 mlx5_ib_dbg(dev, "map failed\n"); 754 goto err_umem; 755 } 756 757 rwq->create_type = MLX5_WQ_USER; 758 return 0; 759 760 err_umem: 761 ib_umem_release(rwq->umem); 762 return err; 763 } 764 765 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 766 struct mlx5_ib_qp *qp, struct ib_udata *udata, 767 struct ib_qp_init_attr *attr, 768 u32 **in, 769 struct mlx5_ib_create_qp_resp *resp, int *inlen, 770 struct mlx5_ib_qp_base *base) 771 { 772 struct mlx5_ib_ucontext *context; 773 struct mlx5_ib_create_qp ucmd; 774 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 775 int page_shift = 0; 776 int uar_index; 777 int npages; 778 u32 offset = 0; 779 int uuarn; 780 int ncont = 0; 781 __be64 *pas; 782 void *qpc; 783 int err; 784 785 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 786 if (err) { 787 mlx5_ib_dbg(dev, "copy failed\n"); 788 return err; 789 } 790 791 context = to_mucontext(pd->uobject->context); 792 /* 793 * TBD: should come from the verbs when we have the API 794 */ 795 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 796 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 797 uuarn = MLX5_CROSS_CHANNEL_UUAR; 798 else { 799 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 800 if (uuarn < 0) { 801 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 802 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 803 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 804 if (uuarn < 0) { 805 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 806 mlx5_ib_dbg(dev, "reverting to high latency\n"); 807 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 808 if (uuarn < 0) { 809 mlx5_ib_warn(dev, "uuar allocation failed\n"); 810 return uuarn; 811 } 812 } 813 } 814 } 815 816 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 817 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 818 819 qp->rq.offset = 0; 820 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 821 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 822 823 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 824 if (err) 825 goto err_uuar; 826 827 if (ucmd.buf_addr && ubuffer->buf_size) { 828 ubuffer->buf_addr = ucmd.buf_addr; 829 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 830 ubuffer->buf_size, 831 &ubuffer->umem, &npages, &page_shift, 832 &ncont, &offset); 833 if (err) 834 goto err_uuar; 835 } else { 836 ubuffer->umem = NULL; 837 } 838 839 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 840 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 841 *in = mlx5_vzalloc(*inlen); 842 if (!*in) { 843 err = -ENOMEM; 844 goto err_umem; 845 } 846 847 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 848 if (ubuffer->umem) 849 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 850 851 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 852 853 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 854 MLX5_SET(qpc, qpc, page_offset, offset); 855 856 MLX5_SET(qpc, qpc, uar_page, uar_index); 857 resp->uuar_index = uuarn; 858 qp->uuarn = uuarn; 859 860 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 861 if (err) { 862 mlx5_ib_dbg(dev, "map failed\n"); 863 goto err_free; 864 } 865 866 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 867 if (err) { 868 mlx5_ib_dbg(dev, "copy failed\n"); 869 goto err_unmap; 870 } 871 qp->create_type = MLX5_QP_USER; 872 873 return 0; 874 875 err_unmap: 876 mlx5_ib_db_unmap_user(context, &qp->db); 877 878 err_free: 879 kvfree(*in); 880 881 err_umem: 882 if (ubuffer->umem) 883 ib_umem_release(ubuffer->umem); 884 885 err_uuar: 886 free_uuar(&context->uuari, uuarn); 887 return err; 888 } 889 890 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp, 891 struct mlx5_ib_qp_base *base) 892 { 893 struct mlx5_ib_ucontext *context; 894 895 context = to_mucontext(pd->uobject->context); 896 mlx5_ib_db_unmap_user(context, &qp->db); 897 if (base->ubuffer.umem) 898 ib_umem_release(base->ubuffer.umem); 899 free_uuar(&context->uuari, qp->uuarn); 900 } 901 902 static int create_kernel_qp(struct mlx5_ib_dev *dev, 903 struct ib_qp_init_attr *init_attr, 904 struct mlx5_ib_qp *qp, 905 u32 **in, int *inlen, 906 struct mlx5_ib_qp_base *base) 907 { 908 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 909 struct mlx5_uuar_info *uuari; 910 int uar_index; 911 void *qpc; 912 int uuarn; 913 int err; 914 915 uuari = &dev->mdev->priv.uuari; 916 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 917 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 918 IB_QP_CREATE_IPOIB_UD_LSO | 919 mlx5_ib_create_qp_sqpn_qp1())) 920 return -EINVAL; 921 922 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 923 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 924 925 uuarn = alloc_uuar(uuari, lc); 926 if (uuarn < 0) { 927 mlx5_ib_dbg(dev, "\n"); 928 return -ENOMEM; 929 } 930 931 qp->bf = &uuari->bfs[uuarn]; 932 uar_index = qp->bf->uar->index; 933 934 err = calc_sq_size(dev, init_attr, qp); 935 if (err < 0) { 936 mlx5_ib_dbg(dev, "err %d\n", err); 937 goto err_uuar; 938 } 939 940 qp->rq.offset = 0; 941 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 942 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 943 944 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 945 if (err) { 946 mlx5_ib_dbg(dev, "err %d\n", err); 947 goto err_uuar; 948 } 949 950 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 951 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 952 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 953 *in = mlx5_vzalloc(*inlen); 954 if (!*in) { 955 err = -ENOMEM; 956 goto err_buf; 957 } 958 959 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 960 MLX5_SET(qpc, qpc, uar_page, uar_index); 961 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 962 963 /* Set "fast registration enabled" for all kernel QPs */ 964 MLX5_SET(qpc, qpc, fre, 1); 965 MLX5_SET(qpc, qpc, rlky, 1); 966 967 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 968 MLX5_SET(qpc, qpc, deth_sqpn, 1); 969 qp->flags |= MLX5_IB_QP_SQPN_QP1; 970 } 971 972 mlx5_fill_page_array(&qp->buf, 973 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 974 975 err = mlx5_db_alloc(dev->mdev, &qp->db); 976 if (err) { 977 mlx5_ib_dbg(dev, "err %d\n", err); 978 goto err_free; 979 } 980 981 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 982 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 983 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 984 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 985 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 986 987 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 988 !qp->sq.w_list || !qp->sq.wqe_head) { 989 err = -ENOMEM; 990 goto err_wrid; 991 } 992 qp->create_type = MLX5_QP_KERNEL; 993 994 return 0; 995 996 err_wrid: 997 mlx5_db_free(dev->mdev, &qp->db); 998 kfree(qp->sq.wqe_head); 999 kfree(qp->sq.w_list); 1000 kfree(qp->sq.wrid); 1001 kfree(qp->sq.wr_data); 1002 kfree(qp->rq.wrid); 1003 1004 err_free: 1005 kvfree(*in); 1006 1007 err_buf: 1008 mlx5_buf_free(dev->mdev, &qp->buf); 1009 1010 err_uuar: 1011 free_uuar(&dev->mdev->priv.uuari, uuarn); 1012 return err; 1013 } 1014 1015 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1016 { 1017 mlx5_db_free(dev->mdev, &qp->db); 1018 kfree(qp->sq.wqe_head); 1019 kfree(qp->sq.w_list); 1020 kfree(qp->sq.wrid); 1021 kfree(qp->sq.wr_data); 1022 kfree(qp->rq.wrid); 1023 mlx5_buf_free(dev->mdev, &qp->buf); 1024 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn); 1025 } 1026 1027 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1028 { 1029 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1030 (attr->qp_type == IB_QPT_XRC_INI)) 1031 return MLX5_SRQ_RQ; 1032 else if (!qp->has_rq) 1033 return MLX5_ZERO_LEN_RQ; 1034 else 1035 return MLX5_NON_ZERO_RQ; 1036 } 1037 1038 static int is_connected(enum ib_qp_type qp_type) 1039 { 1040 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1041 return 1; 1042 1043 return 0; 1044 } 1045 1046 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1047 struct mlx5_ib_sq *sq, u32 tdn) 1048 { 1049 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1050 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1051 1052 MLX5_SET(tisc, tisc, transport_domain, tdn); 1053 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1054 } 1055 1056 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1057 struct mlx5_ib_sq *sq) 1058 { 1059 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1060 } 1061 1062 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1063 struct mlx5_ib_sq *sq, void *qpin, 1064 struct ib_pd *pd) 1065 { 1066 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1067 __be64 *pas; 1068 void *in; 1069 void *sqc; 1070 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1071 void *wq; 1072 int inlen; 1073 int err; 1074 int page_shift = 0; 1075 int npages; 1076 int ncont = 0; 1077 u32 offset = 0; 1078 1079 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1080 &sq->ubuffer.umem, &npages, &page_shift, 1081 &ncont, &offset); 1082 if (err) 1083 return err; 1084 1085 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1086 in = mlx5_vzalloc(inlen); 1087 if (!in) { 1088 err = -ENOMEM; 1089 goto err_umem; 1090 } 1091 1092 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1093 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1094 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1095 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1096 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1097 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1098 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1099 1100 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1101 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1102 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1103 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1104 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1105 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1106 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1107 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1108 MLX5_SET(wq, wq, page_offset, offset); 1109 1110 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1111 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1112 1113 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1114 1115 kvfree(in); 1116 1117 if (err) 1118 goto err_umem; 1119 1120 return 0; 1121 1122 err_umem: 1123 ib_umem_release(sq->ubuffer.umem); 1124 sq->ubuffer.umem = NULL; 1125 1126 return err; 1127 } 1128 1129 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1130 struct mlx5_ib_sq *sq) 1131 { 1132 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1133 ib_umem_release(sq->ubuffer.umem); 1134 } 1135 1136 static int get_rq_pas_size(void *qpc) 1137 { 1138 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1139 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1140 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1141 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1142 u32 po_quanta = 1 << (log_page_size - 6); 1143 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1144 u32 page_size = 1 << log_page_size; 1145 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1146 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1147 1148 return rq_num_pas * sizeof(u64); 1149 } 1150 1151 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1152 struct mlx5_ib_rq *rq, void *qpin) 1153 { 1154 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1155 __be64 *pas; 1156 __be64 *qp_pas; 1157 void *in; 1158 void *rqc; 1159 void *wq; 1160 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1161 int inlen; 1162 int err; 1163 u32 rq_pas_size = get_rq_pas_size(qpc); 1164 1165 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1166 in = mlx5_vzalloc(inlen); 1167 if (!in) 1168 return -ENOMEM; 1169 1170 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1171 MLX5_SET(rqc, rqc, vsd, 1); 1172 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1173 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1174 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1175 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1176 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1177 1178 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1179 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1180 1181 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1182 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1183 MLX5_SET(wq, wq, end_padding_mode, 1184 MLX5_GET(qpc, qpc, end_padding_mode)); 1185 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1186 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1187 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1188 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1189 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1190 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1191 1192 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1193 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1194 memcpy(pas, qp_pas, rq_pas_size); 1195 1196 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1197 1198 kvfree(in); 1199 1200 return err; 1201 } 1202 1203 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1204 struct mlx5_ib_rq *rq) 1205 { 1206 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1207 } 1208 1209 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1210 struct mlx5_ib_rq *rq, u32 tdn) 1211 { 1212 u32 *in; 1213 void *tirc; 1214 int inlen; 1215 int err; 1216 1217 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1218 in = mlx5_vzalloc(inlen); 1219 if (!in) 1220 return -ENOMEM; 1221 1222 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1223 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1224 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1225 MLX5_SET(tirc, tirc, transport_domain, tdn); 1226 1227 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1228 1229 kvfree(in); 1230 1231 return err; 1232 } 1233 1234 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1235 struct mlx5_ib_rq *rq) 1236 { 1237 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1238 } 1239 1240 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1241 u32 *in, 1242 struct ib_pd *pd) 1243 { 1244 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1245 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1246 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1247 struct ib_uobject *uobj = pd->uobject; 1248 struct ib_ucontext *ucontext = uobj->context; 1249 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1250 int err; 1251 u32 tdn = mucontext->tdn; 1252 1253 if (qp->sq.wqe_cnt) { 1254 err = create_raw_packet_qp_tis(dev, sq, tdn); 1255 if (err) 1256 return err; 1257 1258 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1259 if (err) 1260 goto err_destroy_tis; 1261 1262 sq->base.container_mibqp = qp; 1263 } 1264 1265 if (qp->rq.wqe_cnt) { 1266 rq->base.container_mibqp = qp; 1267 1268 err = create_raw_packet_qp_rq(dev, rq, in); 1269 if (err) 1270 goto err_destroy_sq; 1271 1272 1273 err = create_raw_packet_qp_tir(dev, rq, tdn); 1274 if (err) 1275 goto err_destroy_rq; 1276 } 1277 1278 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1279 rq->base.mqp.qpn; 1280 1281 return 0; 1282 1283 err_destroy_rq: 1284 destroy_raw_packet_qp_rq(dev, rq); 1285 err_destroy_sq: 1286 if (!qp->sq.wqe_cnt) 1287 return err; 1288 destroy_raw_packet_qp_sq(dev, sq); 1289 err_destroy_tis: 1290 destroy_raw_packet_qp_tis(dev, sq); 1291 1292 return err; 1293 } 1294 1295 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1296 struct mlx5_ib_qp *qp) 1297 { 1298 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1299 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1300 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1301 1302 if (qp->rq.wqe_cnt) { 1303 destroy_raw_packet_qp_tir(dev, rq); 1304 destroy_raw_packet_qp_rq(dev, rq); 1305 } 1306 1307 if (qp->sq.wqe_cnt) { 1308 destroy_raw_packet_qp_sq(dev, sq); 1309 destroy_raw_packet_qp_tis(dev, sq); 1310 } 1311 } 1312 1313 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1314 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1315 { 1316 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1317 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1318 1319 sq->sq = &qp->sq; 1320 rq->rq = &qp->rq; 1321 sq->doorbell = &qp->db; 1322 rq->doorbell = &qp->db; 1323 } 1324 1325 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1326 { 1327 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1328 } 1329 1330 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1331 struct ib_pd *pd, 1332 struct ib_qp_init_attr *init_attr, 1333 struct ib_udata *udata) 1334 { 1335 struct ib_uobject *uobj = pd->uobject; 1336 struct ib_ucontext *ucontext = uobj->context; 1337 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1338 struct mlx5_ib_create_qp_resp resp = {}; 1339 int inlen; 1340 int err; 1341 u32 *in; 1342 void *tirc; 1343 void *hfso; 1344 u32 selected_fields = 0; 1345 size_t min_resp_len; 1346 u32 tdn = mucontext->tdn; 1347 struct mlx5_ib_create_qp_rss ucmd = {}; 1348 size_t required_cmd_sz; 1349 1350 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1351 return -EOPNOTSUPP; 1352 1353 if (init_attr->create_flags || init_attr->send_cq) 1354 return -EINVAL; 1355 1356 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index); 1357 if (udata->outlen < min_resp_len) 1358 return -EINVAL; 1359 1360 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1361 if (udata->inlen < required_cmd_sz) { 1362 mlx5_ib_dbg(dev, "invalid inlen\n"); 1363 return -EINVAL; 1364 } 1365 1366 if (udata->inlen > sizeof(ucmd) && 1367 !ib_is_udata_cleared(udata, sizeof(ucmd), 1368 udata->inlen - sizeof(ucmd))) { 1369 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1370 return -EOPNOTSUPP; 1371 } 1372 1373 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1374 mlx5_ib_dbg(dev, "copy failed\n"); 1375 return -EFAULT; 1376 } 1377 1378 if (ucmd.comp_mask) { 1379 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1380 return -EOPNOTSUPP; 1381 } 1382 1383 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1384 mlx5_ib_dbg(dev, "invalid reserved\n"); 1385 return -EOPNOTSUPP; 1386 } 1387 1388 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1389 if (err) { 1390 mlx5_ib_dbg(dev, "copy failed\n"); 1391 return -EINVAL; 1392 } 1393 1394 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1395 in = mlx5_vzalloc(inlen); 1396 if (!in) 1397 return -ENOMEM; 1398 1399 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1400 MLX5_SET(tirc, tirc, disp_type, 1401 MLX5_TIRC_DISP_TYPE_INDIRECT); 1402 MLX5_SET(tirc, tirc, indirect_table, 1403 init_attr->rwq_ind_tbl->ind_tbl_num); 1404 MLX5_SET(tirc, tirc, transport_domain, tdn); 1405 1406 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1407 switch (ucmd.rx_hash_function) { 1408 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1409 { 1410 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1411 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1412 1413 if (len != ucmd.rx_key_len) { 1414 err = -EINVAL; 1415 goto err; 1416 } 1417 1418 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1419 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1420 memcpy(rss_key, ucmd.rx_hash_key, len); 1421 break; 1422 } 1423 default: 1424 err = -EOPNOTSUPP; 1425 goto err; 1426 } 1427 1428 if (!ucmd.rx_hash_fields_mask) { 1429 /* special case when this TIR serves as steering entry without hashing */ 1430 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1431 goto create_tir; 1432 err = -EINVAL; 1433 goto err; 1434 } 1435 1436 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1437 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1438 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1439 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1440 err = -EINVAL; 1441 goto err; 1442 } 1443 1444 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1445 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1446 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1447 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1448 MLX5_L3_PROT_TYPE_IPV4); 1449 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1450 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1451 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1452 MLX5_L3_PROT_TYPE_IPV6); 1453 1454 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1455 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1456 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1457 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1458 err = -EINVAL; 1459 goto err; 1460 } 1461 1462 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1463 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1464 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1465 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1466 MLX5_L4_PROT_TYPE_TCP); 1467 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1468 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1469 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1470 MLX5_L4_PROT_TYPE_UDP); 1471 1472 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1473 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1474 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1475 1476 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1477 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1478 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1479 1480 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1481 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1482 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1483 1484 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1485 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1486 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1487 1488 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1489 1490 create_tir: 1491 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1492 1493 if (err) 1494 goto err; 1495 1496 kvfree(in); 1497 /* qpn is reserved for that QP */ 1498 qp->trans_qp.base.mqp.qpn = 0; 1499 qp->flags |= MLX5_IB_QP_RSS; 1500 return 0; 1501 1502 err: 1503 kvfree(in); 1504 return err; 1505 } 1506 1507 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1508 struct ib_qp_init_attr *init_attr, 1509 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1510 { 1511 struct mlx5_ib_resources *devr = &dev->devr; 1512 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1513 struct mlx5_core_dev *mdev = dev->mdev; 1514 struct mlx5_ib_create_qp_resp resp; 1515 struct mlx5_ib_cq *send_cq; 1516 struct mlx5_ib_cq *recv_cq; 1517 unsigned long flags; 1518 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1519 struct mlx5_ib_create_qp ucmd; 1520 struct mlx5_ib_qp_base *base; 1521 void *qpc; 1522 u32 *in; 1523 int err; 1524 1525 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1526 &qp->raw_packet_qp.rq.base : 1527 &qp->trans_qp.base; 1528 1529 mutex_init(&qp->mutex); 1530 spin_lock_init(&qp->sq.lock); 1531 spin_lock_init(&qp->rq.lock); 1532 1533 if (init_attr->rwq_ind_tbl) { 1534 if (!udata) 1535 return -ENOSYS; 1536 1537 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1538 return err; 1539 } 1540 1541 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1542 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1543 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1544 return -EINVAL; 1545 } else { 1546 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1547 } 1548 } 1549 1550 if (init_attr->create_flags & 1551 (IB_QP_CREATE_CROSS_CHANNEL | 1552 IB_QP_CREATE_MANAGED_SEND | 1553 IB_QP_CREATE_MANAGED_RECV)) { 1554 if (!MLX5_CAP_GEN(mdev, cd)) { 1555 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1556 return -EINVAL; 1557 } 1558 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1559 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1560 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1561 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1562 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1563 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1564 } 1565 1566 if (init_attr->qp_type == IB_QPT_UD && 1567 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1568 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1569 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1570 return -EOPNOTSUPP; 1571 } 1572 1573 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1574 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1575 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1576 return -EOPNOTSUPP; 1577 } 1578 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1579 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1580 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1581 return -EOPNOTSUPP; 1582 } 1583 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1584 } 1585 1586 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1587 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1588 1589 if (pd && pd->uobject) { 1590 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1591 mlx5_ib_dbg(dev, "copy failed\n"); 1592 return -EFAULT; 1593 } 1594 1595 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1596 &ucmd, udata->inlen, &uidx); 1597 if (err) 1598 return err; 1599 1600 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1601 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1602 } else { 1603 qp->wq_sig = !!wq_signature; 1604 } 1605 1606 qp->has_rq = qp_has_rq(init_attr); 1607 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1608 qp, (pd && pd->uobject) ? &ucmd : NULL); 1609 if (err) { 1610 mlx5_ib_dbg(dev, "err %d\n", err); 1611 return err; 1612 } 1613 1614 if (pd) { 1615 if (pd->uobject) { 1616 __u32 max_wqes = 1617 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1618 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1619 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1620 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1621 mlx5_ib_dbg(dev, "invalid rq params\n"); 1622 return -EINVAL; 1623 } 1624 if (ucmd.sq_wqe_count > max_wqes) { 1625 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1626 ucmd.sq_wqe_count, max_wqes); 1627 return -EINVAL; 1628 } 1629 if (init_attr->create_flags & 1630 mlx5_ib_create_qp_sqpn_qp1()) { 1631 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1632 return -EINVAL; 1633 } 1634 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1635 &resp, &inlen, base); 1636 if (err) 1637 mlx5_ib_dbg(dev, "err %d\n", err); 1638 } else { 1639 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1640 base); 1641 if (err) 1642 mlx5_ib_dbg(dev, "err %d\n", err); 1643 } 1644 1645 if (err) 1646 return err; 1647 } else { 1648 in = mlx5_vzalloc(inlen); 1649 if (!in) 1650 return -ENOMEM; 1651 1652 qp->create_type = MLX5_QP_EMPTY; 1653 } 1654 1655 if (is_sqp(init_attr->qp_type)) 1656 qp->port = init_attr->port_num; 1657 1658 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1659 1660 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1661 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1662 1663 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1664 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1665 else 1666 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1667 1668 1669 if (qp->wq_sig) 1670 MLX5_SET(qpc, qpc, wq_signature, 1); 1671 1672 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1673 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1674 1675 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1676 MLX5_SET(qpc, qpc, cd_master, 1); 1677 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1678 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1679 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1680 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1681 1682 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1683 int rcqe_sz; 1684 int scqe_sz; 1685 1686 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1687 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1688 1689 if (rcqe_sz == 128) 1690 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1691 else 1692 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1693 1694 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1695 if (scqe_sz == 128) 1696 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1697 else 1698 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1699 } 1700 } 1701 1702 if (qp->rq.wqe_cnt) { 1703 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1704 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1705 } 1706 1707 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1708 1709 if (qp->sq.wqe_cnt) 1710 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1711 else 1712 MLX5_SET(qpc, qpc, no_sq, 1); 1713 1714 /* Set default resources */ 1715 switch (init_attr->qp_type) { 1716 case IB_QPT_XRC_TGT: 1717 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1718 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1719 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1720 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1721 break; 1722 case IB_QPT_XRC_INI: 1723 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1724 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1725 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1726 break; 1727 default: 1728 if (init_attr->srq) { 1729 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1730 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1731 } else { 1732 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1733 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1734 } 1735 } 1736 1737 if (init_attr->send_cq) 1738 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1739 1740 if (init_attr->recv_cq) 1741 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1742 1743 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1744 1745 /* 0xffffff means we ask to work with cqe version 0 */ 1746 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1747 MLX5_SET(qpc, qpc, user_index, uidx); 1748 1749 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1750 if (init_attr->qp_type == IB_QPT_UD && 1751 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1752 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1753 qp->flags |= MLX5_IB_QP_LSO; 1754 } 1755 1756 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1757 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1758 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1759 err = create_raw_packet_qp(dev, qp, in, pd); 1760 } else { 1761 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1762 } 1763 1764 if (err) { 1765 mlx5_ib_dbg(dev, "create qp failed\n"); 1766 goto err_create; 1767 } 1768 1769 kvfree(in); 1770 1771 base->container_mibqp = qp; 1772 base->mqp.event = mlx5_ib_qp_event; 1773 1774 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1775 &send_cq, &recv_cq); 1776 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1777 mlx5_ib_lock_cqs(send_cq, recv_cq); 1778 /* Maintain device to QPs access, needed for further handling via reset 1779 * flow 1780 */ 1781 list_add_tail(&qp->qps_list, &dev->qp_list); 1782 /* Maintain CQ to QPs access, needed for further handling via reset flow 1783 */ 1784 if (send_cq) 1785 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1786 if (recv_cq) 1787 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1788 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1789 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1790 1791 return 0; 1792 1793 err_create: 1794 if (qp->create_type == MLX5_QP_USER) 1795 destroy_qp_user(pd, qp, base); 1796 else if (qp->create_type == MLX5_QP_KERNEL) 1797 destroy_qp_kernel(dev, qp); 1798 1799 kvfree(in); 1800 return err; 1801 } 1802 1803 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1804 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1805 { 1806 if (send_cq) { 1807 if (recv_cq) { 1808 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1809 spin_lock(&send_cq->lock); 1810 spin_lock_nested(&recv_cq->lock, 1811 SINGLE_DEPTH_NESTING); 1812 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1813 spin_lock(&send_cq->lock); 1814 __acquire(&recv_cq->lock); 1815 } else { 1816 spin_lock(&recv_cq->lock); 1817 spin_lock_nested(&send_cq->lock, 1818 SINGLE_DEPTH_NESTING); 1819 } 1820 } else { 1821 spin_lock(&send_cq->lock); 1822 __acquire(&recv_cq->lock); 1823 } 1824 } else if (recv_cq) { 1825 spin_lock(&recv_cq->lock); 1826 __acquire(&send_cq->lock); 1827 } else { 1828 __acquire(&send_cq->lock); 1829 __acquire(&recv_cq->lock); 1830 } 1831 } 1832 1833 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1834 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1835 { 1836 if (send_cq) { 1837 if (recv_cq) { 1838 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1839 spin_unlock(&recv_cq->lock); 1840 spin_unlock(&send_cq->lock); 1841 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1842 __release(&recv_cq->lock); 1843 spin_unlock(&send_cq->lock); 1844 } else { 1845 spin_unlock(&send_cq->lock); 1846 spin_unlock(&recv_cq->lock); 1847 } 1848 } else { 1849 __release(&recv_cq->lock); 1850 spin_unlock(&send_cq->lock); 1851 } 1852 } else if (recv_cq) { 1853 __release(&send_cq->lock); 1854 spin_unlock(&recv_cq->lock); 1855 } else { 1856 __release(&recv_cq->lock); 1857 __release(&send_cq->lock); 1858 } 1859 } 1860 1861 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1862 { 1863 return to_mpd(qp->ibqp.pd); 1864 } 1865 1866 static void get_cqs(enum ib_qp_type qp_type, 1867 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1868 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1869 { 1870 switch (qp_type) { 1871 case IB_QPT_XRC_TGT: 1872 *send_cq = NULL; 1873 *recv_cq = NULL; 1874 break; 1875 case MLX5_IB_QPT_REG_UMR: 1876 case IB_QPT_XRC_INI: 1877 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1878 *recv_cq = NULL; 1879 break; 1880 1881 case IB_QPT_SMI: 1882 case MLX5_IB_QPT_HW_GSI: 1883 case IB_QPT_RC: 1884 case IB_QPT_UC: 1885 case IB_QPT_UD: 1886 case IB_QPT_RAW_IPV6: 1887 case IB_QPT_RAW_ETHERTYPE: 1888 case IB_QPT_RAW_PACKET: 1889 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1890 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1891 break; 1892 1893 case IB_QPT_MAX: 1894 default: 1895 *send_cq = NULL; 1896 *recv_cq = NULL; 1897 break; 1898 } 1899 } 1900 1901 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1902 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1903 u8 lag_tx_affinity); 1904 1905 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1906 { 1907 struct mlx5_ib_cq *send_cq, *recv_cq; 1908 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1909 unsigned long flags; 1910 int err; 1911 1912 if (qp->ibqp.rwq_ind_tbl) { 1913 destroy_rss_raw_qp_tir(dev, qp); 1914 return; 1915 } 1916 1917 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 1918 &qp->raw_packet_qp.rq.base : 1919 &qp->trans_qp.base; 1920 1921 if (qp->state != IB_QPS_RESET) { 1922 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 1923 err = mlx5_core_qp_modify(dev->mdev, 1924 MLX5_CMD_OP_2RST_QP, 0, 1925 NULL, &base->mqp); 1926 } else { 1927 struct mlx5_modify_raw_qp_param raw_qp_param = { 1928 .operation = MLX5_CMD_OP_2RST_QP 1929 }; 1930 1931 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 1932 } 1933 if (err) 1934 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1935 base->mqp.qpn); 1936 } 1937 1938 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 1939 &send_cq, &recv_cq); 1940 1941 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1942 mlx5_ib_lock_cqs(send_cq, recv_cq); 1943 /* del from lists under both locks above to protect reset flow paths */ 1944 list_del(&qp->qps_list); 1945 if (send_cq) 1946 list_del(&qp->cq_send_list); 1947 1948 if (recv_cq) 1949 list_del(&qp->cq_recv_list); 1950 1951 if (qp->create_type == MLX5_QP_KERNEL) { 1952 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 1953 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1954 if (send_cq != recv_cq) 1955 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 1956 NULL); 1957 } 1958 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1959 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1960 1961 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1962 destroy_raw_packet_qp(dev, qp); 1963 } else { 1964 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 1965 if (err) 1966 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 1967 base->mqp.qpn); 1968 } 1969 1970 if (qp->create_type == MLX5_QP_KERNEL) 1971 destroy_qp_kernel(dev, qp); 1972 else if (qp->create_type == MLX5_QP_USER) 1973 destroy_qp_user(&get_pd(qp)->ibpd, qp, base); 1974 } 1975 1976 static const char *ib_qp_type_str(enum ib_qp_type type) 1977 { 1978 switch (type) { 1979 case IB_QPT_SMI: 1980 return "IB_QPT_SMI"; 1981 case IB_QPT_GSI: 1982 return "IB_QPT_GSI"; 1983 case IB_QPT_RC: 1984 return "IB_QPT_RC"; 1985 case IB_QPT_UC: 1986 return "IB_QPT_UC"; 1987 case IB_QPT_UD: 1988 return "IB_QPT_UD"; 1989 case IB_QPT_RAW_IPV6: 1990 return "IB_QPT_RAW_IPV6"; 1991 case IB_QPT_RAW_ETHERTYPE: 1992 return "IB_QPT_RAW_ETHERTYPE"; 1993 case IB_QPT_XRC_INI: 1994 return "IB_QPT_XRC_INI"; 1995 case IB_QPT_XRC_TGT: 1996 return "IB_QPT_XRC_TGT"; 1997 case IB_QPT_RAW_PACKET: 1998 return "IB_QPT_RAW_PACKET"; 1999 case MLX5_IB_QPT_REG_UMR: 2000 return "MLX5_IB_QPT_REG_UMR"; 2001 case IB_QPT_MAX: 2002 default: 2003 return "Invalid QP type"; 2004 } 2005 } 2006 2007 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2008 struct ib_qp_init_attr *init_attr, 2009 struct ib_udata *udata) 2010 { 2011 struct mlx5_ib_dev *dev; 2012 struct mlx5_ib_qp *qp; 2013 u16 xrcdn = 0; 2014 int err; 2015 2016 if (pd) { 2017 dev = to_mdev(pd->device); 2018 2019 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2020 if (!pd->uobject) { 2021 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2022 return ERR_PTR(-EINVAL); 2023 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2024 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2025 return ERR_PTR(-EINVAL); 2026 } 2027 } 2028 } else { 2029 /* being cautious here */ 2030 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2031 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2032 pr_warn("%s: no PD for transport %s\n", __func__, 2033 ib_qp_type_str(init_attr->qp_type)); 2034 return ERR_PTR(-EINVAL); 2035 } 2036 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2037 } 2038 2039 switch (init_attr->qp_type) { 2040 case IB_QPT_XRC_TGT: 2041 case IB_QPT_XRC_INI: 2042 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2043 mlx5_ib_dbg(dev, "XRC not supported\n"); 2044 return ERR_PTR(-ENOSYS); 2045 } 2046 init_attr->recv_cq = NULL; 2047 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2048 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2049 init_attr->send_cq = NULL; 2050 } 2051 2052 /* fall through */ 2053 case IB_QPT_RAW_PACKET: 2054 case IB_QPT_RC: 2055 case IB_QPT_UC: 2056 case IB_QPT_UD: 2057 case IB_QPT_SMI: 2058 case MLX5_IB_QPT_HW_GSI: 2059 case MLX5_IB_QPT_REG_UMR: 2060 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2061 if (!qp) 2062 return ERR_PTR(-ENOMEM); 2063 2064 err = create_qp_common(dev, pd, init_attr, udata, qp); 2065 if (err) { 2066 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2067 kfree(qp); 2068 return ERR_PTR(err); 2069 } 2070 2071 if (is_qp0(init_attr->qp_type)) 2072 qp->ibqp.qp_num = 0; 2073 else if (is_qp1(init_attr->qp_type)) 2074 qp->ibqp.qp_num = 1; 2075 else 2076 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2077 2078 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2079 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2080 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2081 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2082 2083 qp->trans_qp.xrcdn = xrcdn; 2084 2085 break; 2086 2087 case IB_QPT_GSI: 2088 return mlx5_ib_gsi_create_qp(pd, init_attr); 2089 2090 case IB_QPT_RAW_IPV6: 2091 case IB_QPT_RAW_ETHERTYPE: 2092 case IB_QPT_MAX: 2093 default: 2094 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2095 init_attr->qp_type); 2096 /* Don't support raw QPs */ 2097 return ERR_PTR(-EINVAL); 2098 } 2099 2100 return &qp->ibqp; 2101 } 2102 2103 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2104 { 2105 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2106 struct mlx5_ib_qp *mqp = to_mqp(qp); 2107 2108 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2109 return mlx5_ib_gsi_destroy_qp(qp); 2110 2111 destroy_qp_common(dev, mqp); 2112 2113 kfree(mqp); 2114 2115 return 0; 2116 } 2117 2118 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2119 int attr_mask) 2120 { 2121 u32 hw_access_flags = 0; 2122 u8 dest_rd_atomic; 2123 u32 access_flags; 2124 2125 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2126 dest_rd_atomic = attr->max_dest_rd_atomic; 2127 else 2128 dest_rd_atomic = qp->trans_qp.resp_depth; 2129 2130 if (attr_mask & IB_QP_ACCESS_FLAGS) 2131 access_flags = attr->qp_access_flags; 2132 else 2133 access_flags = qp->trans_qp.atomic_rd_en; 2134 2135 if (!dest_rd_atomic) 2136 access_flags &= IB_ACCESS_REMOTE_WRITE; 2137 2138 if (access_flags & IB_ACCESS_REMOTE_READ) 2139 hw_access_flags |= MLX5_QP_BIT_RRE; 2140 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2141 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2142 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2143 hw_access_flags |= MLX5_QP_BIT_RWE; 2144 2145 return cpu_to_be32(hw_access_flags); 2146 } 2147 2148 enum { 2149 MLX5_PATH_FLAG_FL = 1 << 0, 2150 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2151 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2152 }; 2153 2154 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2155 { 2156 if (rate == IB_RATE_PORT_CURRENT) { 2157 return 0; 2158 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2159 return -EINVAL; 2160 } else { 2161 while (rate != IB_RATE_2_5_GBPS && 2162 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2163 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2164 --rate; 2165 } 2166 2167 return rate + MLX5_STAT_RATE_OFFSET; 2168 } 2169 2170 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2171 struct mlx5_ib_sq *sq, u8 sl) 2172 { 2173 void *in; 2174 void *tisc; 2175 int inlen; 2176 int err; 2177 2178 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2179 in = mlx5_vzalloc(inlen); 2180 if (!in) 2181 return -ENOMEM; 2182 2183 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2184 2185 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2186 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2187 2188 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2189 2190 kvfree(in); 2191 2192 return err; 2193 } 2194 2195 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2196 struct mlx5_ib_sq *sq, u8 tx_affinity) 2197 { 2198 void *in; 2199 void *tisc; 2200 int inlen; 2201 int err; 2202 2203 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2204 in = mlx5_vzalloc(inlen); 2205 if (!in) 2206 return -ENOMEM; 2207 2208 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2209 2210 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2211 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2212 2213 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2214 2215 kvfree(in); 2216 2217 return err; 2218 } 2219 2220 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2221 const struct ib_ah_attr *ah, 2222 struct mlx5_qp_path *path, u8 port, int attr_mask, 2223 u32 path_flags, const struct ib_qp_attr *attr, 2224 bool alt) 2225 { 2226 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2227 int err; 2228 2229 if (attr_mask & IB_QP_PKEY_INDEX) 2230 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2231 attr->pkey_index); 2232 2233 if (ah->ah_flags & IB_AH_GRH) { 2234 if (ah->grh.sgid_index >= 2235 dev->mdev->port_caps[port - 1].gid_table_len) { 2236 pr_err("sgid_index (%u) too large. max is %d\n", 2237 ah->grh.sgid_index, 2238 dev->mdev->port_caps[port - 1].gid_table_len); 2239 return -EINVAL; 2240 } 2241 } 2242 2243 if (ll == IB_LINK_LAYER_ETHERNET) { 2244 if (!(ah->ah_flags & IB_AH_GRH)) 2245 return -EINVAL; 2246 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2247 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2248 ah->grh.sgid_index); 2249 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2250 } else { 2251 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2252 path->fl_free_ar |= 2253 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2254 path->rlid = cpu_to_be16(ah->dlid); 2255 path->grh_mlid = ah->src_path_bits & 0x7f; 2256 if (ah->ah_flags & IB_AH_GRH) 2257 path->grh_mlid |= 1 << 7; 2258 path->dci_cfi_prio_sl = ah->sl & 0xf; 2259 } 2260 2261 if (ah->ah_flags & IB_AH_GRH) { 2262 path->mgid_index = ah->grh.sgid_index; 2263 path->hop_limit = ah->grh.hop_limit; 2264 path->tclass_flowlabel = 2265 cpu_to_be32((ah->grh.traffic_class << 20) | 2266 (ah->grh.flow_label)); 2267 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2268 } 2269 2270 err = ib_rate_to_mlx5(dev, ah->static_rate); 2271 if (err < 0) 2272 return err; 2273 path->static_rate = err; 2274 path->port = port; 2275 2276 if (attr_mask & IB_QP_TIMEOUT) 2277 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2278 2279 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2280 return modify_raw_packet_eth_prio(dev->mdev, 2281 &qp->raw_packet_qp.sq, 2282 ah->sl & 0xf); 2283 2284 return 0; 2285 } 2286 2287 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2288 [MLX5_QP_STATE_INIT] = { 2289 [MLX5_QP_STATE_INIT] = { 2290 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2291 MLX5_QP_OPTPAR_RAE | 2292 MLX5_QP_OPTPAR_RWE | 2293 MLX5_QP_OPTPAR_PKEY_INDEX | 2294 MLX5_QP_OPTPAR_PRI_PORT, 2295 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2296 MLX5_QP_OPTPAR_PKEY_INDEX | 2297 MLX5_QP_OPTPAR_PRI_PORT, 2298 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2299 MLX5_QP_OPTPAR_Q_KEY | 2300 MLX5_QP_OPTPAR_PRI_PORT, 2301 }, 2302 [MLX5_QP_STATE_RTR] = { 2303 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2304 MLX5_QP_OPTPAR_RRE | 2305 MLX5_QP_OPTPAR_RAE | 2306 MLX5_QP_OPTPAR_RWE | 2307 MLX5_QP_OPTPAR_PKEY_INDEX, 2308 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2309 MLX5_QP_OPTPAR_RWE | 2310 MLX5_QP_OPTPAR_PKEY_INDEX, 2311 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2312 MLX5_QP_OPTPAR_Q_KEY, 2313 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2314 MLX5_QP_OPTPAR_Q_KEY, 2315 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2316 MLX5_QP_OPTPAR_RRE | 2317 MLX5_QP_OPTPAR_RAE | 2318 MLX5_QP_OPTPAR_RWE | 2319 MLX5_QP_OPTPAR_PKEY_INDEX, 2320 }, 2321 }, 2322 [MLX5_QP_STATE_RTR] = { 2323 [MLX5_QP_STATE_RTS] = { 2324 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2325 MLX5_QP_OPTPAR_RRE | 2326 MLX5_QP_OPTPAR_RAE | 2327 MLX5_QP_OPTPAR_RWE | 2328 MLX5_QP_OPTPAR_PM_STATE | 2329 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2330 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2331 MLX5_QP_OPTPAR_RWE | 2332 MLX5_QP_OPTPAR_PM_STATE, 2333 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2334 }, 2335 }, 2336 [MLX5_QP_STATE_RTS] = { 2337 [MLX5_QP_STATE_RTS] = { 2338 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2339 MLX5_QP_OPTPAR_RAE | 2340 MLX5_QP_OPTPAR_RWE | 2341 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2342 MLX5_QP_OPTPAR_PM_STATE | 2343 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2344 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2345 MLX5_QP_OPTPAR_PM_STATE | 2346 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2347 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2348 MLX5_QP_OPTPAR_SRQN | 2349 MLX5_QP_OPTPAR_CQN_RCV, 2350 }, 2351 }, 2352 [MLX5_QP_STATE_SQER] = { 2353 [MLX5_QP_STATE_RTS] = { 2354 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2355 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2356 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2357 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2358 MLX5_QP_OPTPAR_RWE | 2359 MLX5_QP_OPTPAR_RAE | 2360 MLX5_QP_OPTPAR_RRE, 2361 }, 2362 }, 2363 }; 2364 2365 static int ib_nr_to_mlx5_nr(int ib_mask) 2366 { 2367 switch (ib_mask) { 2368 case IB_QP_STATE: 2369 return 0; 2370 case IB_QP_CUR_STATE: 2371 return 0; 2372 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2373 return 0; 2374 case IB_QP_ACCESS_FLAGS: 2375 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2376 MLX5_QP_OPTPAR_RAE; 2377 case IB_QP_PKEY_INDEX: 2378 return MLX5_QP_OPTPAR_PKEY_INDEX; 2379 case IB_QP_PORT: 2380 return MLX5_QP_OPTPAR_PRI_PORT; 2381 case IB_QP_QKEY: 2382 return MLX5_QP_OPTPAR_Q_KEY; 2383 case IB_QP_AV: 2384 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2385 MLX5_QP_OPTPAR_PRI_PORT; 2386 case IB_QP_PATH_MTU: 2387 return 0; 2388 case IB_QP_TIMEOUT: 2389 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2390 case IB_QP_RETRY_CNT: 2391 return MLX5_QP_OPTPAR_RETRY_COUNT; 2392 case IB_QP_RNR_RETRY: 2393 return MLX5_QP_OPTPAR_RNR_RETRY; 2394 case IB_QP_RQ_PSN: 2395 return 0; 2396 case IB_QP_MAX_QP_RD_ATOMIC: 2397 return MLX5_QP_OPTPAR_SRA_MAX; 2398 case IB_QP_ALT_PATH: 2399 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2400 case IB_QP_MIN_RNR_TIMER: 2401 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2402 case IB_QP_SQ_PSN: 2403 return 0; 2404 case IB_QP_MAX_DEST_RD_ATOMIC: 2405 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2406 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2407 case IB_QP_PATH_MIG_STATE: 2408 return MLX5_QP_OPTPAR_PM_STATE; 2409 case IB_QP_CAP: 2410 return 0; 2411 case IB_QP_DEST_QPN: 2412 return 0; 2413 } 2414 return 0; 2415 } 2416 2417 static int ib_mask_to_mlx5_opt(int ib_mask) 2418 { 2419 int result = 0; 2420 int i; 2421 2422 for (i = 0; i < 8 * sizeof(int); i++) { 2423 if ((1 << i) & ib_mask) 2424 result |= ib_nr_to_mlx5_nr(1 << i); 2425 } 2426 2427 return result; 2428 } 2429 2430 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2431 struct mlx5_ib_rq *rq, int new_state, 2432 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2433 { 2434 void *in; 2435 void *rqc; 2436 int inlen; 2437 int err; 2438 2439 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2440 in = mlx5_vzalloc(inlen); 2441 if (!in) 2442 return -ENOMEM; 2443 2444 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2445 2446 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2447 MLX5_SET(rqc, rqc, state, new_state); 2448 2449 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2450 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2451 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2452 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID); 2453 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2454 } else 2455 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2456 dev->ib_dev.name); 2457 } 2458 2459 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2460 if (err) 2461 goto out; 2462 2463 rq->state = new_state; 2464 2465 out: 2466 kvfree(in); 2467 return err; 2468 } 2469 2470 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2471 struct mlx5_ib_sq *sq, 2472 int new_state, 2473 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2474 { 2475 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2476 u32 old_rate = ibqp->rate_limit; 2477 u32 new_rate = old_rate; 2478 u16 rl_index = 0; 2479 void *in; 2480 void *sqc; 2481 int inlen; 2482 int err; 2483 2484 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2485 in = mlx5_vzalloc(inlen); 2486 if (!in) 2487 return -ENOMEM; 2488 2489 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2490 2491 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2492 MLX5_SET(sqc, sqc, state, new_state); 2493 2494 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2495 if (new_state != MLX5_SQC_STATE_RDY) 2496 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2497 __func__); 2498 else 2499 new_rate = raw_qp_param->rate_limit; 2500 } 2501 2502 if (old_rate != new_rate) { 2503 if (new_rate) { 2504 err = mlx5_rl_add_rate(dev, new_rate, &rl_index); 2505 if (err) { 2506 pr_err("Failed configuring rate %u: %d\n", 2507 new_rate, err); 2508 goto out; 2509 } 2510 } 2511 2512 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2513 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2514 } 2515 2516 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2517 if (err) { 2518 /* Remove new rate from table if failed */ 2519 if (new_rate && 2520 old_rate != new_rate) 2521 mlx5_rl_remove_rate(dev, new_rate); 2522 goto out; 2523 } 2524 2525 /* Only remove the old rate after new rate was set */ 2526 if ((old_rate && 2527 (old_rate != new_rate)) || 2528 (new_state != MLX5_SQC_STATE_RDY)) 2529 mlx5_rl_remove_rate(dev, old_rate); 2530 2531 ibqp->rate_limit = new_rate; 2532 sq->state = new_state; 2533 2534 out: 2535 kvfree(in); 2536 return err; 2537 } 2538 2539 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2540 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2541 u8 tx_affinity) 2542 { 2543 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2544 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2545 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2546 int modify_rq = !!qp->rq.wqe_cnt; 2547 int modify_sq = !!qp->sq.wqe_cnt; 2548 int rq_state; 2549 int sq_state; 2550 int err; 2551 2552 switch (raw_qp_param->operation) { 2553 case MLX5_CMD_OP_RST2INIT_QP: 2554 rq_state = MLX5_RQC_STATE_RDY; 2555 sq_state = MLX5_SQC_STATE_RDY; 2556 break; 2557 case MLX5_CMD_OP_2ERR_QP: 2558 rq_state = MLX5_RQC_STATE_ERR; 2559 sq_state = MLX5_SQC_STATE_ERR; 2560 break; 2561 case MLX5_CMD_OP_2RST_QP: 2562 rq_state = MLX5_RQC_STATE_RST; 2563 sq_state = MLX5_SQC_STATE_RST; 2564 break; 2565 case MLX5_CMD_OP_RTR2RTS_QP: 2566 case MLX5_CMD_OP_RTS2RTS_QP: 2567 if (raw_qp_param->set_mask == 2568 MLX5_RAW_QP_RATE_LIMIT) { 2569 modify_rq = 0; 2570 sq_state = sq->state; 2571 } else { 2572 return raw_qp_param->set_mask ? -EINVAL : 0; 2573 } 2574 break; 2575 case MLX5_CMD_OP_INIT2INIT_QP: 2576 case MLX5_CMD_OP_INIT2RTR_QP: 2577 if (raw_qp_param->set_mask) 2578 return -EINVAL; 2579 else 2580 return 0; 2581 default: 2582 WARN_ON(1); 2583 return -EINVAL; 2584 } 2585 2586 if (modify_rq) { 2587 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2588 if (err) 2589 return err; 2590 } 2591 2592 if (modify_sq) { 2593 if (tx_affinity) { 2594 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2595 tx_affinity); 2596 if (err) 2597 return err; 2598 } 2599 2600 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2601 } 2602 2603 return 0; 2604 } 2605 2606 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2607 const struct ib_qp_attr *attr, int attr_mask, 2608 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2609 { 2610 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2611 [MLX5_QP_STATE_RST] = { 2612 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2613 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2614 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2615 }, 2616 [MLX5_QP_STATE_INIT] = { 2617 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2618 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2619 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2620 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2621 }, 2622 [MLX5_QP_STATE_RTR] = { 2623 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2624 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2625 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2626 }, 2627 [MLX5_QP_STATE_RTS] = { 2628 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2629 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2630 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2631 }, 2632 [MLX5_QP_STATE_SQD] = { 2633 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2634 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2635 }, 2636 [MLX5_QP_STATE_SQER] = { 2637 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2638 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2639 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2640 }, 2641 [MLX5_QP_STATE_ERR] = { 2642 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2643 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2644 } 2645 }; 2646 2647 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2648 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2649 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2650 struct mlx5_ib_cq *send_cq, *recv_cq; 2651 struct mlx5_qp_context *context; 2652 struct mlx5_ib_pd *pd; 2653 struct mlx5_ib_port *mibport = NULL; 2654 enum mlx5_qp_state mlx5_cur, mlx5_new; 2655 enum mlx5_qp_optpar optpar; 2656 int mlx5_st; 2657 int err; 2658 u16 op; 2659 u8 tx_affinity = 0; 2660 2661 context = kzalloc(sizeof(*context), GFP_KERNEL); 2662 if (!context) 2663 return -ENOMEM; 2664 2665 err = to_mlx5_st(ibqp->qp_type); 2666 if (err < 0) { 2667 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2668 goto out; 2669 } 2670 2671 context->flags = cpu_to_be32(err << 16); 2672 2673 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2674 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2675 } else { 2676 switch (attr->path_mig_state) { 2677 case IB_MIG_MIGRATED: 2678 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2679 break; 2680 case IB_MIG_REARM: 2681 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2682 break; 2683 case IB_MIG_ARMED: 2684 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2685 break; 2686 } 2687 } 2688 2689 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2690 if ((ibqp->qp_type == IB_QPT_RC) || 2691 (ibqp->qp_type == IB_QPT_UD && 2692 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 2693 (ibqp->qp_type == IB_QPT_UC) || 2694 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2695 (ibqp->qp_type == IB_QPT_XRC_INI) || 2696 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 2697 if (mlx5_lag_is_active(dev->mdev)) { 2698 tx_affinity = (unsigned int)atomic_add_return(1, 2699 &dev->roce.next_port) % 2700 MLX5_MAX_PORTS + 1; 2701 context->flags |= cpu_to_be32(tx_affinity << 24); 2702 } 2703 } 2704 } 2705 2706 if (is_sqp(ibqp->qp_type)) { 2707 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2708 } else if (ibqp->qp_type == IB_QPT_UD || 2709 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2710 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2711 } else if (attr_mask & IB_QP_PATH_MTU) { 2712 if (attr->path_mtu < IB_MTU_256 || 2713 attr->path_mtu > IB_MTU_4096) { 2714 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2715 err = -EINVAL; 2716 goto out; 2717 } 2718 context->mtu_msgmax = (attr->path_mtu << 5) | 2719 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2720 } 2721 2722 if (attr_mask & IB_QP_DEST_QPN) 2723 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2724 2725 if (attr_mask & IB_QP_PKEY_INDEX) 2726 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2727 2728 /* todo implement counter_index functionality */ 2729 2730 if (is_sqp(ibqp->qp_type)) 2731 context->pri_path.port = qp->port; 2732 2733 if (attr_mask & IB_QP_PORT) 2734 context->pri_path.port = attr->port_num; 2735 2736 if (attr_mask & IB_QP_AV) { 2737 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2738 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2739 attr_mask, 0, attr, false); 2740 if (err) 2741 goto out; 2742 } 2743 2744 if (attr_mask & IB_QP_TIMEOUT) 2745 context->pri_path.ackto_lt |= attr->timeout << 3; 2746 2747 if (attr_mask & IB_QP_ALT_PATH) { 2748 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2749 &context->alt_path, 2750 attr->alt_port_num, 2751 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2752 0, attr, true); 2753 if (err) 2754 goto out; 2755 } 2756 2757 pd = get_pd(qp); 2758 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2759 &send_cq, &recv_cq); 2760 2761 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2762 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2763 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2764 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2765 2766 if (attr_mask & IB_QP_RNR_RETRY) 2767 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2768 2769 if (attr_mask & IB_QP_RETRY_CNT) 2770 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2771 2772 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2773 if (attr->max_rd_atomic) 2774 context->params1 |= 2775 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2776 } 2777 2778 if (attr_mask & IB_QP_SQ_PSN) 2779 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2780 2781 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2782 if (attr->max_dest_rd_atomic) 2783 context->params2 |= 2784 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2785 } 2786 2787 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2788 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2789 2790 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2791 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2792 2793 if (attr_mask & IB_QP_RQ_PSN) 2794 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2795 2796 if (attr_mask & IB_QP_QKEY) 2797 context->qkey = cpu_to_be32(attr->qkey); 2798 2799 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2800 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2801 2802 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2803 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2804 qp->port) - 1; 2805 mibport = &dev->port[port_num]; 2806 context->qp_counter_set_usr_page |= 2807 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2808 } 2809 2810 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2811 context->sq_crq_size |= cpu_to_be16(1 << 4); 2812 2813 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2814 context->deth_sqpn = cpu_to_be32(1); 2815 2816 mlx5_cur = to_mlx5_state(cur_state); 2817 mlx5_new = to_mlx5_state(new_state); 2818 mlx5_st = to_mlx5_st(ibqp->qp_type); 2819 if (mlx5_st < 0) 2820 goto out; 2821 2822 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2823 !optab[mlx5_cur][mlx5_new]) 2824 goto out; 2825 2826 op = optab[mlx5_cur][mlx5_new]; 2827 optpar = ib_mask_to_mlx5_opt(attr_mask); 2828 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2829 2830 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2831 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2832 2833 raw_qp_param.operation = op; 2834 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2835 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id; 2836 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2837 } 2838 2839 if (attr_mask & IB_QP_RATE_LIMIT) { 2840 raw_qp_param.rate_limit = attr->rate_limit; 2841 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 2842 } 2843 2844 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 2845 } else { 2846 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2847 &base->mqp); 2848 } 2849 2850 if (err) 2851 goto out; 2852 2853 qp->state = new_state; 2854 2855 if (attr_mask & IB_QP_ACCESS_FLAGS) 2856 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2857 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2858 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2859 if (attr_mask & IB_QP_PORT) 2860 qp->port = attr->port_num; 2861 if (attr_mask & IB_QP_ALT_PATH) 2862 qp->trans_qp.alt_port = attr->alt_port_num; 2863 2864 /* 2865 * If we moved a kernel QP to RESET, clean up all old CQ 2866 * entries and reinitialize the QP. 2867 */ 2868 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2869 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2870 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2871 if (send_cq != recv_cq) 2872 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2873 2874 qp->rq.head = 0; 2875 qp->rq.tail = 0; 2876 qp->sq.head = 0; 2877 qp->sq.tail = 0; 2878 qp->sq.cur_post = 0; 2879 qp->sq.last_poll = 0; 2880 qp->db.db[MLX5_RCV_DBR] = 0; 2881 qp->db.db[MLX5_SND_DBR] = 0; 2882 } 2883 2884 out: 2885 kfree(context); 2886 return err; 2887 } 2888 2889 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2890 int attr_mask, struct ib_udata *udata) 2891 { 2892 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2893 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2894 enum ib_qp_type qp_type; 2895 enum ib_qp_state cur_state, new_state; 2896 int err = -EINVAL; 2897 int port; 2898 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2899 2900 if (ibqp->rwq_ind_tbl) 2901 return -ENOSYS; 2902 2903 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2904 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2905 2906 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2907 IB_QPT_GSI : ibqp->qp_type; 2908 2909 mutex_lock(&qp->mutex); 2910 2911 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2912 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2913 2914 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 2915 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2916 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 2917 } 2918 2919 if (qp_type != MLX5_IB_QPT_REG_UMR && 2920 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 2921 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2922 cur_state, new_state, ibqp->qp_type, attr_mask); 2923 goto out; 2924 } 2925 2926 if ((attr_mask & IB_QP_PORT) && 2927 (attr->port_num == 0 || 2928 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2929 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2930 attr->port_num, dev->num_ports); 2931 goto out; 2932 } 2933 2934 if (attr_mask & IB_QP_PKEY_INDEX) { 2935 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2936 if (attr->pkey_index >= 2937 dev->mdev->port_caps[port - 1].pkey_table_len) { 2938 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 2939 attr->pkey_index); 2940 goto out; 2941 } 2942 } 2943 2944 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2945 attr->max_rd_atomic > 2946 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 2947 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 2948 attr->max_rd_atomic); 2949 goto out; 2950 } 2951 2952 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2953 attr->max_dest_rd_atomic > 2954 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 2955 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 2956 attr->max_dest_rd_atomic); 2957 goto out; 2958 } 2959 2960 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2961 err = 0; 2962 goto out; 2963 } 2964 2965 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2966 2967 out: 2968 mutex_unlock(&qp->mutex); 2969 return err; 2970 } 2971 2972 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2973 { 2974 struct mlx5_ib_cq *cq; 2975 unsigned cur; 2976 2977 cur = wq->head - wq->tail; 2978 if (likely(cur + nreq < wq->max_post)) 2979 return 0; 2980 2981 cq = to_mcq(ib_cq); 2982 spin_lock(&cq->lock); 2983 cur = wq->head - wq->tail; 2984 spin_unlock(&cq->lock); 2985 2986 return cur + nreq >= wq->max_post; 2987 } 2988 2989 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 2990 u64 remote_addr, u32 rkey) 2991 { 2992 rseg->raddr = cpu_to_be64(remote_addr); 2993 rseg->rkey = cpu_to_be32(rkey); 2994 rseg->reserved = 0; 2995 } 2996 2997 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 2998 struct ib_send_wr *wr, void *qend, 2999 struct mlx5_ib_qp *qp, int *size) 3000 { 3001 void *seg = eseg; 3002 3003 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3004 3005 if (wr->send_flags & IB_SEND_IP_CSUM) 3006 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3007 MLX5_ETH_WQE_L4_CSUM; 3008 3009 seg += sizeof(struct mlx5_wqe_eth_seg); 3010 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3011 3012 if (wr->opcode == IB_WR_LSO) { 3013 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3014 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 3015 u64 left, leftlen, copysz; 3016 void *pdata = ud_wr->header; 3017 3018 left = ud_wr->hlen; 3019 eseg->mss = cpu_to_be16(ud_wr->mss); 3020 eseg->inline_hdr_sz = cpu_to_be16(left); 3021 3022 /* 3023 * check if there is space till the end of queue, if yes, 3024 * copy all in one shot, otherwise copy till the end of queue, 3025 * rollback and than the copy the left 3026 */ 3027 leftlen = qend - (void *)eseg->inline_hdr_start; 3028 copysz = min_t(u64, leftlen, left); 3029 3030 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3031 3032 if (likely(copysz > size_of_inl_hdr_start)) { 3033 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3034 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3035 } 3036 3037 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3038 seg = mlx5_get_send_wqe(qp, 0); 3039 left -= copysz; 3040 pdata += copysz; 3041 memcpy(seg, pdata, left); 3042 seg += ALIGN(left, 16); 3043 *size += ALIGN(left, 16) / 16; 3044 } 3045 } 3046 3047 return seg; 3048 } 3049 3050 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3051 struct ib_send_wr *wr) 3052 { 3053 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3054 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3055 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3056 } 3057 3058 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3059 { 3060 dseg->byte_count = cpu_to_be32(sg->length); 3061 dseg->lkey = cpu_to_be32(sg->lkey); 3062 dseg->addr = cpu_to_be64(sg->addr); 3063 } 3064 3065 static u64 get_xlt_octo(u64 bytes) 3066 { 3067 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3068 MLX5_IB_UMR_OCTOWORD; 3069 } 3070 3071 static __be64 frwr_mkey_mask(void) 3072 { 3073 u64 result; 3074 3075 result = MLX5_MKEY_MASK_LEN | 3076 MLX5_MKEY_MASK_PAGE_SIZE | 3077 MLX5_MKEY_MASK_START_ADDR | 3078 MLX5_MKEY_MASK_EN_RINVAL | 3079 MLX5_MKEY_MASK_KEY | 3080 MLX5_MKEY_MASK_LR | 3081 MLX5_MKEY_MASK_LW | 3082 MLX5_MKEY_MASK_RR | 3083 MLX5_MKEY_MASK_RW | 3084 MLX5_MKEY_MASK_A | 3085 MLX5_MKEY_MASK_SMALL_FENCE | 3086 MLX5_MKEY_MASK_FREE; 3087 3088 return cpu_to_be64(result); 3089 } 3090 3091 static __be64 sig_mkey_mask(void) 3092 { 3093 u64 result; 3094 3095 result = MLX5_MKEY_MASK_LEN | 3096 MLX5_MKEY_MASK_PAGE_SIZE | 3097 MLX5_MKEY_MASK_START_ADDR | 3098 MLX5_MKEY_MASK_EN_SIGERR | 3099 MLX5_MKEY_MASK_EN_RINVAL | 3100 MLX5_MKEY_MASK_KEY | 3101 MLX5_MKEY_MASK_LR | 3102 MLX5_MKEY_MASK_LW | 3103 MLX5_MKEY_MASK_RR | 3104 MLX5_MKEY_MASK_RW | 3105 MLX5_MKEY_MASK_SMALL_FENCE | 3106 MLX5_MKEY_MASK_FREE | 3107 MLX5_MKEY_MASK_BSF_EN; 3108 3109 return cpu_to_be64(result); 3110 } 3111 3112 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3113 struct mlx5_ib_mr *mr) 3114 { 3115 int size = mr->ndescs * mr->desc_size; 3116 3117 memset(umr, 0, sizeof(*umr)); 3118 3119 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3120 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3121 umr->mkey_mask = frwr_mkey_mask(); 3122 } 3123 3124 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3125 { 3126 memset(umr, 0, sizeof(*umr)); 3127 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3128 umr->flags = MLX5_UMR_INLINE; 3129 } 3130 3131 static __be64 get_umr_enable_mr_mask(void) 3132 { 3133 u64 result; 3134 3135 result = MLX5_MKEY_MASK_KEY | 3136 MLX5_MKEY_MASK_FREE; 3137 3138 return cpu_to_be64(result); 3139 } 3140 3141 static __be64 get_umr_disable_mr_mask(void) 3142 { 3143 u64 result; 3144 3145 result = MLX5_MKEY_MASK_FREE; 3146 3147 return cpu_to_be64(result); 3148 } 3149 3150 static __be64 get_umr_update_translation_mask(void) 3151 { 3152 u64 result; 3153 3154 result = MLX5_MKEY_MASK_LEN | 3155 MLX5_MKEY_MASK_PAGE_SIZE | 3156 MLX5_MKEY_MASK_START_ADDR; 3157 3158 return cpu_to_be64(result); 3159 } 3160 3161 static __be64 get_umr_update_access_mask(int atomic) 3162 { 3163 u64 result; 3164 3165 result = MLX5_MKEY_MASK_LR | 3166 MLX5_MKEY_MASK_LW | 3167 MLX5_MKEY_MASK_RR | 3168 MLX5_MKEY_MASK_RW; 3169 3170 if (atomic) 3171 result |= MLX5_MKEY_MASK_A; 3172 3173 return cpu_to_be64(result); 3174 } 3175 3176 static __be64 get_umr_update_pd_mask(void) 3177 { 3178 u64 result; 3179 3180 result = MLX5_MKEY_MASK_PD; 3181 3182 return cpu_to_be64(result); 3183 } 3184 3185 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3186 struct ib_send_wr *wr, int atomic) 3187 { 3188 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3189 3190 memset(umr, 0, sizeof(*umr)); 3191 3192 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3193 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3194 else 3195 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3196 3197 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3198 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3199 u64 offset = get_xlt_octo(umrwr->offset); 3200 3201 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3202 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3203 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3204 } 3205 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3206 umr->mkey_mask |= get_umr_update_translation_mask(); 3207 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3208 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3209 umr->mkey_mask |= get_umr_update_pd_mask(); 3210 } 3211 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3212 umr->mkey_mask |= get_umr_enable_mr_mask(); 3213 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3214 umr->mkey_mask |= get_umr_disable_mr_mask(); 3215 3216 if (!wr->num_sge) 3217 umr->flags |= MLX5_UMR_INLINE; 3218 } 3219 3220 static u8 get_umr_flags(int acc) 3221 { 3222 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3223 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3224 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3225 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3226 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3227 } 3228 3229 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3230 struct mlx5_ib_mr *mr, 3231 u32 key, int access) 3232 { 3233 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3234 3235 memset(seg, 0, sizeof(*seg)); 3236 3237 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3238 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3239 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3240 /* KLMs take twice the size of MTTs */ 3241 ndescs *= 2; 3242 3243 seg->flags = get_umr_flags(access) | mr->access_mode; 3244 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3245 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3246 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3247 seg->len = cpu_to_be64(mr->ibmr.length); 3248 seg->xlt_oct_size = cpu_to_be32(ndescs); 3249 } 3250 3251 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3252 { 3253 memset(seg, 0, sizeof(*seg)); 3254 seg->status = MLX5_MKEY_STATUS_FREE; 3255 } 3256 3257 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3258 { 3259 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3260 3261 memset(seg, 0, sizeof(*seg)); 3262 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3263 seg->status = MLX5_MKEY_STATUS_FREE; 3264 3265 seg->flags = convert_access(umrwr->access_flags); 3266 if (umrwr->pd) 3267 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3268 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3269 !umrwr->length) 3270 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3271 3272 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3273 seg->len = cpu_to_be64(umrwr->length); 3274 seg->log2_page_size = umrwr->page_shift; 3275 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3276 mlx5_mkey_variant(umrwr->mkey)); 3277 } 3278 3279 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3280 struct mlx5_ib_mr *mr, 3281 struct mlx5_ib_pd *pd) 3282 { 3283 int bcount = mr->desc_size * mr->ndescs; 3284 3285 dseg->addr = cpu_to_be64(mr->desc_map); 3286 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3287 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3288 } 3289 3290 static __be32 send_ieth(struct ib_send_wr *wr) 3291 { 3292 switch (wr->opcode) { 3293 case IB_WR_SEND_WITH_IMM: 3294 case IB_WR_RDMA_WRITE_WITH_IMM: 3295 return wr->ex.imm_data; 3296 3297 case IB_WR_SEND_WITH_INV: 3298 return cpu_to_be32(wr->ex.invalidate_rkey); 3299 3300 default: 3301 return 0; 3302 } 3303 } 3304 3305 static u8 calc_sig(void *wqe, int size) 3306 { 3307 u8 *p = wqe; 3308 u8 res = 0; 3309 int i; 3310 3311 for (i = 0; i < size; i++) 3312 res ^= p[i]; 3313 3314 return ~res; 3315 } 3316 3317 static u8 wq_sig(void *wqe) 3318 { 3319 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3320 } 3321 3322 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3323 void *wqe, int *sz) 3324 { 3325 struct mlx5_wqe_inline_seg *seg; 3326 void *qend = qp->sq.qend; 3327 void *addr; 3328 int inl = 0; 3329 int copy; 3330 int len; 3331 int i; 3332 3333 seg = wqe; 3334 wqe += sizeof(*seg); 3335 for (i = 0; i < wr->num_sge; i++) { 3336 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3337 len = wr->sg_list[i].length; 3338 inl += len; 3339 3340 if (unlikely(inl > qp->max_inline_data)) 3341 return -ENOMEM; 3342 3343 if (unlikely(wqe + len > qend)) { 3344 copy = qend - wqe; 3345 memcpy(wqe, addr, copy); 3346 addr += copy; 3347 len -= copy; 3348 wqe = mlx5_get_send_wqe(qp, 0); 3349 } 3350 memcpy(wqe, addr, len); 3351 wqe += len; 3352 } 3353 3354 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3355 3356 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3357 3358 return 0; 3359 } 3360 3361 static u16 prot_field_size(enum ib_signature_type type) 3362 { 3363 switch (type) { 3364 case IB_SIG_TYPE_T10_DIF: 3365 return MLX5_DIF_SIZE; 3366 default: 3367 return 0; 3368 } 3369 } 3370 3371 static u8 bs_selector(int block_size) 3372 { 3373 switch (block_size) { 3374 case 512: return 0x1; 3375 case 520: return 0x2; 3376 case 4096: return 0x3; 3377 case 4160: return 0x4; 3378 case 1073741824: return 0x5; 3379 default: return 0; 3380 } 3381 } 3382 3383 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3384 struct mlx5_bsf_inl *inl) 3385 { 3386 /* Valid inline section and allow BSF refresh */ 3387 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3388 MLX5_BSF_REFRESH_DIF); 3389 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3390 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3391 /* repeating block */ 3392 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3393 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3394 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3395 3396 if (domain->sig.dif.ref_remap) 3397 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3398 3399 if (domain->sig.dif.app_escape) { 3400 if (domain->sig.dif.ref_escape) 3401 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3402 else 3403 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3404 } 3405 3406 inl->dif_app_bitmask_check = 3407 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3408 } 3409 3410 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3411 struct ib_sig_attrs *sig_attrs, 3412 struct mlx5_bsf *bsf, u32 data_size) 3413 { 3414 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3415 struct mlx5_bsf_basic *basic = &bsf->basic; 3416 struct ib_sig_domain *mem = &sig_attrs->mem; 3417 struct ib_sig_domain *wire = &sig_attrs->wire; 3418 3419 memset(bsf, 0, sizeof(*bsf)); 3420 3421 /* Basic + Extended + Inline */ 3422 basic->bsf_size_sbs = 1 << 7; 3423 /* Input domain check byte mask */ 3424 basic->check_byte_mask = sig_attrs->check_mask; 3425 basic->raw_data_size = cpu_to_be32(data_size); 3426 3427 /* Memory domain */ 3428 switch (sig_attrs->mem.sig_type) { 3429 case IB_SIG_TYPE_NONE: 3430 break; 3431 case IB_SIG_TYPE_T10_DIF: 3432 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3433 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3434 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3435 break; 3436 default: 3437 return -EINVAL; 3438 } 3439 3440 /* Wire domain */ 3441 switch (sig_attrs->wire.sig_type) { 3442 case IB_SIG_TYPE_NONE: 3443 break; 3444 case IB_SIG_TYPE_T10_DIF: 3445 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3446 mem->sig_type == wire->sig_type) { 3447 /* Same block structure */ 3448 basic->bsf_size_sbs |= 1 << 4; 3449 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3450 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3451 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3452 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3453 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3454 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3455 } else 3456 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3457 3458 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3459 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3460 break; 3461 default: 3462 return -EINVAL; 3463 } 3464 3465 return 0; 3466 } 3467 3468 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3469 struct mlx5_ib_qp *qp, void **seg, int *size) 3470 { 3471 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3472 struct ib_mr *sig_mr = wr->sig_mr; 3473 struct mlx5_bsf *bsf; 3474 u32 data_len = wr->wr.sg_list->length; 3475 u32 data_key = wr->wr.sg_list->lkey; 3476 u64 data_va = wr->wr.sg_list->addr; 3477 int ret; 3478 int wqe_size; 3479 3480 if (!wr->prot || 3481 (data_key == wr->prot->lkey && 3482 data_va == wr->prot->addr && 3483 data_len == wr->prot->length)) { 3484 /** 3485 * Source domain doesn't contain signature information 3486 * or data and protection are interleaved in memory. 3487 * So need construct: 3488 * ------------------ 3489 * | data_klm | 3490 * ------------------ 3491 * | BSF | 3492 * ------------------ 3493 **/ 3494 struct mlx5_klm *data_klm = *seg; 3495 3496 data_klm->bcount = cpu_to_be32(data_len); 3497 data_klm->key = cpu_to_be32(data_key); 3498 data_klm->va = cpu_to_be64(data_va); 3499 wqe_size = ALIGN(sizeof(*data_klm), 64); 3500 } else { 3501 /** 3502 * Source domain contains signature information 3503 * So need construct a strided block format: 3504 * --------------------------- 3505 * | stride_block_ctrl | 3506 * --------------------------- 3507 * | data_klm | 3508 * --------------------------- 3509 * | prot_klm | 3510 * --------------------------- 3511 * | BSF | 3512 * --------------------------- 3513 **/ 3514 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3515 struct mlx5_stride_block_entry *data_sentry; 3516 struct mlx5_stride_block_entry *prot_sentry; 3517 u32 prot_key = wr->prot->lkey; 3518 u64 prot_va = wr->prot->addr; 3519 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3520 int prot_size; 3521 3522 sblock_ctrl = *seg; 3523 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3524 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3525 3526 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3527 if (!prot_size) { 3528 pr_err("Bad block size given: %u\n", block_size); 3529 return -EINVAL; 3530 } 3531 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3532 prot_size); 3533 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3534 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3535 sblock_ctrl->num_entries = cpu_to_be16(2); 3536 3537 data_sentry->bcount = cpu_to_be16(block_size); 3538 data_sentry->key = cpu_to_be32(data_key); 3539 data_sentry->va = cpu_to_be64(data_va); 3540 data_sentry->stride = cpu_to_be16(block_size); 3541 3542 prot_sentry->bcount = cpu_to_be16(prot_size); 3543 prot_sentry->key = cpu_to_be32(prot_key); 3544 prot_sentry->va = cpu_to_be64(prot_va); 3545 prot_sentry->stride = cpu_to_be16(prot_size); 3546 3547 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3548 sizeof(*prot_sentry), 64); 3549 } 3550 3551 *seg += wqe_size; 3552 *size += wqe_size / 16; 3553 if (unlikely((*seg == qp->sq.qend))) 3554 *seg = mlx5_get_send_wqe(qp, 0); 3555 3556 bsf = *seg; 3557 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3558 if (ret) 3559 return -EINVAL; 3560 3561 *seg += sizeof(*bsf); 3562 *size += sizeof(*bsf) / 16; 3563 if (unlikely((*seg == qp->sq.qend))) 3564 *seg = mlx5_get_send_wqe(qp, 0); 3565 3566 return 0; 3567 } 3568 3569 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3570 struct ib_sig_handover_wr *wr, u32 size, 3571 u32 length, u32 pdn) 3572 { 3573 struct ib_mr *sig_mr = wr->sig_mr; 3574 u32 sig_key = sig_mr->rkey; 3575 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3576 3577 memset(seg, 0, sizeof(*seg)); 3578 3579 seg->flags = get_umr_flags(wr->access_flags) | 3580 MLX5_MKC_ACCESS_MODE_KLMS; 3581 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3582 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3583 MLX5_MKEY_BSF_EN | pdn); 3584 seg->len = cpu_to_be64(length); 3585 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 3586 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3587 } 3588 3589 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3590 u32 size) 3591 { 3592 memset(umr, 0, sizeof(*umr)); 3593 3594 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3595 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3596 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3597 umr->mkey_mask = sig_mkey_mask(); 3598 } 3599 3600 3601 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3602 void **seg, int *size) 3603 { 3604 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3605 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3606 u32 pdn = get_pd(qp)->pdn; 3607 u32 xlt_size; 3608 int region_len, ret; 3609 3610 if (unlikely(wr->wr.num_sge != 1) || 3611 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3612 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3613 unlikely(!sig_mr->sig->sig_status_checked)) 3614 return -EINVAL; 3615 3616 /* length of the protected region, data + protection */ 3617 region_len = wr->wr.sg_list->length; 3618 if (wr->prot && 3619 (wr->prot->lkey != wr->wr.sg_list->lkey || 3620 wr->prot->addr != wr->wr.sg_list->addr || 3621 wr->prot->length != wr->wr.sg_list->length)) 3622 region_len += wr->prot->length; 3623 3624 /** 3625 * KLM octoword size - if protection was provided 3626 * then we use strided block format (3 octowords), 3627 * else we use single KLM (1 octoword) 3628 **/ 3629 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 3630 3631 set_sig_umr_segment(*seg, xlt_size); 3632 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3633 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3634 if (unlikely((*seg == qp->sq.qend))) 3635 *seg = mlx5_get_send_wqe(qp, 0); 3636 3637 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 3638 *seg += sizeof(struct mlx5_mkey_seg); 3639 *size += sizeof(struct mlx5_mkey_seg) / 16; 3640 if (unlikely((*seg == qp->sq.qend))) 3641 *seg = mlx5_get_send_wqe(qp, 0); 3642 3643 ret = set_sig_data_segment(wr, qp, seg, size); 3644 if (ret) 3645 return ret; 3646 3647 sig_mr->sig->sig_status_checked = false; 3648 return 0; 3649 } 3650 3651 static int set_psv_wr(struct ib_sig_domain *domain, 3652 u32 psv_idx, void **seg, int *size) 3653 { 3654 struct mlx5_seg_set_psv *psv_seg = *seg; 3655 3656 memset(psv_seg, 0, sizeof(*psv_seg)); 3657 psv_seg->psv_num = cpu_to_be32(psv_idx); 3658 switch (domain->sig_type) { 3659 case IB_SIG_TYPE_NONE: 3660 break; 3661 case IB_SIG_TYPE_T10_DIF: 3662 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3663 domain->sig.dif.app_tag); 3664 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3665 break; 3666 default: 3667 pr_err("Bad signature type given.\n"); 3668 return 1; 3669 } 3670 3671 *seg += sizeof(*psv_seg); 3672 *size += sizeof(*psv_seg) / 16; 3673 3674 return 0; 3675 } 3676 3677 static int set_reg_wr(struct mlx5_ib_qp *qp, 3678 struct ib_reg_wr *wr, 3679 void **seg, int *size) 3680 { 3681 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3682 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3683 3684 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3685 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3686 "Invalid IB_SEND_INLINE send flag\n"); 3687 return -EINVAL; 3688 } 3689 3690 set_reg_umr_seg(*seg, mr); 3691 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3692 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3693 if (unlikely((*seg == qp->sq.qend))) 3694 *seg = mlx5_get_send_wqe(qp, 0); 3695 3696 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3697 *seg += sizeof(struct mlx5_mkey_seg); 3698 *size += sizeof(struct mlx5_mkey_seg) / 16; 3699 if (unlikely((*seg == qp->sq.qend))) 3700 *seg = mlx5_get_send_wqe(qp, 0); 3701 3702 set_reg_data_seg(*seg, mr, pd); 3703 *seg += sizeof(struct mlx5_wqe_data_seg); 3704 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3705 3706 return 0; 3707 } 3708 3709 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3710 { 3711 set_linv_umr_seg(*seg); 3712 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3713 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3714 if (unlikely((*seg == qp->sq.qend))) 3715 *seg = mlx5_get_send_wqe(qp, 0); 3716 set_linv_mkey_seg(*seg); 3717 *seg += sizeof(struct mlx5_mkey_seg); 3718 *size += sizeof(struct mlx5_mkey_seg) / 16; 3719 if (unlikely((*seg == qp->sq.qend))) 3720 *seg = mlx5_get_send_wqe(qp, 0); 3721 } 3722 3723 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3724 { 3725 __be32 *p = NULL; 3726 int tidx = idx; 3727 int i, j; 3728 3729 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3730 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3731 if ((i & 0xf) == 0) { 3732 void *buf = mlx5_get_send_wqe(qp, tidx); 3733 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3734 p = buf; 3735 j = 0; 3736 } 3737 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3738 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3739 be32_to_cpu(p[j + 3])); 3740 } 3741 } 3742 3743 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 3744 unsigned bytecnt, struct mlx5_ib_qp *qp) 3745 { 3746 while (bytecnt > 0) { 3747 __iowrite64_copy(dst++, src++, 8); 3748 __iowrite64_copy(dst++, src++, 8); 3749 __iowrite64_copy(dst++, src++, 8); 3750 __iowrite64_copy(dst++, src++, 8); 3751 __iowrite64_copy(dst++, src++, 8); 3752 __iowrite64_copy(dst++, src++, 8); 3753 __iowrite64_copy(dst++, src++, 8); 3754 __iowrite64_copy(dst++, src++, 8); 3755 bytecnt -= 64; 3756 if (unlikely(src == qp->sq.qend)) 3757 src = mlx5_get_send_wqe(qp, 0); 3758 } 3759 } 3760 3761 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 3762 { 3763 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3764 wr->send_flags & IB_SEND_FENCE)) 3765 return MLX5_FENCE_MODE_STRONG_ORDERING; 3766 3767 if (unlikely(fence)) { 3768 if (wr->send_flags & IB_SEND_FENCE) 3769 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3770 else 3771 return fence; 3772 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3773 return MLX5_FENCE_MODE_FENCE; 3774 } 3775 3776 return 0; 3777 } 3778 3779 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3780 struct mlx5_wqe_ctrl_seg **ctrl, 3781 struct ib_send_wr *wr, unsigned *idx, 3782 int *size, int nreq) 3783 { 3784 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3785 return -ENOMEM; 3786 3787 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3788 *seg = mlx5_get_send_wqe(qp, *idx); 3789 *ctrl = *seg; 3790 *(uint32_t *)(*seg + 8) = 0; 3791 (*ctrl)->imm = send_ieth(wr); 3792 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3793 (wr->send_flags & IB_SEND_SIGNALED ? 3794 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3795 (wr->send_flags & IB_SEND_SOLICITED ? 3796 MLX5_WQE_CTRL_SOLICITED : 0); 3797 3798 *seg += sizeof(**ctrl); 3799 *size = sizeof(**ctrl) / 16; 3800 3801 return 0; 3802 } 3803 3804 static void finish_wqe(struct mlx5_ib_qp *qp, 3805 struct mlx5_wqe_ctrl_seg *ctrl, 3806 u8 size, unsigned idx, u64 wr_id, 3807 int nreq, u8 fence, u8 next_fence, 3808 u32 mlx5_opcode) 3809 { 3810 u8 opmod = 0; 3811 3812 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3813 mlx5_opcode | ((u32)opmod << 24)); 3814 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3815 ctrl->fm_ce_se |= fence; 3816 qp->fm_cache = next_fence; 3817 if (unlikely(qp->wq_sig)) 3818 ctrl->signature = wq_sig(ctrl); 3819 3820 qp->sq.wrid[idx] = wr_id; 3821 qp->sq.w_list[idx].opcode = mlx5_opcode; 3822 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3823 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3824 qp->sq.w_list[idx].next = qp->sq.cur_post; 3825 } 3826 3827 3828 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3829 struct ib_send_wr **bad_wr) 3830 { 3831 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3832 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3833 struct mlx5_core_dev *mdev = dev->mdev; 3834 struct mlx5_ib_qp *qp; 3835 struct mlx5_ib_mr *mr; 3836 struct mlx5_wqe_data_seg *dpseg; 3837 struct mlx5_wqe_xrc_seg *xrc; 3838 struct mlx5_bf *bf; 3839 int uninitialized_var(size); 3840 void *qend; 3841 unsigned long flags; 3842 unsigned idx; 3843 int err = 0; 3844 int inl = 0; 3845 int num_sge; 3846 void *seg; 3847 int nreq; 3848 int i; 3849 u8 next_fence = 0; 3850 u8 fence; 3851 3852 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3853 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3854 3855 qp = to_mqp(ibqp); 3856 bf = qp->bf; 3857 qend = qp->sq.qend; 3858 3859 spin_lock_irqsave(&qp->sq.lock, flags); 3860 3861 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3862 err = -EIO; 3863 *bad_wr = wr; 3864 nreq = 0; 3865 goto out; 3866 } 3867 3868 for (nreq = 0; wr; nreq++, wr = wr->next) { 3869 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3870 mlx5_ib_warn(dev, "\n"); 3871 err = -EINVAL; 3872 *bad_wr = wr; 3873 goto out; 3874 } 3875 3876 fence = qp->fm_cache; 3877 num_sge = wr->num_sge; 3878 if (unlikely(num_sge > qp->sq.max_gs)) { 3879 mlx5_ib_warn(dev, "\n"); 3880 err = -EINVAL; 3881 *bad_wr = wr; 3882 goto out; 3883 } 3884 3885 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3886 if (err) { 3887 mlx5_ib_warn(dev, "\n"); 3888 err = -ENOMEM; 3889 *bad_wr = wr; 3890 goto out; 3891 } 3892 3893 switch (ibqp->qp_type) { 3894 case IB_QPT_XRC_INI: 3895 xrc = seg; 3896 seg += sizeof(*xrc); 3897 size += sizeof(*xrc) / 16; 3898 /* fall through */ 3899 case IB_QPT_RC: 3900 switch (wr->opcode) { 3901 case IB_WR_RDMA_READ: 3902 case IB_WR_RDMA_WRITE: 3903 case IB_WR_RDMA_WRITE_WITH_IMM: 3904 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3905 rdma_wr(wr)->rkey); 3906 seg += sizeof(struct mlx5_wqe_raddr_seg); 3907 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3908 break; 3909 3910 case IB_WR_ATOMIC_CMP_AND_SWP: 3911 case IB_WR_ATOMIC_FETCH_AND_ADD: 3912 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3913 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3914 err = -ENOSYS; 3915 *bad_wr = wr; 3916 goto out; 3917 3918 case IB_WR_LOCAL_INV: 3919 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3920 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3921 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3922 set_linv_wr(qp, &seg, &size); 3923 num_sge = 0; 3924 break; 3925 3926 case IB_WR_REG_MR: 3927 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3928 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3929 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3930 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3931 if (err) { 3932 *bad_wr = wr; 3933 goto out; 3934 } 3935 num_sge = 0; 3936 break; 3937 3938 case IB_WR_REG_SIG_MR: 3939 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3940 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3941 3942 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3943 err = set_sig_umr_wr(wr, qp, &seg, &size); 3944 if (err) { 3945 mlx5_ib_warn(dev, "\n"); 3946 *bad_wr = wr; 3947 goto out; 3948 } 3949 3950 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3951 nreq, get_fence(fence, wr), 3952 next_fence, MLX5_OPCODE_UMR); 3953 /* 3954 * SET_PSV WQEs are not signaled and solicited 3955 * on error 3956 */ 3957 wr->send_flags &= ~IB_SEND_SIGNALED; 3958 wr->send_flags |= IB_SEND_SOLICITED; 3959 err = begin_wqe(qp, &seg, &ctrl, wr, 3960 &idx, &size, nreq); 3961 if (err) { 3962 mlx5_ib_warn(dev, "\n"); 3963 err = -ENOMEM; 3964 *bad_wr = wr; 3965 goto out; 3966 } 3967 3968 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 3969 mr->sig->psv_memory.psv_idx, &seg, 3970 &size); 3971 if (err) { 3972 mlx5_ib_warn(dev, "\n"); 3973 *bad_wr = wr; 3974 goto out; 3975 } 3976 3977 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3978 nreq, get_fence(fence, wr), 3979 next_fence, MLX5_OPCODE_SET_PSV); 3980 err = begin_wqe(qp, &seg, &ctrl, wr, 3981 &idx, &size, nreq); 3982 if (err) { 3983 mlx5_ib_warn(dev, "\n"); 3984 err = -ENOMEM; 3985 *bad_wr = wr; 3986 goto out; 3987 } 3988 3989 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3990 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 3991 mr->sig->psv_wire.psv_idx, &seg, 3992 &size); 3993 if (err) { 3994 mlx5_ib_warn(dev, "\n"); 3995 *bad_wr = wr; 3996 goto out; 3997 } 3998 3999 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4000 nreq, get_fence(fence, wr), 4001 next_fence, MLX5_OPCODE_SET_PSV); 4002 num_sge = 0; 4003 goto skip_psv; 4004 4005 default: 4006 break; 4007 } 4008 break; 4009 4010 case IB_QPT_UC: 4011 switch (wr->opcode) { 4012 case IB_WR_RDMA_WRITE: 4013 case IB_WR_RDMA_WRITE_WITH_IMM: 4014 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4015 rdma_wr(wr)->rkey); 4016 seg += sizeof(struct mlx5_wqe_raddr_seg); 4017 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4018 break; 4019 4020 default: 4021 break; 4022 } 4023 break; 4024 4025 case IB_QPT_SMI: 4026 case MLX5_IB_QPT_HW_GSI: 4027 set_datagram_seg(seg, wr); 4028 seg += sizeof(struct mlx5_wqe_datagram_seg); 4029 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4030 if (unlikely((seg == qend))) 4031 seg = mlx5_get_send_wqe(qp, 0); 4032 break; 4033 case IB_QPT_UD: 4034 set_datagram_seg(seg, wr); 4035 seg += sizeof(struct mlx5_wqe_datagram_seg); 4036 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4037 4038 if (unlikely((seg == qend))) 4039 seg = mlx5_get_send_wqe(qp, 0); 4040 4041 /* handle qp that supports ud offload */ 4042 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4043 struct mlx5_wqe_eth_pad *pad; 4044 4045 pad = seg; 4046 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4047 seg += sizeof(struct mlx5_wqe_eth_pad); 4048 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4049 4050 seg = set_eth_seg(seg, wr, qend, qp, &size); 4051 4052 if (unlikely((seg == qend))) 4053 seg = mlx5_get_send_wqe(qp, 0); 4054 } 4055 break; 4056 case MLX5_IB_QPT_REG_UMR: 4057 if (wr->opcode != MLX5_IB_WR_UMR) { 4058 err = -EINVAL; 4059 mlx5_ib_warn(dev, "bad opcode\n"); 4060 goto out; 4061 } 4062 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4063 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4064 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4065 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4066 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4067 if (unlikely((seg == qend))) 4068 seg = mlx5_get_send_wqe(qp, 0); 4069 set_reg_mkey_segment(seg, wr); 4070 seg += sizeof(struct mlx5_mkey_seg); 4071 size += sizeof(struct mlx5_mkey_seg) / 16; 4072 if (unlikely((seg == qend))) 4073 seg = mlx5_get_send_wqe(qp, 0); 4074 break; 4075 4076 default: 4077 break; 4078 } 4079 4080 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4081 int uninitialized_var(sz); 4082 4083 err = set_data_inl_seg(qp, wr, seg, &sz); 4084 if (unlikely(err)) { 4085 mlx5_ib_warn(dev, "\n"); 4086 *bad_wr = wr; 4087 goto out; 4088 } 4089 inl = 1; 4090 size += sz; 4091 } else { 4092 dpseg = seg; 4093 for (i = 0; i < num_sge; i++) { 4094 if (unlikely(dpseg == qend)) { 4095 seg = mlx5_get_send_wqe(qp, 0); 4096 dpseg = seg; 4097 } 4098 if (likely(wr->sg_list[i].length)) { 4099 set_data_ptr_seg(dpseg, wr->sg_list + i); 4100 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4101 dpseg++; 4102 } 4103 } 4104 } 4105 4106 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4107 get_fence(fence, wr), next_fence, 4108 mlx5_ib_opcode[wr->opcode]); 4109 skip_psv: 4110 if (0) 4111 dump_wqe(qp, idx, size); 4112 } 4113 4114 out: 4115 if (likely(nreq)) { 4116 qp->sq.head += nreq; 4117 4118 /* Make sure that descriptors are written before 4119 * updating doorbell record and ringing the doorbell 4120 */ 4121 wmb(); 4122 4123 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4124 4125 /* Make sure doorbell record is visible to the HCA before 4126 * we hit doorbell */ 4127 wmb(); 4128 4129 if (bf->need_lock) 4130 spin_lock(&bf->lock); 4131 else 4132 __acquire(&bf->lock); 4133 4134 /* TBD enable WC */ 4135 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 4136 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 4137 /* wc_wmb(); */ 4138 } else { 4139 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 4140 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4141 /* Make sure doorbells don't leak out of SQ spinlock 4142 * and reach the HCA out of order. 4143 */ 4144 mmiowb(); 4145 } 4146 bf->offset ^= bf->buf_size; 4147 if (bf->need_lock) 4148 spin_unlock(&bf->lock); 4149 else 4150 __release(&bf->lock); 4151 } 4152 4153 spin_unlock_irqrestore(&qp->sq.lock, flags); 4154 4155 return err; 4156 } 4157 4158 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4159 { 4160 sig->signature = calc_sig(sig, size); 4161 } 4162 4163 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4164 struct ib_recv_wr **bad_wr) 4165 { 4166 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4167 struct mlx5_wqe_data_seg *scat; 4168 struct mlx5_rwqe_sig *sig; 4169 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4170 struct mlx5_core_dev *mdev = dev->mdev; 4171 unsigned long flags; 4172 int err = 0; 4173 int nreq; 4174 int ind; 4175 int i; 4176 4177 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4178 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4179 4180 spin_lock_irqsave(&qp->rq.lock, flags); 4181 4182 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4183 err = -EIO; 4184 *bad_wr = wr; 4185 nreq = 0; 4186 goto out; 4187 } 4188 4189 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4190 4191 for (nreq = 0; wr; nreq++, wr = wr->next) { 4192 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4193 err = -ENOMEM; 4194 *bad_wr = wr; 4195 goto out; 4196 } 4197 4198 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4199 err = -EINVAL; 4200 *bad_wr = wr; 4201 goto out; 4202 } 4203 4204 scat = get_recv_wqe(qp, ind); 4205 if (qp->wq_sig) 4206 scat++; 4207 4208 for (i = 0; i < wr->num_sge; i++) 4209 set_data_ptr_seg(scat + i, wr->sg_list + i); 4210 4211 if (i < qp->rq.max_gs) { 4212 scat[i].byte_count = 0; 4213 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4214 scat[i].addr = 0; 4215 } 4216 4217 if (qp->wq_sig) { 4218 sig = (struct mlx5_rwqe_sig *)scat; 4219 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4220 } 4221 4222 qp->rq.wrid[ind] = wr->wr_id; 4223 4224 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4225 } 4226 4227 out: 4228 if (likely(nreq)) { 4229 qp->rq.head += nreq; 4230 4231 /* Make sure that descriptors are written before 4232 * doorbell record. 4233 */ 4234 wmb(); 4235 4236 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4237 } 4238 4239 spin_unlock_irqrestore(&qp->rq.lock, flags); 4240 4241 return err; 4242 } 4243 4244 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4245 { 4246 switch (mlx5_state) { 4247 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4248 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4249 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4250 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4251 case MLX5_QP_STATE_SQ_DRAINING: 4252 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4253 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4254 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4255 default: return -1; 4256 } 4257 } 4258 4259 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4260 { 4261 switch (mlx5_mig_state) { 4262 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4263 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4264 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4265 default: return -1; 4266 } 4267 } 4268 4269 static int to_ib_qp_access_flags(int mlx5_flags) 4270 { 4271 int ib_flags = 0; 4272 4273 if (mlx5_flags & MLX5_QP_BIT_RRE) 4274 ib_flags |= IB_ACCESS_REMOTE_READ; 4275 if (mlx5_flags & MLX5_QP_BIT_RWE) 4276 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4277 if (mlx5_flags & MLX5_QP_BIT_RAE) 4278 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4279 4280 return ib_flags; 4281 } 4282 4283 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4284 struct mlx5_qp_path *path) 4285 { 4286 struct mlx5_core_dev *dev = ibdev->mdev; 4287 4288 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4289 ib_ah_attr->port_num = path->port; 4290 4291 if (ib_ah_attr->port_num == 0 || 4292 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4293 return; 4294 4295 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4296 4297 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4298 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4299 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4300 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4301 if (ib_ah_attr->ah_flags) { 4302 ib_ah_attr->grh.sgid_index = path->mgid_index; 4303 ib_ah_attr->grh.hop_limit = path->hop_limit; 4304 ib_ah_attr->grh.traffic_class = 4305 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4306 ib_ah_attr->grh.flow_label = 4307 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4308 memcpy(ib_ah_attr->grh.dgid.raw, 4309 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4310 } 4311 } 4312 4313 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4314 struct mlx5_ib_sq *sq, 4315 u8 *sq_state) 4316 { 4317 void *out; 4318 void *sqc; 4319 int inlen; 4320 int err; 4321 4322 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4323 out = mlx5_vzalloc(inlen); 4324 if (!out) 4325 return -ENOMEM; 4326 4327 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4328 if (err) 4329 goto out; 4330 4331 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4332 *sq_state = MLX5_GET(sqc, sqc, state); 4333 sq->state = *sq_state; 4334 4335 out: 4336 kvfree(out); 4337 return err; 4338 } 4339 4340 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4341 struct mlx5_ib_rq *rq, 4342 u8 *rq_state) 4343 { 4344 void *out; 4345 void *rqc; 4346 int inlen; 4347 int err; 4348 4349 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4350 out = mlx5_vzalloc(inlen); 4351 if (!out) 4352 return -ENOMEM; 4353 4354 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4355 if (err) 4356 goto out; 4357 4358 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4359 *rq_state = MLX5_GET(rqc, rqc, state); 4360 rq->state = *rq_state; 4361 4362 out: 4363 kvfree(out); 4364 return err; 4365 } 4366 4367 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4368 struct mlx5_ib_qp *qp, u8 *qp_state) 4369 { 4370 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4371 [MLX5_RQC_STATE_RST] = { 4372 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4373 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4374 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4375 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4376 }, 4377 [MLX5_RQC_STATE_RDY] = { 4378 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4379 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4380 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4381 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4382 }, 4383 [MLX5_RQC_STATE_ERR] = { 4384 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4385 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4386 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4387 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4388 }, 4389 [MLX5_RQ_STATE_NA] = { 4390 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4391 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4392 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4393 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4394 }, 4395 }; 4396 4397 *qp_state = sqrq_trans[rq_state][sq_state]; 4398 4399 if (*qp_state == MLX5_QP_STATE_BAD) { 4400 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4401 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4402 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4403 return -EINVAL; 4404 } 4405 4406 if (*qp_state == MLX5_QP_STATE) 4407 *qp_state = qp->state; 4408 4409 return 0; 4410 } 4411 4412 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4413 struct mlx5_ib_qp *qp, 4414 u8 *raw_packet_qp_state) 4415 { 4416 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4417 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4418 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4419 int err; 4420 u8 sq_state = MLX5_SQ_STATE_NA; 4421 u8 rq_state = MLX5_RQ_STATE_NA; 4422 4423 if (qp->sq.wqe_cnt) { 4424 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4425 if (err) 4426 return err; 4427 } 4428 4429 if (qp->rq.wqe_cnt) { 4430 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4431 if (err) 4432 return err; 4433 } 4434 4435 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4436 raw_packet_qp_state); 4437 } 4438 4439 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4440 struct ib_qp_attr *qp_attr) 4441 { 4442 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4443 struct mlx5_qp_context *context; 4444 int mlx5_state; 4445 u32 *outb; 4446 int err = 0; 4447 4448 outb = kzalloc(outlen, GFP_KERNEL); 4449 if (!outb) 4450 return -ENOMEM; 4451 4452 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4453 outlen); 4454 if (err) 4455 goto out; 4456 4457 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4458 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4459 4460 mlx5_state = be32_to_cpu(context->flags) >> 28; 4461 4462 qp->state = to_ib_qp_state(mlx5_state); 4463 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4464 qp_attr->path_mig_state = 4465 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4466 qp_attr->qkey = be32_to_cpu(context->qkey); 4467 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4468 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4469 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4470 qp_attr->qp_access_flags = 4471 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4472 4473 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4474 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4475 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4476 qp_attr->alt_pkey_index = 4477 be16_to_cpu(context->alt_path.pkey_index); 4478 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4479 } 4480 4481 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4482 qp_attr->port_num = context->pri_path.port; 4483 4484 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4485 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4486 4487 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4488 4489 qp_attr->max_dest_rd_atomic = 4490 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4491 qp_attr->min_rnr_timer = 4492 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4493 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4494 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4495 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4496 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4497 4498 out: 4499 kfree(outb); 4500 return err; 4501 } 4502 4503 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4504 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4505 { 4506 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4507 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4508 int err = 0; 4509 u8 raw_packet_qp_state; 4510 4511 if (ibqp->rwq_ind_tbl) 4512 return -ENOSYS; 4513 4514 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4515 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4516 qp_init_attr); 4517 4518 mutex_lock(&qp->mutex); 4519 4520 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4521 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4522 if (err) 4523 goto out; 4524 qp->state = raw_packet_qp_state; 4525 qp_attr->port_num = 1; 4526 } else { 4527 err = query_qp_attr(dev, qp, qp_attr); 4528 if (err) 4529 goto out; 4530 } 4531 4532 qp_attr->qp_state = qp->state; 4533 qp_attr->cur_qp_state = qp_attr->qp_state; 4534 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4535 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4536 4537 if (!ibqp->uobject) { 4538 qp_attr->cap.max_send_wr = qp->sq.max_post; 4539 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4540 qp_init_attr->qp_context = ibqp->qp_context; 4541 } else { 4542 qp_attr->cap.max_send_wr = 0; 4543 qp_attr->cap.max_send_sge = 0; 4544 } 4545 4546 qp_init_attr->qp_type = ibqp->qp_type; 4547 qp_init_attr->recv_cq = ibqp->recv_cq; 4548 qp_init_attr->send_cq = ibqp->send_cq; 4549 qp_init_attr->srq = ibqp->srq; 4550 qp_attr->cap.max_inline_data = qp->max_inline_data; 4551 4552 qp_init_attr->cap = qp_attr->cap; 4553 4554 qp_init_attr->create_flags = 0; 4555 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4556 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4557 4558 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4559 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4560 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4561 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4562 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4563 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4564 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4565 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 4566 4567 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4568 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4569 4570 out: 4571 mutex_unlock(&qp->mutex); 4572 return err; 4573 } 4574 4575 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4576 struct ib_ucontext *context, 4577 struct ib_udata *udata) 4578 { 4579 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4580 struct mlx5_ib_xrcd *xrcd; 4581 int err; 4582 4583 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4584 return ERR_PTR(-ENOSYS); 4585 4586 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4587 if (!xrcd) 4588 return ERR_PTR(-ENOMEM); 4589 4590 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4591 if (err) { 4592 kfree(xrcd); 4593 return ERR_PTR(-ENOMEM); 4594 } 4595 4596 return &xrcd->ibxrcd; 4597 } 4598 4599 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4600 { 4601 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4602 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4603 int err; 4604 4605 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4606 if (err) { 4607 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4608 return err; 4609 } 4610 4611 kfree(xrcd); 4612 4613 return 0; 4614 } 4615 4616 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4617 { 4618 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4619 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4620 struct ib_event event; 4621 4622 if (rwq->ibwq.event_handler) { 4623 event.device = rwq->ibwq.device; 4624 event.element.wq = &rwq->ibwq; 4625 switch (type) { 4626 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4627 event.event = IB_EVENT_WQ_FATAL; 4628 break; 4629 default: 4630 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4631 return; 4632 } 4633 4634 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4635 } 4636 } 4637 4638 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4639 struct ib_wq_init_attr *init_attr) 4640 { 4641 struct mlx5_ib_dev *dev; 4642 __be64 *rq_pas0; 4643 void *in; 4644 void *rqc; 4645 void *wq; 4646 int inlen; 4647 int err; 4648 4649 dev = to_mdev(pd->device); 4650 4651 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4652 in = mlx5_vzalloc(inlen); 4653 if (!in) 4654 return -ENOMEM; 4655 4656 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4657 MLX5_SET(rqc, rqc, mem_rq_type, 4658 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4659 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4660 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4661 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4662 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4663 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4664 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4665 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4666 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4667 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4668 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4669 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4670 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4671 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4672 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4673 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4674 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4675 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4676 kvfree(in); 4677 return err; 4678 } 4679 4680 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4681 struct ib_wq_init_attr *wq_init_attr, 4682 struct mlx5_ib_create_wq *ucmd, 4683 struct mlx5_ib_rwq *rwq) 4684 { 4685 /* Sanity check RQ size before proceeding */ 4686 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4687 return -EINVAL; 4688 4689 if (!ucmd->rq_wqe_count) 4690 return -EINVAL; 4691 4692 rwq->wqe_count = ucmd->rq_wqe_count; 4693 rwq->wqe_shift = ucmd->rq_wqe_shift; 4694 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4695 rwq->log_rq_stride = rwq->wqe_shift; 4696 rwq->log_rq_size = ilog2(rwq->wqe_count); 4697 return 0; 4698 } 4699 4700 static int prepare_user_rq(struct ib_pd *pd, 4701 struct ib_wq_init_attr *init_attr, 4702 struct ib_udata *udata, 4703 struct mlx5_ib_rwq *rwq) 4704 { 4705 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4706 struct mlx5_ib_create_wq ucmd = {}; 4707 int err; 4708 size_t required_cmd_sz; 4709 4710 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4711 if (udata->inlen < required_cmd_sz) { 4712 mlx5_ib_dbg(dev, "invalid inlen\n"); 4713 return -EINVAL; 4714 } 4715 4716 if (udata->inlen > sizeof(ucmd) && 4717 !ib_is_udata_cleared(udata, sizeof(ucmd), 4718 udata->inlen - sizeof(ucmd))) { 4719 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4720 return -EOPNOTSUPP; 4721 } 4722 4723 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4724 mlx5_ib_dbg(dev, "copy failed\n"); 4725 return -EFAULT; 4726 } 4727 4728 if (ucmd.comp_mask) { 4729 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4730 return -EOPNOTSUPP; 4731 } 4732 4733 if (ucmd.reserved) { 4734 mlx5_ib_dbg(dev, "invalid reserved\n"); 4735 return -EOPNOTSUPP; 4736 } 4737 4738 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4739 if (err) { 4740 mlx5_ib_dbg(dev, "err %d\n", err); 4741 return err; 4742 } 4743 4744 err = create_user_rq(dev, pd, rwq, &ucmd); 4745 if (err) { 4746 mlx5_ib_dbg(dev, "err %d\n", err); 4747 if (err) 4748 return err; 4749 } 4750 4751 rwq->user_index = ucmd.user_index; 4752 return 0; 4753 } 4754 4755 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4756 struct ib_wq_init_attr *init_attr, 4757 struct ib_udata *udata) 4758 { 4759 struct mlx5_ib_dev *dev; 4760 struct mlx5_ib_rwq *rwq; 4761 struct mlx5_ib_create_wq_resp resp = {}; 4762 size_t min_resp_len; 4763 int err; 4764 4765 if (!udata) 4766 return ERR_PTR(-ENOSYS); 4767 4768 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4769 if (udata->outlen && udata->outlen < min_resp_len) 4770 return ERR_PTR(-EINVAL); 4771 4772 dev = to_mdev(pd->device); 4773 switch (init_attr->wq_type) { 4774 case IB_WQT_RQ: 4775 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4776 if (!rwq) 4777 return ERR_PTR(-ENOMEM); 4778 err = prepare_user_rq(pd, init_attr, udata, rwq); 4779 if (err) 4780 goto err; 4781 err = create_rq(rwq, pd, init_attr); 4782 if (err) 4783 goto err_user_rq; 4784 break; 4785 default: 4786 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4787 init_attr->wq_type); 4788 return ERR_PTR(-EINVAL); 4789 } 4790 4791 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4792 rwq->ibwq.state = IB_WQS_RESET; 4793 if (udata->outlen) { 4794 resp.response_length = offsetof(typeof(resp), response_length) + 4795 sizeof(resp.response_length); 4796 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4797 if (err) 4798 goto err_copy; 4799 } 4800 4801 rwq->core_qp.event = mlx5_ib_wq_event; 4802 rwq->ibwq.event_handler = init_attr->event_handler; 4803 return &rwq->ibwq; 4804 4805 err_copy: 4806 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4807 err_user_rq: 4808 destroy_user_rq(pd, rwq); 4809 err: 4810 kfree(rwq); 4811 return ERR_PTR(err); 4812 } 4813 4814 int mlx5_ib_destroy_wq(struct ib_wq *wq) 4815 { 4816 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4817 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4818 4819 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4820 destroy_user_rq(wq->pd, rwq); 4821 kfree(rwq); 4822 4823 return 0; 4824 } 4825 4826 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4827 struct ib_rwq_ind_table_init_attr *init_attr, 4828 struct ib_udata *udata) 4829 { 4830 struct mlx5_ib_dev *dev = to_mdev(device); 4831 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4832 int sz = 1 << init_attr->log_ind_tbl_size; 4833 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4834 size_t min_resp_len; 4835 int inlen; 4836 int err; 4837 int i; 4838 u32 *in; 4839 void *rqtc; 4840 4841 if (udata->inlen > 0 && 4842 !ib_is_udata_cleared(udata, 0, 4843 udata->inlen)) 4844 return ERR_PTR(-EOPNOTSUPP); 4845 4846 if (init_attr->log_ind_tbl_size > 4847 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4848 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4849 init_attr->log_ind_tbl_size, 4850 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4851 return ERR_PTR(-EINVAL); 4852 } 4853 4854 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4855 if (udata->outlen && udata->outlen < min_resp_len) 4856 return ERR_PTR(-EINVAL); 4857 4858 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4859 if (!rwq_ind_tbl) 4860 return ERR_PTR(-ENOMEM); 4861 4862 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4863 in = mlx5_vzalloc(inlen); 4864 if (!in) { 4865 err = -ENOMEM; 4866 goto err; 4867 } 4868 4869 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4870 4871 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4872 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4873 4874 for (i = 0; i < sz; i++) 4875 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4876 4877 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4878 kvfree(in); 4879 4880 if (err) 4881 goto err; 4882 4883 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4884 if (udata->outlen) { 4885 resp.response_length = offsetof(typeof(resp), response_length) + 4886 sizeof(resp.response_length); 4887 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4888 if (err) 4889 goto err_copy; 4890 } 4891 4892 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4893 4894 err_copy: 4895 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4896 err: 4897 kfree(rwq_ind_tbl); 4898 return ERR_PTR(err); 4899 } 4900 4901 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4902 { 4903 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4904 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4905 4906 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4907 4908 kfree(rwq_ind_tbl); 4909 return 0; 4910 } 4911 4912 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4913 u32 wq_attr_mask, struct ib_udata *udata) 4914 { 4915 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4916 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4917 struct mlx5_ib_modify_wq ucmd = {}; 4918 size_t required_cmd_sz; 4919 int curr_wq_state; 4920 int wq_state; 4921 int inlen; 4922 int err; 4923 void *rqc; 4924 void *in; 4925 4926 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4927 if (udata->inlen < required_cmd_sz) 4928 return -EINVAL; 4929 4930 if (udata->inlen > sizeof(ucmd) && 4931 !ib_is_udata_cleared(udata, sizeof(ucmd), 4932 udata->inlen - sizeof(ucmd))) 4933 return -EOPNOTSUPP; 4934 4935 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4936 return -EFAULT; 4937 4938 if (ucmd.comp_mask || ucmd.reserved) 4939 return -EOPNOTSUPP; 4940 4941 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 4942 in = mlx5_vzalloc(inlen); 4943 if (!in) 4944 return -ENOMEM; 4945 4946 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4947 4948 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 4949 wq_attr->curr_wq_state : wq->state; 4950 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 4951 wq_attr->wq_state : curr_wq_state; 4952 if (curr_wq_state == IB_WQS_ERR) 4953 curr_wq_state = MLX5_RQC_STATE_ERR; 4954 if (wq_state == IB_WQS_ERR) 4955 wq_state = MLX5_RQC_STATE_ERR; 4956 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 4957 MLX5_SET(rqc, rqc, state, wq_state); 4958 4959 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 4960 kvfree(in); 4961 if (!err) 4962 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 4963 4964 return err; 4965 } 4966