1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include "mlx5_ib.h" 36 #include "user.h" 37 38 /* not supported currently */ 39 static int wq_signature; 40 41 enum { 42 MLX5_IB_ACK_REQ_FREQ = 8, 43 }; 44 45 enum { 46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 48 MLX5_IB_LINK_TYPE_IB = 0, 49 MLX5_IB_LINK_TYPE_ETH = 1 50 }; 51 52 enum { 53 MLX5_IB_SQ_STRIDE = 6, 54 MLX5_IB_CACHE_LINE_SIZE = 64, 55 }; 56 57 static const u32 mlx5_ib_opcode[] = { 58 [IB_WR_SEND] = MLX5_OPCODE_SEND, 59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR, 68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 71 }; 72 73 74 static int is_qp0(enum ib_qp_type qp_type) 75 { 76 return qp_type == IB_QPT_SMI; 77 } 78 79 static int is_qp1(enum ib_qp_type qp_type) 80 { 81 return qp_type == IB_QPT_GSI; 82 } 83 84 static int is_sqp(enum ib_qp_type qp_type) 85 { 86 return is_qp0(qp_type) || is_qp1(qp_type); 87 } 88 89 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 90 { 91 return mlx5_buf_offset(&qp->buf, offset); 92 } 93 94 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 95 { 96 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 97 } 98 99 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 100 { 101 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 102 } 103 104 /** 105 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 106 * 107 * @qp: QP to copy from. 108 * @send: copy from the send queue when non-zero, use the receive queue 109 * otherwise. 110 * @wqe_index: index to start copying from. For send work queues, the 111 * wqe_index is in units of MLX5_SEND_WQE_BB. 112 * For receive work queue, it is the number of work queue 113 * element in the queue. 114 * @buffer: destination buffer. 115 * @length: maximum number of bytes to copy. 116 * 117 * Copies at least a single WQE, but may copy more data. 118 * 119 * Return: the number of bytes copied, or an error code. 120 */ 121 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 122 void *buffer, u32 length) 123 { 124 struct ib_device *ibdev = qp->ibqp.device; 125 struct mlx5_ib_dev *dev = to_mdev(ibdev); 126 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 127 size_t offset; 128 size_t wq_end; 129 struct ib_umem *umem = qp->umem; 130 u32 first_copy_length; 131 int wqe_length; 132 int ret; 133 134 if (wq->wqe_cnt == 0) { 135 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 136 qp->ibqp.qp_type); 137 return -EINVAL; 138 } 139 140 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 141 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 142 143 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 144 return -EINVAL; 145 146 if (offset > umem->length || 147 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 148 return -EINVAL; 149 150 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 151 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 152 if (ret) 153 return ret; 154 155 if (send) { 156 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 157 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 158 159 wqe_length = ds * MLX5_WQE_DS_UNITS; 160 } else { 161 wqe_length = 1 << wq->wqe_shift; 162 } 163 164 if (wqe_length <= first_copy_length) 165 return first_copy_length; 166 167 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 168 wqe_length - first_copy_length); 169 if (ret) 170 return ret; 171 172 return wqe_length; 173 } 174 175 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 176 { 177 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 178 struct ib_event event; 179 180 if (type == MLX5_EVENT_TYPE_PATH_MIG) 181 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 182 183 if (ibqp->event_handler) { 184 event.device = ibqp->device; 185 event.element.qp = ibqp; 186 switch (type) { 187 case MLX5_EVENT_TYPE_PATH_MIG: 188 event.event = IB_EVENT_PATH_MIG; 189 break; 190 case MLX5_EVENT_TYPE_COMM_EST: 191 event.event = IB_EVENT_COMM_EST; 192 break; 193 case MLX5_EVENT_TYPE_SQ_DRAINED: 194 event.event = IB_EVENT_SQ_DRAINED; 195 break; 196 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 197 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 198 break; 199 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 200 event.event = IB_EVENT_QP_FATAL; 201 break; 202 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 203 event.event = IB_EVENT_PATH_MIG_ERR; 204 break; 205 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 206 event.event = IB_EVENT_QP_REQ_ERR; 207 break; 208 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 209 event.event = IB_EVENT_QP_ACCESS_ERR; 210 break; 211 default: 212 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 213 return; 214 } 215 216 ibqp->event_handler(&event, ibqp->qp_context); 217 } 218 } 219 220 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 221 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 222 { 223 int wqe_size; 224 int wq_size; 225 226 /* Sanity check RQ size before proceeding */ 227 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 228 return -EINVAL; 229 230 if (!has_rq) { 231 qp->rq.max_gs = 0; 232 qp->rq.wqe_cnt = 0; 233 qp->rq.wqe_shift = 0; 234 } else { 235 if (ucmd) { 236 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 237 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 238 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 239 qp->rq.max_post = qp->rq.wqe_cnt; 240 } else { 241 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 242 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 243 wqe_size = roundup_pow_of_two(wqe_size); 244 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 245 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 246 qp->rq.wqe_cnt = wq_size / wqe_size; 247 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 248 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 249 wqe_size, 250 MLX5_CAP_GEN(dev->mdev, 251 max_wqe_sz_rq)); 252 return -EINVAL; 253 } 254 qp->rq.wqe_shift = ilog2(wqe_size); 255 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 256 qp->rq.max_post = qp->rq.wqe_cnt; 257 } 258 } 259 260 return 0; 261 } 262 263 static int sq_overhead(enum ib_qp_type qp_type) 264 { 265 int size = 0; 266 267 switch (qp_type) { 268 case IB_QPT_XRC_INI: 269 size += sizeof(struct mlx5_wqe_xrc_seg); 270 /* fall through */ 271 case IB_QPT_RC: 272 size += sizeof(struct mlx5_wqe_ctrl_seg) + 273 sizeof(struct mlx5_wqe_atomic_seg) + 274 sizeof(struct mlx5_wqe_raddr_seg); 275 break; 276 277 case IB_QPT_XRC_TGT: 278 return 0; 279 280 case IB_QPT_UC: 281 size += sizeof(struct mlx5_wqe_ctrl_seg) + 282 sizeof(struct mlx5_wqe_raddr_seg) + 283 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 284 sizeof(struct mlx5_mkey_seg); 285 break; 286 287 case IB_QPT_UD: 288 case IB_QPT_SMI: 289 case IB_QPT_GSI: 290 size += sizeof(struct mlx5_wqe_ctrl_seg) + 291 sizeof(struct mlx5_wqe_datagram_seg); 292 break; 293 294 case MLX5_IB_QPT_REG_UMR: 295 size += sizeof(struct mlx5_wqe_ctrl_seg) + 296 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 297 sizeof(struct mlx5_mkey_seg); 298 break; 299 300 default: 301 return -EINVAL; 302 } 303 304 return size; 305 } 306 307 static int calc_send_wqe(struct ib_qp_init_attr *attr) 308 { 309 int inl_size = 0; 310 int size; 311 312 size = sq_overhead(attr->qp_type); 313 if (size < 0) 314 return size; 315 316 if (attr->cap.max_inline_data) { 317 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 318 attr->cap.max_inline_data; 319 } 320 321 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 322 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 323 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 324 return MLX5_SIG_WQE_SIZE; 325 else 326 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 327 } 328 329 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 330 struct mlx5_ib_qp *qp) 331 { 332 int wqe_size; 333 int wq_size; 334 335 if (!attr->cap.max_send_wr) 336 return 0; 337 338 wqe_size = calc_send_wqe(attr); 339 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 340 if (wqe_size < 0) 341 return wqe_size; 342 343 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 344 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 345 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 346 return -EINVAL; 347 } 348 349 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) - 350 sizeof(struct mlx5_wqe_inline_seg); 351 attr->cap.max_inline_data = qp->max_inline_data; 352 353 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 354 qp->signature_en = true; 355 356 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 357 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 358 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 359 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 360 qp->sq.wqe_cnt, 361 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 362 return -ENOMEM; 363 } 364 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 365 qp->sq.max_gs = attr->cap.max_send_sge; 366 qp->sq.max_post = wq_size / wqe_size; 367 attr->cap.max_send_wr = qp->sq.max_post; 368 369 return wq_size; 370 } 371 372 static int set_user_buf_size(struct mlx5_ib_dev *dev, 373 struct mlx5_ib_qp *qp, 374 struct mlx5_ib_create_qp *ucmd) 375 { 376 int desc_sz = 1 << qp->sq.wqe_shift; 377 378 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 379 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 380 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 381 return -EINVAL; 382 } 383 384 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 385 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 386 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 387 return -EINVAL; 388 } 389 390 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 391 392 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 393 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 394 qp->sq.wqe_cnt, 395 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 396 return -EINVAL; 397 } 398 399 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 400 (qp->sq.wqe_cnt << 6); 401 402 return 0; 403 } 404 405 static int qp_has_rq(struct ib_qp_init_attr *attr) 406 { 407 if (attr->qp_type == IB_QPT_XRC_INI || 408 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 409 attr->qp_type == MLX5_IB_QPT_REG_UMR || 410 !attr->cap.max_recv_wr) 411 return 0; 412 413 return 1; 414 } 415 416 static int first_med_uuar(void) 417 { 418 return 1; 419 } 420 421 static int next_uuar(int n) 422 { 423 n++; 424 425 while (((n % 4) & 2)) 426 n++; 427 428 return n; 429 } 430 431 static int num_med_uuar(struct mlx5_uuar_info *uuari) 432 { 433 int n; 434 435 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 436 uuari->num_low_latency_uuars - 1; 437 438 return n >= 0 ? n : 0; 439 } 440 441 static int max_uuari(struct mlx5_uuar_info *uuari) 442 { 443 return uuari->num_uars * 4; 444 } 445 446 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 447 { 448 int med; 449 int i; 450 int t; 451 452 med = num_med_uuar(uuari); 453 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 454 t++; 455 if (t == med) 456 return next_uuar(i); 457 } 458 459 return 0; 460 } 461 462 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 463 { 464 int i; 465 466 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 467 if (!test_bit(i, uuari->bitmap)) { 468 set_bit(i, uuari->bitmap); 469 uuari->count[i]++; 470 return i; 471 } 472 } 473 474 return -ENOMEM; 475 } 476 477 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 478 { 479 int minidx = first_med_uuar(); 480 int i; 481 482 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 483 if (uuari->count[i] < uuari->count[minidx]) 484 minidx = i; 485 } 486 487 uuari->count[minidx]++; 488 return minidx; 489 } 490 491 static int alloc_uuar(struct mlx5_uuar_info *uuari, 492 enum mlx5_ib_latency_class lat) 493 { 494 int uuarn = -EINVAL; 495 496 mutex_lock(&uuari->lock); 497 switch (lat) { 498 case MLX5_IB_LATENCY_CLASS_LOW: 499 uuarn = 0; 500 uuari->count[uuarn]++; 501 break; 502 503 case MLX5_IB_LATENCY_CLASS_MEDIUM: 504 if (uuari->ver < 2) 505 uuarn = -ENOMEM; 506 else 507 uuarn = alloc_med_class_uuar(uuari); 508 break; 509 510 case MLX5_IB_LATENCY_CLASS_HIGH: 511 if (uuari->ver < 2) 512 uuarn = -ENOMEM; 513 else 514 uuarn = alloc_high_class_uuar(uuari); 515 break; 516 517 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 518 uuarn = 2; 519 break; 520 } 521 mutex_unlock(&uuari->lock); 522 523 return uuarn; 524 } 525 526 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 527 { 528 clear_bit(uuarn, uuari->bitmap); 529 --uuari->count[uuarn]; 530 } 531 532 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 533 { 534 clear_bit(uuarn, uuari->bitmap); 535 --uuari->count[uuarn]; 536 } 537 538 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 539 { 540 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 541 int high_uuar = nuuars - uuari->num_low_latency_uuars; 542 543 mutex_lock(&uuari->lock); 544 if (uuarn == 0) { 545 --uuari->count[uuarn]; 546 goto out; 547 } 548 549 if (uuarn < high_uuar) { 550 free_med_class_uuar(uuari, uuarn); 551 goto out; 552 } 553 554 free_high_class_uuar(uuari, uuarn); 555 556 out: 557 mutex_unlock(&uuari->lock); 558 } 559 560 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 561 { 562 switch (state) { 563 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 564 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 565 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 566 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 567 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 568 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 569 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 570 default: return -1; 571 } 572 } 573 574 static int to_mlx5_st(enum ib_qp_type type) 575 { 576 switch (type) { 577 case IB_QPT_RC: return MLX5_QP_ST_RC; 578 case IB_QPT_UC: return MLX5_QP_ST_UC; 579 case IB_QPT_UD: return MLX5_QP_ST_UD; 580 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 581 case IB_QPT_XRC_INI: 582 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 583 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 584 case IB_QPT_GSI: return MLX5_QP_ST_QP1; 585 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 586 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 587 case IB_QPT_RAW_PACKET: 588 case IB_QPT_MAX: 589 default: return -EINVAL; 590 } 591 } 592 593 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 594 { 595 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 596 } 597 598 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 599 struct mlx5_ib_qp *qp, struct ib_udata *udata, 600 struct mlx5_create_qp_mbox_in **in, 601 struct mlx5_ib_create_qp_resp *resp, int *inlen) 602 { 603 struct mlx5_ib_ucontext *context; 604 struct mlx5_ib_create_qp ucmd; 605 int page_shift = 0; 606 int uar_index; 607 int npages; 608 u32 offset = 0; 609 int uuarn; 610 int ncont = 0; 611 int err; 612 613 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 614 if (err) { 615 mlx5_ib_dbg(dev, "copy failed\n"); 616 return err; 617 } 618 619 context = to_mucontext(pd->uobject->context); 620 /* 621 * TBD: should come from the verbs when we have the API 622 */ 623 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 624 if (uuarn < 0) { 625 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 626 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 627 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 628 if (uuarn < 0) { 629 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 630 mlx5_ib_dbg(dev, "reverting to high latency\n"); 631 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 632 if (uuarn < 0) { 633 mlx5_ib_warn(dev, "uuar allocation failed\n"); 634 return uuarn; 635 } 636 } 637 } 638 639 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 640 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 641 642 qp->rq.offset = 0; 643 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 644 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 645 646 err = set_user_buf_size(dev, qp, &ucmd); 647 if (err) 648 goto err_uuar; 649 650 if (ucmd.buf_addr && qp->buf_size) { 651 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 652 qp->buf_size, 0, 0); 653 if (IS_ERR(qp->umem)) { 654 mlx5_ib_dbg(dev, "umem_get failed\n"); 655 err = PTR_ERR(qp->umem); 656 goto err_uuar; 657 } 658 } else { 659 qp->umem = NULL; 660 } 661 662 if (qp->umem) { 663 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift, 664 &ncont, NULL); 665 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset); 666 if (err) { 667 mlx5_ib_warn(dev, "bad offset\n"); 668 goto err_umem; 669 } 670 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n", 671 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset); 672 } 673 674 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont; 675 *in = mlx5_vzalloc(*inlen); 676 if (!*in) { 677 err = -ENOMEM; 678 goto err_umem; 679 } 680 if (qp->umem) 681 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0); 682 (*in)->ctx.log_pg_sz_remote_qpn = 683 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 684 (*in)->ctx.params2 = cpu_to_be32(offset << 6); 685 686 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 687 resp->uuar_index = uuarn; 688 qp->uuarn = uuarn; 689 690 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 691 if (err) { 692 mlx5_ib_dbg(dev, "map failed\n"); 693 goto err_free; 694 } 695 696 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 697 if (err) { 698 mlx5_ib_dbg(dev, "copy failed\n"); 699 goto err_unmap; 700 } 701 qp->create_type = MLX5_QP_USER; 702 703 return 0; 704 705 err_unmap: 706 mlx5_ib_db_unmap_user(context, &qp->db); 707 708 err_free: 709 kvfree(*in); 710 711 err_umem: 712 if (qp->umem) 713 ib_umem_release(qp->umem); 714 715 err_uuar: 716 free_uuar(&context->uuari, uuarn); 717 return err; 718 } 719 720 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp) 721 { 722 struct mlx5_ib_ucontext *context; 723 724 context = to_mucontext(pd->uobject->context); 725 mlx5_ib_db_unmap_user(context, &qp->db); 726 if (qp->umem) 727 ib_umem_release(qp->umem); 728 free_uuar(&context->uuari, qp->uuarn); 729 } 730 731 static int create_kernel_qp(struct mlx5_ib_dev *dev, 732 struct ib_qp_init_attr *init_attr, 733 struct mlx5_ib_qp *qp, 734 struct mlx5_create_qp_mbox_in **in, int *inlen) 735 { 736 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 737 struct mlx5_uuar_info *uuari; 738 int uar_index; 739 int uuarn; 740 int err; 741 742 uuari = &dev->mdev->priv.uuari; 743 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)) 744 return -EINVAL; 745 746 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 747 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 748 749 uuarn = alloc_uuar(uuari, lc); 750 if (uuarn < 0) { 751 mlx5_ib_dbg(dev, "\n"); 752 return -ENOMEM; 753 } 754 755 qp->bf = &uuari->bfs[uuarn]; 756 uar_index = qp->bf->uar->index; 757 758 err = calc_sq_size(dev, init_attr, qp); 759 if (err < 0) { 760 mlx5_ib_dbg(dev, "err %d\n", err); 761 goto err_uuar; 762 } 763 764 qp->rq.offset = 0; 765 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 766 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 767 768 err = mlx5_buf_alloc(dev->mdev, qp->buf_size, &qp->buf); 769 if (err) { 770 mlx5_ib_dbg(dev, "err %d\n", err); 771 goto err_uuar; 772 } 773 774 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 775 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages; 776 *in = mlx5_vzalloc(*inlen); 777 if (!*in) { 778 err = -ENOMEM; 779 goto err_buf; 780 } 781 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 782 (*in)->ctx.log_pg_sz_remote_qpn = 783 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 784 /* Set "fast registration enabled" for all kernel QPs */ 785 (*in)->ctx.params1 |= cpu_to_be32(1 << 11); 786 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4); 787 788 mlx5_fill_page_array(&qp->buf, (*in)->pas); 789 790 err = mlx5_db_alloc(dev->mdev, &qp->db); 791 if (err) { 792 mlx5_ib_dbg(dev, "err %d\n", err); 793 goto err_free; 794 } 795 796 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 797 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 798 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 799 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 800 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 801 802 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 803 !qp->sq.w_list || !qp->sq.wqe_head) { 804 err = -ENOMEM; 805 goto err_wrid; 806 } 807 qp->create_type = MLX5_QP_KERNEL; 808 809 return 0; 810 811 err_wrid: 812 mlx5_db_free(dev->mdev, &qp->db); 813 kfree(qp->sq.wqe_head); 814 kfree(qp->sq.w_list); 815 kfree(qp->sq.wrid); 816 kfree(qp->sq.wr_data); 817 kfree(qp->rq.wrid); 818 819 err_free: 820 kvfree(*in); 821 822 err_buf: 823 mlx5_buf_free(dev->mdev, &qp->buf); 824 825 err_uuar: 826 free_uuar(&dev->mdev->priv.uuari, uuarn); 827 return err; 828 } 829 830 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 831 { 832 mlx5_db_free(dev->mdev, &qp->db); 833 kfree(qp->sq.wqe_head); 834 kfree(qp->sq.w_list); 835 kfree(qp->sq.wrid); 836 kfree(qp->sq.wr_data); 837 kfree(qp->rq.wrid); 838 mlx5_buf_free(dev->mdev, &qp->buf); 839 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn); 840 } 841 842 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 843 { 844 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 845 (attr->qp_type == IB_QPT_XRC_INI)) 846 return cpu_to_be32(MLX5_SRQ_RQ); 847 else if (!qp->has_rq) 848 return cpu_to_be32(MLX5_ZERO_LEN_RQ); 849 else 850 return cpu_to_be32(MLX5_NON_ZERO_RQ); 851 } 852 853 static int is_connected(enum ib_qp_type qp_type) 854 { 855 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 856 return 1; 857 858 return 0; 859 } 860 861 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 862 struct ib_qp_init_attr *init_attr, 863 struct ib_udata *udata, struct mlx5_ib_qp *qp) 864 { 865 struct mlx5_ib_resources *devr = &dev->devr; 866 struct mlx5_core_dev *mdev = dev->mdev; 867 struct mlx5_ib_create_qp_resp resp; 868 struct mlx5_create_qp_mbox_in *in; 869 struct mlx5_ib_create_qp ucmd; 870 int inlen = sizeof(*in); 871 int err; 872 873 mlx5_ib_odp_create_qp(qp); 874 875 mutex_init(&qp->mutex); 876 spin_lock_init(&qp->sq.lock); 877 spin_lock_init(&qp->rq.lock); 878 879 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 880 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 881 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 882 return -EINVAL; 883 } else { 884 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 885 } 886 } 887 888 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 889 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 890 891 if (pd && pd->uobject) { 892 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 893 mlx5_ib_dbg(dev, "copy failed\n"); 894 return -EFAULT; 895 } 896 897 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 898 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 899 } else { 900 qp->wq_sig = !!wq_signature; 901 } 902 903 qp->has_rq = qp_has_rq(init_attr); 904 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 905 qp, (pd && pd->uobject) ? &ucmd : NULL); 906 if (err) { 907 mlx5_ib_dbg(dev, "err %d\n", err); 908 return err; 909 } 910 911 if (pd) { 912 if (pd->uobject) { 913 __u32 max_wqes = 914 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 915 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 916 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 917 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 918 mlx5_ib_dbg(dev, "invalid rq params\n"); 919 return -EINVAL; 920 } 921 if (ucmd.sq_wqe_count > max_wqes) { 922 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 923 ucmd.sq_wqe_count, max_wqes); 924 return -EINVAL; 925 } 926 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen); 927 if (err) 928 mlx5_ib_dbg(dev, "err %d\n", err); 929 } else { 930 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen); 931 if (err) 932 mlx5_ib_dbg(dev, "err %d\n", err); 933 else 934 qp->pa_lkey = to_mpd(pd)->pa_lkey; 935 } 936 937 if (err) 938 return err; 939 } else { 940 in = mlx5_vzalloc(sizeof(*in)); 941 if (!in) 942 return -ENOMEM; 943 944 qp->create_type = MLX5_QP_EMPTY; 945 } 946 947 if (is_sqp(init_attr->qp_type)) 948 qp->port = init_attr->port_num; 949 950 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 | 951 MLX5_QP_PM_MIGRATED << 11); 952 953 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 954 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn); 955 else 956 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE); 957 958 if (qp->wq_sig) 959 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG); 960 961 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 962 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST); 963 964 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 965 int rcqe_sz; 966 int scqe_sz; 967 968 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 969 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 970 971 if (rcqe_sz == 128) 972 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE; 973 else 974 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE; 975 976 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 977 if (scqe_sz == 128) 978 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE; 979 else 980 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE; 981 } 982 } 983 984 if (qp->rq.wqe_cnt) { 985 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4); 986 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3; 987 } 988 989 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr); 990 991 if (qp->sq.wqe_cnt) 992 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11); 993 else 994 in->ctx.sq_crq_size |= cpu_to_be16(0x8000); 995 996 /* Set default resources */ 997 switch (init_attr->qp_type) { 998 case IB_QPT_XRC_TGT: 999 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1000 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1001 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1002 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn); 1003 break; 1004 case IB_QPT_XRC_INI: 1005 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1006 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1007 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1008 break; 1009 default: 1010 if (init_attr->srq) { 1011 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn); 1012 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn); 1013 } else { 1014 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1015 in->ctx.rq_type_srqn |= 1016 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn); 1017 } 1018 } 1019 1020 if (init_attr->send_cq) 1021 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn); 1022 1023 if (init_attr->recv_cq) 1024 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn); 1025 1026 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma); 1027 1028 err = mlx5_core_create_qp(dev->mdev, &qp->mqp, in, inlen); 1029 if (err) { 1030 mlx5_ib_dbg(dev, "create qp failed\n"); 1031 goto err_create; 1032 } 1033 1034 kvfree(in); 1035 /* Hardware wants QPN written in big-endian order (after 1036 * shifting) for send doorbell. Precompute this value to save 1037 * a little bit when posting sends. 1038 */ 1039 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1040 1041 qp->mqp.event = mlx5_ib_qp_event; 1042 1043 return 0; 1044 1045 err_create: 1046 if (qp->create_type == MLX5_QP_USER) 1047 destroy_qp_user(pd, qp); 1048 else if (qp->create_type == MLX5_QP_KERNEL) 1049 destroy_qp_kernel(dev, qp); 1050 1051 kvfree(in); 1052 return err; 1053 } 1054 1055 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1056 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1057 { 1058 if (send_cq) { 1059 if (recv_cq) { 1060 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1061 spin_lock_irq(&send_cq->lock); 1062 spin_lock_nested(&recv_cq->lock, 1063 SINGLE_DEPTH_NESTING); 1064 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1065 spin_lock_irq(&send_cq->lock); 1066 __acquire(&recv_cq->lock); 1067 } else { 1068 spin_lock_irq(&recv_cq->lock); 1069 spin_lock_nested(&send_cq->lock, 1070 SINGLE_DEPTH_NESTING); 1071 } 1072 } else { 1073 spin_lock_irq(&send_cq->lock); 1074 __acquire(&recv_cq->lock); 1075 } 1076 } else if (recv_cq) { 1077 spin_lock_irq(&recv_cq->lock); 1078 __acquire(&send_cq->lock); 1079 } else { 1080 __acquire(&send_cq->lock); 1081 __acquire(&recv_cq->lock); 1082 } 1083 } 1084 1085 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1086 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1087 { 1088 if (send_cq) { 1089 if (recv_cq) { 1090 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1091 spin_unlock(&recv_cq->lock); 1092 spin_unlock_irq(&send_cq->lock); 1093 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1094 __release(&recv_cq->lock); 1095 spin_unlock_irq(&send_cq->lock); 1096 } else { 1097 spin_unlock(&send_cq->lock); 1098 spin_unlock_irq(&recv_cq->lock); 1099 } 1100 } else { 1101 __release(&recv_cq->lock); 1102 spin_unlock_irq(&send_cq->lock); 1103 } 1104 } else if (recv_cq) { 1105 __release(&send_cq->lock); 1106 spin_unlock_irq(&recv_cq->lock); 1107 } else { 1108 __release(&recv_cq->lock); 1109 __release(&send_cq->lock); 1110 } 1111 } 1112 1113 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1114 { 1115 return to_mpd(qp->ibqp.pd); 1116 } 1117 1118 static void get_cqs(struct mlx5_ib_qp *qp, 1119 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1120 { 1121 switch (qp->ibqp.qp_type) { 1122 case IB_QPT_XRC_TGT: 1123 *send_cq = NULL; 1124 *recv_cq = NULL; 1125 break; 1126 case MLX5_IB_QPT_REG_UMR: 1127 case IB_QPT_XRC_INI: 1128 *send_cq = to_mcq(qp->ibqp.send_cq); 1129 *recv_cq = NULL; 1130 break; 1131 1132 case IB_QPT_SMI: 1133 case IB_QPT_GSI: 1134 case IB_QPT_RC: 1135 case IB_QPT_UC: 1136 case IB_QPT_UD: 1137 case IB_QPT_RAW_IPV6: 1138 case IB_QPT_RAW_ETHERTYPE: 1139 *send_cq = to_mcq(qp->ibqp.send_cq); 1140 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1141 break; 1142 1143 case IB_QPT_RAW_PACKET: 1144 case IB_QPT_MAX: 1145 default: 1146 *send_cq = NULL; 1147 *recv_cq = NULL; 1148 break; 1149 } 1150 } 1151 1152 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1153 { 1154 struct mlx5_ib_cq *send_cq, *recv_cq; 1155 struct mlx5_modify_qp_mbox_in *in; 1156 int err; 1157 1158 in = kzalloc(sizeof(*in), GFP_KERNEL); 1159 if (!in) 1160 return; 1161 1162 if (qp->state != IB_QPS_RESET) { 1163 mlx5_ib_qp_disable_pagefaults(qp); 1164 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state), 1165 MLX5_QP_STATE_RST, in, 0, &qp->mqp)) 1166 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n", 1167 qp->mqp.qpn); 1168 } 1169 1170 get_cqs(qp, &send_cq, &recv_cq); 1171 1172 if (qp->create_type == MLX5_QP_KERNEL) { 1173 mlx5_ib_lock_cqs(send_cq, recv_cq); 1174 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn, 1175 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1176 if (send_cq != recv_cq) 1177 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1178 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1179 } 1180 1181 err = mlx5_core_destroy_qp(dev->mdev, &qp->mqp); 1182 if (err) 1183 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn); 1184 kfree(in); 1185 1186 1187 if (qp->create_type == MLX5_QP_KERNEL) 1188 destroy_qp_kernel(dev, qp); 1189 else if (qp->create_type == MLX5_QP_USER) 1190 destroy_qp_user(&get_pd(qp)->ibpd, qp); 1191 } 1192 1193 static const char *ib_qp_type_str(enum ib_qp_type type) 1194 { 1195 switch (type) { 1196 case IB_QPT_SMI: 1197 return "IB_QPT_SMI"; 1198 case IB_QPT_GSI: 1199 return "IB_QPT_GSI"; 1200 case IB_QPT_RC: 1201 return "IB_QPT_RC"; 1202 case IB_QPT_UC: 1203 return "IB_QPT_UC"; 1204 case IB_QPT_UD: 1205 return "IB_QPT_UD"; 1206 case IB_QPT_RAW_IPV6: 1207 return "IB_QPT_RAW_IPV6"; 1208 case IB_QPT_RAW_ETHERTYPE: 1209 return "IB_QPT_RAW_ETHERTYPE"; 1210 case IB_QPT_XRC_INI: 1211 return "IB_QPT_XRC_INI"; 1212 case IB_QPT_XRC_TGT: 1213 return "IB_QPT_XRC_TGT"; 1214 case IB_QPT_RAW_PACKET: 1215 return "IB_QPT_RAW_PACKET"; 1216 case MLX5_IB_QPT_REG_UMR: 1217 return "MLX5_IB_QPT_REG_UMR"; 1218 case IB_QPT_MAX: 1219 default: 1220 return "Invalid QP type"; 1221 } 1222 } 1223 1224 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1225 struct ib_qp_init_attr *init_attr, 1226 struct ib_udata *udata) 1227 { 1228 struct mlx5_ib_dev *dev; 1229 struct mlx5_ib_qp *qp; 1230 u16 xrcdn = 0; 1231 int err; 1232 1233 if (pd) { 1234 dev = to_mdev(pd->device); 1235 } else { 1236 /* being cautious here */ 1237 if (init_attr->qp_type != IB_QPT_XRC_TGT && 1238 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 1239 pr_warn("%s: no PD for transport %s\n", __func__, 1240 ib_qp_type_str(init_attr->qp_type)); 1241 return ERR_PTR(-EINVAL); 1242 } 1243 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 1244 } 1245 1246 switch (init_attr->qp_type) { 1247 case IB_QPT_XRC_TGT: 1248 case IB_QPT_XRC_INI: 1249 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 1250 mlx5_ib_dbg(dev, "XRC not supported\n"); 1251 return ERR_PTR(-ENOSYS); 1252 } 1253 init_attr->recv_cq = NULL; 1254 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 1255 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1256 init_attr->send_cq = NULL; 1257 } 1258 1259 /* fall through */ 1260 case IB_QPT_RC: 1261 case IB_QPT_UC: 1262 case IB_QPT_UD: 1263 case IB_QPT_SMI: 1264 case IB_QPT_GSI: 1265 case MLX5_IB_QPT_REG_UMR: 1266 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1267 if (!qp) 1268 return ERR_PTR(-ENOMEM); 1269 1270 err = create_qp_common(dev, pd, init_attr, udata, qp); 1271 if (err) { 1272 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 1273 kfree(qp); 1274 return ERR_PTR(err); 1275 } 1276 1277 if (is_qp0(init_attr->qp_type)) 1278 qp->ibqp.qp_num = 0; 1279 else if (is_qp1(init_attr->qp_type)) 1280 qp->ibqp.qp_num = 1; 1281 else 1282 qp->ibqp.qp_num = qp->mqp.qpn; 1283 1284 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 1285 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn, 1286 to_mcq(init_attr->send_cq)->mcq.cqn); 1287 1288 qp->xrcdn = xrcdn; 1289 1290 break; 1291 1292 case IB_QPT_RAW_IPV6: 1293 case IB_QPT_RAW_ETHERTYPE: 1294 case IB_QPT_RAW_PACKET: 1295 case IB_QPT_MAX: 1296 default: 1297 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 1298 init_attr->qp_type); 1299 /* Don't support raw QPs */ 1300 return ERR_PTR(-EINVAL); 1301 } 1302 1303 return &qp->ibqp; 1304 } 1305 1306 int mlx5_ib_destroy_qp(struct ib_qp *qp) 1307 { 1308 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1309 struct mlx5_ib_qp *mqp = to_mqp(qp); 1310 1311 destroy_qp_common(dev, mqp); 1312 1313 kfree(mqp); 1314 1315 return 0; 1316 } 1317 1318 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 1319 int attr_mask) 1320 { 1321 u32 hw_access_flags = 0; 1322 u8 dest_rd_atomic; 1323 u32 access_flags; 1324 1325 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1326 dest_rd_atomic = attr->max_dest_rd_atomic; 1327 else 1328 dest_rd_atomic = qp->resp_depth; 1329 1330 if (attr_mask & IB_QP_ACCESS_FLAGS) 1331 access_flags = attr->qp_access_flags; 1332 else 1333 access_flags = qp->atomic_rd_en; 1334 1335 if (!dest_rd_atomic) 1336 access_flags &= IB_ACCESS_REMOTE_WRITE; 1337 1338 if (access_flags & IB_ACCESS_REMOTE_READ) 1339 hw_access_flags |= MLX5_QP_BIT_RRE; 1340 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1341 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 1342 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1343 hw_access_flags |= MLX5_QP_BIT_RWE; 1344 1345 return cpu_to_be32(hw_access_flags); 1346 } 1347 1348 enum { 1349 MLX5_PATH_FLAG_FL = 1 << 0, 1350 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 1351 MLX5_PATH_FLAG_COUNTER = 1 << 2, 1352 }; 1353 1354 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 1355 { 1356 if (rate == IB_RATE_PORT_CURRENT) { 1357 return 0; 1358 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 1359 return -EINVAL; 1360 } else { 1361 while (rate != IB_RATE_2_5_GBPS && 1362 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 1363 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 1364 --rate; 1365 } 1366 1367 return rate + MLX5_STAT_RATE_OFFSET; 1368 } 1369 1370 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah, 1371 struct mlx5_qp_path *path, u8 port, int attr_mask, 1372 u32 path_flags, const struct ib_qp_attr *attr) 1373 { 1374 int err; 1375 1376 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 1377 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0; 1378 1379 if (attr_mask & IB_QP_PKEY_INDEX) 1380 path->pkey_index = attr->pkey_index; 1381 1382 path->grh_mlid = ah->src_path_bits & 0x7f; 1383 path->rlid = cpu_to_be16(ah->dlid); 1384 1385 if (ah->ah_flags & IB_AH_GRH) { 1386 if (ah->grh.sgid_index >= 1387 dev->mdev->port_caps[port - 1].gid_table_len) { 1388 pr_err("sgid_index (%u) too large. max is %d\n", 1389 ah->grh.sgid_index, 1390 dev->mdev->port_caps[port - 1].gid_table_len); 1391 return -EINVAL; 1392 } 1393 path->grh_mlid |= 1 << 7; 1394 path->mgid_index = ah->grh.sgid_index; 1395 path->hop_limit = ah->grh.hop_limit; 1396 path->tclass_flowlabel = 1397 cpu_to_be32((ah->grh.traffic_class << 20) | 1398 (ah->grh.flow_label)); 1399 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1400 } 1401 1402 err = ib_rate_to_mlx5(dev, ah->static_rate); 1403 if (err < 0) 1404 return err; 1405 path->static_rate = err; 1406 path->port = port; 1407 1408 if (attr_mask & IB_QP_TIMEOUT) 1409 path->ackto_lt = attr->timeout << 3; 1410 1411 path->sl = ah->sl & 0xf; 1412 1413 return 0; 1414 } 1415 1416 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 1417 [MLX5_QP_STATE_INIT] = { 1418 [MLX5_QP_STATE_INIT] = { 1419 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1420 MLX5_QP_OPTPAR_RAE | 1421 MLX5_QP_OPTPAR_RWE | 1422 MLX5_QP_OPTPAR_PKEY_INDEX | 1423 MLX5_QP_OPTPAR_PRI_PORT, 1424 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1425 MLX5_QP_OPTPAR_PKEY_INDEX | 1426 MLX5_QP_OPTPAR_PRI_PORT, 1427 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1428 MLX5_QP_OPTPAR_Q_KEY | 1429 MLX5_QP_OPTPAR_PRI_PORT, 1430 }, 1431 [MLX5_QP_STATE_RTR] = { 1432 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1433 MLX5_QP_OPTPAR_RRE | 1434 MLX5_QP_OPTPAR_RAE | 1435 MLX5_QP_OPTPAR_RWE | 1436 MLX5_QP_OPTPAR_PKEY_INDEX, 1437 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1438 MLX5_QP_OPTPAR_RWE | 1439 MLX5_QP_OPTPAR_PKEY_INDEX, 1440 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1441 MLX5_QP_OPTPAR_Q_KEY, 1442 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 1443 MLX5_QP_OPTPAR_Q_KEY, 1444 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1445 MLX5_QP_OPTPAR_RRE | 1446 MLX5_QP_OPTPAR_RAE | 1447 MLX5_QP_OPTPAR_RWE | 1448 MLX5_QP_OPTPAR_PKEY_INDEX, 1449 }, 1450 }, 1451 [MLX5_QP_STATE_RTR] = { 1452 [MLX5_QP_STATE_RTS] = { 1453 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1454 MLX5_QP_OPTPAR_RRE | 1455 MLX5_QP_OPTPAR_RAE | 1456 MLX5_QP_OPTPAR_RWE | 1457 MLX5_QP_OPTPAR_PM_STATE | 1458 MLX5_QP_OPTPAR_RNR_TIMEOUT, 1459 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1460 MLX5_QP_OPTPAR_RWE | 1461 MLX5_QP_OPTPAR_PM_STATE, 1462 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1463 }, 1464 }, 1465 [MLX5_QP_STATE_RTS] = { 1466 [MLX5_QP_STATE_RTS] = { 1467 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1468 MLX5_QP_OPTPAR_RAE | 1469 MLX5_QP_OPTPAR_RWE | 1470 MLX5_QP_OPTPAR_RNR_TIMEOUT | 1471 MLX5_QP_OPTPAR_PM_STATE | 1472 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1473 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1474 MLX5_QP_OPTPAR_PM_STATE | 1475 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1476 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 1477 MLX5_QP_OPTPAR_SRQN | 1478 MLX5_QP_OPTPAR_CQN_RCV, 1479 }, 1480 }, 1481 [MLX5_QP_STATE_SQER] = { 1482 [MLX5_QP_STATE_RTS] = { 1483 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1484 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 1485 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 1486 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 1487 MLX5_QP_OPTPAR_RWE | 1488 MLX5_QP_OPTPAR_RAE | 1489 MLX5_QP_OPTPAR_RRE, 1490 }, 1491 }, 1492 }; 1493 1494 static int ib_nr_to_mlx5_nr(int ib_mask) 1495 { 1496 switch (ib_mask) { 1497 case IB_QP_STATE: 1498 return 0; 1499 case IB_QP_CUR_STATE: 1500 return 0; 1501 case IB_QP_EN_SQD_ASYNC_NOTIFY: 1502 return 0; 1503 case IB_QP_ACCESS_FLAGS: 1504 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 1505 MLX5_QP_OPTPAR_RAE; 1506 case IB_QP_PKEY_INDEX: 1507 return MLX5_QP_OPTPAR_PKEY_INDEX; 1508 case IB_QP_PORT: 1509 return MLX5_QP_OPTPAR_PRI_PORT; 1510 case IB_QP_QKEY: 1511 return MLX5_QP_OPTPAR_Q_KEY; 1512 case IB_QP_AV: 1513 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 1514 MLX5_QP_OPTPAR_PRI_PORT; 1515 case IB_QP_PATH_MTU: 1516 return 0; 1517 case IB_QP_TIMEOUT: 1518 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 1519 case IB_QP_RETRY_CNT: 1520 return MLX5_QP_OPTPAR_RETRY_COUNT; 1521 case IB_QP_RNR_RETRY: 1522 return MLX5_QP_OPTPAR_RNR_RETRY; 1523 case IB_QP_RQ_PSN: 1524 return 0; 1525 case IB_QP_MAX_QP_RD_ATOMIC: 1526 return MLX5_QP_OPTPAR_SRA_MAX; 1527 case IB_QP_ALT_PATH: 1528 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 1529 case IB_QP_MIN_RNR_TIMER: 1530 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 1531 case IB_QP_SQ_PSN: 1532 return 0; 1533 case IB_QP_MAX_DEST_RD_ATOMIC: 1534 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 1535 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 1536 case IB_QP_PATH_MIG_STATE: 1537 return MLX5_QP_OPTPAR_PM_STATE; 1538 case IB_QP_CAP: 1539 return 0; 1540 case IB_QP_DEST_QPN: 1541 return 0; 1542 } 1543 return 0; 1544 } 1545 1546 static int ib_mask_to_mlx5_opt(int ib_mask) 1547 { 1548 int result = 0; 1549 int i; 1550 1551 for (i = 0; i < 8 * sizeof(int); i++) { 1552 if ((1 << i) & ib_mask) 1553 result |= ib_nr_to_mlx5_nr(1 << i); 1554 } 1555 1556 return result; 1557 } 1558 1559 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 1560 const struct ib_qp_attr *attr, int attr_mask, 1561 enum ib_qp_state cur_state, enum ib_qp_state new_state) 1562 { 1563 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1564 struct mlx5_ib_qp *qp = to_mqp(ibqp); 1565 struct mlx5_ib_cq *send_cq, *recv_cq; 1566 struct mlx5_qp_context *context; 1567 struct mlx5_modify_qp_mbox_in *in; 1568 struct mlx5_ib_pd *pd; 1569 enum mlx5_qp_state mlx5_cur, mlx5_new; 1570 enum mlx5_qp_optpar optpar; 1571 int sqd_event; 1572 int mlx5_st; 1573 int err; 1574 1575 in = kzalloc(sizeof(*in), GFP_KERNEL); 1576 if (!in) 1577 return -ENOMEM; 1578 1579 context = &in->ctx; 1580 err = to_mlx5_st(ibqp->qp_type); 1581 if (err < 0) 1582 goto out; 1583 1584 context->flags = cpu_to_be32(err << 16); 1585 1586 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 1587 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 1588 } else { 1589 switch (attr->path_mig_state) { 1590 case IB_MIG_MIGRATED: 1591 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 1592 break; 1593 case IB_MIG_REARM: 1594 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 1595 break; 1596 case IB_MIG_ARMED: 1597 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 1598 break; 1599 } 1600 } 1601 1602 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) { 1603 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 1604 } else if (ibqp->qp_type == IB_QPT_UD || 1605 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 1606 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1607 } else if (attr_mask & IB_QP_PATH_MTU) { 1608 if (attr->path_mtu < IB_MTU_256 || 1609 attr->path_mtu > IB_MTU_4096) { 1610 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 1611 err = -EINVAL; 1612 goto out; 1613 } 1614 context->mtu_msgmax = (attr->path_mtu << 5) | 1615 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 1616 } 1617 1618 if (attr_mask & IB_QP_DEST_QPN) 1619 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 1620 1621 if (attr_mask & IB_QP_PKEY_INDEX) 1622 context->pri_path.pkey_index = attr->pkey_index; 1623 1624 /* todo implement counter_index functionality */ 1625 1626 if (is_sqp(ibqp->qp_type)) 1627 context->pri_path.port = qp->port; 1628 1629 if (attr_mask & IB_QP_PORT) 1630 context->pri_path.port = attr->port_num; 1631 1632 if (attr_mask & IB_QP_AV) { 1633 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path, 1634 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 1635 attr_mask, 0, attr); 1636 if (err) 1637 goto out; 1638 } 1639 1640 if (attr_mask & IB_QP_TIMEOUT) 1641 context->pri_path.ackto_lt |= attr->timeout << 3; 1642 1643 if (attr_mask & IB_QP_ALT_PATH) { 1644 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path, 1645 attr->alt_port_num, attr_mask, 0, attr); 1646 if (err) 1647 goto out; 1648 } 1649 1650 pd = get_pd(qp); 1651 get_cqs(qp, &send_cq, &recv_cq); 1652 1653 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 1654 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 1655 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 1656 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 1657 1658 if (attr_mask & IB_QP_RNR_RETRY) 1659 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1660 1661 if (attr_mask & IB_QP_RETRY_CNT) 1662 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1663 1664 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1665 if (attr->max_rd_atomic) 1666 context->params1 |= 1667 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1668 } 1669 1670 if (attr_mask & IB_QP_SQ_PSN) 1671 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1672 1673 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1674 if (attr->max_dest_rd_atomic) 1675 context->params2 |= 1676 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1677 } 1678 1679 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 1680 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 1681 1682 if (attr_mask & IB_QP_MIN_RNR_TIMER) 1683 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1684 1685 if (attr_mask & IB_QP_RQ_PSN) 1686 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1687 1688 if (attr_mask & IB_QP_QKEY) 1689 context->qkey = cpu_to_be32(attr->qkey); 1690 1691 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1692 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1693 1694 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 1695 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 1696 sqd_event = 1; 1697 else 1698 sqd_event = 0; 1699 1700 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1701 context->sq_crq_size |= cpu_to_be16(1 << 4); 1702 1703 1704 mlx5_cur = to_mlx5_state(cur_state); 1705 mlx5_new = to_mlx5_state(new_state); 1706 mlx5_st = to_mlx5_st(ibqp->qp_type); 1707 if (mlx5_st < 0) 1708 goto out; 1709 1710 /* If moving to a reset or error state, we must disable page faults on 1711 * this QP and flush all current page faults. Otherwise a stale page 1712 * fault may attempt to work on this QP after it is reset and moved 1713 * again to RTS, and may cause the driver and the device to get out of 1714 * sync. */ 1715 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 1716 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 1717 mlx5_ib_qp_disable_pagefaults(qp); 1718 1719 optpar = ib_mask_to_mlx5_opt(attr_mask); 1720 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 1721 in->optparam = cpu_to_be32(optpar); 1722 err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state), 1723 to_mlx5_state(new_state), in, sqd_event, 1724 &qp->mqp); 1725 if (err) 1726 goto out; 1727 1728 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1729 mlx5_ib_qp_enable_pagefaults(qp); 1730 1731 qp->state = new_state; 1732 1733 if (attr_mask & IB_QP_ACCESS_FLAGS) 1734 qp->atomic_rd_en = attr->qp_access_flags; 1735 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1736 qp->resp_depth = attr->max_dest_rd_atomic; 1737 if (attr_mask & IB_QP_PORT) 1738 qp->port = attr->port_num; 1739 if (attr_mask & IB_QP_ALT_PATH) 1740 qp->alt_port = attr->alt_port_num; 1741 1742 /* 1743 * If we moved a kernel QP to RESET, clean up all old CQ 1744 * entries and reinitialize the QP. 1745 */ 1746 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 1747 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn, 1748 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 1749 if (send_cq != recv_cq) 1750 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1751 1752 qp->rq.head = 0; 1753 qp->rq.tail = 0; 1754 qp->sq.head = 0; 1755 qp->sq.tail = 0; 1756 qp->sq.cur_post = 0; 1757 qp->sq.last_poll = 0; 1758 qp->db.db[MLX5_RCV_DBR] = 0; 1759 qp->db.db[MLX5_SND_DBR] = 0; 1760 } 1761 1762 out: 1763 kfree(in); 1764 return err; 1765 } 1766 1767 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1768 int attr_mask, struct ib_udata *udata) 1769 { 1770 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1771 struct mlx5_ib_qp *qp = to_mqp(ibqp); 1772 enum ib_qp_state cur_state, new_state; 1773 int err = -EINVAL; 1774 int port; 1775 1776 mutex_lock(&qp->mutex); 1777 1778 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 1779 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1780 1781 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR && 1782 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask, 1783 IB_LINK_LAYER_UNSPECIFIED)) 1784 goto out; 1785 1786 if ((attr_mask & IB_QP_PORT) && 1787 (attr->port_num == 0 || 1788 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) 1789 goto out; 1790 1791 if (attr_mask & IB_QP_PKEY_INDEX) { 1792 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1793 if (attr->pkey_index >= 1794 dev->mdev->port_caps[port - 1].pkey_table_len) 1795 goto out; 1796 } 1797 1798 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1799 attr->max_rd_atomic > 1800 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) 1801 goto out; 1802 1803 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1804 attr->max_dest_rd_atomic > 1805 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) 1806 goto out; 1807 1808 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 1809 err = 0; 1810 goto out; 1811 } 1812 1813 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 1814 1815 out: 1816 mutex_unlock(&qp->mutex); 1817 return err; 1818 } 1819 1820 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 1821 { 1822 struct mlx5_ib_cq *cq; 1823 unsigned cur; 1824 1825 cur = wq->head - wq->tail; 1826 if (likely(cur + nreq < wq->max_post)) 1827 return 0; 1828 1829 cq = to_mcq(ib_cq); 1830 spin_lock(&cq->lock); 1831 cur = wq->head - wq->tail; 1832 spin_unlock(&cq->lock); 1833 1834 return cur + nreq >= wq->max_post; 1835 } 1836 1837 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 1838 u64 remote_addr, u32 rkey) 1839 { 1840 rseg->raddr = cpu_to_be64(remote_addr); 1841 rseg->rkey = cpu_to_be32(rkey); 1842 rseg->reserved = 0; 1843 } 1844 1845 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 1846 struct ib_send_wr *wr) 1847 { 1848 memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av)); 1849 dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV); 1850 dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1851 } 1852 1853 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 1854 { 1855 dseg->byte_count = cpu_to_be32(sg->length); 1856 dseg->lkey = cpu_to_be32(sg->lkey); 1857 dseg->addr = cpu_to_be64(sg->addr); 1858 } 1859 1860 static __be16 get_klm_octo(int npages) 1861 { 1862 return cpu_to_be16(ALIGN(npages, 8) / 2); 1863 } 1864 1865 static __be64 frwr_mkey_mask(void) 1866 { 1867 u64 result; 1868 1869 result = MLX5_MKEY_MASK_LEN | 1870 MLX5_MKEY_MASK_PAGE_SIZE | 1871 MLX5_MKEY_MASK_START_ADDR | 1872 MLX5_MKEY_MASK_EN_RINVAL | 1873 MLX5_MKEY_MASK_KEY | 1874 MLX5_MKEY_MASK_LR | 1875 MLX5_MKEY_MASK_LW | 1876 MLX5_MKEY_MASK_RR | 1877 MLX5_MKEY_MASK_RW | 1878 MLX5_MKEY_MASK_A | 1879 MLX5_MKEY_MASK_SMALL_FENCE | 1880 MLX5_MKEY_MASK_FREE; 1881 1882 return cpu_to_be64(result); 1883 } 1884 1885 static __be64 sig_mkey_mask(void) 1886 { 1887 u64 result; 1888 1889 result = MLX5_MKEY_MASK_LEN | 1890 MLX5_MKEY_MASK_PAGE_SIZE | 1891 MLX5_MKEY_MASK_START_ADDR | 1892 MLX5_MKEY_MASK_EN_SIGERR | 1893 MLX5_MKEY_MASK_EN_RINVAL | 1894 MLX5_MKEY_MASK_KEY | 1895 MLX5_MKEY_MASK_LR | 1896 MLX5_MKEY_MASK_LW | 1897 MLX5_MKEY_MASK_RR | 1898 MLX5_MKEY_MASK_RW | 1899 MLX5_MKEY_MASK_SMALL_FENCE | 1900 MLX5_MKEY_MASK_FREE | 1901 MLX5_MKEY_MASK_BSF_EN; 1902 1903 return cpu_to_be64(result); 1904 } 1905 1906 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 1907 struct ib_send_wr *wr, int li) 1908 { 1909 memset(umr, 0, sizeof(*umr)); 1910 1911 if (li) { 1912 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 1913 umr->flags = 1 << 7; 1914 return; 1915 } 1916 1917 umr->flags = (1 << 5); /* fail if not free */ 1918 umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len); 1919 umr->mkey_mask = frwr_mkey_mask(); 1920 } 1921 1922 static __be64 get_umr_reg_mr_mask(void) 1923 { 1924 u64 result; 1925 1926 result = MLX5_MKEY_MASK_LEN | 1927 MLX5_MKEY_MASK_PAGE_SIZE | 1928 MLX5_MKEY_MASK_START_ADDR | 1929 MLX5_MKEY_MASK_PD | 1930 MLX5_MKEY_MASK_LR | 1931 MLX5_MKEY_MASK_LW | 1932 MLX5_MKEY_MASK_KEY | 1933 MLX5_MKEY_MASK_RR | 1934 MLX5_MKEY_MASK_RW | 1935 MLX5_MKEY_MASK_A | 1936 MLX5_MKEY_MASK_FREE; 1937 1938 return cpu_to_be64(result); 1939 } 1940 1941 static __be64 get_umr_unreg_mr_mask(void) 1942 { 1943 u64 result; 1944 1945 result = MLX5_MKEY_MASK_FREE; 1946 1947 return cpu_to_be64(result); 1948 } 1949 1950 static __be64 get_umr_update_mtt_mask(void) 1951 { 1952 u64 result; 1953 1954 result = MLX5_MKEY_MASK_FREE; 1955 1956 return cpu_to_be64(result); 1957 } 1958 1959 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 1960 struct ib_send_wr *wr) 1961 { 1962 struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg; 1963 1964 memset(umr, 0, sizeof(*umr)); 1965 1966 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 1967 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 1968 else 1969 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 1970 1971 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 1972 umr->klm_octowords = get_klm_octo(umrwr->npages); 1973 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 1974 umr->mkey_mask = get_umr_update_mtt_mask(); 1975 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 1976 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 1977 } else { 1978 umr->mkey_mask = get_umr_reg_mr_mask(); 1979 } 1980 } else { 1981 umr->mkey_mask = get_umr_unreg_mr_mask(); 1982 } 1983 1984 if (!wr->num_sge) 1985 umr->flags |= MLX5_UMR_INLINE; 1986 } 1987 1988 static u8 get_umr_flags(int acc) 1989 { 1990 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1991 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1992 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1993 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1994 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 1995 } 1996 1997 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr, 1998 int li, int *writ) 1999 { 2000 memset(seg, 0, sizeof(*seg)); 2001 if (li) { 2002 seg->status = MLX5_MKEY_STATUS_FREE; 2003 return; 2004 } 2005 2006 seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags) | 2007 MLX5_ACCESS_MODE_MTT; 2008 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE); 2009 seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00); 2010 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 2011 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start); 2012 seg->len = cpu_to_be64(wr->wr.fast_reg.length); 2013 seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2); 2014 seg->log2_page_size = wr->wr.fast_reg.page_shift; 2015 } 2016 2017 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 2018 { 2019 struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg; 2020 2021 memset(seg, 0, sizeof(*seg)); 2022 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 2023 seg->status = MLX5_MKEY_STATUS_FREE; 2024 return; 2025 } 2026 2027 seg->flags = convert_access(umrwr->access_flags); 2028 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 2029 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 2030 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 2031 } 2032 seg->len = cpu_to_be64(umrwr->length); 2033 seg->log2_page_size = umrwr->page_shift; 2034 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 2035 mlx5_mkey_variant(umrwr->mkey)); 2036 } 2037 2038 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg, 2039 struct ib_send_wr *wr, 2040 struct mlx5_core_dev *mdev, 2041 struct mlx5_ib_pd *pd, 2042 int writ) 2043 { 2044 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list); 2045 u64 *page_list = wr->wr.fast_reg.page_list->page_list; 2046 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0); 2047 int i; 2048 2049 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) 2050 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm); 2051 dseg->addr = cpu_to_be64(mfrpl->map); 2052 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64)); 2053 dseg->lkey = cpu_to_be32(pd->pa_lkey); 2054 } 2055 2056 static __be32 send_ieth(struct ib_send_wr *wr) 2057 { 2058 switch (wr->opcode) { 2059 case IB_WR_SEND_WITH_IMM: 2060 case IB_WR_RDMA_WRITE_WITH_IMM: 2061 return wr->ex.imm_data; 2062 2063 case IB_WR_SEND_WITH_INV: 2064 return cpu_to_be32(wr->ex.invalidate_rkey); 2065 2066 default: 2067 return 0; 2068 } 2069 } 2070 2071 static u8 calc_sig(void *wqe, int size) 2072 { 2073 u8 *p = wqe; 2074 u8 res = 0; 2075 int i; 2076 2077 for (i = 0; i < size; i++) 2078 res ^= p[i]; 2079 2080 return ~res; 2081 } 2082 2083 static u8 wq_sig(void *wqe) 2084 { 2085 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 2086 } 2087 2088 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 2089 void *wqe, int *sz) 2090 { 2091 struct mlx5_wqe_inline_seg *seg; 2092 void *qend = qp->sq.qend; 2093 void *addr; 2094 int inl = 0; 2095 int copy; 2096 int len; 2097 int i; 2098 2099 seg = wqe; 2100 wqe += sizeof(*seg); 2101 for (i = 0; i < wr->num_sge; i++) { 2102 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 2103 len = wr->sg_list[i].length; 2104 inl += len; 2105 2106 if (unlikely(inl > qp->max_inline_data)) 2107 return -ENOMEM; 2108 2109 if (unlikely(wqe + len > qend)) { 2110 copy = qend - wqe; 2111 memcpy(wqe, addr, copy); 2112 addr += copy; 2113 len -= copy; 2114 wqe = mlx5_get_send_wqe(qp, 0); 2115 } 2116 memcpy(wqe, addr, len); 2117 wqe += len; 2118 } 2119 2120 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 2121 2122 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 2123 2124 return 0; 2125 } 2126 2127 static u16 prot_field_size(enum ib_signature_type type) 2128 { 2129 switch (type) { 2130 case IB_SIG_TYPE_T10_DIF: 2131 return MLX5_DIF_SIZE; 2132 default: 2133 return 0; 2134 } 2135 } 2136 2137 static u8 bs_selector(int block_size) 2138 { 2139 switch (block_size) { 2140 case 512: return 0x1; 2141 case 520: return 0x2; 2142 case 4096: return 0x3; 2143 case 4160: return 0x4; 2144 case 1073741824: return 0x5; 2145 default: return 0; 2146 } 2147 } 2148 2149 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 2150 struct mlx5_bsf_inl *inl) 2151 { 2152 /* Valid inline section and allow BSF refresh */ 2153 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 2154 MLX5_BSF_REFRESH_DIF); 2155 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 2156 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 2157 /* repeating block */ 2158 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 2159 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 2160 MLX5_DIF_CRC : MLX5_DIF_IPCS; 2161 2162 if (domain->sig.dif.ref_remap) 2163 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 2164 2165 if (domain->sig.dif.app_escape) { 2166 if (domain->sig.dif.ref_escape) 2167 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 2168 else 2169 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 2170 } 2171 2172 inl->dif_app_bitmask_check = 2173 cpu_to_be16(domain->sig.dif.apptag_check_mask); 2174 } 2175 2176 static int mlx5_set_bsf(struct ib_mr *sig_mr, 2177 struct ib_sig_attrs *sig_attrs, 2178 struct mlx5_bsf *bsf, u32 data_size) 2179 { 2180 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 2181 struct mlx5_bsf_basic *basic = &bsf->basic; 2182 struct ib_sig_domain *mem = &sig_attrs->mem; 2183 struct ib_sig_domain *wire = &sig_attrs->wire; 2184 2185 memset(bsf, 0, sizeof(*bsf)); 2186 2187 /* Basic + Extended + Inline */ 2188 basic->bsf_size_sbs = 1 << 7; 2189 /* Input domain check byte mask */ 2190 basic->check_byte_mask = sig_attrs->check_mask; 2191 basic->raw_data_size = cpu_to_be32(data_size); 2192 2193 /* Memory domain */ 2194 switch (sig_attrs->mem.sig_type) { 2195 case IB_SIG_TYPE_NONE: 2196 break; 2197 case IB_SIG_TYPE_T10_DIF: 2198 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 2199 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 2200 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 2201 break; 2202 default: 2203 return -EINVAL; 2204 } 2205 2206 /* Wire domain */ 2207 switch (sig_attrs->wire.sig_type) { 2208 case IB_SIG_TYPE_NONE: 2209 break; 2210 case IB_SIG_TYPE_T10_DIF: 2211 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 2212 mem->sig_type == wire->sig_type) { 2213 /* Same block structure */ 2214 basic->bsf_size_sbs |= 1 << 4; 2215 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 2216 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 2217 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 2218 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 2219 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 2220 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 2221 } else 2222 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 2223 2224 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 2225 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 2226 break; 2227 default: 2228 return -EINVAL; 2229 } 2230 2231 return 0; 2232 } 2233 2234 static int set_sig_data_segment(struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 2235 void **seg, int *size) 2236 { 2237 struct ib_sig_attrs *sig_attrs = wr->wr.sig_handover.sig_attrs; 2238 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr; 2239 struct mlx5_bsf *bsf; 2240 u32 data_len = wr->sg_list->length; 2241 u32 data_key = wr->sg_list->lkey; 2242 u64 data_va = wr->sg_list->addr; 2243 int ret; 2244 int wqe_size; 2245 2246 if (!wr->wr.sig_handover.prot || 2247 (data_key == wr->wr.sig_handover.prot->lkey && 2248 data_va == wr->wr.sig_handover.prot->addr && 2249 data_len == wr->wr.sig_handover.prot->length)) { 2250 /** 2251 * Source domain doesn't contain signature information 2252 * or data and protection are interleaved in memory. 2253 * So need construct: 2254 * ------------------ 2255 * | data_klm | 2256 * ------------------ 2257 * | BSF | 2258 * ------------------ 2259 **/ 2260 struct mlx5_klm *data_klm = *seg; 2261 2262 data_klm->bcount = cpu_to_be32(data_len); 2263 data_klm->key = cpu_to_be32(data_key); 2264 data_klm->va = cpu_to_be64(data_va); 2265 wqe_size = ALIGN(sizeof(*data_klm), 64); 2266 } else { 2267 /** 2268 * Source domain contains signature information 2269 * So need construct a strided block format: 2270 * --------------------------- 2271 * | stride_block_ctrl | 2272 * --------------------------- 2273 * | data_klm | 2274 * --------------------------- 2275 * | prot_klm | 2276 * --------------------------- 2277 * | BSF | 2278 * --------------------------- 2279 **/ 2280 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 2281 struct mlx5_stride_block_entry *data_sentry; 2282 struct mlx5_stride_block_entry *prot_sentry; 2283 u32 prot_key = wr->wr.sig_handover.prot->lkey; 2284 u64 prot_va = wr->wr.sig_handover.prot->addr; 2285 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 2286 int prot_size; 2287 2288 sblock_ctrl = *seg; 2289 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 2290 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 2291 2292 prot_size = prot_field_size(sig_attrs->mem.sig_type); 2293 if (!prot_size) { 2294 pr_err("Bad block size given: %u\n", block_size); 2295 return -EINVAL; 2296 } 2297 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 2298 prot_size); 2299 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 2300 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 2301 sblock_ctrl->num_entries = cpu_to_be16(2); 2302 2303 data_sentry->bcount = cpu_to_be16(block_size); 2304 data_sentry->key = cpu_to_be32(data_key); 2305 data_sentry->va = cpu_to_be64(data_va); 2306 data_sentry->stride = cpu_to_be16(block_size); 2307 2308 prot_sentry->bcount = cpu_to_be16(prot_size); 2309 prot_sentry->key = cpu_to_be32(prot_key); 2310 prot_sentry->va = cpu_to_be64(prot_va); 2311 prot_sentry->stride = cpu_to_be16(prot_size); 2312 2313 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 2314 sizeof(*prot_sentry), 64); 2315 } 2316 2317 *seg += wqe_size; 2318 *size += wqe_size / 16; 2319 if (unlikely((*seg == qp->sq.qend))) 2320 *seg = mlx5_get_send_wqe(qp, 0); 2321 2322 bsf = *seg; 2323 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 2324 if (ret) 2325 return -EINVAL; 2326 2327 *seg += sizeof(*bsf); 2328 *size += sizeof(*bsf) / 16; 2329 if (unlikely((*seg == qp->sq.qend))) 2330 *seg = mlx5_get_send_wqe(qp, 0); 2331 2332 return 0; 2333 } 2334 2335 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 2336 struct ib_send_wr *wr, u32 nelements, 2337 u32 length, u32 pdn) 2338 { 2339 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr; 2340 u32 sig_key = sig_mr->rkey; 2341 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 2342 2343 memset(seg, 0, sizeof(*seg)); 2344 2345 seg->flags = get_umr_flags(wr->wr.sig_handover.access_flags) | 2346 MLX5_ACCESS_MODE_KLM; 2347 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 2348 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 2349 MLX5_MKEY_BSF_EN | pdn); 2350 seg->len = cpu_to_be64(length); 2351 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 2352 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 2353 } 2354 2355 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 2356 struct ib_send_wr *wr, u32 nelements) 2357 { 2358 memset(umr, 0, sizeof(*umr)); 2359 2360 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 2361 umr->klm_octowords = get_klm_octo(nelements); 2362 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 2363 umr->mkey_mask = sig_mkey_mask(); 2364 } 2365 2366 2367 static int set_sig_umr_wr(struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 2368 void **seg, int *size) 2369 { 2370 struct mlx5_ib_mr *sig_mr = to_mmr(wr->wr.sig_handover.sig_mr); 2371 u32 pdn = get_pd(qp)->pdn; 2372 u32 klm_oct_size; 2373 int region_len, ret; 2374 2375 if (unlikely(wr->num_sge != 1) || 2376 unlikely(wr->wr.sig_handover.access_flags & 2377 IB_ACCESS_REMOTE_ATOMIC) || 2378 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 2379 unlikely(!sig_mr->sig->sig_status_checked)) 2380 return -EINVAL; 2381 2382 /* length of the protected region, data + protection */ 2383 region_len = wr->sg_list->length; 2384 if (wr->wr.sig_handover.prot && 2385 (wr->wr.sig_handover.prot->lkey != wr->sg_list->lkey || 2386 wr->wr.sig_handover.prot->addr != wr->sg_list->addr || 2387 wr->wr.sig_handover.prot->length != wr->sg_list->length)) 2388 region_len += wr->wr.sig_handover.prot->length; 2389 2390 /** 2391 * KLM octoword size - if protection was provided 2392 * then we use strided block format (3 octowords), 2393 * else we use single KLM (1 octoword) 2394 **/ 2395 klm_oct_size = wr->wr.sig_handover.prot ? 3 : 1; 2396 2397 set_sig_umr_segment(*seg, wr, klm_oct_size); 2398 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2399 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2400 if (unlikely((*seg == qp->sq.qend))) 2401 *seg = mlx5_get_send_wqe(qp, 0); 2402 2403 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 2404 *seg += sizeof(struct mlx5_mkey_seg); 2405 *size += sizeof(struct mlx5_mkey_seg) / 16; 2406 if (unlikely((*seg == qp->sq.qend))) 2407 *seg = mlx5_get_send_wqe(qp, 0); 2408 2409 ret = set_sig_data_segment(wr, qp, seg, size); 2410 if (ret) 2411 return ret; 2412 2413 sig_mr->sig->sig_status_checked = false; 2414 return 0; 2415 } 2416 2417 static int set_psv_wr(struct ib_sig_domain *domain, 2418 u32 psv_idx, void **seg, int *size) 2419 { 2420 struct mlx5_seg_set_psv *psv_seg = *seg; 2421 2422 memset(psv_seg, 0, sizeof(*psv_seg)); 2423 psv_seg->psv_num = cpu_to_be32(psv_idx); 2424 switch (domain->sig_type) { 2425 case IB_SIG_TYPE_NONE: 2426 break; 2427 case IB_SIG_TYPE_T10_DIF: 2428 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 2429 domain->sig.dif.app_tag); 2430 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 2431 break; 2432 default: 2433 pr_err("Bad signature type given.\n"); 2434 return 1; 2435 } 2436 2437 *seg += sizeof(*psv_seg); 2438 *size += sizeof(*psv_seg) / 16; 2439 2440 return 0; 2441 } 2442 2443 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size, 2444 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp) 2445 { 2446 int writ = 0; 2447 int li; 2448 2449 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0; 2450 if (unlikely(wr->send_flags & IB_SEND_INLINE)) 2451 return -EINVAL; 2452 2453 set_frwr_umr_segment(*seg, wr, li); 2454 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2455 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2456 if (unlikely((*seg == qp->sq.qend))) 2457 *seg = mlx5_get_send_wqe(qp, 0); 2458 set_mkey_segment(*seg, wr, li, &writ); 2459 *seg += sizeof(struct mlx5_mkey_seg); 2460 *size += sizeof(struct mlx5_mkey_seg) / 16; 2461 if (unlikely((*seg == qp->sq.qend))) 2462 *seg = mlx5_get_send_wqe(qp, 0); 2463 if (!li) { 2464 if (unlikely(wr->wr.fast_reg.page_list_len > 2465 wr->wr.fast_reg.page_list->max_page_list_len)) 2466 return -ENOMEM; 2467 2468 set_frwr_pages(*seg, wr, mdev, pd, writ); 2469 *seg += sizeof(struct mlx5_wqe_data_seg); 2470 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 2471 } 2472 return 0; 2473 } 2474 2475 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 2476 { 2477 __be32 *p = NULL; 2478 int tidx = idx; 2479 int i, j; 2480 2481 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 2482 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 2483 if ((i & 0xf) == 0) { 2484 void *buf = mlx5_get_send_wqe(qp, tidx); 2485 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 2486 p = buf; 2487 j = 0; 2488 } 2489 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 2490 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 2491 be32_to_cpu(p[j + 3])); 2492 } 2493 } 2494 2495 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 2496 unsigned bytecnt, struct mlx5_ib_qp *qp) 2497 { 2498 while (bytecnt > 0) { 2499 __iowrite64_copy(dst++, src++, 8); 2500 __iowrite64_copy(dst++, src++, 8); 2501 __iowrite64_copy(dst++, src++, 8); 2502 __iowrite64_copy(dst++, src++, 8); 2503 __iowrite64_copy(dst++, src++, 8); 2504 __iowrite64_copy(dst++, src++, 8); 2505 __iowrite64_copy(dst++, src++, 8); 2506 __iowrite64_copy(dst++, src++, 8); 2507 bytecnt -= 64; 2508 if (unlikely(src == qp->sq.qend)) 2509 src = mlx5_get_send_wqe(qp, 0); 2510 } 2511 } 2512 2513 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 2514 { 2515 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 2516 wr->send_flags & IB_SEND_FENCE)) 2517 return MLX5_FENCE_MODE_STRONG_ORDERING; 2518 2519 if (unlikely(fence)) { 2520 if (wr->send_flags & IB_SEND_FENCE) 2521 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 2522 else 2523 return fence; 2524 2525 } else { 2526 return 0; 2527 } 2528 } 2529 2530 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 2531 struct mlx5_wqe_ctrl_seg **ctrl, 2532 struct ib_send_wr *wr, unsigned *idx, 2533 int *size, int nreq) 2534 { 2535 int err = 0; 2536 2537 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) { 2538 err = -ENOMEM; 2539 return err; 2540 } 2541 2542 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 2543 *seg = mlx5_get_send_wqe(qp, *idx); 2544 *ctrl = *seg; 2545 *(uint32_t *)(*seg + 8) = 0; 2546 (*ctrl)->imm = send_ieth(wr); 2547 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 2548 (wr->send_flags & IB_SEND_SIGNALED ? 2549 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 2550 (wr->send_flags & IB_SEND_SOLICITED ? 2551 MLX5_WQE_CTRL_SOLICITED : 0); 2552 2553 *seg += sizeof(**ctrl); 2554 *size = sizeof(**ctrl) / 16; 2555 2556 return err; 2557 } 2558 2559 static void finish_wqe(struct mlx5_ib_qp *qp, 2560 struct mlx5_wqe_ctrl_seg *ctrl, 2561 u8 size, unsigned idx, u64 wr_id, 2562 int nreq, u8 fence, u8 next_fence, 2563 u32 mlx5_opcode) 2564 { 2565 u8 opmod = 0; 2566 2567 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 2568 mlx5_opcode | ((u32)opmod << 24)); 2569 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8)); 2570 ctrl->fm_ce_se |= fence; 2571 qp->fm_cache = next_fence; 2572 if (unlikely(qp->wq_sig)) 2573 ctrl->signature = wq_sig(ctrl); 2574 2575 qp->sq.wrid[idx] = wr_id; 2576 qp->sq.w_list[idx].opcode = mlx5_opcode; 2577 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 2578 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 2579 qp->sq.w_list[idx].next = qp->sq.cur_post; 2580 } 2581 2582 2583 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 2584 struct ib_send_wr **bad_wr) 2585 { 2586 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 2587 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2588 struct mlx5_core_dev *mdev = dev->mdev; 2589 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2590 struct mlx5_ib_mr *mr; 2591 struct mlx5_wqe_data_seg *dpseg; 2592 struct mlx5_wqe_xrc_seg *xrc; 2593 struct mlx5_bf *bf = qp->bf; 2594 int uninitialized_var(size); 2595 void *qend = qp->sq.qend; 2596 unsigned long flags; 2597 unsigned idx; 2598 int err = 0; 2599 int inl = 0; 2600 int num_sge; 2601 void *seg; 2602 int nreq; 2603 int i; 2604 u8 next_fence = 0; 2605 u8 fence; 2606 2607 spin_lock_irqsave(&qp->sq.lock, flags); 2608 2609 for (nreq = 0; wr; nreq++, wr = wr->next) { 2610 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 2611 mlx5_ib_warn(dev, "\n"); 2612 err = -EINVAL; 2613 *bad_wr = wr; 2614 goto out; 2615 } 2616 2617 fence = qp->fm_cache; 2618 num_sge = wr->num_sge; 2619 if (unlikely(num_sge > qp->sq.max_gs)) { 2620 mlx5_ib_warn(dev, "\n"); 2621 err = -ENOMEM; 2622 *bad_wr = wr; 2623 goto out; 2624 } 2625 2626 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 2627 if (err) { 2628 mlx5_ib_warn(dev, "\n"); 2629 err = -ENOMEM; 2630 *bad_wr = wr; 2631 goto out; 2632 } 2633 2634 switch (ibqp->qp_type) { 2635 case IB_QPT_XRC_INI: 2636 xrc = seg; 2637 xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num); 2638 seg += sizeof(*xrc); 2639 size += sizeof(*xrc) / 16; 2640 /* fall through */ 2641 case IB_QPT_RC: 2642 switch (wr->opcode) { 2643 case IB_WR_RDMA_READ: 2644 case IB_WR_RDMA_WRITE: 2645 case IB_WR_RDMA_WRITE_WITH_IMM: 2646 set_raddr_seg(seg, wr->wr.rdma.remote_addr, 2647 wr->wr.rdma.rkey); 2648 seg += sizeof(struct mlx5_wqe_raddr_seg); 2649 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 2650 break; 2651 2652 case IB_WR_ATOMIC_CMP_AND_SWP: 2653 case IB_WR_ATOMIC_FETCH_AND_ADD: 2654 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 2655 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 2656 err = -ENOSYS; 2657 *bad_wr = wr; 2658 goto out; 2659 2660 case IB_WR_LOCAL_INV: 2661 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2662 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 2663 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 2664 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp); 2665 if (err) { 2666 mlx5_ib_warn(dev, "\n"); 2667 *bad_wr = wr; 2668 goto out; 2669 } 2670 num_sge = 0; 2671 break; 2672 2673 case IB_WR_FAST_REG_MR: 2674 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2675 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR; 2676 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey); 2677 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp); 2678 if (err) { 2679 mlx5_ib_warn(dev, "\n"); 2680 *bad_wr = wr; 2681 goto out; 2682 } 2683 num_sge = 0; 2684 break; 2685 2686 case IB_WR_REG_SIG_MR: 2687 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 2688 mr = to_mmr(wr->wr.sig_handover.sig_mr); 2689 2690 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 2691 err = set_sig_umr_wr(wr, qp, &seg, &size); 2692 if (err) { 2693 mlx5_ib_warn(dev, "\n"); 2694 *bad_wr = wr; 2695 goto out; 2696 } 2697 2698 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2699 nreq, get_fence(fence, wr), 2700 next_fence, MLX5_OPCODE_UMR); 2701 /* 2702 * SET_PSV WQEs are not signaled and solicited 2703 * on error 2704 */ 2705 wr->send_flags &= ~IB_SEND_SIGNALED; 2706 wr->send_flags |= IB_SEND_SOLICITED; 2707 err = begin_wqe(qp, &seg, &ctrl, wr, 2708 &idx, &size, nreq); 2709 if (err) { 2710 mlx5_ib_warn(dev, "\n"); 2711 err = -ENOMEM; 2712 *bad_wr = wr; 2713 goto out; 2714 } 2715 2716 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->mem, 2717 mr->sig->psv_memory.psv_idx, &seg, 2718 &size); 2719 if (err) { 2720 mlx5_ib_warn(dev, "\n"); 2721 *bad_wr = wr; 2722 goto out; 2723 } 2724 2725 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2726 nreq, get_fence(fence, wr), 2727 next_fence, MLX5_OPCODE_SET_PSV); 2728 err = begin_wqe(qp, &seg, &ctrl, wr, 2729 &idx, &size, nreq); 2730 if (err) { 2731 mlx5_ib_warn(dev, "\n"); 2732 err = -ENOMEM; 2733 *bad_wr = wr; 2734 goto out; 2735 } 2736 2737 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2738 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->wire, 2739 mr->sig->psv_wire.psv_idx, &seg, 2740 &size); 2741 if (err) { 2742 mlx5_ib_warn(dev, "\n"); 2743 *bad_wr = wr; 2744 goto out; 2745 } 2746 2747 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2748 nreq, get_fence(fence, wr), 2749 next_fence, MLX5_OPCODE_SET_PSV); 2750 num_sge = 0; 2751 goto skip_psv; 2752 2753 default: 2754 break; 2755 } 2756 break; 2757 2758 case IB_QPT_UC: 2759 switch (wr->opcode) { 2760 case IB_WR_RDMA_WRITE: 2761 case IB_WR_RDMA_WRITE_WITH_IMM: 2762 set_raddr_seg(seg, wr->wr.rdma.remote_addr, 2763 wr->wr.rdma.rkey); 2764 seg += sizeof(struct mlx5_wqe_raddr_seg); 2765 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 2766 break; 2767 2768 default: 2769 break; 2770 } 2771 break; 2772 2773 case IB_QPT_UD: 2774 case IB_QPT_SMI: 2775 case IB_QPT_GSI: 2776 set_datagram_seg(seg, wr); 2777 seg += sizeof(struct mlx5_wqe_datagram_seg); 2778 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 2779 if (unlikely((seg == qend))) 2780 seg = mlx5_get_send_wqe(qp, 0); 2781 break; 2782 2783 case MLX5_IB_QPT_REG_UMR: 2784 if (wr->opcode != MLX5_IB_WR_UMR) { 2785 err = -EINVAL; 2786 mlx5_ib_warn(dev, "bad opcode\n"); 2787 goto out; 2788 } 2789 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 2790 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey); 2791 set_reg_umr_segment(seg, wr); 2792 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2793 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2794 if (unlikely((seg == qend))) 2795 seg = mlx5_get_send_wqe(qp, 0); 2796 set_reg_mkey_segment(seg, wr); 2797 seg += sizeof(struct mlx5_mkey_seg); 2798 size += sizeof(struct mlx5_mkey_seg) / 16; 2799 if (unlikely((seg == qend))) 2800 seg = mlx5_get_send_wqe(qp, 0); 2801 break; 2802 2803 default: 2804 break; 2805 } 2806 2807 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 2808 int uninitialized_var(sz); 2809 2810 err = set_data_inl_seg(qp, wr, seg, &sz); 2811 if (unlikely(err)) { 2812 mlx5_ib_warn(dev, "\n"); 2813 *bad_wr = wr; 2814 goto out; 2815 } 2816 inl = 1; 2817 size += sz; 2818 } else { 2819 dpseg = seg; 2820 for (i = 0; i < num_sge; i++) { 2821 if (unlikely(dpseg == qend)) { 2822 seg = mlx5_get_send_wqe(qp, 0); 2823 dpseg = seg; 2824 } 2825 if (likely(wr->sg_list[i].length)) { 2826 set_data_ptr_seg(dpseg, wr->sg_list + i); 2827 size += sizeof(struct mlx5_wqe_data_seg) / 16; 2828 dpseg++; 2829 } 2830 } 2831 } 2832 2833 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 2834 get_fence(fence, wr), next_fence, 2835 mlx5_ib_opcode[wr->opcode]); 2836 skip_psv: 2837 if (0) 2838 dump_wqe(qp, idx, size); 2839 } 2840 2841 out: 2842 if (likely(nreq)) { 2843 qp->sq.head += nreq; 2844 2845 /* Make sure that descriptors are written before 2846 * updating doorbell record and ringing the doorbell 2847 */ 2848 wmb(); 2849 2850 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 2851 2852 /* Make sure doorbell record is visible to the HCA before 2853 * we hit doorbell */ 2854 wmb(); 2855 2856 if (bf->need_lock) 2857 spin_lock(&bf->lock); 2858 else 2859 __acquire(&bf->lock); 2860 2861 /* TBD enable WC */ 2862 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 2863 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 2864 /* wc_wmb(); */ 2865 } else { 2866 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 2867 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 2868 /* Make sure doorbells don't leak out of SQ spinlock 2869 * and reach the HCA out of order. 2870 */ 2871 mmiowb(); 2872 } 2873 bf->offset ^= bf->buf_size; 2874 if (bf->need_lock) 2875 spin_unlock(&bf->lock); 2876 else 2877 __release(&bf->lock); 2878 } 2879 2880 spin_unlock_irqrestore(&qp->sq.lock, flags); 2881 2882 return err; 2883 } 2884 2885 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 2886 { 2887 sig->signature = calc_sig(sig, size); 2888 } 2889 2890 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 2891 struct ib_recv_wr **bad_wr) 2892 { 2893 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2894 struct mlx5_wqe_data_seg *scat; 2895 struct mlx5_rwqe_sig *sig; 2896 unsigned long flags; 2897 int err = 0; 2898 int nreq; 2899 int ind; 2900 int i; 2901 2902 spin_lock_irqsave(&qp->rq.lock, flags); 2903 2904 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 2905 2906 for (nreq = 0; wr; nreq++, wr = wr->next) { 2907 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 2908 err = -ENOMEM; 2909 *bad_wr = wr; 2910 goto out; 2911 } 2912 2913 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 2914 err = -EINVAL; 2915 *bad_wr = wr; 2916 goto out; 2917 } 2918 2919 scat = get_recv_wqe(qp, ind); 2920 if (qp->wq_sig) 2921 scat++; 2922 2923 for (i = 0; i < wr->num_sge; i++) 2924 set_data_ptr_seg(scat + i, wr->sg_list + i); 2925 2926 if (i < qp->rq.max_gs) { 2927 scat[i].byte_count = 0; 2928 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 2929 scat[i].addr = 0; 2930 } 2931 2932 if (qp->wq_sig) { 2933 sig = (struct mlx5_rwqe_sig *)scat; 2934 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 2935 } 2936 2937 qp->rq.wrid[ind] = wr->wr_id; 2938 2939 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 2940 } 2941 2942 out: 2943 if (likely(nreq)) { 2944 qp->rq.head += nreq; 2945 2946 /* Make sure that descriptors are written before 2947 * doorbell record. 2948 */ 2949 wmb(); 2950 2951 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 2952 } 2953 2954 spin_unlock_irqrestore(&qp->rq.lock, flags); 2955 2956 return err; 2957 } 2958 2959 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 2960 { 2961 switch (mlx5_state) { 2962 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 2963 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 2964 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 2965 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 2966 case MLX5_QP_STATE_SQ_DRAINING: 2967 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 2968 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 2969 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 2970 default: return -1; 2971 } 2972 } 2973 2974 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 2975 { 2976 switch (mlx5_mig_state) { 2977 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 2978 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 2979 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 2980 default: return -1; 2981 } 2982 } 2983 2984 static int to_ib_qp_access_flags(int mlx5_flags) 2985 { 2986 int ib_flags = 0; 2987 2988 if (mlx5_flags & MLX5_QP_BIT_RRE) 2989 ib_flags |= IB_ACCESS_REMOTE_READ; 2990 if (mlx5_flags & MLX5_QP_BIT_RWE) 2991 ib_flags |= IB_ACCESS_REMOTE_WRITE; 2992 if (mlx5_flags & MLX5_QP_BIT_RAE) 2993 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 2994 2995 return ib_flags; 2996 } 2997 2998 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 2999 struct mlx5_qp_path *path) 3000 { 3001 struct mlx5_core_dev *dev = ibdev->mdev; 3002 3003 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 3004 ib_ah_attr->port_num = path->port; 3005 3006 if (ib_ah_attr->port_num == 0 || 3007 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 3008 return; 3009 3010 ib_ah_attr->sl = path->sl & 0xf; 3011 3012 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3013 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 3014 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3015 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 3016 if (ib_ah_attr->ah_flags) { 3017 ib_ah_attr->grh.sgid_index = path->mgid_index; 3018 ib_ah_attr->grh.hop_limit = path->hop_limit; 3019 ib_ah_attr->grh.traffic_class = 3020 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3021 ib_ah_attr->grh.flow_label = 3022 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3023 memcpy(ib_ah_attr->grh.dgid.raw, 3024 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 3025 } 3026 } 3027 3028 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3029 struct ib_qp_init_attr *qp_init_attr) 3030 { 3031 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3032 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3033 struct mlx5_query_qp_mbox_out *outb; 3034 struct mlx5_qp_context *context; 3035 int mlx5_state; 3036 int err = 0; 3037 3038 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 3039 /* 3040 * Wait for any outstanding page faults, in case the user frees memory 3041 * based upon this query's result. 3042 */ 3043 flush_workqueue(mlx5_ib_page_fault_wq); 3044 #endif 3045 3046 mutex_lock(&qp->mutex); 3047 outb = kzalloc(sizeof(*outb), GFP_KERNEL); 3048 if (!outb) { 3049 err = -ENOMEM; 3050 goto out; 3051 } 3052 context = &outb->ctx; 3053 err = mlx5_core_qp_query(dev->mdev, &qp->mqp, outb, sizeof(*outb)); 3054 if (err) 3055 goto out_free; 3056 3057 mlx5_state = be32_to_cpu(context->flags) >> 28; 3058 3059 qp->state = to_ib_qp_state(mlx5_state); 3060 qp_attr->qp_state = qp->state; 3061 qp_attr->path_mtu = context->mtu_msgmax >> 5; 3062 qp_attr->path_mig_state = 3063 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 3064 qp_attr->qkey = be32_to_cpu(context->qkey); 3065 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 3066 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 3067 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 3068 qp_attr->qp_access_flags = 3069 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 3070 3071 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3072 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 3073 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 3074 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f; 3075 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 3076 } 3077 3078 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f; 3079 qp_attr->port_num = context->pri_path.port; 3080 3081 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3082 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 3083 3084 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 3085 3086 qp_attr->max_dest_rd_atomic = 3087 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 3088 qp_attr->min_rnr_timer = 3089 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 3090 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 3091 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 3092 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 3093 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 3094 qp_attr->cur_qp_state = qp_attr->qp_state; 3095 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3096 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3097 3098 if (!ibqp->uobject) { 3099 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3100 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3101 } else { 3102 qp_attr->cap.max_send_wr = 0; 3103 qp_attr->cap.max_send_sge = 0; 3104 } 3105 3106 /* We don't support inline sends for kernel QPs (yet), and we 3107 * don't know what userspace's value should be. 3108 */ 3109 qp_attr->cap.max_inline_data = 0; 3110 3111 qp_init_attr->cap = qp_attr->cap; 3112 3113 qp_init_attr->create_flags = 0; 3114 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3115 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3116 3117 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 3118 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3119 3120 out_free: 3121 kfree(outb); 3122 3123 out: 3124 mutex_unlock(&qp->mutex); 3125 return err; 3126 } 3127 3128 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 3129 struct ib_ucontext *context, 3130 struct ib_udata *udata) 3131 { 3132 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3133 struct mlx5_ib_xrcd *xrcd; 3134 int err; 3135 3136 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3137 return ERR_PTR(-ENOSYS); 3138 3139 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 3140 if (!xrcd) 3141 return ERR_PTR(-ENOMEM); 3142 3143 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 3144 if (err) { 3145 kfree(xrcd); 3146 return ERR_PTR(-ENOMEM); 3147 } 3148 3149 return &xrcd->ibxrcd; 3150 } 3151 3152 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 3153 { 3154 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 3155 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 3156 int err; 3157 3158 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 3159 if (err) { 3160 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 3161 return err; 3162 } 3163 3164 kfree(xrcd); 3165 3166 return 0; 3167 } 3168