1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 41 /* not supported currently */ 42 static int wq_signature; 43 44 enum { 45 MLX5_IB_ACK_REQ_FREQ = 8, 46 }; 47 48 enum { 49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 51 MLX5_IB_LINK_TYPE_IB = 0, 52 MLX5_IB_LINK_TYPE_ETH = 1 53 }; 54 55 enum { 56 MLX5_IB_SQ_STRIDE = 6, 57 }; 58 59 static const u32 mlx5_ib_opcode[] = { 60 [IB_WR_SEND] = MLX5_OPCODE_SEND, 61 [IB_WR_LSO] = MLX5_OPCODE_LSO, 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 74 }; 75 76 struct mlx5_wqe_eth_pad { 77 u8 rsvd0[16]; 78 }; 79 80 enum raw_qp_set_mask_map { 81 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 82 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 83 }; 84 85 struct mlx5_modify_raw_qp_param { 86 u16 operation; 87 88 u32 set_mask; /* raw_qp_set_mask_map */ 89 90 struct mlx5_rate_limit rl; 91 92 u8 rq_q_ctr_id; 93 }; 94 95 static void get_cqs(enum ib_qp_type qp_type, 96 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 97 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 98 99 static int is_qp0(enum ib_qp_type qp_type) 100 { 101 return qp_type == IB_QPT_SMI; 102 } 103 104 static int is_sqp(enum ib_qp_type qp_type) 105 { 106 return is_qp0(qp_type) || is_qp1(qp_type); 107 } 108 109 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 110 { 111 return mlx5_buf_offset(&qp->buf, offset); 112 } 113 114 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 115 { 116 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 117 } 118 119 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 120 { 121 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 122 } 123 124 /** 125 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 126 * 127 * @qp: QP to copy from. 128 * @send: copy from the send queue when non-zero, use the receive queue 129 * otherwise. 130 * @wqe_index: index to start copying from. For send work queues, the 131 * wqe_index is in units of MLX5_SEND_WQE_BB. 132 * For receive work queue, it is the number of work queue 133 * element in the queue. 134 * @buffer: destination buffer. 135 * @length: maximum number of bytes to copy. 136 * 137 * Copies at least a single WQE, but may copy more data. 138 * 139 * Return: the number of bytes copied, or an error code. 140 */ 141 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 142 void *buffer, u32 length, 143 struct mlx5_ib_qp_base *base) 144 { 145 struct ib_device *ibdev = qp->ibqp.device; 146 struct mlx5_ib_dev *dev = to_mdev(ibdev); 147 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 148 size_t offset; 149 size_t wq_end; 150 struct ib_umem *umem = base->ubuffer.umem; 151 u32 first_copy_length; 152 int wqe_length; 153 int ret; 154 155 if (wq->wqe_cnt == 0) { 156 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 157 qp->ibqp.qp_type); 158 return -EINVAL; 159 } 160 161 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 162 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 163 164 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 165 return -EINVAL; 166 167 if (offset > umem->length || 168 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 169 return -EINVAL; 170 171 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 172 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 173 if (ret) 174 return ret; 175 176 if (send) { 177 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 178 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 179 180 wqe_length = ds * MLX5_WQE_DS_UNITS; 181 } else { 182 wqe_length = 1 << wq->wqe_shift; 183 } 184 185 if (wqe_length <= first_copy_length) 186 return first_copy_length; 187 188 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 189 wqe_length - first_copy_length); 190 if (ret) 191 return ret; 192 193 return wqe_length; 194 } 195 196 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 197 { 198 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 199 struct ib_event event; 200 201 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 202 /* This event is only valid for trans_qps */ 203 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 204 } 205 206 if (ibqp->event_handler) { 207 event.device = ibqp->device; 208 event.element.qp = ibqp; 209 switch (type) { 210 case MLX5_EVENT_TYPE_PATH_MIG: 211 event.event = IB_EVENT_PATH_MIG; 212 break; 213 case MLX5_EVENT_TYPE_COMM_EST: 214 event.event = IB_EVENT_COMM_EST; 215 break; 216 case MLX5_EVENT_TYPE_SQ_DRAINED: 217 event.event = IB_EVENT_SQ_DRAINED; 218 break; 219 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 220 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 221 break; 222 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 223 event.event = IB_EVENT_QP_FATAL; 224 break; 225 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 226 event.event = IB_EVENT_PATH_MIG_ERR; 227 break; 228 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 229 event.event = IB_EVENT_QP_REQ_ERR; 230 break; 231 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 232 event.event = IB_EVENT_QP_ACCESS_ERR; 233 break; 234 default: 235 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 236 return; 237 } 238 239 ibqp->event_handler(&event, ibqp->qp_context); 240 } 241 } 242 243 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 244 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 245 { 246 int wqe_size; 247 int wq_size; 248 249 /* Sanity check RQ size before proceeding */ 250 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 251 return -EINVAL; 252 253 if (!has_rq) { 254 qp->rq.max_gs = 0; 255 qp->rq.wqe_cnt = 0; 256 qp->rq.wqe_shift = 0; 257 cap->max_recv_wr = 0; 258 cap->max_recv_sge = 0; 259 } else { 260 if (ucmd) { 261 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 262 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 263 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 264 qp->rq.max_post = qp->rq.wqe_cnt; 265 } else { 266 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 267 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 268 wqe_size = roundup_pow_of_two(wqe_size); 269 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 270 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 271 qp->rq.wqe_cnt = wq_size / wqe_size; 272 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 273 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 274 wqe_size, 275 MLX5_CAP_GEN(dev->mdev, 276 max_wqe_sz_rq)); 277 return -EINVAL; 278 } 279 qp->rq.wqe_shift = ilog2(wqe_size); 280 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 281 qp->rq.max_post = qp->rq.wqe_cnt; 282 } 283 } 284 285 return 0; 286 } 287 288 static int sq_overhead(struct ib_qp_init_attr *attr) 289 { 290 int size = 0; 291 292 switch (attr->qp_type) { 293 case IB_QPT_XRC_INI: 294 size += sizeof(struct mlx5_wqe_xrc_seg); 295 /* fall through */ 296 case IB_QPT_RC: 297 size += sizeof(struct mlx5_wqe_ctrl_seg) + 298 max(sizeof(struct mlx5_wqe_atomic_seg) + 299 sizeof(struct mlx5_wqe_raddr_seg), 300 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 301 sizeof(struct mlx5_mkey_seg)); 302 break; 303 304 case IB_QPT_XRC_TGT: 305 return 0; 306 307 case IB_QPT_UC: 308 size += sizeof(struct mlx5_wqe_ctrl_seg) + 309 max(sizeof(struct mlx5_wqe_raddr_seg), 310 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 311 sizeof(struct mlx5_mkey_seg)); 312 break; 313 314 case IB_QPT_UD: 315 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 316 size += sizeof(struct mlx5_wqe_eth_pad) + 317 sizeof(struct mlx5_wqe_eth_seg); 318 /* fall through */ 319 case IB_QPT_SMI: 320 case MLX5_IB_QPT_HW_GSI: 321 size += sizeof(struct mlx5_wqe_ctrl_seg) + 322 sizeof(struct mlx5_wqe_datagram_seg); 323 break; 324 325 case MLX5_IB_QPT_REG_UMR: 326 size += sizeof(struct mlx5_wqe_ctrl_seg) + 327 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 328 sizeof(struct mlx5_mkey_seg); 329 break; 330 331 default: 332 return -EINVAL; 333 } 334 335 return size; 336 } 337 338 static int calc_send_wqe(struct ib_qp_init_attr *attr) 339 { 340 int inl_size = 0; 341 int size; 342 343 size = sq_overhead(attr); 344 if (size < 0) 345 return size; 346 347 if (attr->cap.max_inline_data) { 348 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 349 attr->cap.max_inline_data; 350 } 351 352 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 353 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 354 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 355 return MLX5_SIG_WQE_SIZE; 356 else 357 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 358 } 359 360 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 361 { 362 int max_sge; 363 364 if (attr->qp_type == IB_QPT_RC) 365 max_sge = (min_t(int, wqe_size, 512) - 366 sizeof(struct mlx5_wqe_ctrl_seg) - 367 sizeof(struct mlx5_wqe_raddr_seg)) / 368 sizeof(struct mlx5_wqe_data_seg); 369 else if (attr->qp_type == IB_QPT_XRC_INI) 370 max_sge = (min_t(int, wqe_size, 512) - 371 sizeof(struct mlx5_wqe_ctrl_seg) - 372 sizeof(struct mlx5_wqe_xrc_seg) - 373 sizeof(struct mlx5_wqe_raddr_seg)) / 374 sizeof(struct mlx5_wqe_data_seg); 375 else 376 max_sge = (wqe_size - sq_overhead(attr)) / 377 sizeof(struct mlx5_wqe_data_seg); 378 379 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 380 sizeof(struct mlx5_wqe_data_seg)); 381 } 382 383 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 384 struct mlx5_ib_qp *qp) 385 { 386 int wqe_size; 387 int wq_size; 388 389 if (!attr->cap.max_send_wr) 390 return 0; 391 392 wqe_size = calc_send_wqe(attr); 393 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 394 if (wqe_size < 0) 395 return wqe_size; 396 397 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 398 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 399 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 400 return -EINVAL; 401 } 402 403 qp->max_inline_data = wqe_size - sq_overhead(attr) - 404 sizeof(struct mlx5_wqe_inline_seg); 405 attr->cap.max_inline_data = qp->max_inline_data; 406 407 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 408 qp->signature_en = true; 409 410 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 411 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 412 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 413 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 414 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 415 qp->sq.wqe_cnt, 416 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 417 return -ENOMEM; 418 } 419 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 420 qp->sq.max_gs = get_send_sge(attr, wqe_size); 421 if (qp->sq.max_gs < attr->cap.max_send_sge) 422 return -ENOMEM; 423 424 attr->cap.max_send_sge = qp->sq.max_gs; 425 qp->sq.max_post = wq_size / wqe_size; 426 attr->cap.max_send_wr = qp->sq.max_post; 427 428 return wq_size; 429 } 430 431 static int set_user_buf_size(struct mlx5_ib_dev *dev, 432 struct mlx5_ib_qp *qp, 433 struct mlx5_ib_create_qp *ucmd, 434 struct mlx5_ib_qp_base *base, 435 struct ib_qp_init_attr *attr) 436 { 437 int desc_sz = 1 << qp->sq.wqe_shift; 438 439 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 440 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 441 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 442 return -EINVAL; 443 } 444 445 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 446 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 447 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 448 return -EINVAL; 449 } 450 451 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 452 453 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 454 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 455 qp->sq.wqe_cnt, 456 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 457 return -EINVAL; 458 } 459 460 if (attr->qp_type == IB_QPT_RAW_PACKET || 461 qp->flags & MLX5_IB_QP_UNDERLAY) { 462 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 463 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 464 } else { 465 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 466 (qp->sq.wqe_cnt << 6); 467 } 468 469 return 0; 470 } 471 472 static int qp_has_rq(struct ib_qp_init_attr *attr) 473 { 474 if (attr->qp_type == IB_QPT_XRC_INI || 475 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 476 attr->qp_type == MLX5_IB_QPT_REG_UMR || 477 !attr->cap.max_recv_wr) 478 return 0; 479 480 return 1; 481 } 482 483 static int first_med_bfreg(void) 484 { 485 return 1; 486 } 487 488 enum { 489 /* this is the first blue flame register in the array of bfregs assigned 490 * to a processes. Since we do not use it for blue flame but rather 491 * regular 64 bit doorbells, we do not need a lock for maintaiing 492 * "odd/even" order 493 */ 494 NUM_NON_BLUE_FLAME_BFREGS = 1, 495 }; 496 497 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 498 { 499 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 500 } 501 502 static int num_med_bfreg(struct mlx5_ib_dev *dev, 503 struct mlx5_bfreg_info *bfregi) 504 { 505 int n; 506 507 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 508 NUM_NON_BLUE_FLAME_BFREGS; 509 510 return n >= 0 ? n : 0; 511 } 512 513 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 514 struct mlx5_bfreg_info *bfregi) 515 { 516 int med; 517 518 med = num_med_bfreg(dev, bfregi); 519 return ++med; 520 } 521 522 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 523 struct mlx5_bfreg_info *bfregi) 524 { 525 int i; 526 527 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 528 if (!bfregi->count[i]) { 529 bfregi->count[i]++; 530 return i; 531 } 532 } 533 534 return -ENOMEM; 535 } 536 537 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 538 struct mlx5_bfreg_info *bfregi) 539 { 540 int minidx = first_med_bfreg(); 541 int i; 542 543 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) { 544 if (bfregi->count[i] < bfregi->count[minidx]) 545 minidx = i; 546 if (!bfregi->count[minidx]) 547 break; 548 } 549 550 bfregi->count[minidx]++; 551 return minidx; 552 } 553 554 static int alloc_bfreg(struct mlx5_ib_dev *dev, 555 struct mlx5_bfreg_info *bfregi, 556 enum mlx5_ib_latency_class lat) 557 { 558 int bfregn = -EINVAL; 559 560 mutex_lock(&bfregi->lock); 561 switch (lat) { 562 case MLX5_IB_LATENCY_CLASS_LOW: 563 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 564 bfregn = 0; 565 bfregi->count[bfregn]++; 566 break; 567 568 case MLX5_IB_LATENCY_CLASS_MEDIUM: 569 if (bfregi->ver < 2) 570 bfregn = -ENOMEM; 571 else 572 bfregn = alloc_med_class_bfreg(dev, bfregi); 573 break; 574 575 case MLX5_IB_LATENCY_CLASS_HIGH: 576 if (bfregi->ver < 2) 577 bfregn = -ENOMEM; 578 else 579 bfregn = alloc_high_class_bfreg(dev, bfregi); 580 break; 581 } 582 mutex_unlock(&bfregi->lock); 583 584 return bfregn; 585 } 586 587 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 588 { 589 mutex_lock(&bfregi->lock); 590 bfregi->count[bfregn]--; 591 mutex_unlock(&bfregi->lock); 592 } 593 594 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 595 { 596 switch (state) { 597 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 598 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 599 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 600 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 601 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 602 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 603 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 604 default: return -1; 605 } 606 } 607 608 static int to_mlx5_st(enum ib_qp_type type) 609 { 610 switch (type) { 611 case IB_QPT_RC: return MLX5_QP_ST_RC; 612 case IB_QPT_UC: return MLX5_QP_ST_UC; 613 case IB_QPT_UD: return MLX5_QP_ST_UD; 614 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 615 case IB_QPT_XRC_INI: 616 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 617 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 618 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 619 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 620 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 621 case IB_QPT_RAW_PACKET: 622 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 623 case IB_QPT_MAX: 624 default: return -EINVAL; 625 } 626 } 627 628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 629 struct mlx5_ib_cq *recv_cq); 630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 631 struct mlx5_ib_cq *recv_cq); 632 633 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 634 struct mlx5_bfreg_info *bfregi, int bfregn, 635 bool dyn_bfreg) 636 { 637 int bfregs_per_sys_page; 638 int index_of_sys_page; 639 int offset; 640 641 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 642 MLX5_NON_FP_BFREGS_PER_UAR; 643 index_of_sys_page = bfregn / bfregs_per_sys_page; 644 645 if (dyn_bfreg) { 646 index_of_sys_page += bfregi->num_static_sys_pages; 647 if (bfregn > bfregi->num_dyn_bfregs || 648 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 649 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 650 return -EINVAL; 651 } 652 } 653 654 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 655 return bfregi->sys_pages[index_of_sys_page] + offset; 656 } 657 658 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 659 struct ib_pd *pd, 660 unsigned long addr, size_t size, 661 struct ib_umem **umem, 662 int *npages, int *page_shift, int *ncont, 663 u32 *offset) 664 { 665 int err; 666 667 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 668 if (IS_ERR(*umem)) { 669 mlx5_ib_dbg(dev, "umem_get failed\n"); 670 return PTR_ERR(*umem); 671 } 672 673 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 674 675 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 676 if (err) { 677 mlx5_ib_warn(dev, "bad offset\n"); 678 goto err_umem; 679 } 680 681 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 682 addr, size, *npages, *page_shift, *ncont, *offset); 683 684 return 0; 685 686 err_umem: 687 ib_umem_release(*umem); 688 *umem = NULL; 689 690 return err; 691 } 692 693 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 694 struct mlx5_ib_rwq *rwq) 695 { 696 struct mlx5_ib_ucontext *context; 697 698 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 699 atomic_dec(&dev->delay_drop.rqs_cnt); 700 701 context = to_mucontext(pd->uobject->context); 702 mlx5_ib_db_unmap_user(context, &rwq->db); 703 if (rwq->umem) 704 ib_umem_release(rwq->umem); 705 } 706 707 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 708 struct mlx5_ib_rwq *rwq, 709 struct mlx5_ib_create_wq *ucmd) 710 { 711 struct mlx5_ib_ucontext *context; 712 int page_shift = 0; 713 int npages; 714 u32 offset = 0; 715 int ncont = 0; 716 int err; 717 718 if (!ucmd->buf_addr) 719 return -EINVAL; 720 721 context = to_mucontext(pd->uobject->context); 722 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 723 rwq->buf_size, 0, 0); 724 if (IS_ERR(rwq->umem)) { 725 mlx5_ib_dbg(dev, "umem_get failed\n"); 726 err = PTR_ERR(rwq->umem); 727 return err; 728 } 729 730 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 731 &ncont, NULL); 732 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 733 &rwq->rq_page_offset); 734 if (err) { 735 mlx5_ib_warn(dev, "bad offset\n"); 736 goto err_umem; 737 } 738 739 rwq->rq_num_pas = ncont; 740 rwq->page_shift = page_shift; 741 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 742 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 743 744 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 745 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 746 npages, page_shift, ncont, offset); 747 748 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 749 if (err) { 750 mlx5_ib_dbg(dev, "map failed\n"); 751 goto err_umem; 752 } 753 754 rwq->create_type = MLX5_WQ_USER; 755 return 0; 756 757 err_umem: 758 ib_umem_release(rwq->umem); 759 return err; 760 } 761 762 static int adjust_bfregn(struct mlx5_ib_dev *dev, 763 struct mlx5_bfreg_info *bfregi, int bfregn) 764 { 765 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 766 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 767 } 768 769 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 770 struct mlx5_ib_qp *qp, struct ib_udata *udata, 771 struct ib_qp_init_attr *attr, 772 u32 **in, 773 struct mlx5_ib_create_qp_resp *resp, int *inlen, 774 struct mlx5_ib_qp_base *base) 775 { 776 struct mlx5_ib_ucontext *context; 777 struct mlx5_ib_create_qp ucmd; 778 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 779 int page_shift = 0; 780 int uar_index = 0; 781 int npages; 782 u32 offset = 0; 783 int bfregn; 784 int ncont = 0; 785 __be64 *pas; 786 void *qpc; 787 int err; 788 789 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 790 if (err) { 791 mlx5_ib_dbg(dev, "copy failed\n"); 792 return err; 793 } 794 795 context = to_mucontext(pd->uobject->context); 796 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 797 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 798 ucmd.bfreg_index, true); 799 if (uar_index < 0) 800 return uar_index; 801 802 bfregn = MLX5_IB_INVALID_BFREG; 803 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 804 /* 805 * TBD: should come from the verbs when we have the API 806 */ 807 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 808 bfregn = MLX5_CROSS_CHANNEL_BFREG; 809 } 810 else { 811 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 812 if (bfregn < 0) { 813 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 814 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 815 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 816 if (bfregn < 0) { 817 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 818 mlx5_ib_dbg(dev, "reverting to high latency\n"); 819 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 820 if (bfregn < 0) { 821 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 822 return bfregn; 823 } 824 } 825 } 826 } 827 828 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 829 if (bfregn != MLX5_IB_INVALID_BFREG) 830 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 831 false); 832 833 qp->rq.offset = 0; 834 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 835 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 836 837 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 838 if (err) 839 goto err_bfreg; 840 841 if (ucmd.buf_addr && ubuffer->buf_size) { 842 ubuffer->buf_addr = ucmd.buf_addr; 843 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 844 ubuffer->buf_size, 845 &ubuffer->umem, &npages, &page_shift, 846 &ncont, &offset); 847 if (err) 848 goto err_bfreg; 849 } else { 850 ubuffer->umem = NULL; 851 } 852 853 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 854 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 855 *in = kvzalloc(*inlen, GFP_KERNEL); 856 if (!*in) { 857 err = -ENOMEM; 858 goto err_umem; 859 } 860 861 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 862 if (ubuffer->umem) 863 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 864 865 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 866 867 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 868 MLX5_SET(qpc, qpc, page_offset, offset); 869 870 MLX5_SET(qpc, qpc, uar_page, uar_index); 871 if (bfregn != MLX5_IB_INVALID_BFREG) 872 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 873 else 874 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 875 qp->bfregn = bfregn; 876 877 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 878 if (err) { 879 mlx5_ib_dbg(dev, "map failed\n"); 880 goto err_free; 881 } 882 883 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 884 if (err) { 885 mlx5_ib_dbg(dev, "copy failed\n"); 886 goto err_unmap; 887 } 888 qp->create_type = MLX5_QP_USER; 889 890 return 0; 891 892 err_unmap: 893 mlx5_ib_db_unmap_user(context, &qp->db); 894 895 err_free: 896 kvfree(*in); 897 898 err_umem: 899 if (ubuffer->umem) 900 ib_umem_release(ubuffer->umem); 901 902 err_bfreg: 903 if (bfregn != MLX5_IB_INVALID_BFREG) 904 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 905 return err; 906 } 907 908 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 909 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 910 { 911 struct mlx5_ib_ucontext *context; 912 913 context = to_mucontext(pd->uobject->context); 914 mlx5_ib_db_unmap_user(context, &qp->db); 915 if (base->ubuffer.umem) 916 ib_umem_release(base->ubuffer.umem); 917 918 /* 919 * Free only the BFREGs which are handled by the kernel. 920 * BFREGs of UARs allocated dynamically are handled by user. 921 */ 922 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 923 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 924 } 925 926 static int create_kernel_qp(struct mlx5_ib_dev *dev, 927 struct ib_qp_init_attr *init_attr, 928 struct mlx5_ib_qp *qp, 929 u32 **in, int *inlen, 930 struct mlx5_ib_qp_base *base) 931 { 932 int uar_index; 933 void *qpc; 934 int err; 935 936 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 937 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 938 IB_QP_CREATE_IPOIB_UD_LSO | 939 IB_QP_CREATE_NETIF_QP | 940 mlx5_ib_create_qp_sqpn_qp1())) 941 return -EINVAL; 942 943 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 944 qp->bf.bfreg = &dev->fp_bfreg; 945 else 946 qp->bf.bfreg = &dev->bfreg; 947 948 /* We need to divide by two since each register is comprised of 949 * two buffers of identical size, namely odd and even 950 */ 951 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 952 uar_index = qp->bf.bfreg->index; 953 954 err = calc_sq_size(dev, init_attr, qp); 955 if (err < 0) { 956 mlx5_ib_dbg(dev, "err %d\n", err); 957 return err; 958 } 959 960 qp->rq.offset = 0; 961 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 962 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 963 964 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 965 if (err) { 966 mlx5_ib_dbg(dev, "err %d\n", err); 967 return err; 968 } 969 970 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 971 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 972 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 973 *in = kvzalloc(*inlen, GFP_KERNEL); 974 if (!*in) { 975 err = -ENOMEM; 976 goto err_buf; 977 } 978 979 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 980 MLX5_SET(qpc, qpc, uar_page, uar_index); 981 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 982 983 /* Set "fast registration enabled" for all kernel QPs */ 984 MLX5_SET(qpc, qpc, fre, 1); 985 MLX5_SET(qpc, qpc, rlky, 1); 986 987 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 988 MLX5_SET(qpc, qpc, deth_sqpn, 1); 989 qp->flags |= MLX5_IB_QP_SQPN_QP1; 990 } 991 992 mlx5_fill_page_array(&qp->buf, 993 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 994 995 err = mlx5_db_alloc(dev->mdev, &qp->db); 996 if (err) { 997 mlx5_ib_dbg(dev, "err %d\n", err); 998 goto err_free; 999 } 1000 1001 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1002 sizeof(*qp->sq.wrid), GFP_KERNEL); 1003 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1004 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1005 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1006 sizeof(*qp->rq.wrid), GFP_KERNEL); 1007 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1008 sizeof(*qp->sq.w_list), GFP_KERNEL); 1009 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1010 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1011 1012 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1013 !qp->sq.w_list || !qp->sq.wqe_head) { 1014 err = -ENOMEM; 1015 goto err_wrid; 1016 } 1017 qp->create_type = MLX5_QP_KERNEL; 1018 1019 return 0; 1020 1021 err_wrid: 1022 kvfree(qp->sq.wqe_head); 1023 kvfree(qp->sq.w_list); 1024 kvfree(qp->sq.wrid); 1025 kvfree(qp->sq.wr_data); 1026 kvfree(qp->rq.wrid); 1027 mlx5_db_free(dev->mdev, &qp->db); 1028 1029 err_free: 1030 kvfree(*in); 1031 1032 err_buf: 1033 mlx5_buf_free(dev->mdev, &qp->buf); 1034 return err; 1035 } 1036 1037 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1038 { 1039 kvfree(qp->sq.wqe_head); 1040 kvfree(qp->sq.w_list); 1041 kvfree(qp->sq.wrid); 1042 kvfree(qp->sq.wr_data); 1043 kvfree(qp->rq.wrid); 1044 mlx5_db_free(dev->mdev, &qp->db); 1045 mlx5_buf_free(dev->mdev, &qp->buf); 1046 } 1047 1048 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1049 { 1050 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1051 (attr->qp_type == MLX5_IB_QPT_DCI) || 1052 (attr->qp_type == IB_QPT_XRC_INI)) 1053 return MLX5_SRQ_RQ; 1054 else if (!qp->has_rq) 1055 return MLX5_ZERO_LEN_RQ; 1056 else 1057 return MLX5_NON_ZERO_RQ; 1058 } 1059 1060 static int is_connected(enum ib_qp_type qp_type) 1061 { 1062 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1063 return 1; 1064 1065 return 0; 1066 } 1067 1068 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1069 struct mlx5_ib_qp *qp, 1070 struct mlx5_ib_sq *sq, u32 tdn) 1071 { 1072 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1073 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1074 1075 MLX5_SET(tisc, tisc, transport_domain, tdn); 1076 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1077 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1078 1079 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1080 } 1081 1082 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1083 struct mlx5_ib_sq *sq) 1084 { 1085 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1086 } 1087 1088 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1089 struct mlx5_ib_sq *sq) 1090 { 1091 if (sq->flow_rule) 1092 mlx5_del_flow_rules(sq->flow_rule); 1093 } 1094 1095 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1096 struct mlx5_ib_sq *sq, void *qpin, 1097 struct ib_pd *pd) 1098 { 1099 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1100 __be64 *pas; 1101 void *in; 1102 void *sqc; 1103 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1104 void *wq; 1105 int inlen; 1106 int err; 1107 int page_shift = 0; 1108 int npages; 1109 int ncont = 0; 1110 u32 offset = 0; 1111 1112 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1113 &sq->ubuffer.umem, &npages, &page_shift, 1114 &ncont, &offset); 1115 if (err) 1116 return err; 1117 1118 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1119 in = kvzalloc(inlen, GFP_KERNEL); 1120 if (!in) { 1121 err = -ENOMEM; 1122 goto err_umem; 1123 } 1124 1125 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1126 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1127 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1128 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1129 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1130 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1131 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1132 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1133 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1134 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1135 MLX5_CAP_ETH(dev->mdev, swp)) 1136 MLX5_SET(sqc, sqc, allow_swp, 1); 1137 1138 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1139 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1140 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1141 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1142 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1143 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1144 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1145 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1146 MLX5_SET(wq, wq, page_offset, offset); 1147 1148 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1149 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1150 1151 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1152 1153 kvfree(in); 1154 1155 if (err) 1156 goto err_umem; 1157 1158 err = create_flow_rule_vport_sq(dev, sq); 1159 if (err) 1160 goto err_flow; 1161 1162 return 0; 1163 1164 err_flow: 1165 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1166 1167 err_umem: 1168 ib_umem_release(sq->ubuffer.umem); 1169 sq->ubuffer.umem = NULL; 1170 1171 return err; 1172 } 1173 1174 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1175 struct mlx5_ib_sq *sq) 1176 { 1177 destroy_flow_rule_vport_sq(dev, sq); 1178 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1179 ib_umem_release(sq->ubuffer.umem); 1180 } 1181 1182 static size_t get_rq_pas_size(void *qpc) 1183 { 1184 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1185 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1186 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1187 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1188 u32 po_quanta = 1 << (log_page_size - 6); 1189 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1190 u32 page_size = 1 << log_page_size; 1191 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1192 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1193 1194 return rq_num_pas * sizeof(u64); 1195 } 1196 1197 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1198 struct mlx5_ib_rq *rq, void *qpin, 1199 size_t qpinlen) 1200 { 1201 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1202 __be64 *pas; 1203 __be64 *qp_pas; 1204 void *in; 1205 void *rqc; 1206 void *wq; 1207 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1208 size_t rq_pas_size = get_rq_pas_size(qpc); 1209 size_t inlen; 1210 int err; 1211 1212 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1213 return -EINVAL; 1214 1215 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1216 in = kvzalloc(inlen, GFP_KERNEL); 1217 if (!in) 1218 return -ENOMEM; 1219 1220 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1221 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1222 MLX5_SET(rqc, rqc, vsd, 1); 1223 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1224 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1225 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1226 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1227 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1228 1229 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1230 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1231 1232 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1233 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1234 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1235 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1236 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1237 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1238 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1239 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1240 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1241 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1242 1243 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1244 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1245 memcpy(pas, qp_pas, rq_pas_size); 1246 1247 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1248 1249 kvfree(in); 1250 1251 return err; 1252 } 1253 1254 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1255 struct mlx5_ib_rq *rq) 1256 { 1257 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1258 } 1259 1260 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1261 { 1262 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1263 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1264 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1265 } 1266 1267 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1268 struct mlx5_ib_rq *rq, u32 tdn, 1269 bool tunnel_offload_en) 1270 { 1271 u32 *in; 1272 void *tirc; 1273 int inlen; 1274 int err; 1275 1276 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1277 in = kvzalloc(inlen, GFP_KERNEL); 1278 if (!in) 1279 return -ENOMEM; 1280 1281 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1282 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1283 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1284 MLX5_SET(tirc, tirc, transport_domain, tdn); 1285 if (tunnel_offload_en) 1286 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1287 1288 if (dev->rep) 1289 MLX5_SET(tirc, tirc, self_lb_block, 1290 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1291 1292 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1293 1294 kvfree(in); 1295 1296 return err; 1297 } 1298 1299 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1300 struct mlx5_ib_rq *rq) 1301 { 1302 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1303 } 1304 1305 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1306 u32 *in, size_t inlen, 1307 struct ib_pd *pd) 1308 { 1309 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1310 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1311 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1312 struct ib_uobject *uobj = pd->uobject; 1313 struct ib_ucontext *ucontext = uobj->context; 1314 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1315 int err; 1316 u32 tdn = mucontext->tdn; 1317 1318 if (qp->sq.wqe_cnt) { 1319 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1320 if (err) 1321 return err; 1322 1323 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1324 if (err) 1325 goto err_destroy_tis; 1326 1327 sq->base.container_mibqp = qp; 1328 sq->base.mqp.event = mlx5_ib_qp_event; 1329 } 1330 1331 if (qp->rq.wqe_cnt) { 1332 rq->base.container_mibqp = qp; 1333 1334 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1335 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1336 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1337 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1338 err = create_raw_packet_qp_rq(dev, rq, in, inlen); 1339 if (err) 1340 goto err_destroy_sq; 1341 1342 1343 err = create_raw_packet_qp_tir(dev, rq, tdn, 1344 qp->tunnel_offload_en); 1345 if (err) 1346 goto err_destroy_rq; 1347 } 1348 1349 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1350 rq->base.mqp.qpn; 1351 1352 return 0; 1353 1354 err_destroy_rq: 1355 destroy_raw_packet_qp_rq(dev, rq); 1356 err_destroy_sq: 1357 if (!qp->sq.wqe_cnt) 1358 return err; 1359 destroy_raw_packet_qp_sq(dev, sq); 1360 err_destroy_tis: 1361 destroy_raw_packet_qp_tis(dev, sq); 1362 1363 return err; 1364 } 1365 1366 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1367 struct mlx5_ib_qp *qp) 1368 { 1369 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1370 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1371 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1372 1373 if (qp->rq.wqe_cnt) { 1374 destroy_raw_packet_qp_tir(dev, rq); 1375 destroy_raw_packet_qp_rq(dev, rq); 1376 } 1377 1378 if (qp->sq.wqe_cnt) { 1379 destroy_raw_packet_qp_sq(dev, sq); 1380 destroy_raw_packet_qp_tis(dev, sq); 1381 } 1382 } 1383 1384 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1385 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1386 { 1387 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1388 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1389 1390 sq->sq = &qp->sq; 1391 rq->rq = &qp->rq; 1392 sq->doorbell = &qp->db; 1393 rq->doorbell = &qp->db; 1394 } 1395 1396 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1397 { 1398 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1399 } 1400 1401 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1402 struct ib_pd *pd, 1403 struct ib_qp_init_attr *init_attr, 1404 struct ib_udata *udata) 1405 { 1406 struct ib_uobject *uobj = pd->uobject; 1407 struct ib_ucontext *ucontext = uobj->context; 1408 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1409 struct mlx5_ib_create_qp_resp resp = {}; 1410 int inlen; 1411 int err; 1412 u32 *in; 1413 void *tirc; 1414 void *hfso; 1415 u32 selected_fields = 0; 1416 u32 outer_l4; 1417 size_t min_resp_len; 1418 u32 tdn = mucontext->tdn; 1419 struct mlx5_ib_create_qp_rss ucmd = {}; 1420 size_t required_cmd_sz; 1421 1422 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1423 return -EOPNOTSUPP; 1424 1425 if (init_attr->create_flags || init_attr->send_cq) 1426 return -EINVAL; 1427 1428 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1429 if (udata->outlen < min_resp_len) 1430 return -EINVAL; 1431 1432 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1433 if (udata->inlen < required_cmd_sz) { 1434 mlx5_ib_dbg(dev, "invalid inlen\n"); 1435 return -EINVAL; 1436 } 1437 1438 if (udata->inlen > sizeof(ucmd) && 1439 !ib_is_udata_cleared(udata, sizeof(ucmd), 1440 udata->inlen - sizeof(ucmd))) { 1441 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1442 return -EOPNOTSUPP; 1443 } 1444 1445 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1446 mlx5_ib_dbg(dev, "copy failed\n"); 1447 return -EFAULT; 1448 } 1449 1450 if (ucmd.comp_mask) { 1451 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1452 return -EOPNOTSUPP; 1453 } 1454 1455 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1456 mlx5_ib_dbg(dev, "invalid flags\n"); 1457 return -EOPNOTSUPP; 1458 } 1459 1460 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1461 !tunnel_offload_supported(dev->mdev)) { 1462 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1463 return -EOPNOTSUPP; 1464 } 1465 1466 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1467 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1468 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1469 return -EOPNOTSUPP; 1470 } 1471 1472 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1473 if (err) { 1474 mlx5_ib_dbg(dev, "copy failed\n"); 1475 return -EINVAL; 1476 } 1477 1478 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1479 in = kvzalloc(inlen, GFP_KERNEL); 1480 if (!in) 1481 return -ENOMEM; 1482 1483 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1484 MLX5_SET(tirc, tirc, disp_type, 1485 MLX5_TIRC_DISP_TYPE_INDIRECT); 1486 MLX5_SET(tirc, tirc, indirect_table, 1487 init_attr->rwq_ind_tbl->ind_tbl_num); 1488 MLX5_SET(tirc, tirc, transport_domain, tdn); 1489 1490 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1491 1492 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1493 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1494 1495 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1496 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1497 else 1498 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1499 1500 switch (ucmd.rx_hash_function) { 1501 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1502 { 1503 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1504 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1505 1506 if (len != ucmd.rx_key_len) { 1507 err = -EINVAL; 1508 goto err; 1509 } 1510 1511 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1512 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1513 memcpy(rss_key, ucmd.rx_hash_key, len); 1514 break; 1515 } 1516 default: 1517 err = -EOPNOTSUPP; 1518 goto err; 1519 } 1520 1521 if (!ucmd.rx_hash_fields_mask) { 1522 /* special case when this TIR serves as steering entry without hashing */ 1523 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1524 goto create_tir; 1525 err = -EINVAL; 1526 goto err; 1527 } 1528 1529 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1530 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1531 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1532 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1533 err = -EINVAL; 1534 goto err; 1535 } 1536 1537 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1538 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1539 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1540 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1541 MLX5_L3_PROT_TYPE_IPV4); 1542 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1544 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1545 MLX5_L3_PROT_TYPE_IPV6); 1546 1547 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1548 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1549 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1550 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1551 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1552 1553 /* Check that only one l4 protocol is set */ 1554 if (outer_l4 & (outer_l4 - 1)) { 1555 err = -EINVAL; 1556 goto err; 1557 } 1558 1559 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1560 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1561 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1562 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1563 MLX5_L4_PROT_TYPE_TCP); 1564 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1565 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1566 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1567 MLX5_L4_PROT_TYPE_UDP); 1568 1569 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1570 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1571 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1572 1573 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1574 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1575 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1576 1577 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1578 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1579 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1580 1581 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1582 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1583 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1584 1585 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1586 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1587 1588 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1589 1590 create_tir: 1591 if (dev->rep) 1592 MLX5_SET(tirc, tirc, self_lb_block, 1593 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1594 1595 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1596 1597 if (err) 1598 goto err; 1599 1600 kvfree(in); 1601 /* qpn is reserved for that QP */ 1602 qp->trans_qp.base.mqp.qpn = 0; 1603 qp->flags |= MLX5_IB_QP_RSS; 1604 return 0; 1605 1606 err: 1607 kvfree(in); 1608 return err; 1609 } 1610 1611 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1612 struct ib_qp_init_attr *init_attr, 1613 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1614 { 1615 struct mlx5_ib_resources *devr = &dev->devr; 1616 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1617 struct mlx5_core_dev *mdev = dev->mdev; 1618 struct mlx5_ib_create_qp_resp resp; 1619 struct mlx5_ib_cq *send_cq; 1620 struct mlx5_ib_cq *recv_cq; 1621 unsigned long flags; 1622 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1623 struct mlx5_ib_create_qp ucmd; 1624 struct mlx5_ib_qp_base *base; 1625 int mlx5_st; 1626 void *qpc; 1627 u32 *in; 1628 int err; 1629 1630 mutex_init(&qp->mutex); 1631 spin_lock_init(&qp->sq.lock); 1632 spin_lock_init(&qp->rq.lock); 1633 1634 mlx5_st = to_mlx5_st(init_attr->qp_type); 1635 if (mlx5_st < 0) 1636 return -EINVAL; 1637 1638 if (init_attr->rwq_ind_tbl) { 1639 if (!udata) 1640 return -ENOSYS; 1641 1642 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1643 return err; 1644 } 1645 1646 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1647 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1648 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1649 return -EINVAL; 1650 } else { 1651 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1652 } 1653 } 1654 1655 if (init_attr->create_flags & 1656 (IB_QP_CREATE_CROSS_CHANNEL | 1657 IB_QP_CREATE_MANAGED_SEND | 1658 IB_QP_CREATE_MANAGED_RECV)) { 1659 if (!MLX5_CAP_GEN(mdev, cd)) { 1660 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1661 return -EINVAL; 1662 } 1663 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1664 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1665 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1666 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1667 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1668 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1669 } 1670 1671 if (init_attr->qp_type == IB_QPT_UD && 1672 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1673 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1674 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1675 return -EOPNOTSUPP; 1676 } 1677 1678 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1679 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1680 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1681 return -EOPNOTSUPP; 1682 } 1683 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1684 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1685 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1686 return -EOPNOTSUPP; 1687 } 1688 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1689 } 1690 1691 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1692 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1693 1694 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1695 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1696 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1697 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1698 return -EOPNOTSUPP; 1699 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1700 } 1701 1702 if (pd && pd->uobject) { 1703 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1704 mlx5_ib_dbg(dev, "copy failed\n"); 1705 return -EFAULT; 1706 } 1707 1708 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1709 &ucmd, udata->inlen, &uidx); 1710 if (err) 1711 return err; 1712 1713 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1714 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1715 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1716 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1717 !tunnel_offload_supported(mdev)) { 1718 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1719 return -EOPNOTSUPP; 1720 } 1721 qp->tunnel_offload_en = true; 1722 } 1723 1724 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1725 if (init_attr->qp_type != IB_QPT_UD || 1726 (MLX5_CAP_GEN(dev->mdev, port_type) != 1727 MLX5_CAP_PORT_TYPE_IB) || 1728 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1729 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1730 return -EOPNOTSUPP; 1731 } 1732 1733 qp->flags |= MLX5_IB_QP_UNDERLAY; 1734 qp->underlay_qpn = init_attr->source_qpn; 1735 } 1736 } else { 1737 qp->wq_sig = !!wq_signature; 1738 } 1739 1740 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1741 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1742 &qp->raw_packet_qp.rq.base : 1743 &qp->trans_qp.base; 1744 1745 qp->has_rq = qp_has_rq(init_attr); 1746 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1747 qp, (pd && pd->uobject) ? &ucmd : NULL); 1748 if (err) { 1749 mlx5_ib_dbg(dev, "err %d\n", err); 1750 return err; 1751 } 1752 1753 if (pd) { 1754 if (pd->uobject) { 1755 __u32 max_wqes = 1756 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1757 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1758 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1759 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1760 mlx5_ib_dbg(dev, "invalid rq params\n"); 1761 return -EINVAL; 1762 } 1763 if (ucmd.sq_wqe_count > max_wqes) { 1764 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1765 ucmd.sq_wqe_count, max_wqes); 1766 return -EINVAL; 1767 } 1768 if (init_attr->create_flags & 1769 mlx5_ib_create_qp_sqpn_qp1()) { 1770 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1771 return -EINVAL; 1772 } 1773 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1774 &resp, &inlen, base); 1775 if (err) 1776 mlx5_ib_dbg(dev, "err %d\n", err); 1777 } else { 1778 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1779 base); 1780 if (err) 1781 mlx5_ib_dbg(dev, "err %d\n", err); 1782 } 1783 1784 if (err) 1785 return err; 1786 } else { 1787 in = kvzalloc(inlen, GFP_KERNEL); 1788 if (!in) 1789 return -ENOMEM; 1790 1791 qp->create_type = MLX5_QP_EMPTY; 1792 } 1793 1794 if (is_sqp(init_attr->qp_type)) 1795 qp->port = init_attr->port_num; 1796 1797 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1798 1799 MLX5_SET(qpc, qpc, st, mlx5_st); 1800 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1801 1802 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1803 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1804 else 1805 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1806 1807 1808 if (qp->wq_sig) 1809 MLX5_SET(qpc, qpc, wq_signature, 1); 1810 1811 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1812 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1813 1814 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1815 MLX5_SET(qpc, qpc, cd_master, 1); 1816 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1817 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1818 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1819 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1820 1821 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1822 int rcqe_sz; 1823 int scqe_sz; 1824 1825 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1826 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1827 1828 if (rcqe_sz == 128) 1829 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1830 else 1831 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1832 1833 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1834 if (scqe_sz == 128) 1835 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1836 else 1837 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1838 } 1839 } 1840 1841 if (qp->rq.wqe_cnt) { 1842 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1843 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1844 } 1845 1846 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1847 1848 if (qp->sq.wqe_cnt) { 1849 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1850 } else { 1851 MLX5_SET(qpc, qpc, no_sq, 1); 1852 if (init_attr->srq && 1853 init_attr->srq->srq_type == IB_SRQT_TM) 1854 MLX5_SET(qpc, qpc, offload_type, 1855 MLX5_QPC_OFFLOAD_TYPE_RNDV); 1856 } 1857 1858 /* Set default resources */ 1859 switch (init_attr->qp_type) { 1860 case IB_QPT_XRC_TGT: 1861 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1862 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1863 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1864 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1865 break; 1866 case IB_QPT_XRC_INI: 1867 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1868 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1869 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1870 break; 1871 default: 1872 if (init_attr->srq) { 1873 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1874 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1875 } else { 1876 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1877 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1878 } 1879 } 1880 1881 if (init_attr->send_cq) 1882 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1883 1884 if (init_attr->recv_cq) 1885 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1886 1887 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1888 1889 /* 0xffffff means we ask to work with cqe version 0 */ 1890 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1891 MLX5_SET(qpc, qpc, user_index, uidx); 1892 1893 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1894 if (init_attr->qp_type == IB_QPT_UD && 1895 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1896 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1897 qp->flags |= MLX5_IB_QP_LSO; 1898 } 1899 1900 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1901 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 1902 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 1903 err = -EOPNOTSUPP; 1904 goto err; 1905 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1906 MLX5_SET(qpc, qpc, end_padding_mode, 1907 MLX5_WQ_END_PAD_MODE_ALIGN); 1908 } else { 1909 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 1910 } 1911 } 1912 1913 if (inlen < 0) { 1914 err = -EINVAL; 1915 goto err; 1916 } 1917 1918 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1919 qp->flags & MLX5_IB_QP_UNDERLAY) { 1920 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1921 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1922 err = create_raw_packet_qp(dev, qp, in, inlen, pd); 1923 } else { 1924 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1925 } 1926 1927 if (err) { 1928 mlx5_ib_dbg(dev, "create qp failed\n"); 1929 goto err_create; 1930 } 1931 1932 kvfree(in); 1933 1934 base->container_mibqp = qp; 1935 base->mqp.event = mlx5_ib_qp_event; 1936 1937 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1938 &send_cq, &recv_cq); 1939 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1940 mlx5_ib_lock_cqs(send_cq, recv_cq); 1941 /* Maintain device to QPs access, needed for further handling via reset 1942 * flow 1943 */ 1944 list_add_tail(&qp->qps_list, &dev->qp_list); 1945 /* Maintain CQ to QPs access, needed for further handling via reset flow 1946 */ 1947 if (send_cq) 1948 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1949 if (recv_cq) 1950 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1951 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1952 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1953 1954 return 0; 1955 1956 err_create: 1957 if (qp->create_type == MLX5_QP_USER) 1958 destroy_qp_user(dev, pd, qp, base); 1959 else if (qp->create_type == MLX5_QP_KERNEL) 1960 destroy_qp_kernel(dev, qp); 1961 1962 err: 1963 kvfree(in); 1964 return err; 1965 } 1966 1967 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1968 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1969 { 1970 if (send_cq) { 1971 if (recv_cq) { 1972 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1973 spin_lock(&send_cq->lock); 1974 spin_lock_nested(&recv_cq->lock, 1975 SINGLE_DEPTH_NESTING); 1976 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1977 spin_lock(&send_cq->lock); 1978 __acquire(&recv_cq->lock); 1979 } else { 1980 spin_lock(&recv_cq->lock); 1981 spin_lock_nested(&send_cq->lock, 1982 SINGLE_DEPTH_NESTING); 1983 } 1984 } else { 1985 spin_lock(&send_cq->lock); 1986 __acquire(&recv_cq->lock); 1987 } 1988 } else if (recv_cq) { 1989 spin_lock(&recv_cq->lock); 1990 __acquire(&send_cq->lock); 1991 } else { 1992 __acquire(&send_cq->lock); 1993 __acquire(&recv_cq->lock); 1994 } 1995 } 1996 1997 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1998 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1999 { 2000 if (send_cq) { 2001 if (recv_cq) { 2002 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2003 spin_unlock(&recv_cq->lock); 2004 spin_unlock(&send_cq->lock); 2005 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2006 __release(&recv_cq->lock); 2007 spin_unlock(&send_cq->lock); 2008 } else { 2009 spin_unlock(&send_cq->lock); 2010 spin_unlock(&recv_cq->lock); 2011 } 2012 } else { 2013 __release(&recv_cq->lock); 2014 spin_unlock(&send_cq->lock); 2015 } 2016 } else if (recv_cq) { 2017 __release(&send_cq->lock); 2018 spin_unlock(&recv_cq->lock); 2019 } else { 2020 __release(&recv_cq->lock); 2021 __release(&send_cq->lock); 2022 } 2023 } 2024 2025 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2026 { 2027 return to_mpd(qp->ibqp.pd); 2028 } 2029 2030 static void get_cqs(enum ib_qp_type qp_type, 2031 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2032 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2033 { 2034 switch (qp_type) { 2035 case IB_QPT_XRC_TGT: 2036 *send_cq = NULL; 2037 *recv_cq = NULL; 2038 break; 2039 case MLX5_IB_QPT_REG_UMR: 2040 case IB_QPT_XRC_INI: 2041 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2042 *recv_cq = NULL; 2043 break; 2044 2045 case IB_QPT_SMI: 2046 case MLX5_IB_QPT_HW_GSI: 2047 case IB_QPT_RC: 2048 case IB_QPT_UC: 2049 case IB_QPT_UD: 2050 case IB_QPT_RAW_IPV6: 2051 case IB_QPT_RAW_ETHERTYPE: 2052 case IB_QPT_RAW_PACKET: 2053 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2054 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2055 break; 2056 2057 case IB_QPT_MAX: 2058 default: 2059 *send_cq = NULL; 2060 *recv_cq = NULL; 2061 break; 2062 } 2063 } 2064 2065 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2066 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2067 u8 lag_tx_affinity); 2068 2069 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2070 { 2071 struct mlx5_ib_cq *send_cq, *recv_cq; 2072 struct mlx5_ib_qp_base *base; 2073 unsigned long flags; 2074 int err; 2075 2076 if (qp->ibqp.rwq_ind_tbl) { 2077 destroy_rss_raw_qp_tir(dev, qp); 2078 return; 2079 } 2080 2081 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2082 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2083 &qp->raw_packet_qp.rq.base : 2084 &qp->trans_qp.base; 2085 2086 if (qp->state != IB_QPS_RESET) { 2087 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2088 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2089 err = mlx5_core_qp_modify(dev->mdev, 2090 MLX5_CMD_OP_2RST_QP, 0, 2091 NULL, &base->mqp); 2092 } else { 2093 struct mlx5_modify_raw_qp_param raw_qp_param = { 2094 .operation = MLX5_CMD_OP_2RST_QP 2095 }; 2096 2097 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2098 } 2099 if (err) 2100 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2101 base->mqp.qpn); 2102 } 2103 2104 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2105 &send_cq, &recv_cq); 2106 2107 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2108 mlx5_ib_lock_cqs(send_cq, recv_cq); 2109 /* del from lists under both locks above to protect reset flow paths */ 2110 list_del(&qp->qps_list); 2111 if (send_cq) 2112 list_del(&qp->cq_send_list); 2113 2114 if (recv_cq) 2115 list_del(&qp->cq_recv_list); 2116 2117 if (qp->create_type == MLX5_QP_KERNEL) { 2118 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2119 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2120 if (send_cq != recv_cq) 2121 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2122 NULL); 2123 } 2124 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2125 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2126 2127 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2128 qp->flags & MLX5_IB_QP_UNDERLAY) { 2129 destroy_raw_packet_qp(dev, qp); 2130 } else { 2131 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2132 if (err) 2133 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2134 base->mqp.qpn); 2135 } 2136 2137 if (qp->create_type == MLX5_QP_KERNEL) 2138 destroy_qp_kernel(dev, qp); 2139 else if (qp->create_type == MLX5_QP_USER) 2140 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2141 } 2142 2143 static const char *ib_qp_type_str(enum ib_qp_type type) 2144 { 2145 switch (type) { 2146 case IB_QPT_SMI: 2147 return "IB_QPT_SMI"; 2148 case IB_QPT_GSI: 2149 return "IB_QPT_GSI"; 2150 case IB_QPT_RC: 2151 return "IB_QPT_RC"; 2152 case IB_QPT_UC: 2153 return "IB_QPT_UC"; 2154 case IB_QPT_UD: 2155 return "IB_QPT_UD"; 2156 case IB_QPT_RAW_IPV6: 2157 return "IB_QPT_RAW_IPV6"; 2158 case IB_QPT_RAW_ETHERTYPE: 2159 return "IB_QPT_RAW_ETHERTYPE"; 2160 case IB_QPT_XRC_INI: 2161 return "IB_QPT_XRC_INI"; 2162 case IB_QPT_XRC_TGT: 2163 return "IB_QPT_XRC_TGT"; 2164 case IB_QPT_RAW_PACKET: 2165 return "IB_QPT_RAW_PACKET"; 2166 case MLX5_IB_QPT_REG_UMR: 2167 return "MLX5_IB_QPT_REG_UMR"; 2168 case IB_QPT_DRIVER: 2169 return "IB_QPT_DRIVER"; 2170 case IB_QPT_MAX: 2171 default: 2172 return "Invalid QP type"; 2173 } 2174 } 2175 2176 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2177 struct ib_qp_init_attr *attr, 2178 struct mlx5_ib_create_qp *ucmd) 2179 { 2180 struct mlx5_ib_qp *qp; 2181 int err = 0; 2182 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2183 void *dctc; 2184 2185 if (!attr->srq || !attr->recv_cq) 2186 return ERR_PTR(-EINVAL); 2187 2188 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2189 ucmd, sizeof(*ucmd), &uidx); 2190 if (err) 2191 return ERR_PTR(err); 2192 2193 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2194 if (!qp) 2195 return ERR_PTR(-ENOMEM); 2196 2197 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2198 if (!qp->dct.in) { 2199 err = -ENOMEM; 2200 goto err_free; 2201 } 2202 2203 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2204 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2205 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2206 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2207 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2208 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2209 MLX5_SET(dctc, dctc, user_index, uidx); 2210 2211 qp->state = IB_QPS_RESET; 2212 2213 return &qp->ibqp; 2214 err_free: 2215 kfree(qp); 2216 return ERR_PTR(err); 2217 } 2218 2219 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2220 struct ib_qp_init_attr *init_attr, 2221 struct mlx5_ib_create_qp *ucmd, 2222 struct ib_udata *udata) 2223 { 2224 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2225 int err; 2226 2227 if (!udata) 2228 return -EINVAL; 2229 2230 if (udata->inlen < sizeof(*ucmd)) { 2231 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2232 return -EINVAL; 2233 } 2234 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2235 if (err) 2236 return err; 2237 2238 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2239 init_attr->qp_type = MLX5_IB_QPT_DCI; 2240 } else { 2241 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2242 init_attr->qp_type = MLX5_IB_QPT_DCT; 2243 } else { 2244 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2245 return -EINVAL; 2246 } 2247 } 2248 2249 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2250 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2251 return -EOPNOTSUPP; 2252 } 2253 2254 return 0; 2255 } 2256 2257 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2258 struct ib_qp_init_attr *verbs_init_attr, 2259 struct ib_udata *udata) 2260 { 2261 struct mlx5_ib_dev *dev; 2262 struct mlx5_ib_qp *qp; 2263 u16 xrcdn = 0; 2264 int err; 2265 struct ib_qp_init_attr mlx_init_attr; 2266 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2267 2268 if (pd) { 2269 dev = to_mdev(pd->device); 2270 2271 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2272 if (!pd->uobject) { 2273 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2274 return ERR_PTR(-EINVAL); 2275 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2276 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2277 return ERR_PTR(-EINVAL); 2278 } 2279 } 2280 } else { 2281 /* being cautious here */ 2282 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2283 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2284 pr_warn("%s: no PD for transport %s\n", __func__, 2285 ib_qp_type_str(init_attr->qp_type)); 2286 return ERR_PTR(-EINVAL); 2287 } 2288 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2289 } 2290 2291 if (init_attr->qp_type == IB_QPT_DRIVER) { 2292 struct mlx5_ib_create_qp ucmd; 2293 2294 init_attr = &mlx_init_attr; 2295 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2296 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2297 if (err) 2298 return ERR_PTR(err); 2299 2300 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2301 if (init_attr->cap.max_recv_wr || 2302 init_attr->cap.max_recv_sge) { 2303 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2304 return ERR_PTR(-EINVAL); 2305 } 2306 } else { 2307 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2308 } 2309 } 2310 2311 switch (init_attr->qp_type) { 2312 case IB_QPT_XRC_TGT: 2313 case IB_QPT_XRC_INI: 2314 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2315 mlx5_ib_dbg(dev, "XRC not supported\n"); 2316 return ERR_PTR(-ENOSYS); 2317 } 2318 init_attr->recv_cq = NULL; 2319 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2320 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2321 init_attr->send_cq = NULL; 2322 } 2323 2324 /* fall through */ 2325 case IB_QPT_RAW_PACKET: 2326 case IB_QPT_RC: 2327 case IB_QPT_UC: 2328 case IB_QPT_UD: 2329 case IB_QPT_SMI: 2330 case MLX5_IB_QPT_HW_GSI: 2331 case MLX5_IB_QPT_REG_UMR: 2332 case MLX5_IB_QPT_DCI: 2333 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2334 if (!qp) 2335 return ERR_PTR(-ENOMEM); 2336 2337 err = create_qp_common(dev, pd, init_attr, udata, qp); 2338 if (err) { 2339 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2340 kfree(qp); 2341 return ERR_PTR(err); 2342 } 2343 2344 if (is_qp0(init_attr->qp_type)) 2345 qp->ibqp.qp_num = 0; 2346 else if (is_qp1(init_attr->qp_type)) 2347 qp->ibqp.qp_num = 1; 2348 else 2349 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2350 2351 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2352 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2353 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2354 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2355 2356 qp->trans_qp.xrcdn = xrcdn; 2357 2358 break; 2359 2360 case IB_QPT_GSI: 2361 return mlx5_ib_gsi_create_qp(pd, init_attr); 2362 2363 case IB_QPT_RAW_IPV6: 2364 case IB_QPT_RAW_ETHERTYPE: 2365 case IB_QPT_MAX: 2366 default: 2367 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2368 init_attr->qp_type); 2369 /* Don't support raw QPs */ 2370 return ERR_PTR(-EINVAL); 2371 } 2372 2373 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2374 qp->qp_sub_type = init_attr->qp_type; 2375 2376 return &qp->ibqp; 2377 } 2378 2379 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2380 { 2381 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2382 2383 if (mqp->state == IB_QPS_RTR) { 2384 int err; 2385 2386 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2387 if (err) { 2388 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2389 return err; 2390 } 2391 } 2392 2393 kfree(mqp->dct.in); 2394 kfree(mqp); 2395 return 0; 2396 } 2397 2398 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2399 { 2400 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2401 struct mlx5_ib_qp *mqp = to_mqp(qp); 2402 2403 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2404 return mlx5_ib_gsi_destroy_qp(qp); 2405 2406 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2407 return mlx5_ib_destroy_dct(mqp); 2408 2409 destroy_qp_common(dev, mqp); 2410 2411 kfree(mqp); 2412 2413 return 0; 2414 } 2415 2416 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2417 int attr_mask) 2418 { 2419 u32 hw_access_flags = 0; 2420 u8 dest_rd_atomic; 2421 u32 access_flags; 2422 2423 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2424 dest_rd_atomic = attr->max_dest_rd_atomic; 2425 else 2426 dest_rd_atomic = qp->trans_qp.resp_depth; 2427 2428 if (attr_mask & IB_QP_ACCESS_FLAGS) 2429 access_flags = attr->qp_access_flags; 2430 else 2431 access_flags = qp->trans_qp.atomic_rd_en; 2432 2433 if (!dest_rd_atomic) 2434 access_flags &= IB_ACCESS_REMOTE_WRITE; 2435 2436 if (access_flags & IB_ACCESS_REMOTE_READ) 2437 hw_access_flags |= MLX5_QP_BIT_RRE; 2438 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2439 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2440 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2441 hw_access_flags |= MLX5_QP_BIT_RWE; 2442 2443 return cpu_to_be32(hw_access_flags); 2444 } 2445 2446 enum { 2447 MLX5_PATH_FLAG_FL = 1 << 0, 2448 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2449 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2450 }; 2451 2452 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2453 { 2454 if (rate == IB_RATE_PORT_CURRENT) { 2455 return 0; 2456 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2457 return -EINVAL; 2458 } else { 2459 while (rate != IB_RATE_2_5_GBPS && 2460 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2461 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2462 --rate; 2463 } 2464 2465 return rate + MLX5_STAT_RATE_OFFSET; 2466 } 2467 2468 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2469 struct mlx5_ib_sq *sq, u8 sl) 2470 { 2471 void *in; 2472 void *tisc; 2473 int inlen; 2474 int err; 2475 2476 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2477 in = kvzalloc(inlen, GFP_KERNEL); 2478 if (!in) 2479 return -ENOMEM; 2480 2481 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2482 2483 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2484 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2485 2486 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2487 2488 kvfree(in); 2489 2490 return err; 2491 } 2492 2493 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2494 struct mlx5_ib_sq *sq, u8 tx_affinity) 2495 { 2496 void *in; 2497 void *tisc; 2498 int inlen; 2499 int err; 2500 2501 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2502 in = kvzalloc(inlen, GFP_KERNEL); 2503 if (!in) 2504 return -ENOMEM; 2505 2506 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2507 2508 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2509 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2510 2511 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2512 2513 kvfree(in); 2514 2515 return err; 2516 } 2517 2518 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2519 const struct rdma_ah_attr *ah, 2520 struct mlx5_qp_path *path, u8 port, int attr_mask, 2521 u32 path_flags, const struct ib_qp_attr *attr, 2522 bool alt) 2523 { 2524 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2525 int err; 2526 enum ib_gid_type gid_type; 2527 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2528 u8 sl = rdma_ah_get_sl(ah); 2529 2530 if (attr_mask & IB_QP_PKEY_INDEX) 2531 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2532 attr->pkey_index); 2533 2534 if (ah_flags & IB_AH_GRH) { 2535 if (grh->sgid_index >= 2536 dev->mdev->port_caps[port - 1].gid_table_len) { 2537 pr_err("sgid_index (%u) too large. max is %d\n", 2538 grh->sgid_index, 2539 dev->mdev->port_caps[port - 1].gid_table_len); 2540 return -EINVAL; 2541 } 2542 } 2543 2544 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2545 if (!(ah_flags & IB_AH_GRH)) 2546 return -EINVAL; 2547 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2548 &gid_type); 2549 if (err) 2550 return err; 2551 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2552 if (qp->ibqp.qp_type == IB_QPT_RC || 2553 qp->ibqp.qp_type == IB_QPT_UC || 2554 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2555 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2556 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2557 grh->sgid_index); 2558 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2559 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2560 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2561 } else { 2562 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2563 path->fl_free_ar |= 2564 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2565 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2566 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2567 if (ah_flags & IB_AH_GRH) 2568 path->grh_mlid |= 1 << 7; 2569 path->dci_cfi_prio_sl = sl & 0xf; 2570 } 2571 2572 if (ah_flags & IB_AH_GRH) { 2573 path->mgid_index = grh->sgid_index; 2574 path->hop_limit = grh->hop_limit; 2575 path->tclass_flowlabel = 2576 cpu_to_be32((grh->traffic_class << 20) | 2577 (grh->flow_label)); 2578 memcpy(path->rgid, grh->dgid.raw, 16); 2579 } 2580 2581 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2582 if (err < 0) 2583 return err; 2584 path->static_rate = err; 2585 path->port = port; 2586 2587 if (attr_mask & IB_QP_TIMEOUT) 2588 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2589 2590 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2591 return modify_raw_packet_eth_prio(dev->mdev, 2592 &qp->raw_packet_qp.sq, 2593 sl & 0xf); 2594 2595 return 0; 2596 } 2597 2598 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2599 [MLX5_QP_STATE_INIT] = { 2600 [MLX5_QP_STATE_INIT] = { 2601 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2602 MLX5_QP_OPTPAR_RAE | 2603 MLX5_QP_OPTPAR_RWE | 2604 MLX5_QP_OPTPAR_PKEY_INDEX | 2605 MLX5_QP_OPTPAR_PRI_PORT, 2606 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2607 MLX5_QP_OPTPAR_PKEY_INDEX | 2608 MLX5_QP_OPTPAR_PRI_PORT, 2609 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2610 MLX5_QP_OPTPAR_Q_KEY | 2611 MLX5_QP_OPTPAR_PRI_PORT, 2612 }, 2613 [MLX5_QP_STATE_RTR] = { 2614 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2615 MLX5_QP_OPTPAR_RRE | 2616 MLX5_QP_OPTPAR_RAE | 2617 MLX5_QP_OPTPAR_RWE | 2618 MLX5_QP_OPTPAR_PKEY_INDEX, 2619 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2620 MLX5_QP_OPTPAR_RWE | 2621 MLX5_QP_OPTPAR_PKEY_INDEX, 2622 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2623 MLX5_QP_OPTPAR_Q_KEY, 2624 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2625 MLX5_QP_OPTPAR_Q_KEY, 2626 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2627 MLX5_QP_OPTPAR_RRE | 2628 MLX5_QP_OPTPAR_RAE | 2629 MLX5_QP_OPTPAR_RWE | 2630 MLX5_QP_OPTPAR_PKEY_INDEX, 2631 }, 2632 }, 2633 [MLX5_QP_STATE_RTR] = { 2634 [MLX5_QP_STATE_RTS] = { 2635 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2636 MLX5_QP_OPTPAR_RRE | 2637 MLX5_QP_OPTPAR_RAE | 2638 MLX5_QP_OPTPAR_RWE | 2639 MLX5_QP_OPTPAR_PM_STATE | 2640 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2641 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2642 MLX5_QP_OPTPAR_RWE | 2643 MLX5_QP_OPTPAR_PM_STATE, 2644 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2645 }, 2646 }, 2647 [MLX5_QP_STATE_RTS] = { 2648 [MLX5_QP_STATE_RTS] = { 2649 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2650 MLX5_QP_OPTPAR_RAE | 2651 MLX5_QP_OPTPAR_RWE | 2652 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2653 MLX5_QP_OPTPAR_PM_STATE | 2654 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2655 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2656 MLX5_QP_OPTPAR_PM_STATE | 2657 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2658 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2659 MLX5_QP_OPTPAR_SRQN | 2660 MLX5_QP_OPTPAR_CQN_RCV, 2661 }, 2662 }, 2663 [MLX5_QP_STATE_SQER] = { 2664 [MLX5_QP_STATE_RTS] = { 2665 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2666 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2667 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2668 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2669 MLX5_QP_OPTPAR_RWE | 2670 MLX5_QP_OPTPAR_RAE | 2671 MLX5_QP_OPTPAR_RRE, 2672 }, 2673 }, 2674 }; 2675 2676 static int ib_nr_to_mlx5_nr(int ib_mask) 2677 { 2678 switch (ib_mask) { 2679 case IB_QP_STATE: 2680 return 0; 2681 case IB_QP_CUR_STATE: 2682 return 0; 2683 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2684 return 0; 2685 case IB_QP_ACCESS_FLAGS: 2686 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2687 MLX5_QP_OPTPAR_RAE; 2688 case IB_QP_PKEY_INDEX: 2689 return MLX5_QP_OPTPAR_PKEY_INDEX; 2690 case IB_QP_PORT: 2691 return MLX5_QP_OPTPAR_PRI_PORT; 2692 case IB_QP_QKEY: 2693 return MLX5_QP_OPTPAR_Q_KEY; 2694 case IB_QP_AV: 2695 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2696 MLX5_QP_OPTPAR_PRI_PORT; 2697 case IB_QP_PATH_MTU: 2698 return 0; 2699 case IB_QP_TIMEOUT: 2700 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2701 case IB_QP_RETRY_CNT: 2702 return MLX5_QP_OPTPAR_RETRY_COUNT; 2703 case IB_QP_RNR_RETRY: 2704 return MLX5_QP_OPTPAR_RNR_RETRY; 2705 case IB_QP_RQ_PSN: 2706 return 0; 2707 case IB_QP_MAX_QP_RD_ATOMIC: 2708 return MLX5_QP_OPTPAR_SRA_MAX; 2709 case IB_QP_ALT_PATH: 2710 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2711 case IB_QP_MIN_RNR_TIMER: 2712 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2713 case IB_QP_SQ_PSN: 2714 return 0; 2715 case IB_QP_MAX_DEST_RD_ATOMIC: 2716 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2717 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2718 case IB_QP_PATH_MIG_STATE: 2719 return MLX5_QP_OPTPAR_PM_STATE; 2720 case IB_QP_CAP: 2721 return 0; 2722 case IB_QP_DEST_QPN: 2723 return 0; 2724 } 2725 return 0; 2726 } 2727 2728 static int ib_mask_to_mlx5_opt(int ib_mask) 2729 { 2730 int result = 0; 2731 int i; 2732 2733 for (i = 0; i < 8 * sizeof(int); i++) { 2734 if ((1 << i) & ib_mask) 2735 result |= ib_nr_to_mlx5_nr(1 << i); 2736 } 2737 2738 return result; 2739 } 2740 2741 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2742 struct mlx5_ib_rq *rq, int new_state, 2743 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2744 { 2745 void *in; 2746 void *rqc; 2747 int inlen; 2748 int err; 2749 2750 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2751 in = kvzalloc(inlen, GFP_KERNEL); 2752 if (!in) 2753 return -ENOMEM; 2754 2755 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2756 2757 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2758 MLX5_SET(rqc, rqc, state, new_state); 2759 2760 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2761 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2762 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2763 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2764 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2765 } else 2766 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2767 dev->ib_dev.name); 2768 } 2769 2770 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2771 if (err) 2772 goto out; 2773 2774 rq->state = new_state; 2775 2776 out: 2777 kvfree(in); 2778 return err; 2779 } 2780 2781 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2782 struct mlx5_ib_sq *sq, 2783 int new_state, 2784 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2785 { 2786 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2787 struct mlx5_rate_limit old_rl = ibqp->rl; 2788 struct mlx5_rate_limit new_rl = old_rl; 2789 bool new_rate_added = false; 2790 u16 rl_index = 0; 2791 void *in; 2792 void *sqc; 2793 int inlen; 2794 int err; 2795 2796 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2797 in = kvzalloc(inlen, GFP_KERNEL); 2798 if (!in) 2799 return -ENOMEM; 2800 2801 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2802 2803 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2804 MLX5_SET(sqc, sqc, state, new_state); 2805 2806 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2807 if (new_state != MLX5_SQC_STATE_RDY) 2808 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2809 __func__); 2810 else 2811 new_rl = raw_qp_param->rl; 2812 } 2813 2814 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 2815 if (new_rl.rate) { 2816 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 2817 if (err) { 2818 pr_err("Failed configuring rate limit(err %d): \ 2819 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 2820 err, new_rl.rate, new_rl.max_burst_sz, 2821 new_rl.typical_pkt_sz); 2822 2823 goto out; 2824 } 2825 new_rate_added = true; 2826 } 2827 2828 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2829 /* index 0 means no limit */ 2830 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2831 } 2832 2833 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2834 if (err) { 2835 /* Remove new rate from table if failed */ 2836 if (new_rate_added) 2837 mlx5_rl_remove_rate(dev, &new_rl); 2838 goto out; 2839 } 2840 2841 /* Only remove the old rate after new rate was set */ 2842 if ((old_rl.rate && 2843 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 2844 (new_state != MLX5_SQC_STATE_RDY)) 2845 mlx5_rl_remove_rate(dev, &old_rl); 2846 2847 ibqp->rl = new_rl; 2848 sq->state = new_state; 2849 2850 out: 2851 kvfree(in); 2852 return err; 2853 } 2854 2855 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2856 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2857 u8 tx_affinity) 2858 { 2859 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2860 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2861 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2862 int modify_rq = !!qp->rq.wqe_cnt; 2863 int modify_sq = !!qp->sq.wqe_cnt; 2864 int rq_state; 2865 int sq_state; 2866 int err; 2867 2868 switch (raw_qp_param->operation) { 2869 case MLX5_CMD_OP_RST2INIT_QP: 2870 rq_state = MLX5_RQC_STATE_RDY; 2871 sq_state = MLX5_SQC_STATE_RDY; 2872 break; 2873 case MLX5_CMD_OP_2ERR_QP: 2874 rq_state = MLX5_RQC_STATE_ERR; 2875 sq_state = MLX5_SQC_STATE_ERR; 2876 break; 2877 case MLX5_CMD_OP_2RST_QP: 2878 rq_state = MLX5_RQC_STATE_RST; 2879 sq_state = MLX5_SQC_STATE_RST; 2880 break; 2881 case MLX5_CMD_OP_RTR2RTS_QP: 2882 case MLX5_CMD_OP_RTS2RTS_QP: 2883 if (raw_qp_param->set_mask == 2884 MLX5_RAW_QP_RATE_LIMIT) { 2885 modify_rq = 0; 2886 sq_state = sq->state; 2887 } else { 2888 return raw_qp_param->set_mask ? -EINVAL : 0; 2889 } 2890 break; 2891 case MLX5_CMD_OP_INIT2INIT_QP: 2892 case MLX5_CMD_OP_INIT2RTR_QP: 2893 if (raw_qp_param->set_mask) 2894 return -EINVAL; 2895 else 2896 return 0; 2897 default: 2898 WARN_ON(1); 2899 return -EINVAL; 2900 } 2901 2902 if (modify_rq) { 2903 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2904 if (err) 2905 return err; 2906 } 2907 2908 if (modify_sq) { 2909 if (tx_affinity) { 2910 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2911 tx_affinity); 2912 if (err) 2913 return err; 2914 } 2915 2916 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2917 } 2918 2919 return 0; 2920 } 2921 2922 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2923 const struct ib_qp_attr *attr, int attr_mask, 2924 enum ib_qp_state cur_state, enum ib_qp_state new_state, 2925 const struct mlx5_ib_modify_qp *ucmd) 2926 { 2927 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2928 [MLX5_QP_STATE_RST] = { 2929 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2930 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2931 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2932 }, 2933 [MLX5_QP_STATE_INIT] = { 2934 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2935 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2936 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2937 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2938 }, 2939 [MLX5_QP_STATE_RTR] = { 2940 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2941 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2942 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2943 }, 2944 [MLX5_QP_STATE_RTS] = { 2945 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2946 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2947 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2948 }, 2949 [MLX5_QP_STATE_SQD] = { 2950 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2951 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2952 }, 2953 [MLX5_QP_STATE_SQER] = { 2954 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2955 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2956 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2957 }, 2958 [MLX5_QP_STATE_ERR] = { 2959 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2960 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2961 } 2962 }; 2963 2964 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2965 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2966 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2967 struct mlx5_ib_cq *send_cq, *recv_cq; 2968 struct mlx5_qp_context *context; 2969 struct mlx5_ib_pd *pd; 2970 struct mlx5_ib_port *mibport = NULL; 2971 enum mlx5_qp_state mlx5_cur, mlx5_new; 2972 enum mlx5_qp_optpar optpar; 2973 int mlx5_st; 2974 int err; 2975 u16 op; 2976 u8 tx_affinity = 0; 2977 2978 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 2979 qp->qp_sub_type : ibqp->qp_type); 2980 if (mlx5_st < 0) 2981 return -EINVAL; 2982 2983 context = kzalloc(sizeof(*context), GFP_KERNEL); 2984 if (!context) 2985 return -ENOMEM; 2986 2987 context->flags = cpu_to_be32(mlx5_st << 16); 2988 2989 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2990 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2991 } else { 2992 switch (attr->path_mig_state) { 2993 case IB_MIG_MIGRATED: 2994 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2995 break; 2996 case IB_MIG_REARM: 2997 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2998 break; 2999 case IB_MIG_ARMED: 3000 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3001 break; 3002 } 3003 } 3004 3005 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3006 if ((ibqp->qp_type == IB_QPT_RC) || 3007 (ibqp->qp_type == IB_QPT_UD && 3008 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3009 (ibqp->qp_type == IB_QPT_UC) || 3010 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3011 (ibqp->qp_type == IB_QPT_XRC_INI) || 3012 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3013 if (mlx5_lag_is_active(dev->mdev)) { 3014 u8 p = mlx5_core_native_port_num(dev->mdev); 3015 tx_affinity = (unsigned int)atomic_add_return(1, 3016 &dev->roce[p].next_port) % 3017 MLX5_MAX_PORTS + 1; 3018 context->flags |= cpu_to_be32(tx_affinity << 24); 3019 } 3020 } 3021 } 3022 3023 if (is_sqp(ibqp->qp_type)) { 3024 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3025 } else if ((ibqp->qp_type == IB_QPT_UD && 3026 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3027 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3028 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3029 } else if (attr_mask & IB_QP_PATH_MTU) { 3030 if (attr->path_mtu < IB_MTU_256 || 3031 attr->path_mtu > IB_MTU_4096) { 3032 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3033 err = -EINVAL; 3034 goto out; 3035 } 3036 context->mtu_msgmax = (attr->path_mtu << 5) | 3037 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3038 } 3039 3040 if (attr_mask & IB_QP_DEST_QPN) 3041 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3042 3043 if (attr_mask & IB_QP_PKEY_INDEX) 3044 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3045 3046 /* todo implement counter_index functionality */ 3047 3048 if (is_sqp(ibqp->qp_type)) 3049 context->pri_path.port = qp->port; 3050 3051 if (attr_mask & IB_QP_PORT) 3052 context->pri_path.port = attr->port_num; 3053 3054 if (attr_mask & IB_QP_AV) { 3055 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3056 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3057 attr_mask, 0, attr, false); 3058 if (err) 3059 goto out; 3060 } 3061 3062 if (attr_mask & IB_QP_TIMEOUT) 3063 context->pri_path.ackto_lt |= attr->timeout << 3; 3064 3065 if (attr_mask & IB_QP_ALT_PATH) { 3066 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3067 &context->alt_path, 3068 attr->alt_port_num, 3069 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3070 0, attr, true); 3071 if (err) 3072 goto out; 3073 } 3074 3075 pd = get_pd(qp); 3076 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3077 &send_cq, &recv_cq); 3078 3079 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3080 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3081 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3082 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3083 3084 if (attr_mask & IB_QP_RNR_RETRY) 3085 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3086 3087 if (attr_mask & IB_QP_RETRY_CNT) 3088 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3089 3090 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3091 if (attr->max_rd_atomic) 3092 context->params1 |= 3093 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3094 } 3095 3096 if (attr_mask & IB_QP_SQ_PSN) 3097 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3098 3099 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3100 if (attr->max_dest_rd_atomic) 3101 context->params2 |= 3102 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3103 } 3104 3105 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3106 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 3107 3108 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3109 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3110 3111 if (attr_mask & IB_QP_RQ_PSN) 3112 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3113 3114 if (attr_mask & IB_QP_QKEY) 3115 context->qkey = cpu_to_be32(attr->qkey); 3116 3117 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3118 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3119 3120 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3121 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3122 qp->port) - 1; 3123 3124 /* Underlay port should be used - index 0 function per port */ 3125 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3126 port_num = 0; 3127 3128 mibport = &dev->port[port_num]; 3129 context->qp_counter_set_usr_page |= 3130 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3131 } 3132 3133 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3134 context->sq_crq_size |= cpu_to_be16(1 << 4); 3135 3136 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3137 context->deth_sqpn = cpu_to_be32(1); 3138 3139 mlx5_cur = to_mlx5_state(cur_state); 3140 mlx5_new = to_mlx5_state(new_state); 3141 3142 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3143 !optab[mlx5_cur][mlx5_new]) { 3144 err = -EINVAL; 3145 goto out; 3146 } 3147 3148 op = optab[mlx5_cur][mlx5_new]; 3149 optpar = ib_mask_to_mlx5_opt(attr_mask); 3150 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3151 3152 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3153 qp->flags & MLX5_IB_QP_UNDERLAY) { 3154 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3155 3156 raw_qp_param.operation = op; 3157 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3158 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3159 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3160 } 3161 3162 if (attr_mask & IB_QP_RATE_LIMIT) { 3163 raw_qp_param.rl.rate = attr->rate_limit; 3164 3165 if (ucmd->burst_info.max_burst_sz) { 3166 if (attr->rate_limit && 3167 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3168 raw_qp_param.rl.max_burst_sz = 3169 ucmd->burst_info.max_burst_sz; 3170 } else { 3171 err = -EINVAL; 3172 goto out; 3173 } 3174 } 3175 3176 if (ucmd->burst_info.typical_pkt_sz) { 3177 if (attr->rate_limit && 3178 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3179 raw_qp_param.rl.typical_pkt_sz = 3180 ucmd->burst_info.typical_pkt_sz; 3181 } else { 3182 err = -EINVAL; 3183 goto out; 3184 } 3185 } 3186 3187 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3188 } 3189 3190 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3191 } else { 3192 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3193 &base->mqp); 3194 } 3195 3196 if (err) 3197 goto out; 3198 3199 qp->state = new_state; 3200 3201 if (attr_mask & IB_QP_ACCESS_FLAGS) 3202 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3203 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3204 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3205 if (attr_mask & IB_QP_PORT) 3206 qp->port = attr->port_num; 3207 if (attr_mask & IB_QP_ALT_PATH) 3208 qp->trans_qp.alt_port = attr->alt_port_num; 3209 3210 /* 3211 * If we moved a kernel QP to RESET, clean up all old CQ 3212 * entries and reinitialize the QP. 3213 */ 3214 if (new_state == IB_QPS_RESET && 3215 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3216 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3217 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3218 if (send_cq != recv_cq) 3219 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3220 3221 qp->rq.head = 0; 3222 qp->rq.tail = 0; 3223 qp->sq.head = 0; 3224 qp->sq.tail = 0; 3225 qp->sq.cur_post = 0; 3226 qp->sq.last_poll = 0; 3227 qp->db.db[MLX5_RCV_DBR] = 0; 3228 qp->db.db[MLX5_SND_DBR] = 0; 3229 } 3230 3231 out: 3232 kfree(context); 3233 return err; 3234 } 3235 3236 static inline bool is_valid_mask(int mask, int req, int opt) 3237 { 3238 if ((mask & req) != req) 3239 return false; 3240 3241 if (mask & ~(req | opt)) 3242 return false; 3243 3244 return true; 3245 } 3246 3247 /* check valid transition for driver QP types 3248 * for now the only QP type that this function supports is DCI 3249 */ 3250 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3251 enum ib_qp_attr_mask attr_mask) 3252 { 3253 int req = IB_QP_STATE; 3254 int opt = 0; 3255 3256 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3257 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3258 return is_valid_mask(attr_mask, req, opt); 3259 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3260 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3261 return is_valid_mask(attr_mask, req, opt); 3262 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3263 req |= IB_QP_PATH_MTU; 3264 opt = IB_QP_PKEY_INDEX; 3265 return is_valid_mask(attr_mask, req, opt); 3266 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3267 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3268 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3269 opt = IB_QP_MIN_RNR_TIMER; 3270 return is_valid_mask(attr_mask, req, opt); 3271 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3272 opt = IB_QP_MIN_RNR_TIMER; 3273 return is_valid_mask(attr_mask, req, opt); 3274 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3275 return is_valid_mask(attr_mask, req, opt); 3276 } 3277 return false; 3278 } 3279 3280 /* mlx5_ib_modify_dct: modify a DCT QP 3281 * valid transitions are: 3282 * RESET to INIT: must set access_flags, pkey_index and port 3283 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3284 * mtu, gid_index and hop_limit 3285 * Other transitions and attributes are illegal 3286 */ 3287 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3288 int attr_mask, struct ib_udata *udata) 3289 { 3290 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3291 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3292 enum ib_qp_state cur_state, new_state; 3293 int err = 0; 3294 int required = IB_QP_STATE; 3295 void *dctc; 3296 3297 if (!(attr_mask & IB_QP_STATE)) 3298 return -EINVAL; 3299 3300 cur_state = qp->state; 3301 new_state = attr->qp_state; 3302 3303 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3304 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3305 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3306 if (!is_valid_mask(attr_mask, required, 0)) 3307 return -EINVAL; 3308 3309 if (attr->port_num == 0 || 3310 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3311 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3312 attr->port_num, dev->num_ports); 3313 return -EINVAL; 3314 } 3315 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3316 MLX5_SET(dctc, dctc, rre, 1); 3317 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3318 MLX5_SET(dctc, dctc, rwe, 1); 3319 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3320 if (!mlx5_ib_dc_atomic_is_supported(dev)) 3321 return -EOPNOTSUPP; 3322 MLX5_SET(dctc, dctc, rae, 1); 3323 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX); 3324 } 3325 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3326 MLX5_SET(dctc, dctc, port, attr->port_num); 3327 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3328 3329 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3330 struct mlx5_ib_modify_qp_resp resp = {}; 3331 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3332 sizeof(resp.dctn); 3333 3334 if (udata->outlen < min_resp_len) 3335 return -EINVAL; 3336 resp.response_length = min_resp_len; 3337 3338 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3339 if (!is_valid_mask(attr_mask, required, 0)) 3340 return -EINVAL; 3341 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3342 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3343 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3344 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3345 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3346 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3347 3348 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3349 MLX5_ST_SZ_BYTES(create_dct_in)); 3350 if (err) 3351 return err; 3352 resp.dctn = qp->dct.mdct.mqp.qpn; 3353 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3354 if (err) { 3355 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3356 return err; 3357 } 3358 } else { 3359 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3360 return -EINVAL; 3361 } 3362 if (err) 3363 qp->state = IB_QPS_ERR; 3364 else 3365 qp->state = new_state; 3366 return err; 3367 } 3368 3369 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3370 int attr_mask, struct ib_udata *udata) 3371 { 3372 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3373 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3374 struct mlx5_ib_modify_qp ucmd = {}; 3375 enum ib_qp_type qp_type; 3376 enum ib_qp_state cur_state, new_state; 3377 size_t required_cmd_sz; 3378 int err = -EINVAL; 3379 int port; 3380 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 3381 3382 if (ibqp->rwq_ind_tbl) 3383 return -ENOSYS; 3384 3385 if (udata && udata->inlen) { 3386 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3387 sizeof(ucmd.reserved); 3388 if (udata->inlen < required_cmd_sz) 3389 return -EINVAL; 3390 3391 if (udata->inlen > sizeof(ucmd) && 3392 !ib_is_udata_cleared(udata, sizeof(ucmd), 3393 udata->inlen - sizeof(ucmd))) 3394 return -EOPNOTSUPP; 3395 3396 if (ib_copy_from_udata(&ucmd, udata, 3397 min(udata->inlen, sizeof(ucmd)))) 3398 return -EFAULT; 3399 3400 if (ucmd.comp_mask || 3401 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3402 memchr_inv(&ucmd.burst_info.reserved, 0, 3403 sizeof(ucmd.burst_info.reserved))) 3404 return -EOPNOTSUPP; 3405 } 3406 3407 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3408 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3409 3410 if (ibqp->qp_type == IB_QPT_DRIVER) 3411 qp_type = qp->qp_sub_type; 3412 else 3413 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3414 IB_QPT_GSI : ibqp->qp_type; 3415 3416 if (qp_type == MLX5_IB_QPT_DCT) 3417 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3418 3419 mutex_lock(&qp->mutex); 3420 3421 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3422 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3423 3424 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3425 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3426 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 3427 } 3428 3429 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3430 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3431 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3432 attr_mask); 3433 goto out; 3434 } 3435 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3436 qp_type != MLX5_IB_QPT_DCI && 3437 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 3438 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3439 cur_state, new_state, ibqp->qp_type, attr_mask); 3440 goto out; 3441 } else if (qp_type == MLX5_IB_QPT_DCI && 3442 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3443 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3444 cur_state, new_state, qp_type, attr_mask); 3445 goto out; 3446 } 3447 3448 if ((attr_mask & IB_QP_PORT) && 3449 (attr->port_num == 0 || 3450 attr->port_num > dev->num_ports)) { 3451 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3452 attr->port_num, dev->num_ports); 3453 goto out; 3454 } 3455 3456 if (attr_mask & IB_QP_PKEY_INDEX) { 3457 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3458 if (attr->pkey_index >= 3459 dev->mdev->port_caps[port - 1].pkey_table_len) { 3460 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3461 attr->pkey_index); 3462 goto out; 3463 } 3464 } 3465 3466 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3467 attr->max_rd_atomic > 3468 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3469 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3470 attr->max_rd_atomic); 3471 goto out; 3472 } 3473 3474 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3475 attr->max_dest_rd_atomic > 3476 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3477 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3478 attr->max_dest_rd_atomic); 3479 goto out; 3480 } 3481 3482 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3483 err = 0; 3484 goto out; 3485 } 3486 3487 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3488 new_state, &ucmd); 3489 3490 out: 3491 mutex_unlock(&qp->mutex); 3492 return err; 3493 } 3494 3495 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3496 { 3497 struct mlx5_ib_cq *cq; 3498 unsigned cur; 3499 3500 cur = wq->head - wq->tail; 3501 if (likely(cur + nreq < wq->max_post)) 3502 return 0; 3503 3504 cq = to_mcq(ib_cq); 3505 spin_lock(&cq->lock); 3506 cur = wq->head - wq->tail; 3507 spin_unlock(&cq->lock); 3508 3509 return cur + nreq >= wq->max_post; 3510 } 3511 3512 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3513 u64 remote_addr, u32 rkey) 3514 { 3515 rseg->raddr = cpu_to_be64(remote_addr); 3516 rseg->rkey = cpu_to_be32(rkey); 3517 rseg->reserved = 0; 3518 } 3519 3520 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3521 struct ib_send_wr *wr, void *qend, 3522 struct mlx5_ib_qp *qp, int *size) 3523 { 3524 void *seg = eseg; 3525 3526 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3527 3528 if (wr->send_flags & IB_SEND_IP_CSUM) 3529 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3530 MLX5_ETH_WQE_L4_CSUM; 3531 3532 seg += sizeof(struct mlx5_wqe_eth_seg); 3533 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3534 3535 if (wr->opcode == IB_WR_LSO) { 3536 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3537 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3538 u64 left, leftlen, copysz; 3539 void *pdata = ud_wr->header; 3540 3541 left = ud_wr->hlen; 3542 eseg->mss = cpu_to_be16(ud_wr->mss); 3543 eseg->inline_hdr.sz = cpu_to_be16(left); 3544 3545 /* 3546 * check if there is space till the end of queue, if yes, 3547 * copy all in one shot, otherwise copy till the end of queue, 3548 * rollback and than the copy the left 3549 */ 3550 leftlen = qend - (void *)eseg->inline_hdr.start; 3551 copysz = min_t(u64, leftlen, left); 3552 3553 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3554 3555 if (likely(copysz > size_of_inl_hdr_start)) { 3556 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3557 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3558 } 3559 3560 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3561 seg = mlx5_get_send_wqe(qp, 0); 3562 left -= copysz; 3563 pdata += copysz; 3564 memcpy(seg, pdata, left); 3565 seg += ALIGN(left, 16); 3566 *size += ALIGN(left, 16) / 16; 3567 } 3568 } 3569 3570 return seg; 3571 } 3572 3573 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3574 struct ib_send_wr *wr) 3575 { 3576 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3577 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3578 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3579 } 3580 3581 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3582 { 3583 dseg->byte_count = cpu_to_be32(sg->length); 3584 dseg->lkey = cpu_to_be32(sg->lkey); 3585 dseg->addr = cpu_to_be64(sg->addr); 3586 } 3587 3588 static u64 get_xlt_octo(u64 bytes) 3589 { 3590 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3591 MLX5_IB_UMR_OCTOWORD; 3592 } 3593 3594 static __be64 frwr_mkey_mask(void) 3595 { 3596 u64 result; 3597 3598 result = MLX5_MKEY_MASK_LEN | 3599 MLX5_MKEY_MASK_PAGE_SIZE | 3600 MLX5_MKEY_MASK_START_ADDR | 3601 MLX5_MKEY_MASK_EN_RINVAL | 3602 MLX5_MKEY_MASK_KEY | 3603 MLX5_MKEY_MASK_LR | 3604 MLX5_MKEY_MASK_LW | 3605 MLX5_MKEY_MASK_RR | 3606 MLX5_MKEY_MASK_RW | 3607 MLX5_MKEY_MASK_A | 3608 MLX5_MKEY_MASK_SMALL_FENCE | 3609 MLX5_MKEY_MASK_FREE; 3610 3611 return cpu_to_be64(result); 3612 } 3613 3614 static __be64 sig_mkey_mask(void) 3615 { 3616 u64 result; 3617 3618 result = MLX5_MKEY_MASK_LEN | 3619 MLX5_MKEY_MASK_PAGE_SIZE | 3620 MLX5_MKEY_MASK_START_ADDR | 3621 MLX5_MKEY_MASK_EN_SIGERR | 3622 MLX5_MKEY_MASK_EN_RINVAL | 3623 MLX5_MKEY_MASK_KEY | 3624 MLX5_MKEY_MASK_LR | 3625 MLX5_MKEY_MASK_LW | 3626 MLX5_MKEY_MASK_RR | 3627 MLX5_MKEY_MASK_RW | 3628 MLX5_MKEY_MASK_SMALL_FENCE | 3629 MLX5_MKEY_MASK_FREE | 3630 MLX5_MKEY_MASK_BSF_EN; 3631 3632 return cpu_to_be64(result); 3633 } 3634 3635 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3636 struct mlx5_ib_mr *mr) 3637 { 3638 int size = mr->ndescs * mr->desc_size; 3639 3640 memset(umr, 0, sizeof(*umr)); 3641 3642 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3643 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3644 umr->mkey_mask = frwr_mkey_mask(); 3645 } 3646 3647 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3648 { 3649 memset(umr, 0, sizeof(*umr)); 3650 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3651 umr->flags = MLX5_UMR_INLINE; 3652 } 3653 3654 static __be64 get_umr_enable_mr_mask(void) 3655 { 3656 u64 result; 3657 3658 result = MLX5_MKEY_MASK_KEY | 3659 MLX5_MKEY_MASK_FREE; 3660 3661 return cpu_to_be64(result); 3662 } 3663 3664 static __be64 get_umr_disable_mr_mask(void) 3665 { 3666 u64 result; 3667 3668 result = MLX5_MKEY_MASK_FREE; 3669 3670 return cpu_to_be64(result); 3671 } 3672 3673 static __be64 get_umr_update_translation_mask(void) 3674 { 3675 u64 result; 3676 3677 result = MLX5_MKEY_MASK_LEN | 3678 MLX5_MKEY_MASK_PAGE_SIZE | 3679 MLX5_MKEY_MASK_START_ADDR; 3680 3681 return cpu_to_be64(result); 3682 } 3683 3684 static __be64 get_umr_update_access_mask(int atomic) 3685 { 3686 u64 result; 3687 3688 result = MLX5_MKEY_MASK_LR | 3689 MLX5_MKEY_MASK_LW | 3690 MLX5_MKEY_MASK_RR | 3691 MLX5_MKEY_MASK_RW; 3692 3693 if (atomic) 3694 result |= MLX5_MKEY_MASK_A; 3695 3696 return cpu_to_be64(result); 3697 } 3698 3699 static __be64 get_umr_update_pd_mask(void) 3700 { 3701 u64 result; 3702 3703 result = MLX5_MKEY_MASK_PD; 3704 3705 return cpu_to_be64(result); 3706 } 3707 3708 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 3709 { 3710 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 3711 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 3712 (mask & MLX5_MKEY_MASK_A && 3713 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 3714 return -EPERM; 3715 return 0; 3716 } 3717 3718 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 3719 struct mlx5_wqe_umr_ctrl_seg *umr, 3720 struct ib_send_wr *wr, int atomic) 3721 { 3722 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3723 3724 memset(umr, 0, sizeof(*umr)); 3725 3726 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3727 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3728 else 3729 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3730 3731 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3732 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3733 u64 offset = get_xlt_octo(umrwr->offset); 3734 3735 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3736 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3737 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3738 } 3739 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3740 umr->mkey_mask |= get_umr_update_translation_mask(); 3741 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3742 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3743 umr->mkey_mask |= get_umr_update_pd_mask(); 3744 } 3745 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3746 umr->mkey_mask |= get_umr_enable_mr_mask(); 3747 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3748 umr->mkey_mask |= get_umr_disable_mr_mask(); 3749 3750 if (!wr->num_sge) 3751 umr->flags |= MLX5_UMR_INLINE; 3752 3753 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 3754 } 3755 3756 static u8 get_umr_flags(int acc) 3757 { 3758 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3759 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3760 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3761 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3762 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3763 } 3764 3765 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3766 struct mlx5_ib_mr *mr, 3767 u32 key, int access) 3768 { 3769 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3770 3771 memset(seg, 0, sizeof(*seg)); 3772 3773 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3774 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3775 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3776 /* KLMs take twice the size of MTTs */ 3777 ndescs *= 2; 3778 3779 seg->flags = get_umr_flags(access) | mr->access_mode; 3780 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3781 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3782 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3783 seg->len = cpu_to_be64(mr->ibmr.length); 3784 seg->xlt_oct_size = cpu_to_be32(ndescs); 3785 } 3786 3787 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3788 { 3789 memset(seg, 0, sizeof(*seg)); 3790 seg->status = MLX5_MKEY_STATUS_FREE; 3791 } 3792 3793 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3794 { 3795 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3796 3797 memset(seg, 0, sizeof(*seg)); 3798 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3799 seg->status = MLX5_MKEY_STATUS_FREE; 3800 3801 seg->flags = convert_access(umrwr->access_flags); 3802 if (umrwr->pd) 3803 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3804 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3805 !umrwr->length) 3806 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3807 3808 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3809 seg->len = cpu_to_be64(umrwr->length); 3810 seg->log2_page_size = umrwr->page_shift; 3811 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3812 mlx5_mkey_variant(umrwr->mkey)); 3813 } 3814 3815 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3816 struct mlx5_ib_mr *mr, 3817 struct mlx5_ib_pd *pd) 3818 { 3819 int bcount = mr->desc_size * mr->ndescs; 3820 3821 dseg->addr = cpu_to_be64(mr->desc_map); 3822 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3823 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3824 } 3825 3826 static __be32 send_ieth(struct ib_send_wr *wr) 3827 { 3828 switch (wr->opcode) { 3829 case IB_WR_SEND_WITH_IMM: 3830 case IB_WR_RDMA_WRITE_WITH_IMM: 3831 return wr->ex.imm_data; 3832 3833 case IB_WR_SEND_WITH_INV: 3834 return cpu_to_be32(wr->ex.invalidate_rkey); 3835 3836 default: 3837 return 0; 3838 } 3839 } 3840 3841 static u8 calc_sig(void *wqe, int size) 3842 { 3843 u8 *p = wqe; 3844 u8 res = 0; 3845 int i; 3846 3847 for (i = 0; i < size; i++) 3848 res ^= p[i]; 3849 3850 return ~res; 3851 } 3852 3853 static u8 wq_sig(void *wqe) 3854 { 3855 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3856 } 3857 3858 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3859 void *wqe, int *sz) 3860 { 3861 struct mlx5_wqe_inline_seg *seg; 3862 void *qend = qp->sq.qend; 3863 void *addr; 3864 int inl = 0; 3865 int copy; 3866 int len; 3867 int i; 3868 3869 seg = wqe; 3870 wqe += sizeof(*seg); 3871 for (i = 0; i < wr->num_sge; i++) { 3872 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3873 len = wr->sg_list[i].length; 3874 inl += len; 3875 3876 if (unlikely(inl > qp->max_inline_data)) 3877 return -ENOMEM; 3878 3879 if (unlikely(wqe + len > qend)) { 3880 copy = qend - wqe; 3881 memcpy(wqe, addr, copy); 3882 addr += copy; 3883 len -= copy; 3884 wqe = mlx5_get_send_wqe(qp, 0); 3885 } 3886 memcpy(wqe, addr, len); 3887 wqe += len; 3888 } 3889 3890 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3891 3892 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3893 3894 return 0; 3895 } 3896 3897 static u16 prot_field_size(enum ib_signature_type type) 3898 { 3899 switch (type) { 3900 case IB_SIG_TYPE_T10_DIF: 3901 return MLX5_DIF_SIZE; 3902 default: 3903 return 0; 3904 } 3905 } 3906 3907 static u8 bs_selector(int block_size) 3908 { 3909 switch (block_size) { 3910 case 512: return 0x1; 3911 case 520: return 0x2; 3912 case 4096: return 0x3; 3913 case 4160: return 0x4; 3914 case 1073741824: return 0x5; 3915 default: return 0; 3916 } 3917 } 3918 3919 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3920 struct mlx5_bsf_inl *inl) 3921 { 3922 /* Valid inline section and allow BSF refresh */ 3923 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3924 MLX5_BSF_REFRESH_DIF); 3925 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3926 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3927 /* repeating block */ 3928 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3929 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3930 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3931 3932 if (domain->sig.dif.ref_remap) 3933 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3934 3935 if (domain->sig.dif.app_escape) { 3936 if (domain->sig.dif.ref_escape) 3937 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3938 else 3939 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3940 } 3941 3942 inl->dif_app_bitmask_check = 3943 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3944 } 3945 3946 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3947 struct ib_sig_attrs *sig_attrs, 3948 struct mlx5_bsf *bsf, u32 data_size) 3949 { 3950 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3951 struct mlx5_bsf_basic *basic = &bsf->basic; 3952 struct ib_sig_domain *mem = &sig_attrs->mem; 3953 struct ib_sig_domain *wire = &sig_attrs->wire; 3954 3955 memset(bsf, 0, sizeof(*bsf)); 3956 3957 /* Basic + Extended + Inline */ 3958 basic->bsf_size_sbs = 1 << 7; 3959 /* Input domain check byte mask */ 3960 basic->check_byte_mask = sig_attrs->check_mask; 3961 basic->raw_data_size = cpu_to_be32(data_size); 3962 3963 /* Memory domain */ 3964 switch (sig_attrs->mem.sig_type) { 3965 case IB_SIG_TYPE_NONE: 3966 break; 3967 case IB_SIG_TYPE_T10_DIF: 3968 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3969 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3970 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3971 break; 3972 default: 3973 return -EINVAL; 3974 } 3975 3976 /* Wire domain */ 3977 switch (sig_attrs->wire.sig_type) { 3978 case IB_SIG_TYPE_NONE: 3979 break; 3980 case IB_SIG_TYPE_T10_DIF: 3981 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3982 mem->sig_type == wire->sig_type) { 3983 /* Same block structure */ 3984 basic->bsf_size_sbs |= 1 << 4; 3985 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3986 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3987 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3988 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3989 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3990 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3991 } else 3992 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3993 3994 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3995 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3996 break; 3997 default: 3998 return -EINVAL; 3999 } 4000 4001 return 0; 4002 } 4003 4004 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 4005 struct mlx5_ib_qp *qp, void **seg, int *size) 4006 { 4007 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4008 struct ib_mr *sig_mr = wr->sig_mr; 4009 struct mlx5_bsf *bsf; 4010 u32 data_len = wr->wr.sg_list->length; 4011 u32 data_key = wr->wr.sg_list->lkey; 4012 u64 data_va = wr->wr.sg_list->addr; 4013 int ret; 4014 int wqe_size; 4015 4016 if (!wr->prot || 4017 (data_key == wr->prot->lkey && 4018 data_va == wr->prot->addr && 4019 data_len == wr->prot->length)) { 4020 /** 4021 * Source domain doesn't contain signature information 4022 * or data and protection are interleaved in memory. 4023 * So need construct: 4024 * ------------------ 4025 * | data_klm | 4026 * ------------------ 4027 * | BSF | 4028 * ------------------ 4029 **/ 4030 struct mlx5_klm *data_klm = *seg; 4031 4032 data_klm->bcount = cpu_to_be32(data_len); 4033 data_klm->key = cpu_to_be32(data_key); 4034 data_klm->va = cpu_to_be64(data_va); 4035 wqe_size = ALIGN(sizeof(*data_klm), 64); 4036 } else { 4037 /** 4038 * Source domain contains signature information 4039 * So need construct a strided block format: 4040 * --------------------------- 4041 * | stride_block_ctrl | 4042 * --------------------------- 4043 * | data_klm | 4044 * --------------------------- 4045 * | prot_klm | 4046 * --------------------------- 4047 * | BSF | 4048 * --------------------------- 4049 **/ 4050 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4051 struct mlx5_stride_block_entry *data_sentry; 4052 struct mlx5_stride_block_entry *prot_sentry; 4053 u32 prot_key = wr->prot->lkey; 4054 u64 prot_va = wr->prot->addr; 4055 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4056 int prot_size; 4057 4058 sblock_ctrl = *seg; 4059 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4060 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4061 4062 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4063 if (!prot_size) { 4064 pr_err("Bad block size given: %u\n", block_size); 4065 return -EINVAL; 4066 } 4067 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4068 prot_size); 4069 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4070 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4071 sblock_ctrl->num_entries = cpu_to_be16(2); 4072 4073 data_sentry->bcount = cpu_to_be16(block_size); 4074 data_sentry->key = cpu_to_be32(data_key); 4075 data_sentry->va = cpu_to_be64(data_va); 4076 data_sentry->stride = cpu_to_be16(block_size); 4077 4078 prot_sentry->bcount = cpu_to_be16(prot_size); 4079 prot_sentry->key = cpu_to_be32(prot_key); 4080 prot_sentry->va = cpu_to_be64(prot_va); 4081 prot_sentry->stride = cpu_to_be16(prot_size); 4082 4083 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4084 sizeof(*prot_sentry), 64); 4085 } 4086 4087 *seg += wqe_size; 4088 *size += wqe_size / 16; 4089 if (unlikely((*seg == qp->sq.qend))) 4090 *seg = mlx5_get_send_wqe(qp, 0); 4091 4092 bsf = *seg; 4093 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4094 if (ret) 4095 return -EINVAL; 4096 4097 *seg += sizeof(*bsf); 4098 *size += sizeof(*bsf) / 16; 4099 if (unlikely((*seg == qp->sq.qend))) 4100 *seg = mlx5_get_send_wqe(qp, 0); 4101 4102 return 0; 4103 } 4104 4105 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4106 struct ib_sig_handover_wr *wr, u32 size, 4107 u32 length, u32 pdn) 4108 { 4109 struct ib_mr *sig_mr = wr->sig_mr; 4110 u32 sig_key = sig_mr->rkey; 4111 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4112 4113 memset(seg, 0, sizeof(*seg)); 4114 4115 seg->flags = get_umr_flags(wr->access_flags) | 4116 MLX5_MKC_ACCESS_MODE_KLMS; 4117 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4118 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4119 MLX5_MKEY_BSF_EN | pdn); 4120 seg->len = cpu_to_be64(length); 4121 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4122 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4123 } 4124 4125 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4126 u32 size) 4127 { 4128 memset(umr, 0, sizeof(*umr)); 4129 4130 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4131 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4132 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4133 umr->mkey_mask = sig_mkey_mask(); 4134 } 4135 4136 4137 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 4138 void **seg, int *size) 4139 { 4140 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4141 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4142 u32 pdn = get_pd(qp)->pdn; 4143 u32 xlt_size; 4144 int region_len, ret; 4145 4146 if (unlikely(wr->wr.num_sge != 1) || 4147 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4148 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4149 unlikely(!sig_mr->sig->sig_status_checked)) 4150 return -EINVAL; 4151 4152 /* length of the protected region, data + protection */ 4153 region_len = wr->wr.sg_list->length; 4154 if (wr->prot && 4155 (wr->prot->lkey != wr->wr.sg_list->lkey || 4156 wr->prot->addr != wr->wr.sg_list->addr || 4157 wr->prot->length != wr->wr.sg_list->length)) 4158 region_len += wr->prot->length; 4159 4160 /** 4161 * KLM octoword size - if protection was provided 4162 * then we use strided block format (3 octowords), 4163 * else we use single KLM (1 octoword) 4164 **/ 4165 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4166 4167 set_sig_umr_segment(*seg, xlt_size); 4168 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4169 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4170 if (unlikely((*seg == qp->sq.qend))) 4171 *seg = mlx5_get_send_wqe(qp, 0); 4172 4173 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4174 *seg += sizeof(struct mlx5_mkey_seg); 4175 *size += sizeof(struct mlx5_mkey_seg) / 16; 4176 if (unlikely((*seg == qp->sq.qend))) 4177 *seg = mlx5_get_send_wqe(qp, 0); 4178 4179 ret = set_sig_data_segment(wr, qp, seg, size); 4180 if (ret) 4181 return ret; 4182 4183 sig_mr->sig->sig_status_checked = false; 4184 return 0; 4185 } 4186 4187 static int set_psv_wr(struct ib_sig_domain *domain, 4188 u32 psv_idx, void **seg, int *size) 4189 { 4190 struct mlx5_seg_set_psv *psv_seg = *seg; 4191 4192 memset(psv_seg, 0, sizeof(*psv_seg)); 4193 psv_seg->psv_num = cpu_to_be32(psv_idx); 4194 switch (domain->sig_type) { 4195 case IB_SIG_TYPE_NONE: 4196 break; 4197 case IB_SIG_TYPE_T10_DIF: 4198 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4199 domain->sig.dif.app_tag); 4200 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4201 break; 4202 default: 4203 pr_err("Bad signature type (%d) is given.\n", 4204 domain->sig_type); 4205 return -EINVAL; 4206 } 4207 4208 *seg += sizeof(*psv_seg); 4209 *size += sizeof(*psv_seg) / 16; 4210 4211 return 0; 4212 } 4213 4214 static int set_reg_wr(struct mlx5_ib_qp *qp, 4215 struct ib_reg_wr *wr, 4216 void **seg, int *size) 4217 { 4218 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4219 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4220 4221 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4222 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4223 "Invalid IB_SEND_INLINE send flag\n"); 4224 return -EINVAL; 4225 } 4226 4227 set_reg_umr_seg(*seg, mr); 4228 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4229 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4230 if (unlikely((*seg == qp->sq.qend))) 4231 *seg = mlx5_get_send_wqe(qp, 0); 4232 4233 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4234 *seg += sizeof(struct mlx5_mkey_seg); 4235 *size += sizeof(struct mlx5_mkey_seg) / 16; 4236 if (unlikely((*seg == qp->sq.qend))) 4237 *seg = mlx5_get_send_wqe(qp, 0); 4238 4239 set_reg_data_seg(*seg, mr, pd); 4240 *seg += sizeof(struct mlx5_wqe_data_seg); 4241 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4242 4243 return 0; 4244 } 4245 4246 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 4247 { 4248 set_linv_umr_seg(*seg); 4249 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4250 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4251 if (unlikely((*seg == qp->sq.qend))) 4252 *seg = mlx5_get_send_wqe(qp, 0); 4253 set_linv_mkey_seg(*seg); 4254 *seg += sizeof(struct mlx5_mkey_seg); 4255 *size += sizeof(struct mlx5_mkey_seg) / 16; 4256 if (unlikely((*seg == qp->sq.qend))) 4257 *seg = mlx5_get_send_wqe(qp, 0); 4258 } 4259 4260 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 4261 { 4262 __be32 *p = NULL; 4263 int tidx = idx; 4264 int i, j; 4265 4266 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 4267 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4268 if ((i & 0xf) == 0) { 4269 void *buf = mlx5_get_send_wqe(qp, tidx); 4270 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4271 p = buf; 4272 j = 0; 4273 } 4274 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4275 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4276 be32_to_cpu(p[j + 3])); 4277 } 4278 } 4279 4280 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4281 struct mlx5_wqe_ctrl_seg **ctrl, 4282 struct ib_send_wr *wr, unsigned *idx, 4283 int *size, int nreq) 4284 { 4285 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4286 return -ENOMEM; 4287 4288 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4289 *seg = mlx5_get_send_wqe(qp, *idx); 4290 *ctrl = *seg; 4291 *(uint32_t *)(*seg + 8) = 0; 4292 (*ctrl)->imm = send_ieth(wr); 4293 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4294 (wr->send_flags & IB_SEND_SIGNALED ? 4295 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4296 (wr->send_flags & IB_SEND_SOLICITED ? 4297 MLX5_WQE_CTRL_SOLICITED : 0); 4298 4299 *seg += sizeof(**ctrl); 4300 *size = sizeof(**ctrl) / 16; 4301 4302 return 0; 4303 } 4304 4305 static void finish_wqe(struct mlx5_ib_qp *qp, 4306 struct mlx5_wqe_ctrl_seg *ctrl, 4307 u8 size, unsigned idx, u64 wr_id, 4308 int nreq, u8 fence, u32 mlx5_opcode) 4309 { 4310 u8 opmod = 0; 4311 4312 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4313 mlx5_opcode | ((u32)opmod << 24)); 4314 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4315 ctrl->fm_ce_se |= fence; 4316 if (unlikely(qp->wq_sig)) 4317 ctrl->signature = wq_sig(ctrl); 4318 4319 qp->sq.wrid[idx] = wr_id; 4320 qp->sq.w_list[idx].opcode = mlx5_opcode; 4321 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4322 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4323 qp->sq.w_list[idx].next = qp->sq.cur_post; 4324 } 4325 4326 4327 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 4328 struct ib_send_wr **bad_wr) 4329 { 4330 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4331 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4332 struct mlx5_core_dev *mdev = dev->mdev; 4333 struct mlx5_ib_qp *qp; 4334 struct mlx5_ib_mr *mr; 4335 struct mlx5_wqe_data_seg *dpseg; 4336 struct mlx5_wqe_xrc_seg *xrc; 4337 struct mlx5_bf *bf; 4338 int uninitialized_var(size); 4339 void *qend; 4340 unsigned long flags; 4341 unsigned idx; 4342 int err = 0; 4343 int num_sge; 4344 void *seg; 4345 int nreq; 4346 int i; 4347 u8 next_fence = 0; 4348 u8 fence; 4349 4350 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4351 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4352 4353 qp = to_mqp(ibqp); 4354 bf = &qp->bf; 4355 qend = qp->sq.qend; 4356 4357 spin_lock_irqsave(&qp->sq.lock, flags); 4358 4359 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4360 err = -EIO; 4361 *bad_wr = wr; 4362 nreq = 0; 4363 goto out; 4364 } 4365 4366 for (nreq = 0; wr; nreq++, wr = wr->next) { 4367 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4368 mlx5_ib_warn(dev, "\n"); 4369 err = -EINVAL; 4370 *bad_wr = wr; 4371 goto out; 4372 } 4373 4374 num_sge = wr->num_sge; 4375 if (unlikely(num_sge > qp->sq.max_gs)) { 4376 mlx5_ib_warn(dev, "\n"); 4377 err = -EINVAL; 4378 *bad_wr = wr; 4379 goto out; 4380 } 4381 4382 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 4383 if (err) { 4384 mlx5_ib_warn(dev, "\n"); 4385 err = -ENOMEM; 4386 *bad_wr = wr; 4387 goto out; 4388 } 4389 4390 if (wr->opcode == IB_WR_LOCAL_INV || 4391 wr->opcode == IB_WR_REG_MR) { 4392 fence = dev->umr_fence; 4393 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4394 } else if (wr->send_flags & IB_SEND_FENCE) { 4395 if (qp->next_fence) 4396 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4397 else 4398 fence = MLX5_FENCE_MODE_FENCE; 4399 } else { 4400 fence = qp->next_fence; 4401 } 4402 4403 switch (ibqp->qp_type) { 4404 case IB_QPT_XRC_INI: 4405 xrc = seg; 4406 seg += sizeof(*xrc); 4407 size += sizeof(*xrc) / 16; 4408 /* fall through */ 4409 case IB_QPT_RC: 4410 switch (wr->opcode) { 4411 case IB_WR_RDMA_READ: 4412 case IB_WR_RDMA_WRITE: 4413 case IB_WR_RDMA_WRITE_WITH_IMM: 4414 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4415 rdma_wr(wr)->rkey); 4416 seg += sizeof(struct mlx5_wqe_raddr_seg); 4417 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4418 break; 4419 4420 case IB_WR_ATOMIC_CMP_AND_SWP: 4421 case IB_WR_ATOMIC_FETCH_AND_ADD: 4422 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4423 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4424 err = -ENOSYS; 4425 *bad_wr = wr; 4426 goto out; 4427 4428 case IB_WR_LOCAL_INV: 4429 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4430 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4431 set_linv_wr(qp, &seg, &size); 4432 num_sge = 0; 4433 break; 4434 4435 case IB_WR_REG_MR: 4436 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4437 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4438 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4439 if (err) { 4440 *bad_wr = wr; 4441 goto out; 4442 } 4443 num_sge = 0; 4444 break; 4445 4446 case IB_WR_REG_SIG_MR: 4447 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4448 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4449 4450 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4451 err = set_sig_umr_wr(wr, qp, &seg, &size); 4452 if (err) { 4453 mlx5_ib_warn(dev, "\n"); 4454 *bad_wr = wr; 4455 goto out; 4456 } 4457 4458 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4459 fence, MLX5_OPCODE_UMR); 4460 /* 4461 * SET_PSV WQEs are not signaled and solicited 4462 * on error 4463 */ 4464 wr->send_flags &= ~IB_SEND_SIGNALED; 4465 wr->send_flags |= IB_SEND_SOLICITED; 4466 err = begin_wqe(qp, &seg, &ctrl, wr, 4467 &idx, &size, nreq); 4468 if (err) { 4469 mlx5_ib_warn(dev, "\n"); 4470 err = -ENOMEM; 4471 *bad_wr = wr; 4472 goto out; 4473 } 4474 4475 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4476 mr->sig->psv_memory.psv_idx, &seg, 4477 &size); 4478 if (err) { 4479 mlx5_ib_warn(dev, "\n"); 4480 *bad_wr = wr; 4481 goto out; 4482 } 4483 4484 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4485 fence, MLX5_OPCODE_SET_PSV); 4486 err = begin_wqe(qp, &seg, &ctrl, wr, 4487 &idx, &size, nreq); 4488 if (err) { 4489 mlx5_ib_warn(dev, "\n"); 4490 err = -ENOMEM; 4491 *bad_wr = wr; 4492 goto out; 4493 } 4494 4495 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4496 mr->sig->psv_wire.psv_idx, &seg, 4497 &size); 4498 if (err) { 4499 mlx5_ib_warn(dev, "\n"); 4500 *bad_wr = wr; 4501 goto out; 4502 } 4503 4504 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4505 fence, MLX5_OPCODE_SET_PSV); 4506 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4507 num_sge = 0; 4508 goto skip_psv; 4509 4510 default: 4511 break; 4512 } 4513 break; 4514 4515 case IB_QPT_UC: 4516 switch (wr->opcode) { 4517 case IB_WR_RDMA_WRITE: 4518 case IB_WR_RDMA_WRITE_WITH_IMM: 4519 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4520 rdma_wr(wr)->rkey); 4521 seg += sizeof(struct mlx5_wqe_raddr_seg); 4522 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4523 break; 4524 4525 default: 4526 break; 4527 } 4528 break; 4529 4530 case IB_QPT_SMI: 4531 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4532 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4533 err = -EPERM; 4534 *bad_wr = wr; 4535 goto out; 4536 } 4537 /* fall through */ 4538 case MLX5_IB_QPT_HW_GSI: 4539 set_datagram_seg(seg, wr); 4540 seg += sizeof(struct mlx5_wqe_datagram_seg); 4541 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4542 if (unlikely((seg == qend))) 4543 seg = mlx5_get_send_wqe(qp, 0); 4544 break; 4545 case IB_QPT_UD: 4546 set_datagram_seg(seg, wr); 4547 seg += sizeof(struct mlx5_wqe_datagram_seg); 4548 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4549 4550 if (unlikely((seg == qend))) 4551 seg = mlx5_get_send_wqe(qp, 0); 4552 4553 /* handle qp that supports ud offload */ 4554 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4555 struct mlx5_wqe_eth_pad *pad; 4556 4557 pad = seg; 4558 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4559 seg += sizeof(struct mlx5_wqe_eth_pad); 4560 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4561 4562 seg = set_eth_seg(seg, wr, qend, qp, &size); 4563 4564 if (unlikely((seg == qend))) 4565 seg = mlx5_get_send_wqe(qp, 0); 4566 } 4567 break; 4568 case MLX5_IB_QPT_REG_UMR: 4569 if (wr->opcode != MLX5_IB_WR_UMR) { 4570 err = -EINVAL; 4571 mlx5_ib_warn(dev, "bad opcode\n"); 4572 goto out; 4573 } 4574 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4575 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4576 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4577 if (unlikely(err)) 4578 goto out; 4579 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4580 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4581 if (unlikely((seg == qend))) 4582 seg = mlx5_get_send_wqe(qp, 0); 4583 set_reg_mkey_segment(seg, wr); 4584 seg += sizeof(struct mlx5_mkey_seg); 4585 size += sizeof(struct mlx5_mkey_seg) / 16; 4586 if (unlikely((seg == qend))) 4587 seg = mlx5_get_send_wqe(qp, 0); 4588 break; 4589 4590 default: 4591 break; 4592 } 4593 4594 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4595 int uninitialized_var(sz); 4596 4597 err = set_data_inl_seg(qp, wr, seg, &sz); 4598 if (unlikely(err)) { 4599 mlx5_ib_warn(dev, "\n"); 4600 *bad_wr = wr; 4601 goto out; 4602 } 4603 size += sz; 4604 } else { 4605 dpseg = seg; 4606 for (i = 0; i < num_sge; i++) { 4607 if (unlikely(dpseg == qend)) { 4608 seg = mlx5_get_send_wqe(qp, 0); 4609 dpseg = seg; 4610 } 4611 if (likely(wr->sg_list[i].length)) { 4612 set_data_ptr_seg(dpseg, wr->sg_list + i); 4613 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4614 dpseg++; 4615 } 4616 } 4617 } 4618 4619 qp->next_fence = next_fence; 4620 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4621 mlx5_ib_opcode[wr->opcode]); 4622 skip_psv: 4623 if (0) 4624 dump_wqe(qp, idx, size); 4625 } 4626 4627 out: 4628 if (likely(nreq)) { 4629 qp->sq.head += nreq; 4630 4631 /* Make sure that descriptors are written before 4632 * updating doorbell record and ringing the doorbell 4633 */ 4634 wmb(); 4635 4636 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4637 4638 /* Make sure doorbell record is visible to the HCA before 4639 * we hit doorbell */ 4640 wmb(); 4641 4642 /* currently we support only regular doorbells */ 4643 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4644 /* Make sure doorbells don't leak out of SQ spinlock 4645 * and reach the HCA out of order. 4646 */ 4647 mmiowb(); 4648 bf->offset ^= bf->buf_size; 4649 } 4650 4651 spin_unlock_irqrestore(&qp->sq.lock, flags); 4652 4653 return err; 4654 } 4655 4656 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4657 { 4658 sig->signature = calc_sig(sig, size); 4659 } 4660 4661 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4662 struct ib_recv_wr **bad_wr) 4663 { 4664 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4665 struct mlx5_wqe_data_seg *scat; 4666 struct mlx5_rwqe_sig *sig; 4667 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4668 struct mlx5_core_dev *mdev = dev->mdev; 4669 unsigned long flags; 4670 int err = 0; 4671 int nreq; 4672 int ind; 4673 int i; 4674 4675 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4676 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4677 4678 spin_lock_irqsave(&qp->rq.lock, flags); 4679 4680 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4681 err = -EIO; 4682 *bad_wr = wr; 4683 nreq = 0; 4684 goto out; 4685 } 4686 4687 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4688 4689 for (nreq = 0; wr; nreq++, wr = wr->next) { 4690 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4691 err = -ENOMEM; 4692 *bad_wr = wr; 4693 goto out; 4694 } 4695 4696 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4697 err = -EINVAL; 4698 *bad_wr = wr; 4699 goto out; 4700 } 4701 4702 scat = get_recv_wqe(qp, ind); 4703 if (qp->wq_sig) 4704 scat++; 4705 4706 for (i = 0; i < wr->num_sge; i++) 4707 set_data_ptr_seg(scat + i, wr->sg_list + i); 4708 4709 if (i < qp->rq.max_gs) { 4710 scat[i].byte_count = 0; 4711 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4712 scat[i].addr = 0; 4713 } 4714 4715 if (qp->wq_sig) { 4716 sig = (struct mlx5_rwqe_sig *)scat; 4717 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4718 } 4719 4720 qp->rq.wrid[ind] = wr->wr_id; 4721 4722 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4723 } 4724 4725 out: 4726 if (likely(nreq)) { 4727 qp->rq.head += nreq; 4728 4729 /* Make sure that descriptors are written before 4730 * doorbell record. 4731 */ 4732 wmb(); 4733 4734 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4735 } 4736 4737 spin_unlock_irqrestore(&qp->rq.lock, flags); 4738 4739 return err; 4740 } 4741 4742 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4743 { 4744 switch (mlx5_state) { 4745 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4746 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4747 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4748 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4749 case MLX5_QP_STATE_SQ_DRAINING: 4750 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4751 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4752 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4753 default: return -1; 4754 } 4755 } 4756 4757 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4758 { 4759 switch (mlx5_mig_state) { 4760 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4761 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4762 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4763 default: return -1; 4764 } 4765 } 4766 4767 static int to_ib_qp_access_flags(int mlx5_flags) 4768 { 4769 int ib_flags = 0; 4770 4771 if (mlx5_flags & MLX5_QP_BIT_RRE) 4772 ib_flags |= IB_ACCESS_REMOTE_READ; 4773 if (mlx5_flags & MLX5_QP_BIT_RWE) 4774 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4775 if (mlx5_flags & MLX5_QP_BIT_RAE) 4776 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4777 4778 return ib_flags; 4779 } 4780 4781 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4782 struct rdma_ah_attr *ah_attr, 4783 struct mlx5_qp_path *path) 4784 { 4785 4786 memset(ah_attr, 0, sizeof(*ah_attr)); 4787 4788 if (!path->port || path->port > ibdev->num_ports) 4789 return; 4790 4791 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4792 4793 rdma_ah_set_port_num(ah_attr, path->port); 4794 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4795 4796 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4797 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4798 rdma_ah_set_static_rate(ah_attr, 4799 path->static_rate ? path->static_rate - 5 : 0); 4800 if (path->grh_mlid & (1 << 7)) { 4801 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4802 4803 rdma_ah_set_grh(ah_attr, NULL, 4804 tc_fl & 0xfffff, 4805 path->mgid_index, 4806 path->hop_limit, 4807 (tc_fl >> 20) & 0xff); 4808 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4809 } 4810 } 4811 4812 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4813 struct mlx5_ib_sq *sq, 4814 u8 *sq_state) 4815 { 4816 int err; 4817 4818 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4819 if (err) 4820 goto out; 4821 sq->state = *sq_state; 4822 4823 out: 4824 return err; 4825 } 4826 4827 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4828 struct mlx5_ib_rq *rq, 4829 u8 *rq_state) 4830 { 4831 void *out; 4832 void *rqc; 4833 int inlen; 4834 int err; 4835 4836 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4837 out = kvzalloc(inlen, GFP_KERNEL); 4838 if (!out) 4839 return -ENOMEM; 4840 4841 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4842 if (err) 4843 goto out; 4844 4845 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4846 *rq_state = MLX5_GET(rqc, rqc, state); 4847 rq->state = *rq_state; 4848 4849 out: 4850 kvfree(out); 4851 return err; 4852 } 4853 4854 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4855 struct mlx5_ib_qp *qp, u8 *qp_state) 4856 { 4857 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4858 [MLX5_RQC_STATE_RST] = { 4859 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4860 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4861 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4862 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4863 }, 4864 [MLX5_RQC_STATE_RDY] = { 4865 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4866 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4867 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4868 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4869 }, 4870 [MLX5_RQC_STATE_ERR] = { 4871 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4872 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4873 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4874 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4875 }, 4876 [MLX5_RQ_STATE_NA] = { 4877 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4878 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4879 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4880 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4881 }, 4882 }; 4883 4884 *qp_state = sqrq_trans[rq_state][sq_state]; 4885 4886 if (*qp_state == MLX5_QP_STATE_BAD) { 4887 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4888 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4889 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4890 return -EINVAL; 4891 } 4892 4893 if (*qp_state == MLX5_QP_STATE) 4894 *qp_state = qp->state; 4895 4896 return 0; 4897 } 4898 4899 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4900 struct mlx5_ib_qp *qp, 4901 u8 *raw_packet_qp_state) 4902 { 4903 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4904 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4905 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4906 int err; 4907 u8 sq_state = MLX5_SQ_STATE_NA; 4908 u8 rq_state = MLX5_RQ_STATE_NA; 4909 4910 if (qp->sq.wqe_cnt) { 4911 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4912 if (err) 4913 return err; 4914 } 4915 4916 if (qp->rq.wqe_cnt) { 4917 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4918 if (err) 4919 return err; 4920 } 4921 4922 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4923 raw_packet_qp_state); 4924 } 4925 4926 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4927 struct ib_qp_attr *qp_attr) 4928 { 4929 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4930 struct mlx5_qp_context *context; 4931 int mlx5_state; 4932 u32 *outb; 4933 int err = 0; 4934 4935 outb = kzalloc(outlen, GFP_KERNEL); 4936 if (!outb) 4937 return -ENOMEM; 4938 4939 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4940 outlen); 4941 if (err) 4942 goto out; 4943 4944 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4945 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4946 4947 mlx5_state = be32_to_cpu(context->flags) >> 28; 4948 4949 qp->state = to_ib_qp_state(mlx5_state); 4950 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4951 qp_attr->path_mig_state = 4952 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4953 qp_attr->qkey = be32_to_cpu(context->qkey); 4954 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4955 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4956 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4957 qp_attr->qp_access_flags = 4958 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4959 4960 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4961 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4962 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4963 qp_attr->alt_pkey_index = 4964 be16_to_cpu(context->alt_path.pkey_index); 4965 qp_attr->alt_port_num = 4966 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4967 } 4968 4969 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4970 qp_attr->port_num = context->pri_path.port; 4971 4972 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4973 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4974 4975 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4976 4977 qp_attr->max_dest_rd_atomic = 4978 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4979 qp_attr->min_rnr_timer = 4980 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4981 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4982 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4983 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4984 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4985 4986 out: 4987 kfree(outb); 4988 return err; 4989 } 4990 4991 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4992 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4993 struct ib_qp_init_attr *qp_init_attr) 4994 { 4995 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4996 u32 *out; 4997 u32 access_flags = 0; 4998 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4999 void *dctc; 5000 int err; 5001 int supported_mask = IB_QP_STATE | 5002 IB_QP_ACCESS_FLAGS | 5003 IB_QP_PORT | 5004 IB_QP_MIN_RNR_TIMER | 5005 IB_QP_AV | 5006 IB_QP_PATH_MTU | 5007 IB_QP_PKEY_INDEX; 5008 5009 if (qp_attr_mask & ~supported_mask) 5010 return -EINVAL; 5011 if (mqp->state != IB_QPS_RTR) 5012 return -EINVAL; 5013 5014 out = kzalloc(outlen, GFP_KERNEL); 5015 if (!out) 5016 return -ENOMEM; 5017 5018 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5019 if (err) 5020 goto out; 5021 5022 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5023 5024 if (qp_attr_mask & IB_QP_STATE) 5025 qp_attr->qp_state = IB_QPS_RTR; 5026 5027 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5028 if (MLX5_GET(dctc, dctc, rre)) 5029 access_flags |= IB_ACCESS_REMOTE_READ; 5030 if (MLX5_GET(dctc, dctc, rwe)) 5031 access_flags |= IB_ACCESS_REMOTE_WRITE; 5032 if (MLX5_GET(dctc, dctc, rae)) 5033 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5034 qp_attr->qp_access_flags = access_flags; 5035 } 5036 5037 if (qp_attr_mask & IB_QP_PORT) 5038 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5039 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5040 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5041 if (qp_attr_mask & IB_QP_AV) { 5042 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5043 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5044 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5045 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5046 } 5047 if (qp_attr_mask & IB_QP_PATH_MTU) 5048 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5049 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5050 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5051 out: 5052 kfree(out); 5053 return err; 5054 } 5055 5056 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5057 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5058 { 5059 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5060 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5061 int err = 0; 5062 u8 raw_packet_qp_state; 5063 5064 if (ibqp->rwq_ind_tbl) 5065 return -ENOSYS; 5066 5067 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5068 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5069 qp_init_attr); 5070 5071 /* Not all of output fields are applicable, make sure to zero them */ 5072 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5073 memset(qp_attr, 0, sizeof(*qp_attr)); 5074 5075 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5076 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5077 qp_attr_mask, qp_init_attr); 5078 5079 mutex_lock(&qp->mutex); 5080 5081 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5082 qp->flags & MLX5_IB_QP_UNDERLAY) { 5083 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5084 if (err) 5085 goto out; 5086 qp->state = raw_packet_qp_state; 5087 qp_attr->port_num = 1; 5088 } else { 5089 err = query_qp_attr(dev, qp, qp_attr); 5090 if (err) 5091 goto out; 5092 } 5093 5094 qp_attr->qp_state = qp->state; 5095 qp_attr->cur_qp_state = qp_attr->qp_state; 5096 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5097 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5098 5099 if (!ibqp->uobject) { 5100 qp_attr->cap.max_send_wr = qp->sq.max_post; 5101 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5102 qp_init_attr->qp_context = ibqp->qp_context; 5103 } else { 5104 qp_attr->cap.max_send_wr = 0; 5105 qp_attr->cap.max_send_sge = 0; 5106 } 5107 5108 qp_init_attr->qp_type = ibqp->qp_type; 5109 qp_init_attr->recv_cq = ibqp->recv_cq; 5110 qp_init_attr->send_cq = ibqp->send_cq; 5111 qp_init_attr->srq = ibqp->srq; 5112 qp_attr->cap.max_inline_data = qp->max_inline_data; 5113 5114 qp_init_attr->cap = qp_attr->cap; 5115 5116 qp_init_attr->create_flags = 0; 5117 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5118 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5119 5120 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5121 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5122 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5123 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5124 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5125 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5126 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5127 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5128 5129 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5130 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5131 5132 out: 5133 mutex_unlock(&qp->mutex); 5134 return err; 5135 } 5136 5137 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5138 struct ib_ucontext *context, 5139 struct ib_udata *udata) 5140 { 5141 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5142 struct mlx5_ib_xrcd *xrcd; 5143 int err; 5144 5145 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5146 return ERR_PTR(-ENOSYS); 5147 5148 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5149 if (!xrcd) 5150 return ERR_PTR(-ENOMEM); 5151 5152 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 5153 if (err) { 5154 kfree(xrcd); 5155 return ERR_PTR(-ENOMEM); 5156 } 5157 5158 return &xrcd->ibxrcd; 5159 } 5160 5161 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5162 { 5163 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5164 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5165 int err; 5166 5167 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 5168 if (err) 5169 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5170 5171 kfree(xrcd); 5172 return 0; 5173 } 5174 5175 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5176 { 5177 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5178 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5179 struct ib_event event; 5180 5181 if (rwq->ibwq.event_handler) { 5182 event.device = rwq->ibwq.device; 5183 event.element.wq = &rwq->ibwq; 5184 switch (type) { 5185 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5186 event.event = IB_EVENT_WQ_FATAL; 5187 break; 5188 default: 5189 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5190 return; 5191 } 5192 5193 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5194 } 5195 } 5196 5197 static int set_delay_drop(struct mlx5_ib_dev *dev) 5198 { 5199 int err = 0; 5200 5201 mutex_lock(&dev->delay_drop.lock); 5202 if (dev->delay_drop.activate) 5203 goto out; 5204 5205 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5206 if (err) 5207 goto out; 5208 5209 dev->delay_drop.activate = true; 5210 out: 5211 mutex_unlock(&dev->delay_drop.lock); 5212 5213 if (!err) 5214 atomic_inc(&dev->delay_drop.rqs_cnt); 5215 return err; 5216 } 5217 5218 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5219 struct ib_wq_init_attr *init_attr) 5220 { 5221 struct mlx5_ib_dev *dev; 5222 int has_net_offloads; 5223 __be64 *rq_pas0; 5224 void *in; 5225 void *rqc; 5226 void *wq; 5227 int inlen; 5228 int err; 5229 5230 dev = to_mdev(pd->device); 5231 5232 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5233 in = kvzalloc(inlen, GFP_KERNEL); 5234 if (!in) 5235 return -ENOMEM; 5236 5237 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5238 MLX5_SET(rqc, rqc, mem_rq_type, 5239 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5240 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5241 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5242 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5243 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5244 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5245 MLX5_SET(wq, wq, wq_type, 5246 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5247 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5248 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5249 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5250 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5251 err = -EOPNOTSUPP; 5252 goto out; 5253 } else { 5254 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5255 } 5256 } 5257 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5258 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5259 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5260 MLX5_SET(wq, wq, log_wqe_stride_size, 5261 rwq->single_stride_log_num_of_bytes - 5262 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5263 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5264 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5265 } 5266 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5267 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5268 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5269 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5270 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5271 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5272 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5273 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5274 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5275 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5276 err = -EOPNOTSUPP; 5277 goto out; 5278 } 5279 } else { 5280 MLX5_SET(rqc, rqc, vsd, 1); 5281 } 5282 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5283 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5284 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5285 err = -EOPNOTSUPP; 5286 goto out; 5287 } 5288 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5289 } 5290 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5291 if (!(dev->ib_dev.attrs.raw_packet_caps & 5292 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5293 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5294 err = -EOPNOTSUPP; 5295 goto out; 5296 } 5297 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5298 } 5299 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5300 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5301 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5302 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5303 err = set_delay_drop(dev); 5304 if (err) { 5305 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5306 err); 5307 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5308 } else { 5309 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5310 } 5311 } 5312 out: 5313 kvfree(in); 5314 return err; 5315 } 5316 5317 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5318 struct ib_wq_init_attr *wq_init_attr, 5319 struct mlx5_ib_create_wq *ucmd, 5320 struct mlx5_ib_rwq *rwq) 5321 { 5322 /* Sanity check RQ size before proceeding */ 5323 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5324 return -EINVAL; 5325 5326 if (!ucmd->rq_wqe_count) 5327 return -EINVAL; 5328 5329 rwq->wqe_count = ucmd->rq_wqe_count; 5330 rwq->wqe_shift = ucmd->rq_wqe_shift; 5331 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 5332 rwq->log_rq_stride = rwq->wqe_shift; 5333 rwq->log_rq_size = ilog2(rwq->wqe_count); 5334 return 0; 5335 } 5336 5337 static int prepare_user_rq(struct ib_pd *pd, 5338 struct ib_wq_init_attr *init_attr, 5339 struct ib_udata *udata, 5340 struct mlx5_ib_rwq *rwq) 5341 { 5342 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5343 struct mlx5_ib_create_wq ucmd = {}; 5344 int err; 5345 size_t required_cmd_sz; 5346 5347 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5348 + sizeof(ucmd.single_stride_log_num_of_bytes); 5349 if (udata->inlen < required_cmd_sz) { 5350 mlx5_ib_dbg(dev, "invalid inlen\n"); 5351 return -EINVAL; 5352 } 5353 5354 if (udata->inlen > sizeof(ucmd) && 5355 !ib_is_udata_cleared(udata, sizeof(ucmd), 5356 udata->inlen - sizeof(ucmd))) { 5357 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5358 return -EOPNOTSUPP; 5359 } 5360 5361 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5362 mlx5_ib_dbg(dev, "copy failed\n"); 5363 return -EFAULT; 5364 } 5365 5366 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5367 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5368 return -EOPNOTSUPP; 5369 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5370 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5371 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5372 return -EOPNOTSUPP; 5373 } 5374 if ((ucmd.single_stride_log_num_of_bytes < 5375 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5376 (ucmd.single_stride_log_num_of_bytes > 5377 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5378 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5379 ucmd.single_stride_log_num_of_bytes, 5380 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5381 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5382 return -EINVAL; 5383 } 5384 if ((ucmd.single_wqe_log_num_of_strides > 5385 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5386 (ucmd.single_wqe_log_num_of_strides < 5387 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5388 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5389 ucmd.single_wqe_log_num_of_strides, 5390 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5391 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5392 return -EINVAL; 5393 } 5394 rwq->single_stride_log_num_of_bytes = 5395 ucmd.single_stride_log_num_of_bytes; 5396 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5397 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5398 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5399 } 5400 5401 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5402 if (err) { 5403 mlx5_ib_dbg(dev, "err %d\n", err); 5404 return err; 5405 } 5406 5407 err = create_user_rq(dev, pd, rwq, &ucmd); 5408 if (err) { 5409 mlx5_ib_dbg(dev, "err %d\n", err); 5410 if (err) 5411 return err; 5412 } 5413 5414 rwq->user_index = ucmd.user_index; 5415 return 0; 5416 } 5417 5418 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5419 struct ib_wq_init_attr *init_attr, 5420 struct ib_udata *udata) 5421 { 5422 struct mlx5_ib_dev *dev; 5423 struct mlx5_ib_rwq *rwq; 5424 struct mlx5_ib_create_wq_resp resp = {}; 5425 size_t min_resp_len; 5426 int err; 5427 5428 if (!udata) 5429 return ERR_PTR(-ENOSYS); 5430 5431 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5432 if (udata->outlen && udata->outlen < min_resp_len) 5433 return ERR_PTR(-EINVAL); 5434 5435 dev = to_mdev(pd->device); 5436 switch (init_attr->wq_type) { 5437 case IB_WQT_RQ: 5438 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5439 if (!rwq) 5440 return ERR_PTR(-ENOMEM); 5441 err = prepare_user_rq(pd, init_attr, udata, rwq); 5442 if (err) 5443 goto err; 5444 err = create_rq(rwq, pd, init_attr); 5445 if (err) 5446 goto err_user_rq; 5447 break; 5448 default: 5449 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5450 init_attr->wq_type); 5451 return ERR_PTR(-EINVAL); 5452 } 5453 5454 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5455 rwq->ibwq.state = IB_WQS_RESET; 5456 if (udata->outlen) { 5457 resp.response_length = offsetof(typeof(resp), response_length) + 5458 sizeof(resp.response_length); 5459 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5460 if (err) 5461 goto err_copy; 5462 } 5463 5464 rwq->core_qp.event = mlx5_ib_wq_event; 5465 rwq->ibwq.event_handler = init_attr->event_handler; 5466 return &rwq->ibwq; 5467 5468 err_copy: 5469 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5470 err_user_rq: 5471 destroy_user_rq(dev, pd, rwq); 5472 err: 5473 kfree(rwq); 5474 return ERR_PTR(err); 5475 } 5476 5477 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5478 { 5479 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5480 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5481 5482 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5483 destroy_user_rq(dev, wq->pd, rwq); 5484 kfree(rwq); 5485 5486 return 0; 5487 } 5488 5489 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5490 struct ib_rwq_ind_table_init_attr *init_attr, 5491 struct ib_udata *udata) 5492 { 5493 struct mlx5_ib_dev *dev = to_mdev(device); 5494 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5495 int sz = 1 << init_attr->log_ind_tbl_size; 5496 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5497 size_t min_resp_len; 5498 int inlen; 5499 int err; 5500 int i; 5501 u32 *in; 5502 void *rqtc; 5503 5504 if (udata->inlen > 0 && 5505 !ib_is_udata_cleared(udata, 0, 5506 udata->inlen)) 5507 return ERR_PTR(-EOPNOTSUPP); 5508 5509 if (init_attr->log_ind_tbl_size > 5510 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5511 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5512 init_attr->log_ind_tbl_size, 5513 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5514 return ERR_PTR(-EINVAL); 5515 } 5516 5517 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5518 if (udata->outlen && udata->outlen < min_resp_len) 5519 return ERR_PTR(-EINVAL); 5520 5521 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5522 if (!rwq_ind_tbl) 5523 return ERR_PTR(-ENOMEM); 5524 5525 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5526 in = kvzalloc(inlen, GFP_KERNEL); 5527 if (!in) { 5528 err = -ENOMEM; 5529 goto err; 5530 } 5531 5532 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5533 5534 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5535 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5536 5537 for (i = 0; i < sz; i++) 5538 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5539 5540 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5541 kvfree(in); 5542 5543 if (err) 5544 goto err; 5545 5546 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5547 if (udata->outlen) { 5548 resp.response_length = offsetof(typeof(resp), response_length) + 5549 sizeof(resp.response_length); 5550 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5551 if (err) 5552 goto err_copy; 5553 } 5554 5555 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5556 5557 err_copy: 5558 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5559 err: 5560 kfree(rwq_ind_tbl); 5561 return ERR_PTR(err); 5562 } 5563 5564 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5565 { 5566 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5567 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5568 5569 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5570 5571 kfree(rwq_ind_tbl); 5572 return 0; 5573 } 5574 5575 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5576 u32 wq_attr_mask, struct ib_udata *udata) 5577 { 5578 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5579 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5580 struct mlx5_ib_modify_wq ucmd = {}; 5581 size_t required_cmd_sz; 5582 int curr_wq_state; 5583 int wq_state; 5584 int inlen; 5585 int err; 5586 void *rqc; 5587 void *in; 5588 5589 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5590 if (udata->inlen < required_cmd_sz) 5591 return -EINVAL; 5592 5593 if (udata->inlen > sizeof(ucmd) && 5594 !ib_is_udata_cleared(udata, sizeof(ucmd), 5595 udata->inlen - sizeof(ucmd))) 5596 return -EOPNOTSUPP; 5597 5598 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5599 return -EFAULT; 5600 5601 if (ucmd.comp_mask || ucmd.reserved) 5602 return -EOPNOTSUPP; 5603 5604 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5605 in = kvzalloc(inlen, GFP_KERNEL); 5606 if (!in) 5607 return -ENOMEM; 5608 5609 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5610 5611 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5612 wq_attr->curr_wq_state : wq->state; 5613 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5614 wq_attr->wq_state : curr_wq_state; 5615 if (curr_wq_state == IB_WQS_ERR) 5616 curr_wq_state = MLX5_RQC_STATE_ERR; 5617 if (wq_state == IB_WQS_ERR) 5618 wq_state = MLX5_RQC_STATE_ERR; 5619 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5620 MLX5_SET(rqc, rqc, state, wq_state); 5621 5622 if (wq_attr_mask & IB_WQ_FLAGS) { 5623 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5624 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5625 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5626 mlx5_ib_dbg(dev, "VLAN offloads are not " 5627 "supported\n"); 5628 err = -EOPNOTSUPP; 5629 goto out; 5630 } 5631 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5632 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5633 MLX5_SET(rqc, rqc, vsd, 5634 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5635 } 5636 5637 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5638 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5639 err = -EOPNOTSUPP; 5640 goto out; 5641 } 5642 } 5643 5644 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5645 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5646 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5647 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5648 MLX5_SET(rqc, rqc, counter_set_id, 5649 dev->port->cnts.set_id); 5650 } else 5651 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5652 dev->ib_dev.name); 5653 } 5654 5655 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5656 if (!err) 5657 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5658 5659 out: 5660 kvfree(in); 5661 return err; 5662 } 5663