1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "qp.h" 44 #include "wr.h" 45 46 enum { 47 MLX5_IB_ACK_REQ_FREQ = 8, 48 }; 49 50 enum { 51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 53 MLX5_IB_LINK_TYPE_IB = 0, 54 MLX5_IB_LINK_TYPE_ETH = 1 55 }; 56 57 enum raw_qp_set_mask_map { 58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 60 }; 61 62 struct mlx5_modify_raw_qp_param { 63 u16 operation; 64 65 u32 set_mask; /* raw_qp_set_mask_map */ 66 67 struct mlx5_rate_limit rl; 68 69 u8 rq_q_ctr_id; 70 u16 port; 71 }; 72 73 static void get_cqs(enum ib_qp_type qp_type, 74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 76 77 static int is_qp0(enum ib_qp_type qp_type) 78 { 79 return qp_type == IB_QPT_SMI; 80 } 81 82 static int is_sqp(enum ib_qp_type qp_type) 83 { 84 return is_qp0(qp_type) || is_qp1(qp_type); 85 } 86 87 /** 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 89 * to kernel buffer 90 * 91 * @umem: User space memory where the WQ is 92 * @buffer: buffer to copy to 93 * @buflen: buffer length 94 * @wqe_index: index of WQE to copy from 95 * @wq_offset: offset to start of WQ 96 * @wq_wqe_cnt: number of WQEs in WQ 97 * @wq_wqe_shift: log2 of WQE size 98 * @bcnt: number of bytes to copy 99 * @bytes_copied: number of bytes to copy (return value) 100 * 101 * Copies from start of WQE bcnt or less bytes. 102 * Does not gurantee to copy the entire WQE. 103 * 104 * Return: zero on success, or an error code. 105 */ 106 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 107 size_t buflen, int wqe_index, 108 int wq_offset, int wq_wqe_cnt, 109 int wq_wqe_shift, int bcnt, 110 size_t *bytes_copied) 111 { 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 114 size_t copy_length; 115 int ret; 116 117 /* don't copy more than requested, more than buffer length or 118 * beyond WQ end 119 */ 120 copy_length = min_t(u32, buflen, wq_end - offset); 121 copy_length = min_t(u32, copy_length, bcnt); 122 123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 124 if (ret) 125 return ret; 126 127 if (!ret && bytes_copied) 128 *bytes_copied = copy_length; 129 130 return 0; 131 } 132 133 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 134 void *buffer, size_t buflen, size_t *bc) 135 { 136 struct mlx5_wqe_ctrl_seg *ctrl; 137 size_t bytes_copied = 0; 138 size_t wqe_length; 139 void *p; 140 int ds; 141 142 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 143 144 /* read the control segment first */ 145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 146 ctrl = p; 147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 148 wqe_length = ds * MLX5_WQE_DS_UNITS; 149 150 /* read rest of WQE if it spreads over more than one stride */ 151 while (bytes_copied < wqe_length) { 152 size_t copy_length = 153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 154 155 if (!copy_length) 156 break; 157 158 memcpy(buffer + bytes_copied, p, copy_length); 159 bytes_copied += copy_length; 160 161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 163 } 164 *bc = bytes_copied; 165 return 0; 166 } 167 168 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 169 void *buffer, size_t buflen, size_t *bc) 170 { 171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 172 struct ib_umem *umem = base->ubuffer.umem; 173 struct mlx5_ib_wq *wq = &qp->sq; 174 struct mlx5_wqe_ctrl_seg *ctrl; 175 size_t bytes_copied; 176 size_t bytes_copied2; 177 size_t wqe_length; 178 int ret; 179 int ds; 180 181 /* at first read as much as possible */ 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 183 wq->offset, wq->wqe_cnt, 184 wq->wqe_shift, buflen, 185 &bytes_copied); 186 if (ret) 187 return ret; 188 189 /* we need at least control segment size to proceed */ 190 if (bytes_copied < sizeof(*ctrl)) 191 return -EINVAL; 192 193 ctrl = buffer; 194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 195 wqe_length = ds * MLX5_WQE_DS_UNITS; 196 197 /* if we copied enough then we are done */ 198 if (bytes_copied >= wqe_length) { 199 *bc = bytes_copied; 200 return 0; 201 } 202 203 /* otherwise this a wrapped around wqe 204 * so read the remaining bytes starting 205 * from wqe_index 0 206 */ 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 208 buflen - bytes_copied, 0, wq->offset, 209 wq->wqe_cnt, wq->wqe_shift, 210 wqe_length - bytes_copied, 211 &bytes_copied2); 212 213 if (ret) 214 return ret; 215 *bc = bytes_copied + bytes_copied2; 216 return 0; 217 } 218 219 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 220 size_t buflen, size_t *bc) 221 { 222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 223 struct ib_umem *umem = base->ubuffer.umem; 224 225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 226 return -EINVAL; 227 228 if (!umem) 229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 230 buflen, bc); 231 232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 233 } 234 235 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 236 void *buffer, size_t buflen, size_t *bc) 237 { 238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 239 struct ib_umem *umem = base->ubuffer.umem; 240 struct mlx5_ib_wq *wq = &qp->rq; 241 size_t bytes_copied; 242 int ret; 243 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 245 wq->offset, wq->wqe_cnt, 246 wq->wqe_shift, buflen, 247 &bytes_copied); 248 249 if (ret) 250 return ret; 251 *bc = bytes_copied; 252 return 0; 253 } 254 255 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 256 size_t buflen, size_t *bc) 257 { 258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 259 struct ib_umem *umem = base->ubuffer.umem; 260 struct mlx5_ib_wq *wq = &qp->rq; 261 size_t wqe_size = 1 << wq->wqe_shift; 262 263 if (buflen < wqe_size) 264 return -EINVAL; 265 266 if (!umem) 267 return -EOPNOTSUPP; 268 269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 270 } 271 272 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 273 void *buffer, size_t buflen, size_t *bc) 274 { 275 struct ib_umem *umem = srq->umem; 276 size_t bytes_copied; 277 int ret; 278 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 280 srq->msrq.max, srq->msrq.wqe_shift, 281 buflen, &bytes_copied); 282 283 if (ret) 284 return ret; 285 *bc = bytes_copied; 286 return 0; 287 } 288 289 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 290 size_t buflen, size_t *bc) 291 { 292 struct ib_umem *umem = srq->umem; 293 size_t wqe_size = 1 << srq->msrq.wqe_shift; 294 295 if (buflen < wqe_size) 296 return -EINVAL; 297 298 if (!umem) 299 return -EOPNOTSUPP; 300 301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 302 } 303 304 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 305 { 306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 307 struct ib_event event; 308 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 310 /* This event is only valid for trans_qps */ 311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 312 } 313 314 if (ibqp->event_handler) { 315 event.device = ibqp->device; 316 event.element.qp = ibqp; 317 switch (type) { 318 case MLX5_EVENT_TYPE_PATH_MIG: 319 event.event = IB_EVENT_PATH_MIG; 320 break; 321 case MLX5_EVENT_TYPE_COMM_EST: 322 event.event = IB_EVENT_COMM_EST; 323 break; 324 case MLX5_EVENT_TYPE_SQ_DRAINED: 325 event.event = IB_EVENT_SQ_DRAINED; 326 break; 327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 328 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 329 break; 330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 331 event.event = IB_EVENT_QP_FATAL; 332 break; 333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 334 event.event = IB_EVENT_PATH_MIG_ERR; 335 break; 336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 337 event.event = IB_EVENT_QP_REQ_ERR; 338 break; 339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 340 event.event = IB_EVENT_QP_ACCESS_ERR; 341 break; 342 default: 343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 344 return; 345 } 346 347 ibqp->event_handler(&event, ibqp->qp_context); 348 } 349 } 350 351 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 353 { 354 int wqe_size; 355 int wq_size; 356 357 /* Sanity check RQ size before proceeding */ 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 359 return -EINVAL; 360 361 if (!has_rq) { 362 qp->rq.max_gs = 0; 363 qp->rq.wqe_cnt = 0; 364 qp->rq.wqe_shift = 0; 365 cap->max_recv_wr = 0; 366 cap->max_recv_sge = 0; 367 } else { 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 369 370 if (ucmd) { 371 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 373 return -EINVAL; 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 375 if ((1 << qp->rq.wqe_shift) / 376 sizeof(struct mlx5_wqe_data_seg) < 377 wq_sig) 378 return -EINVAL; 379 qp->rq.max_gs = 380 (1 << qp->rq.wqe_shift) / 381 sizeof(struct mlx5_wqe_data_seg) - 382 wq_sig; 383 qp->rq.max_post = qp->rq.wqe_cnt; 384 } else { 385 wqe_size = 386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 387 0; 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 389 wqe_size = roundup_pow_of_two(wqe_size); 390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 392 qp->rq.wqe_cnt = wq_size / wqe_size; 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 395 wqe_size, 396 MLX5_CAP_GEN(dev->mdev, 397 max_wqe_sz_rq)); 398 return -EINVAL; 399 } 400 qp->rq.wqe_shift = ilog2(wqe_size); 401 qp->rq.max_gs = 402 (1 << qp->rq.wqe_shift) / 403 sizeof(struct mlx5_wqe_data_seg) - 404 wq_sig; 405 qp->rq.max_post = qp->rq.wqe_cnt; 406 } 407 } 408 409 return 0; 410 } 411 412 static int sq_overhead(struct ib_qp_init_attr *attr) 413 { 414 int size = 0; 415 416 switch (attr->qp_type) { 417 case IB_QPT_XRC_INI: 418 size += sizeof(struct mlx5_wqe_xrc_seg); 419 fallthrough; 420 case IB_QPT_RC: 421 size += sizeof(struct mlx5_wqe_ctrl_seg) + 422 max(sizeof(struct mlx5_wqe_atomic_seg) + 423 sizeof(struct mlx5_wqe_raddr_seg), 424 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 425 sizeof(struct mlx5_mkey_seg) + 426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 427 MLX5_IB_UMR_OCTOWORD); 428 break; 429 430 case IB_QPT_XRC_TGT: 431 return 0; 432 433 case IB_QPT_UC: 434 size += sizeof(struct mlx5_wqe_ctrl_seg) + 435 max(sizeof(struct mlx5_wqe_raddr_seg), 436 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 437 sizeof(struct mlx5_mkey_seg)); 438 break; 439 440 case IB_QPT_UD: 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 442 size += sizeof(struct mlx5_wqe_eth_pad) + 443 sizeof(struct mlx5_wqe_eth_seg); 444 fallthrough; 445 case IB_QPT_SMI: 446 case MLX5_IB_QPT_HW_GSI: 447 size += sizeof(struct mlx5_wqe_ctrl_seg) + 448 sizeof(struct mlx5_wqe_datagram_seg); 449 break; 450 451 case MLX5_IB_QPT_REG_UMR: 452 size += sizeof(struct mlx5_wqe_ctrl_seg) + 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 454 sizeof(struct mlx5_mkey_seg); 455 break; 456 457 default: 458 return -EINVAL; 459 } 460 461 return size; 462 } 463 464 static int calc_send_wqe(struct ib_qp_init_attr *attr) 465 { 466 int inl_size = 0; 467 int size; 468 469 size = sq_overhead(attr); 470 if (size < 0) 471 return size; 472 473 if (attr->cap.max_inline_data) { 474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 475 attr->cap.max_inline_data; 476 } 477 478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 481 return MLX5_SIG_WQE_SIZE; 482 else 483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 484 } 485 486 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 487 { 488 int max_sge; 489 490 if (attr->qp_type == IB_QPT_RC) 491 max_sge = (min_t(int, wqe_size, 512) - 492 sizeof(struct mlx5_wqe_ctrl_seg) - 493 sizeof(struct mlx5_wqe_raddr_seg)) / 494 sizeof(struct mlx5_wqe_data_seg); 495 else if (attr->qp_type == IB_QPT_XRC_INI) 496 max_sge = (min_t(int, wqe_size, 512) - 497 sizeof(struct mlx5_wqe_ctrl_seg) - 498 sizeof(struct mlx5_wqe_xrc_seg) - 499 sizeof(struct mlx5_wqe_raddr_seg)) / 500 sizeof(struct mlx5_wqe_data_seg); 501 else 502 max_sge = (wqe_size - sq_overhead(attr)) / 503 sizeof(struct mlx5_wqe_data_seg); 504 505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 506 sizeof(struct mlx5_wqe_data_seg)); 507 } 508 509 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 510 struct mlx5_ib_qp *qp) 511 { 512 int wqe_size; 513 int wq_size; 514 515 if (!attr->cap.max_send_wr) 516 return 0; 517 518 wqe_size = calc_send_wqe(attr); 519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 520 if (wqe_size < 0) 521 return wqe_size; 522 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 526 return -EINVAL; 527 } 528 529 qp->max_inline_data = wqe_size - sq_overhead(attr) - 530 sizeof(struct mlx5_wqe_inline_seg); 531 attr->cap.max_inline_data = qp->max_inline_data; 532 533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 538 qp->sq.wqe_cnt, 539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 540 return -ENOMEM; 541 } 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 543 qp->sq.max_gs = get_send_sge(attr, wqe_size); 544 if (qp->sq.max_gs < attr->cap.max_send_sge) 545 return -ENOMEM; 546 547 attr->cap.max_send_sge = qp->sq.max_gs; 548 qp->sq.max_post = wq_size / wqe_size; 549 attr->cap.max_send_wr = qp->sq.max_post; 550 551 return wq_size; 552 } 553 554 static int set_user_buf_size(struct mlx5_ib_dev *dev, 555 struct mlx5_ib_qp *qp, 556 struct mlx5_ib_create_qp *ucmd, 557 struct mlx5_ib_qp_base *base, 558 struct ib_qp_init_attr *attr) 559 { 560 int desc_sz = 1 << qp->sq.wqe_shift; 561 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 565 return -EINVAL; 566 } 567 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 570 ucmd->sq_wqe_count); 571 return -EINVAL; 572 } 573 574 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 575 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 578 qp->sq.wqe_cnt, 579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 580 return -EINVAL; 581 } 582 583 if (attr->qp_type == IB_QPT_RAW_PACKET || 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 587 } else { 588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 589 (qp->sq.wqe_cnt << 6); 590 } 591 592 return 0; 593 } 594 595 static int qp_has_rq(struct ib_qp_init_attr *attr) 596 { 597 if (attr->qp_type == IB_QPT_XRC_INI || 598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 599 attr->qp_type == MLX5_IB_QPT_REG_UMR || 600 !attr->cap.max_recv_wr) 601 return 0; 602 603 return 1; 604 } 605 606 enum { 607 /* this is the first blue flame register in the array of bfregs assigned 608 * to a processes. Since we do not use it for blue flame but rather 609 * regular 64 bit doorbells, we do not need a lock for maintaiing 610 * "odd/even" order 611 */ 612 NUM_NON_BLUE_FLAME_BFREGS = 1, 613 }; 614 615 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 616 { 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 618 } 619 620 static int num_med_bfreg(struct mlx5_ib_dev *dev, 621 struct mlx5_bfreg_info *bfregi) 622 { 623 int n; 624 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 626 NUM_NON_BLUE_FLAME_BFREGS; 627 628 return n >= 0 ? n : 0; 629 } 630 631 static int first_med_bfreg(struct mlx5_ib_dev *dev, 632 struct mlx5_bfreg_info *bfregi) 633 { 634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 635 } 636 637 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 638 struct mlx5_bfreg_info *bfregi) 639 { 640 int med; 641 642 med = num_med_bfreg(dev, bfregi); 643 return ++med; 644 } 645 646 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 647 struct mlx5_bfreg_info *bfregi) 648 { 649 int i; 650 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 652 if (!bfregi->count[i]) { 653 bfregi->count[i]++; 654 return i; 655 } 656 } 657 658 return -ENOMEM; 659 } 660 661 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 662 struct mlx5_bfreg_info *bfregi) 663 { 664 int minidx = first_med_bfreg(dev, bfregi); 665 int i; 666 667 if (minidx < 0) 668 return minidx; 669 670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 671 if (bfregi->count[i] < bfregi->count[minidx]) 672 minidx = i; 673 if (!bfregi->count[minidx]) 674 break; 675 } 676 677 bfregi->count[minidx]++; 678 return minidx; 679 } 680 681 static int alloc_bfreg(struct mlx5_ib_dev *dev, 682 struct mlx5_bfreg_info *bfregi) 683 { 684 int bfregn = -ENOMEM; 685 686 if (bfregi->lib_uar_dyn) 687 return -EINVAL; 688 689 mutex_lock(&bfregi->lock); 690 if (bfregi->ver >= 2) { 691 bfregn = alloc_high_class_bfreg(dev, bfregi); 692 if (bfregn < 0) 693 bfregn = alloc_med_class_bfreg(dev, bfregi); 694 } 695 696 if (bfregn < 0) { 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 698 bfregn = 0; 699 bfregi->count[bfregn]++; 700 } 701 mutex_unlock(&bfregi->lock); 702 703 return bfregn; 704 } 705 706 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 707 { 708 mutex_lock(&bfregi->lock); 709 bfregi->count[bfregn]--; 710 mutex_unlock(&bfregi->lock); 711 } 712 713 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 714 { 715 switch (state) { 716 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 723 default: return -1; 724 } 725 } 726 727 static int to_mlx5_st(enum ib_qp_type type) 728 { 729 switch (type) { 730 case IB_QPT_RC: return MLX5_QP_ST_RC; 731 case IB_QPT_UC: return MLX5_QP_ST_UC; 732 case IB_QPT_UD: return MLX5_QP_ST_UD; 733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 734 case IB_QPT_XRC_INI: 735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 736 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 740 default: return -EINVAL; 741 } 742 } 743 744 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 745 struct mlx5_ib_cq *recv_cq); 746 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 747 struct mlx5_ib_cq *recv_cq); 748 749 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, u32 bfregn, 751 bool dyn_bfreg) 752 { 753 unsigned int bfregs_per_sys_page; 754 u32 index_of_sys_page; 755 u32 offset; 756 757 if (bfregi->lib_uar_dyn) 758 return -EINVAL; 759 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 761 MLX5_NON_FP_BFREGS_PER_UAR; 762 index_of_sys_page = bfregn / bfregs_per_sys_page; 763 764 if (dyn_bfreg) { 765 index_of_sys_page += bfregi->num_static_sys_pages; 766 767 if (index_of_sys_page >= bfregi->num_sys_pages) 768 return -EINVAL; 769 770 if (bfregn > bfregi->num_dyn_bfregs || 771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 773 return -EINVAL; 774 } 775 } 776 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 778 return bfregi->sys_pages[index_of_sys_page] + offset; 779 } 780 781 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 782 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 783 { 784 struct mlx5_ib_ucontext *context = 785 rdma_udata_to_drv_context( 786 udata, 787 struct mlx5_ib_ucontext, 788 ibucontext); 789 790 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 791 atomic_dec(&dev->delay_drop.rqs_cnt); 792 793 mlx5_ib_db_unmap_user(context, &rwq->db); 794 ib_umem_release(rwq->umem); 795 } 796 797 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 798 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 799 struct mlx5_ib_create_wq *ucmd) 800 { 801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 802 udata, struct mlx5_ib_ucontext, ibucontext); 803 unsigned long page_size = 0; 804 u32 offset = 0; 805 int err; 806 807 if (!ucmd->buf_addr) 808 return -EINVAL; 809 810 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 811 if (IS_ERR(rwq->umem)) { 812 mlx5_ib_dbg(dev, "umem_get failed\n"); 813 err = PTR_ERR(rwq->umem); 814 return err; 815 } 816 817 page_size = mlx5_umem_find_best_quantized_pgoff( 818 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 819 page_offset, 64, &rwq->rq_page_offset); 820 if (!page_size) { 821 mlx5_ib_warn(dev, "bad offset\n"); 822 err = -EINVAL; 823 goto err_umem; 824 } 825 826 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 827 rwq->page_shift = order_base_2(page_size); 828 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 829 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 830 831 mlx5_ib_dbg( 832 dev, 833 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 834 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 835 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 836 offset); 837 838 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 839 if (err) { 840 mlx5_ib_dbg(dev, "map failed\n"); 841 goto err_umem; 842 } 843 844 return 0; 845 846 err_umem: 847 ib_umem_release(rwq->umem); 848 return err; 849 } 850 851 static int adjust_bfregn(struct mlx5_ib_dev *dev, 852 struct mlx5_bfreg_info *bfregi, int bfregn) 853 { 854 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 855 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 856 } 857 858 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 859 struct mlx5_ib_qp *qp, struct ib_udata *udata, 860 struct ib_qp_init_attr *attr, u32 **in, 861 struct mlx5_ib_create_qp_resp *resp, int *inlen, 862 struct mlx5_ib_qp_base *base, 863 struct mlx5_ib_create_qp *ucmd) 864 { 865 struct mlx5_ib_ucontext *context; 866 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 867 unsigned int page_offset_quantized = 0; 868 unsigned long page_size = 0; 869 int uar_index = 0; 870 int bfregn; 871 int ncont = 0; 872 __be64 *pas; 873 void *qpc; 874 int err; 875 u16 uid; 876 u32 uar_flags; 877 878 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 879 ibucontext); 880 uar_flags = qp->flags_en & 881 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 882 switch (uar_flags) { 883 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 884 uar_index = ucmd->bfreg_index; 885 bfregn = MLX5_IB_INVALID_BFREG; 886 break; 887 case MLX5_QP_FLAG_BFREG_INDEX: 888 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 889 ucmd->bfreg_index, true); 890 if (uar_index < 0) 891 return uar_index; 892 bfregn = MLX5_IB_INVALID_BFREG; 893 break; 894 case 0: 895 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 896 return -EINVAL; 897 bfregn = alloc_bfreg(dev, &context->bfregi); 898 if (bfregn < 0) 899 return bfregn; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 906 if (bfregn != MLX5_IB_INVALID_BFREG) 907 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 908 false); 909 910 qp->rq.offset = 0; 911 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 912 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 913 914 err = set_user_buf_size(dev, qp, ucmd, base, attr); 915 if (err) 916 goto err_bfreg; 917 918 if (ucmd->buf_addr && ubuffer->buf_size) { 919 ubuffer->buf_addr = ucmd->buf_addr; 920 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 921 ubuffer->buf_size, 0); 922 if (IS_ERR(ubuffer->umem)) { 923 err = PTR_ERR(ubuffer->umem); 924 goto err_bfreg; 925 } 926 page_size = mlx5_umem_find_best_quantized_pgoff( 927 ubuffer->umem, qpc, log_page_size, 928 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 929 &page_offset_quantized); 930 if (!page_size) { 931 err = -EINVAL; 932 goto err_umem; 933 } 934 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 935 } else { 936 ubuffer->umem = NULL; 937 } 938 939 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 940 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 941 *in = kvzalloc(*inlen, GFP_KERNEL); 942 if (!*in) { 943 err = -ENOMEM; 944 goto err_umem; 945 } 946 947 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 948 MLX5_SET(create_qp_in, *in, uid, uid); 949 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 950 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 951 if (ubuffer->umem) { 952 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 953 MLX5_SET(qpc, qpc, log_page_size, 954 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 955 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 956 } 957 MLX5_SET(qpc, qpc, uar_page, uar_index); 958 if (bfregn != MLX5_IB_INVALID_BFREG) 959 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 960 else 961 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 962 qp->bfregn = bfregn; 963 964 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db); 965 if (err) { 966 mlx5_ib_dbg(dev, "map failed\n"); 967 goto err_free; 968 } 969 970 return 0; 971 972 err_free: 973 kvfree(*in); 974 975 err_umem: 976 ib_umem_release(ubuffer->umem); 977 978 err_bfreg: 979 if (bfregn != MLX5_IB_INVALID_BFREG) 980 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 981 return err; 982 } 983 984 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 985 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 986 { 987 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 988 udata, struct mlx5_ib_ucontext, ibucontext); 989 990 if (udata) { 991 /* User QP */ 992 mlx5_ib_db_unmap_user(context, &qp->db); 993 ib_umem_release(base->ubuffer.umem); 994 995 /* 996 * Free only the BFREGs which are handled by the kernel. 997 * BFREGs of UARs allocated dynamically are handled by user. 998 */ 999 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1000 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1001 return; 1002 } 1003 1004 /* Kernel QP */ 1005 kvfree(qp->sq.wqe_head); 1006 kvfree(qp->sq.w_list); 1007 kvfree(qp->sq.wrid); 1008 kvfree(qp->sq.wr_data); 1009 kvfree(qp->rq.wrid); 1010 if (qp->db.db) 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 if (qp->buf.frags) 1013 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1014 } 1015 1016 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1017 struct ib_qp_init_attr *init_attr, 1018 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1019 struct mlx5_ib_qp_base *base) 1020 { 1021 int uar_index; 1022 void *qpc; 1023 int err; 1024 1025 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1026 qp->bf.bfreg = &dev->fp_bfreg; 1027 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1028 qp->bf.bfreg = &dev->wc_bfreg; 1029 else 1030 qp->bf.bfreg = &dev->bfreg; 1031 1032 /* We need to divide by two since each register is comprised of 1033 * two buffers of identical size, namely odd and even 1034 */ 1035 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1036 uar_index = qp->bf.bfreg->index; 1037 1038 err = calc_sq_size(dev, init_attr, qp); 1039 if (err < 0) { 1040 mlx5_ib_dbg(dev, "err %d\n", err); 1041 return err; 1042 } 1043 1044 qp->rq.offset = 0; 1045 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1046 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1047 1048 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1049 &qp->buf, dev->mdev->priv.numa_node); 1050 if (err) { 1051 mlx5_ib_dbg(dev, "err %d\n", err); 1052 return err; 1053 } 1054 1055 if (qp->rq.wqe_cnt) 1056 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1057 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1058 1059 if (qp->sq.wqe_cnt) { 1060 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1061 MLX5_SEND_WQE_BB; 1062 mlx5_init_fbc_offset(qp->buf.frags + 1063 (qp->sq.offset / PAGE_SIZE), 1064 ilog2(MLX5_SEND_WQE_BB), 1065 ilog2(qp->sq.wqe_cnt), 1066 sq_strides_offset, &qp->sq.fbc); 1067 1068 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1069 } 1070 1071 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1072 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1073 *in = kvzalloc(*inlen, GFP_KERNEL); 1074 if (!*in) { 1075 err = -ENOMEM; 1076 goto err_buf; 1077 } 1078 1079 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1080 MLX5_SET(qpc, qpc, uar_page, uar_index); 1081 MLX5_SET(qpc, qpc, ts_format, MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT); 1082 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1083 1084 /* Set "fast registration enabled" for all kernel QPs */ 1085 MLX5_SET(qpc, qpc, fre, 1); 1086 MLX5_SET(qpc, qpc, rlky, 1); 1087 1088 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1089 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1090 1091 mlx5_fill_page_frag_array(&qp->buf, 1092 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1093 *in, pas)); 1094 1095 err = mlx5_db_alloc(dev->mdev, &qp->db); 1096 if (err) { 1097 mlx5_ib_dbg(dev, "err %d\n", err); 1098 goto err_free; 1099 } 1100 1101 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1102 sizeof(*qp->sq.wrid), GFP_KERNEL); 1103 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1104 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1105 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1106 sizeof(*qp->rq.wrid), GFP_KERNEL); 1107 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1108 sizeof(*qp->sq.w_list), GFP_KERNEL); 1109 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1110 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1111 1112 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1113 !qp->sq.w_list || !qp->sq.wqe_head) { 1114 err = -ENOMEM; 1115 goto err_wrid; 1116 } 1117 1118 return 0; 1119 1120 err_wrid: 1121 kvfree(qp->sq.wqe_head); 1122 kvfree(qp->sq.w_list); 1123 kvfree(qp->sq.wrid); 1124 kvfree(qp->sq.wr_data); 1125 kvfree(qp->rq.wrid); 1126 mlx5_db_free(dev->mdev, &qp->db); 1127 1128 err_free: 1129 kvfree(*in); 1130 1131 err_buf: 1132 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1133 return err; 1134 } 1135 1136 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1137 { 1138 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1139 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1140 return MLX5_SRQ_RQ; 1141 else if (!qp->has_rq) 1142 return MLX5_ZERO_LEN_RQ; 1143 1144 return MLX5_NON_ZERO_RQ; 1145 } 1146 1147 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1148 struct mlx5_ib_qp *qp, 1149 struct mlx5_ib_sq *sq, u32 tdn, 1150 struct ib_pd *pd) 1151 { 1152 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1153 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1154 1155 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1156 MLX5_SET(tisc, tisc, transport_domain, tdn); 1157 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1158 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1159 1160 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1161 } 1162 1163 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1164 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1165 { 1166 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1167 } 1168 1169 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1170 { 1171 if (sq->flow_rule) 1172 mlx5_del_flow_rules(sq->flow_rule); 1173 sq->flow_rule = NULL; 1174 } 1175 1176 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1177 { 1178 bool fr_supported = 1179 MLX5_CAP_GEN(dev->mdev, rq_ts_format) == 1180 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1181 MLX5_CAP_GEN(dev->mdev, rq_ts_format) == 1182 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1183 1184 if (send_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1185 if (!fr_supported) { 1186 mlx5_ib_dbg(dev, "Free running TS format is not supported\n"); 1187 return -EOPNOTSUPP; 1188 } 1189 return MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING; 1190 } 1191 return MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT; 1192 } 1193 1194 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1195 { 1196 bool fr_supported = 1197 MLX5_CAP_GEN(dev->mdev, sq_ts_format) == 1198 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1199 MLX5_CAP_GEN(dev->mdev, sq_ts_format) == 1200 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1201 1202 if (send_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1203 if (!fr_supported) { 1204 mlx5_ib_dbg(dev, "Free running TS format is not supported\n"); 1205 return -EOPNOTSUPP; 1206 } 1207 return MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING; 1208 } 1209 return MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT; 1210 } 1211 1212 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1213 struct mlx5_ib_cq *recv_cq) 1214 { 1215 bool fr_supported = 1216 MLX5_CAP_ROCE(dev->mdev, qp_ts_format) == 1217 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1218 MLX5_CAP_ROCE(dev->mdev, qp_ts_format) == 1219 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1220 int ts_format = MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 1221 1222 if (recv_cq && 1223 recv_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) 1224 ts_format = MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING; 1225 1226 if (send_cq && 1227 send_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) 1228 ts_format = MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING; 1229 1230 if (ts_format == MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING && 1231 !fr_supported) { 1232 mlx5_ib_dbg(dev, "Free running TS format is not supported\n"); 1233 return -EOPNOTSUPP; 1234 } 1235 return ts_format; 1236 } 1237 1238 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1239 struct ib_udata *udata, 1240 struct mlx5_ib_sq *sq, void *qpin, 1241 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1242 { 1243 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1244 __be64 *pas; 1245 void *in; 1246 void *sqc; 1247 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1248 void *wq; 1249 int inlen; 1250 int err; 1251 unsigned int page_offset_quantized; 1252 unsigned long page_size; 1253 int ts_format; 1254 1255 ts_format = get_sq_ts_format(dev, cq); 1256 if (ts_format < 0) 1257 return ts_format; 1258 1259 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1260 ubuffer->buf_size, 0); 1261 if (IS_ERR(sq->ubuffer.umem)) 1262 return PTR_ERR(sq->ubuffer.umem); 1263 page_size = mlx5_umem_find_best_quantized_pgoff( 1264 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1265 page_offset, 64, &page_offset_quantized); 1266 if (!page_size) { 1267 err = -EINVAL; 1268 goto err_umem; 1269 } 1270 1271 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1272 sizeof(u64) * 1273 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1274 in = kvzalloc(inlen, GFP_KERNEL); 1275 if (!in) { 1276 err = -ENOMEM; 1277 goto err_umem; 1278 } 1279 1280 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1281 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1282 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1283 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1284 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1285 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1286 MLX5_SET(sqc, sqc, ts_format, ts_format); 1287 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1288 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1289 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1290 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1291 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1292 MLX5_CAP_ETH(dev->mdev, swp)) 1293 MLX5_SET(sqc, sqc, allow_swp, 1); 1294 1295 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1296 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1297 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1298 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1299 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1300 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1301 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1302 MLX5_SET(wq, wq, log_wq_pg_sz, 1303 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1304 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1305 1306 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1307 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1308 1309 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1310 1311 kvfree(in); 1312 1313 if (err) 1314 goto err_umem; 1315 1316 return 0; 1317 1318 err_umem: 1319 ib_umem_release(sq->ubuffer.umem); 1320 sq->ubuffer.umem = NULL; 1321 1322 return err; 1323 } 1324 1325 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1326 struct mlx5_ib_sq *sq) 1327 { 1328 destroy_flow_rule_vport_sq(sq); 1329 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1330 ib_umem_release(sq->ubuffer.umem); 1331 } 1332 1333 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1334 struct mlx5_ib_rq *rq, void *qpin, 1335 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1336 { 1337 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1338 __be64 *pas; 1339 void *in; 1340 void *rqc; 1341 void *wq; 1342 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1343 struct ib_umem *umem = rq->base.ubuffer.umem; 1344 unsigned int page_offset_quantized; 1345 unsigned long page_size = 0; 1346 int ts_format; 1347 size_t inlen; 1348 int err; 1349 1350 ts_format = get_rq_ts_format(dev, cq); 1351 if (ts_format < 0) 1352 return ts_format; 1353 1354 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1355 MLX5_ADAPTER_PAGE_SHIFT, 1356 page_offset, 64, 1357 &page_offset_quantized); 1358 if (!page_size) 1359 return -EINVAL; 1360 1361 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1362 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1363 in = kvzalloc(inlen, GFP_KERNEL); 1364 if (!in) 1365 return -ENOMEM; 1366 1367 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1368 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1369 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1370 MLX5_SET(rqc, rqc, vsd, 1); 1371 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1372 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1373 MLX5_SET(rqc, rqc, ts_format, ts_format); 1374 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1375 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1376 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1377 1378 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1379 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1380 1381 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1382 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1383 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1384 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1385 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1386 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1387 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1388 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1389 MLX5_SET(wq, wq, log_wq_pg_sz, 1390 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1391 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1392 1393 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1394 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1395 1396 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1397 1398 kvfree(in); 1399 1400 return err; 1401 } 1402 1403 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1404 struct mlx5_ib_rq *rq) 1405 { 1406 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1407 } 1408 1409 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1410 struct mlx5_ib_rq *rq, 1411 u32 qp_flags_en, 1412 struct ib_pd *pd) 1413 { 1414 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1415 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1416 mlx5_ib_disable_lb(dev, false, true); 1417 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1418 } 1419 1420 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1421 struct mlx5_ib_rq *rq, u32 tdn, 1422 u32 *qp_flags_en, struct ib_pd *pd, 1423 u32 *out) 1424 { 1425 u8 lb_flag = 0; 1426 u32 *in; 1427 void *tirc; 1428 int inlen; 1429 int err; 1430 1431 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1432 in = kvzalloc(inlen, GFP_KERNEL); 1433 if (!in) 1434 return -ENOMEM; 1435 1436 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1437 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1438 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1439 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1440 MLX5_SET(tirc, tirc, transport_domain, tdn); 1441 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1442 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1443 1444 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1445 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1446 1447 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1448 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1449 1450 if (dev->is_rep) { 1451 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1452 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1453 } 1454 1455 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1456 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1457 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1458 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1459 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1460 err = mlx5_ib_enable_lb(dev, false, true); 1461 1462 if (err) 1463 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1464 } 1465 kvfree(in); 1466 1467 return err; 1468 } 1469 1470 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1471 u32 *in, size_t inlen, struct ib_pd *pd, 1472 struct ib_udata *udata, 1473 struct mlx5_ib_create_qp_resp *resp, 1474 struct ib_qp_init_attr *init_attr) 1475 { 1476 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1477 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1478 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1479 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1480 udata, struct mlx5_ib_ucontext, ibucontext); 1481 int err; 1482 u32 tdn = mucontext->tdn; 1483 u16 uid = to_mpd(pd)->uid; 1484 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1485 1486 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1487 return -EINVAL; 1488 if (qp->sq.wqe_cnt) { 1489 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1490 if (err) 1491 return err; 1492 1493 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1494 to_mcq(init_attr->send_cq)); 1495 if (err) 1496 goto err_destroy_tis; 1497 1498 if (uid) { 1499 resp->tisn = sq->tisn; 1500 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1501 resp->sqn = sq->base.mqp.qpn; 1502 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1503 } 1504 1505 sq->base.container_mibqp = qp; 1506 sq->base.mqp.event = mlx5_ib_qp_event; 1507 } 1508 1509 if (qp->rq.wqe_cnt) { 1510 rq->base.container_mibqp = qp; 1511 1512 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1513 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1514 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1515 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1516 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1517 to_mcq(init_attr->recv_cq)); 1518 if (err) 1519 goto err_destroy_sq; 1520 1521 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1522 out); 1523 if (err) 1524 goto err_destroy_rq; 1525 1526 if (uid) { 1527 resp->rqn = rq->base.mqp.qpn; 1528 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1529 resp->tirn = rq->tirn; 1530 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1531 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1532 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1533 resp->tir_icm_addr = MLX5_GET( 1534 create_tir_out, out, icm_address_31_0); 1535 resp->tir_icm_addr |= 1536 (u64)MLX5_GET(create_tir_out, out, 1537 icm_address_39_32) 1538 << 32; 1539 resp->tir_icm_addr |= 1540 (u64)MLX5_GET(create_tir_out, out, 1541 icm_address_63_40) 1542 << 40; 1543 resp->comp_mask |= 1544 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1545 } 1546 } 1547 } 1548 1549 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1550 rq->base.mqp.qpn; 1551 return 0; 1552 1553 err_destroy_rq: 1554 destroy_raw_packet_qp_rq(dev, rq); 1555 err_destroy_sq: 1556 if (!qp->sq.wqe_cnt) 1557 return err; 1558 destroy_raw_packet_qp_sq(dev, sq); 1559 err_destroy_tis: 1560 destroy_raw_packet_qp_tis(dev, sq, pd); 1561 1562 return err; 1563 } 1564 1565 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1566 struct mlx5_ib_qp *qp) 1567 { 1568 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1569 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1570 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1571 1572 if (qp->rq.wqe_cnt) { 1573 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1574 destroy_raw_packet_qp_rq(dev, rq); 1575 } 1576 1577 if (qp->sq.wqe_cnt) { 1578 destroy_raw_packet_qp_sq(dev, sq); 1579 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1580 } 1581 } 1582 1583 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1584 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1585 { 1586 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1587 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1588 1589 sq->sq = &qp->sq; 1590 rq->rq = &qp->rq; 1591 sq->doorbell = &qp->db; 1592 rq->doorbell = &qp->db; 1593 } 1594 1595 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1596 { 1597 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1598 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1599 mlx5_ib_disable_lb(dev, false, true); 1600 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1601 to_mpd(qp->ibqp.pd)->uid); 1602 } 1603 1604 struct mlx5_create_qp_params { 1605 struct ib_udata *udata; 1606 size_t inlen; 1607 size_t outlen; 1608 size_t ucmd_size; 1609 void *ucmd; 1610 u8 is_rss_raw : 1; 1611 struct ib_qp_init_attr *attr; 1612 u32 uidx; 1613 struct mlx5_ib_create_qp_resp resp; 1614 }; 1615 1616 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1617 struct mlx5_ib_qp *qp, 1618 struct mlx5_create_qp_params *params) 1619 { 1620 struct ib_qp_init_attr *init_attr = params->attr; 1621 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1622 struct ib_udata *udata = params->udata; 1623 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1624 udata, struct mlx5_ib_ucontext, ibucontext); 1625 int inlen; 1626 int outlen; 1627 int err; 1628 u32 *in; 1629 u32 *out; 1630 void *tirc; 1631 void *hfso; 1632 u32 selected_fields = 0; 1633 u32 outer_l4; 1634 u32 tdn = mucontext->tdn; 1635 u8 lb_flag = 0; 1636 1637 if (ucmd->comp_mask) { 1638 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1639 return -EOPNOTSUPP; 1640 } 1641 1642 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1643 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1644 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1645 return -EOPNOTSUPP; 1646 } 1647 1648 if (dev->is_rep) 1649 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1650 1651 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1652 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1653 1654 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1655 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1656 1657 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1658 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1659 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1660 if (!in) 1661 return -ENOMEM; 1662 1663 out = in + MLX5_ST_SZ_DW(create_tir_in); 1664 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1665 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1666 MLX5_SET(tirc, tirc, disp_type, 1667 MLX5_TIRC_DISP_TYPE_INDIRECT); 1668 MLX5_SET(tirc, tirc, indirect_table, 1669 init_attr->rwq_ind_tbl->ind_tbl_num); 1670 MLX5_SET(tirc, tirc, transport_domain, tdn); 1671 1672 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1673 1674 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1675 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1676 1677 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1678 1679 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1680 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1681 else 1682 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1683 1684 switch (ucmd->rx_hash_function) { 1685 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1686 { 1687 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1688 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1689 1690 if (len != ucmd->rx_key_len) { 1691 err = -EINVAL; 1692 goto err; 1693 } 1694 1695 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1696 memcpy(rss_key, ucmd->rx_hash_key, len); 1697 break; 1698 } 1699 default: 1700 err = -EOPNOTSUPP; 1701 goto err; 1702 } 1703 1704 if (!ucmd->rx_hash_fields_mask) { 1705 /* special case when this TIR serves as steering entry without hashing */ 1706 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1707 goto create_tir; 1708 err = -EINVAL; 1709 goto err; 1710 } 1711 1712 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1713 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1714 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1715 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1716 err = -EINVAL; 1717 goto err; 1718 } 1719 1720 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1721 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1722 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1723 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1724 MLX5_L3_PROT_TYPE_IPV4); 1725 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1726 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1727 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1728 MLX5_L3_PROT_TYPE_IPV6); 1729 1730 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1731 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1732 << 0 | 1733 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1734 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1735 << 1 | 1736 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1737 1738 /* Check that only one l4 protocol is set */ 1739 if (outer_l4 & (outer_l4 - 1)) { 1740 err = -EINVAL; 1741 goto err; 1742 } 1743 1744 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1745 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1746 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1747 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1748 MLX5_L4_PROT_TYPE_TCP); 1749 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1750 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1751 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1752 MLX5_L4_PROT_TYPE_UDP); 1753 1754 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1755 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1756 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1757 1758 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1759 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1760 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1761 1762 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1763 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1764 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1765 1766 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1767 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1768 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1769 1770 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1771 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1772 1773 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1774 1775 create_tir: 1776 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1777 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1778 1779 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1780 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1781 err = mlx5_ib_enable_lb(dev, false, true); 1782 1783 if (err) 1784 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1785 to_mpd(pd)->uid); 1786 } 1787 1788 if (err) 1789 goto err; 1790 1791 if (mucontext->devx_uid) { 1792 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1793 params->resp.tirn = qp->rss_qp.tirn; 1794 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1795 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1796 params->resp.tir_icm_addr = 1797 MLX5_GET(create_tir_out, out, icm_address_31_0); 1798 params->resp.tir_icm_addr |= 1799 (u64)MLX5_GET(create_tir_out, out, 1800 icm_address_39_32) 1801 << 32; 1802 params->resp.tir_icm_addr |= 1803 (u64)MLX5_GET(create_tir_out, out, 1804 icm_address_63_40) 1805 << 40; 1806 params->resp.comp_mask |= 1807 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1808 } 1809 } 1810 1811 kvfree(in); 1812 /* qpn is reserved for that QP */ 1813 qp->trans_qp.base.mqp.qpn = 0; 1814 qp->is_rss = true; 1815 return 0; 1816 1817 err: 1818 kvfree(in); 1819 return err; 1820 } 1821 1822 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1823 struct mlx5_ib_qp *qp, 1824 struct ib_qp_init_attr *init_attr, 1825 void *qpc) 1826 { 1827 int scqe_sz; 1828 bool allow_scat_cqe = false; 1829 1830 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1831 1832 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1833 return; 1834 1835 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1836 if (scqe_sz == 128) { 1837 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1838 return; 1839 } 1840 1841 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1842 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1843 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1844 } 1845 1846 static int atomic_size_to_mode(int size_mask) 1847 { 1848 /* driver does not support atomic_size > 256B 1849 * and does not know how to translate bigger sizes 1850 */ 1851 int supported_size_mask = size_mask & 0x1ff; 1852 int log_max_size; 1853 1854 if (!supported_size_mask) 1855 return -EOPNOTSUPP; 1856 1857 log_max_size = __fls(supported_size_mask); 1858 1859 if (log_max_size > 3) 1860 return log_max_size; 1861 1862 return MLX5_ATOMIC_MODE_8B; 1863 } 1864 1865 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1866 enum ib_qp_type qp_type) 1867 { 1868 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1869 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1870 int atomic_mode = -EOPNOTSUPP; 1871 int atomic_size_mask; 1872 1873 if (!atomic) 1874 return -EOPNOTSUPP; 1875 1876 if (qp_type == MLX5_IB_QPT_DCT) 1877 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1878 else 1879 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1880 1881 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1882 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1883 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1884 1885 if (atomic_mode <= 0 && 1886 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1887 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1888 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1889 1890 return atomic_mode; 1891 } 1892 1893 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1894 struct mlx5_create_qp_params *params) 1895 { 1896 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1897 struct ib_qp_init_attr *attr = params->attr; 1898 u32 uidx = params->uidx; 1899 struct mlx5_ib_resources *devr = &dev->devr; 1900 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1901 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1902 struct mlx5_core_dev *mdev = dev->mdev; 1903 struct mlx5_ib_qp_base *base; 1904 unsigned long flags; 1905 void *qpc; 1906 u32 *in; 1907 int err; 1908 1909 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1910 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1911 1912 in = kvzalloc(inlen, GFP_KERNEL); 1913 if (!in) 1914 return -ENOMEM; 1915 1916 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd) 1917 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1918 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1919 1920 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 1921 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1922 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 1923 1924 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1925 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1926 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1927 MLX5_SET(qpc, qpc, cd_master, 1); 1928 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1929 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1930 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1931 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1932 1933 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 1934 MLX5_SET(qpc, qpc, no_sq, 1); 1935 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1936 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1937 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1938 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 1939 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1940 1941 /* 0xffffff means we ask to work with cqe version 0 */ 1942 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1943 MLX5_SET(qpc, qpc, user_index, uidx); 1944 1945 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1946 MLX5_SET(qpc, qpc, end_padding_mode, 1947 MLX5_WQ_END_PAD_MODE_ALIGN); 1948 /* Special case to clean flag */ 1949 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 1950 } 1951 1952 base = &qp->trans_qp.base; 1953 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 1954 kvfree(in); 1955 if (err) 1956 return err; 1957 1958 base->container_mibqp = qp; 1959 base->mqp.event = mlx5_ib_qp_event; 1960 if (MLX5_CAP_GEN(mdev, ece_support)) 1961 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 1962 1963 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1964 list_add_tail(&qp->qps_list, &dev->qp_list); 1965 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1966 1967 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 1968 return 0; 1969 } 1970 1971 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1972 struct mlx5_ib_qp *qp, 1973 struct mlx5_create_qp_params *params) 1974 { 1975 struct ib_qp_init_attr *init_attr = params->attr; 1976 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1977 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1978 struct ib_udata *udata = params->udata; 1979 u32 uidx = params->uidx; 1980 struct mlx5_ib_resources *devr = &dev->devr; 1981 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1982 struct mlx5_core_dev *mdev = dev->mdev; 1983 struct mlx5_ib_cq *send_cq; 1984 struct mlx5_ib_cq *recv_cq; 1985 unsigned long flags; 1986 struct mlx5_ib_qp_base *base; 1987 int ts_format; 1988 int mlx5_st; 1989 void *qpc; 1990 u32 *in; 1991 int err; 1992 1993 spin_lock_init(&qp->sq.lock); 1994 spin_lock_init(&qp->rq.lock); 1995 1996 mlx5_st = to_mlx5_st(qp->type); 1997 if (mlx5_st < 0) 1998 return -EINVAL; 1999 2000 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2001 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2002 2003 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2004 qp->underlay_qpn = init_attr->source_qpn; 2005 2006 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2007 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2008 &qp->raw_packet_qp.rq.base : 2009 &qp->trans_qp.base; 2010 2011 qp->has_rq = qp_has_rq(init_attr); 2012 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2013 if (err) { 2014 mlx5_ib_dbg(dev, "err %d\n", err); 2015 return err; 2016 } 2017 2018 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2019 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2020 return -EINVAL; 2021 2022 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2023 return -EINVAL; 2024 2025 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2026 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2027 to_mcq(init_attr->recv_cq)); 2028 if (ts_format < 0) 2029 return ts_format; 2030 } 2031 2032 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2033 &inlen, base, ucmd); 2034 if (err) 2035 return err; 2036 2037 if (is_sqp(init_attr->qp_type)) 2038 qp->port = init_attr->port_num; 2039 2040 if (MLX5_CAP_GEN(mdev, ece_support)) 2041 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2042 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2043 2044 MLX5_SET(qpc, qpc, st, mlx5_st); 2045 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2046 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2047 2048 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2049 MLX5_SET(qpc, qpc, wq_signature, 1); 2050 2051 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2052 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2053 2054 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2055 MLX5_SET(qpc, qpc, cd_master, 1); 2056 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2057 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2058 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2059 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2060 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2061 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2062 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2063 (init_attr->qp_type == IB_QPT_RC || 2064 init_attr->qp_type == IB_QPT_UC)) { 2065 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2066 2067 MLX5_SET(qpc, qpc, cs_res, 2068 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2069 MLX5_RES_SCAT_DATA32_CQE); 2070 } 2071 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2072 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2073 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2074 2075 if (qp->rq.wqe_cnt) { 2076 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2077 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2078 } 2079 2080 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2081 MLX5_SET(qpc, qpc, ts_format, ts_format); 2082 2083 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2084 2085 if (qp->sq.wqe_cnt) { 2086 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2087 } else { 2088 MLX5_SET(qpc, qpc, no_sq, 1); 2089 if (init_attr->srq && 2090 init_attr->srq->srq_type == IB_SRQT_TM) 2091 MLX5_SET(qpc, qpc, offload_type, 2092 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2093 } 2094 2095 /* Set default resources */ 2096 switch (init_attr->qp_type) { 2097 case IB_QPT_XRC_INI: 2098 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2099 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2100 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2101 break; 2102 default: 2103 if (init_attr->srq) { 2104 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2105 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2106 } else { 2107 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2108 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2109 } 2110 } 2111 2112 if (init_attr->send_cq) 2113 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2114 2115 if (init_attr->recv_cq) 2116 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2117 2118 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2119 2120 /* 0xffffff means we ask to work with cqe version 0 */ 2121 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2122 MLX5_SET(qpc, qpc, user_index, uidx); 2123 2124 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2125 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2126 MLX5_SET(qpc, qpc, end_padding_mode, 2127 MLX5_WQ_END_PAD_MODE_ALIGN); 2128 /* Special case to clean flag */ 2129 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2130 } 2131 2132 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2133 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2134 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2135 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2136 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2137 ¶ms->resp, init_attr); 2138 } else 2139 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2140 2141 kvfree(in); 2142 if (err) 2143 goto err_create; 2144 2145 base->container_mibqp = qp; 2146 base->mqp.event = mlx5_ib_qp_event; 2147 if (MLX5_CAP_GEN(mdev, ece_support)) 2148 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2149 2150 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2151 &send_cq, &recv_cq); 2152 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2153 mlx5_ib_lock_cqs(send_cq, recv_cq); 2154 /* Maintain device to QPs access, needed for further handling via reset 2155 * flow 2156 */ 2157 list_add_tail(&qp->qps_list, &dev->qp_list); 2158 /* Maintain CQ to QPs access, needed for further handling via reset flow 2159 */ 2160 if (send_cq) 2161 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2162 if (recv_cq) 2163 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2164 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2165 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2166 2167 return 0; 2168 2169 err_create: 2170 destroy_qp(dev, qp, base, udata); 2171 return err; 2172 } 2173 2174 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2175 struct mlx5_ib_qp *qp, 2176 struct mlx5_create_qp_params *params) 2177 { 2178 struct ib_qp_init_attr *attr = params->attr; 2179 u32 uidx = params->uidx; 2180 struct mlx5_ib_resources *devr = &dev->devr; 2181 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2182 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2183 struct mlx5_core_dev *mdev = dev->mdev; 2184 struct mlx5_ib_cq *send_cq; 2185 struct mlx5_ib_cq *recv_cq; 2186 unsigned long flags; 2187 struct mlx5_ib_qp_base *base; 2188 int mlx5_st; 2189 void *qpc; 2190 u32 *in; 2191 int err; 2192 2193 spin_lock_init(&qp->sq.lock); 2194 spin_lock_init(&qp->rq.lock); 2195 2196 mlx5_st = to_mlx5_st(qp->type); 2197 if (mlx5_st < 0) 2198 return -EINVAL; 2199 2200 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2201 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2202 2203 base = &qp->trans_qp.base; 2204 2205 qp->has_rq = qp_has_rq(attr); 2206 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2207 if (err) { 2208 mlx5_ib_dbg(dev, "err %d\n", err); 2209 return err; 2210 } 2211 2212 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2213 if (err) 2214 return err; 2215 2216 if (is_sqp(attr->qp_type)) 2217 qp->port = attr->port_num; 2218 2219 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2220 2221 MLX5_SET(qpc, qpc, st, mlx5_st); 2222 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2223 2224 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2225 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2226 else 2227 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2228 2229 2230 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2231 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2232 2233 if (qp->rq.wqe_cnt) { 2234 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2235 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2236 } 2237 2238 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2239 2240 if (qp->sq.wqe_cnt) 2241 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2242 else 2243 MLX5_SET(qpc, qpc, no_sq, 1); 2244 2245 if (attr->srq) { 2246 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2247 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2248 to_msrq(attr->srq)->msrq.srqn); 2249 } else { 2250 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2251 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2252 to_msrq(devr->s1)->msrq.srqn); 2253 } 2254 2255 if (attr->send_cq) 2256 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2257 2258 if (attr->recv_cq) 2259 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2260 2261 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2262 2263 /* 0xffffff means we ask to work with cqe version 0 */ 2264 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2265 MLX5_SET(qpc, qpc, user_index, uidx); 2266 2267 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2268 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2269 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2270 2271 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2272 kvfree(in); 2273 if (err) 2274 goto err_create; 2275 2276 base->container_mibqp = qp; 2277 base->mqp.event = mlx5_ib_qp_event; 2278 2279 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2280 &send_cq, &recv_cq); 2281 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2282 mlx5_ib_lock_cqs(send_cq, recv_cq); 2283 /* Maintain device to QPs access, needed for further handling via reset 2284 * flow 2285 */ 2286 list_add_tail(&qp->qps_list, &dev->qp_list); 2287 /* Maintain CQ to QPs access, needed for further handling via reset flow 2288 */ 2289 if (send_cq) 2290 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2291 if (recv_cq) 2292 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2293 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2294 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2295 2296 return 0; 2297 2298 err_create: 2299 destroy_qp(dev, qp, base, NULL); 2300 return err; 2301 } 2302 2303 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2304 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2305 { 2306 if (send_cq) { 2307 if (recv_cq) { 2308 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2309 spin_lock(&send_cq->lock); 2310 spin_lock_nested(&recv_cq->lock, 2311 SINGLE_DEPTH_NESTING); 2312 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2313 spin_lock(&send_cq->lock); 2314 __acquire(&recv_cq->lock); 2315 } else { 2316 spin_lock(&recv_cq->lock); 2317 spin_lock_nested(&send_cq->lock, 2318 SINGLE_DEPTH_NESTING); 2319 } 2320 } else { 2321 spin_lock(&send_cq->lock); 2322 __acquire(&recv_cq->lock); 2323 } 2324 } else if (recv_cq) { 2325 spin_lock(&recv_cq->lock); 2326 __acquire(&send_cq->lock); 2327 } else { 2328 __acquire(&send_cq->lock); 2329 __acquire(&recv_cq->lock); 2330 } 2331 } 2332 2333 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2334 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2335 { 2336 if (send_cq) { 2337 if (recv_cq) { 2338 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2339 spin_unlock(&recv_cq->lock); 2340 spin_unlock(&send_cq->lock); 2341 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2342 __release(&recv_cq->lock); 2343 spin_unlock(&send_cq->lock); 2344 } else { 2345 spin_unlock(&send_cq->lock); 2346 spin_unlock(&recv_cq->lock); 2347 } 2348 } else { 2349 __release(&recv_cq->lock); 2350 spin_unlock(&send_cq->lock); 2351 } 2352 } else if (recv_cq) { 2353 __release(&send_cq->lock); 2354 spin_unlock(&recv_cq->lock); 2355 } else { 2356 __release(&recv_cq->lock); 2357 __release(&send_cq->lock); 2358 } 2359 } 2360 2361 static void get_cqs(enum ib_qp_type qp_type, 2362 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2363 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2364 { 2365 switch (qp_type) { 2366 case IB_QPT_XRC_TGT: 2367 *send_cq = NULL; 2368 *recv_cq = NULL; 2369 break; 2370 case MLX5_IB_QPT_REG_UMR: 2371 case IB_QPT_XRC_INI: 2372 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2373 *recv_cq = NULL; 2374 break; 2375 2376 case IB_QPT_SMI: 2377 case MLX5_IB_QPT_HW_GSI: 2378 case IB_QPT_RC: 2379 case IB_QPT_UC: 2380 case IB_QPT_UD: 2381 case IB_QPT_RAW_PACKET: 2382 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2383 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2384 break; 2385 default: 2386 *send_cq = NULL; 2387 *recv_cq = NULL; 2388 break; 2389 } 2390 } 2391 2392 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2393 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2394 u8 lag_tx_affinity); 2395 2396 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2397 struct ib_udata *udata) 2398 { 2399 struct mlx5_ib_cq *send_cq, *recv_cq; 2400 struct mlx5_ib_qp_base *base; 2401 unsigned long flags; 2402 int err; 2403 2404 if (qp->is_rss) { 2405 destroy_rss_raw_qp_tir(dev, qp); 2406 return; 2407 } 2408 2409 base = (qp->type == IB_QPT_RAW_PACKET || 2410 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2411 &qp->raw_packet_qp.rq.base : 2412 &qp->trans_qp.base; 2413 2414 if (qp->state != IB_QPS_RESET) { 2415 if (qp->type != IB_QPT_RAW_PACKET && 2416 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2417 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2418 NULL, &base->mqp, NULL); 2419 } else { 2420 struct mlx5_modify_raw_qp_param raw_qp_param = { 2421 .operation = MLX5_CMD_OP_2RST_QP 2422 }; 2423 2424 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2425 } 2426 if (err) 2427 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2428 base->mqp.qpn); 2429 } 2430 2431 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2432 &recv_cq); 2433 2434 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2435 mlx5_ib_lock_cqs(send_cq, recv_cq); 2436 /* del from lists under both locks above to protect reset flow paths */ 2437 list_del(&qp->qps_list); 2438 if (send_cq) 2439 list_del(&qp->cq_send_list); 2440 2441 if (recv_cq) 2442 list_del(&qp->cq_recv_list); 2443 2444 if (!udata) { 2445 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2446 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2447 if (send_cq != recv_cq) 2448 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2449 NULL); 2450 } 2451 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2452 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2453 2454 if (qp->type == IB_QPT_RAW_PACKET || 2455 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2456 destroy_raw_packet_qp(dev, qp); 2457 } else { 2458 err = mlx5_core_destroy_qp(dev, &base->mqp); 2459 if (err) 2460 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2461 base->mqp.qpn); 2462 } 2463 2464 destroy_qp(dev, qp, base, udata); 2465 } 2466 2467 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2468 struct mlx5_ib_qp *qp, 2469 struct mlx5_create_qp_params *params) 2470 { 2471 struct ib_qp_init_attr *attr = params->attr; 2472 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2473 u32 uidx = params->uidx; 2474 void *dctc; 2475 2476 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2477 return -EOPNOTSUPP; 2478 2479 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2480 if (!qp->dct.in) 2481 return -ENOMEM; 2482 2483 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2484 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2485 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2486 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2487 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2488 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2489 MLX5_SET(dctc, dctc, user_index, uidx); 2490 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2491 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2492 2493 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2494 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2495 2496 if (rcqe_sz == 128) 2497 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2498 } 2499 2500 qp->state = IB_QPS_RESET; 2501 rdma_restrack_no_track(&qp->ibqp.res); 2502 return 0; 2503 } 2504 2505 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2506 enum ib_qp_type *type) 2507 { 2508 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2509 goto out; 2510 2511 switch (attr->qp_type) { 2512 case IB_QPT_XRC_TGT: 2513 case IB_QPT_XRC_INI: 2514 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2515 goto out; 2516 fallthrough; 2517 case IB_QPT_RC: 2518 case IB_QPT_UC: 2519 case IB_QPT_SMI: 2520 case MLX5_IB_QPT_HW_GSI: 2521 case IB_QPT_DRIVER: 2522 case IB_QPT_GSI: 2523 case IB_QPT_RAW_PACKET: 2524 case IB_QPT_UD: 2525 case MLX5_IB_QPT_REG_UMR: 2526 break; 2527 default: 2528 goto out; 2529 } 2530 2531 *type = attr->qp_type; 2532 return 0; 2533 2534 out: 2535 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2536 return -EOPNOTSUPP; 2537 } 2538 2539 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2540 struct ib_qp_init_attr *attr, 2541 struct ib_udata *udata) 2542 { 2543 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2544 udata, struct mlx5_ib_ucontext, ibucontext); 2545 2546 if (!udata) { 2547 /* Kernel create_qp callers */ 2548 if (attr->rwq_ind_tbl) 2549 return -EOPNOTSUPP; 2550 2551 switch (attr->qp_type) { 2552 case IB_QPT_RAW_PACKET: 2553 case IB_QPT_DRIVER: 2554 return -EOPNOTSUPP; 2555 default: 2556 return 0; 2557 } 2558 } 2559 2560 /* Userspace create_qp callers */ 2561 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2562 mlx5_ib_dbg(dev, 2563 "Raw Packet QP is only supported for CQE version > 0\n"); 2564 return -EINVAL; 2565 } 2566 2567 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2568 mlx5_ib_dbg(dev, 2569 "Wrong QP type %d for the RWQ indirect table\n", 2570 attr->qp_type); 2571 return -EINVAL; 2572 } 2573 2574 /* 2575 * We don't need to see this warning, it means that kernel code 2576 * missing ib_pd. Placed here to catch developer's mistakes. 2577 */ 2578 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2579 "There is a missing PD pointer assignment\n"); 2580 return 0; 2581 } 2582 2583 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2584 bool cond, struct mlx5_ib_qp *qp) 2585 { 2586 if (!(*flags & flag)) 2587 return; 2588 2589 if (cond) { 2590 qp->flags_en |= flag; 2591 *flags &= ~flag; 2592 return; 2593 } 2594 2595 switch (flag) { 2596 case MLX5_QP_FLAG_SCATTER_CQE: 2597 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2598 /* 2599 * We don't return error if these flags were provided, 2600 * and mlx5 doesn't have right capability. 2601 */ 2602 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2603 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2604 return; 2605 default: 2606 break; 2607 } 2608 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2609 } 2610 2611 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2612 void *ucmd, struct ib_qp_init_attr *attr) 2613 { 2614 struct mlx5_core_dev *mdev = dev->mdev; 2615 bool cond; 2616 int flags; 2617 2618 if (attr->rwq_ind_tbl) 2619 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2620 else 2621 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2622 2623 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2624 case MLX5_QP_FLAG_TYPE_DCI: 2625 qp->type = MLX5_IB_QPT_DCI; 2626 break; 2627 case MLX5_QP_FLAG_TYPE_DCT: 2628 qp->type = MLX5_IB_QPT_DCT; 2629 break; 2630 default: 2631 if (qp->type != IB_QPT_DRIVER) 2632 break; 2633 /* 2634 * It is IB_QPT_DRIVER and or no subtype or 2635 * wrong subtype were provided. 2636 */ 2637 return -EINVAL; 2638 } 2639 2640 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2641 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2642 2643 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2644 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2645 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2646 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2647 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2648 2649 if (qp->type == IB_QPT_RAW_PACKET) { 2650 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2651 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2652 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2653 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2654 cond, qp); 2655 process_vendor_flag(dev, &flags, 2656 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2657 qp); 2658 process_vendor_flag(dev, &flags, 2659 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2660 qp); 2661 } 2662 2663 if (qp->type == IB_QPT_RC) 2664 process_vendor_flag(dev, &flags, 2665 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2666 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2667 2668 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2669 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2670 2671 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2672 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2673 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2674 if (attr->rwq_ind_tbl && cond) { 2675 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2676 cond); 2677 return -EINVAL; 2678 } 2679 2680 if (flags) 2681 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2682 2683 return (flags) ? -EINVAL : 0; 2684 } 2685 2686 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2687 bool cond, struct mlx5_ib_qp *qp) 2688 { 2689 if (!(*flags & flag)) 2690 return; 2691 2692 if (cond) { 2693 qp->flags |= flag; 2694 *flags &= ~flag; 2695 return; 2696 } 2697 2698 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2699 /* 2700 * Special case, if condition didn't meet, it won't be error, 2701 * just different in-kernel flow. 2702 */ 2703 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2704 return; 2705 } 2706 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2707 } 2708 2709 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2710 struct ib_qp_init_attr *attr) 2711 { 2712 enum ib_qp_type qp_type = qp->type; 2713 struct mlx5_core_dev *mdev = dev->mdev; 2714 int create_flags = attr->create_flags; 2715 bool cond; 2716 2717 if (qp_type == MLX5_IB_QPT_DCT) 2718 return (create_flags) ? -EINVAL : 0; 2719 2720 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2721 return (create_flags) ? -EINVAL : 0; 2722 2723 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2724 mlx5_get_flow_namespace(dev->mdev, 2725 MLX5_FLOW_NAMESPACE_BYPASS), 2726 qp); 2727 process_create_flag(dev, &create_flags, 2728 IB_QP_CREATE_INTEGRITY_EN, 2729 MLX5_CAP_GEN(mdev, sho), qp); 2730 process_create_flag(dev, &create_flags, 2731 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2732 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2733 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2734 MLX5_CAP_GEN(mdev, cd), qp); 2735 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2736 MLX5_CAP_GEN(mdev, cd), qp); 2737 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2738 MLX5_CAP_GEN(mdev, cd), qp); 2739 2740 if (qp_type == IB_QPT_UD) { 2741 process_create_flag(dev, &create_flags, 2742 IB_QP_CREATE_IPOIB_UD_LSO, 2743 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2744 qp); 2745 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2746 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 2747 cond, qp); 2748 } 2749 2750 if (qp_type == IB_QPT_RAW_PACKET) { 2751 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2752 MLX5_CAP_ETH(mdev, scatter_fcs); 2753 process_create_flag(dev, &create_flags, 2754 IB_QP_CREATE_SCATTER_FCS, cond, qp); 2755 2756 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2757 MLX5_CAP_ETH(mdev, vlan_cap); 2758 process_create_flag(dev, &create_flags, 2759 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 2760 } 2761 2762 process_create_flag(dev, &create_flags, 2763 IB_QP_CREATE_PCI_WRITE_END_PADDING, 2764 MLX5_CAP_GEN(mdev, end_pad), qp); 2765 2766 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 2767 qp_type != MLX5_IB_QPT_REG_UMR, qp); 2768 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 2769 true, qp); 2770 2771 if (create_flags) { 2772 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 2773 create_flags); 2774 return -EOPNOTSUPP; 2775 } 2776 return 0; 2777 } 2778 2779 static int process_udata_size(struct mlx5_ib_dev *dev, 2780 struct mlx5_create_qp_params *params) 2781 { 2782 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 2783 struct ib_udata *udata = params->udata; 2784 size_t outlen = udata->outlen; 2785 size_t inlen = udata->inlen; 2786 2787 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 2788 params->ucmd_size = ucmd; 2789 if (!params->is_rss_raw) { 2790 /* User has old rdma-core, which doesn't support ECE */ 2791 size_t min_inlen = 2792 offsetof(struct mlx5_ib_create_qp, ece_options); 2793 2794 /* 2795 * We will check in check_ucmd_data() that user 2796 * cleared everything after inlen. 2797 */ 2798 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 2799 goto out; 2800 } 2801 2802 /* RSS RAW QP */ 2803 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 2804 return -EINVAL; 2805 2806 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 2807 return -EINVAL; 2808 2809 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 2810 params->ucmd_size = ucmd; 2811 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 2812 return -EINVAL; 2813 2814 params->inlen = min(ucmd, inlen); 2815 out: 2816 if (!params->inlen) 2817 mlx5_ib_dbg(dev, "udata is too small\n"); 2818 2819 return (params->inlen) ? 0 : -EINVAL; 2820 } 2821 2822 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2823 struct mlx5_ib_qp *qp, 2824 struct mlx5_create_qp_params *params) 2825 { 2826 int err; 2827 2828 if (params->is_rss_raw) { 2829 err = create_rss_raw_qp_tir(dev, pd, qp, params); 2830 goto out; 2831 } 2832 2833 switch (qp->type) { 2834 case MLX5_IB_QPT_DCT: 2835 err = create_dct(dev, pd, qp, params); 2836 break; 2837 case IB_QPT_XRC_TGT: 2838 err = create_xrc_tgt_qp(dev, qp, params); 2839 break; 2840 case IB_QPT_GSI: 2841 err = mlx5_ib_create_gsi(pd, qp, params->attr); 2842 break; 2843 default: 2844 if (params->udata) 2845 err = create_user_qp(dev, pd, qp, params); 2846 else 2847 err = create_kernel_qp(dev, pd, qp, params); 2848 } 2849 2850 out: 2851 if (err) { 2852 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 2853 return err; 2854 } 2855 2856 if (is_qp0(qp->type)) 2857 qp->ibqp.qp_num = 0; 2858 else if (is_qp1(qp->type)) 2859 qp->ibqp.qp_num = 1; 2860 else 2861 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2862 2863 mlx5_ib_dbg(dev, 2864 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 2865 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2866 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 2867 -1, 2868 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 2869 -1, 2870 params->resp.ece_options); 2871 2872 return 0; 2873 } 2874 2875 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2876 struct ib_qp_init_attr *attr) 2877 { 2878 int ret = 0; 2879 2880 switch (qp->type) { 2881 case MLX5_IB_QPT_DCT: 2882 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 2883 break; 2884 case MLX5_IB_QPT_DCI: 2885 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 2886 -EINVAL : 2887 0; 2888 break; 2889 case IB_QPT_RAW_PACKET: 2890 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 2891 break; 2892 default: 2893 break; 2894 } 2895 2896 if (ret) 2897 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 2898 2899 return ret; 2900 } 2901 2902 static int get_qp_uidx(struct mlx5_ib_qp *qp, 2903 struct mlx5_create_qp_params *params) 2904 { 2905 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2906 struct ib_udata *udata = params->udata; 2907 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2908 udata, struct mlx5_ib_ucontext, ibucontext); 2909 2910 if (params->is_rss_raw) 2911 return 0; 2912 2913 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 2914 } 2915 2916 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2917 { 2918 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2919 2920 if (mqp->state == IB_QPS_RTR) { 2921 int err; 2922 2923 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 2924 if (err) { 2925 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2926 return err; 2927 } 2928 } 2929 2930 kfree(mqp->dct.in); 2931 kfree(mqp); 2932 return 0; 2933 } 2934 2935 static int check_ucmd_data(struct mlx5_ib_dev *dev, 2936 struct mlx5_create_qp_params *params) 2937 { 2938 struct ib_udata *udata = params->udata; 2939 size_t size, last; 2940 int ret; 2941 2942 if (params->is_rss_raw) 2943 /* 2944 * These QPs don't have "reserved" field in their 2945 * create_qp input struct, so their data is always valid. 2946 */ 2947 last = sizeof(struct mlx5_ib_create_qp_rss); 2948 else 2949 last = offsetof(struct mlx5_ib_create_qp, reserved); 2950 2951 if (udata->inlen <= last) 2952 return 0; 2953 2954 /* 2955 * User provides different create_qp structures based on the 2956 * flow and we need to know if he cleared memory after our 2957 * struct create_qp ends. 2958 */ 2959 size = udata->inlen - last; 2960 ret = ib_is_udata_cleared(params->udata, last, size); 2961 if (!ret) 2962 mlx5_ib_dbg( 2963 dev, 2964 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 2965 udata->inlen, params->ucmd_size, last, size); 2966 return ret ? 0 : -EINVAL; 2967 } 2968 2969 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr, 2970 struct ib_udata *udata) 2971 { 2972 struct mlx5_create_qp_params params = {}; 2973 struct mlx5_ib_dev *dev; 2974 struct mlx5_ib_qp *qp; 2975 enum ib_qp_type type; 2976 int err; 2977 2978 dev = pd ? to_mdev(pd->device) : 2979 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device); 2980 2981 err = check_qp_type(dev, attr, &type); 2982 if (err) 2983 return ERR_PTR(err); 2984 2985 err = check_valid_flow(dev, pd, attr, udata); 2986 if (err) 2987 return ERR_PTR(err); 2988 2989 params.udata = udata; 2990 params.uidx = MLX5_IB_DEFAULT_UIDX; 2991 params.attr = attr; 2992 params.is_rss_raw = !!attr->rwq_ind_tbl; 2993 2994 if (udata) { 2995 err = process_udata_size(dev, ¶ms); 2996 if (err) 2997 return ERR_PTR(err); 2998 2999 err = check_ucmd_data(dev, ¶ms); 3000 if (err) 3001 return ERR_PTR(err); 3002 3003 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3004 if (!params.ucmd) 3005 return ERR_PTR(-ENOMEM); 3006 3007 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3008 if (err) 3009 goto free_ucmd; 3010 } 3011 3012 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 3013 if (!qp) { 3014 err = -ENOMEM; 3015 goto free_ucmd; 3016 } 3017 3018 mutex_init(&qp->mutex); 3019 qp->type = type; 3020 if (udata) { 3021 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3022 if (err) 3023 goto free_qp; 3024 3025 err = get_qp_uidx(qp, ¶ms); 3026 if (err) 3027 goto free_qp; 3028 } 3029 err = process_create_flags(dev, qp, attr); 3030 if (err) 3031 goto free_qp; 3032 3033 err = check_qp_attr(dev, qp, attr); 3034 if (err) 3035 goto free_qp; 3036 3037 err = create_qp(dev, pd, qp, ¶ms); 3038 if (err) 3039 goto free_qp; 3040 3041 kfree(params.ucmd); 3042 params.ucmd = NULL; 3043 3044 if (udata) 3045 /* 3046 * It is safe to copy response for all user create QP flows, 3047 * including MLX5_IB_QPT_DCT, which doesn't need it. 3048 * In that case, resp will be filled with zeros. 3049 */ 3050 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3051 if (err) 3052 goto destroy_qp; 3053 3054 return &qp->ibqp; 3055 3056 destroy_qp: 3057 switch (qp->type) { 3058 case MLX5_IB_QPT_DCT: 3059 mlx5_ib_destroy_dct(qp); 3060 break; 3061 case IB_QPT_GSI: 3062 mlx5_ib_destroy_gsi(qp); 3063 break; 3064 default: 3065 /* 3066 * These lines below are temp solution till QP allocation 3067 * will be moved to be under IB/core responsiblity. 3068 */ 3069 qp->ibqp.send_cq = attr->send_cq; 3070 qp->ibqp.recv_cq = attr->recv_cq; 3071 qp->ibqp.pd = pd; 3072 destroy_qp_common(dev, qp, udata); 3073 } 3074 3075 qp = NULL; 3076 free_qp: 3077 kfree(qp); 3078 free_ucmd: 3079 kfree(params.ucmd); 3080 return ERR_PTR(err); 3081 } 3082 3083 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3084 { 3085 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3086 struct mlx5_ib_qp *mqp = to_mqp(qp); 3087 3088 if (unlikely(qp->qp_type == IB_QPT_GSI)) 3089 return mlx5_ib_destroy_gsi(mqp); 3090 3091 if (mqp->type == MLX5_IB_QPT_DCT) 3092 return mlx5_ib_destroy_dct(mqp); 3093 3094 destroy_qp_common(dev, mqp, udata); 3095 3096 kfree(mqp); 3097 3098 return 0; 3099 } 3100 3101 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3102 const struct ib_qp_attr *attr, int attr_mask, 3103 void *qpc) 3104 { 3105 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3106 u8 dest_rd_atomic; 3107 u32 access_flags; 3108 3109 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3110 dest_rd_atomic = attr->max_dest_rd_atomic; 3111 else 3112 dest_rd_atomic = qp->trans_qp.resp_depth; 3113 3114 if (attr_mask & IB_QP_ACCESS_FLAGS) 3115 access_flags = attr->qp_access_flags; 3116 else 3117 access_flags = qp->trans_qp.atomic_rd_en; 3118 3119 if (!dest_rd_atomic) 3120 access_flags &= IB_ACCESS_REMOTE_WRITE; 3121 3122 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3123 3124 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3125 int atomic_mode; 3126 3127 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 3128 if (atomic_mode < 0) 3129 return -EOPNOTSUPP; 3130 3131 MLX5_SET(qpc, qpc, rae, 1); 3132 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3133 } 3134 3135 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3136 return 0; 3137 } 3138 3139 enum { 3140 MLX5_PATH_FLAG_FL = 1 << 0, 3141 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3142 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3143 }; 3144 3145 static int ib_to_mlx5_rate_map(u8 rate) 3146 { 3147 switch (rate) { 3148 case IB_RATE_PORT_CURRENT: 3149 return 0; 3150 case IB_RATE_56_GBPS: 3151 return 1; 3152 case IB_RATE_25_GBPS: 3153 return 2; 3154 case IB_RATE_100_GBPS: 3155 return 3; 3156 case IB_RATE_200_GBPS: 3157 return 4; 3158 case IB_RATE_50_GBPS: 3159 return 5; 3160 case IB_RATE_400_GBPS: 3161 return 6; 3162 default: 3163 return rate + MLX5_STAT_RATE_OFFSET; 3164 } 3165 3166 return 0; 3167 } 3168 3169 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3170 { 3171 u32 stat_rate_support; 3172 3173 if (rate == IB_RATE_PORT_CURRENT) 3174 return 0; 3175 3176 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3177 return -EINVAL; 3178 3179 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3180 while (rate != IB_RATE_PORT_CURRENT && 3181 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3182 --rate; 3183 3184 return ib_to_mlx5_rate_map(rate); 3185 } 3186 3187 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3188 struct mlx5_ib_sq *sq, u8 sl, 3189 struct ib_pd *pd) 3190 { 3191 void *in; 3192 void *tisc; 3193 int inlen; 3194 int err; 3195 3196 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3197 in = kvzalloc(inlen, GFP_KERNEL); 3198 if (!in) 3199 return -ENOMEM; 3200 3201 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3202 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3203 3204 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3205 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3206 3207 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3208 3209 kvfree(in); 3210 3211 return err; 3212 } 3213 3214 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3215 struct mlx5_ib_sq *sq, u8 tx_affinity, 3216 struct ib_pd *pd) 3217 { 3218 void *in; 3219 void *tisc; 3220 int inlen; 3221 int err; 3222 3223 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3224 in = kvzalloc(inlen, GFP_KERNEL); 3225 if (!in) 3226 return -ENOMEM; 3227 3228 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3229 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3230 3231 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3232 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3233 3234 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3235 3236 kvfree(in); 3237 3238 return err; 3239 } 3240 3241 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3242 u32 lqpn, u32 rqpn) 3243 3244 { 3245 u32 fl = ah->grh.flow_label; 3246 3247 if (!fl) 3248 fl = rdma_calc_flow_label(lqpn, rqpn); 3249 3250 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3251 } 3252 3253 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3254 const struct rdma_ah_attr *ah, void *path, u8 port, 3255 int attr_mask, u32 path_flags, 3256 const struct ib_qp_attr *attr, bool alt) 3257 { 3258 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3259 int err; 3260 enum ib_gid_type gid_type; 3261 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3262 u8 sl = rdma_ah_get_sl(ah); 3263 3264 if (attr_mask & IB_QP_PKEY_INDEX) 3265 MLX5_SET(ads, path, pkey_index, 3266 alt ? attr->alt_pkey_index : attr->pkey_index); 3267 3268 if (ah_flags & IB_AH_GRH) { 3269 const struct ib_port_immutable *immutable; 3270 3271 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3272 if (grh->sgid_index >= immutable->gid_tbl_len) { 3273 pr_err("sgid_index (%u) too large. max is %d\n", 3274 grh->sgid_index, 3275 immutable->gid_tbl_len); 3276 return -EINVAL; 3277 } 3278 } 3279 3280 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3281 if (!(ah_flags & IB_AH_GRH)) 3282 return -EINVAL; 3283 3284 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3285 ah->roce.dmac); 3286 if ((qp->ibqp.qp_type == IB_QPT_RC || 3287 qp->ibqp.qp_type == IB_QPT_UC || 3288 qp->ibqp.qp_type == IB_QPT_XRC_INI || 3289 qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 3290 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3291 (attr_mask & IB_QP_DEST_QPN)) 3292 mlx5_set_path_udp_sport(path, ah, 3293 qp->ibqp.qp_num, 3294 attr->dest_qp_num); 3295 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3296 gid_type = ah->grh.sgid_attr->gid_type; 3297 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3298 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3299 } else { 3300 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3301 MLX5_SET(ads, path, free_ar, 3302 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3303 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3304 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3305 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3306 MLX5_SET(ads, path, sl, sl); 3307 } 3308 3309 if (ah_flags & IB_AH_GRH) { 3310 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3311 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3312 MLX5_SET(ads, path, tclass, grh->traffic_class); 3313 MLX5_SET(ads, path, flow_label, grh->flow_label); 3314 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3315 sizeof(grh->dgid.raw)); 3316 } 3317 3318 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3319 if (err < 0) 3320 return err; 3321 MLX5_SET(ads, path, stat_rate, err); 3322 MLX5_SET(ads, path, vhca_port_num, port); 3323 3324 if (attr_mask & IB_QP_TIMEOUT) 3325 MLX5_SET(ads, path, ack_timeout, 3326 alt ? attr->alt_timeout : attr->timeout); 3327 3328 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3329 return modify_raw_packet_eth_prio(dev->mdev, 3330 &qp->raw_packet_qp.sq, 3331 sl & 0xf, qp->ibqp.pd); 3332 3333 return 0; 3334 } 3335 3336 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3337 [MLX5_QP_STATE_INIT] = { 3338 [MLX5_QP_STATE_INIT] = { 3339 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3340 MLX5_QP_OPTPAR_RAE | 3341 MLX5_QP_OPTPAR_RWE | 3342 MLX5_QP_OPTPAR_PKEY_INDEX | 3343 MLX5_QP_OPTPAR_PRI_PORT | 3344 MLX5_QP_OPTPAR_LAG_TX_AFF, 3345 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3346 MLX5_QP_OPTPAR_PKEY_INDEX | 3347 MLX5_QP_OPTPAR_PRI_PORT | 3348 MLX5_QP_OPTPAR_LAG_TX_AFF, 3349 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3350 MLX5_QP_OPTPAR_Q_KEY | 3351 MLX5_QP_OPTPAR_PRI_PORT, 3352 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3353 MLX5_QP_OPTPAR_RAE | 3354 MLX5_QP_OPTPAR_RWE | 3355 MLX5_QP_OPTPAR_PKEY_INDEX | 3356 MLX5_QP_OPTPAR_PRI_PORT | 3357 MLX5_QP_OPTPAR_LAG_TX_AFF, 3358 }, 3359 [MLX5_QP_STATE_RTR] = { 3360 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3361 MLX5_QP_OPTPAR_RRE | 3362 MLX5_QP_OPTPAR_RAE | 3363 MLX5_QP_OPTPAR_RWE | 3364 MLX5_QP_OPTPAR_PKEY_INDEX | 3365 MLX5_QP_OPTPAR_LAG_TX_AFF, 3366 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3367 MLX5_QP_OPTPAR_RWE | 3368 MLX5_QP_OPTPAR_PKEY_INDEX | 3369 MLX5_QP_OPTPAR_LAG_TX_AFF, 3370 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3371 MLX5_QP_OPTPAR_Q_KEY, 3372 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3373 MLX5_QP_OPTPAR_Q_KEY, 3374 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3375 MLX5_QP_OPTPAR_RRE | 3376 MLX5_QP_OPTPAR_RAE | 3377 MLX5_QP_OPTPAR_RWE | 3378 MLX5_QP_OPTPAR_PKEY_INDEX | 3379 MLX5_QP_OPTPAR_LAG_TX_AFF, 3380 }, 3381 }, 3382 [MLX5_QP_STATE_RTR] = { 3383 [MLX5_QP_STATE_RTS] = { 3384 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3385 MLX5_QP_OPTPAR_RRE | 3386 MLX5_QP_OPTPAR_RAE | 3387 MLX5_QP_OPTPAR_RWE | 3388 MLX5_QP_OPTPAR_PM_STATE | 3389 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3390 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3391 MLX5_QP_OPTPAR_RWE | 3392 MLX5_QP_OPTPAR_PM_STATE, 3393 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3394 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3395 MLX5_QP_OPTPAR_RRE | 3396 MLX5_QP_OPTPAR_RAE | 3397 MLX5_QP_OPTPAR_RWE | 3398 MLX5_QP_OPTPAR_PM_STATE | 3399 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3400 }, 3401 }, 3402 [MLX5_QP_STATE_RTS] = { 3403 [MLX5_QP_STATE_RTS] = { 3404 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3405 MLX5_QP_OPTPAR_RAE | 3406 MLX5_QP_OPTPAR_RWE | 3407 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3408 MLX5_QP_OPTPAR_PM_STATE | 3409 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3410 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3411 MLX5_QP_OPTPAR_PM_STATE | 3412 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3413 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3414 MLX5_QP_OPTPAR_SRQN | 3415 MLX5_QP_OPTPAR_CQN_RCV, 3416 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3417 MLX5_QP_OPTPAR_RAE | 3418 MLX5_QP_OPTPAR_RWE | 3419 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3420 MLX5_QP_OPTPAR_PM_STATE | 3421 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3422 }, 3423 }, 3424 [MLX5_QP_STATE_SQER] = { 3425 [MLX5_QP_STATE_RTS] = { 3426 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3427 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3428 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3429 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3430 MLX5_QP_OPTPAR_RWE | 3431 MLX5_QP_OPTPAR_RAE | 3432 MLX5_QP_OPTPAR_RRE, 3433 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3434 MLX5_QP_OPTPAR_RWE | 3435 MLX5_QP_OPTPAR_RAE | 3436 MLX5_QP_OPTPAR_RRE, 3437 }, 3438 }, 3439 }; 3440 3441 static int ib_nr_to_mlx5_nr(int ib_mask) 3442 { 3443 switch (ib_mask) { 3444 case IB_QP_STATE: 3445 return 0; 3446 case IB_QP_CUR_STATE: 3447 return 0; 3448 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3449 return 0; 3450 case IB_QP_ACCESS_FLAGS: 3451 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3452 MLX5_QP_OPTPAR_RAE; 3453 case IB_QP_PKEY_INDEX: 3454 return MLX5_QP_OPTPAR_PKEY_INDEX; 3455 case IB_QP_PORT: 3456 return MLX5_QP_OPTPAR_PRI_PORT; 3457 case IB_QP_QKEY: 3458 return MLX5_QP_OPTPAR_Q_KEY; 3459 case IB_QP_AV: 3460 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3461 MLX5_QP_OPTPAR_PRI_PORT; 3462 case IB_QP_PATH_MTU: 3463 return 0; 3464 case IB_QP_TIMEOUT: 3465 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3466 case IB_QP_RETRY_CNT: 3467 return MLX5_QP_OPTPAR_RETRY_COUNT; 3468 case IB_QP_RNR_RETRY: 3469 return MLX5_QP_OPTPAR_RNR_RETRY; 3470 case IB_QP_RQ_PSN: 3471 return 0; 3472 case IB_QP_MAX_QP_RD_ATOMIC: 3473 return MLX5_QP_OPTPAR_SRA_MAX; 3474 case IB_QP_ALT_PATH: 3475 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3476 case IB_QP_MIN_RNR_TIMER: 3477 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3478 case IB_QP_SQ_PSN: 3479 return 0; 3480 case IB_QP_MAX_DEST_RD_ATOMIC: 3481 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3482 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3483 case IB_QP_PATH_MIG_STATE: 3484 return MLX5_QP_OPTPAR_PM_STATE; 3485 case IB_QP_CAP: 3486 return 0; 3487 case IB_QP_DEST_QPN: 3488 return 0; 3489 } 3490 return 0; 3491 } 3492 3493 static int ib_mask_to_mlx5_opt(int ib_mask) 3494 { 3495 int result = 0; 3496 int i; 3497 3498 for (i = 0; i < 8 * sizeof(int); i++) { 3499 if ((1 << i) & ib_mask) 3500 result |= ib_nr_to_mlx5_nr(1 << i); 3501 } 3502 3503 return result; 3504 } 3505 3506 static int modify_raw_packet_qp_rq( 3507 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3508 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3509 { 3510 void *in; 3511 void *rqc; 3512 int inlen; 3513 int err; 3514 3515 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3516 in = kvzalloc(inlen, GFP_KERNEL); 3517 if (!in) 3518 return -ENOMEM; 3519 3520 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3521 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3522 3523 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3524 MLX5_SET(rqc, rqc, state, new_state); 3525 3526 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3527 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3528 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3529 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3530 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3531 } else 3532 dev_info_once( 3533 &dev->ib_dev.dev, 3534 "RAW PACKET QP counters are not supported on current FW\n"); 3535 } 3536 3537 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3538 if (err) 3539 goto out; 3540 3541 rq->state = new_state; 3542 3543 out: 3544 kvfree(in); 3545 return err; 3546 } 3547 3548 static int modify_raw_packet_qp_sq( 3549 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3550 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3551 { 3552 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3553 struct mlx5_rate_limit old_rl = ibqp->rl; 3554 struct mlx5_rate_limit new_rl = old_rl; 3555 bool new_rate_added = false; 3556 u16 rl_index = 0; 3557 void *in; 3558 void *sqc; 3559 int inlen; 3560 int err; 3561 3562 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3563 in = kvzalloc(inlen, GFP_KERNEL); 3564 if (!in) 3565 return -ENOMEM; 3566 3567 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3568 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3569 3570 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3571 MLX5_SET(sqc, sqc, state, new_state); 3572 3573 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3574 if (new_state != MLX5_SQC_STATE_RDY) 3575 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3576 __func__); 3577 else 3578 new_rl = raw_qp_param->rl; 3579 } 3580 3581 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3582 if (new_rl.rate) { 3583 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3584 if (err) { 3585 pr_err("Failed configuring rate limit(err %d): \ 3586 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3587 err, new_rl.rate, new_rl.max_burst_sz, 3588 new_rl.typical_pkt_sz); 3589 3590 goto out; 3591 } 3592 new_rate_added = true; 3593 } 3594 3595 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3596 /* index 0 means no limit */ 3597 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3598 } 3599 3600 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3601 if (err) { 3602 /* Remove new rate from table if failed */ 3603 if (new_rate_added) 3604 mlx5_rl_remove_rate(dev, &new_rl); 3605 goto out; 3606 } 3607 3608 /* Only remove the old rate after new rate was set */ 3609 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3610 (new_state != MLX5_SQC_STATE_RDY)) { 3611 mlx5_rl_remove_rate(dev, &old_rl); 3612 if (new_state != MLX5_SQC_STATE_RDY) 3613 memset(&new_rl, 0, sizeof(new_rl)); 3614 } 3615 3616 ibqp->rl = new_rl; 3617 sq->state = new_state; 3618 3619 out: 3620 kvfree(in); 3621 return err; 3622 } 3623 3624 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3625 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3626 u8 tx_affinity) 3627 { 3628 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3629 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3630 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3631 int modify_rq = !!qp->rq.wqe_cnt; 3632 int modify_sq = !!qp->sq.wqe_cnt; 3633 int rq_state; 3634 int sq_state; 3635 int err; 3636 3637 switch (raw_qp_param->operation) { 3638 case MLX5_CMD_OP_RST2INIT_QP: 3639 rq_state = MLX5_RQC_STATE_RDY; 3640 sq_state = MLX5_SQC_STATE_RST; 3641 break; 3642 case MLX5_CMD_OP_2ERR_QP: 3643 rq_state = MLX5_RQC_STATE_ERR; 3644 sq_state = MLX5_SQC_STATE_ERR; 3645 break; 3646 case MLX5_CMD_OP_2RST_QP: 3647 rq_state = MLX5_RQC_STATE_RST; 3648 sq_state = MLX5_SQC_STATE_RST; 3649 break; 3650 case MLX5_CMD_OP_RTR2RTS_QP: 3651 case MLX5_CMD_OP_RTS2RTS_QP: 3652 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3653 return -EINVAL; 3654 3655 modify_rq = 0; 3656 sq_state = MLX5_SQC_STATE_RDY; 3657 break; 3658 case MLX5_CMD_OP_INIT2INIT_QP: 3659 case MLX5_CMD_OP_INIT2RTR_QP: 3660 if (raw_qp_param->set_mask) 3661 return -EINVAL; 3662 else 3663 return 0; 3664 default: 3665 WARN_ON(1); 3666 return -EINVAL; 3667 } 3668 3669 if (modify_rq) { 3670 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3671 qp->ibqp.pd); 3672 if (err) 3673 return err; 3674 } 3675 3676 if (modify_sq) { 3677 struct mlx5_flow_handle *flow_rule; 3678 3679 if (tx_affinity) { 3680 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3681 tx_affinity, 3682 qp->ibqp.pd); 3683 if (err) 3684 return err; 3685 } 3686 3687 flow_rule = create_flow_rule_vport_sq(dev, sq, 3688 raw_qp_param->port); 3689 if (IS_ERR(flow_rule)) 3690 return PTR_ERR(flow_rule); 3691 3692 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3693 raw_qp_param, qp->ibqp.pd); 3694 if (err) { 3695 if (flow_rule) 3696 mlx5_del_flow_rules(flow_rule); 3697 return err; 3698 } 3699 3700 if (flow_rule) { 3701 destroy_flow_rule_vport_sq(sq); 3702 sq->flow_rule = flow_rule; 3703 } 3704 3705 return err; 3706 } 3707 3708 return 0; 3709 } 3710 3711 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3712 struct ib_udata *udata) 3713 { 3714 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3715 udata, struct mlx5_ib_ucontext, ibucontext); 3716 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3717 atomic_t *tx_port_affinity; 3718 3719 if (ucontext) 3720 tx_port_affinity = &ucontext->tx_port_affinity; 3721 else 3722 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3723 3724 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3725 MLX5_MAX_PORTS + 1; 3726 } 3727 3728 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3729 { 3730 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3731 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3732 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3733 (qp->type == MLX5_IB_QPT_DCI)) 3734 return true; 3735 return false; 3736 } 3737 3738 static unsigned int get_tx_affinity(struct ib_qp *qp, 3739 const struct ib_qp_attr *attr, 3740 int attr_mask, u8 init, 3741 struct ib_udata *udata) 3742 { 3743 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3744 udata, struct mlx5_ib_ucontext, ibucontext); 3745 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3746 struct mlx5_ib_qp *mqp = to_mqp(qp); 3747 struct mlx5_ib_qp_base *qp_base; 3748 unsigned int tx_affinity; 3749 3750 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 3751 qp_supports_affinity(mqp))) 3752 return 0; 3753 3754 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3755 tx_affinity = mqp->gsi_lag_port; 3756 else if (init) 3757 tx_affinity = get_tx_affinity_rr(dev, udata); 3758 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 3759 tx_affinity = 3760 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 3761 else 3762 return 0; 3763 3764 qp_base = &mqp->trans_qp.base; 3765 if (ucontext) 3766 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3767 tx_affinity, qp_base->mqp.qpn, ucontext); 3768 else 3769 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3770 tx_affinity, qp_base->mqp.qpn); 3771 return tx_affinity; 3772 } 3773 3774 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3775 struct rdma_counter *counter) 3776 { 3777 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3778 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 3779 struct mlx5_ib_qp *mqp = to_mqp(qp); 3780 struct mlx5_ib_qp_base *base; 3781 u32 set_id; 3782 u32 *qpc; 3783 3784 if (counter) 3785 set_id = counter->id; 3786 else 3787 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3788 3789 base = &mqp->trans_qp.base; 3790 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 3791 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 3792 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 3793 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 3794 MLX5_QP_OPTPAR_COUNTER_SET_ID); 3795 3796 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 3797 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3798 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 3799 } 3800 3801 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3802 const struct ib_qp_attr *attr, int attr_mask, 3803 enum ib_qp_state cur_state, 3804 enum ib_qp_state new_state, 3805 const struct mlx5_ib_modify_qp *ucmd, 3806 struct mlx5_ib_modify_qp_resp *resp, 3807 struct ib_udata *udata) 3808 { 3809 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3810 [MLX5_QP_STATE_RST] = { 3811 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3812 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3813 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3814 }, 3815 [MLX5_QP_STATE_INIT] = { 3816 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3817 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3818 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3819 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3820 }, 3821 [MLX5_QP_STATE_RTR] = { 3822 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3823 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3824 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3825 }, 3826 [MLX5_QP_STATE_RTS] = { 3827 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3828 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3829 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3830 }, 3831 [MLX5_QP_STATE_SQD] = { 3832 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3833 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3834 }, 3835 [MLX5_QP_STATE_SQER] = { 3836 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3837 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3838 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3839 }, 3840 [MLX5_QP_STATE_ERR] = { 3841 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3842 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3843 } 3844 }; 3845 3846 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3847 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3848 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3849 struct mlx5_ib_cq *send_cq, *recv_cq; 3850 struct mlx5_ib_pd *pd; 3851 enum mlx5_qp_state mlx5_cur, mlx5_new; 3852 void *qpc, *pri_path, *alt_path; 3853 enum mlx5_qp_optpar optpar = 0; 3854 u32 set_id = 0; 3855 int mlx5_st; 3856 int err; 3857 u16 op; 3858 u8 tx_affinity = 0; 3859 3860 mlx5_st = to_mlx5_st(qp->type); 3861 if (mlx5_st < 0) 3862 return -EINVAL; 3863 3864 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 3865 if (!qpc) 3866 return -ENOMEM; 3867 3868 pd = to_mpd(qp->ibqp.pd); 3869 MLX5_SET(qpc, qpc, st, mlx5_st); 3870 3871 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3872 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3873 } else { 3874 switch (attr->path_mig_state) { 3875 case IB_MIG_MIGRATED: 3876 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3877 break; 3878 case IB_MIG_REARM: 3879 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 3880 break; 3881 case IB_MIG_ARMED: 3882 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 3883 break; 3884 } 3885 } 3886 3887 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 3888 cur_state == IB_QPS_RESET && 3889 new_state == IB_QPS_INIT, udata); 3890 3891 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 3892 if (tx_affinity && new_state == IB_QPS_RTR && 3893 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 3894 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 3895 3896 if (is_sqp(ibqp->qp_type)) { 3897 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 3898 MLX5_SET(qpc, qpc, log_msg_max, 8); 3899 } else if ((ibqp->qp_type == IB_QPT_UD && 3900 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 3901 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3902 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 3903 MLX5_SET(qpc, qpc, log_msg_max, 12); 3904 } else if (attr_mask & IB_QP_PATH_MTU) { 3905 if (attr->path_mtu < IB_MTU_256 || 3906 attr->path_mtu > IB_MTU_4096) { 3907 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3908 err = -EINVAL; 3909 goto out; 3910 } 3911 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 3912 MLX5_SET(qpc, qpc, log_msg_max, 3913 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 3914 } 3915 3916 if (attr_mask & IB_QP_DEST_QPN) 3917 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 3918 3919 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 3920 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 3921 3922 if (attr_mask & IB_QP_PKEY_INDEX) 3923 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 3924 3925 /* todo implement counter_index functionality */ 3926 3927 if (is_sqp(ibqp->qp_type)) 3928 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 3929 3930 if (attr_mask & IB_QP_PORT) 3931 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 3932 3933 if (attr_mask & IB_QP_AV) { 3934 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 3935 attr_mask & IB_QP_PORT ? attr->port_num : 3936 qp->port, 3937 attr_mask, 0, attr, false); 3938 if (err) 3939 goto out; 3940 } 3941 3942 if (attr_mask & IB_QP_TIMEOUT) 3943 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 3944 3945 if (attr_mask & IB_QP_ALT_PATH) { 3946 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 3947 attr->alt_port_num, 3948 attr_mask | IB_QP_PKEY_INDEX | 3949 IB_QP_TIMEOUT, 3950 0, attr, true); 3951 if (err) 3952 goto out; 3953 } 3954 3955 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3956 &send_cq, &recv_cq); 3957 3958 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3959 if (send_cq) 3960 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 3961 if (recv_cq) 3962 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 3963 3964 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 3965 3966 if (attr_mask & IB_QP_RNR_RETRY) 3967 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 3968 3969 if (attr_mask & IB_QP_RETRY_CNT) 3970 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 3971 3972 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 3973 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 3974 3975 if (attr_mask & IB_QP_SQ_PSN) 3976 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 3977 3978 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 3979 MLX5_SET(qpc, qpc, log_rra_max, 3980 ilog2(attr->max_dest_rd_atomic)); 3981 3982 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3983 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 3984 if (err) 3985 goto out; 3986 } 3987 3988 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3989 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 3990 3991 if (attr_mask & IB_QP_RQ_PSN) 3992 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 3993 3994 if (attr_mask & IB_QP_QKEY) 3995 MLX5_SET(qpc, qpc, q_key, attr->qkey); 3996 3997 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3998 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 3999 4000 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4001 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4002 qp->port) - 1; 4003 4004 /* Underlay port should be used - index 0 function per port */ 4005 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4006 port_num = 0; 4007 4008 if (ibqp->counter) 4009 set_id = ibqp->counter->id; 4010 else 4011 set_id = mlx5_ib_get_counters_id(dev, port_num); 4012 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4013 } 4014 4015 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4016 MLX5_SET(qpc, qpc, rlky, 1); 4017 4018 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4019 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4020 4021 mlx5_cur = to_mlx5_state(cur_state); 4022 mlx5_new = to_mlx5_state(new_state); 4023 4024 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4025 !optab[mlx5_cur][mlx5_new]) { 4026 err = -EINVAL; 4027 goto out; 4028 } 4029 4030 op = optab[mlx5_cur][mlx5_new]; 4031 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4032 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4033 4034 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4035 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4036 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4037 4038 raw_qp_param.operation = op; 4039 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4040 raw_qp_param.rq_q_ctr_id = set_id; 4041 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4042 } 4043 4044 if (attr_mask & IB_QP_PORT) 4045 raw_qp_param.port = attr->port_num; 4046 4047 if (attr_mask & IB_QP_RATE_LIMIT) { 4048 raw_qp_param.rl.rate = attr->rate_limit; 4049 4050 if (ucmd->burst_info.max_burst_sz) { 4051 if (attr->rate_limit && 4052 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4053 raw_qp_param.rl.max_burst_sz = 4054 ucmd->burst_info.max_burst_sz; 4055 } else { 4056 err = -EINVAL; 4057 goto out; 4058 } 4059 } 4060 4061 if (ucmd->burst_info.typical_pkt_sz) { 4062 if (attr->rate_limit && 4063 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4064 raw_qp_param.rl.typical_pkt_sz = 4065 ucmd->burst_info.typical_pkt_sz; 4066 } else { 4067 err = -EINVAL; 4068 goto out; 4069 } 4070 } 4071 4072 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4073 } 4074 4075 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4076 } else { 4077 if (udata) { 4078 /* For the kernel flows, the resp will stay zero */ 4079 resp->ece_options = 4080 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4081 ucmd->ece_options : 0; 4082 resp->response_length = sizeof(*resp); 4083 } 4084 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4085 &resp->ece_options); 4086 } 4087 4088 if (err) 4089 goto out; 4090 4091 qp->state = new_state; 4092 4093 if (attr_mask & IB_QP_ACCESS_FLAGS) 4094 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4095 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4096 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4097 if (attr_mask & IB_QP_PORT) 4098 qp->port = attr->port_num; 4099 if (attr_mask & IB_QP_ALT_PATH) 4100 qp->trans_qp.alt_port = attr->alt_port_num; 4101 4102 /* 4103 * If we moved a kernel QP to RESET, clean up all old CQ 4104 * entries and reinitialize the QP. 4105 */ 4106 if (new_state == IB_QPS_RESET && 4107 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 4108 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4109 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4110 if (send_cq != recv_cq) 4111 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4112 4113 qp->rq.head = 0; 4114 qp->rq.tail = 0; 4115 qp->sq.head = 0; 4116 qp->sq.tail = 0; 4117 qp->sq.cur_post = 0; 4118 if (qp->sq.wqe_cnt) 4119 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4120 qp->sq.last_poll = 0; 4121 qp->db.db[MLX5_RCV_DBR] = 0; 4122 qp->db.db[MLX5_SND_DBR] = 0; 4123 } 4124 4125 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4126 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4127 if (!err) 4128 qp->counter_pending = 0; 4129 } 4130 4131 out: 4132 kfree(qpc); 4133 return err; 4134 } 4135 4136 static inline bool is_valid_mask(int mask, int req, int opt) 4137 { 4138 if ((mask & req) != req) 4139 return false; 4140 4141 if (mask & ~(req | opt)) 4142 return false; 4143 4144 return true; 4145 } 4146 4147 /* check valid transition for driver QP types 4148 * for now the only QP type that this function supports is DCI 4149 */ 4150 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4151 enum ib_qp_attr_mask attr_mask) 4152 { 4153 int req = IB_QP_STATE; 4154 int opt = 0; 4155 4156 if (new_state == IB_QPS_RESET) { 4157 return is_valid_mask(attr_mask, req, opt); 4158 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4159 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4160 return is_valid_mask(attr_mask, req, opt); 4161 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4162 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4163 return is_valid_mask(attr_mask, req, opt); 4164 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4165 req |= IB_QP_PATH_MTU; 4166 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4167 return is_valid_mask(attr_mask, req, opt); 4168 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4169 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4170 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4171 opt = IB_QP_MIN_RNR_TIMER; 4172 return is_valid_mask(attr_mask, req, opt); 4173 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4174 opt = IB_QP_MIN_RNR_TIMER; 4175 return is_valid_mask(attr_mask, req, opt); 4176 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4177 return is_valid_mask(attr_mask, req, opt); 4178 } 4179 return false; 4180 } 4181 4182 /* mlx5_ib_modify_dct: modify a DCT QP 4183 * valid transitions are: 4184 * RESET to INIT: must set access_flags, pkey_index and port 4185 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4186 * mtu, gid_index and hop_limit 4187 * Other transitions and attributes are illegal 4188 */ 4189 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4190 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4191 struct ib_udata *udata) 4192 { 4193 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4194 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4195 enum ib_qp_state cur_state, new_state; 4196 int required = IB_QP_STATE; 4197 void *dctc; 4198 int err; 4199 4200 if (!(attr_mask & IB_QP_STATE)) 4201 return -EINVAL; 4202 4203 cur_state = qp->state; 4204 new_state = attr->qp_state; 4205 4206 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4207 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4208 /* 4209 * DCT doesn't initialize QP till modify command is executed, 4210 * so we need to overwrite previously set ECE field if user 4211 * provided any value except zero, which means not set/not 4212 * valid. 4213 */ 4214 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4215 4216 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4217 u16 set_id; 4218 4219 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4220 if (!is_valid_mask(attr_mask, required, 0)) 4221 return -EINVAL; 4222 4223 if (attr->port_num == 0 || 4224 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4225 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4226 attr->port_num, dev->num_ports); 4227 return -EINVAL; 4228 } 4229 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4230 MLX5_SET(dctc, dctc, rre, 1); 4231 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4232 MLX5_SET(dctc, dctc, rwe, 1); 4233 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4234 int atomic_mode; 4235 4236 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4237 if (atomic_mode < 0) 4238 return -EOPNOTSUPP; 4239 4240 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4241 MLX5_SET(dctc, dctc, rae, 1); 4242 } 4243 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4244 if (mlx5_lag_is_active(dev->mdev)) 4245 MLX5_SET(dctc, dctc, port, 4246 get_tx_affinity_rr(dev, udata)); 4247 else 4248 MLX5_SET(dctc, dctc, port, attr->port_num); 4249 4250 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4251 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4252 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4253 struct mlx5_ib_modify_qp_resp resp = {}; 4254 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4255 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4256 4257 if (udata->outlen < min_resp_len) 4258 return -EINVAL; 4259 /* 4260 * If we don't have enough space for the ECE options, 4261 * simply indicate it with resp.response_length. 4262 */ 4263 resp.response_length = (udata->outlen < sizeof(resp)) ? 4264 min_resp_len : 4265 sizeof(resp); 4266 4267 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4268 if (!is_valid_mask(attr_mask, required, 0)) 4269 return -EINVAL; 4270 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4271 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4272 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4273 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4274 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4275 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4276 4277 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4278 MLX5_ST_SZ_BYTES(create_dct_in), out, 4279 sizeof(out)); 4280 if (err) 4281 return err; 4282 resp.dctn = qp->dct.mdct.mqp.qpn; 4283 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4284 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4285 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4286 if (err) { 4287 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4288 return err; 4289 } 4290 } else { 4291 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4292 return -EINVAL; 4293 } 4294 4295 qp->state = new_state; 4296 return 0; 4297 } 4298 4299 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4300 struct mlx5_ib_qp *qp, 4301 enum ib_qp_type qp_type) 4302 { 4303 if (dev->profile != &raw_eth_profile) 4304 return true; 4305 4306 if (qp_type == IB_QPT_RAW_PACKET || qp_type == MLX5_IB_QPT_REG_UMR) 4307 return true; 4308 4309 /* Internal QP used for wc testing, with NOPs in wq */ 4310 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 4311 return true; 4312 4313 return false; 4314 } 4315 4316 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4317 int attr_mask, struct ib_udata *udata) 4318 { 4319 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4320 struct mlx5_ib_modify_qp_resp resp = {}; 4321 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4322 struct mlx5_ib_modify_qp ucmd = {}; 4323 enum ib_qp_type qp_type; 4324 enum ib_qp_state cur_state, new_state; 4325 int err = -EINVAL; 4326 4327 if (!mlx5_ib_modify_qp_allowed(dev, qp, ibqp->qp_type)) 4328 return -EOPNOTSUPP; 4329 4330 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4331 return -EOPNOTSUPP; 4332 4333 if (ibqp->rwq_ind_tbl) 4334 return -ENOSYS; 4335 4336 if (udata && udata->inlen) { 4337 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4338 return -EINVAL; 4339 4340 if (udata->inlen > sizeof(ucmd) && 4341 !ib_is_udata_cleared(udata, sizeof(ucmd), 4342 udata->inlen - sizeof(ucmd))) 4343 return -EOPNOTSUPP; 4344 4345 if (ib_copy_from_udata(&ucmd, udata, 4346 min(udata->inlen, sizeof(ucmd)))) 4347 return -EFAULT; 4348 4349 if (ucmd.comp_mask || 4350 memchr_inv(&ucmd.burst_info.reserved, 0, 4351 sizeof(ucmd.burst_info.reserved))) 4352 return -EOPNOTSUPP; 4353 4354 } 4355 4356 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4357 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4358 4359 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI : 4360 qp->type; 4361 4362 if (qp_type == MLX5_IB_QPT_DCT) 4363 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4364 4365 mutex_lock(&qp->mutex); 4366 4367 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4368 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4369 4370 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4371 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4372 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4373 attr_mask); 4374 goto out; 4375 } 4376 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4377 qp_type != MLX5_IB_QPT_DCI && 4378 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4379 attr_mask)) { 4380 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4381 cur_state, new_state, ibqp->qp_type, attr_mask); 4382 goto out; 4383 } else if (qp_type == MLX5_IB_QPT_DCI && 4384 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4385 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4386 cur_state, new_state, qp_type, attr_mask); 4387 goto out; 4388 } 4389 4390 if ((attr_mask & IB_QP_PORT) && 4391 (attr->port_num == 0 || 4392 attr->port_num > dev->num_ports)) { 4393 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4394 attr->port_num, dev->num_ports); 4395 goto out; 4396 } 4397 4398 if ((attr_mask & IB_QP_PKEY_INDEX) && 4399 attr->pkey_index >= dev->pkey_table_len) { 4400 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4401 goto out; 4402 } 4403 4404 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4405 attr->max_rd_atomic > 4406 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4407 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4408 attr->max_rd_atomic); 4409 goto out; 4410 } 4411 4412 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4413 attr->max_dest_rd_atomic > 4414 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4415 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4416 attr->max_dest_rd_atomic); 4417 goto out; 4418 } 4419 4420 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4421 err = 0; 4422 goto out; 4423 } 4424 4425 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4426 new_state, &ucmd, &resp, udata); 4427 4428 /* resp.response_length is set in ECE supported flows only */ 4429 if (!err && resp.response_length && 4430 udata->outlen >= resp.response_length) 4431 /* Return -EFAULT to the user and expect him to destroy QP. */ 4432 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4433 4434 out: 4435 mutex_unlock(&qp->mutex); 4436 return err; 4437 } 4438 4439 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4440 { 4441 switch (mlx5_state) { 4442 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4443 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4444 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4445 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4446 case MLX5_QP_STATE_SQ_DRAINING: 4447 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4448 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4449 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4450 default: return -1; 4451 } 4452 } 4453 4454 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4455 { 4456 switch (mlx5_mig_state) { 4457 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4458 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4459 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4460 default: return -1; 4461 } 4462 } 4463 4464 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4465 struct rdma_ah_attr *ah_attr, void *path) 4466 { 4467 int port = MLX5_GET(ads, path, vhca_port_num); 4468 int static_rate; 4469 4470 memset(ah_attr, 0, sizeof(*ah_attr)); 4471 4472 if (!port || port > ibdev->num_ports) 4473 return; 4474 4475 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4476 4477 rdma_ah_set_port_num(ah_attr, port); 4478 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4479 4480 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4481 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4482 4483 static_rate = MLX5_GET(ads, path, stat_rate); 4484 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0); 4485 if (MLX5_GET(ads, path, grh) || 4486 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4487 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4488 MLX5_GET(ads, path, src_addr_index), 4489 MLX5_GET(ads, path, hop_limit), 4490 MLX5_GET(ads, path, tclass)); 4491 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4492 } 4493 } 4494 4495 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4496 struct mlx5_ib_sq *sq, 4497 u8 *sq_state) 4498 { 4499 int err; 4500 4501 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4502 if (err) 4503 goto out; 4504 sq->state = *sq_state; 4505 4506 out: 4507 return err; 4508 } 4509 4510 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4511 struct mlx5_ib_rq *rq, 4512 u8 *rq_state) 4513 { 4514 void *out; 4515 void *rqc; 4516 int inlen; 4517 int err; 4518 4519 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4520 out = kvzalloc(inlen, GFP_KERNEL); 4521 if (!out) 4522 return -ENOMEM; 4523 4524 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4525 if (err) 4526 goto out; 4527 4528 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4529 *rq_state = MLX5_GET(rqc, rqc, state); 4530 rq->state = *rq_state; 4531 4532 out: 4533 kvfree(out); 4534 return err; 4535 } 4536 4537 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4538 struct mlx5_ib_qp *qp, u8 *qp_state) 4539 { 4540 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4541 [MLX5_RQC_STATE_RST] = { 4542 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4543 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4544 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4545 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4546 }, 4547 [MLX5_RQC_STATE_RDY] = { 4548 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4549 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4550 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4551 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4552 }, 4553 [MLX5_RQC_STATE_ERR] = { 4554 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4555 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4556 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4557 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4558 }, 4559 [MLX5_RQ_STATE_NA] = { 4560 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4561 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4562 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4563 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4564 }, 4565 }; 4566 4567 *qp_state = sqrq_trans[rq_state][sq_state]; 4568 4569 if (*qp_state == MLX5_QP_STATE_BAD) { 4570 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4571 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4572 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4573 return -EINVAL; 4574 } 4575 4576 if (*qp_state == MLX5_QP_STATE) 4577 *qp_state = qp->state; 4578 4579 return 0; 4580 } 4581 4582 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4583 struct mlx5_ib_qp *qp, 4584 u8 *raw_packet_qp_state) 4585 { 4586 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4587 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4588 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4589 int err; 4590 u8 sq_state = MLX5_SQ_STATE_NA; 4591 u8 rq_state = MLX5_RQ_STATE_NA; 4592 4593 if (qp->sq.wqe_cnt) { 4594 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4595 if (err) 4596 return err; 4597 } 4598 4599 if (qp->rq.wqe_cnt) { 4600 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4601 if (err) 4602 return err; 4603 } 4604 4605 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4606 raw_packet_qp_state); 4607 } 4608 4609 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4610 struct ib_qp_attr *qp_attr) 4611 { 4612 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4613 void *qpc, *pri_path, *alt_path; 4614 u32 *outb; 4615 int err; 4616 4617 outb = kzalloc(outlen, GFP_KERNEL); 4618 if (!outb) 4619 return -ENOMEM; 4620 4621 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 4622 if (err) 4623 goto out; 4624 4625 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4626 4627 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4628 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4629 qp_attr->sq_draining = 1; 4630 4631 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4632 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4633 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4634 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4635 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4636 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4637 4638 if (MLX5_GET(qpc, qpc, rre)) 4639 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4640 if (MLX5_GET(qpc, qpc, rwe)) 4641 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4642 if (MLX5_GET(qpc, qpc, rae)) 4643 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4644 4645 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4646 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4647 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4648 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4649 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4650 4651 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4652 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4653 4654 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC || 4655 qp->ibqp.qp_type == IB_QPT_XRC_INI || 4656 qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 4657 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4658 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4659 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4660 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4661 } 4662 4663 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4664 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4665 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4666 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4667 4668 out: 4669 kfree(outb); 4670 return err; 4671 } 4672 4673 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4674 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4675 struct ib_qp_init_attr *qp_init_attr) 4676 { 4677 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4678 u32 *out; 4679 u32 access_flags = 0; 4680 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4681 void *dctc; 4682 int err; 4683 int supported_mask = IB_QP_STATE | 4684 IB_QP_ACCESS_FLAGS | 4685 IB_QP_PORT | 4686 IB_QP_MIN_RNR_TIMER | 4687 IB_QP_AV | 4688 IB_QP_PATH_MTU | 4689 IB_QP_PKEY_INDEX; 4690 4691 if (qp_attr_mask & ~supported_mask) 4692 return -EINVAL; 4693 if (mqp->state != IB_QPS_RTR) 4694 return -EINVAL; 4695 4696 out = kzalloc(outlen, GFP_KERNEL); 4697 if (!out) 4698 return -ENOMEM; 4699 4700 err = mlx5_core_dct_query(dev, dct, out, outlen); 4701 if (err) 4702 goto out; 4703 4704 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4705 4706 if (qp_attr_mask & IB_QP_STATE) 4707 qp_attr->qp_state = IB_QPS_RTR; 4708 4709 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4710 if (MLX5_GET(dctc, dctc, rre)) 4711 access_flags |= IB_ACCESS_REMOTE_READ; 4712 if (MLX5_GET(dctc, dctc, rwe)) 4713 access_flags |= IB_ACCESS_REMOTE_WRITE; 4714 if (MLX5_GET(dctc, dctc, rae)) 4715 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4716 qp_attr->qp_access_flags = access_flags; 4717 } 4718 4719 if (qp_attr_mask & IB_QP_PORT) 4720 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4721 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4722 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4723 if (qp_attr_mask & IB_QP_AV) { 4724 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4725 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4726 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4727 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4728 } 4729 if (qp_attr_mask & IB_QP_PATH_MTU) 4730 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4731 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4732 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4733 out: 4734 kfree(out); 4735 return err; 4736 } 4737 4738 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4739 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4740 { 4741 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4742 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4743 int err = 0; 4744 u8 raw_packet_qp_state; 4745 4746 if (ibqp->rwq_ind_tbl) 4747 return -ENOSYS; 4748 4749 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4750 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4751 qp_init_attr); 4752 4753 /* Not all of output fields are applicable, make sure to zero them */ 4754 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4755 memset(qp_attr, 0, sizeof(*qp_attr)); 4756 4757 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 4758 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4759 qp_attr_mask, qp_init_attr); 4760 4761 mutex_lock(&qp->mutex); 4762 4763 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4764 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4765 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4766 if (err) 4767 goto out; 4768 qp->state = raw_packet_qp_state; 4769 qp_attr->port_num = 1; 4770 } else { 4771 err = query_qp_attr(dev, qp, qp_attr); 4772 if (err) 4773 goto out; 4774 } 4775 4776 qp_attr->qp_state = qp->state; 4777 qp_attr->cur_qp_state = qp_attr->qp_state; 4778 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4779 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4780 4781 if (!ibqp->uobject) { 4782 qp_attr->cap.max_send_wr = qp->sq.max_post; 4783 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4784 qp_init_attr->qp_context = ibqp->qp_context; 4785 } else { 4786 qp_attr->cap.max_send_wr = 0; 4787 qp_attr->cap.max_send_sge = 0; 4788 } 4789 4790 qp_init_attr->qp_type = ibqp->qp_type; 4791 qp_init_attr->recv_cq = ibqp->recv_cq; 4792 qp_init_attr->send_cq = ibqp->send_cq; 4793 qp_init_attr->srq = ibqp->srq; 4794 qp_attr->cap.max_inline_data = qp->max_inline_data; 4795 4796 qp_init_attr->cap = qp_attr->cap; 4797 4798 qp_init_attr->create_flags = qp->flags; 4799 4800 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4801 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4802 4803 out: 4804 mutex_unlock(&qp->mutex); 4805 return err; 4806 } 4807 4808 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 4809 { 4810 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 4811 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 4812 4813 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4814 return -EOPNOTSUPP; 4815 4816 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 4817 } 4818 4819 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4820 { 4821 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4822 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4823 4824 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 4825 } 4826 4827 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4828 { 4829 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4830 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4831 struct ib_event event; 4832 4833 if (rwq->ibwq.event_handler) { 4834 event.device = rwq->ibwq.device; 4835 event.element.wq = &rwq->ibwq; 4836 switch (type) { 4837 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4838 event.event = IB_EVENT_WQ_FATAL; 4839 break; 4840 default: 4841 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4842 return; 4843 } 4844 4845 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4846 } 4847 } 4848 4849 static int set_delay_drop(struct mlx5_ib_dev *dev) 4850 { 4851 int err = 0; 4852 4853 mutex_lock(&dev->delay_drop.lock); 4854 if (dev->delay_drop.activate) 4855 goto out; 4856 4857 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 4858 if (err) 4859 goto out; 4860 4861 dev->delay_drop.activate = true; 4862 out: 4863 mutex_unlock(&dev->delay_drop.lock); 4864 4865 if (!err) 4866 atomic_inc(&dev->delay_drop.rqs_cnt); 4867 return err; 4868 } 4869 4870 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4871 struct ib_wq_init_attr *init_attr) 4872 { 4873 struct mlx5_ib_dev *dev; 4874 int has_net_offloads; 4875 __be64 *rq_pas0; 4876 void *in; 4877 void *rqc; 4878 void *wq; 4879 int inlen; 4880 int err; 4881 4882 dev = to_mdev(pd->device); 4883 4884 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4885 in = kvzalloc(inlen, GFP_KERNEL); 4886 if (!in) 4887 return -ENOMEM; 4888 4889 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4890 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4891 MLX5_SET(rqc, rqc, mem_rq_type, 4892 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4893 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4894 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4895 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4896 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4897 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4898 MLX5_SET(wq, wq, wq_type, 4899 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 4900 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 4901 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 4902 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 4903 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 4904 err = -EOPNOTSUPP; 4905 goto out; 4906 } else { 4907 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4908 } 4909 } 4910 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4911 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 4912 /* 4913 * In Firmware number of strides in each WQE is: 4914 * "512 * 2^single_wqe_log_num_of_strides" 4915 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 4916 * accepted as 0 to 9 4917 */ 4918 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 4919 2, 3, 4, 5, 6, 7, 8, 9 }; 4920 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 4921 MLX5_SET(wq, wq, log_wqe_stride_size, 4922 rwq->single_stride_log_num_of_bytes - 4923 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 4924 MLX5_SET(wq, wq, log_wqe_num_of_strides, 4925 fw_map[rwq->log_num_strides - 4926 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 4927 } 4928 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4929 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4930 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4931 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4932 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4933 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4934 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4935 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4936 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4937 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4938 err = -EOPNOTSUPP; 4939 goto out; 4940 } 4941 } else { 4942 MLX5_SET(rqc, rqc, vsd, 1); 4943 } 4944 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4945 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4946 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4947 err = -EOPNOTSUPP; 4948 goto out; 4949 } 4950 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4951 } 4952 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4953 if (!(dev->ib_dev.attrs.raw_packet_caps & 4954 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4955 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4956 err = -EOPNOTSUPP; 4957 goto out; 4958 } 4959 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4960 } 4961 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4962 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 4963 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 4964 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4965 err = set_delay_drop(dev); 4966 if (err) { 4967 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4968 err); 4969 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 4970 } else { 4971 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4972 } 4973 } 4974 out: 4975 kvfree(in); 4976 return err; 4977 } 4978 4979 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4980 struct ib_wq_init_attr *wq_init_attr, 4981 struct mlx5_ib_create_wq *ucmd, 4982 struct mlx5_ib_rwq *rwq) 4983 { 4984 /* Sanity check RQ size before proceeding */ 4985 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4986 return -EINVAL; 4987 4988 if (!ucmd->rq_wqe_count) 4989 return -EINVAL; 4990 4991 rwq->wqe_count = ucmd->rq_wqe_count; 4992 rwq->wqe_shift = ucmd->rq_wqe_shift; 4993 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 4994 return -EINVAL; 4995 4996 rwq->log_rq_stride = rwq->wqe_shift; 4997 rwq->log_rq_size = ilog2(rwq->wqe_count); 4998 return 0; 4999 } 5000 5001 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5002 { 5003 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5004 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5005 return false; 5006 5007 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5008 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5009 return false; 5010 5011 return true; 5012 } 5013 5014 static int prepare_user_rq(struct ib_pd *pd, 5015 struct ib_wq_init_attr *init_attr, 5016 struct ib_udata *udata, 5017 struct mlx5_ib_rwq *rwq) 5018 { 5019 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5020 struct mlx5_ib_create_wq ucmd = {}; 5021 int err; 5022 size_t required_cmd_sz; 5023 5024 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 5025 single_stride_log_num_of_bytes); 5026 if (udata->inlen < required_cmd_sz) { 5027 mlx5_ib_dbg(dev, "invalid inlen\n"); 5028 return -EINVAL; 5029 } 5030 5031 if (udata->inlen > sizeof(ucmd) && 5032 !ib_is_udata_cleared(udata, sizeof(ucmd), 5033 udata->inlen - sizeof(ucmd))) { 5034 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5035 return -EOPNOTSUPP; 5036 } 5037 5038 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5039 mlx5_ib_dbg(dev, "copy failed\n"); 5040 return -EFAULT; 5041 } 5042 5043 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5044 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5045 return -EOPNOTSUPP; 5046 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5047 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5048 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5049 return -EOPNOTSUPP; 5050 } 5051 if ((ucmd.single_stride_log_num_of_bytes < 5052 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5053 (ucmd.single_stride_log_num_of_bytes > 5054 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5055 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5056 ucmd.single_stride_log_num_of_bytes, 5057 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5058 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5059 return -EINVAL; 5060 } 5061 if (!log_of_strides_valid(dev, 5062 ucmd.single_wqe_log_num_of_strides)) { 5063 mlx5_ib_dbg( 5064 dev, 5065 "Invalid log num strides (%u. Range is %u - %u)\n", 5066 ucmd.single_wqe_log_num_of_strides, 5067 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5068 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5069 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5070 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5071 return -EINVAL; 5072 } 5073 rwq->single_stride_log_num_of_bytes = 5074 ucmd.single_stride_log_num_of_bytes; 5075 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5076 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5077 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5078 } 5079 5080 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5081 if (err) { 5082 mlx5_ib_dbg(dev, "err %d\n", err); 5083 return err; 5084 } 5085 5086 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5087 if (err) { 5088 mlx5_ib_dbg(dev, "err %d\n", err); 5089 return err; 5090 } 5091 5092 rwq->user_index = ucmd.user_index; 5093 return 0; 5094 } 5095 5096 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5097 struct ib_wq_init_attr *init_attr, 5098 struct ib_udata *udata) 5099 { 5100 struct mlx5_ib_dev *dev; 5101 struct mlx5_ib_rwq *rwq; 5102 struct mlx5_ib_create_wq_resp resp = {}; 5103 size_t min_resp_len; 5104 int err; 5105 5106 if (!udata) 5107 return ERR_PTR(-ENOSYS); 5108 5109 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5110 if (udata->outlen && udata->outlen < min_resp_len) 5111 return ERR_PTR(-EINVAL); 5112 5113 if (!capable(CAP_SYS_RAWIO) && 5114 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5115 return ERR_PTR(-EPERM); 5116 5117 dev = to_mdev(pd->device); 5118 switch (init_attr->wq_type) { 5119 case IB_WQT_RQ: 5120 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5121 if (!rwq) 5122 return ERR_PTR(-ENOMEM); 5123 err = prepare_user_rq(pd, init_attr, udata, rwq); 5124 if (err) 5125 goto err; 5126 err = create_rq(rwq, pd, init_attr); 5127 if (err) 5128 goto err_user_rq; 5129 break; 5130 default: 5131 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5132 init_attr->wq_type); 5133 return ERR_PTR(-EINVAL); 5134 } 5135 5136 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5137 rwq->ibwq.state = IB_WQS_RESET; 5138 if (udata->outlen) { 5139 resp.response_length = offsetofend( 5140 struct mlx5_ib_create_wq_resp, response_length); 5141 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5142 if (err) 5143 goto err_copy; 5144 } 5145 5146 rwq->core_qp.event = mlx5_ib_wq_event; 5147 rwq->ibwq.event_handler = init_attr->event_handler; 5148 return &rwq->ibwq; 5149 5150 err_copy: 5151 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5152 err_user_rq: 5153 destroy_user_rq(dev, pd, rwq, udata); 5154 err: 5155 kfree(rwq); 5156 return ERR_PTR(err); 5157 } 5158 5159 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5160 { 5161 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5162 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5163 int ret; 5164 5165 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5166 if (ret) 5167 return ret; 5168 destroy_user_rq(dev, wq->pd, rwq, udata); 5169 kfree(rwq); 5170 return 0; 5171 } 5172 5173 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5174 struct ib_rwq_ind_table_init_attr *init_attr, 5175 struct ib_udata *udata) 5176 { 5177 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5178 to_mrwq_ind_table(ib_rwq_ind_table); 5179 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5180 int sz = 1 << init_attr->log_ind_tbl_size; 5181 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5182 size_t min_resp_len; 5183 int inlen; 5184 int err; 5185 int i; 5186 u32 *in; 5187 void *rqtc; 5188 5189 if (udata->inlen > 0 && 5190 !ib_is_udata_cleared(udata, 0, 5191 udata->inlen)) 5192 return -EOPNOTSUPP; 5193 5194 if (init_attr->log_ind_tbl_size > 5195 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5196 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5197 init_attr->log_ind_tbl_size, 5198 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5199 return -EINVAL; 5200 } 5201 5202 min_resp_len = 5203 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5204 if (udata->outlen && udata->outlen < min_resp_len) 5205 return -EINVAL; 5206 5207 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5208 in = kvzalloc(inlen, GFP_KERNEL); 5209 if (!in) 5210 return -ENOMEM; 5211 5212 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5213 5214 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5215 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5216 5217 for (i = 0; i < sz; i++) 5218 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5219 5220 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5221 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5222 5223 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5224 kvfree(in); 5225 if (err) 5226 return err; 5227 5228 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5229 if (udata->outlen) { 5230 resp.response_length = 5231 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5232 response_length); 5233 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5234 if (err) 5235 goto err_copy; 5236 } 5237 5238 return 0; 5239 5240 err_copy: 5241 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5242 return err; 5243 } 5244 5245 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5246 { 5247 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5248 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5249 5250 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5251 } 5252 5253 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5254 u32 wq_attr_mask, struct ib_udata *udata) 5255 { 5256 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5257 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5258 struct mlx5_ib_modify_wq ucmd = {}; 5259 size_t required_cmd_sz; 5260 int curr_wq_state; 5261 int wq_state; 5262 int inlen; 5263 int err; 5264 void *rqc; 5265 void *in; 5266 5267 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5268 if (udata->inlen < required_cmd_sz) 5269 return -EINVAL; 5270 5271 if (udata->inlen > sizeof(ucmd) && 5272 !ib_is_udata_cleared(udata, sizeof(ucmd), 5273 udata->inlen - sizeof(ucmd))) 5274 return -EOPNOTSUPP; 5275 5276 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5277 return -EFAULT; 5278 5279 if (ucmd.comp_mask || ucmd.reserved) 5280 return -EOPNOTSUPP; 5281 5282 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5283 in = kvzalloc(inlen, GFP_KERNEL); 5284 if (!in) 5285 return -ENOMEM; 5286 5287 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5288 5289 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5290 wq_attr->curr_wq_state : wq->state; 5291 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5292 wq_attr->wq_state : curr_wq_state; 5293 if (curr_wq_state == IB_WQS_ERR) 5294 curr_wq_state = MLX5_RQC_STATE_ERR; 5295 if (wq_state == IB_WQS_ERR) 5296 wq_state = MLX5_RQC_STATE_ERR; 5297 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5298 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5299 MLX5_SET(rqc, rqc, state, wq_state); 5300 5301 if (wq_attr_mask & IB_WQ_FLAGS) { 5302 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5303 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5304 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5305 mlx5_ib_dbg(dev, "VLAN offloads are not " 5306 "supported\n"); 5307 err = -EOPNOTSUPP; 5308 goto out; 5309 } 5310 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5311 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5312 MLX5_SET(rqc, rqc, vsd, 5313 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5314 } 5315 5316 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5317 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5318 err = -EOPNOTSUPP; 5319 goto out; 5320 } 5321 } 5322 5323 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5324 u16 set_id; 5325 5326 set_id = mlx5_ib_get_counters_id(dev, 0); 5327 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5328 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5329 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5330 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5331 } else 5332 dev_info_once( 5333 &dev->ib_dev.dev, 5334 "Receive WQ counters are not supported on current FW\n"); 5335 } 5336 5337 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5338 if (!err) 5339 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5340 5341 out: 5342 kvfree(in); 5343 return err; 5344 } 5345 5346 struct mlx5_ib_drain_cqe { 5347 struct ib_cqe cqe; 5348 struct completion done; 5349 }; 5350 5351 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5352 { 5353 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5354 struct mlx5_ib_drain_cqe, 5355 cqe); 5356 5357 complete(&cqe->done); 5358 } 5359 5360 /* This function returns only once the drained WR was completed */ 5361 static void handle_drain_completion(struct ib_cq *cq, 5362 struct mlx5_ib_drain_cqe *sdrain, 5363 struct mlx5_ib_dev *dev) 5364 { 5365 struct mlx5_core_dev *mdev = dev->mdev; 5366 5367 if (cq->poll_ctx == IB_POLL_DIRECT) { 5368 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5369 ib_process_cq_direct(cq, -1); 5370 return; 5371 } 5372 5373 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5374 struct mlx5_ib_cq *mcq = to_mcq(cq); 5375 bool triggered = false; 5376 unsigned long flags; 5377 5378 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5379 /* Make sure that the CQ handler won't run if wasn't run yet */ 5380 if (!mcq->mcq.reset_notify_added) 5381 mcq->mcq.reset_notify_added = 1; 5382 else 5383 triggered = true; 5384 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5385 5386 if (triggered) { 5387 /* Wait for any scheduled/running task to be ended */ 5388 switch (cq->poll_ctx) { 5389 case IB_POLL_SOFTIRQ: 5390 irq_poll_disable(&cq->iop); 5391 irq_poll_enable(&cq->iop); 5392 break; 5393 case IB_POLL_WORKQUEUE: 5394 cancel_work_sync(&cq->work); 5395 break; 5396 default: 5397 WARN_ON_ONCE(1); 5398 } 5399 } 5400 5401 /* Run the CQ handler - this makes sure that the drain WR will 5402 * be processed if wasn't processed yet. 5403 */ 5404 mcq->mcq.comp(&mcq->mcq, NULL); 5405 } 5406 5407 wait_for_completion(&sdrain->done); 5408 } 5409 5410 void mlx5_ib_drain_sq(struct ib_qp *qp) 5411 { 5412 struct ib_cq *cq = qp->send_cq; 5413 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5414 struct mlx5_ib_drain_cqe sdrain; 5415 const struct ib_send_wr *bad_swr; 5416 struct ib_rdma_wr swr = { 5417 .wr = { 5418 .next = NULL, 5419 { .wr_cqe = &sdrain.cqe, }, 5420 .opcode = IB_WR_RDMA_WRITE, 5421 }, 5422 }; 5423 int ret; 5424 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5425 struct mlx5_core_dev *mdev = dev->mdev; 5426 5427 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5428 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5429 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5430 return; 5431 } 5432 5433 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5434 init_completion(&sdrain.done); 5435 5436 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5437 if (ret) { 5438 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5439 return; 5440 } 5441 5442 handle_drain_completion(cq, &sdrain, dev); 5443 } 5444 5445 void mlx5_ib_drain_rq(struct ib_qp *qp) 5446 { 5447 struct ib_cq *cq = qp->recv_cq; 5448 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5449 struct mlx5_ib_drain_cqe rdrain; 5450 struct ib_recv_wr rwr = {}; 5451 const struct ib_recv_wr *bad_rwr; 5452 int ret; 5453 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5454 struct mlx5_core_dev *mdev = dev->mdev; 5455 5456 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5457 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5458 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5459 return; 5460 } 5461 5462 rwr.wr_cqe = &rdrain.cqe; 5463 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5464 init_completion(&rdrain.done); 5465 5466 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5467 if (ret) { 5468 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5469 return; 5470 } 5471 5472 handle_drain_completion(cq, &rdrain, dev); 5473 } 5474 5475 /* 5476 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5477 * the default counter 5478 */ 5479 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5480 { 5481 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5482 struct mlx5_ib_qp *mqp = to_mqp(qp); 5483 int err = 0; 5484 5485 mutex_lock(&mqp->mutex); 5486 if (mqp->state == IB_QPS_RESET) { 5487 qp->counter = counter; 5488 goto out; 5489 } 5490 5491 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5492 err = -EOPNOTSUPP; 5493 goto out; 5494 } 5495 5496 if (mqp->state == IB_QPS_RTS) { 5497 err = __mlx5_ib_qp_set_counter(qp, counter); 5498 if (!err) 5499 qp->counter = counter; 5500 5501 goto out; 5502 } 5503 5504 mqp->counter_pending = 1; 5505 qp->counter = counter; 5506 5507 out: 5508 mutex_unlock(&mqp->mutex); 5509 return err; 5510 } 5511