1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 41 /* not supported currently */ 42 static int wq_signature; 43 44 enum { 45 MLX5_IB_ACK_REQ_FREQ = 8, 46 }; 47 48 enum { 49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 51 MLX5_IB_LINK_TYPE_IB = 0, 52 MLX5_IB_LINK_TYPE_ETH = 1 53 }; 54 55 enum { 56 MLX5_IB_SQ_STRIDE = 6, 57 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 58 }; 59 60 static const u32 mlx5_ib_opcode[] = { 61 [IB_WR_SEND] = MLX5_OPCODE_SEND, 62 [IB_WR_LSO] = MLX5_OPCODE_LSO, 63 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 64 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 65 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 66 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 67 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 68 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 69 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 70 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 71 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 72 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 73 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 74 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 75 }; 76 77 struct mlx5_wqe_eth_pad { 78 u8 rsvd0[16]; 79 }; 80 81 enum raw_qp_set_mask_map { 82 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 83 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 84 }; 85 86 struct mlx5_modify_raw_qp_param { 87 u16 operation; 88 89 u32 set_mask; /* raw_qp_set_mask_map */ 90 91 struct mlx5_rate_limit rl; 92 93 u8 rq_q_ctr_id; 94 }; 95 96 static void get_cqs(enum ib_qp_type qp_type, 97 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 98 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 99 100 static int is_qp0(enum ib_qp_type qp_type) 101 { 102 return qp_type == IB_QPT_SMI; 103 } 104 105 static int is_sqp(enum ib_qp_type qp_type) 106 { 107 return is_qp0(qp_type) || is_qp1(qp_type); 108 } 109 110 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 111 { 112 return mlx5_buf_offset(&qp->buf, offset); 113 } 114 115 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 116 { 117 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 118 } 119 120 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 121 { 122 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 123 } 124 125 /** 126 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 127 * 128 * @qp: QP to copy from. 129 * @send: copy from the send queue when non-zero, use the receive queue 130 * otherwise. 131 * @wqe_index: index to start copying from. For send work queues, the 132 * wqe_index is in units of MLX5_SEND_WQE_BB. 133 * For receive work queue, it is the number of work queue 134 * element in the queue. 135 * @buffer: destination buffer. 136 * @length: maximum number of bytes to copy. 137 * 138 * Copies at least a single WQE, but may copy more data. 139 * 140 * Return: the number of bytes copied, or an error code. 141 */ 142 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 143 void *buffer, u32 length, 144 struct mlx5_ib_qp_base *base) 145 { 146 struct ib_device *ibdev = qp->ibqp.device; 147 struct mlx5_ib_dev *dev = to_mdev(ibdev); 148 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 149 size_t offset; 150 size_t wq_end; 151 struct ib_umem *umem = base->ubuffer.umem; 152 u32 first_copy_length; 153 int wqe_length; 154 int ret; 155 156 if (wq->wqe_cnt == 0) { 157 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 158 qp->ibqp.qp_type); 159 return -EINVAL; 160 } 161 162 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 163 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 164 165 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 166 return -EINVAL; 167 168 if (offset > umem->length || 169 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 170 return -EINVAL; 171 172 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 173 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 174 if (ret) 175 return ret; 176 177 if (send) { 178 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 179 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 180 181 wqe_length = ds * MLX5_WQE_DS_UNITS; 182 } else { 183 wqe_length = 1 << wq->wqe_shift; 184 } 185 186 if (wqe_length <= first_copy_length) 187 return first_copy_length; 188 189 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 190 wqe_length - first_copy_length); 191 if (ret) 192 return ret; 193 194 return wqe_length; 195 } 196 197 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 198 { 199 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 200 struct ib_event event; 201 202 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 203 /* This event is only valid for trans_qps */ 204 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 205 } 206 207 if (ibqp->event_handler) { 208 event.device = ibqp->device; 209 event.element.qp = ibqp; 210 switch (type) { 211 case MLX5_EVENT_TYPE_PATH_MIG: 212 event.event = IB_EVENT_PATH_MIG; 213 break; 214 case MLX5_EVENT_TYPE_COMM_EST: 215 event.event = IB_EVENT_COMM_EST; 216 break; 217 case MLX5_EVENT_TYPE_SQ_DRAINED: 218 event.event = IB_EVENT_SQ_DRAINED; 219 break; 220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 221 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 222 break; 223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 224 event.event = IB_EVENT_QP_FATAL; 225 break; 226 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 227 event.event = IB_EVENT_PATH_MIG_ERR; 228 break; 229 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 230 event.event = IB_EVENT_QP_REQ_ERR; 231 break; 232 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 233 event.event = IB_EVENT_QP_ACCESS_ERR; 234 break; 235 default: 236 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 237 return; 238 } 239 240 ibqp->event_handler(&event, ibqp->qp_context); 241 } 242 } 243 244 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 245 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 246 { 247 int wqe_size; 248 int wq_size; 249 250 /* Sanity check RQ size before proceeding */ 251 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 252 return -EINVAL; 253 254 if (!has_rq) { 255 qp->rq.max_gs = 0; 256 qp->rq.wqe_cnt = 0; 257 qp->rq.wqe_shift = 0; 258 cap->max_recv_wr = 0; 259 cap->max_recv_sge = 0; 260 } else { 261 if (ucmd) { 262 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 263 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 264 return -EINVAL; 265 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 266 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 267 return -EINVAL; 268 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 269 qp->rq.max_post = qp->rq.wqe_cnt; 270 } else { 271 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 272 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 273 wqe_size = roundup_pow_of_two(wqe_size); 274 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 275 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 276 qp->rq.wqe_cnt = wq_size / wqe_size; 277 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 278 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 279 wqe_size, 280 MLX5_CAP_GEN(dev->mdev, 281 max_wqe_sz_rq)); 282 return -EINVAL; 283 } 284 qp->rq.wqe_shift = ilog2(wqe_size); 285 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 286 qp->rq.max_post = qp->rq.wqe_cnt; 287 } 288 } 289 290 return 0; 291 } 292 293 static int sq_overhead(struct ib_qp_init_attr *attr) 294 { 295 int size = 0; 296 297 switch (attr->qp_type) { 298 case IB_QPT_XRC_INI: 299 size += sizeof(struct mlx5_wqe_xrc_seg); 300 /* fall through */ 301 case IB_QPT_RC: 302 size += sizeof(struct mlx5_wqe_ctrl_seg) + 303 max(sizeof(struct mlx5_wqe_atomic_seg) + 304 sizeof(struct mlx5_wqe_raddr_seg), 305 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 306 sizeof(struct mlx5_mkey_seg) + 307 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 308 MLX5_IB_UMR_OCTOWORD); 309 break; 310 311 case IB_QPT_XRC_TGT: 312 return 0; 313 314 case IB_QPT_UC: 315 size += sizeof(struct mlx5_wqe_ctrl_seg) + 316 max(sizeof(struct mlx5_wqe_raddr_seg), 317 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 318 sizeof(struct mlx5_mkey_seg)); 319 break; 320 321 case IB_QPT_UD: 322 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 323 size += sizeof(struct mlx5_wqe_eth_pad) + 324 sizeof(struct mlx5_wqe_eth_seg); 325 /* fall through */ 326 case IB_QPT_SMI: 327 case MLX5_IB_QPT_HW_GSI: 328 size += sizeof(struct mlx5_wqe_ctrl_seg) + 329 sizeof(struct mlx5_wqe_datagram_seg); 330 break; 331 332 case MLX5_IB_QPT_REG_UMR: 333 size += sizeof(struct mlx5_wqe_ctrl_seg) + 334 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 335 sizeof(struct mlx5_mkey_seg); 336 break; 337 338 default: 339 return -EINVAL; 340 } 341 342 return size; 343 } 344 345 static int calc_send_wqe(struct ib_qp_init_attr *attr) 346 { 347 int inl_size = 0; 348 int size; 349 350 size = sq_overhead(attr); 351 if (size < 0) 352 return size; 353 354 if (attr->cap.max_inline_data) { 355 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 356 attr->cap.max_inline_data; 357 } 358 359 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 360 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 361 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 362 return MLX5_SIG_WQE_SIZE; 363 else 364 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 365 } 366 367 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 368 { 369 int max_sge; 370 371 if (attr->qp_type == IB_QPT_RC) 372 max_sge = (min_t(int, wqe_size, 512) - 373 sizeof(struct mlx5_wqe_ctrl_seg) - 374 sizeof(struct mlx5_wqe_raddr_seg)) / 375 sizeof(struct mlx5_wqe_data_seg); 376 else if (attr->qp_type == IB_QPT_XRC_INI) 377 max_sge = (min_t(int, wqe_size, 512) - 378 sizeof(struct mlx5_wqe_ctrl_seg) - 379 sizeof(struct mlx5_wqe_xrc_seg) - 380 sizeof(struct mlx5_wqe_raddr_seg)) / 381 sizeof(struct mlx5_wqe_data_seg); 382 else 383 max_sge = (wqe_size - sq_overhead(attr)) / 384 sizeof(struct mlx5_wqe_data_seg); 385 386 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 387 sizeof(struct mlx5_wqe_data_seg)); 388 } 389 390 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 391 struct mlx5_ib_qp *qp) 392 { 393 int wqe_size; 394 int wq_size; 395 396 if (!attr->cap.max_send_wr) 397 return 0; 398 399 wqe_size = calc_send_wqe(attr); 400 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 401 if (wqe_size < 0) 402 return wqe_size; 403 404 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 405 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 406 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 407 return -EINVAL; 408 } 409 410 qp->max_inline_data = wqe_size - sq_overhead(attr) - 411 sizeof(struct mlx5_wqe_inline_seg); 412 attr->cap.max_inline_data = qp->max_inline_data; 413 414 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 415 qp->signature_en = true; 416 417 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 418 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 420 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 421 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 422 qp->sq.wqe_cnt, 423 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 424 return -ENOMEM; 425 } 426 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 427 qp->sq.max_gs = get_send_sge(attr, wqe_size); 428 if (qp->sq.max_gs < attr->cap.max_send_sge) 429 return -ENOMEM; 430 431 attr->cap.max_send_sge = qp->sq.max_gs; 432 qp->sq.max_post = wq_size / wqe_size; 433 attr->cap.max_send_wr = qp->sq.max_post; 434 435 return wq_size; 436 } 437 438 static int set_user_buf_size(struct mlx5_ib_dev *dev, 439 struct mlx5_ib_qp *qp, 440 struct mlx5_ib_create_qp *ucmd, 441 struct mlx5_ib_qp_base *base, 442 struct ib_qp_init_attr *attr) 443 { 444 int desc_sz = 1 << qp->sq.wqe_shift; 445 446 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 447 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 448 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 449 return -EINVAL; 450 } 451 452 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 453 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 454 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 455 return -EINVAL; 456 } 457 458 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 459 460 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 461 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 462 qp->sq.wqe_cnt, 463 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 464 return -EINVAL; 465 } 466 467 if (attr->qp_type == IB_QPT_RAW_PACKET || 468 qp->flags & MLX5_IB_QP_UNDERLAY) { 469 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 470 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 471 } else { 472 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 473 (qp->sq.wqe_cnt << 6); 474 } 475 476 return 0; 477 } 478 479 static int qp_has_rq(struct ib_qp_init_attr *attr) 480 { 481 if (attr->qp_type == IB_QPT_XRC_INI || 482 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 483 attr->qp_type == MLX5_IB_QPT_REG_UMR || 484 !attr->cap.max_recv_wr) 485 return 0; 486 487 return 1; 488 } 489 490 enum { 491 /* this is the first blue flame register in the array of bfregs assigned 492 * to a processes. Since we do not use it for blue flame but rather 493 * regular 64 bit doorbells, we do not need a lock for maintaiing 494 * "odd/even" order 495 */ 496 NUM_NON_BLUE_FLAME_BFREGS = 1, 497 }; 498 499 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 500 { 501 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 502 } 503 504 static int num_med_bfreg(struct mlx5_ib_dev *dev, 505 struct mlx5_bfreg_info *bfregi) 506 { 507 int n; 508 509 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 510 NUM_NON_BLUE_FLAME_BFREGS; 511 512 return n >= 0 ? n : 0; 513 } 514 515 static int first_med_bfreg(struct mlx5_ib_dev *dev, 516 struct mlx5_bfreg_info *bfregi) 517 { 518 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 519 } 520 521 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 522 struct mlx5_bfreg_info *bfregi) 523 { 524 int med; 525 526 med = num_med_bfreg(dev, bfregi); 527 return ++med; 528 } 529 530 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 531 struct mlx5_bfreg_info *bfregi) 532 { 533 int i; 534 535 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 536 if (!bfregi->count[i]) { 537 bfregi->count[i]++; 538 return i; 539 } 540 } 541 542 return -ENOMEM; 543 } 544 545 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 546 struct mlx5_bfreg_info *bfregi) 547 { 548 int minidx = first_med_bfreg(dev, bfregi); 549 int i; 550 551 if (minidx < 0) 552 return minidx; 553 554 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 555 if (bfregi->count[i] < bfregi->count[minidx]) 556 minidx = i; 557 if (!bfregi->count[minidx]) 558 break; 559 } 560 561 bfregi->count[minidx]++; 562 return minidx; 563 } 564 565 static int alloc_bfreg(struct mlx5_ib_dev *dev, 566 struct mlx5_bfreg_info *bfregi, 567 enum mlx5_ib_latency_class lat) 568 { 569 int bfregn = -EINVAL; 570 571 mutex_lock(&bfregi->lock); 572 switch (lat) { 573 case MLX5_IB_LATENCY_CLASS_LOW: 574 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 575 bfregn = 0; 576 bfregi->count[bfregn]++; 577 break; 578 579 case MLX5_IB_LATENCY_CLASS_MEDIUM: 580 if (bfregi->ver < 2) 581 bfregn = -ENOMEM; 582 else 583 bfregn = alloc_med_class_bfreg(dev, bfregi); 584 break; 585 586 case MLX5_IB_LATENCY_CLASS_HIGH: 587 if (bfregi->ver < 2) 588 bfregn = -ENOMEM; 589 else 590 bfregn = alloc_high_class_bfreg(dev, bfregi); 591 break; 592 } 593 mutex_unlock(&bfregi->lock); 594 595 return bfregn; 596 } 597 598 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 599 { 600 mutex_lock(&bfregi->lock); 601 bfregi->count[bfregn]--; 602 mutex_unlock(&bfregi->lock); 603 } 604 605 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 606 { 607 switch (state) { 608 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 609 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 610 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 611 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 612 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 613 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 614 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 615 default: return -1; 616 } 617 } 618 619 static int to_mlx5_st(enum ib_qp_type type) 620 { 621 switch (type) { 622 case IB_QPT_RC: return MLX5_QP_ST_RC; 623 case IB_QPT_UC: return MLX5_QP_ST_UC; 624 case IB_QPT_UD: return MLX5_QP_ST_UD; 625 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 626 case IB_QPT_XRC_INI: 627 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 628 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 629 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 630 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 631 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 632 case IB_QPT_RAW_PACKET: 633 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 634 case IB_QPT_MAX: 635 default: return -EINVAL; 636 } 637 } 638 639 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 640 struct mlx5_ib_cq *recv_cq); 641 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 642 struct mlx5_ib_cq *recv_cq); 643 644 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 645 struct mlx5_bfreg_info *bfregi, int bfregn, 646 bool dyn_bfreg) 647 { 648 int bfregs_per_sys_page; 649 int index_of_sys_page; 650 int offset; 651 652 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 653 MLX5_NON_FP_BFREGS_PER_UAR; 654 index_of_sys_page = bfregn / bfregs_per_sys_page; 655 656 if (dyn_bfreg) { 657 index_of_sys_page += bfregi->num_static_sys_pages; 658 if (bfregn > bfregi->num_dyn_bfregs || 659 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 660 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 661 return -EINVAL; 662 } 663 } 664 665 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 666 return bfregi->sys_pages[index_of_sys_page] + offset; 667 } 668 669 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 670 struct ib_pd *pd, 671 unsigned long addr, size_t size, 672 struct ib_umem **umem, 673 int *npages, int *page_shift, int *ncont, 674 u32 *offset) 675 { 676 int err; 677 678 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 679 if (IS_ERR(*umem)) { 680 mlx5_ib_dbg(dev, "umem_get failed\n"); 681 return PTR_ERR(*umem); 682 } 683 684 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 685 686 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 687 if (err) { 688 mlx5_ib_warn(dev, "bad offset\n"); 689 goto err_umem; 690 } 691 692 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 693 addr, size, *npages, *page_shift, *ncont, *offset); 694 695 return 0; 696 697 err_umem: 698 ib_umem_release(*umem); 699 *umem = NULL; 700 701 return err; 702 } 703 704 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 705 struct mlx5_ib_rwq *rwq) 706 { 707 struct mlx5_ib_ucontext *context; 708 709 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 710 atomic_dec(&dev->delay_drop.rqs_cnt); 711 712 context = to_mucontext(pd->uobject->context); 713 mlx5_ib_db_unmap_user(context, &rwq->db); 714 if (rwq->umem) 715 ib_umem_release(rwq->umem); 716 } 717 718 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 719 struct mlx5_ib_rwq *rwq, 720 struct mlx5_ib_create_wq *ucmd) 721 { 722 struct mlx5_ib_ucontext *context; 723 int page_shift = 0; 724 int npages; 725 u32 offset = 0; 726 int ncont = 0; 727 int err; 728 729 if (!ucmd->buf_addr) 730 return -EINVAL; 731 732 context = to_mucontext(pd->uobject->context); 733 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 734 rwq->buf_size, 0, 0); 735 if (IS_ERR(rwq->umem)) { 736 mlx5_ib_dbg(dev, "umem_get failed\n"); 737 err = PTR_ERR(rwq->umem); 738 return err; 739 } 740 741 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 742 &ncont, NULL); 743 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 744 &rwq->rq_page_offset); 745 if (err) { 746 mlx5_ib_warn(dev, "bad offset\n"); 747 goto err_umem; 748 } 749 750 rwq->rq_num_pas = ncont; 751 rwq->page_shift = page_shift; 752 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 753 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 754 755 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 756 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 757 npages, page_shift, ncont, offset); 758 759 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 760 if (err) { 761 mlx5_ib_dbg(dev, "map failed\n"); 762 goto err_umem; 763 } 764 765 rwq->create_type = MLX5_WQ_USER; 766 return 0; 767 768 err_umem: 769 ib_umem_release(rwq->umem); 770 return err; 771 } 772 773 static int adjust_bfregn(struct mlx5_ib_dev *dev, 774 struct mlx5_bfreg_info *bfregi, int bfregn) 775 { 776 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 777 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 778 } 779 780 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 781 struct mlx5_ib_qp *qp, struct ib_udata *udata, 782 struct ib_qp_init_attr *attr, 783 u32 **in, 784 struct mlx5_ib_create_qp_resp *resp, int *inlen, 785 struct mlx5_ib_qp_base *base) 786 { 787 struct mlx5_ib_ucontext *context; 788 struct mlx5_ib_create_qp ucmd; 789 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 790 int page_shift = 0; 791 int uar_index = 0; 792 int npages; 793 u32 offset = 0; 794 int bfregn; 795 int ncont = 0; 796 __be64 *pas; 797 void *qpc; 798 int err; 799 800 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 801 if (err) { 802 mlx5_ib_dbg(dev, "copy failed\n"); 803 return err; 804 } 805 806 context = to_mucontext(pd->uobject->context); 807 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 808 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 809 ucmd.bfreg_index, true); 810 if (uar_index < 0) 811 return uar_index; 812 813 bfregn = MLX5_IB_INVALID_BFREG; 814 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 815 /* 816 * TBD: should come from the verbs when we have the API 817 */ 818 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 819 bfregn = MLX5_CROSS_CHANNEL_BFREG; 820 } 821 else { 822 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 823 if (bfregn < 0) { 824 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 825 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 826 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 827 if (bfregn < 0) { 828 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 829 mlx5_ib_dbg(dev, "reverting to high latency\n"); 830 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 831 if (bfregn < 0) { 832 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 833 return bfregn; 834 } 835 } 836 } 837 } 838 839 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 840 if (bfregn != MLX5_IB_INVALID_BFREG) 841 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 842 false); 843 844 qp->rq.offset = 0; 845 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 846 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 847 848 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 849 if (err) 850 goto err_bfreg; 851 852 if (ucmd.buf_addr && ubuffer->buf_size) { 853 ubuffer->buf_addr = ucmd.buf_addr; 854 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 855 ubuffer->buf_size, 856 &ubuffer->umem, &npages, &page_shift, 857 &ncont, &offset); 858 if (err) 859 goto err_bfreg; 860 } else { 861 ubuffer->umem = NULL; 862 } 863 864 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 865 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 866 *in = kvzalloc(*inlen, GFP_KERNEL); 867 if (!*in) { 868 err = -ENOMEM; 869 goto err_umem; 870 } 871 872 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 873 if (ubuffer->umem) 874 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 875 876 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 877 878 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 879 MLX5_SET(qpc, qpc, page_offset, offset); 880 881 MLX5_SET(qpc, qpc, uar_page, uar_index); 882 if (bfregn != MLX5_IB_INVALID_BFREG) 883 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 884 else 885 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 886 qp->bfregn = bfregn; 887 888 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 889 if (err) { 890 mlx5_ib_dbg(dev, "map failed\n"); 891 goto err_free; 892 } 893 894 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 895 if (err) { 896 mlx5_ib_dbg(dev, "copy failed\n"); 897 goto err_unmap; 898 } 899 qp->create_type = MLX5_QP_USER; 900 901 return 0; 902 903 err_unmap: 904 mlx5_ib_db_unmap_user(context, &qp->db); 905 906 err_free: 907 kvfree(*in); 908 909 err_umem: 910 if (ubuffer->umem) 911 ib_umem_release(ubuffer->umem); 912 913 err_bfreg: 914 if (bfregn != MLX5_IB_INVALID_BFREG) 915 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 916 return err; 917 } 918 919 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 920 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 921 { 922 struct mlx5_ib_ucontext *context; 923 924 context = to_mucontext(pd->uobject->context); 925 mlx5_ib_db_unmap_user(context, &qp->db); 926 if (base->ubuffer.umem) 927 ib_umem_release(base->ubuffer.umem); 928 929 /* 930 * Free only the BFREGs which are handled by the kernel. 931 * BFREGs of UARs allocated dynamically are handled by user. 932 */ 933 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 934 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 935 } 936 937 static int create_kernel_qp(struct mlx5_ib_dev *dev, 938 struct ib_qp_init_attr *init_attr, 939 struct mlx5_ib_qp *qp, 940 u32 **in, int *inlen, 941 struct mlx5_ib_qp_base *base) 942 { 943 int uar_index; 944 void *qpc; 945 int err; 946 947 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 948 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 949 IB_QP_CREATE_IPOIB_UD_LSO | 950 IB_QP_CREATE_NETIF_QP | 951 mlx5_ib_create_qp_sqpn_qp1())) 952 return -EINVAL; 953 954 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 955 qp->bf.bfreg = &dev->fp_bfreg; 956 else 957 qp->bf.bfreg = &dev->bfreg; 958 959 /* We need to divide by two since each register is comprised of 960 * two buffers of identical size, namely odd and even 961 */ 962 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 963 uar_index = qp->bf.bfreg->index; 964 965 err = calc_sq_size(dev, init_attr, qp); 966 if (err < 0) { 967 mlx5_ib_dbg(dev, "err %d\n", err); 968 return err; 969 } 970 971 qp->rq.offset = 0; 972 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 973 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 974 975 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 976 if (err) { 977 mlx5_ib_dbg(dev, "err %d\n", err); 978 return err; 979 } 980 981 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 982 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 983 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 984 *in = kvzalloc(*inlen, GFP_KERNEL); 985 if (!*in) { 986 err = -ENOMEM; 987 goto err_buf; 988 } 989 990 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 991 MLX5_SET(qpc, qpc, uar_page, uar_index); 992 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 993 994 /* Set "fast registration enabled" for all kernel QPs */ 995 MLX5_SET(qpc, qpc, fre, 1); 996 MLX5_SET(qpc, qpc, rlky, 1); 997 998 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 999 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1000 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1001 } 1002 1003 mlx5_fill_page_array(&qp->buf, 1004 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 1005 1006 err = mlx5_db_alloc(dev->mdev, &qp->db); 1007 if (err) { 1008 mlx5_ib_dbg(dev, "err %d\n", err); 1009 goto err_free; 1010 } 1011 1012 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1013 sizeof(*qp->sq.wrid), GFP_KERNEL); 1014 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1015 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1016 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1017 sizeof(*qp->rq.wrid), GFP_KERNEL); 1018 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1019 sizeof(*qp->sq.w_list), GFP_KERNEL); 1020 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1021 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1022 1023 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1024 !qp->sq.w_list || !qp->sq.wqe_head) { 1025 err = -ENOMEM; 1026 goto err_wrid; 1027 } 1028 qp->create_type = MLX5_QP_KERNEL; 1029 1030 return 0; 1031 1032 err_wrid: 1033 kvfree(qp->sq.wqe_head); 1034 kvfree(qp->sq.w_list); 1035 kvfree(qp->sq.wrid); 1036 kvfree(qp->sq.wr_data); 1037 kvfree(qp->rq.wrid); 1038 mlx5_db_free(dev->mdev, &qp->db); 1039 1040 err_free: 1041 kvfree(*in); 1042 1043 err_buf: 1044 mlx5_buf_free(dev->mdev, &qp->buf); 1045 return err; 1046 } 1047 1048 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1049 { 1050 kvfree(qp->sq.wqe_head); 1051 kvfree(qp->sq.w_list); 1052 kvfree(qp->sq.wrid); 1053 kvfree(qp->sq.wr_data); 1054 kvfree(qp->rq.wrid); 1055 mlx5_db_free(dev->mdev, &qp->db); 1056 mlx5_buf_free(dev->mdev, &qp->buf); 1057 } 1058 1059 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1060 { 1061 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1062 (attr->qp_type == MLX5_IB_QPT_DCI) || 1063 (attr->qp_type == IB_QPT_XRC_INI)) 1064 return MLX5_SRQ_RQ; 1065 else if (!qp->has_rq) 1066 return MLX5_ZERO_LEN_RQ; 1067 else 1068 return MLX5_NON_ZERO_RQ; 1069 } 1070 1071 static int is_connected(enum ib_qp_type qp_type) 1072 { 1073 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1074 return 1; 1075 1076 return 0; 1077 } 1078 1079 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1080 struct mlx5_ib_qp *qp, 1081 struct mlx5_ib_sq *sq, u32 tdn) 1082 { 1083 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1084 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1085 1086 MLX5_SET(tisc, tisc, transport_domain, tdn); 1087 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1088 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1089 1090 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1091 } 1092 1093 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1094 struct mlx5_ib_sq *sq) 1095 { 1096 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1097 } 1098 1099 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1100 struct mlx5_ib_sq *sq) 1101 { 1102 if (sq->flow_rule) 1103 mlx5_del_flow_rules(sq->flow_rule); 1104 } 1105 1106 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1107 struct mlx5_ib_sq *sq, void *qpin, 1108 struct ib_pd *pd) 1109 { 1110 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1111 __be64 *pas; 1112 void *in; 1113 void *sqc; 1114 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1115 void *wq; 1116 int inlen; 1117 int err; 1118 int page_shift = 0; 1119 int npages; 1120 int ncont = 0; 1121 u32 offset = 0; 1122 1123 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1124 &sq->ubuffer.umem, &npages, &page_shift, 1125 &ncont, &offset); 1126 if (err) 1127 return err; 1128 1129 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1130 in = kvzalloc(inlen, GFP_KERNEL); 1131 if (!in) { 1132 err = -ENOMEM; 1133 goto err_umem; 1134 } 1135 1136 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1137 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1138 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1139 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1140 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1141 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1142 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1143 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1144 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1145 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1146 MLX5_CAP_ETH(dev->mdev, swp)) 1147 MLX5_SET(sqc, sqc, allow_swp, 1); 1148 1149 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1150 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1151 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1152 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1153 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1154 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1155 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1156 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1157 MLX5_SET(wq, wq, page_offset, offset); 1158 1159 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1160 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1161 1162 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1163 1164 kvfree(in); 1165 1166 if (err) 1167 goto err_umem; 1168 1169 err = create_flow_rule_vport_sq(dev, sq); 1170 if (err) 1171 goto err_flow; 1172 1173 return 0; 1174 1175 err_flow: 1176 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1177 1178 err_umem: 1179 ib_umem_release(sq->ubuffer.umem); 1180 sq->ubuffer.umem = NULL; 1181 1182 return err; 1183 } 1184 1185 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1186 struct mlx5_ib_sq *sq) 1187 { 1188 destroy_flow_rule_vport_sq(dev, sq); 1189 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1190 ib_umem_release(sq->ubuffer.umem); 1191 } 1192 1193 static size_t get_rq_pas_size(void *qpc) 1194 { 1195 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1196 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1197 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1198 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1199 u32 po_quanta = 1 << (log_page_size - 6); 1200 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1201 u32 page_size = 1 << log_page_size; 1202 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1203 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1204 1205 return rq_num_pas * sizeof(u64); 1206 } 1207 1208 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1209 struct mlx5_ib_rq *rq, void *qpin, 1210 size_t qpinlen) 1211 { 1212 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1213 __be64 *pas; 1214 __be64 *qp_pas; 1215 void *in; 1216 void *rqc; 1217 void *wq; 1218 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1219 size_t rq_pas_size = get_rq_pas_size(qpc); 1220 size_t inlen; 1221 int err; 1222 1223 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1224 return -EINVAL; 1225 1226 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1227 in = kvzalloc(inlen, GFP_KERNEL); 1228 if (!in) 1229 return -ENOMEM; 1230 1231 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1232 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1233 MLX5_SET(rqc, rqc, vsd, 1); 1234 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1235 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1236 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1237 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1238 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1239 1240 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1241 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1242 1243 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1244 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1245 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1246 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1247 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1248 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1249 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1250 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1251 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1252 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1253 1254 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1255 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1256 memcpy(pas, qp_pas, rq_pas_size); 1257 1258 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1259 1260 kvfree(in); 1261 1262 return err; 1263 } 1264 1265 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1266 struct mlx5_ib_rq *rq) 1267 { 1268 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1269 } 1270 1271 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1272 { 1273 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1274 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1275 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1276 } 1277 1278 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1279 struct mlx5_ib_rq *rq, u32 tdn, 1280 bool tunnel_offload_en) 1281 { 1282 u32 *in; 1283 void *tirc; 1284 int inlen; 1285 int err; 1286 1287 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1288 in = kvzalloc(inlen, GFP_KERNEL); 1289 if (!in) 1290 return -ENOMEM; 1291 1292 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1293 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1294 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1295 MLX5_SET(tirc, tirc, transport_domain, tdn); 1296 if (tunnel_offload_en) 1297 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1298 1299 if (dev->rep) 1300 MLX5_SET(tirc, tirc, self_lb_block, 1301 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1302 1303 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1304 1305 kvfree(in); 1306 1307 return err; 1308 } 1309 1310 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1311 struct mlx5_ib_rq *rq) 1312 { 1313 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1314 } 1315 1316 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1317 u32 *in, size_t inlen, 1318 struct ib_pd *pd) 1319 { 1320 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1321 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1322 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1323 struct ib_uobject *uobj = pd->uobject; 1324 struct ib_ucontext *ucontext = uobj->context; 1325 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1326 int err; 1327 u32 tdn = mucontext->tdn; 1328 1329 if (qp->sq.wqe_cnt) { 1330 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1331 if (err) 1332 return err; 1333 1334 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1335 if (err) 1336 goto err_destroy_tis; 1337 1338 sq->base.container_mibqp = qp; 1339 sq->base.mqp.event = mlx5_ib_qp_event; 1340 } 1341 1342 if (qp->rq.wqe_cnt) { 1343 rq->base.container_mibqp = qp; 1344 1345 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1346 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1347 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1348 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1349 err = create_raw_packet_qp_rq(dev, rq, in, inlen); 1350 if (err) 1351 goto err_destroy_sq; 1352 1353 1354 err = create_raw_packet_qp_tir(dev, rq, tdn, 1355 qp->tunnel_offload_en); 1356 if (err) 1357 goto err_destroy_rq; 1358 } 1359 1360 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1361 rq->base.mqp.qpn; 1362 1363 return 0; 1364 1365 err_destroy_rq: 1366 destroy_raw_packet_qp_rq(dev, rq); 1367 err_destroy_sq: 1368 if (!qp->sq.wqe_cnt) 1369 return err; 1370 destroy_raw_packet_qp_sq(dev, sq); 1371 err_destroy_tis: 1372 destroy_raw_packet_qp_tis(dev, sq); 1373 1374 return err; 1375 } 1376 1377 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1378 struct mlx5_ib_qp *qp) 1379 { 1380 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1381 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1382 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1383 1384 if (qp->rq.wqe_cnt) { 1385 destroy_raw_packet_qp_tir(dev, rq); 1386 destroy_raw_packet_qp_rq(dev, rq); 1387 } 1388 1389 if (qp->sq.wqe_cnt) { 1390 destroy_raw_packet_qp_sq(dev, sq); 1391 destroy_raw_packet_qp_tis(dev, sq); 1392 } 1393 } 1394 1395 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1396 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1397 { 1398 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1399 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1400 1401 sq->sq = &qp->sq; 1402 rq->rq = &qp->rq; 1403 sq->doorbell = &qp->db; 1404 rq->doorbell = &qp->db; 1405 } 1406 1407 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1408 { 1409 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1410 } 1411 1412 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1413 struct ib_pd *pd, 1414 struct ib_qp_init_attr *init_attr, 1415 struct ib_udata *udata) 1416 { 1417 struct ib_uobject *uobj = pd->uobject; 1418 struct ib_ucontext *ucontext = uobj->context; 1419 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1420 struct mlx5_ib_create_qp_resp resp = {}; 1421 int inlen; 1422 int err; 1423 u32 *in; 1424 void *tirc; 1425 void *hfso; 1426 u32 selected_fields = 0; 1427 u32 outer_l4; 1428 size_t min_resp_len; 1429 u32 tdn = mucontext->tdn; 1430 struct mlx5_ib_create_qp_rss ucmd = {}; 1431 size_t required_cmd_sz; 1432 1433 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1434 return -EOPNOTSUPP; 1435 1436 if (init_attr->create_flags || init_attr->send_cq) 1437 return -EINVAL; 1438 1439 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1440 if (udata->outlen < min_resp_len) 1441 return -EINVAL; 1442 1443 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1444 if (udata->inlen < required_cmd_sz) { 1445 mlx5_ib_dbg(dev, "invalid inlen\n"); 1446 return -EINVAL; 1447 } 1448 1449 if (udata->inlen > sizeof(ucmd) && 1450 !ib_is_udata_cleared(udata, sizeof(ucmd), 1451 udata->inlen - sizeof(ucmd))) { 1452 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1453 return -EOPNOTSUPP; 1454 } 1455 1456 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1457 mlx5_ib_dbg(dev, "copy failed\n"); 1458 return -EFAULT; 1459 } 1460 1461 if (ucmd.comp_mask) { 1462 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1463 return -EOPNOTSUPP; 1464 } 1465 1466 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1467 mlx5_ib_dbg(dev, "invalid flags\n"); 1468 return -EOPNOTSUPP; 1469 } 1470 1471 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1472 !tunnel_offload_supported(dev->mdev)) { 1473 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1474 return -EOPNOTSUPP; 1475 } 1476 1477 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1478 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1479 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1480 return -EOPNOTSUPP; 1481 } 1482 1483 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1484 if (err) { 1485 mlx5_ib_dbg(dev, "copy failed\n"); 1486 return -EINVAL; 1487 } 1488 1489 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1490 in = kvzalloc(inlen, GFP_KERNEL); 1491 if (!in) 1492 return -ENOMEM; 1493 1494 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1495 MLX5_SET(tirc, tirc, disp_type, 1496 MLX5_TIRC_DISP_TYPE_INDIRECT); 1497 MLX5_SET(tirc, tirc, indirect_table, 1498 init_attr->rwq_ind_tbl->ind_tbl_num); 1499 MLX5_SET(tirc, tirc, transport_domain, tdn); 1500 1501 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1502 1503 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1504 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1505 1506 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1507 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1508 else 1509 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1510 1511 switch (ucmd.rx_hash_function) { 1512 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1513 { 1514 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1515 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1516 1517 if (len != ucmd.rx_key_len) { 1518 err = -EINVAL; 1519 goto err; 1520 } 1521 1522 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1523 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1524 memcpy(rss_key, ucmd.rx_hash_key, len); 1525 break; 1526 } 1527 default: 1528 err = -EOPNOTSUPP; 1529 goto err; 1530 } 1531 1532 if (!ucmd.rx_hash_fields_mask) { 1533 /* special case when this TIR serves as steering entry without hashing */ 1534 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1535 goto create_tir; 1536 err = -EINVAL; 1537 goto err; 1538 } 1539 1540 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1541 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1542 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1544 err = -EINVAL; 1545 goto err; 1546 } 1547 1548 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1549 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1550 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1551 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1552 MLX5_L3_PROT_TYPE_IPV4); 1553 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1554 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1555 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1556 MLX5_L3_PROT_TYPE_IPV6); 1557 1558 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1559 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1560 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1561 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1562 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1563 1564 /* Check that only one l4 protocol is set */ 1565 if (outer_l4 & (outer_l4 - 1)) { 1566 err = -EINVAL; 1567 goto err; 1568 } 1569 1570 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1571 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1572 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1573 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1574 MLX5_L4_PROT_TYPE_TCP); 1575 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1576 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1577 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1578 MLX5_L4_PROT_TYPE_UDP); 1579 1580 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1581 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1582 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1583 1584 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1585 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1586 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1587 1588 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1589 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1590 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1591 1592 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1593 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1594 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1595 1596 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1597 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1598 1599 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1600 1601 create_tir: 1602 if (dev->rep) 1603 MLX5_SET(tirc, tirc, self_lb_block, 1604 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1605 1606 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1607 1608 if (err) 1609 goto err; 1610 1611 kvfree(in); 1612 /* qpn is reserved for that QP */ 1613 qp->trans_qp.base.mqp.qpn = 0; 1614 qp->flags |= MLX5_IB_QP_RSS; 1615 return 0; 1616 1617 err: 1618 kvfree(in); 1619 return err; 1620 } 1621 1622 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1623 struct ib_qp_init_attr *init_attr, 1624 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1625 { 1626 struct mlx5_ib_resources *devr = &dev->devr; 1627 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1628 struct mlx5_core_dev *mdev = dev->mdev; 1629 struct mlx5_ib_create_qp_resp resp; 1630 struct mlx5_ib_cq *send_cq; 1631 struct mlx5_ib_cq *recv_cq; 1632 unsigned long flags; 1633 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1634 struct mlx5_ib_create_qp ucmd; 1635 struct mlx5_ib_qp_base *base; 1636 int mlx5_st; 1637 void *qpc; 1638 u32 *in; 1639 int err; 1640 1641 mutex_init(&qp->mutex); 1642 spin_lock_init(&qp->sq.lock); 1643 spin_lock_init(&qp->rq.lock); 1644 1645 mlx5_st = to_mlx5_st(init_attr->qp_type); 1646 if (mlx5_st < 0) 1647 return -EINVAL; 1648 1649 if (init_attr->rwq_ind_tbl) { 1650 if (!udata) 1651 return -ENOSYS; 1652 1653 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1654 return err; 1655 } 1656 1657 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1658 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1659 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1660 return -EINVAL; 1661 } else { 1662 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1663 } 1664 } 1665 1666 if (init_attr->create_flags & 1667 (IB_QP_CREATE_CROSS_CHANNEL | 1668 IB_QP_CREATE_MANAGED_SEND | 1669 IB_QP_CREATE_MANAGED_RECV)) { 1670 if (!MLX5_CAP_GEN(mdev, cd)) { 1671 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1672 return -EINVAL; 1673 } 1674 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1675 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1676 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1677 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1678 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1679 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1680 } 1681 1682 if (init_attr->qp_type == IB_QPT_UD && 1683 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1684 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1685 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1686 return -EOPNOTSUPP; 1687 } 1688 1689 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1690 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1691 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1692 return -EOPNOTSUPP; 1693 } 1694 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1695 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1696 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1697 return -EOPNOTSUPP; 1698 } 1699 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1700 } 1701 1702 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1703 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1704 1705 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1706 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1707 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1708 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1709 return -EOPNOTSUPP; 1710 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1711 } 1712 1713 if (pd && pd->uobject) { 1714 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1715 mlx5_ib_dbg(dev, "copy failed\n"); 1716 return -EFAULT; 1717 } 1718 1719 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1720 &ucmd, udata->inlen, &uidx); 1721 if (err) 1722 return err; 1723 1724 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1725 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1726 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1727 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1728 !tunnel_offload_supported(mdev)) { 1729 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1730 return -EOPNOTSUPP; 1731 } 1732 qp->tunnel_offload_en = true; 1733 } 1734 1735 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1736 if (init_attr->qp_type != IB_QPT_UD || 1737 (MLX5_CAP_GEN(dev->mdev, port_type) != 1738 MLX5_CAP_PORT_TYPE_IB) || 1739 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1740 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1741 return -EOPNOTSUPP; 1742 } 1743 1744 qp->flags |= MLX5_IB_QP_UNDERLAY; 1745 qp->underlay_qpn = init_attr->source_qpn; 1746 } 1747 } else { 1748 qp->wq_sig = !!wq_signature; 1749 } 1750 1751 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1752 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1753 &qp->raw_packet_qp.rq.base : 1754 &qp->trans_qp.base; 1755 1756 qp->has_rq = qp_has_rq(init_attr); 1757 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1758 qp, (pd && pd->uobject) ? &ucmd : NULL); 1759 if (err) { 1760 mlx5_ib_dbg(dev, "err %d\n", err); 1761 return err; 1762 } 1763 1764 if (pd) { 1765 if (pd->uobject) { 1766 __u32 max_wqes = 1767 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1768 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1769 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1770 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1771 mlx5_ib_dbg(dev, "invalid rq params\n"); 1772 return -EINVAL; 1773 } 1774 if (ucmd.sq_wqe_count > max_wqes) { 1775 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1776 ucmd.sq_wqe_count, max_wqes); 1777 return -EINVAL; 1778 } 1779 if (init_attr->create_flags & 1780 mlx5_ib_create_qp_sqpn_qp1()) { 1781 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1782 return -EINVAL; 1783 } 1784 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1785 &resp, &inlen, base); 1786 if (err) 1787 mlx5_ib_dbg(dev, "err %d\n", err); 1788 } else { 1789 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1790 base); 1791 if (err) 1792 mlx5_ib_dbg(dev, "err %d\n", err); 1793 } 1794 1795 if (err) 1796 return err; 1797 } else { 1798 in = kvzalloc(inlen, GFP_KERNEL); 1799 if (!in) 1800 return -ENOMEM; 1801 1802 qp->create_type = MLX5_QP_EMPTY; 1803 } 1804 1805 if (is_sqp(init_attr->qp_type)) 1806 qp->port = init_attr->port_num; 1807 1808 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1809 1810 MLX5_SET(qpc, qpc, st, mlx5_st); 1811 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1812 1813 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1814 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1815 else 1816 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1817 1818 1819 if (qp->wq_sig) 1820 MLX5_SET(qpc, qpc, wq_signature, 1); 1821 1822 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1823 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1824 1825 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1826 MLX5_SET(qpc, qpc, cd_master, 1); 1827 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1828 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1829 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1830 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1831 1832 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1833 int rcqe_sz; 1834 int scqe_sz; 1835 1836 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1837 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1838 1839 if (rcqe_sz == 128) 1840 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1841 else 1842 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1843 1844 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1845 if (scqe_sz == 128) 1846 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1847 else 1848 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1849 } 1850 } 1851 1852 if (qp->rq.wqe_cnt) { 1853 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1854 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1855 } 1856 1857 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1858 1859 if (qp->sq.wqe_cnt) { 1860 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1861 } else { 1862 MLX5_SET(qpc, qpc, no_sq, 1); 1863 if (init_attr->srq && 1864 init_attr->srq->srq_type == IB_SRQT_TM) 1865 MLX5_SET(qpc, qpc, offload_type, 1866 MLX5_QPC_OFFLOAD_TYPE_RNDV); 1867 } 1868 1869 /* Set default resources */ 1870 switch (init_attr->qp_type) { 1871 case IB_QPT_XRC_TGT: 1872 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1873 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1874 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1875 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1876 break; 1877 case IB_QPT_XRC_INI: 1878 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1879 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1880 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1881 break; 1882 default: 1883 if (init_attr->srq) { 1884 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1885 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1886 } else { 1887 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1888 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1889 } 1890 } 1891 1892 if (init_attr->send_cq) 1893 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1894 1895 if (init_attr->recv_cq) 1896 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1897 1898 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1899 1900 /* 0xffffff means we ask to work with cqe version 0 */ 1901 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1902 MLX5_SET(qpc, qpc, user_index, uidx); 1903 1904 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1905 if (init_attr->qp_type == IB_QPT_UD && 1906 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1907 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1908 qp->flags |= MLX5_IB_QP_LSO; 1909 } 1910 1911 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1912 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 1913 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 1914 err = -EOPNOTSUPP; 1915 goto err; 1916 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1917 MLX5_SET(qpc, qpc, end_padding_mode, 1918 MLX5_WQ_END_PAD_MODE_ALIGN); 1919 } else { 1920 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 1921 } 1922 } 1923 1924 if (inlen < 0) { 1925 err = -EINVAL; 1926 goto err; 1927 } 1928 1929 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1930 qp->flags & MLX5_IB_QP_UNDERLAY) { 1931 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1932 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1933 err = create_raw_packet_qp(dev, qp, in, inlen, pd); 1934 } else { 1935 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1936 } 1937 1938 if (err) { 1939 mlx5_ib_dbg(dev, "create qp failed\n"); 1940 goto err_create; 1941 } 1942 1943 kvfree(in); 1944 1945 base->container_mibqp = qp; 1946 base->mqp.event = mlx5_ib_qp_event; 1947 1948 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1949 &send_cq, &recv_cq); 1950 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1951 mlx5_ib_lock_cqs(send_cq, recv_cq); 1952 /* Maintain device to QPs access, needed for further handling via reset 1953 * flow 1954 */ 1955 list_add_tail(&qp->qps_list, &dev->qp_list); 1956 /* Maintain CQ to QPs access, needed for further handling via reset flow 1957 */ 1958 if (send_cq) 1959 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1960 if (recv_cq) 1961 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1962 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1963 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1964 1965 return 0; 1966 1967 err_create: 1968 if (qp->create_type == MLX5_QP_USER) 1969 destroy_qp_user(dev, pd, qp, base); 1970 else if (qp->create_type == MLX5_QP_KERNEL) 1971 destroy_qp_kernel(dev, qp); 1972 1973 err: 1974 kvfree(in); 1975 return err; 1976 } 1977 1978 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1979 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1980 { 1981 if (send_cq) { 1982 if (recv_cq) { 1983 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1984 spin_lock(&send_cq->lock); 1985 spin_lock_nested(&recv_cq->lock, 1986 SINGLE_DEPTH_NESTING); 1987 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1988 spin_lock(&send_cq->lock); 1989 __acquire(&recv_cq->lock); 1990 } else { 1991 spin_lock(&recv_cq->lock); 1992 spin_lock_nested(&send_cq->lock, 1993 SINGLE_DEPTH_NESTING); 1994 } 1995 } else { 1996 spin_lock(&send_cq->lock); 1997 __acquire(&recv_cq->lock); 1998 } 1999 } else if (recv_cq) { 2000 spin_lock(&recv_cq->lock); 2001 __acquire(&send_cq->lock); 2002 } else { 2003 __acquire(&send_cq->lock); 2004 __acquire(&recv_cq->lock); 2005 } 2006 } 2007 2008 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2009 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2010 { 2011 if (send_cq) { 2012 if (recv_cq) { 2013 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2014 spin_unlock(&recv_cq->lock); 2015 spin_unlock(&send_cq->lock); 2016 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2017 __release(&recv_cq->lock); 2018 spin_unlock(&send_cq->lock); 2019 } else { 2020 spin_unlock(&send_cq->lock); 2021 spin_unlock(&recv_cq->lock); 2022 } 2023 } else { 2024 __release(&recv_cq->lock); 2025 spin_unlock(&send_cq->lock); 2026 } 2027 } else if (recv_cq) { 2028 __release(&send_cq->lock); 2029 spin_unlock(&recv_cq->lock); 2030 } else { 2031 __release(&recv_cq->lock); 2032 __release(&send_cq->lock); 2033 } 2034 } 2035 2036 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2037 { 2038 return to_mpd(qp->ibqp.pd); 2039 } 2040 2041 static void get_cqs(enum ib_qp_type qp_type, 2042 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2043 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2044 { 2045 switch (qp_type) { 2046 case IB_QPT_XRC_TGT: 2047 *send_cq = NULL; 2048 *recv_cq = NULL; 2049 break; 2050 case MLX5_IB_QPT_REG_UMR: 2051 case IB_QPT_XRC_INI: 2052 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2053 *recv_cq = NULL; 2054 break; 2055 2056 case IB_QPT_SMI: 2057 case MLX5_IB_QPT_HW_GSI: 2058 case IB_QPT_RC: 2059 case IB_QPT_UC: 2060 case IB_QPT_UD: 2061 case IB_QPT_RAW_IPV6: 2062 case IB_QPT_RAW_ETHERTYPE: 2063 case IB_QPT_RAW_PACKET: 2064 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2065 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2066 break; 2067 2068 case IB_QPT_MAX: 2069 default: 2070 *send_cq = NULL; 2071 *recv_cq = NULL; 2072 break; 2073 } 2074 } 2075 2076 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2077 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2078 u8 lag_tx_affinity); 2079 2080 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2081 { 2082 struct mlx5_ib_cq *send_cq, *recv_cq; 2083 struct mlx5_ib_qp_base *base; 2084 unsigned long flags; 2085 int err; 2086 2087 if (qp->ibqp.rwq_ind_tbl) { 2088 destroy_rss_raw_qp_tir(dev, qp); 2089 return; 2090 } 2091 2092 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2093 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2094 &qp->raw_packet_qp.rq.base : 2095 &qp->trans_qp.base; 2096 2097 if (qp->state != IB_QPS_RESET) { 2098 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2099 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2100 err = mlx5_core_qp_modify(dev->mdev, 2101 MLX5_CMD_OP_2RST_QP, 0, 2102 NULL, &base->mqp); 2103 } else { 2104 struct mlx5_modify_raw_qp_param raw_qp_param = { 2105 .operation = MLX5_CMD_OP_2RST_QP 2106 }; 2107 2108 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2109 } 2110 if (err) 2111 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2112 base->mqp.qpn); 2113 } 2114 2115 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2116 &send_cq, &recv_cq); 2117 2118 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2119 mlx5_ib_lock_cqs(send_cq, recv_cq); 2120 /* del from lists under both locks above to protect reset flow paths */ 2121 list_del(&qp->qps_list); 2122 if (send_cq) 2123 list_del(&qp->cq_send_list); 2124 2125 if (recv_cq) 2126 list_del(&qp->cq_recv_list); 2127 2128 if (qp->create_type == MLX5_QP_KERNEL) { 2129 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2130 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2131 if (send_cq != recv_cq) 2132 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2133 NULL); 2134 } 2135 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2136 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2137 2138 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2139 qp->flags & MLX5_IB_QP_UNDERLAY) { 2140 destroy_raw_packet_qp(dev, qp); 2141 } else { 2142 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2143 if (err) 2144 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2145 base->mqp.qpn); 2146 } 2147 2148 if (qp->create_type == MLX5_QP_KERNEL) 2149 destroy_qp_kernel(dev, qp); 2150 else if (qp->create_type == MLX5_QP_USER) 2151 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2152 } 2153 2154 static const char *ib_qp_type_str(enum ib_qp_type type) 2155 { 2156 switch (type) { 2157 case IB_QPT_SMI: 2158 return "IB_QPT_SMI"; 2159 case IB_QPT_GSI: 2160 return "IB_QPT_GSI"; 2161 case IB_QPT_RC: 2162 return "IB_QPT_RC"; 2163 case IB_QPT_UC: 2164 return "IB_QPT_UC"; 2165 case IB_QPT_UD: 2166 return "IB_QPT_UD"; 2167 case IB_QPT_RAW_IPV6: 2168 return "IB_QPT_RAW_IPV6"; 2169 case IB_QPT_RAW_ETHERTYPE: 2170 return "IB_QPT_RAW_ETHERTYPE"; 2171 case IB_QPT_XRC_INI: 2172 return "IB_QPT_XRC_INI"; 2173 case IB_QPT_XRC_TGT: 2174 return "IB_QPT_XRC_TGT"; 2175 case IB_QPT_RAW_PACKET: 2176 return "IB_QPT_RAW_PACKET"; 2177 case MLX5_IB_QPT_REG_UMR: 2178 return "MLX5_IB_QPT_REG_UMR"; 2179 case IB_QPT_DRIVER: 2180 return "IB_QPT_DRIVER"; 2181 case IB_QPT_MAX: 2182 default: 2183 return "Invalid QP type"; 2184 } 2185 } 2186 2187 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2188 struct ib_qp_init_attr *attr, 2189 struct mlx5_ib_create_qp *ucmd) 2190 { 2191 struct mlx5_ib_qp *qp; 2192 int err = 0; 2193 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2194 void *dctc; 2195 2196 if (!attr->srq || !attr->recv_cq) 2197 return ERR_PTR(-EINVAL); 2198 2199 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2200 ucmd, sizeof(*ucmd), &uidx); 2201 if (err) 2202 return ERR_PTR(err); 2203 2204 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2205 if (!qp) 2206 return ERR_PTR(-ENOMEM); 2207 2208 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2209 if (!qp->dct.in) { 2210 err = -ENOMEM; 2211 goto err_free; 2212 } 2213 2214 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2215 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2216 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2217 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2218 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2219 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2220 MLX5_SET(dctc, dctc, user_index, uidx); 2221 2222 qp->state = IB_QPS_RESET; 2223 2224 return &qp->ibqp; 2225 err_free: 2226 kfree(qp); 2227 return ERR_PTR(err); 2228 } 2229 2230 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2231 struct ib_qp_init_attr *init_attr, 2232 struct mlx5_ib_create_qp *ucmd, 2233 struct ib_udata *udata) 2234 { 2235 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2236 int err; 2237 2238 if (!udata) 2239 return -EINVAL; 2240 2241 if (udata->inlen < sizeof(*ucmd)) { 2242 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2243 return -EINVAL; 2244 } 2245 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2246 if (err) 2247 return err; 2248 2249 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2250 init_attr->qp_type = MLX5_IB_QPT_DCI; 2251 } else { 2252 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2253 init_attr->qp_type = MLX5_IB_QPT_DCT; 2254 } else { 2255 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2256 return -EINVAL; 2257 } 2258 } 2259 2260 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2261 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2262 return -EOPNOTSUPP; 2263 } 2264 2265 return 0; 2266 } 2267 2268 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2269 struct ib_qp_init_attr *verbs_init_attr, 2270 struct ib_udata *udata) 2271 { 2272 struct mlx5_ib_dev *dev; 2273 struct mlx5_ib_qp *qp; 2274 u16 xrcdn = 0; 2275 int err; 2276 struct ib_qp_init_attr mlx_init_attr; 2277 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2278 2279 if (pd) { 2280 dev = to_mdev(pd->device); 2281 2282 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2283 if (!pd->uobject) { 2284 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2285 return ERR_PTR(-EINVAL); 2286 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2287 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2288 return ERR_PTR(-EINVAL); 2289 } 2290 } 2291 } else { 2292 /* being cautious here */ 2293 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2294 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2295 pr_warn("%s: no PD for transport %s\n", __func__, 2296 ib_qp_type_str(init_attr->qp_type)); 2297 return ERR_PTR(-EINVAL); 2298 } 2299 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2300 } 2301 2302 if (init_attr->qp_type == IB_QPT_DRIVER) { 2303 struct mlx5_ib_create_qp ucmd; 2304 2305 init_attr = &mlx_init_attr; 2306 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2307 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2308 if (err) 2309 return ERR_PTR(err); 2310 2311 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2312 if (init_attr->cap.max_recv_wr || 2313 init_attr->cap.max_recv_sge) { 2314 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2315 return ERR_PTR(-EINVAL); 2316 } 2317 } else { 2318 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2319 } 2320 } 2321 2322 switch (init_attr->qp_type) { 2323 case IB_QPT_XRC_TGT: 2324 case IB_QPT_XRC_INI: 2325 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2326 mlx5_ib_dbg(dev, "XRC not supported\n"); 2327 return ERR_PTR(-ENOSYS); 2328 } 2329 init_attr->recv_cq = NULL; 2330 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2331 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2332 init_attr->send_cq = NULL; 2333 } 2334 2335 /* fall through */ 2336 case IB_QPT_RAW_PACKET: 2337 case IB_QPT_RC: 2338 case IB_QPT_UC: 2339 case IB_QPT_UD: 2340 case IB_QPT_SMI: 2341 case MLX5_IB_QPT_HW_GSI: 2342 case MLX5_IB_QPT_REG_UMR: 2343 case MLX5_IB_QPT_DCI: 2344 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2345 if (!qp) 2346 return ERR_PTR(-ENOMEM); 2347 2348 err = create_qp_common(dev, pd, init_attr, udata, qp); 2349 if (err) { 2350 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2351 kfree(qp); 2352 return ERR_PTR(err); 2353 } 2354 2355 if (is_qp0(init_attr->qp_type)) 2356 qp->ibqp.qp_num = 0; 2357 else if (is_qp1(init_attr->qp_type)) 2358 qp->ibqp.qp_num = 1; 2359 else 2360 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2361 2362 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2363 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2364 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2365 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2366 2367 qp->trans_qp.xrcdn = xrcdn; 2368 2369 break; 2370 2371 case IB_QPT_GSI: 2372 return mlx5_ib_gsi_create_qp(pd, init_attr); 2373 2374 case IB_QPT_RAW_IPV6: 2375 case IB_QPT_RAW_ETHERTYPE: 2376 case IB_QPT_MAX: 2377 default: 2378 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2379 init_attr->qp_type); 2380 /* Don't support raw QPs */ 2381 return ERR_PTR(-EINVAL); 2382 } 2383 2384 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2385 qp->qp_sub_type = init_attr->qp_type; 2386 2387 return &qp->ibqp; 2388 } 2389 2390 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2391 { 2392 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2393 2394 if (mqp->state == IB_QPS_RTR) { 2395 int err; 2396 2397 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2398 if (err) { 2399 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2400 return err; 2401 } 2402 } 2403 2404 kfree(mqp->dct.in); 2405 kfree(mqp); 2406 return 0; 2407 } 2408 2409 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2410 { 2411 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2412 struct mlx5_ib_qp *mqp = to_mqp(qp); 2413 2414 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2415 return mlx5_ib_gsi_destroy_qp(qp); 2416 2417 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2418 return mlx5_ib_destroy_dct(mqp); 2419 2420 destroy_qp_common(dev, mqp); 2421 2422 kfree(mqp); 2423 2424 return 0; 2425 } 2426 2427 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2428 int attr_mask) 2429 { 2430 u32 hw_access_flags = 0; 2431 u8 dest_rd_atomic; 2432 u32 access_flags; 2433 2434 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2435 dest_rd_atomic = attr->max_dest_rd_atomic; 2436 else 2437 dest_rd_atomic = qp->trans_qp.resp_depth; 2438 2439 if (attr_mask & IB_QP_ACCESS_FLAGS) 2440 access_flags = attr->qp_access_flags; 2441 else 2442 access_flags = qp->trans_qp.atomic_rd_en; 2443 2444 if (!dest_rd_atomic) 2445 access_flags &= IB_ACCESS_REMOTE_WRITE; 2446 2447 if (access_flags & IB_ACCESS_REMOTE_READ) 2448 hw_access_flags |= MLX5_QP_BIT_RRE; 2449 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2450 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2451 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2452 hw_access_flags |= MLX5_QP_BIT_RWE; 2453 2454 return cpu_to_be32(hw_access_flags); 2455 } 2456 2457 enum { 2458 MLX5_PATH_FLAG_FL = 1 << 0, 2459 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2460 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2461 }; 2462 2463 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2464 { 2465 if (rate == IB_RATE_PORT_CURRENT) 2466 return 0; 2467 2468 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) 2469 return -EINVAL; 2470 2471 while (rate != IB_RATE_PORT_CURRENT && 2472 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2473 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2474 --rate; 2475 2476 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2477 } 2478 2479 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2480 struct mlx5_ib_sq *sq, u8 sl) 2481 { 2482 void *in; 2483 void *tisc; 2484 int inlen; 2485 int err; 2486 2487 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2488 in = kvzalloc(inlen, GFP_KERNEL); 2489 if (!in) 2490 return -ENOMEM; 2491 2492 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2493 2494 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2495 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2496 2497 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2498 2499 kvfree(in); 2500 2501 return err; 2502 } 2503 2504 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2505 struct mlx5_ib_sq *sq, u8 tx_affinity) 2506 { 2507 void *in; 2508 void *tisc; 2509 int inlen; 2510 int err; 2511 2512 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2513 in = kvzalloc(inlen, GFP_KERNEL); 2514 if (!in) 2515 return -ENOMEM; 2516 2517 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2518 2519 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2520 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2521 2522 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2523 2524 kvfree(in); 2525 2526 return err; 2527 } 2528 2529 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2530 const struct rdma_ah_attr *ah, 2531 struct mlx5_qp_path *path, u8 port, int attr_mask, 2532 u32 path_flags, const struct ib_qp_attr *attr, 2533 bool alt) 2534 { 2535 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2536 int err; 2537 enum ib_gid_type gid_type; 2538 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2539 u8 sl = rdma_ah_get_sl(ah); 2540 2541 if (attr_mask & IB_QP_PKEY_INDEX) 2542 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2543 attr->pkey_index); 2544 2545 if (ah_flags & IB_AH_GRH) { 2546 if (grh->sgid_index >= 2547 dev->mdev->port_caps[port - 1].gid_table_len) { 2548 pr_err("sgid_index (%u) too large. max is %d\n", 2549 grh->sgid_index, 2550 dev->mdev->port_caps[port - 1].gid_table_len); 2551 return -EINVAL; 2552 } 2553 } 2554 2555 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2556 if (!(ah_flags & IB_AH_GRH)) 2557 return -EINVAL; 2558 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2559 &gid_type); 2560 if (err) 2561 return err; 2562 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2563 if (qp->ibqp.qp_type == IB_QPT_RC || 2564 qp->ibqp.qp_type == IB_QPT_UC || 2565 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2566 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2567 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2568 grh->sgid_index); 2569 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2570 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2571 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2572 } else { 2573 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2574 path->fl_free_ar |= 2575 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2576 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2577 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2578 if (ah_flags & IB_AH_GRH) 2579 path->grh_mlid |= 1 << 7; 2580 path->dci_cfi_prio_sl = sl & 0xf; 2581 } 2582 2583 if (ah_flags & IB_AH_GRH) { 2584 path->mgid_index = grh->sgid_index; 2585 path->hop_limit = grh->hop_limit; 2586 path->tclass_flowlabel = 2587 cpu_to_be32((grh->traffic_class << 20) | 2588 (grh->flow_label)); 2589 memcpy(path->rgid, grh->dgid.raw, 16); 2590 } 2591 2592 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2593 if (err < 0) 2594 return err; 2595 path->static_rate = err; 2596 path->port = port; 2597 2598 if (attr_mask & IB_QP_TIMEOUT) 2599 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2600 2601 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2602 return modify_raw_packet_eth_prio(dev->mdev, 2603 &qp->raw_packet_qp.sq, 2604 sl & 0xf); 2605 2606 return 0; 2607 } 2608 2609 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2610 [MLX5_QP_STATE_INIT] = { 2611 [MLX5_QP_STATE_INIT] = { 2612 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2613 MLX5_QP_OPTPAR_RAE | 2614 MLX5_QP_OPTPAR_RWE | 2615 MLX5_QP_OPTPAR_PKEY_INDEX | 2616 MLX5_QP_OPTPAR_PRI_PORT, 2617 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2618 MLX5_QP_OPTPAR_PKEY_INDEX | 2619 MLX5_QP_OPTPAR_PRI_PORT, 2620 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2621 MLX5_QP_OPTPAR_Q_KEY | 2622 MLX5_QP_OPTPAR_PRI_PORT, 2623 }, 2624 [MLX5_QP_STATE_RTR] = { 2625 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2626 MLX5_QP_OPTPAR_RRE | 2627 MLX5_QP_OPTPAR_RAE | 2628 MLX5_QP_OPTPAR_RWE | 2629 MLX5_QP_OPTPAR_PKEY_INDEX, 2630 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2631 MLX5_QP_OPTPAR_RWE | 2632 MLX5_QP_OPTPAR_PKEY_INDEX, 2633 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2634 MLX5_QP_OPTPAR_Q_KEY, 2635 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2636 MLX5_QP_OPTPAR_Q_KEY, 2637 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2638 MLX5_QP_OPTPAR_RRE | 2639 MLX5_QP_OPTPAR_RAE | 2640 MLX5_QP_OPTPAR_RWE | 2641 MLX5_QP_OPTPAR_PKEY_INDEX, 2642 }, 2643 }, 2644 [MLX5_QP_STATE_RTR] = { 2645 [MLX5_QP_STATE_RTS] = { 2646 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2647 MLX5_QP_OPTPAR_RRE | 2648 MLX5_QP_OPTPAR_RAE | 2649 MLX5_QP_OPTPAR_RWE | 2650 MLX5_QP_OPTPAR_PM_STATE | 2651 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2652 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2653 MLX5_QP_OPTPAR_RWE | 2654 MLX5_QP_OPTPAR_PM_STATE, 2655 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2656 }, 2657 }, 2658 [MLX5_QP_STATE_RTS] = { 2659 [MLX5_QP_STATE_RTS] = { 2660 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2661 MLX5_QP_OPTPAR_RAE | 2662 MLX5_QP_OPTPAR_RWE | 2663 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2664 MLX5_QP_OPTPAR_PM_STATE | 2665 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2666 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2667 MLX5_QP_OPTPAR_PM_STATE | 2668 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2669 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2670 MLX5_QP_OPTPAR_SRQN | 2671 MLX5_QP_OPTPAR_CQN_RCV, 2672 }, 2673 }, 2674 [MLX5_QP_STATE_SQER] = { 2675 [MLX5_QP_STATE_RTS] = { 2676 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2677 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2678 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2679 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2680 MLX5_QP_OPTPAR_RWE | 2681 MLX5_QP_OPTPAR_RAE | 2682 MLX5_QP_OPTPAR_RRE, 2683 }, 2684 }, 2685 }; 2686 2687 static int ib_nr_to_mlx5_nr(int ib_mask) 2688 { 2689 switch (ib_mask) { 2690 case IB_QP_STATE: 2691 return 0; 2692 case IB_QP_CUR_STATE: 2693 return 0; 2694 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2695 return 0; 2696 case IB_QP_ACCESS_FLAGS: 2697 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2698 MLX5_QP_OPTPAR_RAE; 2699 case IB_QP_PKEY_INDEX: 2700 return MLX5_QP_OPTPAR_PKEY_INDEX; 2701 case IB_QP_PORT: 2702 return MLX5_QP_OPTPAR_PRI_PORT; 2703 case IB_QP_QKEY: 2704 return MLX5_QP_OPTPAR_Q_KEY; 2705 case IB_QP_AV: 2706 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2707 MLX5_QP_OPTPAR_PRI_PORT; 2708 case IB_QP_PATH_MTU: 2709 return 0; 2710 case IB_QP_TIMEOUT: 2711 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2712 case IB_QP_RETRY_CNT: 2713 return MLX5_QP_OPTPAR_RETRY_COUNT; 2714 case IB_QP_RNR_RETRY: 2715 return MLX5_QP_OPTPAR_RNR_RETRY; 2716 case IB_QP_RQ_PSN: 2717 return 0; 2718 case IB_QP_MAX_QP_RD_ATOMIC: 2719 return MLX5_QP_OPTPAR_SRA_MAX; 2720 case IB_QP_ALT_PATH: 2721 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2722 case IB_QP_MIN_RNR_TIMER: 2723 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2724 case IB_QP_SQ_PSN: 2725 return 0; 2726 case IB_QP_MAX_DEST_RD_ATOMIC: 2727 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2728 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2729 case IB_QP_PATH_MIG_STATE: 2730 return MLX5_QP_OPTPAR_PM_STATE; 2731 case IB_QP_CAP: 2732 return 0; 2733 case IB_QP_DEST_QPN: 2734 return 0; 2735 } 2736 return 0; 2737 } 2738 2739 static int ib_mask_to_mlx5_opt(int ib_mask) 2740 { 2741 int result = 0; 2742 int i; 2743 2744 for (i = 0; i < 8 * sizeof(int); i++) { 2745 if ((1 << i) & ib_mask) 2746 result |= ib_nr_to_mlx5_nr(1 << i); 2747 } 2748 2749 return result; 2750 } 2751 2752 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2753 struct mlx5_ib_rq *rq, int new_state, 2754 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2755 { 2756 void *in; 2757 void *rqc; 2758 int inlen; 2759 int err; 2760 2761 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2762 in = kvzalloc(inlen, GFP_KERNEL); 2763 if (!in) 2764 return -ENOMEM; 2765 2766 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2767 2768 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2769 MLX5_SET(rqc, rqc, state, new_state); 2770 2771 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2772 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2773 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2774 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2775 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2776 } else 2777 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2778 dev->ib_dev.name); 2779 } 2780 2781 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2782 if (err) 2783 goto out; 2784 2785 rq->state = new_state; 2786 2787 out: 2788 kvfree(in); 2789 return err; 2790 } 2791 2792 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2793 struct mlx5_ib_sq *sq, 2794 int new_state, 2795 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2796 { 2797 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2798 struct mlx5_rate_limit old_rl = ibqp->rl; 2799 struct mlx5_rate_limit new_rl = old_rl; 2800 bool new_rate_added = false; 2801 u16 rl_index = 0; 2802 void *in; 2803 void *sqc; 2804 int inlen; 2805 int err; 2806 2807 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2808 in = kvzalloc(inlen, GFP_KERNEL); 2809 if (!in) 2810 return -ENOMEM; 2811 2812 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2813 2814 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2815 MLX5_SET(sqc, sqc, state, new_state); 2816 2817 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2818 if (new_state != MLX5_SQC_STATE_RDY) 2819 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2820 __func__); 2821 else 2822 new_rl = raw_qp_param->rl; 2823 } 2824 2825 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 2826 if (new_rl.rate) { 2827 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 2828 if (err) { 2829 pr_err("Failed configuring rate limit(err %d): \ 2830 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 2831 err, new_rl.rate, new_rl.max_burst_sz, 2832 new_rl.typical_pkt_sz); 2833 2834 goto out; 2835 } 2836 new_rate_added = true; 2837 } 2838 2839 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2840 /* index 0 means no limit */ 2841 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2842 } 2843 2844 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2845 if (err) { 2846 /* Remove new rate from table if failed */ 2847 if (new_rate_added) 2848 mlx5_rl_remove_rate(dev, &new_rl); 2849 goto out; 2850 } 2851 2852 /* Only remove the old rate after new rate was set */ 2853 if ((old_rl.rate && 2854 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 2855 (new_state != MLX5_SQC_STATE_RDY)) 2856 mlx5_rl_remove_rate(dev, &old_rl); 2857 2858 ibqp->rl = new_rl; 2859 sq->state = new_state; 2860 2861 out: 2862 kvfree(in); 2863 return err; 2864 } 2865 2866 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2867 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2868 u8 tx_affinity) 2869 { 2870 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2871 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2872 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2873 int modify_rq = !!qp->rq.wqe_cnt; 2874 int modify_sq = !!qp->sq.wqe_cnt; 2875 int rq_state; 2876 int sq_state; 2877 int err; 2878 2879 switch (raw_qp_param->operation) { 2880 case MLX5_CMD_OP_RST2INIT_QP: 2881 rq_state = MLX5_RQC_STATE_RDY; 2882 sq_state = MLX5_SQC_STATE_RDY; 2883 break; 2884 case MLX5_CMD_OP_2ERR_QP: 2885 rq_state = MLX5_RQC_STATE_ERR; 2886 sq_state = MLX5_SQC_STATE_ERR; 2887 break; 2888 case MLX5_CMD_OP_2RST_QP: 2889 rq_state = MLX5_RQC_STATE_RST; 2890 sq_state = MLX5_SQC_STATE_RST; 2891 break; 2892 case MLX5_CMD_OP_RTR2RTS_QP: 2893 case MLX5_CMD_OP_RTS2RTS_QP: 2894 if (raw_qp_param->set_mask == 2895 MLX5_RAW_QP_RATE_LIMIT) { 2896 modify_rq = 0; 2897 sq_state = sq->state; 2898 } else { 2899 return raw_qp_param->set_mask ? -EINVAL : 0; 2900 } 2901 break; 2902 case MLX5_CMD_OP_INIT2INIT_QP: 2903 case MLX5_CMD_OP_INIT2RTR_QP: 2904 if (raw_qp_param->set_mask) 2905 return -EINVAL; 2906 else 2907 return 0; 2908 default: 2909 WARN_ON(1); 2910 return -EINVAL; 2911 } 2912 2913 if (modify_rq) { 2914 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2915 if (err) 2916 return err; 2917 } 2918 2919 if (modify_sq) { 2920 if (tx_affinity) { 2921 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2922 tx_affinity); 2923 if (err) 2924 return err; 2925 } 2926 2927 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2928 } 2929 2930 return 0; 2931 } 2932 2933 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2934 const struct ib_qp_attr *attr, int attr_mask, 2935 enum ib_qp_state cur_state, enum ib_qp_state new_state, 2936 const struct mlx5_ib_modify_qp *ucmd) 2937 { 2938 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2939 [MLX5_QP_STATE_RST] = { 2940 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2941 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2942 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2943 }, 2944 [MLX5_QP_STATE_INIT] = { 2945 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2946 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2947 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2948 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2949 }, 2950 [MLX5_QP_STATE_RTR] = { 2951 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2952 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2953 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2954 }, 2955 [MLX5_QP_STATE_RTS] = { 2956 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2957 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2958 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2959 }, 2960 [MLX5_QP_STATE_SQD] = { 2961 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2962 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2963 }, 2964 [MLX5_QP_STATE_SQER] = { 2965 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2966 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2967 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2968 }, 2969 [MLX5_QP_STATE_ERR] = { 2970 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2971 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2972 } 2973 }; 2974 2975 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2976 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2977 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2978 struct mlx5_ib_cq *send_cq, *recv_cq; 2979 struct mlx5_qp_context *context; 2980 struct mlx5_ib_pd *pd; 2981 struct mlx5_ib_port *mibport = NULL; 2982 enum mlx5_qp_state mlx5_cur, mlx5_new; 2983 enum mlx5_qp_optpar optpar; 2984 int mlx5_st; 2985 int err; 2986 u16 op; 2987 u8 tx_affinity = 0; 2988 2989 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 2990 qp->qp_sub_type : ibqp->qp_type); 2991 if (mlx5_st < 0) 2992 return -EINVAL; 2993 2994 context = kzalloc(sizeof(*context), GFP_KERNEL); 2995 if (!context) 2996 return -ENOMEM; 2997 2998 context->flags = cpu_to_be32(mlx5_st << 16); 2999 3000 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3001 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3002 } else { 3003 switch (attr->path_mig_state) { 3004 case IB_MIG_MIGRATED: 3005 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3006 break; 3007 case IB_MIG_REARM: 3008 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3009 break; 3010 case IB_MIG_ARMED: 3011 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3012 break; 3013 } 3014 } 3015 3016 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3017 if ((ibqp->qp_type == IB_QPT_RC) || 3018 (ibqp->qp_type == IB_QPT_UD && 3019 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3020 (ibqp->qp_type == IB_QPT_UC) || 3021 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3022 (ibqp->qp_type == IB_QPT_XRC_INI) || 3023 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3024 if (mlx5_lag_is_active(dev->mdev)) { 3025 u8 p = mlx5_core_native_port_num(dev->mdev); 3026 tx_affinity = (unsigned int)atomic_add_return(1, 3027 &dev->roce[p].next_port) % 3028 MLX5_MAX_PORTS + 1; 3029 context->flags |= cpu_to_be32(tx_affinity << 24); 3030 } 3031 } 3032 } 3033 3034 if (is_sqp(ibqp->qp_type)) { 3035 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3036 } else if ((ibqp->qp_type == IB_QPT_UD && 3037 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3038 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3039 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3040 } else if (attr_mask & IB_QP_PATH_MTU) { 3041 if (attr->path_mtu < IB_MTU_256 || 3042 attr->path_mtu > IB_MTU_4096) { 3043 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3044 err = -EINVAL; 3045 goto out; 3046 } 3047 context->mtu_msgmax = (attr->path_mtu << 5) | 3048 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3049 } 3050 3051 if (attr_mask & IB_QP_DEST_QPN) 3052 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3053 3054 if (attr_mask & IB_QP_PKEY_INDEX) 3055 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3056 3057 /* todo implement counter_index functionality */ 3058 3059 if (is_sqp(ibqp->qp_type)) 3060 context->pri_path.port = qp->port; 3061 3062 if (attr_mask & IB_QP_PORT) 3063 context->pri_path.port = attr->port_num; 3064 3065 if (attr_mask & IB_QP_AV) { 3066 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3067 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3068 attr_mask, 0, attr, false); 3069 if (err) 3070 goto out; 3071 } 3072 3073 if (attr_mask & IB_QP_TIMEOUT) 3074 context->pri_path.ackto_lt |= attr->timeout << 3; 3075 3076 if (attr_mask & IB_QP_ALT_PATH) { 3077 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3078 &context->alt_path, 3079 attr->alt_port_num, 3080 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3081 0, attr, true); 3082 if (err) 3083 goto out; 3084 } 3085 3086 pd = get_pd(qp); 3087 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3088 &send_cq, &recv_cq); 3089 3090 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3091 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3092 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3093 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3094 3095 if (attr_mask & IB_QP_RNR_RETRY) 3096 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3097 3098 if (attr_mask & IB_QP_RETRY_CNT) 3099 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3100 3101 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3102 if (attr->max_rd_atomic) 3103 context->params1 |= 3104 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3105 } 3106 3107 if (attr_mask & IB_QP_SQ_PSN) 3108 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3109 3110 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3111 if (attr->max_dest_rd_atomic) 3112 context->params2 |= 3113 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3114 } 3115 3116 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3117 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 3118 3119 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3120 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3121 3122 if (attr_mask & IB_QP_RQ_PSN) 3123 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3124 3125 if (attr_mask & IB_QP_QKEY) 3126 context->qkey = cpu_to_be32(attr->qkey); 3127 3128 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3129 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3130 3131 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3132 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3133 qp->port) - 1; 3134 3135 /* Underlay port should be used - index 0 function per port */ 3136 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3137 port_num = 0; 3138 3139 mibport = &dev->port[port_num]; 3140 context->qp_counter_set_usr_page |= 3141 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3142 } 3143 3144 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3145 context->sq_crq_size |= cpu_to_be16(1 << 4); 3146 3147 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3148 context->deth_sqpn = cpu_to_be32(1); 3149 3150 mlx5_cur = to_mlx5_state(cur_state); 3151 mlx5_new = to_mlx5_state(new_state); 3152 3153 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3154 !optab[mlx5_cur][mlx5_new]) { 3155 err = -EINVAL; 3156 goto out; 3157 } 3158 3159 op = optab[mlx5_cur][mlx5_new]; 3160 optpar = ib_mask_to_mlx5_opt(attr_mask); 3161 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3162 3163 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3164 qp->flags & MLX5_IB_QP_UNDERLAY) { 3165 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3166 3167 raw_qp_param.operation = op; 3168 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3169 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3170 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3171 } 3172 3173 if (attr_mask & IB_QP_RATE_LIMIT) { 3174 raw_qp_param.rl.rate = attr->rate_limit; 3175 3176 if (ucmd->burst_info.max_burst_sz) { 3177 if (attr->rate_limit && 3178 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3179 raw_qp_param.rl.max_burst_sz = 3180 ucmd->burst_info.max_burst_sz; 3181 } else { 3182 err = -EINVAL; 3183 goto out; 3184 } 3185 } 3186 3187 if (ucmd->burst_info.typical_pkt_sz) { 3188 if (attr->rate_limit && 3189 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3190 raw_qp_param.rl.typical_pkt_sz = 3191 ucmd->burst_info.typical_pkt_sz; 3192 } else { 3193 err = -EINVAL; 3194 goto out; 3195 } 3196 } 3197 3198 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3199 } 3200 3201 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3202 } else { 3203 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3204 &base->mqp); 3205 } 3206 3207 if (err) 3208 goto out; 3209 3210 qp->state = new_state; 3211 3212 if (attr_mask & IB_QP_ACCESS_FLAGS) 3213 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3214 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3215 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3216 if (attr_mask & IB_QP_PORT) 3217 qp->port = attr->port_num; 3218 if (attr_mask & IB_QP_ALT_PATH) 3219 qp->trans_qp.alt_port = attr->alt_port_num; 3220 3221 /* 3222 * If we moved a kernel QP to RESET, clean up all old CQ 3223 * entries and reinitialize the QP. 3224 */ 3225 if (new_state == IB_QPS_RESET && 3226 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3227 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3228 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3229 if (send_cq != recv_cq) 3230 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3231 3232 qp->rq.head = 0; 3233 qp->rq.tail = 0; 3234 qp->sq.head = 0; 3235 qp->sq.tail = 0; 3236 qp->sq.cur_post = 0; 3237 qp->sq.last_poll = 0; 3238 qp->db.db[MLX5_RCV_DBR] = 0; 3239 qp->db.db[MLX5_SND_DBR] = 0; 3240 } 3241 3242 out: 3243 kfree(context); 3244 return err; 3245 } 3246 3247 static inline bool is_valid_mask(int mask, int req, int opt) 3248 { 3249 if ((mask & req) != req) 3250 return false; 3251 3252 if (mask & ~(req | opt)) 3253 return false; 3254 3255 return true; 3256 } 3257 3258 /* check valid transition for driver QP types 3259 * for now the only QP type that this function supports is DCI 3260 */ 3261 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3262 enum ib_qp_attr_mask attr_mask) 3263 { 3264 int req = IB_QP_STATE; 3265 int opt = 0; 3266 3267 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3268 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3269 return is_valid_mask(attr_mask, req, opt); 3270 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3271 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3272 return is_valid_mask(attr_mask, req, opt); 3273 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3274 req |= IB_QP_PATH_MTU; 3275 opt = IB_QP_PKEY_INDEX; 3276 return is_valid_mask(attr_mask, req, opt); 3277 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3278 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3279 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3280 opt = IB_QP_MIN_RNR_TIMER; 3281 return is_valid_mask(attr_mask, req, opt); 3282 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3283 opt = IB_QP_MIN_RNR_TIMER; 3284 return is_valid_mask(attr_mask, req, opt); 3285 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3286 return is_valid_mask(attr_mask, req, opt); 3287 } 3288 return false; 3289 } 3290 3291 /* mlx5_ib_modify_dct: modify a DCT QP 3292 * valid transitions are: 3293 * RESET to INIT: must set access_flags, pkey_index and port 3294 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3295 * mtu, gid_index and hop_limit 3296 * Other transitions and attributes are illegal 3297 */ 3298 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3299 int attr_mask, struct ib_udata *udata) 3300 { 3301 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3302 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3303 enum ib_qp_state cur_state, new_state; 3304 int err = 0; 3305 int required = IB_QP_STATE; 3306 void *dctc; 3307 3308 if (!(attr_mask & IB_QP_STATE)) 3309 return -EINVAL; 3310 3311 cur_state = qp->state; 3312 new_state = attr->qp_state; 3313 3314 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3315 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3316 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3317 if (!is_valid_mask(attr_mask, required, 0)) 3318 return -EINVAL; 3319 3320 if (attr->port_num == 0 || 3321 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3322 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3323 attr->port_num, dev->num_ports); 3324 return -EINVAL; 3325 } 3326 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3327 MLX5_SET(dctc, dctc, rre, 1); 3328 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3329 MLX5_SET(dctc, dctc, rwe, 1); 3330 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3331 if (!mlx5_ib_dc_atomic_is_supported(dev)) 3332 return -EOPNOTSUPP; 3333 MLX5_SET(dctc, dctc, rae, 1); 3334 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX); 3335 } 3336 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3337 MLX5_SET(dctc, dctc, port, attr->port_num); 3338 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3339 3340 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3341 struct mlx5_ib_modify_qp_resp resp = {}; 3342 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3343 sizeof(resp.dctn); 3344 3345 if (udata->outlen < min_resp_len) 3346 return -EINVAL; 3347 resp.response_length = min_resp_len; 3348 3349 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3350 if (!is_valid_mask(attr_mask, required, 0)) 3351 return -EINVAL; 3352 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3353 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3354 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3355 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3356 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3357 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3358 3359 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3360 MLX5_ST_SZ_BYTES(create_dct_in)); 3361 if (err) 3362 return err; 3363 resp.dctn = qp->dct.mdct.mqp.qpn; 3364 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3365 if (err) { 3366 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3367 return err; 3368 } 3369 } else { 3370 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3371 return -EINVAL; 3372 } 3373 if (err) 3374 qp->state = IB_QPS_ERR; 3375 else 3376 qp->state = new_state; 3377 return err; 3378 } 3379 3380 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3381 int attr_mask, struct ib_udata *udata) 3382 { 3383 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3384 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3385 struct mlx5_ib_modify_qp ucmd = {}; 3386 enum ib_qp_type qp_type; 3387 enum ib_qp_state cur_state, new_state; 3388 size_t required_cmd_sz; 3389 int err = -EINVAL; 3390 int port; 3391 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 3392 3393 if (ibqp->rwq_ind_tbl) 3394 return -ENOSYS; 3395 3396 if (udata && udata->inlen) { 3397 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3398 sizeof(ucmd.reserved); 3399 if (udata->inlen < required_cmd_sz) 3400 return -EINVAL; 3401 3402 if (udata->inlen > sizeof(ucmd) && 3403 !ib_is_udata_cleared(udata, sizeof(ucmd), 3404 udata->inlen - sizeof(ucmd))) 3405 return -EOPNOTSUPP; 3406 3407 if (ib_copy_from_udata(&ucmd, udata, 3408 min(udata->inlen, sizeof(ucmd)))) 3409 return -EFAULT; 3410 3411 if (ucmd.comp_mask || 3412 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3413 memchr_inv(&ucmd.burst_info.reserved, 0, 3414 sizeof(ucmd.burst_info.reserved))) 3415 return -EOPNOTSUPP; 3416 } 3417 3418 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3419 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3420 3421 if (ibqp->qp_type == IB_QPT_DRIVER) 3422 qp_type = qp->qp_sub_type; 3423 else 3424 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3425 IB_QPT_GSI : ibqp->qp_type; 3426 3427 if (qp_type == MLX5_IB_QPT_DCT) 3428 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3429 3430 mutex_lock(&qp->mutex); 3431 3432 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3433 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3434 3435 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3436 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3437 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 3438 } 3439 3440 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3441 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3442 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3443 attr_mask); 3444 goto out; 3445 } 3446 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3447 qp_type != MLX5_IB_QPT_DCI && 3448 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 3449 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3450 cur_state, new_state, ibqp->qp_type, attr_mask); 3451 goto out; 3452 } else if (qp_type == MLX5_IB_QPT_DCI && 3453 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3454 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3455 cur_state, new_state, qp_type, attr_mask); 3456 goto out; 3457 } 3458 3459 if ((attr_mask & IB_QP_PORT) && 3460 (attr->port_num == 0 || 3461 attr->port_num > dev->num_ports)) { 3462 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3463 attr->port_num, dev->num_ports); 3464 goto out; 3465 } 3466 3467 if (attr_mask & IB_QP_PKEY_INDEX) { 3468 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3469 if (attr->pkey_index >= 3470 dev->mdev->port_caps[port - 1].pkey_table_len) { 3471 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3472 attr->pkey_index); 3473 goto out; 3474 } 3475 } 3476 3477 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3478 attr->max_rd_atomic > 3479 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3480 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3481 attr->max_rd_atomic); 3482 goto out; 3483 } 3484 3485 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3486 attr->max_dest_rd_atomic > 3487 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3488 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3489 attr->max_dest_rd_atomic); 3490 goto out; 3491 } 3492 3493 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3494 err = 0; 3495 goto out; 3496 } 3497 3498 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3499 new_state, &ucmd); 3500 3501 out: 3502 mutex_unlock(&qp->mutex); 3503 return err; 3504 } 3505 3506 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3507 { 3508 struct mlx5_ib_cq *cq; 3509 unsigned cur; 3510 3511 cur = wq->head - wq->tail; 3512 if (likely(cur + nreq < wq->max_post)) 3513 return 0; 3514 3515 cq = to_mcq(ib_cq); 3516 spin_lock(&cq->lock); 3517 cur = wq->head - wq->tail; 3518 spin_unlock(&cq->lock); 3519 3520 return cur + nreq >= wq->max_post; 3521 } 3522 3523 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3524 u64 remote_addr, u32 rkey) 3525 { 3526 rseg->raddr = cpu_to_be64(remote_addr); 3527 rseg->rkey = cpu_to_be32(rkey); 3528 rseg->reserved = 0; 3529 } 3530 3531 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3532 struct ib_send_wr *wr, void *qend, 3533 struct mlx5_ib_qp *qp, int *size) 3534 { 3535 void *seg = eseg; 3536 3537 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3538 3539 if (wr->send_flags & IB_SEND_IP_CSUM) 3540 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3541 MLX5_ETH_WQE_L4_CSUM; 3542 3543 seg += sizeof(struct mlx5_wqe_eth_seg); 3544 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3545 3546 if (wr->opcode == IB_WR_LSO) { 3547 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3548 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3549 u64 left, leftlen, copysz; 3550 void *pdata = ud_wr->header; 3551 3552 left = ud_wr->hlen; 3553 eseg->mss = cpu_to_be16(ud_wr->mss); 3554 eseg->inline_hdr.sz = cpu_to_be16(left); 3555 3556 /* 3557 * check if there is space till the end of queue, if yes, 3558 * copy all in one shot, otherwise copy till the end of queue, 3559 * rollback and than the copy the left 3560 */ 3561 leftlen = qend - (void *)eseg->inline_hdr.start; 3562 copysz = min_t(u64, leftlen, left); 3563 3564 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3565 3566 if (likely(copysz > size_of_inl_hdr_start)) { 3567 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3568 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3569 } 3570 3571 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3572 seg = mlx5_get_send_wqe(qp, 0); 3573 left -= copysz; 3574 pdata += copysz; 3575 memcpy(seg, pdata, left); 3576 seg += ALIGN(left, 16); 3577 *size += ALIGN(left, 16) / 16; 3578 } 3579 } 3580 3581 return seg; 3582 } 3583 3584 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3585 struct ib_send_wr *wr) 3586 { 3587 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3588 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3589 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3590 } 3591 3592 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3593 { 3594 dseg->byte_count = cpu_to_be32(sg->length); 3595 dseg->lkey = cpu_to_be32(sg->lkey); 3596 dseg->addr = cpu_to_be64(sg->addr); 3597 } 3598 3599 static u64 get_xlt_octo(u64 bytes) 3600 { 3601 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3602 MLX5_IB_UMR_OCTOWORD; 3603 } 3604 3605 static __be64 frwr_mkey_mask(void) 3606 { 3607 u64 result; 3608 3609 result = MLX5_MKEY_MASK_LEN | 3610 MLX5_MKEY_MASK_PAGE_SIZE | 3611 MLX5_MKEY_MASK_START_ADDR | 3612 MLX5_MKEY_MASK_EN_RINVAL | 3613 MLX5_MKEY_MASK_KEY | 3614 MLX5_MKEY_MASK_LR | 3615 MLX5_MKEY_MASK_LW | 3616 MLX5_MKEY_MASK_RR | 3617 MLX5_MKEY_MASK_RW | 3618 MLX5_MKEY_MASK_A | 3619 MLX5_MKEY_MASK_SMALL_FENCE | 3620 MLX5_MKEY_MASK_FREE; 3621 3622 return cpu_to_be64(result); 3623 } 3624 3625 static __be64 sig_mkey_mask(void) 3626 { 3627 u64 result; 3628 3629 result = MLX5_MKEY_MASK_LEN | 3630 MLX5_MKEY_MASK_PAGE_SIZE | 3631 MLX5_MKEY_MASK_START_ADDR | 3632 MLX5_MKEY_MASK_EN_SIGERR | 3633 MLX5_MKEY_MASK_EN_RINVAL | 3634 MLX5_MKEY_MASK_KEY | 3635 MLX5_MKEY_MASK_LR | 3636 MLX5_MKEY_MASK_LW | 3637 MLX5_MKEY_MASK_RR | 3638 MLX5_MKEY_MASK_RW | 3639 MLX5_MKEY_MASK_SMALL_FENCE | 3640 MLX5_MKEY_MASK_FREE | 3641 MLX5_MKEY_MASK_BSF_EN; 3642 3643 return cpu_to_be64(result); 3644 } 3645 3646 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3647 struct mlx5_ib_mr *mr, bool umr_inline) 3648 { 3649 int size = mr->ndescs * mr->desc_size; 3650 3651 memset(umr, 0, sizeof(*umr)); 3652 3653 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3654 if (umr_inline) 3655 umr->flags |= MLX5_UMR_INLINE; 3656 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3657 umr->mkey_mask = frwr_mkey_mask(); 3658 } 3659 3660 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3661 { 3662 memset(umr, 0, sizeof(*umr)); 3663 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3664 umr->flags = MLX5_UMR_INLINE; 3665 } 3666 3667 static __be64 get_umr_enable_mr_mask(void) 3668 { 3669 u64 result; 3670 3671 result = MLX5_MKEY_MASK_KEY | 3672 MLX5_MKEY_MASK_FREE; 3673 3674 return cpu_to_be64(result); 3675 } 3676 3677 static __be64 get_umr_disable_mr_mask(void) 3678 { 3679 u64 result; 3680 3681 result = MLX5_MKEY_MASK_FREE; 3682 3683 return cpu_to_be64(result); 3684 } 3685 3686 static __be64 get_umr_update_translation_mask(void) 3687 { 3688 u64 result; 3689 3690 result = MLX5_MKEY_MASK_LEN | 3691 MLX5_MKEY_MASK_PAGE_SIZE | 3692 MLX5_MKEY_MASK_START_ADDR; 3693 3694 return cpu_to_be64(result); 3695 } 3696 3697 static __be64 get_umr_update_access_mask(int atomic) 3698 { 3699 u64 result; 3700 3701 result = MLX5_MKEY_MASK_LR | 3702 MLX5_MKEY_MASK_LW | 3703 MLX5_MKEY_MASK_RR | 3704 MLX5_MKEY_MASK_RW; 3705 3706 if (atomic) 3707 result |= MLX5_MKEY_MASK_A; 3708 3709 return cpu_to_be64(result); 3710 } 3711 3712 static __be64 get_umr_update_pd_mask(void) 3713 { 3714 u64 result; 3715 3716 result = MLX5_MKEY_MASK_PD; 3717 3718 return cpu_to_be64(result); 3719 } 3720 3721 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 3722 { 3723 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 3724 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 3725 (mask & MLX5_MKEY_MASK_A && 3726 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 3727 return -EPERM; 3728 return 0; 3729 } 3730 3731 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 3732 struct mlx5_wqe_umr_ctrl_seg *umr, 3733 struct ib_send_wr *wr, int atomic) 3734 { 3735 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3736 3737 memset(umr, 0, sizeof(*umr)); 3738 3739 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3740 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3741 else 3742 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3743 3744 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3745 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3746 u64 offset = get_xlt_octo(umrwr->offset); 3747 3748 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3749 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3750 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3751 } 3752 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3753 umr->mkey_mask |= get_umr_update_translation_mask(); 3754 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3755 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3756 umr->mkey_mask |= get_umr_update_pd_mask(); 3757 } 3758 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3759 umr->mkey_mask |= get_umr_enable_mr_mask(); 3760 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3761 umr->mkey_mask |= get_umr_disable_mr_mask(); 3762 3763 if (!wr->num_sge) 3764 umr->flags |= MLX5_UMR_INLINE; 3765 3766 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 3767 } 3768 3769 static u8 get_umr_flags(int acc) 3770 { 3771 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3772 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3773 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3774 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3775 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3776 } 3777 3778 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3779 struct mlx5_ib_mr *mr, 3780 u32 key, int access) 3781 { 3782 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3783 3784 memset(seg, 0, sizeof(*seg)); 3785 3786 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3787 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3788 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3789 /* KLMs take twice the size of MTTs */ 3790 ndescs *= 2; 3791 3792 seg->flags = get_umr_flags(access) | mr->access_mode; 3793 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3794 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3795 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3796 seg->len = cpu_to_be64(mr->ibmr.length); 3797 seg->xlt_oct_size = cpu_to_be32(ndescs); 3798 } 3799 3800 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3801 { 3802 memset(seg, 0, sizeof(*seg)); 3803 seg->status = MLX5_MKEY_STATUS_FREE; 3804 } 3805 3806 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3807 { 3808 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3809 3810 memset(seg, 0, sizeof(*seg)); 3811 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3812 seg->status = MLX5_MKEY_STATUS_FREE; 3813 3814 seg->flags = convert_access(umrwr->access_flags); 3815 if (umrwr->pd) 3816 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3817 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3818 !umrwr->length) 3819 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3820 3821 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3822 seg->len = cpu_to_be64(umrwr->length); 3823 seg->log2_page_size = umrwr->page_shift; 3824 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3825 mlx5_mkey_variant(umrwr->mkey)); 3826 } 3827 3828 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3829 struct mlx5_ib_mr *mr, 3830 struct mlx5_ib_pd *pd) 3831 { 3832 int bcount = mr->desc_size * mr->ndescs; 3833 3834 dseg->addr = cpu_to_be64(mr->desc_map); 3835 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3836 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3837 } 3838 3839 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp, 3840 struct mlx5_ib_mr *mr, int mr_list_size) 3841 { 3842 void *qend = qp->sq.qend; 3843 void *addr = mr->descs; 3844 int copy; 3845 3846 if (unlikely(seg + mr_list_size > qend)) { 3847 copy = qend - seg; 3848 memcpy(seg, addr, copy); 3849 addr += copy; 3850 mr_list_size -= copy; 3851 seg = mlx5_get_send_wqe(qp, 0); 3852 } 3853 memcpy(seg, addr, mr_list_size); 3854 seg += mr_list_size; 3855 } 3856 3857 static __be32 send_ieth(struct ib_send_wr *wr) 3858 { 3859 switch (wr->opcode) { 3860 case IB_WR_SEND_WITH_IMM: 3861 case IB_WR_RDMA_WRITE_WITH_IMM: 3862 return wr->ex.imm_data; 3863 3864 case IB_WR_SEND_WITH_INV: 3865 return cpu_to_be32(wr->ex.invalidate_rkey); 3866 3867 default: 3868 return 0; 3869 } 3870 } 3871 3872 static u8 calc_sig(void *wqe, int size) 3873 { 3874 u8 *p = wqe; 3875 u8 res = 0; 3876 int i; 3877 3878 for (i = 0; i < size; i++) 3879 res ^= p[i]; 3880 3881 return ~res; 3882 } 3883 3884 static u8 wq_sig(void *wqe) 3885 { 3886 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3887 } 3888 3889 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3890 void *wqe, int *sz) 3891 { 3892 struct mlx5_wqe_inline_seg *seg; 3893 void *qend = qp->sq.qend; 3894 void *addr; 3895 int inl = 0; 3896 int copy; 3897 int len; 3898 int i; 3899 3900 seg = wqe; 3901 wqe += sizeof(*seg); 3902 for (i = 0; i < wr->num_sge; i++) { 3903 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3904 len = wr->sg_list[i].length; 3905 inl += len; 3906 3907 if (unlikely(inl > qp->max_inline_data)) 3908 return -ENOMEM; 3909 3910 if (unlikely(wqe + len > qend)) { 3911 copy = qend - wqe; 3912 memcpy(wqe, addr, copy); 3913 addr += copy; 3914 len -= copy; 3915 wqe = mlx5_get_send_wqe(qp, 0); 3916 } 3917 memcpy(wqe, addr, len); 3918 wqe += len; 3919 } 3920 3921 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3922 3923 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3924 3925 return 0; 3926 } 3927 3928 static u16 prot_field_size(enum ib_signature_type type) 3929 { 3930 switch (type) { 3931 case IB_SIG_TYPE_T10_DIF: 3932 return MLX5_DIF_SIZE; 3933 default: 3934 return 0; 3935 } 3936 } 3937 3938 static u8 bs_selector(int block_size) 3939 { 3940 switch (block_size) { 3941 case 512: return 0x1; 3942 case 520: return 0x2; 3943 case 4096: return 0x3; 3944 case 4160: return 0x4; 3945 case 1073741824: return 0x5; 3946 default: return 0; 3947 } 3948 } 3949 3950 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3951 struct mlx5_bsf_inl *inl) 3952 { 3953 /* Valid inline section and allow BSF refresh */ 3954 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3955 MLX5_BSF_REFRESH_DIF); 3956 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3957 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3958 /* repeating block */ 3959 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3960 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3961 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3962 3963 if (domain->sig.dif.ref_remap) 3964 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3965 3966 if (domain->sig.dif.app_escape) { 3967 if (domain->sig.dif.ref_escape) 3968 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3969 else 3970 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3971 } 3972 3973 inl->dif_app_bitmask_check = 3974 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3975 } 3976 3977 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3978 struct ib_sig_attrs *sig_attrs, 3979 struct mlx5_bsf *bsf, u32 data_size) 3980 { 3981 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3982 struct mlx5_bsf_basic *basic = &bsf->basic; 3983 struct ib_sig_domain *mem = &sig_attrs->mem; 3984 struct ib_sig_domain *wire = &sig_attrs->wire; 3985 3986 memset(bsf, 0, sizeof(*bsf)); 3987 3988 /* Basic + Extended + Inline */ 3989 basic->bsf_size_sbs = 1 << 7; 3990 /* Input domain check byte mask */ 3991 basic->check_byte_mask = sig_attrs->check_mask; 3992 basic->raw_data_size = cpu_to_be32(data_size); 3993 3994 /* Memory domain */ 3995 switch (sig_attrs->mem.sig_type) { 3996 case IB_SIG_TYPE_NONE: 3997 break; 3998 case IB_SIG_TYPE_T10_DIF: 3999 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4000 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4001 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4002 break; 4003 default: 4004 return -EINVAL; 4005 } 4006 4007 /* Wire domain */ 4008 switch (sig_attrs->wire.sig_type) { 4009 case IB_SIG_TYPE_NONE: 4010 break; 4011 case IB_SIG_TYPE_T10_DIF: 4012 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4013 mem->sig_type == wire->sig_type) { 4014 /* Same block structure */ 4015 basic->bsf_size_sbs |= 1 << 4; 4016 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4017 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4018 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4019 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4020 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4021 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4022 } else 4023 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4024 4025 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4026 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4027 break; 4028 default: 4029 return -EINVAL; 4030 } 4031 4032 return 0; 4033 } 4034 4035 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 4036 struct mlx5_ib_qp *qp, void **seg, int *size) 4037 { 4038 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4039 struct ib_mr *sig_mr = wr->sig_mr; 4040 struct mlx5_bsf *bsf; 4041 u32 data_len = wr->wr.sg_list->length; 4042 u32 data_key = wr->wr.sg_list->lkey; 4043 u64 data_va = wr->wr.sg_list->addr; 4044 int ret; 4045 int wqe_size; 4046 4047 if (!wr->prot || 4048 (data_key == wr->prot->lkey && 4049 data_va == wr->prot->addr && 4050 data_len == wr->prot->length)) { 4051 /** 4052 * Source domain doesn't contain signature information 4053 * or data and protection are interleaved in memory. 4054 * So need construct: 4055 * ------------------ 4056 * | data_klm | 4057 * ------------------ 4058 * | BSF | 4059 * ------------------ 4060 **/ 4061 struct mlx5_klm *data_klm = *seg; 4062 4063 data_klm->bcount = cpu_to_be32(data_len); 4064 data_klm->key = cpu_to_be32(data_key); 4065 data_klm->va = cpu_to_be64(data_va); 4066 wqe_size = ALIGN(sizeof(*data_klm), 64); 4067 } else { 4068 /** 4069 * Source domain contains signature information 4070 * So need construct a strided block format: 4071 * --------------------------- 4072 * | stride_block_ctrl | 4073 * --------------------------- 4074 * | data_klm | 4075 * --------------------------- 4076 * | prot_klm | 4077 * --------------------------- 4078 * | BSF | 4079 * --------------------------- 4080 **/ 4081 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4082 struct mlx5_stride_block_entry *data_sentry; 4083 struct mlx5_stride_block_entry *prot_sentry; 4084 u32 prot_key = wr->prot->lkey; 4085 u64 prot_va = wr->prot->addr; 4086 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4087 int prot_size; 4088 4089 sblock_ctrl = *seg; 4090 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4091 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4092 4093 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4094 if (!prot_size) { 4095 pr_err("Bad block size given: %u\n", block_size); 4096 return -EINVAL; 4097 } 4098 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4099 prot_size); 4100 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4101 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4102 sblock_ctrl->num_entries = cpu_to_be16(2); 4103 4104 data_sentry->bcount = cpu_to_be16(block_size); 4105 data_sentry->key = cpu_to_be32(data_key); 4106 data_sentry->va = cpu_to_be64(data_va); 4107 data_sentry->stride = cpu_to_be16(block_size); 4108 4109 prot_sentry->bcount = cpu_to_be16(prot_size); 4110 prot_sentry->key = cpu_to_be32(prot_key); 4111 prot_sentry->va = cpu_to_be64(prot_va); 4112 prot_sentry->stride = cpu_to_be16(prot_size); 4113 4114 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4115 sizeof(*prot_sentry), 64); 4116 } 4117 4118 *seg += wqe_size; 4119 *size += wqe_size / 16; 4120 if (unlikely((*seg == qp->sq.qend))) 4121 *seg = mlx5_get_send_wqe(qp, 0); 4122 4123 bsf = *seg; 4124 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4125 if (ret) 4126 return -EINVAL; 4127 4128 *seg += sizeof(*bsf); 4129 *size += sizeof(*bsf) / 16; 4130 if (unlikely((*seg == qp->sq.qend))) 4131 *seg = mlx5_get_send_wqe(qp, 0); 4132 4133 return 0; 4134 } 4135 4136 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4137 struct ib_sig_handover_wr *wr, u32 size, 4138 u32 length, u32 pdn) 4139 { 4140 struct ib_mr *sig_mr = wr->sig_mr; 4141 u32 sig_key = sig_mr->rkey; 4142 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4143 4144 memset(seg, 0, sizeof(*seg)); 4145 4146 seg->flags = get_umr_flags(wr->access_flags) | 4147 MLX5_MKC_ACCESS_MODE_KLMS; 4148 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4149 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4150 MLX5_MKEY_BSF_EN | pdn); 4151 seg->len = cpu_to_be64(length); 4152 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4153 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4154 } 4155 4156 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4157 u32 size) 4158 { 4159 memset(umr, 0, sizeof(*umr)); 4160 4161 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4162 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4163 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4164 umr->mkey_mask = sig_mkey_mask(); 4165 } 4166 4167 4168 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 4169 void **seg, int *size) 4170 { 4171 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4172 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4173 u32 pdn = get_pd(qp)->pdn; 4174 u32 xlt_size; 4175 int region_len, ret; 4176 4177 if (unlikely(wr->wr.num_sge != 1) || 4178 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4179 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4180 unlikely(!sig_mr->sig->sig_status_checked)) 4181 return -EINVAL; 4182 4183 /* length of the protected region, data + protection */ 4184 region_len = wr->wr.sg_list->length; 4185 if (wr->prot && 4186 (wr->prot->lkey != wr->wr.sg_list->lkey || 4187 wr->prot->addr != wr->wr.sg_list->addr || 4188 wr->prot->length != wr->wr.sg_list->length)) 4189 region_len += wr->prot->length; 4190 4191 /** 4192 * KLM octoword size - if protection was provided 4193 * then we use strided block format (3 octowords), 4194 * else we use single KLM (1 octoword) 4195 **/ 4196 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4197 4198 set_sig_umr_segment(*seg, xlt_size); 4199 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4200 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4201 if (unlikely((*seg == qp->sq.qend))) 4202 *seg = mlx5_get_send_wqe(qp, 0); 4203 4204 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4205 *seg += sizeof(struct mlx5_mkey_seg); 4206 *size += sizeof(struct mlx5_mkey_seg) / 16; 4207 if (unlikely((*seg == qp->sq.qend))) 4208 *seg = mlx5_get_send_wqe(qp, 0); 4209 4210 ret = set_sig_data_segment(wr, qp, seg, size); 4211 if (ret) 4212 return ret; 4213 4214 sig_mr->sig->sig_status_checked = false; 4215 return 0; 4216 } 4217 4218 static int set_psv_wr(struct ib_sig_domain *domain, 4219 u32 psv_idx, void **seg, int *size) 4220 { 4221 struct mlx5_seg_set_psv *psv_seg = *seg; 4222 4223 memset(psv_seg, 0, sizeof(*psv_seg)); 4224 psv_seg->psv_num = cpu_to_be32(psv_idx); 4225 switch (domain->sig_type) { 4226 case IB_SIG_TYPE_NONE: 4227 break; 4228 case IB_SIG_TYPE_T10_DIF: 4229 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4230 domain->sig.dif.app_tag); 4231 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4232 break; 4233 default: 4234 pr_err("Bad signature type (%d) is given.\n", 4235 domain->sig_type); 4236 return -EINVAL; 4237 } 4238 4239 *seg += sizeof(*psv_seg); 4240 *size += sizeof(*psv_seg) / 16; 4241 4242 return 0; 4243 } 4244 4245 static int set_reg_wr(struct mlx5_ib_qp *qp, 4246 struct ib_reg_wr *wr, 4247 void **seg, int *size) 4248 { 4249 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4250 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4251 int mr_list_size = mr->ndescs * mr->desc_size; 4252 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4253 4254 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4255 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4256 "Invalid IB_SEND_INLINE send flag\n"); 4257 return -EINVAL; 4258 } 4259 4260 set_reg_umr_seg(*seg, mr, umr_inline); 4261 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4262 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4263 if (unlikely((*seg == qp->sq.qend))) 4264 *seg = mlx5_get_send_wqe(qp, 0); 4265 4266 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4267 *seg += sizeof(struct mlx5_mkey_seg); 4268 *size += sizeof(struct mlx5_mkey_seg) / 16; 4269 if (unlikely((*seg == qp->sq.qend))) 4270 *seg = mlx5_get_send_wqe(qp, 0); 4271 4272 if (umr_inline) { 4273 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size); 4274 *size += get_xlt_octo(mr_list_size); 4275 } else { 4276 set_reg_data_seg(*seg, mr, pd); 4277 *seg += sizeof(struct mlx5_wqe_data_seg); 4278 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4279 } 4280 return 0; 4281 } 4282 4283 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 4284 { 4285 set_linv_umr_seg(*seg); 4286 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4287 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4288 if (unlikely((*seg == qp->sq.qend))) 4289 *seg = mlx5_get_send_wqe(qp, 0); 4290 set_linv_mkey_seg(*seg); 4291 *seg += sizeof(struct mlx5_mkey_seg); 4292 *size += sizeof(struct mlx5_mkey_seg) / 16; 4293 if (unlikely((*seg == qp->sq.qend))) 4294 *seg = mlx5_get_send_wqe(qp, 0); 4295 } 4296 4297 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 4298 { 4299 __be32 *p = NULL; 4300 int tidx = idx; 4301 int i, j; 4302 4303 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 4304 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4305 if ((i & 0xf) == 0) { 4306 void *buf = mlx5_get_send_wqe(qp, tidx); 4307 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4308 p = buf; 4309 j = 0; 4310 } 4311 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4312 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4313 be32_to_cpu(p[j + 3])); 4314 } 4315 } 4316 4317 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4318 struct mlx5_wqe_ctrl_seg **ctrl, 4319 struct ib_send_wr *wr, unsigned *idx, 4320 int *size, int nreq) 4321 { 4322 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4323 return -ENOMEM; 4324 4325 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4326 *seg = mlx5_get_send_wqe(qp, *idx); 4327 *ctrl = *seg; 4328 *(uint32_t *)(*seg + 8) = 0; 4329 (*ctrl)->imm = send_ieth(wr); 4330 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4331 (wr->send_flags & IB_SEND_SIGNALED ? 4332 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4333 (wr->send_flags & IB_SEND_SOLICITED ? 4334 MLX5_WQE_CTRL_SOLICITED : 0); 4335 4336 *seg += sizeof(**ctrl); 4337 *size = sizeof(**ctrl) / 16; 4338 4339 return 0; 4340 } 4341 4342 static void finish_wqe(struct mlx5_ib_qp *qp, 4343 struct mlx5_wqe_ctrl_seg *ctrl, 4344 u8 size, unsigned idx, u64 wr_id, 4345 int nreq, u8 fence, u32 mlx5_opcode) 4346 { 4347 u8 opmod = 0; 4348 4349 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4350 mlx5_opcode | ((u32)opmod << 24)); 4351 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4352 ctrl->fm_ce_se |= fence; 4353 if (unlikely(qp->wq_sig)) 4354 ctrl->signature = wq_sig(ctrl); 4355 4356 qp->sq.wrid[idx] = wr_id; 4357 qp->sq.w_list[idx].opcode = mlx5_opcode; 4358 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4359 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4360 qp->sq.w_list[idx].next = qp->sq.cur_post; 4361 } 4362 4363 4364 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 4365 struct ib_send_wr **bad_wr) 4366 { 4367 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4368 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4369 struct mlx5_core_dev *mdev = dev->mdev; 4370 struct mlx5_ib_qp *qp; 4371 struct mlx5_ib_mr *mr; 4372 struct mlx5_wqe_data_seg *dpseg; 4373 struct mlx5_wqe_xrc_seg *xrc; 4374 struct mlx5_bf *bf; 4375 int uninitialized_var(size); 4376 void *qend; 4377 unsigned long flags; 4378 unsigned idx; 4379 int err = 0; 4380 int num_sge; 4381 void *seg; 4382 int nreq; 4383 int i; 4384 u8 next_fence = 0; 4385 u8 fence; 4386 4387 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4388 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4389 4390 qp = to_mqp(ibqp); 4391 bf = &qp->bf; 4392 qend = qp->sq.qend; 4393 4394 spin_lock_irqsave(&qp->sq.lock, flags); 4395 4396 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4397 err = -EIO; 4398 *bad_wr = wr; 4399 nreq = 0; 4400 goto out; 4401 } 4402 4403 for (nreq = 0; wr; nreq++, wr = wr->next) { 4404 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4405 mlx5_ib_warn(dev, "\n"); 4406 err = -EINVAL; 4407 *bad_wr = wr; 4408 goto out; 4409 } 4410 4411 num_sge = wr->num_sge; 4412 if (unlikely(num_sge > qp->sq.max_gs)) { 4413 mlx5_ib_warn(dev, "\n"); 4414 err = -EINVAL; 4415 *bad_wr = wr; 4416 goto out; 4417 } 4418 4419 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 4420 if (err) { 4421 mlx5_ib_warn(dev, "\n"); 4422 err = -ENOMEM; 4423 *bad_wr = wr; 4424 goto out; 4425 } 4426 4427 if (wr->opcode == IB_WR_LOCAL_INV || 4428 wr->opcode == IB_WR_REG_MR) { 4429 fence = dev->umr_fence; 4430 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4431 } else if (wr->send_flags & IB_SEND_FENCE) { 4432 if (qp->next_fence) 4433 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4434 else 4435 fence = MLX5_FENCE_MODE_FENCE; 4436 } else { 4437 fence = qp->next_fence; 4438 } 4439 4440 switch (ibqp->qp_type) { 4441 case IB_QPT_XRC_INI: 4442 xrc = seg; 4443 seg += sizeof(*xrc); 4444 size += sizeof(*xrc) / 16; 4445 /* fall through */ 4446 case IB_QPT_RC: 4447 switch (wr->opcode) { 4448 case IB_WR_RDMA_READ: 4449 case IB_WR_RDMA_WRITE: 4450 case IB_WR_RDMA_WRITE_WITH_IMM: 4451 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4452 rdma_wr(wr)->rkey); 4453 seg += sizeof(struct mlx5_wqe_raddr_seg); 4454 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4455 break; 4456 4457 case IB_WR_ATOMIC_CMP_AND_SWP: 4458 case IB_WR_ATOMIC_FETCH_AND_ADD: 4459 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4460 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4461 err = -ENOSYS; 4462 *bad_wr = wr; 4463 goto out; 4464 4465 case IB_WR_LOCAL_INV: 4466 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4467 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4468 set_linv_wr(qp, &seg, &size); 4469 num_sge = 0; 4470 break; 4471 4472 case IB_WR_REG_MR: 4473 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4474 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4475 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4476 if (err) { 4477 *bad_wr = wr; 4478 goto out; 4479 } 4480 num_sge = 0; 4481 break; 4482 4483 case IB_WR_REG_SIG_MR: 4484 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4485 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4486 4487 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4488 err = set_sig_umr_wr(wr, qp, &seg, &size); 4489 if (err) { 4490 mlx5_ib_warn(dev, "\n"); 4491 *bad_wr = wr; 4492 goto out; 4493 } 4494 4495 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4496 fence, MLX5_OPCODE_UMR); 4497 /* 4498 * SET_PSV WQEs are not signaled and solicited 4499 * on error 4500 */ 4501 wr->send_flags &= ~IB_SEND_SIGNALED; 4502 wr->send_flags |= IB_SEND_SOLICITED; 4503 err = begin_wqe(qp, &seg, &ctrl, wr, 4504 &idx, &size, nreq); 4505 if (err) { 4506 mlx5_ib_warn(dev, "\n"); 4507 err = -ENOMEM; 4508 *bad_wr = wr; 4509 goto out; 4510 } 4511 4512 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4513 mr->sig->psv_memory.psv_idx, &seg, 4514 &size); 4515 if (err) { 4516 mlx5_ib_warn(dev, "\n"); 4517 *bad_wr = wr; 4518 goto out; 4519 } 4520 4521 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4522 fence, MLX5_OPCODE_SET_PSV); 4523 err = begin_wqe(qp, &seg, &ctrl, wr, 4524 &idx, &size, nreq); 4525 if (err) { 4526 mlx5_ib_warn(dev, "\n"); 4527 err = -ENOMEM; 4528 *bad_wr = wr; 4529 goto out; 4530 } 4531 4532 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4533 mr->sig->psv_wire.psv_idx, &seg, 4534 &size); 4535 if (err) { 4536 mlx5_ib_warn(dev, "\n"); 4537 *bad_wr = wr; 4538 goto out; 4539 } 4540 4541 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4542 fence, MLX5_OPCODE_SET_PSV); 4543 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4544 num_sge = 0; 4545 goto skip_psv; 4546 4547 default: 4548 break; 4549 } 4550 break; 4551 4552 case IB_QPT_UC: 4553 switch (wr->opcode) { 4554 case IB_WR_RDMA_WRITE: 4555 case IB_WR_RDMA_WRITE_WITH_IMM: 4556 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4557 rdma_wr(wr)->rkey); 4558 seg += sizeof(struct mlx5_wqe_raddr_seg); 4559 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4560 break; 4561 4562 default: 4563 break; 4564 } 4565 break; 4566 4567 case IB_QPT_SMI: 4568 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4569 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4570 err = -EPERM; 4571 *bad_wr = wr; 4572 goto out; 4573 } 4574 /* fall through */ 4575 case MLX5_IB_QPT_HW_GSI: 4576 set_datagram_seg(seg, wr); 4577 seg += sizeof(struct mlx5_wqe_datagram_seg); 4578 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4579 if (unlikely((seg == qend))) 4580 seg = mlx5_get_send_wqe(qp, 0); 4581 break; 4582 case IB_QPT_UD: 4583 set_datagram_seg(seg, wr); 4584 seg += sizeof(struct mlx5_wqe_datagram_seg); 4585 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4586 4587 if (unlikely((seg == qend))) 4588 seg = mlx5_get_send_wqe(qp, 0); 4589 4590 /* handle qp that supports ud offload */ 4591 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4592 struct mlx5_wqe_eth_pad *pad; 4593 4594 pad = seg; 4595 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4596 seg += sizeof(struct mlx5_wqe_eth_pad); 4597 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4598 4599 seg = set_eth_seg(seg, wr, qend, qp, &size); 4600 4601 if (unlikely((seg == qend))) 4602 seg = mlx5_get_send_wqe(qp, 0); 4603 } 4604 break; 4605 case MLX5_IB_QPT_REG_UMR: 4606 if (wr->opcode != MLX5_IB_WR_UMR) { 4607 err = -EINVAL; 4608 mlx5_ib_warn(dev, "bad opcode\n"); 4609 goto out; 4610 } 4611 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4612 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4613 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4614 if (unlikely(err)) 4615 goto out; 4616 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4617 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4618 if (unlikely((seg == qend))) 4619 seg = mlx5_get_send_wqe(qp, 0); 4620 set_reg_mkey_segment(seg, wr); 4621 seg += sizeof(struct mlx5_mkey_seg); 4622 size += sizeof(struct mlx5_mkey_seg) / 16; 4623 if (unlikely((seg == qend))) 4624 seg = mlx5_get_send_wqe(qp, 0); 4625 break; 4626 4627 default: 4628 break; 4629 } 4630 4631 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4632 int uninitialized_var(sz); 4633 4634 err = set_data_inl_seg(qp, wr, seg, &sz); 4635 if (unlikely(err)) { 4636 mlx5_ib_warn(dev, "\n"); 4637 *bad_wr = wr; 4638 goto out; 4639 } 4640 size += sz; 4641 } else { 4642 dpseg = seg; 4643 for (i = 0; i < num_sge; i++) { 4644 if (unlikely(dpseg == qend)) { 4645 seg = mlx5_get_send_wqe(qp, 0); 4646 dpseg = seg; 4647 } 4648 if (likely(wr->sg_list[i].length)) { 4649 set_data_ptr_seg(dpseg, wr->sg_list + i); 4650 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4651 dpseg++; 4652 } 4653 } 4654 } 4655 4656 qp->next_fence = next_fence; 4657 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4658 mlx5_ib_opcode[wr->opcode]); 4659 skip_psv: 4660 if (0) 4661 dump_wqe(qp, idx, size); 4662 } 4663 4664 out: 4665 if (likely(nreq)) { 4666 qp->sq.head += nreq; 4667 4668 /* Make sure that descriptors are written before 4669 * updating doorbell record and ringing the doorbell 4670 */ 4671 wmb(); 4672 4673 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4674 4675 /* Make sure doorbell record is visible to the HCA before 4676 * we hit doorbell */ 4677 wmb(); 4678 4679 /* currently we support only regular doorbells */ 4680 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4681 /* Make sure doorbells don't leak out of SQ spinlock 4682 * and reach the HCA out of order. 4683 */ 4684 mmiowb(); 4685 bf->offset ^= bf->buf_size; 4686 } 4687 4688 spin_unlock_irqrestore(&qp->sq.lock, flags); 4689 4690 return err; 4691 } 4692 4693 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4694 { 4695 sig->signature = calc_sig(sig, size); 4696 } 4697 4698 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4699 struct ib_recv_wr **bad_wr) 4700 { 4701 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4702 struct mlx5_wqe_data_seg *scat; 4703 struct mlx5_rwqe_sig *sig; 4704 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4705 struct mlx5_core_dev *mdev = dev->mdev; 4706 unsigned long flags; 4707 int err = 0; 4708 int nreq; 4709 int ind; 4710 int i; 4711 4712 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4713 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4714 4715 spin_lock_irqsave(&qp->rq.lock, flags); 4716 4717 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4718 err = -EIO; 4719 *bad_wr = wr; 4720 nreq = 0; 4721 goto out; 4722 } 4723 4724 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4725 4726 for (nreq = 0; wr; nreq++, wr = wr->next) { 4727 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4728 err = -ENOMEM; 4729 *bad_wr = wr; 4730 goto out; 4731 } 4732 4733 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4734 err = -EINVAL; 4735 *bad_wr = wr; 4736 goto out; 4737 } 4738 4739 scat = get_recv_wqe(qp, ind); 4740 if (qp->wq_sig) 4741 scat++; 4742 4743 for (i = 0; i < wr->num_sge; i++) 4744 set_data_ptr_seg(scat + i, wr->sg_list + i); 4745 4746 if (i < qp->rq.max_gs) { 4747 scat[i].byte_count = 0; 4748 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4749 scat[i].addr = 0; 4750 } 4751 4752 if (qp->wq_sig) { 4753 sig = (struct mlx5_rwqe_sig *)scat; 4754 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4755 } 4756 4757 qp->rq.wrid[ind] = wr->wr_id; 4758 4759 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4760 } 4761 4762 out: 4763 if (likely(nreq)) { 4764 qp->rq.head += nreq; 4765 4766 /* Make sure that descriptors are written before 4767 * doorbell record. 4768 */ 4769 wmb(); 4770 4771 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4772 } 4773 4774 spin_unlock_irqrestore(&qp->rq.lock, flags); 4775 4776 return err; 4777 } 4778 4779 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4780 { 4781 switch (mlx5_state) { 4782 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4783 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4784 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4785 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4786 case MLX5_QP_STATE_SQ_DRAINING: 4787 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4788 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4789 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4790 default: return -1; 4791 } 4792 } 4793 4794 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4795 { 4796 switch (mlx5_mig_state) { 4797 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4798 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4799 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4800 default: return -1; 4801 } 4802 } 4803 4804 static int to_ib_qp_access_flags(int mlx5_flags) 4805 { 4806 int ib_flags = 0; 4807 4808 if (mlx5_flags & MLX5_QP_BIT_RRE) 4809 ib_flags |= IB_ACCESS_REMOTE_READ; 4810 if (mlx5_flags & MLX5_QP_BIT_RWE) 4811 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4812 if (mlx5_flags & MLX5_QP_BIT_RAE) 4813 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4814 4815 return ib_flags; 4816 } 4817 4818 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4819 struct rdma_ah_attr *ah_attr, 4820 struct mlx5_qp_path *path) 4821 { 4822 4823 memset(ah_attr, 0, sizeof(*ah_attr)); 4824 4825 if (!path->port || path->port > ibdev->num_ports) 4826 return; 4827 4828 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4829 4830 rdma_ah_set_port_num(ah_attr, path->port); 4831 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4832 4833 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4834 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4835 rdma_ah_set_static_rate(ah_attr, 4836 path->static_rate ? path->static_rate - 5 : 0); 4837 if (path->grh_mlid & (1 << 7)) { 4838 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4839 4840 rdma_ah_set_grh(ah_attr, NULL, 4841 tc_fl & 0xfffff, 4842 path->mgid_index, 4843 path->hop_limit, 4844 (tc_fl >> 20) & 0xff); 4845 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4846 } 4847 } 4848 4849 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4850 struct mlx5_ib_sq *sq, 4851 u8 *sq_state) 4852 { 4853 int err; 4854 4855 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4856 if (err) 4857 goto out; 4858 sq->state = *sq_state; 4859 4860 out: 4861 return err; 4862 } 4863 4864 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4865 struct mlx5_ib_rq *rq, 4866 u8 *rq_state) 4867 { 4868 void *out; 4869 void *rqc; 4870 int inlen; 4871 int err; 4872 4873 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4874 out = kvzalloc(inlen, GFP_KERNEL); 4875 if (!out) 4876 return -ENOMEM; 4877 4878 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4879 if (err) 4880 goto out; 4881 4882 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4883 *rq_state = MLX5_GET(rqc, rqc, state); 4884 rq->state = *rq_state; 4885 4886 out: 4887 kvfree(out); 4888 return err; 4889 } 4890 4891 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4892 struct mlx5_ib_qp *qp, u8 *qp_state) 4893 { 4894 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4895 [MLX5_RQC_STATE_RST] = { 4896 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4897 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4898 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4899 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4900 }, 4901 [MLX5_RQC_STATE_RDY] = { 4902 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4903 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4904 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4905 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4906 }, 4907 [MLX5_RQC_STATE_ERR] = { 4908 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4909 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4910 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4911 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4912 }, 4913 [MLX5_RQ_STATE_NA] = { 4914 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4915 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4916 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4917 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4918 }, 4919 }; 4920 4921 *qp_state = sqrq_trans[rq_state][sq_state]; 4922 4923 if (*qp_state == MLX5_QP_STATE_BAD) { 4924 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4925 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4926 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4927 return -EINVAL; 4928 } 4929 4930 if (*qp_state == MLX5_QP_STATE) 4931 *qp_state = qp->state; 4932 4933 return 0; 4934 } 4935 4936 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4937 struct mlx5_ib_qp *qp, 4938 u8 *raw_packet_qp_state) 4939 { 4940 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4941 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4942 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4943 int err; 4944 u8 sq_state = MLX5_SQ_STATE_NA; 4945 u8 rq_state = MLX5_RQ_STATE_NA; 4946 4947 if (qp->sq.wqe_cnt) { 4948 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4949 if (err) 4950 return err; 4951 } 4952 4953 if (qp->rq.wqe_cnt) { 4954 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4955 if (err) 4956 return err; 4957 } 4958 4959 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4960 raw_packet_qp_state); 4961 } 4962 4963 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4964 struct ib_qp_attr *qp_attr) 4965 { 4966 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4967 struct mlx5_qp_context *context; 4968 int mlx5_state; 4969 u32 *outb; 4970 int err = 0; 4971 4972 outb = kzalloc(outlen, GFP_KERNEL); 4973 if (!outb) 4974 return -ENOMEM; 4975 4976 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4977 outlen); 4978 if (err) 4979 goto out; 4980 4981 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4982 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4983 4984 mlx5_state = be32_to_cpu(context->flags) >> 28; 4985 4986 qp->state = to_ib_qp_state(mlx5_state); 4987 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4988 qp_attr->path_mig_state = 4989 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4990 qp_attr->qkey = be32_to_cpu(context->qkey); 4991 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4992 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4993 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4994 qp_attr->qp_access_flags = 4995 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4996 4997 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4998 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4999 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5000 qp_attr->alt_pkey_index = 5001 be16_to_cpu(context->alt_path.pkey_index); 5002 qp_attr->alt_port_num = 5003 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5004 } 5005 5006 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5007 qp_attr->port_num = context->pri_path.port; 5008 5009 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5010 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5011 5012 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5013 5014 qp_attr->max_dest_rd_atomic = 5015 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5016 qp_attr->min_rnr_timer = 5017 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5018 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5019 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5020 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5021 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5022 5023 out: 5024 kfree(outb); 5025 return err; 5026 } 5027 5028 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5029 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5030 struct ib_qp_init_attr *qp_init_attr) 5031 { 5032 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5033 u32 *out; 5034 u32 access_flags = 0; 5035 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5036 void *dctc; 5037 int err; 5038 int supported_mask = IB_QP_STATE | 5039 IB_QP_ACCESS_FLAGS | 5040 IB_QP_PORT | 5041 IB_QP_MIN_RNR_TIMER | 5042 IB_QP_AV | 5043 IB_QP_PATH_MTU | 5044 IB_QP_PKEY_INDEX; 5045 5046 if (qp_attr_mask & ~supported_mask) 5047 return -EINVAL; 5048 if (mqp->state != IB_QPS_RTR) 5049 return -EINVAL; 5050 5051 out = kzalloc(outlen, GFP_KERNEL); 5052 if (!out) 5053 return -ENOMEM; 5054 5055 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5056 if (err) 5057 goto out; 5058 5059 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5060 5061 if (qp_attr_mask & IB_QP_STATE) 5062 qp_attr->qp_state = IB_QPS_RTR; 5063 5064 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5065 if (MLX5_GET(dctc, dctc, rre)) 5066 access_flags |= IB_ACCESS_REMOTE_READ; 5067 if (MLX5_GET(dctc, dctc, rwe)) 5068 access_flags |= IB_ACCESS_REMOTE_WRITE; 5069 if (MLX5_GET(dctc, dctc, rae)) 5070 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5071 qp_attr->qp_access_flags = access_flags; 5072 } 5073 5074 if (qp_attr_mask & IB_QP_PORT) 5075 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5076 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5077 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5078 if (qp_attr_mask & IB_QP_AV) { 5079 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5080 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5081 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5082 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5083 } 5084 if (qp_attr_mask & IB_QP_PATH_MTU) 5085 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5086 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5087 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5088 out: 5089 kfree(out); 5090 return err; 5091 } 5092 5093 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5094 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5095 { 5096 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5097 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5098 int err = 0; 5099 u8 raw_packet_qp_state; 5100 5101 if (ibqp->rwq_ind_tbl) 5102 return -ENOSYS; 5103 5104 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5105 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5106 qp_init_attr); 5107 5108 /* Not all of output fields are applicable, make sure to zero them */ 5109 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5110 memset(qp_attr, 0, sizeof(*qp_attr)); 5111 5112 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5113 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5114 qp_attr_mask, qp_init_attr); 5115 5116 mutex_lock(&qp->mutex); 5117 5118 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5119 qp->flags & MLX5_IB_QP_UNDERLAY) { 5120 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5121 if (err) 5122 goto out; 5123 qp->state = raw_packet_qp_state; 5124 qp_attr->port_num = 1; 5125 } else { 5126 err = query_qp_attr(dev, qp, qp_attr); 5127 if (err) 5128 goto out; 5129 } 5130 5131 qp_attr->qp_state = qp->state; 5132 qp_attr->cur_qp_state = qp_attr->qp_state; 5133 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5134 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5135 5136 if (!ibqp->uobject) { 5137 qp_attr->cap.max_send_wr = qp->sq.max_post; 5138 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5139 qp_init_attr->qp_context = ibqp->qp_context; 5140 } else { 5141 qp_attr->cap.max_send_wr = 0; 5142 qp_attr->cap.max_send_sge = 0; 5143 } 5144 5145 qp_init_attr->qp_type = ibqp->qp_type; 5146 qp_init_attr->recv_cq = ibqp->recv_cq; 5147 qp_init_attr->send_cq = ibqp->send_cq; 5148 qp_init_attr->srq = ibqp->srq; 5149 qp_attr->cap.max_inline_data = qp->max_inline_data; 5150 5151 qp_init_attr->cap = qp_attr->cap; 5152 5153 qp_init_attr->create_flags = 0; 5154 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5155 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5156 5157 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5158 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5159 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5160 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5161 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5162 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5163 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5164 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5165 5166 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5167 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5168 5169 out: 5170 mutex_unlock(&qp->mutex); 5171 return err; 5172 } 5173 5174 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5175 struct ib_ucontext *context, 5176 struct ib_udata *udata) 5177 { 5178 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5179 struct mlx5_ib_xrcd *xrcd; 5180 int err; 5181 5182 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5183 return ERR_PTR(-ENOSYS); 5184 5185 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5186 if (!xrcd) 5187 return ERR_PTR(-ENOMEM); 5188 5189 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 5190 if (err) { 5191 kfree(xrcd); 5192 return ERR_PTR(-ENOMEM); 5193 } 5194 5195 return &xrcd->ibxrcd; 5196 } 5197 5198 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5199 { 5200 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5201 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5202 int err; 5203 5204 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 5205 if (err) 5206 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5207 5208 kfree(xrcd); 5209 return 0; 5210 } 5211 5212 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5213 { 5214 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5215 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5216 struct ib_event event; 5217 5218 if (rwq->ibwq.event_handler) { 5219 event.device = rwq->ibwq.device; 5220 event.element.wq = &rwq->ibwq; 5221 switch (type) { 5222 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5223 event.event = IB_EVENT_WQ_FATAL; 5224 break; 5225 default: 5226 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5227 return; 5228 } 5229 5230 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5231 } 5232 } 5233 5234 static int set_delay_drop(struct mlx5_ib_dev *dev) 5235 { 5236 int err = 0; 5237 5238 mutex_lock(&dev->delay_drop.lock); 5239 if (dev->delay_drop.activate) 5240 goto out; 5241 5242 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5243 if (err) 5244 goto out; 5245 5246 dev->delay_drop.activate = true; 5247 out: 5248 mutex_unlock(&dev->delay_drop.lock); 5249 5250 if (!err) 5251 atomic_inc(&dev->delay_drop.rqs_cnt); 5252 return err; 5253 } 5254 5255 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5256 struct ib_wq_init_attr *init_attr) 5257 { 5258 struct mlx5_ib_dev *dev; 5259 int has_net_offloads; 5260 __be64 *rq_pas0; 5261 void *in; 5262 void *rqc; 5263 void *wq; 5264 int inlen; 5265 int err; 5266 5267 dev = to_mdev(pd->device); 5268 5269 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5270 in = kvzalloc(inlen, GFP_KERNEL); 5271 if (!in) 5272 return -ENOMEM; 5273 5274 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5275 MLX5_SET(rqc, rqc, mem_rq_type, 5276 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5277 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5278 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5279 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5280 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5281 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5282 MLX5_SET(wq, wq, wq_type, 5283 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5284 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5285 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5286 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5287 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5288 err = -EOPNOTSUPP; 5289 goto out; 5290 } else { 5291 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5292 } 5293 } 5294 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5295 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5296 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5297 MLX5_SET(wq, wq, log_wqe_stride_size, 5298 rwq->single_stride_log_num_of_bytes - 5299 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5300 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5301 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5302 } 5303 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5304 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5305 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5306 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5307 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5308 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5309 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5310 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5311 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5312 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5313 err = -EOPNOTSUPP; 5314 goto out; 5315 } 5316 } else { 5317 MLX5_SET(rqc, rqc, vsd, 1); 5318 } 5319 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5320 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5321 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5322 err = -EOPNOTSUPP; 5323 goto out; 5324 } 5325 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5326 } 5327 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5328 if (!(dev->ib_dev.attrs.raw_packet_caps & 5329 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5330 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5331 err = -EOPNOTSUPP; 5332 goto out; 5333 } 5334 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5335 } 5336 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5337 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5338 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5339 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5340 err = set_delay_drop(dev); 5341 if (err) { 5342 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5343 err); 5344 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5345 } else { 5346 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5347 } 5348 } 5349 out: 5350 kvfree(in); 5351 return err; 5352 } 5353 5354 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5355 struct ib_wq_init_attr *wq_init_attr, 5356 struct mlx5_ib_create_wq *ucmd, 5357 struct mlx5_ib_rwq *rwq) 5358 { 5359 /* Sanity check RQ size before proceeding */ 5360 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5361 return -EINVAL; 5362 5363 if (!ucmd->rq_wqe_count) 5364 return -EINVAL; 5365 5366 rwq->wqe_count = ucmd->rq_wqe_count; 5367 rwq->wqe_shift = ucmd->rq_wqe_shift; 5368 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 5369 rwq->log_rq_stride = rwq->wqe_shift; 5370 rwq->log_rq_size = ilog2(rwq->wqe_count); 5371 return 0; 5372 } 5373 5374 static int prepare_user_rq(struct ib_pd *pd, 5375 struct ib_wq_init_attr *init_attr, 5376 struct ib_udata *udata, 5377 struct mlx5_ib_rwq *rwq) 5378 { 5379 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5380 struct mlx5_ib_create_wq ucmd = {}; 5381 int err; 5382 size_t required_cmd_sz; 5383 5384 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5385 + sizeof(ucmd.single_stride_log_num_of_bytes); 5386 if (udata->inlen < required_cmd_sz) { 5387 mlx5_ib_dbg(dev, "invalid inlen\n"); 5388 return -EINVAL; 5389 } 5390 5391 if (udata->inlen > sizeof(ucmd) && 5392 !ib_is_udata_cleared(udata, sizeof(ucmd), 5393 udata->inlen - sizeof(ucmd))) { 5394 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5395 return -EOPNOTSUPP; 5396 } 5397 5398 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5399 mlx5_ib_dbg(dev, "copy failed\n"); 5400 return -EFAULT; 5401 } 5402 5403 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5404 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5405 return -EOPNOTSUPP; 5406 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5407 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5408 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5409 return -EOPNOTSUPP; 5410 } 5411 if ((ucmd.single_stride_log_num_of_bytes < 5412 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5413 (ucmd.single_stride_log_num_of_bytes > 5414 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5415 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5416 ucmd.single_stride_log_num_of_bytes, 5417 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5418 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5419 return -EINVAL; 5420 } 5421 if ((ucmd.single_wqe_log_num_of_strides > 5422 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5423 (ucmd.single_wqe_log_num_of_strides < 5424 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5425 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5426 ucmd.single_wqe_log_num_of_strides, 5427 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5428 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5429 return -EINVAL; 5430 } 5431 rwq->single_stride_log_num_of_bytes = 5432 ucmd.single_stride_log_num_of_bytes; 5433 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5434 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5435 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5436 } 5437 5438 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5439 if (err) { 5440 mlx5_ib_dbg(dev, "err %d\n", err); 5441 return err; 5442 } 5443 5444 err = create_user_rq(dev, pd, rwq, &ucmd); 5445 if (err) { 5446 mlx5_ib_dbg(dev, "err %d\n", err); 5447 if (err) 5448 return err; 5449 } 5450 5451 rwq->user_index = ucmd.user_index; 5452 return 0; 5453 } 5454 5455 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5456 struct ib_wq_init_attr *init_attr, 5457 struct ib_udata *udata) 5458 { 5459 struct mlx5_ib_dev *dev; 5460 struct mlx5_ib_rwq *rwq; 5461 struct mlx5_ib_create_wq_resp resp = {}; 5462 size_t min_resp_len; 5463 int err; 5464 5465 if (!udata) 5466 return ERR_PTR(-ENOSYS); 5467 5468 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5469 if (udata->outlen && udata->outlen < min_resp_len) 5470 return ERR_PTR(-EINVAL); 5471 5472 dev = to_mdev(pd->device); 5473 switch (init_attr->wq_type) { 5474 case IB_WQT_RQ: 5475 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5476 if (!rwq) 5477 return ERR_PTR(-ENOMEM); 5478 err = prepare_user_rq(pd, init_attr, udata, rwq); 5479 if (err) 5480 goto err; 5481 err = create_rq(rwq, pd, init_attr); 5482 if (err) 5483 goto err_user_rq; 5484 break; 5485 default: 5486 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5487 init_attr->wq_type); 5488 return ERR_PTR(-EINVAL); 5489 } 5490 5491 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5492 rwq->ibwq.state = IB_WQS_RESET; 5493 if (udata->outlen) { 5494 resp.response_length = offsetof(typeof(resp), response_length) + 5495 sizeof(resp.response_length); 5496 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5497 if (err) 5498 goto err_copy; 5499 } 5500 5501 rwq->core_qp.event = mlx5_ib_wq_event; 5502 rwq->ibwq.event_handler = init_attr->event_handler; 5503 return &rwq->ibwq; 5504 5505 err_copy: 5506 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5507 err_user_rq: 5508 destroy_user_rq(dev, pd, rwq); 5509 err: 5510 kfree(rwq); 5511 return ERR_PTR(err); 5512 } 5513 5514 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5515 { 5516 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5517 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5518 5519 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5520 destroy_user_rq(dev, wq->pd, rwq); 5521 kfree(rwq); 5522 5523 return 0; 5524 } 5525 5526 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5527 struct ib_rwq_ind_table_init_attr *init_attr, 5528 struct ib_udata *udata) 5529 { 5530 struct mlx5_ib_dev *dev = to_mdev(device); 5531 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5532 int sz = 1 << init_attr->log_ind_tbl_size; 5533 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5534 size_t min_resp_len; 5535 int inlen; 5536 int err; 5537 int i; 5538 u32 *in; 5539 void *rqtc; 5540 5541 if (udata->inlen > 0 && 5542 !ib_is_udata_cleared(udata, 0, 5543 udata->inlen)) 5544 return ERR_PTR(-EOPNOTSUPP); 5545 5546 if (init_attr->log_ind_tbl_size > 5547 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5548 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5549 init_attr->log_ind_tbl_size, 5550 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5551 return ERR_PTR(-EINVAL); 5552 } 5553 5554 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5555 if (udata->outlen && udata->outlen < min_resp_len) 5556 return ERR_PTR(-EINVAL); 5557 5558 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5559 if (!rwq_ind_tbl) 5560 return ERR_PTR(-ENOMEM); 5561 5562 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5563 in = kvzalloc(inlen, GFP_KERNEL); 5564 if (!in) { 5565 err = -ENOMEM; 5566 goto err; 5567 } 5568 5569 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5570 5571 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5572 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5573 5574 for (i = 0; i < sz; i++) 5575 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5576 5577 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5578 kvfree(in); 5579 5580 if (err) 5581 goto err; 5582 5583 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5584 if (udata->outlen) { 5585 resp.response_length = offsetof(typeof(resp), response_length) + 5586 sizeof(resp.response_length); 5587 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5588 if (err) 5589 goto err_copy; 5590 } 5591 5592 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5593 5594 err_copy: 5595 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5596 err: 5597 kfree(rwq_ind_tbl); 5598 return ERR_PTR(err); 5599 } 5600 5601 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5602 { 5603 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5604 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5605 5606 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5607 5608 kfree(rwq_ind_tbl); 5609 return 0; 5610 } 5611 5612 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5613 u32 wq_attr_mask, struct ib_udata *udata) 5614 { 5615 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5616 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5617 struct mlx5_ib_modify_wq ucmd = {}; 5618 size_t required_cmd_sz; 5619 int curr_wq_state; 5620 int wq_state; 5621 int inlen; 5622 int err; 5623 void *rqc; 5624 void *in; 5625 5626 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5627 if (udata->inlen < required_cmd_sz) 5628 return -EINVAL; 5629 5630 if (udata->inlen > sizeof(ucmd) && 5631 !ib_is_udata_cleared(udata, sizeof(ucmd), 5632 udata->inlen - sizeof(ucmd))) 5633 return -EOPNOTSUPP; 5634 5635 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5636 return -EFAULT; 5637 5638 if (ucmd.comp_mask || ucmd.reserved) 5639 return -EOPNOTSUPP; 5640 5641 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5642 in = kvzalloc(inlen, GFP_KERNEL); 5643 if (!in) 5644 return -ENOMEM; 5645 5646 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5647 5648 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5649 wq_attr->curr_wq_state : wq->state; 5650 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5651 wq_attr->wq_state : curr_wq_state; 5652 if (curr_wq_state == IB_WQS_ERR) 5653 curr_wq_state = MLX5_RQC_STATE_ERR; 5654 if (wq_state == IB_WQS_ERR) 5655 wq_state = MLX5_RQC_STATE_ERR; 5656 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5657 MLX5_SET(rqc, rqc, state, wq_state); 5658 5659 if (wq_attr_mask & IB_WQ_FLAGS) { 5660 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5661 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5662 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5663 mlx5_ib_dbg(dev, "VLAN offloads are not " 5664 "supported\n"); 5665 err = -EOPNOTSUPP; 5666 goto out; 5667 } 5668 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5669 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5670 MLX5_SET(rqc, rqc, vsd, 5671 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5672 } 5673 5674 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5675 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5676 err = -EOPNOTSUPP; 5677 goto out; 5678 } 5679 } 5680 5681 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5682 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5683 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5684 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5685 MLX5_SET(rqc, rqc, counter_set_id, 5686 dev->port->cnts.set_id); 5687 } else 5688 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5689 dev->ib_dev.name); 5690 } 5691 5692 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5693 if (!err) 5694 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5695 5696 out: 5697 kvfree(in); 5698 return err; 5699 } 5700