1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "cmd.h" 42 43 /* not supported currently */ 44 static int wq_signature; 45 46 enum { 47 MLX5_IB_ACK_REQ_FREQ = 8, 48 }; 49 50 enum { 51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 53 MLX5_IB_LINK_TYPE_IB = 0, 54 MLX5_IB_LINK_TYPE_ETH = 1 55 }; 56 57 enum { 58 MLX5_IB_SQ_STRIDE = 6, 59 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 60 }; 61 62 static const u32 mlx5_ib_opcode[] = { 63 [IB_WR_SEND] = MLX5_OPCODE_SEND, 64 [IB_WR_LSO] = MLX5_OPCODE_LSO, 65 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 66 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 67 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 68 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 69 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 70 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 71 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 72 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 73 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 74 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 75 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 76 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 77 }; 78 79 struct mlx5_wqe_eth_pad { 80 u8 rsvd0[16]; 81 }; 82 83 enum raw_qp_set_mask_map { 84 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 85 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 86 }; 87 88 struct mlx5_modify_raw_qp_param { 89 u16 operation; 90 91 u32 set_mask; /* raw_qp_set_mask_map */ 92 93 struct mlx5_rate_limit rl; 94 95 u8 rq_q_ctr_id; 96 u16 port; 97 }; 98 99 static void get_cqs(enum ib_qp_type qp_type, 100 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 101 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 102 103 static int is_qp0(enum ib_qp_type qp_type) 104 { 105 return qp_type == IB_QPT_SMI; 106 } 107 108 static int is_sqp(enum ib_qp_type qp_type) 109 { 110 return is_qp0(qp_type) || is_qp1(qp_type); 111 } 112 113 /** 114 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 115 * to kernel buffer 116 * 117 * @umem: User space memory where the WQ is 118 * @buffer: buffer to copy to 119 * @buflen: buffer length 120 * @wqe_index: index of WQE to copy from 121 * @wq_offset: offset to start of WQ 122 * @wq_wqe_cnt: number of WQEs in WQ 123 * @wq_wqe_shift: log2 of WQE size 124 * @bcnt: number of bytes to copy 125 * @bytes_copied: number of bytes to copy (return value) 126 * 127 * Copies from start of WQE bcnt or less bytes. 128 * Does not gurantee to copy the entire WQE. 129 * 130 * Return: zero on success, or an error code. 131 */ 132 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, 133 void *buffer, 134 u32 buflen, 135 int wqe_index, 136 int wq_offset, 137 int wq_wqe_cnt, 138 int wq_wqe_shift, 139 int bcnt, 140 size_t *bytes_copied) 141 { 142 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 143 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 144 size_t copy_length; 145 int ret; 146 147 /* don't copy more than requested, more than buffer length or 148 * beyond WQ end 149 */ 150 copy_length = min_t(u32, buflen, wq_end - offset); 151 copy_length = min_t(u32, copy_length, bcnt); 152 153 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 154 if (ret) 155 return ret; 156 157 if (!ret && bytes_copied) 158 *bytes_copied = copy_length; 159 160 return 0; 161 } 162 163 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, 164 int wqe_index, 165 void *buffer, 166 int buflen, 167 size_t *bc) 168 { 169 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 170 struct ib_umem *umem = base->ubuffer.umem; 171 struct mlx5_ib_wq *wq = &qp->sq; 172 struct mlx5_wqe_ctrl_seg *ctrl; 173 size_t bytes_copied; 174 size_t bytes_copied2; 175 size_t wqe_length; 176 int ret; 177 int ds; 178 179 if (buflen < sizeof(*ctrl)) 180 return -EINVAL; 181 182 /* at first read as much as possible */ 183 ret = mlx5_ib_read_user_wqe_common(umem, 184 buffer, 185 buflen, 186 wqe_index, 187 wq->offset, 188 wq->wqe_cnt, 189 wq->wqe_shift, 190 buflen, 191 &bytes_copied); 192 if (ret) 193 return ret; 194 195 /* we need at least control segment size to proceed */ 196 if (bytes_copied < sizeof(*ctrl)) 197 return -EINVAL; 198 199 ctrl = buffer; 200 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 201 wqe_length = ds * MLX5_WQE_DS_UNITS; 202 203 /* if we copied enough then we are done */ 204 if (bytes_copied >= wqe_length) { 205 *bc = bytes_copied; 206 return 0; 207 } 208 209 /* otherwise this a wrapped around wqe 210 * so read the remaining bytes starting 211 * from wqe_index 0 212 */ 213 ret = mlx5_ib_read_user_wqe_common(umem, 214 buffer + bytes_copied, 215 buflen - bytes_copied, 216 0, 217 wq->offset, 218 wq->wqe_cnt, 219 wq->wqe_shift, 220 wqe_length - bytes_copied, 221 &bytes_copied2); 222 223 if (ret) 224 return ret; 225 *bc = bytes_copied + bytes_copied2; 226 return 0; 227 } 228 229 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, 230 int wqe_index, 231 void *buffer, 232 int buflen, 233 size_t *bc) 234 { 235 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 236 struct ib_umem *umem = base->ubuffer.umem; 237 struct mlx5_ib_wq *wq = &qp->rq; 238 size_t bytes_copied; 239 int ret; 240 241 ret = mlx5_ib_read_user_wqe_common(umem, 242 buffer, 243 buflen, 244 wqe_index, 245 wq->offset, 246 wq->wqe_cnt, 247 wq->wqe_shift, 248 buflen, 249 &bytes_copied); 250 251 if (ret) 252 return ret; 253 *bc = bytes_copied; 254 return 0; 255 } 256 257 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, 258 int wqe_index, 259 void *buffer, 260 int buflen, 261 size_t *bc) 262 { 263 struct ib_umem *umem = srq->umem; 264 size_t bytes_copied; 265 int ret; 266 267 ret = mlx5_ib_read_user_wqe_common(umem, 268 buffer, 269 buflen, 270 wqe_index, 271 0, 272 srq->msrq.max, 273 srq->msrq.wqe_shift, 274 buflen, 275 &bytes_copied); 276 277 if (ret) 278 return ret; 279 *bc = bytes_copied; 280 return 0; 281 } 282 283 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 284 { 285 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 286 struct ib_event event; 287 288 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 289 /* This event is only valid for trans_qps */ 290 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 291 } 292 293 if (ibqp->event_handler) { 294 event.device = ibqp->device; 295 event.element.qp = ibqp; 296 switch (type) { 297 case MLX5_EVENT_TYPE_PATH_MIG: 298 event.event = IB_EVENT_PATH_MIG; 299 break; 300 case MLX5_EVENT_TYPE_COMM_EST: 301 event.event = IB_EVENT_COMM_EST; 302 break; 303 case MLX5_EVENT_TYPE_SQ_DRAINED: 304 event.event = IB_EVENT_SQ_DRAINED; 305 break; 306 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 307 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 308 break; 309 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 310 event.event = IB_EVENT_QP_FATAL; 311 break; 312 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 313 event.event = IB_EVENT_PATH_MIG_ERR; 314 break; 315 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 316 event.event = IB_EVENT_QP_REQ_ERR; 317 break; 318 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 319 event.event = IB_EVENT_QP_ACCESS_ERR; 320 break; 321 default: 322 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 323 return; 324 } 325 326 ibqp->event_handler(&event, ibqp->qp_context); 327 } 328 } 329 330 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 331 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 332 { 333 int wqe_size; 334 int wq_size; 335 336 /* Sanity check RQ size before proceeding */ 337 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 338 return -EINVAL; 339 340 if (!has_rq) { 341 qp->rq.max_gs = 0; 342 qp->rq.wqe_cnt = 0; 343 qp->rq.wqe_shift = 0; 344 cap->max_recv_wr = 0; 345 cap->max_recv_sge = 0; 346 } else { 347 if (ucmd) { 348 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 349 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 350 return -EINVAL; 351 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 352 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 353 return -EINVAL; 354 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 355 qp->rq.max_post = qp->rq.wqe_cnt; 356 } else { 357 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 358 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 359 wqe_size = roundup_pow_of_two(wqe_size); 360 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 361 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 362 qp->rq.wqe_cnt = wq_size / wqe_size; 363 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 364 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 365 wqe_size, 366 MLX5_CAP_GEN(dev->mdev, 367 max_wqe_sz_rq)); 368 return -EINVAL; 369 } 370 qp->rq.wqe_shift = ilog2(wqe_size); 371 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 372 qp->rq.max_post = qp->rq.wqe_cnt; 373 } 374 } 375 376 return 0; 377 } 378 379 static int sq_overhead(struct ib_qp_init_attr *attr) 380 { 381 int size = 0; 382 383 switch (attr->qp_type) { 384 case IB_QPT_XRC_INI: 385 size += sizeof(struct mlx5_wqe_xrc_seg); 386 /* fall through */ 387 case IB_QPT_RC: 388 size += sizeof(struct mlx5_wqe_ctrl_seg) + 389 max(sizeof(struct mlx5_wqe_atomic_seg) + 390 sizeof(struct mlx5_wqe_raddr_seg), 391 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 392 sizeof(struct mlx5_mkey_seg) + 393 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 394 MLX5_IB_UMR_OCTOWORD); 395 break; 396 397 case IB_QPT_XRC_TGT: 398 return 0; 399 400 case IB_QPT_UC: 401 size += sizeof(struct mlx5_wqe_ctrl_seg) + 402 max(sizeof(struct mlx5_wqe_raddr_seg), 403 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 404 sizeof(struct mlx5_mkey_seg)); 405 break; 406 407 case IB_QPT_UD: 408 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 409 size += sizeof(struct mlx5_wqe_eth_pad) + 410 sizeof(struct mlx5_wqe_eth_seg); 411 /* fall through */ 412 case IB_QPT_SMI: 413 case MLX5_IB_QPT_HW_GSI: 414 size += sizeof(struct mlx5_wqe_ctrl_seg) + 415 sizeof(struct mlx5_wqe_datagram_seg); 416 break; 417 418 case MLX5_IB_QPT_REG_UMR: 419 size += sizeof(struct mlx5_wqe_ctrl_seg) + 420 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 421 sizeof(struct mlx5_mkey_seg); 422 break; 423 424 default: 425 return -EINVAL; 426 } 427 428 return size; 429 } 430 431 static int calc_send_wqe(struct ib_qp_init_attr *attr) 432 { 433 int inl_size = 0; 434 int size; 435 436 size = sq_overhead(attr); 437 if (size < 0) 438 return size; 439 440 if (attr->cap.max_inline_data) { 441 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 442 attr->cap.max_inline_data; 443 } 444 445 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 446 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 447 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 448 return MLX5_SIG_WQE_SIZE; 449 else 450 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 451 } 452 453 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 454 { 455 int max_sge; 456 457 if (attr->qp_type == IB_QPT_RC) 458 max_sge = (min_t(int, wqe_size, 512) - 459 sizeof(struct mlx5_wqe_ctrl_seg) - 460 sizeof(struct mlx5_wqe_raddr_seg)) / 461 sizeof(struct mlx5_wqe_data_seg); 462 else if (attr->qp_type == IB_QPT_XRC_INI) 463 max_sge = (min_t(int, wqe_size, 512) - 464 sizeof(struct mlx5_wqe_ctrl_seg) - 465 sizeof(struct mlx5_wqe_xrc_seg) - 466 sizeof(struct mlx5_wqe_raddr_seg)) / 467 sizeof(struct mlx5_wqe_data_seg); 468 else 469 max_sge = (wqe_size - sq_overhead(attr)) / 470 sizeof(struct mlx5_wqe_data_seg); 471 472 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 473 sizeof(struct mlx5_wqe_data_seg)); 474 } 475 476 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 477 struct mlx5_ib_qp *qp) 478 { 479 int wqe_size; 480 int wq_size; 481 482 if (!attr->cap.max_send_wr) 483 return 0; 484 485 wqe_size = calc_send_wqe(attr); 486 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 487 if (wqe_size < 0) 488 return wqe_size; 489 490 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 491 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 492 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 493 return -EINVAL; 494 } 495 496 qp->max_inline_data = wqe_size - sq_overhead(attr) - 497 sizeof(struct mlx5_wqe_inline_seg); 498 attr->cap.max_inline_data = qp->max_inline_data; 499 500 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 501 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 502 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 503 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 504 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 505 qp->sq.wqe_cnt, 506 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 507 return -ENOMEM; 508 } 509 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 510 qp->sq.max_gs = get_send_sge(attr, wqe_size); 511 if (qp->sq.max_gs < attr->cap.max_send_sge) 512 return -ENOMEM; 513 514 attr->cap.max_send_sge = qp->sq.max_gs; 515 qp->sq.max_post = wq_size / wqe_size; 516 attr->cap.max_send_wr = qp->sq.max_post; 517 518 return wq_size; 519 } 520 521 static int set_user_buf_size(struct mlx5_ib_dev *dev, 522 struct mlx5_ib_qp *qp, 523 struct mlx5_ib_create_qp *ucmd, 524 struct mlx5_ib_qp_base *base, 525 struct ib_qp_init_attr *attr) 526 { 527 int desc_sz = 1 << qp->sq.wqe_shift; 528 529 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 530 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 531 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 532 return -EINVAL; 533 } 534 535 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 536 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 537 ucmd->sq_wqe_count); 538 return -EINVAL; 539 } 540 541 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 542 543 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 544 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 545 qp->sq.wqe_cnt, 546 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 547 return -EINVAL; 548 } 549 550 if (attr->qp_type == IB_QPT_RAW_PACKET || 551 qp->flags & MLX5_IB_QP_UNDERLAY) { 552 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 553 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 554 } else { 555 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 556 (qp->sq.wqe_cnt << 6); 557 } 558 559 return 0; 560 } 561 562 static int qp_has_rq(struct ib_qp_init_attr *attr) 563 { 564 if (attr->qp_type == IB_QPT_XRC_INI || 565 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 566 attr->qp_type == MLX5_IB_QPT_REG_UMR || 567 !attr->cap.max_recv_wr) 568 return 0; 569 570 return 1; 571 } 572 573 enum { 574 /* this is the first blue flame register in the array of bfregs assigned 575 * to a processes. Since we do not use it for blue flame but rather 576 * regular 64 bit doorbells, we do not need a lock for maintaiing 577 * "odd/even" order 578 */ 579 NUM_NON_BLUE_FLAME_BFREGS = 1, 580 }; 581 582 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 583 { 584 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 585 } 586 587 static int num_med_bfreg(struct mlx5_ib_dev *dev, 588 struct mlx5_bfreg_info *bfregi) 589 { 590 int n; 591 592 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 593 NUM_NON_BLUE_FLAME_BFREGS; 594 595 return n >= 0 ? n : 0; 596 } 597 598 static int first_med_bfreg(struct mlx5_ib_dev *dev, 599 struct mlx5_bfreg_info *bfregi) 600 { 601 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 602 } 603 604 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 605 struct mlx5_bfreg_info *bfregi) 606 { 607 int med; 608 609 med = num_med_bfreg(dev, bfregi); 610 return ++med; 611 } 612 613 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 614 struct mlx5_bfreg_info *bfregi) 615 { 616 int i; 617 618 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 619 if (!bfregi->count[i]) { 620 bfregi->count[i]++; 621 return i; 622 } 623 } 624 625 return -ENOMEM; 626 } 627 628 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 629 struct mlx5_bfreg_info *bfregi) 630 { 631 int minidx = first_med_bfreg(dev, bfregi); 632 int i; 633 634 if (minidx < 0) 635 return minidx; 636 637 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 638 if (bfregi->count[i] < bfregi->count[minidx]) 639 minidx = i; 640 if (!bfregi->count[minidx]) 641 break; 642 } 643 644 bfregi->count[minidx]++; 645 return minidx; 646 } 647 648 static int alloc_bfreg(struct mlx5_ib_dev *dev, 649 struct mlx5_bfreg_info *bfregi) 650 { 651 int bfregn = -ENOMEM; 652 653 mutex_lock(&bfregi->lock); 654 if (bfregi->ver >= 2) { 655 bfregn = alloc_high_class_bfreg(dev, bfregi); 656 if (bfregn < 0) 657 bfregn = alloc_med_class_bfreg(dev, bfregi); 658 } 659 660 if (bfregn < 0) { 661 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 662 bfregn = 0; 663 bfregi->count[bfregn]++; 664 } 665 mutex_unlock(&bfregi->lock); 666 667 return bfregn; 668 } 669 670 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 671 { 672 mutex_lock(&bfregi->lock); 673 bfregi->count[bfregn]--; 674 mutex_unlock(&bfregi->lock); 675 } 676 677 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 678 { 679 switch (state) { 680 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 681 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 682 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 683 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 684 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 685 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 686 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 687 default: return -1; 688 } 689 } 690 691 static int to_mlx5_st(enum ib_qp_type type) 692 { 693 switch (type) { 694 case IB_QPT_RC: return MLX5_QP_ST_RC; 695 case IB_QPT_UC: return MLX5_QP_ST_UC; 696 case IB_QPT_UD: return MLX5_QP_ST_UD; 697 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 698 case IB_QPT_XRC_INI: 699 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 700 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 701 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 702 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 703 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 704 case IB_QPT_RAW_PACKET: 705 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 706 case IB_QPT_MAX: 707 default: return -EINVAL; 708 } 709 } 710 711 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 712 struct mlx5_ib_cq *recv_cq); 713 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 714 struct mlx5_ib_cq *recv_cq); 715 716 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 717 struct mlx5_bfreg_info *bfregi, u32 bfregn, 718 bool dyn_bfreg) 719 { 720 unsigned int bfregs_per_sys_page; 721 u32 index_of_sys_page; 722 u32 offset; 723 724 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 725 MLX5_NON_FP_BFREGS_PER_UAR; 726 index_of_sys_page = bfregn / bfregs_per_sys_page; 727 728 if (dyn_bfreg) { 729 index_of_sys_page += bfregi->num_static_sys_pages; 730 731 if (index_of_sys_page >= bfregi->num_sys_pages) 732 return -EINVAL; 733 734 if (bfregn > bfregi->num_dyn_bfregs || 735 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 736 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 737 return -EINVAL; 738 } 739 } 740 741 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 742 return bfregi->sys_pages[index_of_sys_page] + offset; 743 } 744 745 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, 746 unsigned long addr, size_t size, 747 struct ib_umem **umem, int *npages, int *page_shift, 748 int *ncont, u32 *offset) 749 { 750 int err; 751 752 *umem = ib_umem_get(udata, addr, size, 0); 753 if (IS_ERR(*umem)) { 754 mlx5_ib_dbg(dev, "umem_get failed\n"); 755 return PTR_ERR(*umem); 756 } 757 758 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 759 760 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 761 if (err) { 762 mlx5_ib_warn(dev, "bad offset\n"); 763 goto err_umem; 764 } 765 766 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 767 addr, size, *npages, *page_shift, *ncont, *offset); 768 769 return 0; 770 771 err_umem: 772 ib_umem_release(*umem); 773 *umem = NULL; 774 775 return err; 776 } 777 778 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 779 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 780 { 781 struct mlx5_ib_ucontext *context = 782 rdma_udata_to_drv_context( 783 udata, 784 struct mlx5_ib_ucontext, 785 ibucontext); 786 787 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 788 atomic_dec(&dev->delay_drop.rqs_cnt); 789 790 mlx5_ib_db_unmap_user(context, &rwq->db); 791 ib_umem_release(rwq->umem); 792 } 793 794 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 795 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 796 struct mlx5_ib_create_wq *ucmd) 797 { 798 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 799 udata, struct mlx5_ib_ucontext, ibucontext); 800 int page_shift = 0; 801 int npages; 802 u32 offset = 0; 803 int ncont = 0; 804 int err; 805 806 if (!ucmd->buf_addr) 807 return -EINVAL; 808 809 rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0); 810 if (IS_ERR(rwq->umem)) { 811 mlx5_ib_dbg(dev, "umem_get failed\n"); 812 err = PTR_ERR(rwq->umem); 813 return err; 814 } 815 816 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 817 &ncont, NULL); 818 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 819 &rwq->rq_page_offset); 820 if (err) { 821 mlx5_ib_warn(dev, "bad offset\n"); 822 goto err_umem; 823 } 824 825 rwq->rq_num_pas = ncont; 826 rwq->page_shift = page_shift; 827 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 828 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 829 830 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 831 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 832 npages, page_shift, ncont, offset); 833 834 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 835 if (err) { 836 mlx5_ib_dbg(dev, "map failed\n"); 837 goto err_umem; 838 } 839 840 rwq->create_type = MLX5_WQ_USER; 841 return 0; 842 843 err_umem: 844 ib_umem_release(rwq->umem); 845 return err; 846 } 847 848 static int adjust_bfregn(struct mlx5_ib_dev *dev, 849 struct mlx5_bfreg_info *bfregi, int bfregn) 850 { 851 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 852 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 853 } 854 855 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 856 struct mlx5_ib_qp *qp, struct ib_udata *udata, 857 struct ib_qp_init_attr *attr, 858 u32 **in, 859 struct mlx5_ib_create_qp_resp *resp, int *inlen, 860 struct mlx5_ib_qp_base *base) 861 { 862 struct mlx5_ib_ucontext *context; 863 struct mlx5_ib_create_qp ucmd; 864 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 865 int page_shift = 0; 866 int uar_index = 0; 867 int npages; 868 u32 offset = 0; 869 int bfregn; 870 int ncont = 0; 871 __be64 *pas; 872 void *qpc; 873 int err; 874 u16 uid; 875 876 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 877 if (err) { 878 mlx5_ib_dbg(dev, "copy failed\n"); 879 return err; 880 } 881 882 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 883 ibucontext); 884 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 885 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 886 ucmd.bfreg_index, true); 887 if (uar_index < 0) 888 return uar_index; 889 890 bfregn = MLX5_IB_INVALID_BFREG; 891 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 892 /* 893 * TBD: should come from the verbs when we have the API 894 */ 895 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 896 bfregn = MLX5_CROSS_CHANNEL_BFREG; 897 } 898 else { 899 bfregn = alloc_bfreg(dev, &context->bfregi); 900 if (bfregn < 0) 901 return bfregn; 902 } 903 904 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 905 if (bfregn != MLX5_IB_INVALID_BFREG) 906 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 907 false); 908 909 qp->rq.offset = 0; 910 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 911 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 912 913 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 914 if (err) 915 goto err_bfreg; 916 917 if (ucmd.buf_addr && ubuffer->buf_size) { 918 ubuffer->buf_addr = ucmd.buf_addr; 919 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, 920 ubuffer->buf_size, &ubuffer->umem, 921 &npages, &page_shift, &ncont, &offset); 922 if (err) 923 goto err_bfreg; 924 } else { 925 ubuffer->umem = NULL; 926 } 927 928 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 929 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 930 *in = kvzalloc(*inlen, GFP_KERNEL); 931 if (!*in) { 932 err = -ENOMEM; 933 goto err_umem; 934 } 935 936 uid = (attr->qp_type != IB_QPT_XRC_TGT && 937 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 938 MLX5_SET(create_qp_in, *in, uid, uid); 939 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 940 if (ubuffer->umem) 941 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 942 943 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 944 945 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 946 MLX5_SET(qpc, qpc, page_offset, offset); 947 948 MLX5_SET(qpc, qpc, uar_page, uar_index); 949 if (bfregn != MLX5_IB_INVALID_BFREG) 950 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 951 else 952 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 953 qp->bfregn = bfregn; 954 955 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db); 956 if (err) { 957 mlx5_ib_dbg(dev, "map failed\n"); 958 goto err_free; 959 } 960 961 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 962 if (err) { 963 mlx5_ib_dbg(dev, "copy failed\n"); 964 goto err_unmap; 965 } 966 qp->create_type = MLX5_QP_USER; 967 968 return 0; 969 970 err_unmap: 971 mlx5_ib_db_unmap_user(context, &qp->db); 972 973 err_free: 974 kvfree(*in); 975 976 err_umem: 977 ib_umem_release(ubuffer->umem); 978 979 err_bfreg: 980 if (bfregn != MLX5_IB_INVALID_BFREG) 981 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 982 return err; 983 } 984 985 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 986 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base, 987 struct ib_udata *udata) 988 { 989 struct mlx5_ib_ucontext *context = 990 rdma_udata_to_drv_context( 991 udata, 992 struct mlx5_ib_ucontext, 993 ibucontext); 994 995 mlx5_ib_db_unmap_user(context, &qp->db); 996 ib_umem_release(base->ubuffer.umem); 997 998 /* 999 * Free only the BFREGs which are handled by the kernel. 1000 * BFREGs of UARs allocated dynamically are handled by user. 1001 */ 1002 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1003 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1004 } 1005 1006 /* get_sq_edge - Get the next nearby edge. 1007 * 1008 * An 'edge' is defined as the first following address after the end 1009 * of the fragment or the SQ. Accordingly, during the WQE construction 1010 * which repetitively increases the pointer to write the next data, it 1011 * simply should check if it gets to an edge. 1012 * 1013 * @sq - SQ buffer. 1014 * @idx - Stride index in the SQ buffer. 1015 * 1016 * Return: 1017 * The new edge. 1018 */ 1019 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) 1020 { 1021 void *fragment_end; 1022 1023 fragment_end = mlx5_frag_buf_get_wqe 1024 (&sq->fbc, 1025 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); 1026 1027 return fragment_end + MLX5_SEND_WQE_BB; 1028 } 1029 1030 static int create_kernel_qp(struct mlx5_ib_dev *dev, 1031 struct ib_qp_init_attr *init_attr, 1032 struct mlx5_ib_qp *qp, 1033 u32 **in, int *inlen, 1034 struct mlx5_ib_qp_base *base) 1035 { 1036 int uar_index; 1037 void *qpc; 1038 int err; 1039 1040 if (init_attr->create_flags & ~(IB_QP_CREATE_INTEGRITY_EN | 1041 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 1042 IB_QP_CREATE_IPOIB_UD_LSO | 1043 IB_QP_CREATE_NETIF_QP | 1044 MLX5_IB_QP_CREATE_SQPN_QP1 | 1045 MLX5_IB_QP_CREATE_WC_TEST)) 1046 return -EINVAL; 1047 1048 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1049 qp->bf.bfreg = &dev->fp_bfreg; 1050 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) 1051 qp->bf.bfreg = &dev->wc_bfreg; 1052 else 1053 qp->bf.bfreg = &dev->bfreg; 1054 1055 /* We need to divide by two since each register is comprised of 1056 * two buffers of identical size, namely odd and even 1057 */ 1058 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1059 uar_index = qp->bf.bfreg->index; 1060 1061 err = calc_sq_size(dev, init_attr, qp); 1062 if (err < 0) { 1063 mlx5_ib_dbg(dev, "err %d\n", err); 1064 return err; 1065 } 1066 1067 qp->rq.offset = 0; 1068 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1069 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1070 1071 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1072 &qp->buf, dev->mdev->priv.numa_node); 1073 if (err) { 1074 mlx5_ib_dbg(dev, "err %d\n", err); 1075 return err; 1076 } 1077 1078 if (qp->rq.wqe_cnt) 1079 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1080 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1081 1082 if (qp->sq.wqe_cnt) { 1083 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1084 MLX5_SEND_WQE_BB; 1085 mlx5_init_fbc_offset(qp->buf.frags + 1086 (qp->sq.offset / PAGE_SIZE), 1087 ilog2(MLX5_SEND_WQE_BB), 1088 ilog2(qp->sq.wqe_cnt), 1089 sq_strides_offset, &qp->sq.fbc); 1090 1091 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1092 } 1093 1094 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1095 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1096 *in = kvzalloc(*inlen, GFP_KERNEL); 1097 if (!*in) { 1098 err = -ENOMEM; 1099 goto err_buf; 1100 } 1101 1102 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1103 MLX5_SET(qpc, qpc, uar_page, uar_index); 1104 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1105 1106 /* Set "fast registration enabled" for all kernel QPs */ 1107 MLX5_SET(qpc, qpc, fre, 1); 1108 MLX5_SET(qpc, qpc, rlky, 1); 1109 1110 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { 1111 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1112 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1113 } 1114 1115 mlx5_fill_page_frag_array(&qp->buf, 1116 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1117 *in, pas)); 1118 1119 err = mlx5_db_alloc(dev->mdev, &qp->db); 1120 if (err) { 1121 mlx5_ib_dbg(dev, "err %d\n", err); 1122 goto err_free; 1123 } 1124 1125 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1126 sizeof(*qp->sq.wrid), GFP_KERNEL); 1127 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1128 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1129 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1130 sizeof(*qp->rq.wrid), GFP_KERNEL); 1131 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1132 sizeof(*qp->sq.w_list), GFP_KERNEL); 1133 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1134 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1135 1136 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1137 !qp->sq.w_list || !qp->sq.wqe_head) { 1138 err = -ENOMEM; 1139 goto err_wrid; 1140 } 1141 qp->create_type = MLX5_QP_KERNEL; 1142 1143 return 0; 1144 1145 err_wrid: 1146 kvfree(qp->sq.wqe_head); 1147 kvfree(qp->sq.w_list); 1148 kvfree(qp->sq.wrid); 1149 kvfree(qp->sq.wr_data); 1150 kvfree(qp->rq.wrid); 1151 mlx5_db_free(dev->mdev, &qp->db); 1152 1153 err_free: 1154 kvfree(*in); 1155 1156 err_buf: 1157 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1158 return err; 1159 } 1160 1161 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1162 { 1163 kvfree(qp->sq.wqe_head); 1164 kvfree(qp->sq.w_list); 1165 kvfree(qp->sq.wrid); 1166 kvfree(qp->sq.wr_data); 1167 kvfree(qp->rq.wrid); 1168 mlx5_db_free(dev->mdev, &qp->db); 1169 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1170 } 1171 1172 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1173 { 1174 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1175 (attr->qp_type == MLX5_IB_QPT_DCI) || 1176 (attr->qp_type == IB_QPT_XRC_INI)) 1177 return MLX5_SRQ_RQ; 1178 else if (!qp->has_rq) 1179 return MLX5_ZERO_LEN_RQ; 1180 else 1181 return MLX5_NON_ZERO_RQ; 1182 } 1183 1184 static int is_connected(enum ib_qp_type qp_type) 1185 { 1186 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || 1187 qp_type == MLX5_IB_QPT_DCI) 1188 return 1; 1189 1190 return 0; 1191 } 1192 1193 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1194 struct mlx5_ib_qp *qp, 1195 struct mlx5_ib_sq *sq, u32 tdn, 1196 struct ib_pd *pd) 1197 { 1198 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1199 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1200 1201 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1202 MLX5_SET(tisc, tisc, transport_domain, tdn); 1203 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1204 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1205 1206 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1207 } 1208 1209 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1210 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1211 { 1212 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1213 } 1214 1215 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1216 { 1217 if (sq->flow_rule) 1218 mlx5_del_flow_rules(sq->flow_rule); 1219 sq->flow_rule = NULL; 1220 } 1221 1222 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1223 struct ib_udata *udata, 1224 struct mlx5_ib_sq *sq, void *qpin, 1225 struct ib_pd *pd) 1226 { 1227 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1228 __be64 *pas; 1229 void *in; 1230 void *sqc; 1231 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1232 void *wq; 1233 int inlen; 1234 int err; 1235 int page_shift = 0; 1236 int npages; 1237 int ncont = 0; 1238 u32 offset = 0; 1239 1240 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, 1241 &sq->ubuffer.umem, &npages, &page_shift, &ncont, 1242 &offset); 1243 if (err) 1244 return err; 1245 1246 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1247 in = kvzalloc(inlen, GFP_KERNEL); 1248 if (!in) { 1249 err = -ENOMEM; 1250 goto err_umem; 1251 } 1252 1253 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1254 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1255 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1256 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1257 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1258 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1259 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1260 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1261 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1262 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1263 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1264 MLX5_CAP_ETH(dev->mdev, swp)) 1265 MLX5_SET(sqc, sqc, allow_swp, 1); 1266 1267 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1268 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1269 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1270 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1271 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1272 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1273 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1274 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1275 MLX5_SET(wq, wq, page_offset, offset); 1276 1277 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1278 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1279 1280 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1281 1282 kvfree(in); 1283 1284 if (err) 1285 goto err_umem; 1286 1287 return 0; 1288 1289 err_umem: 1290 ib_umem_release(sq->ubuffer.umem); 1291 sq->ubuffer.umem = NULL; 1292 1293 return err; 1294 } 1295 1296 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1297 struct mlx5_ib_sq *sq) 1298 { 1299 destroy_flow_rule_vport_sq(sq); 1300 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1301 ib_umem_release(sq->ubuffer.umem); 1302 } 1303 1304 static size_t get_rq_pas_size(void *qpc) 1305 { 1306 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1307 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1308 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1309 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1310 u32 po_quanta = 1 << (log_page_size - 6); 1311 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1312 u32 page_size = 1 << log_page_size; 1313 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1314 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1315 1316 return rq_num_pas * sizeof(u64); 1317 } 1318 1319 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1320 struct mlx5_ib_rq *rq, void *qpin, 1321 size_t qpinlen, struct ib_pd *pd) 1322 { 1323 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1324 __be64 *pas; 1325 __be64 *qp_pas; 1326 void *in; 1327 void *rqc; 1328 void *wq; 1329 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1330 size_t rq_pas_size = get_rq_pas_size(qpc); 1331 size_t inlen; 1332 int err; 1333 1334 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1335 return -EINVAL; 1336 1337 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1338 in = kvzalloc(inlen, GFP_KERNEL); 1339 if (!in) 1340 return -ENOMEM; 1341 1342 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1343 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1344 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1345 MLX5_SET(rqc, rqc, vsd, 1); 1346 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1347 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1348 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1349 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1350 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1351 1352 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1353 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1354 1355 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1356 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1357 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1358 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1359 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1360 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1361 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1362 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1363 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1364 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1365 1366 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1367 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1368 memcpy(pas, qp_pas, rq_pas_size); 1369 1370 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1371 1372 kvfree(in); 1373 1374 return err; 1375 } 1376 1377 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1378 struct mlx5_ib_rq *rq) 1379 { 1380 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1381 } 1382 1383 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1384 { 1385 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1386 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1387 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1388 } 1389 1390 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1391 struct mlx5_ib_rq *rq, 1392 u32 qp_flags_en, 1393 struct ib_pd *pd) 1394 { 1395 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1396 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1397 mlx5_ib_disable_lb(dev, false, true); 1398 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1399 } 1400 1401 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1402 struct mlx5_ib_rq *rq, u32 tdn, 1403 u32 *qp_flags_en, 1404 struct ib_pd *pd, 1405 u32 *out, int outlen) 1406 { 1407 u8 lb_flag = 0; 1408 u32 *in; 1409 void *tirc; 1410 int inlen; 1411 int err; 1412 1413 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1414 in = kvzalloc(inlen, GFP_KERNEL); 1415 if (!in) 1416 return -ENOMEM; 1417 1418 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1419 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1420 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1421 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1422 MLX5_SET(tirc, tirc, transport_domain, tdn); 1423 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1424 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1425 1426 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1427 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1428 1429 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1430 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1431 1432 if (dev->is_rep) { 1433 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1434 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1435 } 1436 1437 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1438 1439 err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen); 1440 1441 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1442 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1443 err = mlx5_ib_enable_lb(dev, false, true); 1444 1445 if (err) 1446 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1447 } 1448 kvfree(in); 1449 1450 return err; 1451 } 1452 1453 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1454 u32 *in, size_t inlen, 1455 struct ib_pd *pd, 1456 struct ib_udata *udata, 1457 struct mlx5_ib_create_qp_resp *resp) 1458 { 1459 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1460 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1461 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1462 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1463 udata, struct mlx5_ib_ucontext, ibucontext); 1464 int err; 1465 u32 tdn = mucontext->tdn; 1466 u16 uid = to_mpd(pd)->uid; 1467 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1468 1469 if (qp->sq.wqe_cnt) { 1470 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1471 if (err) 1472 return err; 1473 1474 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); 1475 if (err) 1476 goto err_destroy_tis; 1477 1478 if (uid) { 1479 resp->tisn = sq->tisn; 1480 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1481 resp->sqn = sq->base.mqp.qpn; 1482 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1483 } 1484 1485 sq->base.container_mibqp = qp; 1486 sq->base.mqp.event = mlx5_ib_qp_event; 1487 } 1488 1489 if (qp->rq.wqe_cnt) { 1490 rq->base.container_mibqp = qp; 1491 1492 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1493 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1494 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1495 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1496 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1497 if (err) 1498 goto err_destroy_sq; 1499 1500 err = create_raw_packet_qp_tir( 1501 dev, rq, tdn, &qp->flags_en, pd, out, 1502 MLX5_ST_SZ_BYTES(create_tir_out)); 1503 if (err) 1504 goto err_destroy_rq; 1505 1506 if (uid) { 1507 resp->rqn = rq->base.mqp.qpn; 1508 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1509 resp->tirn = rq->tirn; 1510 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1511 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1512 resp->tir_icm_addr = MLX5_GET( 1513 create_tir_out, out, icm_address_31_0); 1514 resp->tir_icm_addr |= 1515 (u64)MLX5_GET(create_tir_out, out, 1516 icm_address_39_32) 1517 << 32; 1518 resp->tir_icm_addr |= 1519 (u64)MLX5_GET(create_tir_out, out, 1520 icm_address_63_40) 1521 << 40; 1522 resp->comp_mask |= 1523 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1524 } 1525 } 1526 } 1527 1528 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1529 rq->base.mqp.qpn; 1530 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1531 if (err) 1532 goto err_destroy_tir; 1533 1534 return 0; 1535 1536 err_destroy_tir: 1537 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); 1538 err_destroy_rq: 1539 destroy_raw_packet_qp_rq(dev, rq); 1540 err_destroy_sq: 1541 if (!qp->sq.wqe_cnt) 1542 return err; 1543 destroy_raw_packet_qp_sq(dev, sq); 1544 err_destroy_tis: 1545 destroy_raw_packet_qp_tis(dev, sq, pd); 1546 1547 return err; 1548 } 1549 1550 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1551 struct mlx5_ib_qp *qp) 1552 { 1553 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1554 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1555 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1556 1557 if (qp->rq.wqe_cnt) { 1558 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1559 destroy_raw_packet_qp_rq(dev, rq); 1560 } 1561 1562 if (qp->sq.wqe_cnt) { 1563 destroy_raw_packet_qp_sq(dev, sq); 1564 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1565 } 1566 } 1567 1568 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1569 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1570 { 1571 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1572 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1573 1574 sq->sq = &qp->sq; 1575 rq->rq = &qp->rq; 1576 sq->doorbell = &qp->db; 1577 rq->doorbell = &qp->db; 1578 } 1579 1580 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1581 { 1582 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1583 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1584 mlx5_ib_disable_lb(dev, false, true); 1585 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1586 to_mpd(qp->ibqp.pd)->uid); 1587 } 1588 1589 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1590 struct ib_pd *pd, 1591 struct ib_qp_init_attr *init_attr, 1592 struct ib_udata *udata) 1593 { 1594 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1595 udata, struct mlx5_ib_ucontext, ibucontext); 1596 struct mlx5_ib_create_qp_resp resp = {}; 1597 int inlen; 1598 int outlen; 1599 int err; 1600 u32 *in; 1601 u32 *out; 1602 void *tirc; 1603 void *hfso; 1604 u32 selected_fields = 0; 1605 u32 outer_l4; 1606 size_t min_resp_len; 1607 u32 tdn = mucontext->tdn; 1608 struct mlx5_ib_create_qp_rss ucmd = {}; 1609 size_t required_cmd_sz; 1610 u8 lb_flag = 0; 1611 1612 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1613 return -EOPNOTSUPP; 1614 1615 if (init_attr->create_flags || init_attr->send_cq) 1616 return -EINVAL; 1617 1618 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1619 if (udata->outlen < min_resp_len) 1620 return -EINVAL; 1621 1622 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1623 if (udata->inlen < required_cmd_sz) { 1624 mlx5_ib_dbg(dev, "invalid inlen\n"); 1625 return -EINVAL; 1626 } 1627 1628 if (udata->inlen > sizeof(ucmd) && 1629 !ib_is_udata_cleared(udata, sizeof(ucmd), 1630 udata->inlen - sizeof(ucmd))) { 1631 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1632 return -EOPNOTSUPP; 1633 } 1634 1635 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1636 mlx5_ib_dbg(dev, "copy failed\n"); 1637 return -EFAULT; 1638 } 1639 1640 if (ucmd.comp_mask) { 1641 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1642 return -EOPNOTSUPP; 1643 } 1644 1645 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1646 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1647 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { 1648 mlx5_ib_dbg(dev, "invalid flags\n"); 1649 return -EOPNOTSUPP; 1650 } 1651 1652 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1653 !tunnel_offload_supported(dev->mdev)) { 1654 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1655 return -EOPNOTSUPP; 1656 } 1657 1658 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1659 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1660 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1661 return -EOPNOTSUPP; 1662 } 1663 1664 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) { 1665 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1666 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1667 } 1668 1669 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1670 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1671 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1672 } 1673 1674 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1675 if (err) { 1676 mlx5_ib_dbg(dev, "copy failed\n"); 1677 return -EINVAL; 1678 } 1679 1680 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1681 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1682 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1683 if (!in) 1684 return -ENOMEM; 1685 1686 out = in + MLX5_ST_SZ_DW(create_tir_in); 1687 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1688 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1689 MLX5_SET(tirc, tirc, disp_type, 1690 MLX5_TIRC_DISP_TYPE_INDIRECT); 1691 MLX5_SET(tirc, tirc, indirect_table, 1692 init_attr->rwq_ind_tbl->ind_tbl_num); 1693 MLX5_SET(tirc, tirc, transport_domain, tdn); 1694 1695 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1696 1697 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1698 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1699 1700 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1701 1702 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1703 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1704 else 1705 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1706 1707 switch (ucmd.rx_hash_function) { 1708 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1709 { 1710 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1711 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1712 1713 if (len != ucmd.rx_key_len) { 1714 err = -EINVAL; 1715 goto err; 1716 } 1717 1718 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1719 memcpy(rss_key, ucmd.rx_hash_key, len); 1720 break; 1721 } 1722 default: 1723 err = -EOPNOTSUPP; 1724 goto err; 1725 } 1726 1727 if (!ucmd.rx_hash_fields_mask) { 1728 /* special case when this TIR serves as steering entry without hashing */ 1729 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1730 goto create_tir; 1731 err = -EINVAL; 1732 goto err; 1733 } 1734 1735 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1736 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1737 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1738 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1739 err = -EINVAL; 1740 goto err; 1741 } 1742 1743 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1744 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1745 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1746 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1747 MLX5_L3_PROT_TYPE_IPV4); 1748 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1749 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1750 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1751 MLX5_L3_PROT_TYPE_IPV6); 1752 1753 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1754 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1755 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1756 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1757 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1758 1759 /* Check that only one l4 protocol is set */ 1760 if (outer_l4 & (outer_l4 - 1)) { 1761 err = -EINVAL; 1762 goto err; 1763 } 1764 1765 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1766 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1767 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1768 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1769 MLX5_L4_PROT_TYPE_TCP); 1770 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1771 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1772 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1773 MLX5_L4_PROT_TYPE_UDP); 1774 1775 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1776 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1777 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1778 1779 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1780 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1781 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1782 1783 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1784 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1785 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1786 1787 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1788 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1789 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1790 1791 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1792 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1793 1794 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1795 1796 create_tir: 1797 err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen); 1798 1799 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1800 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1801 err = mlx5_ib_enable_lb(dev, false, true); 1802 1803 if (err) 1804 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1805 to_mpd(pd)->uid); 1806 } 1807 1808 if (err) 1809 goto err; 1810 1811 if (mucontext->devx_uid) { 1812 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1813 resp.tirn = qp->rss_qp.tirn; 1814 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1815 resp.tir_icm_addr = 1816 MLX5_GET(create_tir_out, out, icm_address_31_0); 1817 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, 1818 icm_address_39_32) 1819 << 32; 1820 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, 1821 icm_address_63_40) 1822 << 40; 1823 resp.comp_mask |= 1824 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1825 } 1826 } 1827 1828 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1829 if (err) 1830 goto err_copy; 1831 1832 kvfree(in); 1833 /* qpn is reserved for that QP */ 1834 qp->trans_qp.base.mqp.qpn = 0; 1835 qp->flags |= MLX5_IB_QP_RSS; 1836 return 0; 1837 1838 err_copy: 1839 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); 1840 err: 1841 kvfree(in); 1842 return err; 1843 } 1844 1845 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, 1846 void *qpc) 1847 { 1848 int rcqe_sz; 1849 1850 if (init_attr->qp_type == MLX5_IB_QPT_DCI) 1851 return; 1852 1853 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1854 1855 if (init_attr->qp_type == MLX5_IB_QPT_DCT) { 1856 if (rcqe_sz == 128) 1857 MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1858 1859 return; 1860 } 1861 1862 MLX5_SET(qpc, qpc, cs_res, 1863 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 1864 MLX5_RES_SCAT_DATA32_CQE); 1865 } 1866 1867 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1868 struct ib_qp_init_attr *init_attr, 1869 struct mlx5_ib_create_qp *ucmd, 1870 void *qpc) 1871 { 1872 enum ib_qp_type qpt = init_attr->qp_type; 1873 int scqe_sz; 1874 bool allow_scat_cqe = 0; 1875 1876 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) 1877 return; 1878 1879 if (ucmd) 1880 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1881 1882 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1883 return; 1884 1885 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1886 if (scqe_sz == 128) { 1887 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1888 return; 1889 } 1890 1891 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1892 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1893 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1894 } 1895 1896 static int atomic_size_to_mode(int size_mask) 1897 { 1898 /* driver does not support atomic_size > 256B 1899 * and does not know how to translate bigger sizes 1900 */ 1901 int supported_size_mask = size_mask & 0x1ff; 1902 int log_max_size; 1903 1904 if (!supported_size_mask) 1905 return -EOPNOTSUPP; 1906 1907 log_max_size = __fls(supported_size_mask); 1908 1909 if (log_max_size > 3) 1910 return log_max_size; 1911 1912 return MLX5_ATOMIC_MODE_8B; 1913 } 1914 1915 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1916 enum ib_qp_type qp_type) 1917 { 1918 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1919 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1920 int atomic_mode = -EOPNOTSUPP; 1921 int atomic_size_mask; 1922 1923 if (!atomic) 1924 return -EOPNOTSUPP; 1925 1926 if (qp_type == MLX5_IB_QPT_DCT) 1927 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1928 else 1929 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1930 1931 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1932 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1933 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1934 1935 if (atomic_mode <= 0 && 1936 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1937 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1938 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1939 1940 return atomic_mode; 1941 } 1942 1943 static inline bool check_flags_mask(uint64_t input, uint64_t supported) 1944 { 1945 return (input & ~supported) == 0; 1946 } 1947 1948 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1949 struct ib_qp_init_attr *init_attr, 1950 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1951 { 1952 struct mlx5_ib_resources *devr = &dev->devr; 1953 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1954 struct mlx5_core_dev *mdev = dev->mdev; 1955 struct mlx5_ib_create_qp_resp resp = {}; 1956 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 1957 udata, struct mlx5_ib_ucontext, ibucontext); 1958 struct mlx5_ib_cq *send_cq; 1959 struct mlx5_ib_cq *recv_cq; 1960 unsigned long flags; 1961 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1962 struct mlx5_ib_create_qp ucmd; 1963 struct mlx5_ib_qp_base *base; 1964 int mlx5_st; 1965 void *qpc; 1966 u32 *in; 1967 int err; 1968 1969 mutex_init(&qp->mutex); 1970 spin_lock_init(&qp->sq.lock); 1971 spin_lock_init(&qp->rq.lock); 1972 1973 mlx5_st = to_mlx5_st(init_attr->qp_type); 1974 if (mlx5_st < 0) 1975 return -EINVAL; 1976 1977 if (init_attr->rwq_ind_tbl) { 1978 if (!udata) 1979 return -ENOSYS; 1980 1981 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1982 return err; 1983 } 1984 1985 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1986 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1987 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1988 return -EINVAL; 1989 } else { 1990 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1991 } 1992 } 1993 1994 if (init_attr->create_flags & 1995 (IB_QP_CREATE_CROSS_CHANNEL | 1996 IB_QP_CREATE_MANAGED_SEND | 1997 IB_QP_CREATE_MANAGED_RECV)) { 1998 if (!MLX5_CAP_GEN(mdev, cd)) { 1999 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 2000 return -EINVAL; 2001 } 2002 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 2003 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 2004 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 2005 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 2006 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 2007 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 2008 } 2009 2010 if (init_attr->qp_type == IB_QPT_UD && 2011 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 2012 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 2013 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 2014 return -EOPNOTSUPP; 2015 } 2016 2017 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 2018 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2019 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 2020 return -EOPNOTSUPP; 2021 } 2022 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 2023 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 2024 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 2025 return -EOPNOTSUPP; 2026 } 2027 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 2028 } 2029 2030 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2031 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2032 2033 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 2034 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 2035 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 2036 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 2037 return -EOPNOTSUPP; 2038 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 2039 } 2040 2041 if (udata) { 2042 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 2043 mlx5_ib_dbg(dev, "copy failed\n"); 2044 return -EFAULT; 2045 } 2046 2047 if (!check_flags_mask(ucmd.flags, 2048 MLX5_QP_FLAG_ALLOW_SCATTER_CQE | 2049 MLX5_QP_FLAG_BFREG_INDEX | 2050 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE | 2051 MLX5_QP_FLAG_SCATTER_CQE | 2052 MLX5_QP_FLAG_SIGNATURE | 2053 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC | 2054 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2055 MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2056 MLX5_QP_FLAG_TYPE_DCI | 2057 MLX5_QP_FLAG_TYPE_DCT)) 2058 return -EINVAL; 2059 2060 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx); 2061 if (err) 2062 return err; 2063 2064 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 2065 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) 2066 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 2067 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 2068 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 2069 !tunnel_offload_supported(mdev)) { 2070 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 2071 return -EOPNOTSUPP; 2072 } 2073 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; 2074 } 2075 2076 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { 2077 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2078 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); 2079 return -EOPNOTSUPP; 2080 } 2081 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 2082 } 2083 2084 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 2085 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2086 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); 2087 return -EOPNOTSUPP; 2088 } 2089 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 2090 } 2091 2092 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { 2093 if (init_attr->qp_type != IB_QPT_RC || 2094 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { 2095 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); 2096 return -EOPNOTSUPP; 2097 } 2098 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; 2099 } 2100 2101 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 2102 if (init_attr->qp_type != IB_QPT_UD || 2103 (MLX5_CAP_GEN(dev->mdev, port_type) != 2104 MLX5_CAP_PORT_TYPE_IB) || 2105 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 2106 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 2107 return -EOPNOTSUPP; 2108 } 2109 2110 qp->flags |= MLX5_IB_QP_UNDERLAY; 2111 qp->underlay_qpn = init_attr->source_qpn; 2112 } 2113 } else { 2114 qp->wq_sig = !!wq_signature; 2115 } 2116 2117 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2118 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2119 &qp->raw_packet_qp.rq.base : 2120 &qp->trans_qp.base; 2121 2122 qp->has_rq = qp_has_rq(init_attr); 2123 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 2124 qp, udata ? &ucmd : NULL); 2125 if (err) { 2126 mlx5_ib_dbg(dev, "err %d\n", err); 2127 return err; 2128 } 2129 2130 if (pd) { 2131 if (udata) { 2132 __u32 max_wqes = 2133 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 2134 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 2135 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 2136 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 2137 mlx5_ib_dbg(dev, "invalid rq params\n"); 2138 return -EINVAL; 2139 } 2140 if (ucmd.sq_wqe_count > max_wqes) { 2141 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 2142 ucmd.sq_wqe_count, max_wqes); 2143 return -EINVAL; 2144 } 2145 if (init_attr->create_flags & 2146 MLX5_IB_QP_CREATE_SQPN_QP1) { 2147 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 2148 return -EINVAL; 2149 } 2150 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 2151 &resp, &inlen, base); 2152 if (err) 2153 mlx5_ib_dbg(dev, "err %d\n", err); 2154 } else { 2155 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 2156 base); 2157 if (err) 2158 mlx5_ib_dbg(dev, "err %d\n", err); 2159 } 2160 2161 if (err) 2162 return err; 2163 } else { 2164 in = kvzalloc(inlen, GFP_KERNEL); 2165 if (!in) 2166 return -ENOMEM; 2167 2168 qp->create_type = MLX5_QP_EMPTY; 2169 } 2170 2171 if (is_sqp(init_attr->qp_type)) 2172 qp->port = init_attr->port_num; 2173 2174 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2175 2176 MLX5_SET(qpc, qpc, st, mlx5_st); 2177 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2178 2179 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 2180 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2181 else 2182 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2183 2184 2185 if (qp->wq_sig) 2186 MLX5_SET(qpc, qpc, wq_signature, 1); 2187 2188 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2189 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2190 2191 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 2192 MLX5_SET(qpc, qpc, cd_master, 1); 2193 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 2194 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2195 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 2196 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2197 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) 2198 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2199 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 2200 configure_responder_scat_cqe(init_attr, qpc); 2201 configure_requester_scat_cqe(dev, init_attr, 2202 udata ? &ucmd : NULL, 2203 qpc); 2204 } 2205 2206 if (qp->rq.wqe_cnt) { 2207 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2208 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2209 } 2210 2211 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2212 2213 if (qp->sq.wqe_cnt) { 2214 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2215 } else { 2216 MLX5_SET(qpc, qpc, no_sq, 1); 2217 if (init_attr->srq && 2218 init_attr->srq->srq_type == IB_SRQT_TM) 2219 MLX5_SET(qpc, qpc, offload_type, 2220 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2221 } 2222 2223 /* Set default resources */ 2224 switch (init_attr->qp_type) { 2225 case IB_QPT_XRC_TGT: 2226 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2227 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2228 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2229 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 2230 break; 2231 case IB_QPT_XRC_INI: 2232 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2233 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2234 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2235 break; 2236 default: 2237 if (init_attr->srq) { 2238 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2239 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2240 } else { 2241 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2242 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2243 } 2244 } 2245 2246 if (init_attr->send_cq) 2247 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2248 2249 if (init_attr->recv_cq) 2250 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2251 2252 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2253 2254 /* 0xffffff means we ask to work with cqe version 0 */ 2255 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2256 MLX5_SET(qpc, qpc, user_index, uidx); 2257 2258 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2259 if (init_attr->qp_type == IB_QPT_UD && 2260 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 2261 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2262 qp->flags |= MLX5_IB_QP_LSO; 2263 } 2264 2265 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2266 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 2267 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 2268 err = -EOPNOTSUPP; 2269 goto err; 2270 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2271 MLX5_SET(qpc, qpc, end_padding_mode, 2272 MLX5_WQ_END_PAD_MODE_ALIGN); 2273 } else { 2274 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 2275 } 2276 } 2277 2278 if (inlen < 0) { 2279 err = -EINVAL; 2280 goto err; 2281 } 2282 2283 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2284 qp->flags & MLX5_IB_QP_UNDERLAY) { 2285 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 2286 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2287 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2288 &resp); 2289 } else { 2290 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 2291 } 2292 2293 if (err) { 2294 mlx5_ib_dbg(dev, "create qp failed\n"); 2295 goto err_create; 2296 } 2297 2298 kvfree(in); 2299 2300 base->container_mibqp = qp; 2301 base->mqp.event = mlx5_ib_qp_event; 2302 2303 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 2304 &send_cq, &recv_cq); 2305 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2306 mlx5_ib_lock_cqs(send_cq, recv_cq); 2307 /* Maintain device to QPs access, needed for further handling via reset 2308 * flow 2309 */ 2310 list_add_tail(&qp->qps_list, &dev->qp_list); 2311 /* Maintain CQ to QPs access, needed for further handling via reset flow 2312 */ 2313 if (send_cq) 2314 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2315 if (recv_cq) 2316 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2317 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2318 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2319 2320 return 0; 2321 2322 err_create: 2323 if (qp->create_type == MLX5_QP_USER) 2324 destroy_qp_user(dev, pd, qp, base, udata); 2325 else if (qp->create_type == MLX5_QP_KERNEL) 2326 destroy_qp_kernel(dev, qp); 2327 2328 err: 2329 kvfree(in); 2330 return err; 2331 } 2332 2333 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2334 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2335 { 2336 if (send_cq) { 2337 if (recv_cq) { 2338 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2339 spin_lock(&send_cq->lock); 2340 spin_lock_nested(&recv_cq->lock, 2341 SINGLE_DEPTH_NESTING); 2342 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2343 spin_lock(&send_cq->lock); 2344 __acquire(&recv_cq->lock); 2345 } else { 2346 spin_lock(&recv_cq->lock); 2347 spin_lock_nested(&send_cq->lock, 2348 SINGLE_DEPTH_NESTING); 2349 } 2350 } else { 2351 spin_lock(&send_cq->lock); 2352 __acquire(&recv_cq->lock); 2353 } 2354 } else if (recv_cq) { 2355 spin_lock(&recv_cq->lock); 2356 __acquire(&send_cq->lock); 2357 } else { 2358 __acquire(&send_cq->lock); 2359 __acquire(&recv_cq->lock); 2360 } 2361 } 2362 2363 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2364 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2365 { 2366 if (send_cq) { 2367 if (recv_cq) { 2368 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2369 spin_unlock(&recv_cq->lock); 2370 spin_unlock(&send_cq->lock); 2371 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2372 __release(&recv_cq->lock); 2373 spin_unlock(&send_cq->lock); 2374 } else { 2375 spin_unlock(&send_cq->lock); 2376 spin_unlock(&recv_cq->lock); 2377 } 2378 } else { 2379 __release(&recv_cq->lock); 2380 spin_unlock(&send_cq->lock); 2381 } 2382 } else if (recv_cq) { 2383 __release(&send_cq->lock); 2384 spin_unlock(&recv_cq->lock); 2385 } else { 2386 __release(&recv_cq->lock); 2387 __release(&send_cq->lock); 2388 } 2389 } 2390 2391 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2392 { 2393 return to_mpd(qp->ibqp.pd); 2394 } 2395 2396 static void get_cqs(enum ib_qp_type qp_type, 2397 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2398 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2399 { 2400 switch (qp_type) { 2401 case IB_QPT_XRC_TGT: 2402 *send_cq = NULL; 2403 *recv_cq = NULL; 2404 break; 2405 case MLX5_IB_QPT_REG_UMR: 2406 case IB_QPT_XRC_INI: 2407 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2408 *recv_cq = NULL; 2409 break; 2410 2411 case IB_QPT_SMI: 2412 case MLX5_IB_QPT_HW_GSI: 2413 case IB_QPT_RC: 2414 case IB_QPT_UC: 2415 case IB_QPT_UD: 2416 case IB_QPT_RAW_IPV6: 2417 case IB_QPT_RAW_ETHERTYPE: 2418 case IB_QPT_RAW_PACKET: 2419 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2420 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2421 break; 2422 2423 case IB_QPT_MAX: 2424 default: 2425 *send_cq = NULL; 2426 *recv_cq = NULL; 2427 break; 2428 } 2429 } 2430 2431 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2432 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2433 u8 lag_tx_affinity); 2434 2435 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2436 struct ib_udata *udata) 2437 { 2438 struct mlx5_ib_cq *send_cq, *recv_cq; 2439 struct mlx5_ib_qp_base *base; 2440 unsigned long flags; 2441 int err; 2442 2443 if (qp->ibqp.rwq_ind_tbl) { 2444 destroy_rss_raw_qp_tir(dev, qp); 2445 return; 2446 } 2447 2448 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2449 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2450 &qp->raw_packet_qp.rq.base : 2451 &qp->trans_qp.base; 2452 2453 if (qp->state != IB_QPS_RESET) { 2454 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2455 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2456 err = mlx5_core_qp_modify(dev->mdev, 2457 MLX5_CMD_OP_2RST_QP, 0, 2458 NULL, &base->mqp); 2459 } else { 2460 struct mlx5_modify_raw_qp_param raw_qp_param = { 2461 .operation = MLX5_CMD_OP_2RST_QP 2462 }; 2463 2464 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2465 } 2466 if (err) 2467 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2468 base->mqp.qpn); 2469 } 2470 2471 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2472 &send_cq, &recv_cq); 2473 2474 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2475 mlx5_ib_lock_cqs(send_cq, recv_cq); 2476 /* del from lists under both locks above to protect reset flow paths */ 2477 list_del(&qp->qps_list); 2478 if (send_cq) 2479 list_del(&qp->cq_send_list); 2480 2481 if (recv_cq) 2482 list_del(&qp->cq_recv_list); 2483 2484 if (qp->create_type == MLX5_QP_KERNEL) { 2485 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2486 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2487 if (send_cq != recv_cq) 2488 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2489 NULL); 2490 } 2491 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2492 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2493 2494 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2495 qp->flags & MLX5_IB_QP_UNDERLAY) { 2496 destroy_raw_packet_qp(dev, qp); 2497 } else { 2498 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2499 if (err) 2500 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2501 base->mqp.qpn); 2502 } 2503 2504 if (qp->create_type == MLX5_QP_KERNEL) 2505 destroy_qp_kernel(dev, qp); 2506 else if (qp->create_type == MLX5_QP_USER) 2507 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); 2508 } 2509 2510 static const char *ib_qp_type_str(enum ib_qp_type type) 2511 { 2512 switch (type) { 2513 case IB_QPT_SMI: 2514 return "IB_QPT_SMI"; 2515 case IB_QPT_GSI: 2516 return "IB_QPT_GSI"; 2517 case IB_QPT_RC: 2518 return "IB_QPT_RC"; 2519 case IB_QPT_UC: 2520 return "IB_QPT_UC"; 2521 case IB_QPT_UD: 2522 return "IB_QPT_UD"; 2523 case IB_QPT_RAW_IPV6: 2524 return "IB_QPT_RAW_IPV6"; 2525 case IB_QPT_RAW_ETHERTYPE: 2526 return "IB_QPT_RAW_ETHERTYPE"; 2527 case IB_QPT_XRC_INI: 2528 return "IB_QPT_XRC_INI"; 2529 case IB_QPT_XRC_TGT: 2530 return "IB_QPT_XRC_TGT"; 2531 case IB_QPT_RAW_PACKET: 2532 return "IB_QPT_RAW_PACKET"; 2533 case MLX5_IB_QPT_REG_UMR: 2534 return "MLX5_IB_QPT_REG_UMR"; 2535 case IB_QPT_DRIVER: 2536 return "IB_QPT_DRIVER"; 2537 case IB_QPT_MAX: 2538 default: 2539 return "Invalid QP type"; 2540 } 2541 } 2542 2543 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2544 struct ib_qp_init_attr *attr, 2545 struct mlx5_ib_create_qp *ucmd, 2546 struct ib_udata *udata) 2547 { 2548 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2549 udata, struct mlx5_ib_ucontext, ibucontext); 2550 struct mlx5_ib_qp *qp; 2551 int err = 0; 2552 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2553 void *dctc; 2554 2555 if (!attr->srq || !attr->recv_cq) 2556 return ERR_PTR(-EINVAL); 2557 2558 err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx); 2559 if (err) 2560 return ERR_PTR(err); 2561 2562 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2563 if (!qp) 2564 return ERR_PTR(-ENOMEM); 2565 2566 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2567 if (!qp->dct.in) { 2568 err = -ENOMEM; 2569 goto err_free; 2570 } 2571 2572 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2573 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2574 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2575 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2576 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2577 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2578 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2579 MLX5_SET(dctc, dctc, user_index, uidx); 2580 2581 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) 2582 configure_responder_scat_cqe(attr, dctc); 2583 2584 qp->state = IB_QPS_RESET; 2585 2586 return &qp->ibqp; 2587 err_free: 2588 kfree(qp); 2589 return ERR_PTR(err); 2590 } 2591 2592 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2593 struct ib_qp_init_attr *init_attr, 2594 struct mlx5_ib_create_qp *ucmd, 2595 struct ib_udata *udata) 2596 { 2597 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2598 int err; 2599 2600 if (!udata) 2601 return -EINVAL; 2602 2603 if (udata->inlen < sizeof(*ucmd)) { 2604 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2605 return -EINVAL; 2606 } 2607 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2608 if (err) 2609 return err; 2610 2611 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2612 init_attr->qp_type = MLX5_IB_QPT_DCI; 2613 } else { 2614 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2615 init_attr->qp_type = MLX5_IB_QPT_DCT; 2616 } else { 2617 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2618 return -EINVAL; 2619 } 2620 } 2621 2622 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2623 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2624 return -EOPNOTSUPP; 2625 } 2626 2627 return 0; 2628 } 2629 2630 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2631 struct ib_qp_init_attr *verbs_init_attr, 2632 struct ib_udata *udata) 2633 { 2634 struct mlx5_ib_dev *dev; 2635 struct mlx5_ib_qp *qp; 2636 u16 xrcdn = 0; 2637 int err; 2638 struct ib_qp_init_attr mlx_init_attr; 2639 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2640 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2641 udata, struct mlx5_ib_ucontext, ibucontext); 2642 2643 if (pd) { 2644 dev = to_mdev(pd->device); 2645 2646 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2647 if (!ucontext) { 2648 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2649 return ERR_PTR(-EINVAL); 2650 } else if (!ucontext->cqe_version) { 2651 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2652 return ERR_PTR(-EINVAL); 2653 } 2654 } 2655 } else { 2656 /* being cautious here */ 2657 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2658 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2659 pr_warn("%s: no PD for transport %s\n", __func__, 2660 ib_qp_type_str(init_attr->qp_type)); 2661 return ERR_PTR(-EINVAL); 2662 } 2663 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2664 } 2665 2666 if (init_attr->qp_type == IB_QPT_DRIVER) { 2667 struct mlx5_ib_create_qp ucmd; 2668 2669 init_attr = &mlx_init_attr; 2670 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2671 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2672 if (err) 2673 return ERR_PTR(err); 2674 2675 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2676 if (init_attr->cap.max_recv_wr || 2677 init_attr->cap.max_recv_sge) { 2678 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2679 return ERR_PTR(-EINVAL); 2680 } 2681 } else { 2682 return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata); 2683 } 2684 } 2685 2686 switch (init_attr->qp_type) { 2687 case IB_QPT_XRC_TGT: 2688 case IB_QPT_XRC_INI: 2689 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2690 mlx5_ib_dbg(dev, "XRC not supported\n"); 2691 return ERR_PTR(-ENOSYS); 2692 } 2693 init_attr->recv_cq = NULL; 2694 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2695 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2696 init_attr->send_cq = NULL; 2697 } 2698 2699 /* fall through */ 2700 case IB_QPT_RAW_PACKET: 2701 case IB_QPT_RC: 2702 case IB_QPT_UC: 2703 case IB_QPT_UD: 2704 case IB_QPT_SMI: 2705 case MLX5_IB_QPT_HW_GSI: 2706 case MLX5_IB_QPT_REG_UMR: 2707 case MLX5_IB_QPT_DCI: 2708 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2709 if (!qp) 2710 return ERR_PTR(-ENOMEM); 2711 2712 err = create_qp_common(dev, pd, init_attr, udata, qp); 2713 if (err) { 2714 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2715 kfree(qp); 2716 return ERR_PTR(err); 2717 } 2718 2719 if (is_qp0(init_attr->qp_type)) 2720 qp->ibqp.qp_num = 0; 2721 else if (is_qp1(init_attr->qp_type)) 2722 qp->ibqp.qp_num = 1; 2723 else 2724 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2725 2726 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2727 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2728 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2729 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2730 2731 qp->trans_qp.xrcdn = xrcdn; 2732 2733 break; 2734 2735 case IB_QPT_GSI: 2736 return mlx5_ib_gsi_create_qp(pd, init_attr); 2737 2738 case IB_QPT_RAW_IPV6: 2739 case IB_QPT_RAW_ETHERTYPE: 2740 case IB_QPT_MAX: 2741 default: 2742 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2743 init_attr->qp_type); 2744 /* Don't support raw QPs */ 2745 return ERR_PTR(-EINVAL); 2746 } 2747 2748 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2749 qp->qp_sub_type = init_attr->qp_type; 2750 2751 return &qp->ibqp; 2752 } 2753 2754 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2755 { 2756 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2757 2758 if (mqp->state == IB_QPS_RTR) { 2759 int err; 2760 2761 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2762 if (err) { 2763 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2764 return err; 2765 } 2766 } 2767 2768 kfree(mqp->dct.in); 2769 kfree(mqp); 2770 return 0; 2771 } 2772 2773 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2774 { 2775 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2776 struct mlx5_ib_qp *mqp = to_mqp(qp); 2777 2778 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2779 return mlx5_ib_gsi_destroy_qp(qp); 2780 2781 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2782 return mlx5_ib_destroy_dct(mqp); 2783 2784 destroy_qp_common(dev, mqp, udata); 2785 2786 kfree(mqp); 2787 2788 return 0; 2789 } 2790 2791 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2792 const struct ib_qp_attr *attr, 2793 int attr_mask, __be32 *hw_access_flags_be) 2794 { 2795 u8 dest_rd_atomic; 2796 u32 access_flags, hw_access_flags = 0; 2797 2798 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2799 2800 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2801 dest_rd_atomic = attr->max_dest_rd_atomic; 2802 else 2803 dest_rd_atomic = qp->trans_qp.resp_depth; 2804 2805 if (attr_mask & IB_QP_ACCESS_FLAGS) 2806 access_flags = attr->qp_access_flags; 2807 else 2808 access_flags = qp->trans_qp.atomic_rd_en; 2809 2810 if (!dest_rd_atomic) 2811 access_flags &= IB_ACCESS_REMOTE_WRITE; 2812 2813 if (access_flags & IB_ACCESS_REMOTE_READ) 2814 hw_access_flags |= MLX5_QP_BIT_RRE; 2815 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2816 int atomic_mode; 2817 2818 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2819 if (atomic_mode < 0) 2820 return -EOPNOTSUPP; 2821 2822 hw_access_flags |= MLX5_QP_BIT_RAE; 2823 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; 2824 } 2825 2826 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2827 hw_access_flags |= MLX5_QP_BIT_RWE; 2828 2829 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2830 2831 return 0; 2832 } 2833 2834 enum { 2835 MLX5_PATH_FLAG_FL = 1 << 0, 2836 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2837 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2838 }; 2839 2840 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2841 { 2842 if (rate == IB_RATE_PORT_CURRENT) 2843 return 0; 2844 2845 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 2846 return -EINVAL; 2847 2848 while (rate != IB_RATE_PORT_CURRENT && 2849 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2850 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2851 --rate; 2852 2853 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2854 } 2855 2856 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2857 struct mlx5_ib_sq *sq, u8 sl, 2858 struct ib_pd *pd) 2859 { 2860 void *in; 2861 void *tisc; 2862 int inlen; 2863 int err; 2864 2865 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2866 in = kvzalloc(inlen, GFP_KERNEL); 2867 if (!in) 2868 return -ENOMEM; 2869 2870 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2871 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2872 2873 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2874 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2875 2876 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2877 2878 kvfree(in); 2879 2880 return err; 2881 } 2882 2883 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2884 struct mlx5_ib_sq *sq, u8 tx_affinity, 2885 struct ib_pd *pd) 2886 { 2887 void *in; 2888 void *tisc; 2889 int inlen; 2890 int err; 2891 2892 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2893 in = kvzalloc(inlen, GFP_KERNEL); 2894 if (!in) 2895 return -ENOMEM; 2896 2897 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2898 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2899 2900 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2901 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2902 2903 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2904 2905 kvfree(in); 2906 2907 return err; 2908 } 2909 2910 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2911 const struct rdma_ah_attr *ah, 2912 struct mlx5_qp_path *path, u8 port, int attr_mask, 2913 u32 path_flags, const struct ib_qp_attr *attr, 2914 bool alt) 2915 { 2916 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2917 int err; 2918 enum ib_gid_type gid_type; 2919 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2920 u8 sl = rdma_ah_get_sl(ah); 2921 2922 if (attr_mask & IB_QP_PKEY_INDEX) 2923 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2924 attr->pkey_index); 2925 2926 if (ah_flags & IB_AH_GRH) { 2927 if (grh->sgid_index >= 2928 dev->mdev->port_caps[port - 1].gid_table_len) { 2929 pr_err("sgid_index (%u) too large. max is %d\n", 2930 grh->sgid_index, 2931 dev->mdev->port_caps[port - 1].gid_table_len); 2932 return -EINVAL; 2933 } 2934 } 2935 2936 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2937 if (!(ah_flags & IB_AH_GRH)) 2938 return -EINVAL; 2939 2940 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2941 if (qp->ibqp.qp_type == IB_QPT_RC || 2942 qp->ibqp.qp_type == IB_QPT_UC || 2943 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2944 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2945 path->udp_sport = 2946 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); 2947 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2948 gid_type = ah->grh.sgid_attr->gid_type; 2949 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2950 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2951 } else { 2952 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2953 path->fl_free_ar |= 2954 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2955 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2956 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2957 if (ah_flags & IB_AH_GRH) 2958 path->grh_mlid |= 1 << 7; 2959 path->dci_cfi_prio_sl = sl & 0xf; 2960 } 2961 2962 if (ah_flags & IB_AH_GRH) { 2963 path->mgid_index = grh->sgid_index; 2964 path->hop_limit = grh->hop_limit; 2965 path->tclass_flowlabel = 2966 cpu_to_be32((grh->traffic_class << 20) | 2967 (grh->flow_label)); 2968 memcpy(path->rgid, grh->dgid.raw, 16); 2969 } 2970 2971 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2972 if (err < 0) 2973 return err; 2974 path->static_rate = err; 2975 path->port = port; 2976 2977 if (attr_mask & IB_QP_TIMEOUT) 2978 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2979 2980 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2981 return modify_raw_packet_eth_prio(dev->mdev, 2982 &qp->raw_packet_qp.sq, 2983 sl & 0xf, qp->ibqp.pd); 2984 2985 return 0; 2986 } 2987 2988 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2989 [MLX5_QP_STATE_INIT] = { 2990 [MLX5_QP_STATE_INIT] = { 2991 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2992 MLX5_QP_OPTPAR_RAE | 2993 MLX5_QP_OPTPAR_RWE | 2994 MLX5_QP_OPTPAR_PKEY_INDEX | 2995 MLX5_QP_OPTPAR_PRI_PORT, 2996 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2997 MLX5_QP_OPTPAR_PKEY_INDEX | 2998 MLX5_QP_OPTPAR_PRI_PORT, 2999 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3000 MLX5_QP_OPTPAR_Q_KEY | 3001 MLX5_QP_OPTPAR_PRI_PORT, 3002 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3003 MLX5_QP_OPTPAR_RAE | 3004 MLX5_QP_OPTPAR_RWE | 3005 MLX5_QP_OPTPAR_PKEY_INDEX | 3006 MLX5_QP_OPTPAR_PRI_PORT, 3007 }, 3008 [MLX5_QP_STATE_RTR] = { 3009 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3010 MLX5_QP_OPTPAR_RRE | 3011 MLX5_QP_OPTPAR_RAE | 3012 MLX5_QP_OPTPAR_RWE | 3013 MLX5_QP_OPTPAR_PKEY_INDEX, 3014 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3015 MLX5_QP_OPTPAR_RWE | 3016 MLX5_QP_OPTPAR_PKEY_INDEX, 3017 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3018 MLX5_QP_OPTPAR_Q_KEY, 3019 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3020 MLX5_QP_OPTPAR_Q_KEY, 3021 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3022 MLX5_QP_OPTPAR_RRE | 3023 MLX5_QP_OPTPAR_RAE | 3024 MLX5_QP_OPTPAR_RWE | 3025 MLX5_QP_OPTPAR_PKEY_INDEX, 3026 }, 3027 }, 3028 [MLX5_QP_STATE_RTR] = { 3029 [MLX5_QP_STATE_RTS] = { 3030 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3031 MLX5_QP_OPTPAR_RRE | 3032 MLX5_QP_OPTPAR_RAE | 3033 MLX5_QP_OPTPAR_RWE | 3034 MLX5_QP_OPTPAR_PM_STATE | 3035 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3036 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3037 MLX5_QP_OPTPAR_RWE | 3038 MLX5_QP_OPTPAR_PM_STATE, 3039 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3040 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3041 MLX5_QP_OPTPAR_RRE | 3042 MLX5_QP_OPTPAR_RAE | 3043 MLX5_QP_OPTPAR_RWE | 3044 MLX5_QP_OPTPAR_PM_STATE | 3045 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3046 }, 3047 }, 3048 [MLX5_QP_STATE_RTS] = { 3049 [MLX5_QP_STATE_RTS] = { 3050 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3051 MLX5_QP_OPTPAR_RAE | 3052 MLX5_QP_OPTPAR_RWE | 3053 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3054 MLX5_QP_OPTPAR_PM_STATE | 3055 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3056 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3057 MLX5_QP_OPTPAR_PM_STATE | 3058 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3059 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3060 MLX5_QP_OPTPAR_SRQN | 3061 MLX5_QP_OPTPAR_CQN_RCV, 3062 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3063 MLX5_QP_OPTPAR_RAE | 3064 MLX5_QP_OPTPAR_RWE | 3065 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3066 MLX5_QP_OPTPAR_PM_STATE | 3067 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3068 }, 3069 }, 3070 [MLX5_QP_STATE_SQER] = { 3071 [MLX5_QP_STATE_RTS] = { 3072 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3073 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3074 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3075 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3076 MLX5_QP_OPTPAR_RWE | 3077 MLX5_QP_OPTPAR_RAE | 3078 MLX5_QP_OPTPAR_RRE, 3079 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3080 MLX5_QP_OPTPAR_RWE | 3081 MLX5_QP_OPTPAR_RAE | 3082 MLX5_QP_OPTPAR_RRE, 3083 }, 3084 }, 3085 }; 3086 3087 static int ib_nr_to_mlx5_nr(int ib_mask) 3088 { 3089 switch (ib_mask) { 3090 case IB_QP_STATE: 3091 return 0; 3092 case IB_QP_CUR_STATE: 3093 return 0; 3094 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3095 return 0; 3096 case IB_QP_ACCESS_FLAGS: 3097 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3098 MLX5_QP_OPTPAR_RAE; 3099 case IB_QP_PKEY_INDEX: 3100 return MLX5_QP_OPTPAR_PKEY_INDEX; 3101 case IB_QP_PORT: 3102 return MLX5_QP_OPTPAR_PRI_PORT; 3103 case IB_QP_QKEY: 3104 return MLX5_QP_OPTPAR_Q_KEY; 3105 case IB_QP_AV: 3106 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3107 MLX5_QP_OPTPAR_PRI_PORT; 3108 case IB_QP_PATH_MTU: 3109 return 0; 3110 case IB_QP_TIMEOUT: 3111 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3112 case IB_QP_RETRY_CNT: 3113 return MLX5_QP_OPTPAR_RETRY_COUNT; 3114 case IB_QP_RNR_RETRY: 3115 return MLX5_QP_OPTPAR_RNR_RETRY; 3116 case IB_QP_RQ_PSN: 3117 return 0; 3118 case IB_QP_MAX_QP_RD_ATOMIC: 3119 return MLX5_QP_OPTPAR_SRA_MAX; 3120 case IB_QP_ALT_PATH: 3121 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3122 case IB_QP_MIN_RNR_TIMER: 3123 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3124 case IB_QP_SQ_PSN: 3125 return 0; 3126 case IB_QP_MAX_DEST_RD_ATOMIC: 3127 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3128 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3129 case IB_QP_PATH_MIG_STATE: 3130 return MLX5_QP_OPTPAR_PM_STATE; 3131 case IB_QP_CAP: 3132 return 0; 3133 case IB_QP_DEST_QPN: 3134 return 0; 3135 } 3136 return 0; 3137 } 3138 3139 static int ib_mask_to_mlx5_opt(int ib_mask) 3140 { 3141 int result = 0; 3142 int i; 3143 3144 for (i = 0; i < 8 * sizeof(int); i++) { 3145 if ((1 << i) & ib_mask) 3146 result |= ib_nr_to_mlx5_nr(1 << i); 3147 } 3148 3149 return result; 3150 } 3151 3152 static int modify_raw_packet_qp_rq( 3153 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3154 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3155 { 3156 void *in; 3157 void *rqc; 3158 int inlen; 3159 int err; 3160 3161 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3162 in = kvzalloc(inlen, GFP_KERNEL); 3163 if (!in) 3164 return -ENOMEM; 3165 3166 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3167 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3168 3169 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3170 MLX5_SET(rqc, rqc, state, new_state); 3171 3172 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3173 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3174 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3175 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3176 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3177 } else 3178 dev_info_once( 3179 &dev->ib_dev.dev, 3180 "RAW PACKET QP counters are not supported on current FW\n"); 3181 } 3182 3183 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 3184 if (err) 3185 goto out; 3186 3187 rq->state = new_state; 3188 3189 out: 3190 kvfree(in); 3191 return err; 3192 } 3193 3194 static int modify_raw_packet_qp_sq( 3195 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3196 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3197 { 3198 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3199 struct mlx5_rate_limit old_rl = ibqp->rl; 3200 struct mlx5_rate_limit new_rl = old_rl; 3201 bool new_rate_added = false; 3202 u16 rl_index = 0; 3203 void *in; 3204 void *sqc; 3205 int inlen; 3206 int err; 3207 3208 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3209 in = kvzalloc(inlen, GFP_KERNEL); 3210 if (!in) 3211 return -ENOMEM; 3212 3213 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3214 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3215 3216 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3217 MLX5_SET(sqc, sqc, state, new_state); 3218 3219 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3220 if (new_state != MLX5_SQC_STATE_RDY) 3221 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3222 __func__); 3223 else 3224 new_rl = raw_qp_param->rl; 3225 } 3226 3227 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3228 if (new_rl.rate) { 3229 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3230 if (err) { 3231 pr_err("Failed configuring rate limit(err %d): \ 3232 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3233 err, new_rl.rate, new_rl.max_burst_sz, 3234 new_rl.typical_pkt_sz); 3235 3236 goto out; 3237 } 3238 new_rate_added = true; 3239 } 3240 3241 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3242 /* index 0 means no limit */ 3243 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3244 } 3245 3246 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 3247 if (err) { 3248 /* Remove new rate from table if failed */ 3249 if (new_rate_added) 3250 mlx5_rl_remove_rate(dev, &new_rl); 3251 goto out; 3252 } 3253 3254 /* Only remove the old rate after new rate was set */ 3255 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3256 (new_state != MLX5_SQC_STATE_RDY)) { 3257 mlx5_rl_remove_rate(dev, &old_rl); 3258 if (new_state != MLX5_SQC_STATE_RDY) 3259 memset(&new_rl, 0, sizeof(new_rl)); 3260 } 3261 3262 ibqp->rl = new_rl; 3263 sq->state = new_state; 3264 3265 out: 3266 kvfree(in); 3267 return err; 3268 } 3269 3270 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3271 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3272 u8 tx_affinity) 3273 { 3274 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3275 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3276 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3277 int modify_rq = !!qp->rq.wqe_cnt; 3278 int modify_sq = !!qp->sq.wqe_cnt; 3279 int rq_state; 3280 int sq_state; 3281 int err; 3282 3283 switch (raw_qp_param->operation) { 3284 case MLX5_CMD_OP_RST2INIT_QP: 3285 rq_state = MLX5_RQC_STATE_RDY; 3286 sq_state = MLX5_SQC_STATE_RDY; 3287 break; 3288 case MLX5_CMD_OP_2ERR_QP: 3289 rq_state = MLX5_RQC_STATE_ERR; 3290 sq_state = MLX5_SQC_STATE_ERR; 3291 break; 3292 case MLX5_CMD_OP_2RST_QP: 3293 rq_state = MLX5_RQC_STATE_RST; 3294 sq_state = MLX5_SQC_STATE_RST; 3295 break; 3296 case MLX5_CMD_OP_RTR2RTS_QP: 3297 case MLX5_CMD_OP_RTS2RTS_QP: 3298 if (raw_qp_param->set_mask == 3299 MLX5_RAW_QP_RATE_LIMIT) { 3300 modify_rq = 0; 3301 sq_state = sq->state; 3302 } else { 3303 return raw_qp_param->set_mask ? -EINVAL : 0; 3304 } 3305 break; 3306 case MLX5_CMD_OP_INIT2INIT_QP: 3307 case MLX5_CMD_OP_INIT2RTR_QP: 3308 if (raw_qp_param->set_mask) 3309 return -EINVAL; 3310 else 3311 return 0; 3312 default: 3313 WARN_ON(1); 3314 return -EINVAL; 3315 } 3316 3317 if (modify_rq) { 3318 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3319 qp->ibqp.pd); 3320 if (err) 3321 return err; 3322 } 3323 3324 if (modify_sq) { 3325 struct mlx5_flow_handle *flow_rule; 3326 3327 if (tx_affinity) { 3328 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3329 tx_affinity, 3330 qp->ibqp.pd); 3331 if (err) 3332 return err; 3333 } 3334 3335 flow_rule = create_flow_rule_vport_sq(dev, sq, 3336 raw_qp_param->port); 3337 if (IS_ERR(flow_rule)) 3338 return PTR_ERR(flow_rule); 3339 3340 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3341 raw_qp_param, qp->ibqp.pd); 3342 if (err) { 3343 if (flow_rule) 3344 mlx5_del_flow_rules(flow_rule); 3345 return err; 3346 } 3347 3348 if (flow_rule) { 3349 destroy_flow_rule_vport_sq(sq); 3350 sq->flow_rule = flow_rule; 3351 } 3352 3353 return err; 3354 } 3355 3356 return 0; 3357 } 3358 3359 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, 3360 struct mlx5_ib_pd *pd, 3361 struct mlx5_ib_qp_base *qp_base, 3362 u8 port_num, struct ib_udata *udata) 3363 { 3364 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3365 udata, struct mlx5_ib_ucontext, ibucontext); 3366 unsigned int tx_port_affinity; 3367 3368 if (ucontext) { 3369 tx_port_affinity = (unsigned int)atomic_add_return( 3370 1, &ucontext->tx_port_affinity) % 3371 MLX5_MAX_PORTS + 3372 1; 3373 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3374 tx_port_affinity, qp_base->mqp.qpn, ucontext); 3375 } else { 3376 tx_port_affinity = 3377 (unsigned int)atomic_add_return( 3378 1, &dev->port[port_num].roce.tx_port_affinity) % 3379 MLX5_MAX_PORTS + 3380 1; 3381 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3382 tx_port_affinity, qp_base->mqp.qpn); 3383 } 3384 3385 return tx_port_affinity; 3386 } 3387 3388 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3389 struct rdma_counter *counter) 3390 { 3391 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3392 struct mlx5_ib_qp *mqp = to_mqp(qp); 3393 struct mlx5_qp_context context = {}; 3394 struct mlx5_ib_qp_base *base; 3395 u32 set_id; 3396 3397 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) 3398 return 0; 3399 3400 if (counter) 3401 set_id = counter->id; 3402 else 3403 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3404 3405 base = &mqp->trans_qp.base; 3406 context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff); 3407 context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24); 3408 return mlx5_core_qp_modify(dev->mdev, 3409 MLX5_CMD_OP_RTS2RTS_QP, 3410 MLX5_QP_OPTPAR_COUNTER_SET_ID, 3411 &context, &base->mqp); 3412 } 3413 3414 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3415 const struct ib_qp_attr *attr, int attr_mask, 3416 enum ib_qp_state cur_state, 3417 enum ib_qp_state new_state, 3418 const struct mlx5_ib_modify_qp *ucmd, 3419 struct ib_udata *udata) 3420 { 3421 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3422 [MLX5_QP_STATE_RST] = { 3423 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3424 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3425 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3426 }, 3427 [MLX5_QP_STATE_INIT] = { 3428 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3429 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3430 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3431 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3432 }, 3433 [MLX5_QP_STATE_RTR] = { 3434 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3435 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3436 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3437 }, 3438 [MLX5_QP_STATE_RTS] = { 3439 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3440 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3441 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3442 }, 3443 [MLX5_QP_STATE_SQD] = { 3444 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3445 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3446 }, 3447 [MLX5_QP_STATE_SQER] = { 3448 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3449 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3450 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3451 }, 3452 [MLX5_QP_STATE_ERR] = { 3453 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3454 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3455 } 3456 }; 3457 3458 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3459 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3460 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3461 struct mlx5_ib_cq *send_cq, *recv_cq; 3462 struct mlx5_qp_context *context; 3463 struct mlx5_ib_pd *pd; 3464 enum mlx5_qp_state mlx5_cur, mlx5_new; 3465 enum mlx5_qp_optpar optpar; 3466 u32 set_id = 0; 3467 int mlx5_st; 3468 int err; 3469 u16 op; 3470 u8 tx_affinity = 0; 3471 3472 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3473 qp->qp_sub_type : ibqp->qp_type); 3474 if (mlx5_st < 0) 3475 return -EINVAL; 3476 3477 context = kzalloc(sizeof(*context), GFP_KERNEL); 3478 if (!context) 3479 return -ENOMEM; 3480 3481 pd = get_pd(qp); 3482 context->flags = cpu_to_be32(mlx5_st << 16); 3483 3484 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3485 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3486 } else { 3487 switch (attr->path_mig_state) { 3488 case IB_MIG_MIGRATED: 3489 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3490 break; 3491 case IB_MIG_REARM: 3492 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3493 break; 3494 case IB_MIG_ARMED: 3495 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3496 break; 3497 } 3498 } 3499 3500 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3501 if ((ibqp->qp_type == IB_QPT_RC) || 3502 (ibqp->qp_type == IB_QPT_UD && 3503 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3504 (ibqp->qp_type == IB_QPT_UC) || 3505 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3506 (ibqp->qp_type == IB_QPT_XRC_INI) || 3507 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3508 if (dev->lag_active) { 3509 u8 p = mlx5_core_native_port_num(dev->mdev) - 1; 3510 tx_affinity = get_tx_affinity(dev, pd, base, p, 3511 udata); 3512 context->flags |= cpu_to_be32(tx_affinity << 24); 3513 } 3514 } 3515 } 3516 3517 if (is_sqp(ibqp->qp_type)) { 3518 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3519 } else if ((ibqp->qp_type == IB_QPT_UD && 3520 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3521 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3522 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3523 } else if (attr_mask & IB_QP_PATH_MTU) { 3524 if (attr->path_mtu < IB_MTU_256 || 3525 attr->path_mtu > IB_MTU_4096) { 3526 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3527 err = -EINVAL; 3528 goto out; 3529 } 3530 context->mtu_msgmax = (attr->path_mtu << 5) | 3531 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3532 } 3533 3534 if (attr_mask & IB_QP_DEST_QPN) 3535 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3536 3537 if (attr_mask & IB_QP_PKEY_INDEX) 3538 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3539 3540 /* todo implement counter_index functionality */ 3541 3542 if (is_sqp(ibqp->qp_type)) 3543 context->pri_path.port = qp->port; 3544 3545 if (attr_mask & IB_QP_PORT) 3546 context->pri_path.port = attr->port_num; 3547 3548 if (attr_mask & IB_QP_AV) { 3549 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3550 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3551 attr_mask, 0, attr, false); 3552 if (err) 3553 goto out; 3554 } 3555 3556 if (attr_mask & IB_QP_TIMEOUT) 3557 context->pri_path.ackto_lt |= attr->timeout << 3; 3558 3559 if (attr_mask & IB_QP_ALT_PATH) { 3560 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3561 &context->alt_path, 3562 attr->alt_port_num, 3563 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3564 0, attr, true); 3565 if (err) 3566 goto out; 3567 } 3568 3569 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3570 &send_cq, &recv_cq); 3571 3572 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3573 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3574 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3575 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3576 3577 if (attr_mask & IB_QP_RNR_RETRY) 3578 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3579 3580 if (attr_mask & IB_QP_RETRY_CNT) 3581 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3582 3583 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3584 if (attr->max_rd_atomic) 3585 context->params1 |= 3586 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3587 } 3588 3589 if (attr_mask & IB_QP_SQ_PSN) 3590 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3591 3592 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3593 if (attr->max_dest_rd_atomic) 3594 context->params2 |= 3595 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3596 } 3597 3598 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3599 __be32 access_flags; 3600 3601 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 3602 if (err) 3603 goto out; 3604 3605 context->params2 |= access_flags; 3606 } 3607 3608 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3609 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3610 3611 if (attr_mask & IB_QP_RQ_PSN) 3612 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3613 3614 if (attr_mask & IB_QP_QKEY) 3615 context->qkey = cpu_to_be32(attr->qkey); 3616 3617 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3618 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3619 3620 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3621 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3622 qp->port) - 1; 3623 3624 /* Underlay port should be used - index 0 function per port */ 3625 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3626 port_num = 0; 3627 3628 if (ibqp->counter) 3629 set_id = ibqp->counter->id; 3630 else 3631 set_id = mlx5_ib_get_counters_id(dev, port_num); 3632 context->qp_counter_set_usr_page |= 3633 cpu_to_be32(set_id << 24); 3634 } 3635 3636 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3637 context->sq_crq_size |= cpu_to_be16(1 << 4); 3638 3639 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3640 context->deth_sqpn = cpu_to_be32(1); 3641 3642 mlx5_cur = to_mlx5_state(cur_state); 3643 mlx5_new = to_mlx5_state(new_state); 3644 3645 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3646 !optab[mlx5_cur][mlx5_new]) { 3647 err = -EINVAL; 3648 goto out; 3649 } 3650 3651 op = optab[mlx5_cur][mlx5_new]; 3652 optpar = ib_mask_to_mlx5_opt(attr_mask); 3653 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3654 3655 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3656 qp->flags & MLX5_IB_QP_UNDERLAY) { 3657 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3658 3659 raw_qp_param.operation = op; 3660 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3661 raw_qp_param.rq_q_ctr_id = set_id; 3662 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3663 } 3664 3665 if (attr_mask & IB_QP_PORT) 3666 raw_qp_param.port = attr->port_num; 3667 3668 if (attr_mask & IB_QP_RATE_LIMIT) { 3669 raw_qp_param.rl.rate = attr->rate_limit; 3670 3671 if (ucmd->burst_info.max_burst_sz) { 3672 if (attr->rate_limit && 3673 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3674 raw_qp_param.rl.max_burst_sz = 3675 ucmd->burst_info.max_burst_sz; 3676 } else { 3677 err = -EINVAL; 3678 goto out; 3679 } 3680 } 3681 3682 if (ucmd->burst_info.typical_pkt_sz) { 3683 if (attr->rate_limit && 3684 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3685 raw_qp_param.rl.typical_pkt_sz = 3686 ucmd->burst_info.typical_pkt_sz; 3687 } else { 3688 err = -EINVAL; 3689 goto out; 3690 } 3691 } 3692 3693 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3694 } 3695 3696 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3697 } else { 3698 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3699 &base->mqp); 3700 } 3701 3702 if (err) 3703 goto out; 3704 3705 qp->state = new_state; 3706 3707 if (attr_mask & IB_QP_ACCESS_FLAGS) 3708 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3709 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3710 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3711 if (attr_mask & IB_QP_PORT) 3712 qp->port = attr->port_num; 3713 if (attr_mask & IB_QP_ALT_PATH) 3714 qp->trans_qp.alt_port = attr->alt_port_num; 3715 3716 /* 3717 * If we moved a kernel QP to RESET, clean up all old CQ 3718 * entries and reinitialize the QP. 3719 */ 3720 if (new_state == IB_QPS_RESET && 3721 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3722 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3723 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3724 if (send_cq != recv_cq) 3725 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3726 3727 qp->rq.head = 0; 3728 qp->rq.tail = 0; 3729 qp->sq.head = 0; 3730 qp->sq.tail = 0; 3731 qp->sq.cur_post = 0; 3732 if (qp->sq.wqe_cnt) 3733 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 3734 qp->db.db[MLX5_RCV_DBR] = 0; 3735 qp->db.db[MLX5_SND_DBR] = 0; 3736 } 3737 3738 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 3739 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 3740 if (!err) 3741 qp->counter_pending = 0; 3742 } 3743 3744 out: 3745 kfree(context); 3746 return err; 3747 } 3748 3749 static inline bool is_valid_mask(int mask, int req, int opt) 3750 { 3751 if ((mask & req) != req) 3752 return false; 3753 3754 if (mask & ~(req | opt)) 3755 return false; 3756 3757 return true; 3758 } 3759 3760 /* check valid transition for driver QP types 3761 * for now the only QP type that this function supports is DCI 3762 */ 3763 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3764 enum ib_qp_attr_mask attr_mask) 3765 { 3766 int req = IB_QP_STATE; 3767 int opt = 0; 3768 3769 if (new_state == IB_QPS_RESET) { 3770 return is_valid_mask(attr_mask, req, opt); 3771 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3772 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3773 return is_valid_mask(attr_mask, req, opt); 3774 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3775 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3776 return is_valid_mask(attr_mask, req, opt); 3777 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3778 req |= IB_QP_PATH_MTU; 3779 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 3780 return is_valid_mask(attr_mask, req, opt); 3781 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3782 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3783 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3784 opt = IB_QP_MIN_RNR_TIMER; 3785 return is_valid_mask(attr_mask, req, opt); 3786 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3787 opt = IB_QP_MIN_RNR_TIMER; 3788 return is_valid_mask(attr_mask, req, opt); 3789 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3790 return is_valid_mask(attr_mask, req, opt); 3791 } 3792 return false; 3793 } 3794 3795 /* mlx5_ib_modify_dct: modify a DCT QP 3796 * valid transitions are: 3797 * RESET to INIT: must set access_flags, pkey_index and port 3798 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3799 * mtu, gid_index and hop_limit 3800 * Other transitions and attributes are illegal 3801 */ 3802 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3803 int attr_mask, struct ib_udata *udata) 3804 { 3805 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3806 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3807 enum ib_qp_state cur_state, new_state; 3808 int err = 0; 3809 int required = IB_QP_STATE; 3810 void *dctc; 3811 3812 if (!(attr_mask & IB_QP_STATE)) 3813 return -EINVAL; 3814 3815 cur_state = qp->state; 3816 new_state = attr->qp_state; 3817 3818 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3819 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3820 u16 set_id; 3821 3822 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3823 if (!is_valid_mask(attr_mask, required, 0)) 3824 return -EINVAL; 3825 3826 if (attr->port_num == 0 || 3827 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3828 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3829 attr->port_num, dev->num_ports); 3830 return -EINVAL; 3831 } 3832 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3833 MLX5_SET(dctc, dctc, rre, 1); 3834 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3835 MLX5_SET(dctc, dctc, rwe, 1); 3836 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3837 int atomic_mode; 3838 3839 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 3840 if (atomic_mode < 0) 3841 return -EOPNOTSUPP; 3842 3843 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 3844 MLX5_SET(dctc, dctc, rae, 1); 3845 } 3846 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3847 MLX5_SET(dctc, dctc, port, attr->port_num); 3848 3849 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 3850 MLX5_SET(dctc, dctc, counter_set_id, set_id); 3851 3852 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3853 struct mlx5_ib_modify_qp_resp resp = {}; 3854 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0}; 3855 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3856 sizeof(resp.dctn); 3857 3858 if (udata->outlen < min_resp_len) 3859 return -EINVAL; 3860 resp.response_length = min_resp_len; 3861 3862 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3863 if (!is_valid_mask(attr_mask, required, 0)) 3864 return -EINVAL; 3865 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3866 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3867 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3868 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3869 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3870 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3871 3872 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3873 MLX5_ST_SZ_BYTES(create_dct_in), out, 3874 sizeof(out)); 3875 if (err) 3876 return err; 3877 resp.dctn = qp->dct.mdct.mqp.qpn; 3878 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3879 if (err) { 3880 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3881 return err; 3882 } 3883 } else { 3884 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3885 return -EINVAL; 3886 } 3887 if (err) 3888 qp->state = IB_QPS_ERR; 3889 else 3890 qp->state = new_state; 3891 return err; 3892 } 3893 3894 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3895 int attr_mask, struct ib_udata *udata) 3896 { 3897 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3898 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3899 struct mlx5_ib_modify_qp ucmd = {}; 3900 enum ib_qp_type qp_type; 3901 enum ib_qp_state cur_state, new_state; 3902 size_t required_cmd_sz; 3903 int err = -EINVAL; 3904 int port; 3905 3906 if (ibqp->rwq_ind_tbl) 3907 return -ENOSYS; 3908 3909 if (udata && udata->inlen) { 3910 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3911 sizeof(ucmd.reserved); 3912 if (udata->inlen < required_cmd_sz) 3913 return -EINVAL; 3914 3915 if (udata->inlen > sizeof(ucmd) && 3916 !ib_is_udata_cleared(udata, sizeof(ucmd), 3917 udata->inlen - sizeof(ucmd))) 3918 return -EOPNOTSUPP; 3919 3920 if (ib_copy_from_udata(&ucmd, udata, 3921 min(udata->inlen, sizeof(ucmd)))) 3922 return -EFAULT; 3923 3924 if (ucmd.comp_mask || 3925 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3926 memchr_inv(&ucmd.burst_info.reserved, 0, 3927 sizeof(ucmd.burst_info.reserved))) 3928 return -EOPNOTSUPP; 3929 } 3930 3931 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3932 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3933 3934 if (ibqp->qp_type == IB_QPT_DRIVER) 3935 qp_type = qp->qp_sub_type; 3936 else 3937 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3938 IB_QPT_GSI : ibqp->qp_type; 3939 3940 if (qp_type == MLX5_IB_QPT_DCT) 3941 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3942 3943 mutex_lock(&qp->mutex); 3944 3945 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3946 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3947 3948 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3949 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3950 } 3951 3952 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3953 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3954 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3955 attr_mask); 3956 goto out; 3957 } 3958 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3959 qp_type != MLX5_IB_QPT_DCI && 3960 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 3961 attr_mask)) { 3962 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3963 cur_state, new_state, ibqp->qp_type, attr_mask); 3964 goto out; 3965 } else if (qp_type == MLX5_IB_QPT_DCI && 3966 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3967 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3968 cur_state, new_state, qp_type, attr_mask); 3969 goto out; 3970 } 3971 3972 if ((attr_mask & IB_QP_PORT) && 3973 (attr->port_num == 0 || 3974 attr->port_num > dev->num_ports)) { 3975 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3976 attr->port_num, dev->num_ports); 3977 goto out; 3978 } 3979 3980 if (attr_mask & IB_QP_PKEY_INDEX) { 3981 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3982 if (attr->pkey_index >= 3983 dev->mdev->port_caps[port - 1].pkey_table_len) { 3984 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3985 attr->pkey_index); 3986 goto out; 3987 } 3988 } 3989 3990 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3991 attr->max_rd_atomic > 3992 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3993 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3994 attr->max_rd_atomic); 3995 goto out; 3996 } 3997 3998 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3999 attr->max_dest_rd_atomic > 4000 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4001 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4002 attr->max_dest_rd_atomic); 4003 goto out; 4004 } 4005 4006 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4007 err = 0; 4008 goto out; 4009 } 4010 4011 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4012 new_state, &ucmd, udata); 4013 4014 out: 4015 mutex_unlock(&qp->mutex); 4016 return err; 4017 } 4018 4019 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 4020 u32 wqe_sz, void **cur_edge) 4021 { 4022 u32 idx; 4023 4024 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); 4025 *cur_edge = get_sq_edge(sq, idx); 4026 4027 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); 4028 } 4029 4030 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the 4031 * next nearby edge and get new address translation for current WQE position. 4032 * @sq - SQ buffer. 4033 * @seg: Current WQE position (16B aligned). 4034 * @wqe_sz: Total current WQE size [16B]. 4035 * @cur_edge: Updated current edge. 4036 */ 4037 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 4038 u32 wqe_sz, void **cur_edge) 4039 { 4040 if (likely(*seg != *cur_edge)) 4041 return; 4042 4043 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); 4044 } 4045 4046 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's 4047 * pointers. At the end @seg is aligned to 16B regardless the copied size. 4048 * @sq - SQ buffer. 4049 * @cur_edge: Updated current edge. 4050 * @seg: Current WQE position (16B aligned). 4051 * @wqe_sz: Total current WQE size [16B]. 4052 * @src: Pointer to copy from. 4053 * @n: Number of bytes to copy. 4054 */ 4055 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, 4056 void **seg, u32 *wqe_sz, const void *src, 4057 size_t n) 4058 { 4059 while (likely(n)) { 4060 size_t leftlen = *cur_edge - *seg; 4061 size_t copysz = min_t(size_t, leftlen, n); 4062 size_t stride; 4063 4064 memcpy(*seg, src, copysz); 4065 4066 n -= copysz; 4067 src += copysz; 4068 stride = !n ? ALIGN(copysz, 16) : copysz; 4069 *seg += stride; 4070 *wqe_sz += stride >> 4; 4071 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); 4072 } 4073 } 4074 4075 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 4076 { 4077 struct mlx5_ib_cq *cq; 4078 unsigned cur; 4079 4080 cur = wq->head - wq->tail; 4081 if (likely(cur + nreq < wq->max_post)) 4082 return 0; 4083 4084 cq = to_mcq(ib_cq); 4085 spin_lock(&cq->lock); 4086 cur = wq->head - wq->tail; 4087 spin_unlock(&cq->lock); 4088 4089 return cur + nreq >= wq->max_post; 4090 } 4091 4092 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 4093 u64 remote_addr, u32 rkey) 4094 { 4095 rseg->raddr = cpu_to_be64(remote_addr); 4096 rseg->rkey = cpu_to_be32(rkey); 4097 rseg->reserved = 0; 4098 } 4099 4100 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 4101 void **seg, int *size, void **cur_edge) 4102 { 4103 struct mlx5_wqe_eth_seg *eseg = *seg; 4104 4105 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 4106 4107 if (wr->send_flags & IB_SEND_IP_CSUM) 4108 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 4109 MLX5_ETH_WQE_L4_CSUM; 4110 4111 if (wr->opcode == IB_WR_LSO) { 4112 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 4113 size_t left, copysz; 4114 void *pdata = ud_wr->header; 4115 size_t stride; 4116 4117 left = ud_wr->hlen; 4118 eseg->mss = cpu_to_be16(ud_wr->mss); 4119 eseg->inline_hdr.sz = cpu_to_be16(left); 4120 4121 /* memcpy_send_wqe should get a 16B align address. Hence, we 4122 * first copy up to the current edge and then, if needed, 4123 * fall-through to memcpy_send_wqe. 4124 */ 4125 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, 4126 left); 4127 memcpy(eseg->inline_hdr.start, pdata, copysz); 4128 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - 4129 sizeof(eseg->inline_hdr.start) + copysz, 16); 4130 *size += stride / 16; 4131 *seg += stride; 4132 4133 if (copysz < left) { 4134 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4135 left -= copysz; 4136 pdata += copysz; 4137 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, 4138 left); 4139 } 4140 4141 return; 4142 } 4143 4144 *seg += sizeof(struct mlx5_wqe_eth_seg); 4145 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 4146 } 4147 4148 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 4149 const struct ib_send_wr *wr) 4150 { 4151 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 4152 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 4153 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 4154 } 4155 4156 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 4157 { 4158 dseg->byte_count = cpu_to_be32(sg->length); 4159 dseg->lkey = cpu_to_be32(sg->lkey); 4160 dseg->addr = cpu_to_be64(sg->addr); 4161 } 4162 4163 static u64 get_xlt_octo(u64 bytes) 4164 { 4165 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 4166 MLX5_IB_UMR_OCTOWORD; 4167 } 4168 4169 static __be64 frwr_mkey_mask(bool atomic) 4170 { 4171 u64 result; 4172 4173 result = MLX5_MKEY_MASK_LEN | 4174 MLX5_MKEY_MASK_PAGE_SIZE | 4175 MLX5_MKEY_MASK_START_ADDR | 4176 MLX5_MKEY_MASK_EN_RINVAL | 4177 MLX5_MKEY_MASK_KEY | 4178 MLX5_MKEY_MASK_LR | 4179 MLX5_MKEY_MASK_LW | 4180 MLX5_MKEY_MASK_RR | 4181 MLX5_MKEY_MASK_RW | 4182 MLX5_MKEY_MASK_SMALL_FENCE | 4183 MLX5_MKEY_MASK_FREE; 4184 4185 if (atomic) 4186 result |= MLX5_MKEY_MASK_A; 4187 4188 return cpu_to_be64(result); 4189 } 4190 4191 static __be64 sig_mkey_mask(void) 4192 { 4193 u64 result; 4194 4195 result = MLX5_MKEY_MASK_LEN | 4196 MLX5_MKEY_MASK_PAGE_SIZE | 4197 MLX5_MKEY_MASK_START_ADDR | 4198 MLX5_MKEY_MASK_EN_SIGERR | 4199 MLX5_MKEY_MASK_EN_RINVAL | 4200 MLX5_MKEY_MASK_KEY | 4201 MLX5_MKEY_MASK_LR | 4202 MLX5_MKEY_MASK_LW | 4203 MLX5_MKEY_MASK_RR | 4204 MLX5_MKEY_MASK_RW | 4205 MLX5_MKEY_MASK_SMALL_FENCE | 4206 MLX5_MKEY_MASK_FREE | 4207 MLX5_MKEY_MASK_BSF_EN; 4208 4209 return cpu_to_be64(result); 4210 } 4211 4212 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 4213 struct mlx5_ib_mr *mr, u8 flags, bool atomic) 4214 { 4215 int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size; 4216 4217 memset(umr, 0, sizeof(*umr)); 4218 4219 umr->flags = flags; 4220 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4221 umr->mkey_mask = frwr_mkey_mask(atomic); 4222 } 4223 4224 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 4225 { 4226 memset(umr, 0, sizeof(*umr)); 4227 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 4228 umr->flags = MLX5_UMR_INLINE; 4229 } 4230 4231 static __be64 get_umr_enable_mr_mask(void) 4232 { 4233 u64 result; 4234 4235 result = MLX5_MKEY_MASK_KEY | 4236 MLX5_MKEY_MASK_FREE; 4237 4238 return cpu_to_be64(result); 4239 } 4240 4241 static __be64 get_umr_disable_mr_mask(void) 4242 { 4243 u64 result; 4244 4245 result = MLX5_MKEY_MASK_FREE; 4246 4247 return cpu_to_be64(result); 4248 } 4249 4250 static __be64 get_umr_update_translation_mask(void) 4251 { 4252 u64 result; 4253 4254 result = MLX5_MKEY_MASK_LEN | 4255 MLX5_MKEY_MASK_PAGE_SIZE | 4256 MLX5_MKEY_MASK_START_ADDR; 4257 4258 return cpu_to_be64(result); 4259 } 4260 4261 static __be64 get_umr_update_access_mask(int atomic) 4262 { 4263 u64 result; 4264 4265 result = MLX5_MKEY_MASK_LR | 4266 MLX5_MKEY_MASK_LW | 4267 MLX5_MKEY_MASK_RR | 4268 MLX5_MKEY_MASK_RW; 4269 4270 if (atomic) 4271 result |= MLX5_MKEY_MASK_A; 4272 4273 return cpu_to_be64(result); 4274 } 4275 4276 static __be64 get_umr_update_pd_mask(void) 4277 { 4278 u64 result; 4279 4280 result = MLX5_MKEY_MASK_PD; 4281 4282 return cpu_to_be64(result); 4283 } 4284 4285 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 4286 { 4287 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 4288 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 4289 (mask & MLX5_MKEY_MASK_A && 4290 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 4291 return -EPERM; 4292 return 0; 4293 } 4294 4295 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 4296 struct mlx5_wqe_umr_ctrl_seg *umr, 4297 const struct ib_send_wr *wr, int atomic) 4298 { 4299 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4300 4301 memset(umr, 0, sizeof(*umr)); 4302 4303 if (!umrwr->ignore_free_state) { 4304 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 4305 /* fail if free */ 4306 umr->flags = MLX5_UMR_CHECK_FREE; 4307 else 4308 /* fail if not free */ 4309 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 4310 } 4311 4312 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 4313 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 4314 u64 offset = get_xlt_octo(umrwr->offset); 4315 4316 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 4317 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 4318 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 4319 } 4320 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 4321 umr->mkey_mask |= get_umr_update_translation_mask(); 4322 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 4323 umr->mkey_mask |= get_umr_update_access_mask(atomic); 4324 umr->mkey_mask |= get_umr_update_pd_mask(); 4325 } 4326 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 4327 umr->mkey_mask |= get_umr_enable_mr_mask(); 4328 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4329 umr->mkey_mask |= get_umr_disable_mr_mask(); 4330 4331 if (!wr->num_sge) 4332 umr->flags |= MLX5_UMR_INLINE; 4333 4334 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 4335 } 4336 4337 static u8 get_umr_flags(int acc) 4338 { 4339 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 4340 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 4341 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 4342 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 4343 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 4344 } 4345 4346 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 4347 struct mlx5_ib_mr *mr, 4348 u32 key, int access) 4349 { 4350 int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1; 4351 4352 memset(seg, 0, sizeof(*seg)); 4353 4354 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 4355 seg->log2_page_size = ilog2(mr->ibmr.page_size); 4356 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 4357 /* KLMs take twice the size of MTTs */ 4358 ndescs *= 2; 4359 4360 seg->flags = get_umr_flags(access) | mr->access_mode; 4361 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 4362 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 4363 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 4364 seg->len = cpu_to_be64(mr->ibmr.length); 4365 seg->xlt_oct_size = cpu_to_be32(ndescs); 4366 } 4367 4368 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 4369 { 4370 memset(seg, 0, sizeof(*seg)); 4371 seg->status = MLX5_MKEY_STATUS_FREE; 4372 } 4373 4374 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, 4375 const struct ib_send_wr *wr) 4376 { 4377 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4378 4379 memset(seg, 0, sizeof(*seg)); 4380 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4381 seg->status = MLX5_MKEY_STATUS_FREE; 4382 4383 seg->flags = convert_access(umrwr->access_flags); 4384 if (umrwr->pd) 4385 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 4386 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 4387 !umrwr->length) 4388 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 4389 4390 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 4391 seg->len = cpu_to_be64(umrwr->length); 4392 seg->log2_page_size = umrwr->page_shift; 4393 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 4394 mlx5_mkey_variant(umrwr->mkey)); 4395 } 4396 4397 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 4398 struct mlx5_ib_mr *mr, 4399 struct mlx5_ib_pd *pd) 4400 { 4401 int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs); 4402 4403 dseg->addr = cpu_to_be64(mr->desc_map); 4404 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 4405 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 4406 } 4407 4408 static __be32 send_ieth(const struct ib_send_wr *wr) 4409 { 4410 switch (wr->opcode) { 4411 case IB_WR_SEND_WITH_IMM: 4412 case IB_WR_RDMA_WRITE_WITH_IMM: 4413 return wr->ex.imm_data; 4414 4415 case IB_WR_SEND_WITH_INV: 4416 return cpu_to_be32(wr->ex.invalidate_rkey); 4417 4418 default: 4419 return 0; 4420 } 4421 } 4422 4423 static u8 calc_sig(void *wqe, int size) 4424 { 4425 u8 *p = wqe; 4426 u8 res = 0; 4427 int i; 4428 4429 for (i = 0; i < size; i++) 4430 res ^= p[i]; 4431 4432 return ~res; 4433 } 4434 4435 static u8 wq_sig(void *wqe) 4436 { 4437 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 4438 } 4439 4440 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 4441 void **wqe, int *wqe_sz, void **cur_edge) 4442 { 4443 struct mlx5_wqe_inline_seg *seg; 4444 size_t offset; 4445 int inl = 0; 4446 int i; 4447 4448 seg = *wqe; 4449 *wqe += sizeof(*seg); 4450 offset = sizeof(*seg); 4451 4452 for (i = 0; i < wr->num_sge; i++) { 4453 size_t len = wr->sg_list[i].length; 4454 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); 4455 4456 inl += len; 4457 4458 if (unlikely(inl > qp->max_inline_data)) 4459 return -ENOMEM; 4460 4461 while (likely(len)) { 4462 size_t leftlen; 4463 size_t copysz; 4464 4465 handle_post_send_edge(&qp->sq, wqe, 4466 *wqe_sz + (offset >> 4), 4467 cur_edge); 4468 4469 leftlen = *cur_edge - *wqe; 4470 copysz = min_t(size_t, leftlen, len); 4471 4472 memcpy(*wqe, addr, copysz); 4473 len -= copysz; 4474 addr += copysz; 4475 *wqe += copysz; 4476 offset += copysz; 4477 } 4478 } 4479 4480 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 4481 4482 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 4483 4484 return 0; 4485 } 4486 4487 static u16 prot_field_size(enum ib_signature_type type) 4488 { 4489 switch (type) { 4490 case IB_SIG_TYPE_T10_DIF: 4491 return MLX5_DIF_SIZE; 4492 default: 4493 return 0; 4494 } 4495 } 4496 4497 static u8 bs_selector(int block_size) 4498 { 4499 switch (block_size) { 4500 case 512: return 0x1; 4501 case 520: return 0x2; 4502 case 4096: return 0x3; 4503 case 4160: return 0x4; 4504 case 1073741824: return 0x5; 4505 default: return 0; 4506 } 4507 } 4508 4509 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 4510 struct mlx5_bsf_inl *inl) 4511 { 4512 /* Valid inline section and allow BSF refresh */ 4513 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 4514 MLX5_BSF_REFRESH_DIF); 4515 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 4516 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 4517 /* repeating block */ 4518 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 4519 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 4520 MLX5_DIF_CRC : MLX5_DIF_IPCS; 4521 4522 if (domain->sig.dif.ref_remap) 4523 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 4524 4525 if (domain->sig.dif.app_escape) { 4526 if (domain->sig.dif.ref_escape) 4527 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 4528 else 4529 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 4530 } 4531 4532 inl->dif_app_bitmask_check = 4533 cpu_to_be16(domain->sig.dif.apptag_check_mask); 4534 } 4535 4536 static int mlx5_set_bsf(struct ib_mr *sig_mr, 4537 struct ib_sig_attrs *sig_attrs, 4538 struct mlx5_bsf *bsf, u32 data_size) 4539 { 4540 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 4541 struct mlx5_bsf_basic *basic = &bsf->basic; 4542 struct ib_sig_domain *mem = &sig_attrs->mem; 4543 struct ib_sig_domain *wire = &sig_attrs->wire; 4544 4545 memset(bsf, 0, sizeof(*bsf)); 4546 4547 /* Basic + Extended + Inline */ 4548 basic->bsf_size_sbs = 1 << 7; 4549 /* Input domain check byte mask */ 4550 basic->check_byte_mask = sig_attrs->check_mask; 4551 basic->raw_data_size = cpu_to_be32(data_size); 4552 4553 /* Memory domain */ 4554 switch (sig_attrs->mem.sig_type) { 4555 case IB_SIG_TYPE_NONE: 4556 break; 4557 case IB_SIG_TYPE_T10_DIF: 4558 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4559 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4560 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4561 break; 4562 default: 4563 return -EINVAL; 4564 } 4565 4566 /* Wire domain */ 4567 switch (sig_attrs->wire.sig_type) { 4568 case IB_SIG_TYPE_NONE: 4569 break; 4570 case IB_SIG_TYPE_T10_DIF: 4571 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4572 mem->sig_type == wire->sig_type) { 4573 /* Same block structure */ 4574 basic->bsf_size_sbs |= 1 << 4; 4575 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4576 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4577 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4578 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4579 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4580 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4581 } else 4582 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4583 4584 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4585 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4586 break; 4587 default: 4588 return -EINVAL; 4589 } 4590 4591 return 0; 4592 } 4593 4594 static int set_sig_data_segment(const struct ib_send_wr *send_wr, 4595 struct ib_mr *sig_mr, 4596 struct ib_sig_attrs *sig_attrs, 4597 struct mlx5_ib_qp *qp, void **seg, int *size, 4598 void **cur_edge) 4599 { 4600 struct mlx5_bsf *bsf; 4601 u32 data_len; 4602 u32 data_key; 4603 u64 data_va; 4604 u32 prot_len = 0; 4605 u32 prot_key = 0; 4606 u64 prot_va = 0; 4607 bool prot = false; 4608 int ret; 4609 int wqe_size; 4610 struct mlx5_ib_mr *mr = to_mmr(sig_mr); 4611 struct mlx5_ib_mr *pi_mr = mr->pi_mr; 4612 4613 data_len = pi_mr->data_length; 4614 data_key = pi_mr->ibmr.lkey; 4615 data_va = pi_mr->data_iova; 4616 if (pi_mr->meta_ndescs) { 4617 prot_len = pi_mr->meta_length; 4618 prot_key = pi_mr->ibmr.lkey; 4619 prot_va = pi_mr->pi_iova; 4620 prot = true; 4621 } 4622 4623 if (!prot || (data_key == prot_key && data_va == prot_va && 4624 data_len == prot_len)) { 4625 /** 4626 * Source domain doesn't contain signature information 4627 * or data and protection are interleaved in memory. 4628 * So need construct: 4629 * ------------------ 4630 * | data_klm | 4631 * ------------------ 4632 * | BSF | 4633 * ------------------ 4634 **/ 4635 struct mlx5_klm *data_klm = *seg; 4636 4637 data_klm->bcount = cpu_to_be32(data_len); 4638 data_klm->key = cpu_to_be32(data_key); 4639 data_klm->va = cpu_to_be64(data_va); 4640 wqe_size = ALIGN(sizeof(*data_klm), 64); 4641 } else { 4642 /** 4643 * Source domain contains signature information 4644 * So need construct a strided block format: 4645 * --------------------------- 4646 * | stride_block_ctrl | 4647 * --------------------------- 4648 * | data_klm | 4649 * --------------------------- 4650 * | prot_klm | 4651 * --------------------------- 4652 * | BSF | 4653 * --------------------------- 4654 **/ 4655 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4656 struct mlx5_stride_block_entry *data_sentry; 4657 struct mlx5_stride_block_entry *prot_sentry; 4658 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4659 int prot_size; 4660 4661 sblock_ctrl = *seg; 4662 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4663 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4664 4665 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4666 if (!prot_size) { 4667 pr_err("Bad block size given: %u\n", block_size); 4668 return -EINVAL; 4669 } 4670 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4671 prot_size); 4672 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4673 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4674 sblock_ctrl->num_entries = cpu_to_be16(2); 4675 4676 data_sentry->bcount = cpu_to_be16(block_size); 4677 data_sentry->key = cpu_to_be32(data_key); 4678 data_sentry->va = cpu_to_be64(data_va); 4679 data_sentry->stride = cpu_to_be16(block_size); 4680 4681 prot_sentry->bcount = cpu_to_be16(prot_size); 4682 prot_sentry->key = cpu_to_be32(prot_key); 4683 prot_sentry->va = cpu_to_be64(prot_va); 4684 prot_sentry->stride = cpu_to_be16(prot_size); 4685 4686 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4687 sizeof(*prot_sentry), 64); 4688 } 4689 4690 *seg += wqe_size; 4691 *size += wqe_size / 16; 4692 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4693 4694 bsf = *seg; 4695 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4696 if (ret) 4697 return -EINVAL; 4698 4699 *seg += sizeof(*bsf); 4700 *size += sizeof(*bsf) / 16; 4701 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4702 4703 return 0; 4704 } 4705 4706 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4707 struct ib_mr *sig_mr, int access_flags, 4708 u32 size, u32 length, u32 pdn) 4709 { 4710 u32 sig_key = sig_mr->rkey; 4711 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4712 4713 memset(seg, 0, sizeof(*seg)); 4714 4715 seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS; 4716 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4717 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4718 MLX5_MKEY_BSF_EN | pdn); 4719 seg->len = cpu_to_be64(length); 4720 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4721 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4722 } 4723 4724 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4725 u32 size) 4726 { 4727 memset(umr, 0, sizeof(*umr)); 4728 4729 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4730 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4731 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4732 umr->mkey_mask = sig_mkey_mask(); 4733 } 4734 4735 static int set_pi_umr_wr(const struct ib_send_wr *send_wr, 4736 struct mlx5_ib_qp *qp, void **seg, int *size, 4737 void **cur_edge) 4738 { 4739 const struct ib_reg_wr *wr = reg_wr(send_wr); 4740 struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr); 4741 struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr; 4742 struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs; 4743 u32 pdn = get_pd(qp)->pdn; 4744 u32 xlt_size; 4745 int region_len, ret; 4746 4747 if (unlikely(send_wr->num_sge != 0) || 4748 unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) || 4749 unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) || 4750 unlikely(!sig_mr->sig->sig_status_checked)) 4751 return -EINVAL; 4752 4753 /* length of the protected region, data + protection */ 4754 region_len = pi_mr->ibmr.length; 4755 4756 /** 4757 * KLM octoword size - if protection was provided 4758 * then we use strided block format (3 octowords), 4759 * else we use single KLM (1 octoword) 4760 **/ 4761 if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE) 4762 xlt_size = 0x30; 4763 else 4764 xlt_size = sizeof(struct mlx5_klm); 4765 4766 set_sig_umr_segment(*seg, xlt_size); 4767 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4768 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4769 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4770 4771 set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len, 4772 pdn); 4773 *seg += sizeof(struct mlx5_mkey_seg); 4774 *size += sizeof(struct mlx5_mkey_seg) / 16; 4775 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4776 4777 ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size, 4778 cur_edge); 4779 if (ret) 4780 return ret; 4781 4782 sig_mr->sig->sig_status_checked = false; 4783 return 0; 4784 } 4785 4786 static int set_psv_wr(struct ib_sig_domain *domain, 4787 u32 psv_idx, void **seg, int *size) 4788 { 4789 struct mlx5_seg_set_psv *psv_seg = *seg; 4790 4791 memset(psv_seg, 0, sizeof(*psv_seg)); 4792 psv_seg->psv_num = cpu_to_be32(psv_idx); 4793 switch (domain->sig_type) { 4794 case IB_SIG_TYPE_NONE: 4795 break; 4796 case IB_SIG_TYPE_T10_DIF: 4797 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4798 domain->sig.dif.app_tag); 4799 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4800 break; 4801 default: 4802 pr_err("Bad signature type (%d) is given.\n", 4803 domain->sig_type); 4804 return -EINVAL; 4805 } 4806 4807 *seg += sizeof(*psv_seg); 4808 *size += sizeof(*psv_seg) / 16; 4809 4810 return 0; 4811 } 4812 4813 static int set_reg_wr(struct mlx5_ib_qp *qp, 4814 const struct ib_reg_wr *wr, 4815 void **seg, int *size, void **cur_edge, 4816 bool check_not_free) 4817 { 4818 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4819 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4820 struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device); 4821 int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size; 4822 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4823 bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC; 4824 u8 flags = 0; 4825 4826 if (!mlx5_ib_can_use_umr(dev, atomic)) { 4827 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4828 "Fast update of %s for MR is disabled\n", 4829 (MLX5_CAP_GEN(dev->mdev, 4830 umr_modify_entity_size_disabled)) ? 4831 "entity size" : 4832 "atomic access"); 4833 return -EINVAL; 4834 } 4835 4836 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4837 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4838 "Invalid IB_SEND_INLINE send flag\n"); 4839 return -EINVAL; 4840 } 4841 4842 if (check_not_free) 4843 flags |= MLX5_UMR_CHECK_NOT_FREE; 4844 if (umr_inline) 4845 flags |= MLX5_UMR_INLINE; 4846 4847 set_reg_umr_seg(*seg, mr, flags, atomic); 4848 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4849 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4850 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4851 4852 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4853 *seg += sizeof(struct mlx5_mkey_seg); 4854 *size += sizeof(struct mlx5_mkey_seg) / 16; 4855 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4856 4857 if (umr_inline) { 4858 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, 4859 mr_list_size); 4860 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); 4861 } else { 4862 set_reg_data_seg(*seg, mr, pd); 4863 *seg += sizeof(struct mlx5_wqe_data_seg); 4864 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4865 } 4866 return 0; 4867 } 4868 4869 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, 4870 void **cur_edge) 4871 { 4872 set_linv_umr_seg(*seg); 4873 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4874 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4875 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4876 set_linv_mkey_seg(*seg); 4877 *seg += sizeof(struct mlx5_mkey_seg); 4878 *size += sizeof(struct mlx5_mkey_seg) / 16; 4879 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4880 } 4881 4882 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) 4883 { 4884 __be32 *p = NULL; 4885 int i, j; 4886 4887 pr_debug("dump WQE index %u:\n", idx); 4888 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4889 if ((i & 0xf) == 0) { 4890 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx); 4891 pr_debug("WQBB at %p:\n", (void *)p); 4892 j = 0; 4893 idx = (idx + 1) & (qp->sq.wqe_cnt - 1); 4894 } 4895 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4896 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4897 be32_to_cpu(p[j + 3])); 4898 } 4899 } 4900 4901 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4902 struct mlx5_wqe_ctrl_seg **ctrl, 4903 const struct ib_send_wr *wr, unsigned int *idx, 4904 int *size, void **cur_edge, int nreq, 4905 bool send_signaled, bool solicited) 4906 { 4907 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4908 return -ENOMEM; 4909 4910 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4911 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); 4912 *ctrl = *seg; 4913 *(uint32_t *)(*seg + 8) = 0; 4914 (*ctrl)->imm = send_ieth(wr); 4915 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4916 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4917 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 4918 4919 *seg += sizeof(**ctrl); 4920 *size = sizeof(**ctrl) / 16; 4921 *cur_edge = qp->sq.cur_edge; 4922 4923 return 0; 4924 } 4925 4926 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4927 struct mlx5_wqe_ctrl_seg **ctrl, 4928 const struct ib_send_wr *wr, unsigned *idx, 4929 int *size, void **cur_edge, int nreq) 4930 { 4931 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, 4932 wr->send_flags & IB_SEND_SIGNALED, 4933 wr->send_flags & IB_SEND_SOLICITED); 4934 } 4935 4936 static void finish_wqe(struct mlx5_ib_qp *qp, 4937 struct mlx5_wqe_ctrl_seg *ctrl, 4938 void *seg, u8 size, void *cur_edge, 4939 unsigned int idx, u64 wr_id, int nreq, u8 fence, 4940 u32 mlx5_opcode) 4941 { 4942 u8 opmod = 0; 4943 4944 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4945 mlx5_opcode | ((u32)opmod << 24)); 4946 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4947 ctrl->fm_ce_se |= fence; 4948 if (unlikely(qp->wq_sig)) 4949 ctrl->signature = wq_sig(ctrl); 4950 4951 qp->sq.wrid[idx] = wr_id; 4952 qp->sq.w_list[idx].opcode = mlx5_opcode; 4953 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4954 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4955 qp->sq.w_list[idx].next = qp->sq.cur_post; 4956 4957 /* We save the edge which was possibly updated during the WQE 4958 * construction, into SQ's cache. 4959 */ 4960 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); 4961 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? 4962 get_sq_edge(&qp->sq, qp->sq.cur_post & 4963 (qp->sq.wqe_cnt - 1)) : 4964 cur_edge; 4965 } 4966 4967 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 4968 const struct ib_send_wr **bad_wr, bool drain) 4969 { 4970 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4971 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4972 struct mlx5_core_dev *mdev = dev->mdev; 4973 struct ib_reg_wr reg_pi_wr; 4974 struct mlx5_ib_qp *qp; 4975 struct mlx5_ib_mr *mr; 4976 struct mlx5_ib_mr *pi_mr; 4977 struct mlx5_ib_mr pa_pi_mr; 4978 struct ib_sig_attrs *sig_attrs; 4979 struct mlx5_wqe_xrc_seg *xrc; 4980 struct mlx5_bf *bf; 4981 void *cur_edge; 4982 int uninitialized_var(size); 4983 unsigned long flags; 4984 unsigned idx; 4985 int err = 0; 4986 int num_sge; 4987 void *seg; 4988 int nreq; 4989 int i; 4990 u8 next_fence = 0; 4991 u8 fence; 4992 4993 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 4994 !drain)) { 4995 *bad_wr = wr; 4996 return -EIO; 4997 } 4998 4999 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5000 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 5001 5002 qp = to_mqp(ibqp); 5003 bf = &qp->bf; 5004 5005 spin_lock_irqsave(&qp->sq.lock, flags); 5006 5007 for (nreq = 0; wr; nreq++, wr = wr->next) { 5008 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 5009 mlx5_ib_warn(dev, "\n"); 5010 err = -EINVAL; 5011 *bad_wr = wr; 5012 goto out; 5013 } 5014 5015 num_sge = wr->num_sge; 5016 if (unlikely(num_sge > qp->sq.max_gs)) { 5017 mlx5_ib_warn(dev, "\n"); 5018 err = -EINVAL; 5019 *bad_wr = wr; 5020 goto out; 5021 } 5022 5023 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, 5024 nreq); 5025 if (err) { 5026 mlx5_ib_warn(dev, "\n"); 5027 err = -ENOMEM; 5028 *bad_wr = wr; 5029 goto out; 5030 } 5031 5032 if (wr->opcode == IB_WR_REG_MR || 5033 wr->opcode == IB_WR_REG_MR_INTEGRITY) { 5034 fence = dev->umr_fence; 5035 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 5036 } else { 5037 if (wr->send_flags & IB_SEND_FENCE) { 5038 if (qp->next_fence) 5039 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 5040 else 5041 fence = MLX5_FENCE_MODE_FENCE; 5042 } else { 5043 fence = qp->next_fence; 5044 } 5045 } 5046 5047 switch (ibqp->qp_type) { 5048 case IB_QPT_XRC_INI: 5049 xrc = seg; 5050 seg += sizeof(*xrc); 5051 size += sizeof(*xrc) / 16; 5052 /* fall through */ 5053 case IB_QPT_RC: 5054 switch (wr->opcode) { 5055 case IB_WR_RDMA_READ: 5056 case IB_WR_RDMA_WRITE: 5057 case IB_WR_RDMA_WRITE_WITH_IMM: 5058 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 5059 rdma_wr(wr)->rkey); 5060 seg += sizeof(struct mlx5_wqe_raddr_seg); 5061 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 5062 break; 5063 5064 case IB_WR_ATOMIC_CMP_AND_SWP: 5065 case IB_WR_ATOMIC_FETCH_AND_ADD: 5066 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 5067 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 5068 err = -ENOSYS; 5069 *bad_wr = wr; 5070 goto out; 5071 5072 case IB_WR_LOCAL_INV: 5073 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 5074 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 5075 set_linv_wr(qp, &seg, &size, &cur_edge); 5076 num_sge = 0; 5077 break; 5078 5079 case IB_WR_REG_MR: 5080 qp->sq.wr_data[idx] = IB_WR_REG_MR; 5081 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 5082 err = set_reg_wr(qp, reg_wr(wr), &seg, &size, 5083 &cur_edge, true); 5084 if (err) { 5085 *bad_wr = wr; 5086 goto out; 5087 } 5088 num_sge = 0; 5089 break; 5090 5091 case IB_WR_REG_MR_INTEGRITY: 5092 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY; 5093 5094 mr = to_mmr(reg_wr(wr)->mr); 5095 pi_mr = mr->pi_mr; 5096 5097 if (pi_mr) { 5098 memset(®_pi_wr, 0, 5099 sizeof(struct ib_reg_wr)); 5100 5101 reg_pi_wr.mr = &pi_mr->ibmr; 5102 reg_pi_wr.access = reg_wr(wr)->access; 5103 reg_pi_wr.key = pi_mr->ibmr.rkey; 5104 5105 ctrl->imm = cpu_to_be32(reg_pi_wr.key); 5106 /* UMR for data + prot registration */ 5107 err = set_reg_wr(qp, ®_pi_wr, &seg, 5108 &size, &cur_edge, 5109 false); 5110 if (err) { 5111 *bad_wr = wr; 5112 goto out; 5113 } 5114 finish_wqe(qp, ctrl, seg, size, 5115 cur_edge, idx, wr->wr_id, 5116 nreq, fence, 5117 MLX5_OPCODE_UMR); 5118 5119 err = begin_wqe(qp, &seg, &ctrl, wr, 5120 &idx, &size, &cur_edge, 5121 nreq); 5122 if (err) { 5123 mlx5_ib_warn(dev, "\n"); 5124 err = -ENOMEM; 5125 *bad_wr = wr; 5126 goto out; 5127 } 5128 } else { 5129 memset(&pa_pi_mr, 0, 5130 sizeof(struct mlx5_ib_mr)); 5131 /* No UMR, use local_dma_lkey */ 5132 pa_pi_mr.ibmr.lkey = 5133 mr->ibmr.pd->local_dma_lkey; 5134 5135 pa_pi_mr.ndescs = mr->ndescs; 5136 pa_pi_mr.data_length = mr->data_length; 5137 pa_pi_mr.data_iova = mr->data_iova; 5138 if (mr->meta_ndescs) { 5139 pa_pi_mr.meta_ndescs = 5140 mr->meta_ndescs; 5141 pa_pi_mr.meta_length = 5142 mr->meta_length; 5143 pa_pi_mr.pi_iova = mr->pi_iova; 5144 } 5145 5146 pa_pi_mr.ibmr.length = mr->ibmr.length; 5147 mr->pi_mr = &pa_pi_mr; 5148 } 5149 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 5150 /* UMR for sig MR */ 5151 err = set_pi_umr_wr(wr, qp, &seg, &size, 5152 &cur_edge); 5153 if (err) { 5154 mlx5_ib_warn(dev, "\n"); 5155 *bad_wr = wr; 5156 goto out; 5157 } 5158 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5159 wr->wr_id, nreq, fence, 5160 MLX5_OPCODE_UMR); 5161 5162 /* 5163 * SET_PSV WQEs are not signaled and solicited 5164 * on error 5165 */ 5166 sig_attrs = mr->ibmr.sig_attrs; 5167 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 5168 &size, &cur_edge, nreq, false, 5169 true); 5170 if (err) { 5171 mlx5_ib_warn(dev, "\n"); 5172 err = -ENOMEM; 5173 *bad_wr = wr; 5174 goto out; 5175 } 5176 err = set_psv_wr(&sig_attrs->mem, 5177 mr->sig->psv_memory.psv_idx, 5178 &seg, &size); 5179 if (err) { 5180 mlx5_ib_warn(dev, "\n"); 5181 *bad_wr = wr; 5182 goto out; 5183 } 5184 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5185 wr->wr_id, nreq, next_fence, 5186 MLX5_OPCODE_SET_PSV); 5187 5188 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 5189 &size, &cur_edge, nreq, false, 5190 true); 5191 if (err) { 5192 mlx5_ib_warn(dev, "\n"); 5193 err = -ENOMEM; 5194 *bad_wr = wr; 5195 goto out; 5196 } 5197 err = set_psv_wr(&sig_attrs->wire, 5198 mr->sig->psv_wire.psv_idx, 5199 &seg, &size); 5200 if (err) { 5201 mlx5_ib_warn(dev, "\n"); 5202 *bad_wr = wr; 5203 goto out; 5204 } 5205 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5206 wr->wr_id, nreq, next_fence, 5207 MLX5_OPCODE_SET_PSV); 5208 5209 qp->next_fence = 5210 MLX5_FENCE_MODE_INITIATOR_SMALL; 5211 num_sge = 0; 5212 goto skip_psv; 5213 5214 default: 5215 break; 5216 } 5217 break; 5218 5219 case IB_QPT_UC: 5220 switch (wr->opcode) { 5221 case IB_WR_RDMA_WRITE: 5222 case IB_WR_RDMA_WRITE_WITH_IMM: 5223 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 5224 rdma_wr(wr)->rkey); 5225 seg += sizeof(struct mlx5_wqe_raddr_seg); 5226 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 5227 break; 5228 5229 default: 5230 break; 5231 } 5232 break; 5233 5234 case IB_QPT_SMI: 5235 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 5236 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 5237 err = -EPERM; 5238 *bad_wr = wr; 5239 goto out; 5240 } 5241 /* fall through */ 5242 case MLX5_IB_QPT_HW_GSI: 5243 set_datagram_seg(seg, wr); 5244 seg += sizeof(struct mlx5_wqe_datagram_seg); 5245 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5246 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5247 5248 break; 5249 case IB_QPT_UD: 5250 set_datagram_seg(seg, wr); 5251 seg += sizeof(struct mlx5_wqe_datagram_seg); 5252 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5253 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5254 5255 /* handle qp that supports ud offload */ 5256 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 5257 struct mlx5_wqe_eth_pad *pad; 5258 5259 pad = seg; 5260 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 5261 seg += sizeof(struct mlx5_wqe_eth_pad); 5262 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 5263 set_eth_seg(wr, qp, &seg, &size, &cur_edge); 5264 handle_post_send_edge(&qp->sq, &seg, size, 5265 &cur_edge); 5266 } 5267 break; 5268 case MLX5_IB_QPT_REG_UMR: 5269 if (wr->opcode != MLX5_IB_WR_UMR) { 5270 err = -EINVAL; 5271 mlx5_ib_warn(dev, "bad opcode\n"); 5272 goto out; 5273 } 5274 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 5275 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 5276 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 5277 if (unlikely(err)) 5278 goto out; 5279 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 5280 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 5281 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5282 set_reg_mkey_segment(seg, wr); 5283 seg += sizeof(struct mlx5_mkey_seg); 5284 size += sizeof(struct mlx5_mkey_seg) / 16; 5285 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5286 break; 5287 5288 default: 5289 break; 5290 } 5291 5292 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 5293 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); 5294 if (unlikely(err)) { 5295 mlx5_ib_warn(dev, "\n"); 5296 *bad_wr = wr; 5297 goto out; 5298 } 5299 } else { 5300 for (i = 0; i < num_sge; i++) { 5301 handle_post_send_edge(&qp->sq, &seg, size, 5302 &cur_edge); 5303 if (likely(wr->sg_list[i].length)) { 5304 set_data_ptr_seg 5305 ((struct mlx5_wqe_data_seg *)seg, 5306 wr->sg_list + i); 5307 size += sizeof(struct mlx5_wqe_data_seg) / 16; 5308 seg += sizeof(struct mlx5_wqe_data_seg); 5309 } 5310 } 5311 } 5312 5313 qp->next_fence = next_fence; 5314 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, 5315 fence, mlx5_ib_opcode[wr->opcode]); 5316 skip_psv: 5317 if (0) 5318 dump_wqe(qp, idx, size); 5319 } 5320 5321 out: 5322 if (likely(nreq)) { 5323 qp->sq.head += nreq; 5324 5325 /* Make sure that descriptors are written before 5326 * updating doorbell record and ringing the doorbell 5327 */ 5328 wmb(); 5329 5330 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 5331 5332 /* Make sure doorbell record is visible to the HCA before 5333 * we hit doorbell */ 5334 wmb(); 5335 5336 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset); 5337 /* Make sure doorbells don't leak out of SQ spinlock 5338 * and reach the HCA out of order. 5339 */ 5340 bf->offset ^= bf->buf_size; 5341 } 5342 5343 spin_unlock_irqrestore(&qp->sq.lock, flags); 5344 5345 return err; 5346 } 5347 5348 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5349 const struct ib_send_wr **bad_wr) 5350 { 5351 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); 5352 } 5353 5354 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 5355 { 5356 sig->signature = calc_sig(sig, size); 5357 } 5358 5359 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5360 const struct ib_recv_wr **bad_wr, bool drain) 5361 { 5362 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5363 struct mlx5_wqe_data_seg *scat; 5364 struct mlx5_rwqe_sig *sig; 5365 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5366 struct mlx5_core_dev *mdev = dev->mdev; 5367 unsigned long flags; 5368 int err = 0; 5369 int nreq; 5370 int ind; 5371 int i; 5372 5373 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5374 !drain)) { 5375 *bad_wr = wr; 5376 return -EIO; 5377 } 5378 5379 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5380 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 5381 5382 spin_lock_irqsave(&qp->rq.lock, flags); 5383 5384 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 5385 5386 for (nreq = 0; wr; nreq++, wr = wr->next) { 5387 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 5388 err = -ENOMEM; 5389 *bad_wr = wr; 5390 goto out; 5391 } 5392 5393 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 5394 err = -EINVAL; 5395 *bad_wr = wr; 5396 goto out; 5397 } 5398 5399 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); 5400 if (qp->wq_sig) 5401 scat++; 5402 5403 for (i = 0; i < wr->num_sge; i++) 5404 set_data_ptr_seg(scat + i, wr->sg_list + i); 5405 5406 if (i < qp->rq.max_gs) { 5407 scat[i].byte_count = 0; 5408 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 5409 scat[i].addr = 0; 5410 } 5411 5412 if (qp->wq_sig) { 5413 sig = (struct mlx5_rwqe_sig *)scat; 5414 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 5415 } 5416 5417 qp->rq.wrid[ind] = wr->wr_id; 5418 5419 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 5420 } 5421 5422 out: 5423 if (likely(nreq)) { 5424 qp->rq.head += nreq; 5425 5426 /* Make sure that descriptors are written before 5427 * doorbell record. 5428 */ 5429 wmb(); 5430 5431 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 5432 } 5433 5434 spin_unlock_irqrestore(&qp->rq.lock, flags); 5435 5436 return err; 5437 } 5438 5439 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5440 const struct ib_recv_wr **bad_wr) 5441 { 5442 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); 5443 } 5444 5445 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 5446 { 5447 switch (mlx5_state) { 5448 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 5449 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 5450 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 5451 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 5452 case MLX5_QP_STATE_SQ_DRAINING: 5453 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 5454 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 5455 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 5456 default: return -1; 5457 } 5458 } 5459 5460 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 5461 { 5462 switch (mlx5_mig_state) { 5463 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 5464 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 5465 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 5466 default: return -1; 5467 } 5468 } 5469 5470 static int to_ib_qp_access_flags(int mlx5_flags) 5471 { 5472 int ib_flags = 0; 5473 5474 if (mlx5_flags & MLX5_QP_BIT_RRE) 5475 ib_flags |= IB_ACCESS_REMOTE_READ; 5476 if (mlx5_flags & MLX5_QP_BIT_RWE) 5477 ib_flags |= IB_ACCESS_REMOTE_WRITE; 5478 if (mlx5_flags & MLX5_QP_BIT_RAE) 5479 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 5480 5481 return ib_flags; 5482 } 5483 5484 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 5485 struct rdma_ah_attr *ah_attr, 5486 struct mlx5_qp_path *path) 5487 { 5488 5489 memset(ah_attr, 0, sizeof(*ah_attr)); 5490 5491 if (!path->port || path->port > ibdev->num_ports) 5492 return; 5493 5494 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 5495 5496 rdma_ah_set_port_num(ah_attr, path->port); 5497 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 5498 5499 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 5500 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 5501 rdma_ah_set_static_rate(ah_attr, 5502 path->static_rate ? path->static_rate - 5 : 0); 5503 if (path->grh_mlid & (1 << 7)) { 5504 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 5505 5506 rdma_ah_set_grh(ah_attr, NULL, 5507 tc_fl & 0xfffff, 5508 path->mgid_index, 5509 path->hop_limit, 5510 (tc_fl >> 20) & 0xff); 5511 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 5512 } 5513 } 5514 5515 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 5516 struct mlx5_ib_sq *sq, 5517 u8 *sq_state) 5518 { 5519 int err; 5520 5521 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 5522 if (err) 5523 goto out; 5524 sq->state = *sq_state; 5525 5526 out: 5527 return err; 5528 } 5529 5530 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 5531 struct mlx5_ib_rq *rq, 5532 u8 *rq_state) 5533 { 5534 void *out; 5535 void *rqc; 5536 int inlen; 5537 int err; 5538 5539 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 5540 out = kvzalloc(inlen, GFP_KERNEL); 5541 if (!out) 5542 return -ENOMEM; 5543 5544 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 5545 if (err) 5546 goto out; 5547 5548 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 5549 *rq_state = MLX5_GET(rqc, rqc, state); 5550 rq->state = *rq_state; 5551 5552 out: 5553 kvfree(out); 5554 return err; 5555 } 5556 5557 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 5558 struct mlx5_ib_qp *qp, u8 *qp_state) 5559 { 5560 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 5561 [MLX5_RQC_STATE_RST] = { 5562 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5563 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5564 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 5565 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 5566 }, 5567 [MLX5_RQC_STATE_RDY] = { 5568 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5569 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5570 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 5571 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 5572 }, 5573 [MLX5_RQC_STATE_ERR] = { 5574 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5575 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5576 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 5577 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 5578 }, 5579 [MLX5_RQ_STATE_NA] = { 5580 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5581 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5582 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 5583 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 5584 }, 5585 }; 5586 5587 *qp_state = sqrq_trans[rq_state][sq_state]; 5588 5589 if (*qp_state == MLX5_QP_STATE_BAD) { 5590 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 5591 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 5592 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 5593 return -EINVAL; 5594 } 5595 5596 if (*qp_state == MLX5_QP_STATE) 5597 *qp_state = qp->state; 5598 5599 return 0; 5600 } 5601 5602 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 5603 struct mlx5_ib_qp *qp, 5604 u8 *raw_packet_qp_state) 5605 { 5606 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 5607 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 5608 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 5609 int err; 5610 u8 sq_state = MLX5_SQ_STATE_NA; 5611 u8 rq_state = MLX5_RQ_STATE_NA; 5612 5613 if (qp->sq.wqe_cnt) { 5614 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 5615 if (err) 5616 return err; 5617 } 5618 5619 if (qp->rq.wqe_cnt) { 5620 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 5621 if (err) 5622 return err; 5623 } 5624 5625 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 5626 raw_packet_qp_state); 5627 } 5628 5629 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 5630 struct ib_qp_attr *qp_attr) 5631 { 5632 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 5633 struct mlx5_qp_context *context; 5634 int mlx5_state; 5635 u32 *outb; 5636 int err = 0; 5637 5638 outb = kzalloc(outlen, GFP_KERNEL); 5639 if (!outb) 5640 return -ENOMEM; 5641 5642 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 5643 outlen); 5644 if (err) 5645 goto out; 5646 5647 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 5648 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 5649 5650 mlx5_state = be32_to_cpu(context->flags) >> 28; 5651 5652 qp->state = to_ib_qp_state(mlx5_state); 5653 qp_attr->path_mtu = context->mtu_msgmax >> 5; 5654 qp_attr->path_mig_state = 5655 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 5656 qp_attr->qkey = be32_to_cpu(context->qkey); 5657 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 5658 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 5659 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 5660 qp_attr->qp_access_flags = 5661 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 5662 5663 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 5664 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 5665 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5666 qp_attr->alt_pkey_index = 5667 be16_to_cpu(context->alt_path.pkey_index); 5668 qp_attr->alt_port_num = 5669 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5670 } 5671 5672 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5673 qp_attr->port_num = context->pri_path.port; 5674 5675 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5676 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5677 5678 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5679 5680 qp_attr->max_dest_rd_atomic = 5681 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5682 qp_attr->min_rnr_timer = 5683 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5684 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5685 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5686 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5687 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5688 5689 out: 5690 kfree(outb); 5691 return err; 5692 } 5693 5694 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5695 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5696 struct ib_qp_init_attr *qp_init_attr) 5697 { 5698 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5699 u32 *out; 5700 u32 access_flags = 0; 5701 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5702 void *dctc; 5703 int err; 5704 int supported_mask = IB_QP_STATE | 5705 IB_QP_ACCESS_FLAGS | 5706 IB_QP_PORT | 5707 IB_QP_MIN_RNR_TIMER | 5708 IB_QP_AV | 5709 IB_QP_PATH_MTU | 5710 IB_QP_PKEY_INDEX; 5711 5712 if (qp_attr_mask & ~supported_mask) 5713 return -EINVAL; 5714 if (mqp->state != IB_QPS_RTR) 5715 return -EINVAL; 5716 5717 out = kzalloc(outlen, GFP_KERNEL); 5718 if (!out) 5719 return -ENOMEM; 5720 5721 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5722 if (err) 5723 goto out; 5724 5725 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5726 5727 if (qp_attr_mask & IB_QP_STATE) 5728 qp_attr->qp_state = IB_QPS_RTR; 5729 5730 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5731 if (MLX5_GET(dctc, dctc, rre)) 5732 access_flags |= IB_ACCESS_REMOTE_READ; 5733 if (MLX5_GET(dctc, dctc, rwe)) 5734 access_flags |= IB_ACCESS_REMOTE_WRITE; 5735 if (MLX5_GET(dctc, dctc, rae)) 5736 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5737 qp_attr->qp_access_flags = access_flags; 5738 } 5739 5740 if (qp_attr_mask & IB_QP_PORT) 5741 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5742 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5743 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5744 if (qp_attr_mask & IB_QP_AV) { 5745 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5746 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5747 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5748 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5749 } 5750 if (qp_attr_mask & IB_QP_PATH_MTU) 5751 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5752 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5753 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5754 out: 5755 kfree(out); 5756 return err; 5757 } 5758 5759 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5760 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5761 { 5762 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5763 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5764 int err = 0; 5765 u8 raw_packet_qp_state; 5766 5767 if (ibqp->rwq_ind_tbl) 5768 return -ENOSYS; 5769 5770 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5771 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5772 qp_init_attr); 5773 5774 /* Not all of output fields are applicable, make sure to zero them */ 5775 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5776 memset(qp_attr, 0, sizeof(*qp_attr)); 5777 5778 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5779 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5780 qp_attr_mask, qp_init_attr); 5781 5782 mutex_lock(&qp->mutex); 5783 5784 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5785 qp->flags & MLX5_IB_QP_UNDERLAY) { 5786 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5787 if (err) 5788 goto out; 5789 qp->state = raw_packet_qp_state; 5790 qp_attr->port_num = 1; 5791 } else { 5792 err = query_qp_attr(dev, qp, qp_attr); 5793 if (err) 5794 goto out; 5795 } 5796 5797 qp_attr->qp_state = qp->state; 5798 qp_attr->cur_qp_state = qp_attr->qp_state; 5799 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5800 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5801 5802 if (!ibqp->uobject) { 5803 qp_attr->cap.max_send_wr = qp->sq.max_post; 5804 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5805 qp_init_attr->qp_context = ibqp->qp_context; 5806 } else { 5807 qp_attr->cap.max_send_wr = 0; 5808 qp_attr->cap.max_send_sge = 0; 5809 } 5810 5811 qp_init_attr->qp_type = ibqp->qp_type; 5812 qp_init_attr->recv_cq = ibqp->recv_cq; 5813 qp_init_attr->send_cq = ibqp->send_cq; 5814 qp_init_attr->srq = ibqp->srq; 5815 qp_attr->cap.max_inline_data = qp->max_inline_data; 5816 5817 qp_init_attr->cap = qp_attr->cap; 5818 5819 qp_init_attr->create_flags = 0; 5820 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5821 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5822 5823 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5824 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5825 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5826 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5827 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5828 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5829 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5830 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; 5831 5832 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5833 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5834 5835 out: 5836 mutex_unlock(&qp->mutex); 5837 return err; 5838 } 5839 5840 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5841 struct ib_udata *udata) 5842 { 5843 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5844 struct mlx5_ib_xrcd *xrcd; 5845 int err; 5846 5847 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5848 return ERR_PTR(-ENOSYS); 5849 5850 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5851 if (!xrcd) 5852 return ERR_PTR(-ENOMEM); 5853 5854 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5855 if (err) { 5856 kfree(xrcd); 5857 return ERR_PTR(-ENOMEM); 5858 } 5859 5860 return &xrcd->ibxrcd; 5861 } 5862 5863 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5864 { 5865 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5866 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5867 int err; 5868 5869 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5870 if (err) 5871 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5872 5873 kfree(xrcd); 5874 return 0; 5875 } 5876 5877 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5878 { 5879 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5880 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5881 struct ib_event event; 5882 5883 if (rwq->ibwq.event_handler) { 5884 event.device = rwq->ibwq.device; 5885 event.element.wq = &rwq->ibwq; 5886 switch (type) { 5887 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5888 event.event = IB_EVENT_WQ_FATAL; 5889 break; 5890 default: 5891 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5892 return; 5893 } 5894 5895 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5896 } 5897 } 5898 5899 static int set_delay_drop(struct mlx5_ib_dev *dev) 5900 { 5901 int err = 0; 5902 5903 mutex_lock(&dev->delay_drop.lock); 5904 if (dev->delay_drop.activate) 5905 goto out; 5906 5907 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5908 if (err) 5909 goto out; 5910 5911 dev->delay_drop.activate = true; 5912 out: 5913 mutex_unlock(&dev->delay_drop.lock); 5914 5915 if (!err) 5916 atomic_inc(&dev->delay_drop.rqs_cnt); 5917 return err; 5918 } 5919 5920 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5921 struct ib_wq_init_attr *init_attr) 5922 { 5923 struct mlx5_ib_dev *dev; 5924 int has_net_offloads; 5925 __be64 *rq_pas0; 5926 void *in; 5927 void *rqc; 5928 void *wq; 5929 int inlen; 5930 int err; 5931 5932 dev = to_mdev(pd->device); 5933 5934 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5935 in = kvzalloc(inlen, GFP_KERNEL); 5936 if (!in) 5937 return -ENOMEM; 5938 5939 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5940 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5941 MLX5_SET(rqc, rqc, mem_rq_type, 5942 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5943 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5944 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5945 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5946 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5947 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5948 MLX5_SET(wq, wq, wq_type, 5949 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5950 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5951 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5952 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5953 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5954 err = -EOPNOTSUPP; 5955 goto out; 5956 } else { 5957 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5958 } 5959 } 5960 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5961 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5962 /* 5963 * In Firmware number of strides in each WQE is: 5964 * "512 * 2^single_wqe_log_num_of_strides" 5965 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 5966 * accepted as 0 to 9 5967 */ 5968 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 5969 2, 3, 4, 5, 6, 7, 8, 9 }; 5970 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5971 MLX5_SET(wq, wq, log_wqe_stride_size, 5972 rwq->single_stride_log_num_of_bytes - 5973 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5974 MLX5_SET(wq, wq, log_wqe_num_of_strides, 5975 fw_map[rwq->log_num_strides - 5976 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 5977 } 5978 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5979 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5980 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5981 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5982 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5983 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5984 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5985 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5986 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5987 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5988 err = -EOPNOTSUPP; 5989 goto out; 5990 } 5991 } else { 5992 MLX5_SET(rqc, rqc, vsd, 1); 5993 } 5994 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5995 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5996 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5997 err = -EOPNOTSUPP; 5998 goto out; 5999 } 6000 MLX5_SET(rqc, rqc, scatter_fcs, 1); 6001 } 6002 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 6003 if (!(dev->ib_dev.attrs.raw_packet_caps & 6004 IB_RAW_PACKET_CAP_DELAY_DROP)) { 6005 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 6006 err = -EOPNOTSUPP; 6007 goto out; 6008 } 6009 MLX5_SET(rqc, rqc, delay_drop_en, 1); 6010 } 6011 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 6012 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 6013 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 6014 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 6015 err = set_delay_drop(dev); 6016 if (err) { 6017 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 6018 err); 6019 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 6020 } else { 6021 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 6022 } 6023 } 6024 out: 6025 kvfree(in); 6026 return err; 6027 } 6028 6029 static int set_user_rq_size(struct mlx5_ib_dev *dev, 6030 struct ib_wq_init_attr *wq_init_attr, 6031 struct mlx5_ib_create_wq *ucmd, 6032 struct mlx5_ib_rwq *rwq) 6033 { 6034 /* Sanity check RQ size before proceeding */ 6035 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 6036 return -EINVAL; 6037 6038 if (!ucmd->rq_wqe_count) 6039 return -EINVAL; 6040 6041 rwq->wqe_count = ucmd->rq_wqe_count; 6042 rwq->wqe_shift = ucmd->rq_wqe_shift; 6043 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 6044 return -EINVAL; 6045 6046 rwq->log_rq_stride = rwq->wqe_shift; 6047 rwq->log_rq_size = ilog2(rwq->wqe_count); 6048 return 0; 6049 } 6050 6051 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 6052 { 6053 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 6054 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 6055 return false; 6056 6057 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 6058 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 6059 return false; 6060 6061 return true; 6062 } 6063 6064 static int prepare_user_rq(struct ib_pd *pd, 6065 struct ib_wq_init_attr *init_attr, 6066 struct ib_udata *udata, 6067 struct mlx5_ib_rwq *rwq) 6068 { 6069 struct mlx5_ib_dev *dev = to_mdev(pd->device); 6070 struct mlx5_ib_create_wq ucmd = {}; 6071 int err; 6072 size_t required_cmd_sz; 6073 6074 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 6075 + sizeof(ucmd.single_stride_log_num_of_bytes); 6076 if (udata->inlen < required_cmd_sz) { 6077 mlx5_ib_dbg(dev, "invalid inlen\n"); 6078 return -EINVAL; 6079 } 6080 6081 if (udata->inlen > sizeof(ucmd) && 6082 !ib_is_udata_cleared(udata, sizeof(ucmd), 6083 udata->inlen - sizeof(ucmd))) { 6084 mlx5_ib_dbg(dev, "inlen is not supported\n"); 6085 return -EOPNOTSUPP; 6086 } 6087 6088 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 6089 mlx5_ib_dbg(dev, "copy failed\n"); 6090 return -EFAULT; 6091 } 6092 6093 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 6094 mlx5_ib_dbg(dev, "invalid comp mask\n"); 6095 return -EOPNOTSUPP; 6096 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 6097 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 6098 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 6099 return -EOPNOTSUPP; 6100 } 6101 if ((ucmd.single_stride_log_num_of_bytes < 6102 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 6103 (ucmd.single_stride_log_num_of_bytes > 6104 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 6105 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 6106 ucmd.single_stride_log_num_of_bytes, 6107 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 6108 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 6109 return -EINVAL; 6110 } 6111 if (!log_of_strides_valid(dev, 6112 ucmd.single_wqe_log_num_of_strides)) { 6113 mlx5_ib_dbg( 6114 dev, 6115 "Invalid log num strides (%u. Range is %u - %u)\n", 6116 ucmd.single_wqe_log_num_of_strides, 6117 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 6118 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 6119 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 6120 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 6121 return -EINVAL; 6122 } 6123 rwq->single_stride_log_num_of_bytes = 6124 ucmd.single_stride_log_num_of_bytes; 6125 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 6126 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 6127 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 6128 } 6129 6130 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 6131 if (err) { 6132 mlx5_ib_dbg(dev, "err %d\n", err); 6133 return err; 6134 } 6135 6136 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 6137 if (err) { 6138 mlx5_ib_dbg(dev, "err %d\n", err); 6139 return err; 6140 } 6141 6142 rwq->user_index = ucmd.user_index; 6143 return 0; 6144 } 6145 6146 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 6147 struct ib_wq_init_attr *init_attr, 6148 struct ib_udata *udata) 6149 { 6150 struct mlx5_ib_dev *dev; 6151 struct mlx5_ib_rwq *rwq; 6152 struct mlx5_ib_create_wq_resp resp = {}; 6153 size_t min_resp_len; 6154 int err; 6155 6156 if (!udata) 6157 return ERR_PTR(-ENOSYS); 6158 6159 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 6160 if (udata->outlen && udata->outlen < min_resp_len) 6161 return ERR_PTR(-EINVAL); 6162 6163 dev = to_mdev(pd->device); 6164 switch (init_attr->wq_type) { 6165 case IB_WQT_RQ: 6166 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 6167 if (!rwq) 6168 return ERR_PTR(-ENOMEM); 6169 err = prepare_user_rq(pd, init_attr, udata, rwq); 6170 if (err) 6171 goto err; 6172 err = create_rq(rwq, pd, init_attr); 6173 if (err) 6174 goto err_user_rq; 6175 break; 6176 default: 6177 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 6178 init_attr->wq_type); 6179 return ERR_PTR(-EINVAL); 6180 } 6181 6182 rwq->ibwq.wq_num = rwq->core_qp.qpn; 6183 rwq->ibwq.state = IB_WQS_RESET; 6184 if (udata->outlen) { 6185 resp.response_length = offsetof(typeof(resp), response_length) + 6186 sizeof(resp.response_length); 6187 err = ib_copy_to_udata(udata, &resp, resp.response_length); 6188 if (err) 6189 goto err_copy; 6190 } 6191 6192 rwq->core_qp.event = mlx5_ib_wq_event; 6193 rwq->ibwq.event_handler = init_attr->event_handler; 6194 return &rwq->ibwq; 6195 6196 err_copy: 6197 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 6198 err_user_rq: 6199 destroy_user_rq(dev, pd, rwq, udata); 6200 err: 6201 kfree(rwq); 6202 return ERR_PTR(err); 6203 } 6204 6205 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 6206 { 6207 struct mlx5_ib_dev *dev = to_mdev(wq->device); 6208 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 6209 6210 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 6211 destroy_user_rq(dev, wq->pd, rwq, udata); 6212 kfree(rwq); 6213 } 6214 6215 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 6216 struct ib_rwq_ind_table_init_attr *init_attr, 6217 struct ib_udata *udata) 6218 { 6219 struct mlx5_ib_dev *dev = to_mdev(device); 6220 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 6221 int sz = 1 << init_attr->log_ind_tbl_size; 6222 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 6223 size_t min_resp_len; 6224 int inlen; 6225 int err; 6226 int i; 6227 u32 *in; 6228 void *rqtc; 6229 6230 if (udata->inlen > 0 && 6231 !ib_is_udata_cleared(udata, 0, 6232 udata->inlen)) 6233 return ERR_PTR(-EOPNOTSUPP); 6234 6235 if (init_attr->log_ind_tbl_size > 6236 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 6237 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 6238 init_attr->log_ind_tbl_size, 6239 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 6240 return ERR_PTR(-EINVAL); 6241 } 6242 6243 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 6244 if (udata->outlen && udata->outlen < min_resp_len) 6245 return ERR_PTR(-EINVAL); 6246 6247 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 6248 if (!rwq_ind_tbl) 6249 return ERR_PTR(-ENOMEM); 6250 6251 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 6252 in = kvzalloc(inlen, GFP_KERNEL); 6253 if (!in) { 6254 err = -ENOMEM; 6255 goto err; 6256 } 6257 6258 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 6259 6260 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 6261 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 6262 6263 for (i = 0; i < sz; i++) 6264 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 6265 6266 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 6267 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 6268 6269 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 6270 kvfree(in); 6271 6272 if (err) 6273 goto err; 6274 6275 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 6276 if (udata->outlen) { 6277 resp.response_length = offsetof(typeof(resp), response_length) + 6278 sizeof(resp.response_length); 6279 err = ib_copy_to_udata(udata, &resp, resp.response_length); 6280 if (err) 6281 goto err_copy; 6282 } 6283 6284 return &rwq_ind_tbl->ib_rwq_ind_tbl; 6285 6286 err_copy: 6287 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6288 err: 6289 kfree(rwq_ind_tbl); 6290 return ERR_PTR(err); 6291 } 6292 6293 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 6294 { 6295 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 6296 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 6297 6298 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6299 6300 kfree(rwq_ind_tbl); 6301 return 0; 6302 } 6303 6304 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 6305 u32 wq_attr_mask, struct ib_udata *udata) 6306 { 6307 struct mlx5_ib_dev *dev = to_mdev(wq->device); 6308 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 6309 struct mlx5_ib_modify_wq ucmd = {}; 6310 size_t required_cmd_sz; 6311 int curr_wq_state; 6312 int wq_state; 6313 int inlen; 6314 int err; 6315 void *rqc; 6316 void *in; 6317 6318 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 6319 if (udata->inlen < required_cmd_sz) 6320 return -EINVAL; 6321 6322 if (udata->inlen > sizeof(ucmd) && 6323 !ib_is_udata_cleared(udata, sizeof(ucmd), 6324 udata->inlen - sizeof(ucmd))) 6325 return -EOPNOTSUPP; 6326 6327 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 6328 return -EFAULT; 6329 6330 if (ucmd.comp_mask || ucmd.reserved) 6331 return -EOPNOTSUPP; 6332 6333 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 6334 in = kvzalloc(inlen, GFP_KERNEL); 6335 if (!in) 6336 return -ENOMEM; 6337 6338 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 6339 6340 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 6341 wq_attr->curr_wq_state : wq->state; 6342 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 6343 wq_attr->wq_state : curr_wq_state; 6344 if (curr_wq_state == IB_WQS_ERR) 6345 curr_wq_state = MLX5_RQC_STATE_ERR; 6346 if (wq_state == IB_WQS_ERR) 6347 wq_state = MLX5_RQC_STATE_ERR; 6348 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 6349 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 6350 MLX5_SET(rqc, rqc, state, wq_state); 6351 6352 if (wq_attr_mask & IB_WQ_FLAGS) { 6353 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6354 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 6355 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6356 mlx5_ib_dbg(dev, "VLAN offloads are not " 6357 "supported\n"); 6358 err = -EOPNOTSUPP; 6359 goto out; 6360 } 6361 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6362 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 6363 MLX5_SET(rqc, rqc, vsd, 6364 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 6365 } 6366 6367 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6368 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 6369 err = -EOPNOTSUPP; 6370 goto out; 6371 } 6372 } 6373 6374 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 6375 u16 set_id; 6376 6377 set_id = mlx5_ib_get_counters_id(dev, 0); 6378 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 6379 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6380 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 6381 MLX5_SET(rqc, rqc, counter_set_id, set_id); 6382 } else 6383 dev_info_once( 6384 &dev->ib_dev.dev, 6385 "Receive WQ counters are not supported on current FW\n"); 6386 } 6387 6388 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 6389 if (!err) 6390 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 6391 6392 out: 6393 kvfree(in); 6394 return err; 6395 } 6396 6397 struct mlx5_ib_drain_cqe { 6398 struct ib_cqe cqe; 6399 struct completion done; 6400 }; 6401 6402 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 6403 { 6404 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 6405 struct mlx5_ib_drain_cqe, 6406 cqe); 6407 6408 complete(&cqe->done); 6409 } 6410 6411 /* This function returns only once the drained WR was completed */ 6412 static void handle_drain_completion(struct ib_cq *cq, 6413 struct mlx5_ib_drain_cqe *sdrain, 6414 struct mlx5_ib_dev *dev) 6415 { 6416 struct mlx5_core_dev *mdev = dev->mdev; 6417 6418 if (cq->poll_ctx == IB_POLL_DIRECT) { 6419 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 6420 ib_process_cq_direct(cq, -1); 6421 return; 6422 } 6423 6424 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6425 struct mlx5_ib_cq *mcq = to_mcq(cq); 6426 bool triggered = false; 6427 unsigned long flags; 6428 6429 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 6430 /* Make sure that the CQ handler won't run if wasn't run yet */ 6431 if (!mcq->mcq.reset_notify_added) 6432 mcq->mcq.reset_notify_added = 1; 6433 else 6434 triggered = true; 6435 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 6436 6437 if (triggered) { 6438 /* Wait for any scheduled/running task to be ended */ 6439 switch (cq->poll_ctx) { 6440 case IB_POLL_SOFTIRQ: 6441 irq_poll_disable(&cq->iop); 6442 irq_poll_enable(&cq->iop); 6443 break; 6444 case IB_POLL_WORKQUEUE: 6445 cancel_work_sync(&cq->work); 6446 break; 6447 default: 6448 WARN_ON_ONCE(1); 6449 } 6450 } 6451 6452 /* Run the CQ handler - this makes sure that the drain WR will 6453 * be processed if wasn't processed yet. 6454 */ 6455 mcq->mcq.comp(&mcq->mcq, NULL); 6456 } 6457 6458 wait_for_completion(&sdrain->done); 6459 } 6460 6461 void mlx5_ib_drain_sq(struct ib_qp *qp) 6462 { 6463 struct ib_cq *cq = qp->send_cq; 6464 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6465 struct mlx5_ib_drain_cqe sdrain; 6466 const struct ib_send_wr *bad_swr; 6467 struct ib_rdma_wr swr = { 6468 .wr = { 6469 .next = NULL, 6470 { .wr_cqe = &sdrain.cqe, }, 6471 .opcode = IB_WR_RDMA_WRITE, 6472 }, 6473 }; 6474 int ret; 6475 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6476 struct mlx5_core_dev *mdev = dev->mdev; 6477 6478 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6479 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6480 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6481 return; 6482 } 6483 6484 sdrain.cqe.done = mlx5_ib_drain_qp_done; 6485 init_completion(&sdrain.done); 6486 6487 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); 6488 if (ret) { 6489 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6490 return; 6491 } 6492 6493 handle_drain_completion(cq, &sdrain, dev); 6494 } 6495 6496 void mlx5_ib_drain_rq(struct ib_qp *qp) 6497 { 6498 struct ib_cq *cq = qp->recv_cq; 6499 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6500 struct mlx5_ib_drain_cqe rdrain; 6501 struct ib_recv_wr rwr = {}; 6502 const struct ib_recv_wr *bad_rwr; 6503 int ret; 6504 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6505 struct mlx5_core_dev *mdev = dev->mdev; 6506 6507 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6508 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6509 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6510 return; 6511 } 6512 6513 rwr.wr_cqe = &rdrain.cqe; 6514 rdrain.cqe.done = mlx5_ib_drain_qp_done; 6515 init_completion(&rdrain.done); 6516 6517 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); 6518 if (ret) { 6519 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6520 return; 6521 } 6522 6523 handle_drain_completion(cq, &rdrain, dev); 6524 } 6525 6526 /** 6527 * Bind a qp to a counter. If @counter is NULL then bind the qp to 6528 * the default counter 6529 */ 6530 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 6531 { 6532 struct mlx5_ib_qp *mqp = to_mqp(qp); 6533 int err = 0; 6534 6535 mutex_lock(&mqp->mutex); 6536 if (mqp->state == IB_QPS_RESET) { 6537 qp->counter = counter; 6538 goto out; 6539 } 6540 6541 if (mqp->state == IB_QPS_RTS) { 6542 err = __mlx5_ib_qp_set_counter(qp, counter); 6543 if (!err) 6544 qp->counter = counter; 6545 6546 goto out; 6547 } 6548 6549 mqp->counter_pending = 1; 6550 qp->counter = counter; 6551 6552 out: 6553 mutex_unlock(&mqp->mutex); 6554 return err; 6555 } 6556