1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "qp.h" 44 #include "wr.h" 45 46 enum { 47 MLX5_IB_ACK_REQ_FREQ = 8, 48 }; 49 50 enum { 51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 53 MLX5_IB_LINK_TYPE_IB = 0, 54 MLX5_IB_LINK_TYPE_ETH = 1 55 }; 56 57 enum raw_qp_set_mask_map { 58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 60 }; 61 62 struct mlx5_modify_raw_qp_param { 63 u16 operation; 64 65 u32 set_mask; /* raw_qp_set_mask_map */ 66 67 struct mlx5_rate_limit rl; 68 69 u8 rq_q_ctr_id; 70 u32 port; 71 }; 72 73 static void get_cqs(enum ib_qp_type qp_type, 74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 76 77 static int is_qp0(enum ib_qp_type qp_type) 78 { 79 return qp_type == IB_QPT_SMI; 80 } 81 82 static int is_sqp(enum ib_qp_type qp_type) 83 { 84 return is_qp0(qp_type) || is_qp1(qp_type); 85 } 86 87 /** 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 89 * to kernel buffer 90 * 91 * @umem: User space memory where the WQ is 92 * @buffer: buffer to copy to 93 * @buflen: buffer length 94 * @wqe_index: index of WQE to copy from 95 * @wq_offset: offset to start of WQ 96 * @wq_wqe_cnt: number of WQEs in WQ 97 * @wq_wqe_shift: log2 of WQE size 98 * @bcnt: number of bytes to copy 99 * @bytes_copied: number of bytes to copy (return value) 100 * 101 * Copies from start of WQE bcnt or less bytes. 102 * Does not gurantee to copy the entire WQE. 103 * 104 * Return: zero on success, or an error code. 105 */ 106 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 107 size_t buflen, int wqe_index, 108 int wq_offset, int wq_wqe_cnt, 109 int wq_wqe_shift, int bcnt, 110 size_t *bytes_copied) 111 { 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 114 size_t copy_length; 115 int ret; 116 117 /* don't copy more than requested, more than buffer length or 118 * beyond WQ end 119 */ 120 copy_length = min_t(u32, buflen, wq_end - offset); 121 copy_length = min_t(u32, copy_length, bcnt); 122 123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 124 if (ret) 125 return ret; 126 127 if (!ret && bytes_copied) 128 *bytes_copied = copy_length; 129 130 return 0; 131 } 132 133 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 134 void *buffer, size_t buflen, size_t *bc) 135 { 136 struct mlx5_wqe_ctrl_seg *ctrl; 137 size_t bytes_copied = 0; 138 size_t wqe_length; 139 void *p; 140 int ds; 141 142 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 143 144 /* read the control segment first */ 145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 146 ctrl = p; 147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 148 wqe_length = ds * MLX5_WQE_DS_UNITS; 149 150 /* read rest of WQE if it spreads over more than one stride */ 151 while (bytes_copied < wqe_length) { 152 size_t copy_length = 153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 154 155 if (!copy_length) 156 break; 157 158 memcpy(buffer + bytes_copied, p, copy_length); 159 bytes_copied += copy_length; 160 161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 163 } 164 *bc = bytes_copied; 165 return 0; 166 } 167 168 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 169 void *buffer, size_t buflen, size_t *bc) 170 { 171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 172 struct ib_umem *umem = base->ubuffer.umem; 173 struct mlx5_ib_wq *wq = &qp->sq; 174 struct mlx5_wqe_ctrl_seg *ctrl; 175 size_t bytes_copied; 176 size_t bytes_copied2; 177 size_t wqe_length; 178 int ret; 179 int ds; 180 181 /* at first read as much as possible */ 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 183 wq->offset, wq->wqe_cnt, 184 wq->wqe_shift, buflen, 185 &bytes_copied); 186 if (ret) 187 return ret; 188 189 /* we need at least control segment size to proceed */ 190 if (bytes_copied < sizeof(*ctrl)) 191 return -EINVAL; 192 193 ctrl = buffer; 194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 195 wqe_length = ds * MLX5_WQE_DS_UNITS; 196 197 /* if we copied enough then we are done */ 198 if (bytes_copied >= wqe_length) { 199 *bc = bytes_copied; 200 return 0; 201 } 202 203 /* otherwise this a wrapped around wqe 204 * so read the remaining bytes starting 205 * from wqe_index 0 206 */ 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 208 buflen - bytes_copied, 0, wq->offset, 209 wq->wqe_cnt, wq->wqe_shift, 210 wqe_length - bytes_copied, 211 &bytes_copied2); 212 213 if (ret) 214 return ret; 215 *bc = bytes_copied + bytes_copied2; 216 return 0; 217 } 218 219 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 220 size_t buflen, size_t *bc) 221 { 222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 223 struct ib_umem *umem = base->ubuffer.umem; 224 225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 226 return -EINVAL; 227 228 if (!umem) 229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 230 buflen, bc); 231 232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 233 } 234 235 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 236 void *buffer, size_t buflen, size_t *bc) 237 { 238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 239 struct ib_umem *umem = base->ubuffer.umem; 240 struct mlx5_ib_wq *wq = &qp->rq; 241 size_t bytes_copied; 242 int ret; 243 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 245 wq->offset, wq->wqe_cnt, 246 wq->wqe_shift, buflen, 247 &bytes_copied); 248 249 if (ret) 250 return ret; 251 *bc = bytes_copied; 252 return 0; 253 } 254 255 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 256 size_t buflen, size_t *bc) 257 { 258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 259 struct ib_umem *umem = base->ubuffer.umem; 260 struct mlx5_ib_wq *wq = &qp->rq; 261 size_t wqe_size = 1 << wq->wqe_shift; 262 263 if (buflen < wqe_size) 264 return -EINVAL; 265 266 if (!umem) 267 return -EOPNOTSUPP; 268 269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 270 } 271 272 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 273 void *buffer, size_t buflen, size_t *bc) 274 { 275 struct ib_umem *umem = srq->umem; 276 size_t bytes_copied; 277 int ret; 278 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 280 srq->msrq.max, srq->msrq.wqe_shift, 281 buflen, &bytes_copied); 282 283 if (ret) 284 return ret; 285 *bc = bytes_copied; 286 return 0; 287 } 288 289 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 290 size_t buflen, size_t *bc) 291 { 292 struct ib_umem *umem = srq->umem; 293 size_t wqe_size = 1 << srq->msrq.wqe_shift; 294 295 if (buflen < wqe_size) 296 return -EINVAL; 297 298 if (!umem) 299 return -EOPNOTSUPP; 300 301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 302 } 303 304 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 305 { 306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 307 struct ib_event event; 308 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 310 /* This event is only valid for trans_qps */ 311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 312 } 313 314 if (ibqp->event_handler) { 315 event.device = ibqp->device; 316 event.element.qp = ibqp; 317 switch (type) { 318 case MLX5_EVENT_TYPE_PATH_MIG: 319 event.event = IB_EVENT_PATH_MIG; 320 break; 321 case MLX5_EVENT_TYPE_COMM_EST: 322 event.event = IB_EVENT_COMM_EST; 323 break; 324 case MLX5_EVENT_TYPE_SQ_DRAINED: 325 event.event = IB_EVENT_SQ_DRAINED; 326 break; 327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 328 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 329 break; 330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 331 event.event = IB_EVENT_QP_FATAL; 332 break; 333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 334 event.event = IB_EVENT_PATH_MIG_ERR; 335 break; 336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 337 event.event = IB_EVENT_QP_REQ_ERR; 338 break; 339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 340 event.event = IB_EVENT_QP_ACCESS_ERR; 341 break; 342 default: 343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 344 return; 345 } 346 347 ibqp->event_handler(&event, ibqp->qp_context); 348 } 349 } 350 351 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 353 { 354 int wqe_size; 355 int wq_size; 356 357 /* Sanity check RQ size before proceeding */ 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 359 return -EINVAL; 360 361 if (!has_rq) { 362 qp->rq.max_gs = 0; 363 qp->rq.wqe_cnt = 0; 364 qp->rq.wqe_shift = 0; 365 cap->max_recv_wr = 0; 366 cap->max_recv_sge = 0; 367 } else { 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 369 370 if (ucmd) { 371 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 373 return -EINVAL; 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 375 if ((1 << qp->rq.wqe_shift) / 376 sizeof(struct mlx5_wqe_data_seg) < 377 wq_sig) 378 return -EINVAL; 379 qp->rq.max_gs = 380 (1 << qp->rq.wqe_shift) / 381 sizeof(struct mlx5_wqe_data_seg) - 382 wq_sig; 383 qp->rq.max_post = qp->rq.wqe_cnt; 384 } else { 385 wqe_size = 386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 387 0; 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 389 wqe_size = roundup_pow_of_two(wqe_size); 390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 392 qp->rq.wqe_cnt = wq_size / wqe_size; 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 395 wqe_size, 396 MLX5_CAP_GEN(dev->mdev, 397 max_wqe_sz_rq)); 398 return -EINVAL; 399 } 400 qp->rq.wqe_shift = ilog2(wqe_size); 401 qp->rq.max_gs = 402 (1 << qp->rq.wqe_shift) / 403 sizeof(struct mlx5_wqe_data_seg) - 404 wq_sig; 405 qp->rq.max_post = qp->rq.wqe_cnt; 406 } 407 } 408 409 return 0; 410 } 411 412 static int sq_overhead(struct ib_qp_init_attr *attr) 413 { 414 int size = 0; 415 416 switch (attr->qp_type) { 417 case IB_QPT_XRC_INI: 418 size += sizeof(struct mlx5_wqe_xrc_seg); 419 fallthrough; 420 case IB_QPT_RC: 421 size += sizeof(struct mlx5_wqe_ctrl_seg) + 422 max(sizeof(struct mlx5_wqe_atomic_seg) + 423 sizeof(struct mlx5_wqe_raddr_seg), 424 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 425 sizeof(struct mlx5_mkey_seg) + 426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 427 MLX5_IB_UMR_OCTOWORD); 428 break; 429 430 case IB_QPT_XRC_TGT: 431 return 0; 432 433 case IB_QPT_UC: 434 size += sizeof(struct mlx5_wqe_ctrl_seg) + 435 max(sizeof(struct mlx5_wqe_raddr_seg), 436 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 437 sizeof(struct mlx5_mkey_seg)); 438 break; 439 440 case IB_QPT_UD: 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 442 size += sizeof(struct mlx5_wqe_eth_pad) + 443 sizeof(struct mlx5_wqe_eth_seg); 444 fallthrough; 445 case IB_QPT_SMI: 446 case MLX5_IB_QPT_HW_GSI: 447 size += sizeof(struct mlx5_wqe_ctrl_seg) + 448 sizeof(struct mlx5_wqe_datagram_seg); 449 break; 450 451 case MLX5_IB_QPT_REG_UMR: 452 size += sizeof(struct mlx5_wqe_ctrl_seg) + 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 454 sizeof(struct mlx5_mkey_seg); 455 break; 456 457 default: 458 return -EINVAL; 459 } 460 461 return size; 462 } 463 464 static int calc_send_wqe(struct ib_qp_init_attr *attr) 465 { 466 int inl_size = 0; 467 int size; 468 469 size = sq_overhead(attr); 470 if (size < 0) 471 return size; 472 473 if (attr->cap.max_inline_data) { 474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 475 attr->cap.max_inline_data; 476 } 477 478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 481 return MLX5_SIG_WQE_SIZE; 482 else 483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 484 } 485 486 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 487 { 488 int max_sge; 489 490 if (attr->qp_type == IB_QPT_RC) 491 max_sge = (min_t(int, wqe_size, 512) - 492 sizeof(struct mlx5_wqe_ctrl_seg) - 493 sizeof(struct mlx5_wqe_raddr_seg)) / 494 sizeof(struct mlx5_wqe_data_seg); 495 else if (attr->qp_type == IB_QPT_XRC_INI) 496 max_sge = (min_t(int, wqe_size, 512) - 497 sizeof(struct mlx5_wqe_ctrl_seg) - 498 sizeof(struct mlx5_wqe_xrc_seg) - 499 sizeof(struct mlx5_wqe_raddr_seg)) / 500 sizeof(struct mlx5_wqe_data_seg); 501 else 502 max_sge = (wqe_size - sq_overhead(attr)) / 503 sizeof(struct mlx5_wqe_data_seg); 504 505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 506 sizeof(struct mlx5_wqe_data_seg)); 507 } 508 509 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 510 struct mlx5_ib_qp *qp) 511 { 512 int wqe_size; 513 int wq_size; 514 515 if (!attr->cap.max_send_wr) 516 return 0; 517 518 wqe_size = calc_send_wqe(attr); 519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 520 if (wqe_size < 0) 521 return wqe_size; 522 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 526 return -EINVAL; 527 } 528 529 qp->max_inline_data = wqe_size - sq_overhead(attr) - 530 sizeof(struct mlx5_wqe_inline_seg); 531 attr->cap.max_inline_data = qp->max_inline_data; 532 533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 538 qp->sq.wqe_cnt, 539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 540 return -ENOMEM; 541 } 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 543 qp->sq.max_gs = get_send_sge(attr, wqe_size); 544 if (qp->sq.max_gs < attr->cap.max_send_sge) 545 return -ENOMEM; 546 547 attr->cap.max_send_sge = qp->sq.max_gs; 548 qp->sq.max_post = wq_size / wqe_size; 549 attr->cap.max_send_wr = qp->sq.max_post; 550 551 return wq_size; 552 } 553 554 static int set_user_buf_size(struct mlx5_ib_dev *dev, 555 struct mlx5_ib_qp *qp, 556 struct mlx5_ib_create_qp *ucmd, 557 struct mlx5_ib_qp_base *base, 558 struct ib_qp_init_attr *attr) 559 { 560 int desc_sz = 1 << qp->sq.wqe_shift; 561 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 565 return -EINVAL; 566 } 567 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 570 ucmd->sq_wqe_count); 571 return -EINVAL; 572 } 573 574 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 575 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 578 qp->sq.wqe_cnt, 579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 580 return -EINVAL; 581 } 582 583 if (attr->qp_type == IB_QPT_RAW_PACKET || 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 587 } else { 588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 589 (qp->sq.wqe_cnt << 6); 590 } 591 592 return 0; 593 } 594 595 static int qp_has_rq(struct ib_qp_init_attr *attr) 596 { 597 if (attr->qp_type == IB_QPT_XRC_INI || 598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 599 attr->qp_type == MLX5_IB_QPT_REG_UMR || 600 !attr->cap.max_recv_wr) 601 return 0; 602 603 return 1; 604 } 605 606 enum { 607 /* this is the first blue flame register in the array of bfregs assigned 608 * to a processes. Since we do not use it for blue flame but rather 609 * regular 64 bit doorbells, we do not need a lock for maintaiing 610 * "odd/even" order 611 */ 612 NUM_NON_BLUE_FLAME_BFREGS = 1, 613 }; 614 615 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 616 { 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 618 } 619 620 static int num_med_bfreg(struct mlx5_ib_dev *dev, 621 struct mlx5_bfreg_info *bfregi) 622 { 623 int n; 624 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 626 NUM_NON_BLUE_FLAME_BFREGS; 627 628 return n >= 0 ? n : 0; 629 } 630 631 static int first_med_bfreg(struct mlx5_ib_dev *dev, 632 struct mlx5_bfreg_info *bfregi) 633 { 634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 635 } 636 637 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 638 struct mlx5_bfreg_info *bfregi) 639 { 640 int med; 641 642 med = num_med_bfreg(dev, bfregi); 643 return ++med; 644 } 645 646 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 647 struct mlx5_bfreg_info *bfregi) 648 { 649 int i; 650 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 652 if (!bfregi->count[i]) { 653 bfregi->count[i]++; 654 return i; 655 } 656 } 657 658 return -ENOMEM; 659 } 660 661 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 662 struct mlx5_bfreg_info *bfregi) 663 { 664 int minidx = first_med_bfreg(dev, bfregi); 665 int i; 666 667 if (minidx < 0) 668 return minidx; 669 670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 671 if (bfregi->count[i] < bfregi->count[minidx]) 672 minidx = i; 673 if (!bfregi->count[minidx]) 674 break; 675 } 676 677 bfregi->count[minidx]++; 678 return minidx; 679 } 680 681 static int alloc_bfreg(struct mlx5_ib_dev *dev, 682 struct mlx5_bfreg_info *bfregi) 683 { 684 int bfregn = -ENOMEM; 685 686 if (bfregi->lib_uar_dyn) 687 return -EINVAL; 688 689 mutex_lock(&bfregi->lock); 690 if (bfregi->ver >= 2) { 691 bfregn = alloc_high_class_bfreg(dev, bfregi); 692 if (bfregn < 0) 693 bfregn = alloc_med_class_bfreg(dev, bfregi); 694 } 695 696 if (bfregn < 0) { 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 698 bfregn = 0; 699 bfregi->count[bfregn]++; 700 } 701 mutex_unlock(&bfregi->lock); 702 703 return bfregn; 704 } 705 706 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 707 { 708 mutex_lock(&bfregi->lock); 709 bfregi->count[bfregn]--; 710 mutex_unlock(&bfregi->lock); 711 } 712 713 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 714 { 715 switch (state) { 716 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 723 default: return -1; 724 } 725 } 726 727 static int to_mlx5_st(enum ib_qp_type type) 728 { 729 switch (type) { 730 case IB_QPT_RC: return MLX5_QP_ST_RC; 731 case IB_QPT_UC: return MLX5_QP_ST_UC; 732 case IB_QPT_UD: return MLX5_QP_ST_UD; 733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 734 case IB_QPT_XRC_INI: 735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 736 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 740 default: return -EINVAL; 741 } 742 } 743 744 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 745 struct mlx5_ib_cq *recv_cq); 746 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 747 struct mlx5_ib_cq *recv_cq); 748 749 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, u32 bfregn, 751 bool dyn_bfreg) 752 { 753 unsigned int bfregs_per_sys_page; 754 u32 index_of_sys_page; 755 u32 offset; 756 757 if (bfregi->lib_uar_dyn) 758 return -EINVAL; 759 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 761 MLX5_NON_FP_BFREGS_PER_UAR; 762 index_of_sys_page = bfregn / bfregs_per_sys_page; 763 764 if (dyn_bfreg) { 765 index_of_sys_page += bfregi->num_static_sys_pages; 766 767 if (index_of_sys_page >= bfregi->num_sys_pages) 768 return -EINVAL; 769 770 if (bfregn > bfregi->num_dyn_bfregs || 771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 773 return -EINVAL; 774 } 775 } 776 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 778 return bfregi->sys_pages[index_of_sys_page] + offset; 779 } 780 781 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 782 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 783 { 784 struct mlx5_ib_ucontext *context = 785 rdma_udata_to_drv_context( 786 udata, 787 struct mlx5_ib_ucontext, 788 ibucontext); 789 790 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 791 atomic_dec(&dev->delay_drop.rqs_cnt); 792 793 mlx5_ib_db_unmap_user(context, &rwq->db); 794 ib_umem_release(rwq->umem); 795 } 796 797 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 798 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 799 struct mlx5_ib_create_wq *ucmd) 800 { 801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 802 udata, struct mlx5_ib_ucontext, ibucontext); 803 unsigned long page_size = 0; 804 u32 offset = 0; 805 int err; 806 807 if (!ucmd->buf_addr) 808 return -EINVAL; 809 810 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 811 if (IS_ERR(rwq->umem)) { 812 mlx5_ib_dbg(dev, "umem_get failed\n"); 813 err = PTR_ERR(rwq->umem); 814 return err; 815 } 816 817 page_size = mlx5_umem_find_best_quantized_pgoff( 818 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 819 page_offset, 64, &rwq->rq_page_offset); 820 if (!page_size) { 821 mlx5_ib_warn(dev, "bad offset\n"); 822 err = -EINVAL; 823 goto err_umem; 824 } 825 826 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 827 rwq->page_shift = order_base_2(page_size); 828 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 829 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 830 831 mlx5_ib_dbg( 832 dev, 833 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 834 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 835 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 836 offset); 837 838 err = mlx5_ib_db_map_user(ucontext, ucmd->db_addr, &rwq->db); 839 if (err) { 840 mlx5_ib_dbg(dev, "map failed\n"); 841 goto err_umem; 842 } 843 844 return 0; 845 846 err_umem: 847 ib_umem_release(rwq->umem); 848 return err; 849 } 850 851 static int adjust_bfregn(struct mlx5_ib_dev *dev, 852 struct mlx5_bfreg_info *bfregi, int bfregn) 853 { 854 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 855 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 856 } 857 858 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 859 struct mlx5_ib_qp *qp, struct ib_udata *udata, 860 struct ib_qp_init_attr *attr, u32 **in, 861 struct mlx5_ib_create_qp_resp *resp, int *inlen, 862 struct mlx5_ib_qp_base *base, 863 struct mlx5_ib_create_qp *ucmd) 864 { 865 struct mlx5_ib_ucontext *context; 866 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 867 unsigned int page_offset_quantized = 0; 868 unsigned long page_size = 0; 869 int uar_index = 0; 870 int bfregn; 871 int ncont = 0; 872 __be64 *pas; 873 void *qpc; 874 int err; 875 u16 uid; 876 u32 uar_flags; 877 878 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 879 ibucontext); 880 uar_flags = qp->flags_en & 881 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 882 switch (uar_flags) { 883 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 884 uar_index = ucmd->bfreg_index; 885 bfregn = MLX5_IB_INVALID_BFREG; 886 break; 887 case MLX5_QP_FLAG_BFREG_INDEX: 888 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 889 ucmd->bfreg_index, true); 890 if (uar_index < 0) 891 return uar_index; 892 bfregn = MLX5_IB_INVALID_BFREG; 893 break; 894 case 0: 895 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 896 return -EINVAL; 897 bfregn = alloc_bfreg(dev, &context->bfregi); 898 if (bfregn < 0) 899 return bfregn; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 906 if (bfregn != MLX5_IB_INVALID_BFREG) 907 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 908 false); 909 910 qp->rq.offset = 0; 911 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 912 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 913 914 err = set_user_buf_size(dev, qp, ucmd, base, attr); 915 if (err) 916 goto err_bfreg; 917 918 if (ucmd->buf_addr && ubuffer->buf_size) { 919 ubuffer->buf_addr = ucmd->buf_addr; 920 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 921 ubuffer->buf_size, 0); 922 if (IS_ERR(ubuffer->umem)) { 923 err = PTR_ERR(ubuffer->umem); 924 goto err_bfreg; 925 } 926 page_size = mlx5_umem_find_best_quantized_pgoff( 927 ubuffer->umem, qpc, log_page_size, 928 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 929 &page_offset_quantized); 930 if (!page_size) { 931 err = -EINVAL; 932 goto err_umem; 933 } 934 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 935 } else { 936 ubuffer->umem = NULL; 937 } 938 939 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 940 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 941 *in = kvzalloc(*inlen, GFP_KERNEL); 942 if (!*in) { 943 err = -ENOMEM; 944 goto err_umem; 945 } 946 947 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 948 MLX5_SET(create_qp_in, *in, uid, uid); 949 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 950 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 951 if (ubuffer->umem) { 952 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 953 MLX5_SET(qpc, qpc, log_page_size, 954 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 955 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 956 } 957 MLX5_SET(qpc, qpc, uar_page, uar_index); 958 if (bfregn != MLX5_IB_INVALID_BFREG) 959 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 960 else 961 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 962 qp->bfregn = bfregn; 963 964 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &qp->db); 965 if (err) { 966 mlx5_ib_dbg(dev, "map failed\n"); 967 goto err_free; 968 } 969 970 return 0; 971 972 err_free: 973 kvfree(*in); 974 975 err_umem: 976 ib_umem_release(ubuffer->umem); 977 978 err_bfreg: 979 if (bfregn != MLX5_IB_INVALID_BFREG) 980 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 981 return err; 982 } 983 984 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 985 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 986 { 987 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 988 udata, struct mlx5_ib_ucontext, ibucontext); 989 990 if (udata) { 991 /* User QP */ 992 mlx5_ib_db_unmap_user(context, &qp->db); 993 ib_umem_release(base->ubuffer.umem); 994 995 /* 996 * Free only the BFREGs which are handled by the kernel. 997 * BFREGs of UARs allocated dynamically are handled by user. 998 */ 999 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1000 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1001 return; 1002 } 1003 1004 /* Kernel QP */ 1005 kvfree(qp->sq.wqe_head); 1006 kvfree(qp->sq.w_list); 1007 kvfree(qp->sq.wrid); 1008 kvfree(qp->sq.wr_data); 1009 kvfree(qp->rq.wrid); 1010 if (qp->db.db) 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 if (qp->buf.frags) 1013 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1014 } 1015 1016 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1017 struct ib_qp_init_attr *init_attr, 1018 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1019 struct mlx5_ib_qp_base *base) 1020 { 1021 int uar_index; 1022 void *qpc; 1023 int err; 1024 1025 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1026 qp->bf.bfreg = &dev->fp_bfreg; 1027 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1028 qp->bf.bfreg = &dev->wc_bfreg; 1029 else 1030 qp->bf.bfreg = &dev->bfreg; 1031 1032 /* We need to divide by two since each register is comprised of 1033 * two buffers of identical size, namely odd and even 1034 */ 1035 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1036 uar_index = qp->bf.bfreg->index; 1037 1038 err = calc_sq_size(dev, init_attr, qp); 1039 if (err < 0) { 1040 mlx5_ib_dbg(dev, "err %d\n", err); 1041 return err; 1042 } 1043 1044 qp->rq.offset = 0; 1045 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1046 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1047 1048 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1049 &qp->buf, dev->mdev->priv.numa_node); 1050 if (err) { 1051 mlx5_ib_dbg(dev, "err %d\n", err); 1052 return err; 1053 } 1054 1055 if (qp->rq.wqe_cnt) 1056 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1057 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1058 1059 if (qp->sq.wqe_cnt) { 1060 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1061 MLX5_SEND_WQE_BB; 1062 mlx5_init_fbc_offset(qp->buf.frags + 1063 (qp->sq.offset / PAGE_SIZE), 1064 ilog2(MLX5_SEND_WQE_BB), 1065 ilog2(qp->sq.wqe_cnt), 1066 sq_strides_offset, &qp->sq.fbc); 1067 1068 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1069 } 1070 1071 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1072 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1073 *in = kvzalloc(*inlen, GFP_KERNEL); 1074 if (!*in) { 1075 err = -ENOMEM; 1076 goto err_buf; 1077 } 1078 1079 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1080 MLX5_SET(qpc, qpc, uar_page, uar_index); 1081 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1082 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1083 1084 /* Set "fast registration enabled" for all kernel QPs */ 1085 MLX5_SET(qpc, qpc, fre, 1); 1086 MLX5_SET(qpc, qpc, rlky, 1); 1087 1088 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1089 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1090 1091 mlx5_fill_page_frag_array(&qp->buf, 1092 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1093 *in, pas)); 1094 1095 err = mlx5_db_alloc(dev->mdev, &qp->db); 1096 if (err) { 1097 mlx5_ib_dbg(dev, "err %d\n", err); 1098 goto err_free; 1099 } 1100 1101 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1102 sizeof(*qp->sq.wrid), GFP_KERNEL); 1103 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1104 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1105 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1106 sizeof(*qp->rq.wrid), GFP_KERNEL); 1107 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1108 sizeof(*qp->sq.w_list), GFP_KERNEL); 1109 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1110 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1111 1112 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1113 !qp->sq.w_list || !qp->sq.wqe_head) { 1114 err = -ENOMEM; 1115 goto err_wrid; 1116 } 1117 1118 return 0; 1119 1120 err_wrid: 1121 kvfree(qp->sq.wqe_head); 1122 kvfree(qp->sq.w_list); 1123 kvfree(qp->sq.wrid); 1124 kvfree(qp->sq.wr_data); 1125 kvfree(qp->rq.wrid); 1126 mlx5_db_free(dev->mdev, &qp->db); 1127 1128 err_free: 1129 kvfree(*in); 1130 1131 err_buf: 1132 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1133 return err; 1134 } 1135 1136 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1137 { 1138 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1139 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1140 return MLX5_SRQ_RQ; 1141 else if (!qp->has_rq) 1142 return MLX5_ZERO_LEN_RQ; 1143 1144 return MLX5_NON_ZERO_RQ; 1145 } 1146 1147 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1148 struct mlx5_ib_qp *qp, 1149 struct mlx5_ib_sq *sq, u32 tdn, 1150 struct ib_pd *pd) 1151 { 1152 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1153 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1154 1155 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1156 MLX5_SET(tisc, tisc, transport_domain, tdn); 1157 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1158 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1159 1160 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1161 } 1162 1163 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1164 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1165 { 1166 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1167 } 1168 1169 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1170 { 1171 if (sq->flow_rule) 1172 mlx5_del_flow_rules(sq->flow_rule); 1173 sq->flow_rule = NULL; 1174 } 1175 1176 static bool fr_supported(int ts_cap) 1177 { 1178 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1179 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1180 } 1181 1182 static int get_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1183 bool fr_sup, bool rt_sup) 1184 { 1185 if (cq->private_flags & MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS) { 1186 if (!rt_sup) { 1187 mlx5_ib_dbg(dev, 1188 "Real time TS format is not supported\n"); 1189 return -EOPNOTSUPP; 1190 } 1191 return MLX5_TIMESTAMP_FORMAT_REAL_TIME; 1192 } 1193 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1194 if (!fr_sup) { 1195 mlx5_ib_dbg(dev, 1196 "Free running TS format is not supported\n"); 1197 return -EOPNOTSUPP; 1198 } 1199 return MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1200 } 1201 return fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1202 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1203 } 1204 1205 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *recv_cq) 1206 { 1207 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, rq_ts_format); 1208 1209 return get_ts_format(dev, recv_cq, fr_supported(ts_cap), 1210 rt_supported(ts_cap)); 1211 } 1212 1213 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1214 { 1215 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, sq_ts_format); 1216 1217 return get_ts_format(dev, send_cq, fr_supported(ts_cap), 1218 rt_supported(ts_cap)); 1219 } 1220 1221 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1222 struct mlx5_ib_cq *recv_cq) 1223 { 1224 u8 ts_cap = MLX5_CAP_ROCE(dev->mdev, qp_ts_format); 1225 bool fr_sup = fr_supported(ts_cap); 1226 bool rt_sup = rt_supported(ts_cap); 1227 u8 default_ts = fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1228 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1229 int send_ts_format = 1230 send_cq ? get_ts_format(dev, send_cq, fr_sup, rt_sup) : 1231 default_ts; 1232 int recv_ts_format = 1233 recv_cq ? get_ts_format(dev, recv_cq, fr_sup, rt_sup) : 1234 default_ts; 1235 1236 if (send_ts_format < 0 || recv_ts_format < 0) 1237 return -EOPNOTSUPP; 1238 1239 if (send_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1240 recv_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1241 send_ts_format != recv_ts_format) { 1242 mlx5_ib_dbg( 1243 dev, 1244 "The send ts_format does not match the receive ts_format\n"); 1245 return -EOPNOTSUPP; 1246 } 1247 1248 return send_ts_format == default_ts ? recv_ts_format : send_ts_format; 1249 } 1250 1251 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1252 struct ib_udata *udata, 1253 struct mlx5_ib_sq *sq, void *qpin, 1254 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1255 { 1256 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1257 __be64 *pas; 1258 void *in; 1259 void *sqc; 1260 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1261 void *wq; 1262 int inlen; 1263 int err; 1264 unsigned int page_offset_quantized; 1265 unsigned long page_size; 1266 int ts_format; 1267 1268 ts_format = get_sq_ts_format(dev, cq); 1269 if (ts_format < 0) 1270 return ts_format; 1271 1272 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1273 ubuffer->buf_size, 0); 1274 if (IS_ERR(sq->ubuffer.umem)) 1275 return PTR_ERR(sq->ubuffer.umem); 1276 page_size = mlx5_umem_find_best_quantized_pgoff( 1277 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1278 page_offset, 64, &page_offset_quantized); 1279 if (!page_size) { 1280 err = -EINVAL; 1281 goto err_umem; 1282 } 1283 1284 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1285 sizeof(u64) * 1286 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1287 in = kvzalloc(inlen, GFP_KERNEL); 1288 if (!in) { 1289 err = -ENOMEM; 1290 goto err_umem; 1291 } 1292 1293 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1294 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1295 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1296 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1297 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1298 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1299 MLX5_SET(sqc, sqc, ts_format, ts_format); 1300 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1301 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1302 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1303 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1304 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1305 MLX5_CAP_ETH(dev->mdev, swp)) 1306 MLX5_SET(sqc, sqc, allow_swp, 1); 1307 1308 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1309 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1310 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1311 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1312 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1313 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1314 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1315 MLX5_SET(wq, wq, log_wq_pg_sz, 1316 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1317 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1318 1319 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1320 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1321 1322 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1323 1324 kvfree(in); 1325 1326 if (err) 1327 goto err_umem; 1328 1329 return 0; 1330 1331 err_umem: 1332 ib_umem_release(sq->ubuffer.umem); 1333 sq->ubuffer.umem = NULL; 1334 1335 return err; 1336 } 1337 1338 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1339 struct mlx5_ib_sq *sq) 1340 { 1341 destroy_flow_rule_vport_sq(sq); 1342 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1343 ib_umem_release(sq->ubuffer.umem); 1344 } 1345 1346 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1347 struct mlx5_ib_rq *rq, void *qpin, 1348 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1349 { 1350 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1351 __be64 *pas; 1352 void *in; 1353 void *rqc; 1354 void *wq; 1355 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1356 struct ib_umem *umem = rq->base.ubuffer.umem; 1357 unsigned int page_offset_quantized; 1358 unsigned long page_size = 0; 1359 int ts_format; 1360 size_t inlen; 1361 int err; 1362 1363 ts_format = get_rq_ts_format(dev, cq); 1364 if (ts_format < 0) 1365 return ts_format; 1366 1367 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1368 MLX5_ADAPTER_PAGE_SHIFT, 1369 page_offset, 64, 1370 &page_offset_quantized); 1371 if (!page_size) 1372 return -EINVAL; 1373 1374 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1375 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1376 in = kvzalloc(inlen, GFP_KERNEL); 1377 if (!in) 1378 return -ENOMEM; 1379 1380 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1381 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1382 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1383 MLX5_SET(rqc, rqc, vsd, 1); 1384 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1385 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1386 MLX5_SET(rqc, rqc, ts_format, ts_format); 1387 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1388 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1389 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1390 1391 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1392 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1393 1394 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1395 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1396 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1397 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1398 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1399 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1400 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1401 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1402 MLX5_SET(wq, wq, log_wq_pg_sz, 1403 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1404 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1405 1406 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1407 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1408 1409 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1410 1411 kvfree(in); 1412 1413 return err; 1414 } 1415 1416 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1417 struct mlx5_ib_rq *rq) 1418 { 1419 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1420 } 1421 1422 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1423 struct mlx5_ib_rq *rq, 1424 u32 qp_flags_en, 1425 struct ib_pd *pd) 1426 { 1427 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1428 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1429 mlx5_ib_disable_lb(dev, false, true); 1430 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1431 } 1432 1433 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1434 struct mlx5_ib_rq *rq, u32 tdn, 1435 u32 *qp_flags_en, struct ib_pd *pd, 1436 u32 *out) 1437 { 1438 u8 lb_flag = 0; 1439 u32 *in; 1440 void *tirc; 1441 int inlen; 1442 int err; 1443 1444 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1445 in = kvzalloc(inlen, GFP_KERNEL); 1446 if (!in) 1447 return -ENOMEM; 1448 1449 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1450 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1451 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1452 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1453 MLX5_SET(tirc, tirc, transport_domain, tdn); 1454 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1455 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1456 1457 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1458 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1459 1460 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1461 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1462 1463 if (dev->is_rep) { 1464 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1465 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1466 } 1467 1468 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1469 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1470 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1471 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1472 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1473 err = mlx5_ib_enable_lb(dev, false, true); 1474 1475 if (err) 1476 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1477 } 1478 kvfree(in); 1479 1480 return err; 1481 } 1482 1483 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1484 u32 *in, size_t inlen, struct ib_pd *pd, 1485 struct ib_udata *udata, 1486 struct mlx5_ib_create_qp_resp *resp, 1487 struct ib_qp_init_attr *init_attr) 1488 { 1489 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1490 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1491 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1492 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1493 udata, struct mlx5_ib_ucontext, ibucontext); 1494 int err; 1495 u32 tdn = mucontext->tdn; 1496 u16 uid = to_mpd(pd)->uid; 1497 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1498 1499 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1500 return -EINVAL; 1501 if (qp->sq.wqe_cnt) { 1502 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1503 if (err) 1504 return err; 1505 1506 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1507 to_mcq(init_attr->send_cq)); 1508 if (err) 1509 goto err_destroy_tis; 1510 1511 if (uid) { 1512 resp->tisn = sq->tisn; 1513 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1514 resp->sqn = sq->base.mqp.qpn; 1515 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1516 } 1517 1518 sq->base.container_mibqp = qp; 1519 sq->base.mqp.event = mlx5_ib_qp_event; 1520 } 1521 1522 if (qp->rq.wqe_cnt) { 1523 rq->base.container_mibqp = qp; 1524 1525 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1526 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1527 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1528 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1529 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1530 to_mcq(init_attr->recv_cq)); 1531 if (err) 1532 goto err_destroy_sq; 1533 1534 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1535 out); 1536 if (err) 1537 goto err_destroy_rq; 1538 1539 if (uid) { 1540 resp->rqn = rq->base.mqp.qpn; 1541 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1542 resp->tirn = rq->tirn; 1543 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1544 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1545 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1546 resp->tir_icm_addr = MLX5_GET( 1547 create_tir_out, out, icm_address_31_0); 1548 resp->tir_icm_addr |= 1549 (u64)MLX5_GET(create_tir_out, out, 1550 icm_address_39_32) 1551 << 32; 1552 resp->tir_icm_addr |= 1553 (u64)MLX5_GET(create_tir_out, out, 1554 icm_address_63_40) 1555 << 40; 1556 resp->comp_mask |= 1557 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1558 } 1559 } 1560 } 1561 1562 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1563 rq->base.mqp.qpn; 1564 return 0; 1565 1566 err_destroy_rq: 1567 destroy_raw_packet_qp_rq(dev, rq); 1568 err_destroy_sq: 1569 if (!qp->sq.wqe_cnt) 1570 return err; 1571 destroy_raw_packet_qp_sq(dev, sq); 1572 err_destroy_tis: 1573 destroy_raw_packet_qp_tis(dev, sq, pd); 1574 1575 return err; 1576 } 1577 1578 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1579 struct mlx5_ib_qp *qp) 1580 { 1581 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1582 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1583 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1584 1585 if (qp->rq.wqe_cnt) { 1586 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1587 destroy_raw_packet_qp_rq(dev, rq); 1588 } 1589 1590 if (qp->sq.wqe_cnt) { 1591 destroy_raw_packet_qp_sq(dev, sq); 1592 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1593 } 1594 } 1595 1596 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1597 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1598 { 1599 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1600 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1601 1602 sq->sq = &qp->sq; 1603 rq->rq = &qp->rq; 1604 sq->doorbell = &qp->db; 1605 rq->doorbell = &qp->db; 1606 } 1607 1608 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1609 { 1610 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1611 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1612 mlx5_ib_disable_lb(dev, false, true); 1613 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1614 to_mpd(qp->ibqp.pd)->uid); 1615 } 1616 1617 struct mlx5_create_qp_params { 1618 struct ib_udata *udata; 1619 size_t inlen; 1620 size_t outlen; 1621 size_t ucmd_size; 1622 void *ucmd; 1623 u8 is_rss_raw : 1; 1624 struct ib_qp_init_attr *attr; 1625 u32 uidx; 1626 struct mlx5_ib_create_qp_resp resp; 1627 }; 1628 1629 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1630 struct mlx5_ib_qp *qp, 1631 struct mlx5_create_qp_params *params) 1632 { 1633 struct ib_qp_init_attr *init_attr = params->attr; 1634 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1635 struct ib_udata *udata = params->udata; 1636 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1637 udata, struct mlx5_ib_ucontext, ibucontext); 1638 int inlen; 1639 int outlen; 1640 int err; 1641 u32 *in; 1642 u32 *out; 1643 void *tirc; 1644 void *hfso; 1645 u32 selected_fields = 0; 1646 u32 outer_l4; 1647 u32 tdn = mucontext->tdn; 1648 u8 lb_flag = 0; 1649 1650 if (ucmd->comp_mask) { 1651 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1652 return -EOPNOTSUPP; 1653 } 1654 1655 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1656 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1657 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1658 return -EOPNOTSUPP; 1659 } 1660 1661 if (dev->is_rep) 1662 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1663 1664 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1665 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1666 1667 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1668 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1669 1670 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1671 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1672 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1673 if (!in) 1674 return -ENOMEM; 1675 1676 out = in + MLX5_ST_SZ_DW(create_tir_in); 1677 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1678 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1679 MLX5_SET(tirc, tirc, disp_type, 1680 MLX5_TIRC_DISP_TYPE_INDIRECT); 1681 MLX5_SET(tirc, tirc, indirect_table, 1682 init_attr->rwq_ind_tbl->ind_tbl_num); 1683 MLX5_SET(tirc, tirc, transport_domain, tdn); 1684 1685 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1686 1687 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1688 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1689 1690 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1691 1692 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1693 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1694 else 1695 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1696 1697 switch (ucmd->rx_hash_function) { 1698 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1699 { 1700 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1701 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1702 1703 if (len != ucmd->rx_key_len) { 1704 err = -EINVAL; 1705 goto err; 1706 } 1707 1708 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1709 memcpy(rss_key, ucmd->rx_hash_key, len); 1710 break; 1711 } 1712 default: 1713 err = -EOPNOTSUPP; 1714 goto err; 1715 } 1716 1717 if (!ucmd->rx_hash_fields_mask) { 1718 /* special case when this TIR serves as steering entry without hashing */ 1719 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1720 goto create_tir; 1721 err = -EINVAL; 1722 goto err; 1723 } 1724 1725 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1726 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1727 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1728 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1729 err = -EINVAL; 1730 goto err; 1731 } 1732 1733 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1734 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1735 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1736 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1737 MLX5_L3_PROT_TYPE_IPV4); 1738 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1739 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1740 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1741 MLX5_L3_PROT_TYPE_IPV6); 1742 1743 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1744 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1745 << 0 | 1746 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1747 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1748 << 1 | 1749 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1750 1751 /* Check that only one l4 protocol is set */ 1752 if (outer_l4 & (outer_l4 - 1)) { 1753 err = -EINVAL; 1754 goto err; 1755 } 1756 1757 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1758 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1759 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1760 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1761 MLX5_L4_PROT_TYPE_TCP); 1762 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1763 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1764 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1765 MLX5_L4_PROT_TYPE_UDP); 1766 1767 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1768 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1769 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1770 1771 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1772 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1773 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1774 1775 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1776 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1777 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1778 1779 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1780 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1781 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1782 1783 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1784 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1785 1786 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1787 1788 create_tir: 1789 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1790 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1791 1792 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1793 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1794 err = mlx5_ib_enable_lb(dev, false, true); 1795 1796 if (err) 1797 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1798 to_mpd(pd)->uid); 1799 } 1800 1801 if (err) 1802 goto err; 1803 1804 if (mucontext->devx_uid) { 1805 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1806 params->resp.tirn = qp->rss_qp.tirn; 1807 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1808 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1809 params->resp.tir_icm_addr = 1810 MLX5_GET(create_tir_out, out, icm_address_31_0); 1811 params->resp.tir_icm_addr |= 1812 (u64)MLX5_GET(create_tir_out, out, 1813 icm_address_39_32) 1814 << 32; 1815 params->resp.tir_icm_addr |= 1816 (u64)MLX5_GET(create_tir_out, out, 1817 icm_address_63_40) 1818 << 40; 1819 params->resp.comp_mask |= 1820 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1821 } 1822 } 1823 1824 kvfree(in); 1825 /* qpn is reserved for that QP */ 1826 qp->trans_qp.base.mqp.qpn = 0; 1827 qp->is_rss = true; 1828 return 0; 1829 1830 err: 1831 kvfree(in); 1832 return err; 1833 } 1834 1835 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1836 struct mlx5_ib_qp *qp, 1837 struct ib_qp_init_attr *init_attr, 1838 void *qpc) 1839 { 1840 int scqe_sz; 1841 bool allow_scat_cqe = false; 1842 1843 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1844 1845 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1846 return; 1847 1848 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1849 if (scqe_sz == 128) { 1850 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1851 return; 1852 } 1853 1854 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1855 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1856 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1857 } 1858 1859 static int atomic_size_to_mode(int size_mask) 1860 { 1861 /* driver does not support atomic_size > 256B 1862 * and does not know how to translate bigger sizes 1863 */ 1864 int supported_size_mask = size_mask & 0x1ff; 1865 int log_max_size; 1866 1867 if (!supported_size_mask) 1868 return -EOPNOTSUPP; 1869 1870 log_max_size = __fls(supported_size_mask); 1871 1872 if (log_max_size > 3) 1873 return log_max_size; 1874 1875 return MLX5_ATOMIC_MODE_8B; 1876 } 1877 1878 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1879 enum ib_qp_type qp_type) 1880 { 1881 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1882 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1883 int atomic_mode = -EOPNOTSUPP; 1884 int atomic_size_mask; 1885 1886 if (!atomic) 1887 return -EOPNOTSUPP; 1888 1889 if (qp_type == MLX5_IB_QPT_DCT) 1890 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1891 else 1892 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1893 1894 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1895 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1896 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1897 1898 if (atomic_mode <= 0 && 1899 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1900 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1901 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1902 1903 return atomic_mode; 1904 } 1905 1906 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1907 struct mlx5_create_qp_params *params) 1908 { 1909 struct ib_qp_init_attr *attr = params->attr; 1910 u32 uidx = params->uidx; 1911 struct mlx5_ib_resources *devr = &dev->devr; 1912 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1913 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1914 struct mlx5_core_dev *mdev = dev->mdev; 1915 struct mlx5_ib_qp_base *base; 1916 unsigned long flags; 1917 void *qpc; 1918 u32 *in; 1919 int err; 1920 1921 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1922 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1923 1924 in = kvzalloc(inlen, GFP_KERNEL); 1925 if (!in) 1926 return -ENOMEM; 1927 1928 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1929 1930 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 1931 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1932 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 1933 1934 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1935 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1936 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1937 MLX5_SET(qpc, qpc, cd_master, 1); 1938 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1939 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1940 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1941 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1942 1943 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1944 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 1945 MLX5_SET(qpc, qpc, no_sq, 1); 1946 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1947 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1948 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1949 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 1950 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1951 1952 /* 0xffffff means we ask to work with cqe version 0 */ 1953 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1954 MLX5_SET(qpc, qpc, user_index, uidx); 1955 1956 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1957 MLX5_SET(qpc, qpc, end_padding_mode, 1958 MLX5_WQ_END_PAD_MODE_ALIGN); 1959 /* Special case to clean flag */ 1960 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 1961 } 1962 1963 base = &qp->trans_qp.base; 1964 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 1965 kvfree(in); 1966 if (err) 1967 return err; 1968 1969 base->container_mibqp = qp; 1970 base->mqp.event = mlx5_ib_qp_event; 1971 if (MLX5_CAP_GEN(mdev, ece_support)) 1972 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 1973 1974 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1975 list_add_tail(&qp->qps_list, &dev->qp_list); 1976 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1977 1978 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 1979 return 0; 1980 } 1981 1982 static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1983 struct mlx5_ib_qp *qp, 1984 struct mlx5_create_qp_params *params) 1985 { 1986 struct ib_qp_init_attr *init_attr = params->attr; 1987 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1988 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1989 struct ib_udata *udata = params->udata; 1990 u32 uidx = params->uidx; 1991 struct mlx5_ib_resources *devr = &dev->devr; 1992 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1993 struct mlx5_core_dev *mdev = dev->mdev; 1994 struct mlx5_ib_cq *send_cq; 1995 struct mlx5_ib_cq *recv_cq; 1996 unsigned long flags; 1997 struct mlx5_ib_qp_base *base; 1998 int ts_format; 1999 int mlx5_st; 2000 void *qpc; 2001 u32 *in; 2002 int err; 2003 2004 spin_lock_init(&qp->sq.lock); 2005 spin_lock_init(&qp->rq.lock); 2006 2007 mlx5_st = to_mlx5_st(qp->type); 2008 if (mlx5_st < 0) 2009 return -EINVAL; 2010 2011 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2012 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2013 2014 base = &qp->trans_qp.base; 2015 2016 qp->has_rq = qp_has_rq(init_attr); 2017 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2018 if (err) { 2019 mlx5_ib_dbg(dev, "err %d\n", err); 2020 return err; 2021 } 2022 2023 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2024 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2025 return -EINVAL; 2026 2027 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2028 return -EINVAL; 2029 2030 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2031 to_mcq(init_attr->recv_cq)); 2032 2033 if (ts_format < 0) 2034 return ts_format; 2035 2036 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2037 &inlen, base, ucmd); 2038 if (err) 2039 return err; 2040 2041 if (MLX5_CAP_GEN(mdev, ece_support)) 2042 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2043 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2044 2045 MLX5_SET(qpc, qpc, st, mlx5_st); 2046 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2047 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2048 2049 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2050 MLX5_SET(qpc, qpc, wq_signature, 1); 2051 2052 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2053 MLX5_SET(qpc, qpc, cd_master, 1); 2054 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2055 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2056 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) 2057 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2058 2059 if (qp->rq.wqe_cnt) { 2060 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2061 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2062 } 2063 2064 if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) { 2065 MLX5_SET(qpc, qpc, log_num_dci_stream_channels, 2066 ucmd->dci_streams.log_num_concurent); 2067 MLX5_SET(qpc, qpc, log_num_dci_errored_streams, 2068 ucmd->dci_streams.log_num_errored); 2069 } 2070 2071 MLX5_SET(qpc, qpc, ts_format, ts_format); 2072 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2073 2074 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2075 2076 /* Set default resources */ 2077 if (init_attr->srq) { 2078 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2079 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2080 to_msrq(init_attr->srq)->msrq.srqn); 2081 } else { 2082 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2083 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2084 to_msrq(devr->s1)->msrq.srqn); 2085 } 2086 2087 if (init_attr->send_cq) 2088 MLX5_SET(qpc, qpc, cqn_snd, 2089 to_mcq(init_attr->send_cq)->mcq.cqn); 2090 2091 if (init_attr->recv_cq) 2092 MLX5_SET(qpc, qpc, cqn_rcv, 2093 to_mcq(init_attr->recv_cq)->mcq.cqn); 2094 2095 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2096 2097 /* 0xffffff means we ask to work with cqe version 0 */ 2098 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2099 MLX5_SET(qpc, qpc, user_index, uidx); 2100 2101 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2102 MLX5_SET(qpc, qpc, end_padding_mode, 2103 MLX5_WQ_END_PAD_MODE_ALIGN); 2104 /* Special case to clean flag */ 2105 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2106 } 2107 2108 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2109 2110 kvfree(in); 2111 if (err) 2112 goto err_create; 2113 2114 base->container_mibqp = qp; 2115 base->mqp.event = mlx5_ib_qp_event; 2116 if (MLX5_CAP_GEN(mdev, ece_support)) 2117 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2118 2119 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2120 &send_cq, &recv_cq); 2121 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2122 mlx5_ib_lock_cqs(send_cq, recv_cq); 2123 /* Maintain device to QPs access, needed for further handling via reset 2124 * flow 2125 */ 2126 list_add_tail(&qp->qps_list, &dev->qp_list); 2127 /* Maintain CQ to QPs access, needed for further handling via reset flow 2128 */ 2129 if (send_cq) 2130 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2131 if (recv_cq) 2132 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2133 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2134 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2135 2136 return 0; 2137 2138 err_create: 2139 destroy_qp(dev, qp, base, udata); 2140 return err; 2141 } 2142 2143 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2144 struct mlx5_ib_qp *qp, 2145 struct mlx5_create_qp_params *params) 2146 { 2147 struct ib_qp_init_attr *init_attr = params->attr; 2148 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2149 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2150 struct ib_udata *udata = params->udata; 2151 u32 uidx = params->uidx; 2152 struct mlx5_ib_resources *devr = &dev->devr; 2153 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2154 struct mlx5_core_dev *mdev = dev->mdev; 2155 struct mlx5_ib_cq *send_cq; 2156 struct mlx5_ib_cq *recv_cq; 2157 unsigned long flags; 2158 struct mlx5_ib_qp_base *base; 2159 int ts_format; 2160 int mlx5_st; 2161 void *qpc; 2162 u32 *in; 2163 int err; 2164 2165 spin_lock_init(&qp->sq.lock); 2166 spin_lock_init(&qp->rq.lock); 2167 2168 mlx5_st = to_mlx5_st(qp->type); 2169 if (mlx5_st < 0) 2170 return -EINVAL; 2171 2172 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2173 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2174 2175 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2176 qp->underlay_qpn = init_attr->source_qpn; 2177 2178 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2179 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2180 &qp->raw_packet_qp.rq.base : 2181 &qp->trans_qp.base; 2182 2183 qp->has_rq = qp_has_rq(init_attr); 2184 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2185 if (err) { 2186 mlx5_ib_dbg(dev, "err %d\n", err); 2187 return err; 2188 } 2189 2190 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2191 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2192 return -EINVAL; 2193 2194 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2195 return -EINVAL; 2196 2197 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2198 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2199 to_mcq(init_attr->recv_cq)); 2200 if (ts_format < 0) 2201 return ts_format; 2202 } 2203 2204 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2205 &inlen, base, ucmd); 2206 if (err) 2207 return err; 2208 2209 if (is_sqp(init_attr->qp_type)) 2210 qp->port = init_attr->port_num; 2211 2212 if (MLX5_CAP_GEN(mdev, ece_support)) 2213 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2214 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2215 2216 MLX5_SET(qpc, qpc, st, mlx5_st); 2217 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2218 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2219 2220 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2221 MLX5_SET(qpc, qpc, wq_signature, 1); 2222 2223 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2224 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2225 2226 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2227 MLX5_SET(qpc, qpc, cd_master, 1); 2228 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2229 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2230 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2231 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2232 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2233 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2234 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2235 (init_attr->qp_type == IB_QPT_RC || 2236 init_attr->qp_type == IB_QPT_UC)) { 2237 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2238 2239 MLX5_SET(qpc, qpc, cs_res, 2240 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2241 MLX5_RES_SCAT_DATA32_CQE); 2242 } 2243 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2244 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2245 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2246 2247 if (qp->rq.wqe_cnt) { 2248 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2249 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2250 } 2251 2252 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2253 MLX5_SET(qpc, qpc, ts_format, ts_format); 2254 2255 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2256 2257 if (qp->sq.wqe_cnt) { 2258 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2259 } else { 2260 MLX5_SET(qpc, qpc, no_sq, 1); 2261 if (init_attr->srq && 2262 init_attr->srq->srq_type == IB_SRQT_TM) 2263 MLX5_SET(qpc, qpc, offload_type, 2264 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2265 } 2266 2267 /* Set default resources */ 2268 switch (init_attr->qp_type) { 2269 case IB_QPT_XRC_INI: 2270 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2271 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2272 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2273 break; 2274 default: 2275 if (init_attr->srq) { 2276 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2277 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2278 } else { 2279 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2280 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2281 } 2282 } 2283 2284 if (init_attr->send_cq) 2285 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2286 2287 if (init_attr->recv_cq) 2288 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2289 2290 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2291 2292 /* 0xffffff means we ask to work with cqe version 0 */ 2293 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2294 MLX5_SET(qpc, qpc, user_index, uidx); 2295 2296 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2297 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2298 MLX5_SET(qpc, qpc, end_padding_mode, 2299 MLX5_WQ_END_PAD_MODE_ALIGN); 2300 /* Special case to clean flag */ 2301 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2302 } 2303 2304 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2305 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2306 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2307 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2308 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2309 ¶ms->resp, init_attr); 2310 } else 2311 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2312 2313 kvfree(in); 2314 if (err) 2315 goto err_create; 2316 2317 base->container_mibqp = qp; 2318 base->mqp.event = mlx5_ib_qp_event; 2319 if (MLX5_CAP_GEN(mdev, ece_support)) 2320 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2321 2322 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2323 &send_cq, &recv_cq); 2324 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2325 mlx5_ib_lock_cqs(send_cq, recv_cq); 2326 /* Maintain device to QPs access, needed for further handling via reset 2327 * flow 2328 */ 2329 list_add_tail(&qp->qps_list, &dev->qp_list); 2330 /* Maintain CQ to QPs access, needed for further handling via reset flow 2331 */ 2332 if (send_cq) 2333 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2334 if (recv_cq) 2335 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2336 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2337 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2338 2339 return 0; 2340 2341 err_create: 2342 destroy_qp(dev, qp, base, udata); 2343 return err; 2344 } 2345 2346 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2347 struct mlx5_ib_qp *qp, 2348 struct mlx5_create_qp_params *params) 2349 { 2350 struct ib_qp_init_attr *attr = params->attr; 2351 u32 uidx = params->uidx; 2352 struct mlx5_ib_resources *devr = &dev->devr; 2353 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2354 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2355 struct mlx5_core_dev *mdev = dev->mdev; 2356 struct mlx5_ib_cq *send_cq; 2357 struct mlx5_ib_cq *recv_cq; 2358 unsigned long flags; 2359 struct mlx5_ib_qp_base *base; 2360 int mlx5_st; 2361 void *qpc; 2362 u32 *in; 2363 int err; 2364 2365 spin_lock_init(&qp->sq.lock); 2366 spin_lock_init(&qp->rq.lock); 2367 2368 mlx5_st = to_mlx5_st(qp->type); 2369 if (mlx5_st < 0) 2370 return -EINVAL; 2371 2372 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2373 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2374 2375 base = &qp->trans_qp.base; 2376 2377 qp->has_rq = qp_has_rq(attr); 2378 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2379 if (err) { 2380 mlx5_ib_dbg(dev, "err %d\n", err); 2381 return err; 2382 } 2383 2384 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2385 if (err) 2386 return err; 2387 2388 if (is_sqp(attr->qp_type)) 2389 qp->port = attr->port_num; 2390 2391 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2392 2393 MLX5_SET(qpc, qpc, st, mlx5_st); 2394 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2395 2396 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2397 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2398 else 2399 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2400 2401 2402 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2403 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2404 2405 if (qp->rq.wqe_cnt) { 2406 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2407 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2408 } 2409 2410 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2411 2412 if (qp->sq.wqe_cnt) 2413 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2414 else 2415 MLX5_SET(qpc, qpc, no_sq, 1); 2416 2417 if (attr->srq) { 2418 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2419 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2420 to_msrq(attr->srq)->msrq.srqn); 2421 } else { 2422 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2423 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2424 to_msrq(devr->s1)->msrq.srqn); 2425 } 2426 2427 if (attr->send_cq) 2428 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2429 2430 if (attr->recv_cq) 2431 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2432 2433 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2434 2435 /* 0xffffff means we ask to work with cqe version 0 */ 2436 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2437 MLX5_SET(qpc, qpc, user_index, uidx); 2438 2439 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2440 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2441 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2442 2443 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2444 kvfree(in); 2445 if (err) 2446 goto err_create; 2447 2448 base->container_mibqp = qp; 2449 base->mqp.event = mlx5_ib_qp_event; 2450 2451 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2452 &send_cq, &recv_cq); 2453 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2454 mlx5_ib_lock_cqs(send_cq, recv_cq); 2455 /* Maintain device to QPs access, needed for further handling via reset 2456 * flow 2457 */ 2458 list_add_tail(&qp->qps_list, &dev->qp_list); 2459 /* Maintain CQ to QPs access, needed for further handling via reset flow 2460 */ 2461 if (send_cq) 2462 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2463 if (recv_cq) 2464 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2465 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2466 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2467 2468 return 0; 2469 2470 err_create: 2471 destroy_qp(dev, qp, base, NULL); 2472 return err; 2473 } 2474 2475 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2476 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2477 { 2478 if (send_cq) { 2479 if (recv_cq) { 2480 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2481 spin_lock(&send_cq->lock); 2482 spin_lock_nested(&recv_cq->lock, 2483 SINGLE_DEPTH_NESTING); 2484 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2485 spin_lock(&send_cq->lock); 2486 __acquire(&recv_cq->lock); 2487 } else { 2488 spin_lock(&recv_cq->lock); 2489 spin_lock_nested(&send_cq->lock, 2490 SINGLE_DEPTH_NESTING); 2491 } 2492 } else { 2493 spin_lock(&send_cq->lock); 2494 __acquire(&recv_cq->lock); 2495 } 2496 } else if (recv_cq) { 2497 spin_lock(&recv_cq->lock); 2498 __acquire(&send_cq->lock); 2499 } else { 2500 __acquire(&send_cq->lock); 2501 __acquire(&recv_cq->lock); 2502 } 2503 } 2504 2505 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2506 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2507 { 2508 if (send_cq) { 2509 if (recv_cq) { 2510 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2511 spin_unlock(&recv_cq->lock); 2512 spin_unlock(&send_cq->lock); 2513 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2514 __release(&recv_cq->lock); 2515 spin_unlock(&send_cq->lock); 2516 } else { 2517 spin_unlock(&send_cq->lock); 2518 spin_unlock(&recv_cq->lock); 2519 } 2520 } else { 2521 __release(&recv_cq->lock); 2522 spin_unlock(&send_cq->lock); 2523 } 2524 } else if (recv_cq) { 2525 __release(&send_cq->lock); 2526 spin_unlock(&recv_cq->lock); 2527 } else { 2528 __release(&recv_cq->lock); 2529 __release(&send_cq->lock); 2530 } 2531 } 2532 2533 static void get_cqs(enum ib_qp_type qp_type, 2534 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2535 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2536 { 2537 switch (qp_type) { 2538 case IB_QPT_XRC_TGT: 2539 *send_cq = NULL; 2540 *recv_cq = NULL; 2541 break; 2542 case MLX5_IB_QPT_REG_UMR: 2543 case IB_QPT_XRC_INI: 2544 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2545 *recv_cq = NULL; 2546 break; 2547 2548 case IB_QPT_SMI: 2549 case MLX5_IB_QPT_HW_GSI: 2550 case IB_QPT_RC: 2551 case IB_QPT_UC: 2552 case IB_QPT_UD: 2553 case IB_QPT_RAW_PACKET: 2554 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2555 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2556 break; 2557 default: 2558 *send_cq = NULL; 2559 *recv_cq = NULL; 2560 break; 2561 } 2562 } 2563 2564 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2565 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2566 u8 lag_tx_affinity); 2567 2568 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2569 struct ib_udata *udata) 2570 { 2571 struct mlx5_ib_cq *send_cq, *recv_cq; 2572 struct mlx5_ib_qp_base *base; 2573 unsigned long flags; 2574 int err; 2575 2576 if (qp->is_rss) { 2577 destroy_rss_raw_qp_tir(dev, qp); 2578 return; 2579 } 2580 2581 base = (qp->type == IB_QPT_RAW_PACKET || 2582 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2583 &qp->raw_packet_qp.rq.base : 2584 &qp->trans_qp.base; 2585 2586 if (qp->state != IB_QPS_RESET) { 2587 if (qp->type != IB_QPT_RAW_PACKET && 2588 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2589 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2590 NULL, &base->mqp, NULL); 2591 } else { 2592 struct mlx5_modify_raw_qp_param raw_qp_param = { 2593 .operation = MLX5_CMD_OP_2RST_QP 2594 }; 2595 2596 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2597 } 2598 if (err) 2599 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2600 base->mqp.qpn); 2601 } 2602 2603 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2604 &recv_cq); 2605 2606 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2607 mlx5_ib_lock_cqs(send_cq, recv_cq); 2608 /* del from lists under both locks above to protect reset flow paths */ 2609 list_del(&qp->qps_list); 2610 if (send_cq) 2611 list_del(&qp->cq_send_list); 2612 2613 if (recv_cq) 2614 list_del(&qp->cq_recv_list); 2615 2616 if (!udata) { 2617 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2618 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2619 if (send_cq != recv_cq) 2620 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2621 NULL); 2622 } 2623 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2624 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2625 2626 if (qp->type == IB_QPT_RAW_PACKET || 2627 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2628 destroy_raw_packet_qp(dev, qp); 2629 } else { 2630 err = mlx5_core_destroy_qp(dev, &base->mqp); 2631 if (err) 2632 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2633 base->mqp.qpn); 2634 } 2635 2636 destroy_qp(dev, qp, base, udata); 2637 } 2638 2639 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2640 struct mlx5_ib_qp *qp, 2641 struct mlx5_create_qp_params *params) 2642 { 2643 struct ib_qp_init_attr *attr = params->attr; 2644 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2645 u32 uidx = params->uidx; 2646 void *dctc; 2647 2648 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2649 return -EOPNOTSUPP; 2650 2651 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2652 if (!qp->dct.in) 2653 return -ENOMEM; 2654 2655 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2656 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2657 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2658 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2659 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2660 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2661 MLX5_SET(dctc, dctc, user_index, uidx); 2662 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2663 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2664 2665 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2666 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2667 2668 if (rcqe_sz == 128) 2669 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2670 } 2671 2672 qp->state = IB_QPS_RESET; 2673 return 0; 2674 } 2675 2676 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2677 enum ib_qp_type *type) 2678 { 2679 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2680 goto out; 2681 2682 switch (attr->qp_type) { 2683 case IB_QPT_XRC_TGT: 2684 case IB_QPT_XRC_INI: 2685 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2686 goto out; 2687 fallthrough; 2688 case IB_QPT_RC: 2689 case IB_QPT_UC: 2690 case IB_QPT_SMI: 2691 case MLX5_IB_QPT_HW_GSI: 2692 case IB_QPT_DRIVER: 2693 case IB_QPT_GSI: 2694 case IB_QPT_RAW_PACKET: 2695 case IB_QPT_UD: 2696 case MLX5_IB_QPT_REG_UMR: 2697 break; 2698 default: 2699 goto out; 2700 } 2701 2702 *type = attr->qp_type; 2703 return 0; 2704 2705 out: 2706 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2707 return -EOPNOTSUPP; 2708 } 2709 2710 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2711 struct ib_qp_init_attr *attr, 2712 struct ib_udata *udata) 2713 { 2714 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2715 udata, struct mlx5_ib_ucontext, ibucontext); 2716 2717 if (!udata) { 2718 /* Kernel create_qp callers */ 2719 if (attr->rwq_ind_tbl) 2720 return -EOPNOTSUPP; 2721 2722 switch (attr->qp_type) { 2723 case IB_QPT_RAW_PACKET: 2724 case IB_QPT_DRIVER: 2725 return -EOPNOTSUPP; 2726 default: 2727 return 0; 2728 } 2729 } 2730 2731 /* Userspace create_qp callers */ 2732 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2733 mlx5_ib_dbg(dev, 2734 "Raw Packet QP is only supported for CQE version > 0\n"); 2735 return -EINVAL; 2736 } 2737 2738 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2739 mlx5_ib_dbg(dev, 2740 "Wrong QP type %d for the RWQ indirect table\n", 2741 attr->qp_type); 2742 return -EINVAL; 2743 } 2744 2745 /* 2746 * We don't need to see this warning, it means that kernel code 2747 * missing ib_pd. Placed here to catch developer's mistakes. 2748 */ 2749 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2750 "There is a missing PD pointer assignment\n"); 2751 return 0; 2752 } 2753 2754 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2755 bool cond, struct mlx5_ib_qp *qp) 2756 { 2757 if (!(*flags & flag)) 2758 return; 2759 2760 if (cond) { 2761 qp->flags_en |= flag; 2762 *flags &= ~flag; 2763 return; 2764 } 2765 2766 switch (flag) { 2767 case MLX5_QP_FLAG_SCATTER_CQE: 2768 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2769 /* 2770 * We don't return error if these flags were provided, 2771 * and mlx5 doesn't have right capability. 2772 */ 2773 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2774 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2775 return; 2776 default: 2777 break; 2778 } 2779 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2780 } 2781 2782 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2783 void *ucmd, struct ib_qp_init_attr *attr) 2784 { 2785 struct mlx5_core_dev *mdev = dev->mdev; 2786 bool cond; 2787 int flags; 2788 2789 if (attr->rwq_ind_tbl) 2790 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2791 else 2792 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2793 2794 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2795 case MLX5_QP_FLAG_TYPE_DCI: 2796 qp->type = MLX5_IB_QPT_DCI; 2797 break; 2798 case MLX5_QP_FLAG_TYPE_DCT: 2799 qp->type = MLX5_IB_QPT_DCT; 2800 break; 2801 default: 2802 if (qp->type != IB_QPT_DRIVER) 2803 break; 2804 /* 2805 * It is IB_QPT_DRIVER and or no subtype or 2806 * wrong subtype were provided. 2807 */ 2808 return -EINVAL; 2809 } 2810 2811 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2812 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2813 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM, 2814 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels), 2815 qp); 2816 2817 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2818 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2819 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2820 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2821 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2822 2823 if (qp->type == IB_QPT_RAW_PACKET) { 2824 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2825 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2826 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2827 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2828 cond, qp); 2829 process_vendor_flag(dev, &flags, 2830 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2831 qp); 2832 process_vendor_flag(dev, &flags, 2833 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2834 qp); 2835 } 2836 2837 if (qp->type == IB_QPT_RC) 2838 process_vendor_flag(dev, &flags, 2839 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2840 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2841 2842 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2843 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2844 2845 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2846 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2847 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2848 if (attr->rwq_ind_tbl && cond) { 2849 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2850 cond); 2851 return -EINVAL; 2852 } 2853 2854 if (flags) 2855 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2856 2857 return (flags) ? -EINVAL : 0; 2858 } 2859 2860 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2861 bool cond, struct mlx5_ib_qp *qp) 2862 { 2863 if (!(*flags & flag)) 2864 return; 2865 2866 if (cond) { 2867 qp->flags |= flag; 2868 *flags &= ~flag; 2869 return; 2870 } 2871 2872 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2873 /* 2874 * Special case, if condition didn't meet, it won't be error, 2875 * just different in-kernel flow. 2876 */ 2877 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2878 return; 2879 } 2880 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2881 } 2882 2883 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2884 struct ib_qp_init_attr *attr) 2885 { 2886 enum ib_qp_type qp_type = qp->type; 2887 struct mlx5_core_dev *mdev = dev->mdev; 2888 int create_flags = attr->create_flags; 2889 bool cond; 2890 2891 if (qp_type == MLX5_IB_QPT_DCT) 2892 return (create_flags) ? -EINVAL : 0; 2893 2894 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2895 return (create_flags) ? -EINVAL : 0; 2896 2897 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2898 mlx5_get_flow_namespace(dev->mdev, 2899 MLX5_FLOW_NAMESPACE_BYPASS), 2900 qp); 2901 process_create_flag(dev, &create_flags, 2902 IB_QP_CREATE_INTEGRITY_EN, 2903 MLX5_CAP_GEN(mdev, sho), qp); 2904 process_create_flag(dev, &create_flags, 2905 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2906 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2907 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2908 MLX5_CAP_GEN(mdev, cd), qp); 2909 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2910 MLX5_CAP_GEN(mdev, cd), qp); 2911 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2912 MLX5_CAP_GEN(mdev, cd), qp); 2913 2914 if (qp_type == IB_QPT_UD) { 2915 process_create_flag(dev, &create_flags, 2916 IB_QP_CREATE_IPOIB_UD_LSO, 2917 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2918 qp); 2919 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2920 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 2921 cond, qp); 2922 } 2923 2924 if (qp_type == IB_QPT_RAW_PACKET) { 2925 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2926 MLX5_CAP_ETH(mdev, scatter_fcs); 2927 process_create_flag(dev, &create_flags, 2928 IB_QP_CREATE_SCATTER_FCS, cond, qp); 2929 2930 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2931 MLX5_CAP_ETH(mdev, vlan_cap); 2932 process_create_flag(dev, &create_flags, 2933 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 2934 } 2935 2936 process_create_flag(dev, &create_flags, 2937 IB_QP_CREATE_PCI_WRITE_END_PADDING, 2938 MLX5_CAP_GEN(mdev, end_pad), qp); 2939 2940 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 2941 qp_type != MLX5_IB_QPT_REG_UMR, qp); 2942 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 2943 true, qp); 2944 2945 if (create_flags) { 2946 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 2947 create_flags); 2948 return -EOPNOTSUPP; 2949 } 2950 return 0; 2951 } 2952 2953 static int process_udata_size(struct mlx5_ib_dev *dev, 2954 struct mlx5_create_qp_params *params) 2955 { 2956 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 2957 struct ib_udata *udata = params->udata; 2958 size_t outlen = udata->outlen; 2959 size_t inlen = udata->inlen; 2960 2961 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 2962 params->ucmd_size = ucmd; 2963 if (!params->is_rss_raw) { 2964 /* User has old rdma-core, which doesn't support ECE */ 2965 size_t min_inlen = 2966 offsetof(struct mlx5_ib_create_qp, ece_options); 2967 2968 /* 2969 * We will check in check_ucmd_data() that user 2970 * cleared everything after inlen. 2971 */ 2972 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 2973 goto out; 2974 } 2975 2976 /* RSS RAW QP */ 2977 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 2978 return -EINVAL; 2979 2980 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 2981 return -EINVAL; 2982 2983 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 2984 params->ucmd_size = ucmd; 2985 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 2986 return -EINVAL; 2987 2988 params->inlen = min(ucmd, inlen); 2989 out: 2990 if (!params->inlen) 2991 mlx5_ib_dbg(dev, "udata is too small\n"); 2992 2993 return (params->inlen) ? 0 : -EINVAL; 2994 } 2995 2996 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2997 struct mlx5_ib_qp *qp, 2998 struct mlx5_create_qp_params *params) 2999 { 3000 int err; 3001 3002 if (params->is_rss_raw) { 3003 err = create_rss_raw_qp_tir(dev, pd, qp, params); 3004 goto out; 3005 } 3006 3007 switch (qp->type) { 3008 case MLX5_IB_QPT_DCT: 3009 err = create_dct(dev, pd, qp, params); 3010 rdma_restrack_no_track(&qp->ibqp.res); 3011 break; 3012 case MLX5_IB_QPT_DCI: 3013 err = create_dci(dev, pd, qp, params); 3014 break; 3015 case IB_QPT_XRC_TGT: 3016 err = create_xrc_tgt_qp(dev, qp, params); 3017 break; 3018 case IB_QPT_GSI: 3019 err = mlx5_ib_create_gsi(pd, qp, params->attr); 3020 break; 3021 case MLX5_IB_QPT_HW_GSI: 3022 case MLX5_IB_QPT_REG_UMR: 3023 rdma_restrack_no_track(&qp->ibqp.res); 3024 fallthrough; 3025 default: 3026 if (params->udata) 3027 err = create_user_qp(dev, pd, qp, params); 3028 else 3029 err = create_kernel_qp(dev, pd, qp, params); 3030 } 3031 3032 out: 3033 if (err) { 3034 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 3035 return err; 3036 } 3037 3038 if (is_qp0(qp->type)) 3039 qp->ibqp.qp_num = 0; 3040 else if (is_qp1(qp->type)) 3041 qp->ibqp.qp_num = 1; 3042 else 3043 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 3044 3045 mlx5_ib_dbg(dev, 3046 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 3047 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 3048 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 3049 -1, 3050 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 3051 -1, 3052 params->resp.ece_options); 3053 3054 return 0; 3055 } 3056 3057 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3058 struct ib_qp_init_attr *attr) 3059 { 3060 int ret = 0; 3061 3062 switch (qp->type) { 3063 case MLX5_IB_QPT_DCT: 3064 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 3065 break; 3066 case MLX5_IB_QPT_DCI: 3067 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 3068 -EINVAL : 3069 0; 3070 break; 3071 case IB_QPT_RAW_PACKET: 3072 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 3073 break; 3074 default: 3075 break; 3076 } 3077 3078 if (ret) 3079 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 3080 3081 return ret; 3082 } 3083 3084 static int get_qp_uidx(struct mlx5_ib_qp *qp, 3085 struct mlx5_create_qp_params *params) 3086 { 3087 struct mlx5_ib_create_qp *ucmd = params->ucmd; 3088 struct ib_udata *udata = params->udata; 3089 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3090 udata, struct mlx5_ib_ucontext, ibucontext); 3091 3092 if (params->is_rss_raw) 3093 return 0; 3094 3095 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 3096 } 3097 3098 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 3099 { 3100 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 3101 3102 if (mqp->state == IB_QPS_RTR) { 3103 int err; 3104 3105 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 3106 if (err) { 3107 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 3108 return err; 3109 } 3110 } 3111 3112 kfree(mqp->dct.in); 3113 return 0; 3114 } 3115 3116 static int check_ucmd_data(struct mlx5_ib_dev *dev, 3117 struct mlx5_create_qp_params *params) 3118 { 3119 struct ib_udata *udata = params->udata; 3120 size_t size, last; 3121 int ret; 3122 3123 if (params->is_rss_raw) 3124 /* 3125 * These QPs don't have "reserved" field in their 3126 * create_qp input struct, so their data is always valid. 3127 */ 3128 last = sizeof(struct mlx5_ib_create_qp_rss); 3129 else 3130 last = offsetof(struct mlx5_ib_create_qp, reserved); 3131 3132 if (udata->inlen <= last) 3133 return 0; 3134 3135 /* 3136 * User provides different create_qp structures based on the 3137 * flow and we need to know if he cleared memory after our 3138 * struct create_qp ends. 3139 */ 3140 size = udata->inlen - last; 3141 ret = ib_is_udata_cleared(params->udata, last, size); 3142 if (!ret) 3143 mlx5_ib_dbg( 3144 dev, 3145 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 3146 udata->inlen, params->ucmd_size, last, size); 3147 return ret ? 0 : -EINVAL; 3148 } 3149 3150 int mlx5_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr, 3151 struct ib_udata *udata) 3152 { 3153 struct mlx5_create_qp_params params = {}; 3154 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3155 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3156 struct ib_pd *pd = ibqp->pd; 3157 enum ib_qp_type type; 3158 int err; 3159 3160 err = check_qp_type(dev, attr, &type); 3161 if (err) 3162 return err; 3163 3164 err = check_valid_flow(dev, pd, attr, udata); 3165 if (err) 3166 return err; 3167 3168 params.udata = udata; 3169 params.uidx = MLX5_IB_DEFAULT_UIDX; 3170 params.attr = attr; 3171 params.is_rss_raw = !!attr->rwq_ind_tbl; 3172 3173 if (udata) { 3174 err = process_udata_size(dev, ¶ms); 3175 if (err) 3176 return err; 3177 3178 err = check_ucmd_data(dev, ¶ms); 3179 if (err) 3180 return err; 3181 3182 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3183 if (!params.ucmd) 3184 return -ENOMEM; 3185 3186 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3187 if (err) 3188 goto free_ucmd; 3189 } 3190 3191 mutex_init(&qp->mutex); 3192 qp->type = type; 3193 if (udata) { 3194 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3195 if (err) 3196 goto free_ucmd; 3197 3198 err = get_qp_uidx(qp, ¶ms); 3199 if (err) 3200 goto free_ucmd; 3201 } 3202 err = process_create_flags(dev, qp, attr); 3203 if (err) 3204 goto free_ucmd; 3205 3206 err = check_qp_attr(dev, qp, attr); 3207 if (err) 3208 goto free_ucmd; 3209 3210 err = create_qp(dev, pd, qp, ¶ms); 3211 if (err) 3212 goto free_ucmd; 3213 3214 kfree(params.ucmd); 3215 params.ucmd = NULL; 3216 3217 if (udata) 3218 /* 3219 * It is safe to copy response for all user create QP flows, 3220 * including MLX5_IB_QPT_DCT, which doesn't need it. 3221 * In that case, resp will be filled with zeros. 3222 */ 3223 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3224 if (err) 3225 goto destroy_qp; 3226 3227 return 0; 3228 3229 destroy_qp: 3230 switch (qp->type) { 3231 case MLX5_IB_QPT_DCT: 3232 mlx5_ib_destroy_dct(qp); 3233 break; 3234 case IB_QPT_GSI: 3235 mlx5_ib_destroy_gsi(qp); 3236 break; 3237 default: 3238 destroy_qp_common(dev, qp, udata); 3239 } 3240 3241 free_ucmd: 3242 kfree(params.ucmd); 3243 return err; 3244 } 3245 3246 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3247 { 3248 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3249 struct mlx5_ib_qp *mqp = to_mqp(qp); 3250 3251 if (mqp->type == IB_QPT_GSI) 3252 return mlx5_ib_destroy_gsi(mqp); 3253 3254 if (mqp->type == MLX5_IB_QPT_DCT) 3255 return mlx5_ib_destroy_dct(mqp); 3256 3257 destroy_qp_common(dev, mqp, udata); 3258 return 0; 3259 } 3260 3261 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3262 const struct ib_qp_attr *attr, int attr_mask, 3263 void *qpc) 3264 { 3265 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3266 u8 dest_rd_atomic; 3267 u32 access_flags; 3268 3269 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3270 dest_rd_atomic = attr->max_dest_rd_atomic; 3271 else 3272 dest_rd_atomic = qp->trans_qp.resp_depth; 3273 3274 if (attr_mask & IB_QP_ACCESS_FLAGS) 3275 access_flags = attr->qp_access_flags; 3276 else 3277 access_flags = qp->trans_qp.atomic_rd_en; 3278 3279 if (!dest_rd_atomic) 3280 access_flags &= IB_ACCESS_REMOTE_WRITE; 3281 3282 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3283 3284 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3285 int atomic_mode; 3286 3287 atomic_mode = get_atomic_mode(dev, qp->type); 3288 if (atomic_mode < 0) 3289 return -EOPNOTSUPP; 3290 3291 MLX5_SET(qpc, qpc, rae, 1); 3292 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3293 } 3294 3295 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3296 return 0; 3297 } 3298 3299 enum { 3300 MLX5_PATH_FLAG_FL = 1 << 0, 3301 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3302 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3303 }; 3304 3305 static int mlx5_to_ib_rate_map(u8 rate) 3306 { 3307 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3308 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3309 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3310 IB_RATE_400_GBPS }; 3311 3312 if (rate < ARRAY_SIZE(rates)) 3313 return rates[rate]; 3314 3315 return rate - MLX5_STAT_RATE_OFFSET; 3316 } 3317 3318 static int ib_to_mlx5_rate_map(u8 rate) 3319 { 3320 switch (rate) { 3321 case IB_RATE_PORT_CURRENT: 3322 return 0; 3323 case IB_RATE_56_GBPS: 3324 return 1; 3325 case IB_RATE_25_GBPS: 3326 return 2; 3327 case IB_RATE_100_GBPS: 3328 return 3; 3329 case IB_RATE_200_GBPS: 3330 return 4; 3331 case IB_RATE_50_GBPS: 3332 return 5; 3333 case IB_RATE_400_GBPS: 3334 return 6; 3335 default: 3336 return rate + MLX5_STAT_RATE_OFFSET; 3337 } 3338 3339 return 0; 3340 } 3341 3342 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3343 { 3344 u32 stat_rate_support; 3345 3346 if (rate == IB_RATE_PORT_CURRENT) 3347 return 0; 3348 3349 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3350 return -EINVAL; 3351 3352 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3353 while (rate != IB_RATE_PORT_CURRENT && 3354 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3355 --rate; 3356 3357 return ib_to_mlx5_rate_map(rate); 3358 } 3359 3360 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3361 struct mlx5_ib_sq *sq, u8 sl, 3362 struct ib_pd *pd) 3363 { 3364 void *in; 3365 void *tisc; 3366 int inlen; 3367 int err; 3368 3369 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3370 in = kvzalloc(inlen, GFP_KERNEL); 3371 if (!in) 3372 return -ENOMEM; 3373 3374 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3375 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3376 3377 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3378 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3379 3380 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3381 3382 kvfree(in); 3383 3384 return err; 3385 } 3386 3387 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3388 struct mlx5_ib_sq *sq, u8 tx_affinity, 3389 struct ib_pd *pd) 3390 { 3391 void *in; 3392 void *tisc; 3393 int inlen; 3394 int err; 3395 3396 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3397 in = kvzalloc(inlen, GFP_KERNEL); 3398 if (!in) 3399 return -ENOMEM; 3400 3401 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3402 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3403 3404 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3405 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3406 3407 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3408 3409 kvfree(in); 3410 3411 return err; 3412 } 3413 3414 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3415 u32 lqpn, u32 rqpn) 3416 3417 { 3418 u32 fl = ah->grh.flow_label; 3419 3420 if (!fl) 3421 fl = rdma_calc_flow_label(lqpn, rqpn); 3422 3423 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3424 } 3425 3426 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3427 const struct rdma_ah_attr *ah, void *path, u8 port, 3428 int attr_mask, u32 path_flags, 3429 const struct ib_qp_attr *attr, bool alt) 3430 { 3431 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3432 int err; 3433 enum ib_gid_type gid_type; 3434 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3435 u8 sl = rdma_ah_get_sl(ah); 3436 3437 if (attr_mask & IB_QP_PKEY_INDEX) 3438 MLX5_SET(ads, path, pkey_index, 3439 alt ? attr->alt_pkey_index : attr->pkey_index); 3440 3441 if (ah_flags & IB_AH_GRH) { 3442 const struct ib_port_immutable *immutable; 3443 3444 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3445 if (grh->sgid_index >= immutable->gid_tbl_len) { 3446 pr_err("sgid_index (%u) too large. max is %d\n", 3447 grh->sgid_index, 3448 immutable->gid_tbl_len); 3449 return -EINVAL; 3450 } 3451 } 3452 3453 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3454 if (!(ah_flags & IB_AH_GRH)) 3455 return -EINVAL; 3456 3457 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3458 ah->roce.dmac); 3459 if ((qp->type == IB_QPT_RC || 3460 qp->type == IB_QPT_UC || 3461 qp->type == IB_QPT_XRC_INI || 3462 qp->type == IB_QPT_XRC_TGT) && 3463 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3464 (attr_mask & IB_QP_DEST_QPN)) 3465 mlx5_set_path_udp_sport(path, ah, 3466 qp->ibqp.qp_num, 3467 attr->dest_qp_num); 3468 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3469 gid_type = ah->grh.sgid_attr->gid_type; 3470 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3471 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3472 } else { 3473 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3474 MLX5_SET(ads, path, free_ar, 3475 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3476 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3477 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3478 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3479 MLX5_SET(ads, path, sl, sl); 3480 } 3481 3482 if (ah_flags & IB_AH_GRH) { 3483 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3484 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3485 MLX5_SET(ads, path, tclass, grh->traffic_class); 3486 MLX5_SET(ads, path, flow_label, grh->flow_label); 3487 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3488 sizeof(grh->dgid.raw)); 3489 } 3490 3491 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3492 if (err < 0) 3493 return err; 3494 MLX5_SET(ads, path, stat_rate, err); 3495 MLX5_SET(ads, path, vhca_port_num, port); 3496 3497 if (attr_mask & IB_QP_TIMEOUT) 3498 MLX5_SET(ads, path, ack_timeout, 3499 alt ? attr->alt_timeout : attr->timeout); 3500 3501 if ((qp->type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3502 return modify_raw_packet_eth_prio(dev->mdev, 3503 &qp->raw_packet_qp.sq, 3504 sl & 0xf, qp->ibqp.pd); 3505 3506 return 0; 3507 } 3508 3509 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3510 [MLX5_QP_STATE_INIT] = { 3511 [MLX5_QP_STATE_INIT] = { 3512 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3513 MLX5_QP_OPTPAR_RAE | 3514 MLX5_QP_OPTPAR_RWE | 3515 MLX5_QP_OPTPAR_PKEY_INDEX | 3516 MLX5_QP_OPTPAR_PRI_PORT | 3517 MLX5_QP_OPTPAR_LAG_TX_AFF, 3518 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3519 MLX5_QP_OPTPAR_PKEY_INDEX | 3520 MLX5_QP_OPTPAR_PRI_PORT | 3521 MLX5_QP_OPTPAR_LAG_TX_AFF, 3522 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3523 MLX5_QP_OPTPAR_Q_KEY | 3524 MLX5_QP_OPTPAR_PRI_PORT, 3525 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3526 MLX5_QP_OPTPAR_RAE | 3527 MLX5_QP_OPTPAR_RWE | 3528 MLX5_QP_OPTPAR_PKEY_INDEX | 3529 MLX5_QP_OPTPAR_PRI_PORT | 3530 MLX5_QP_OPTPAR_LAG_TX_AFF, 3531 }, 3532 [MLX5_QP_STATE_RTR] = { 3533 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3534 MLX5_QP_OPTPAR_RRE | 3535 MLX5_QP_OPTPAR_RAE | 3536 MLX5_QP_OPTPAR_RWE | 3537 MLX5_QP_OPTPAR_PKEY_INDEX | 3538 MLX5_QP_OPTPAR_LAG_TX_AFF, 3539 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3540 MLX5_QP_OPTPAR_RWE | 3541 MLX5_QP_OPTPAR_PKEY_INDEX | 3542 MLX5_QP_OPTPAR_LAG_TX_AFF, 3543 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3544 MLX5_QP_OPTPAR_Q_KEY, 3545 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3546 MLX5_QP_OPTPAR_Q_KEY, 3547 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3548 MLX5_QP_OPTPAR_RRE | 3549 MLX5_QP_OPTPAR_RAE | 3550 MLX5_QP_OPTPAR_RWE | 3551 MLX5_QP_OPTPAR_PKEY_INDEX | 3552 MLX5_QP_OPTPAR_LAG_TX_AFF, 3553 }, 3554 }, 3555 [MLX5_QP_STATE_RTR] = { 3556 [MLX5_QP_STATE_RTS] = { 3557 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3558 MLX5_QP_OPTPAR_RRE | 3559 MLX5_QP_OPTPAR_RAE | 3560 MLX5_QP_OPTPAR_RWE | 3561 MLX5_QP_OPTPAR_PM_STATE | 3562 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3563 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3564 MLX5_QP_OPTPAR_RWE | 3565 MLX5_QP_OPTPAR_PM_STATE, 3566 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3567 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3568 MLX5_QP_OPTPAR_RRE | 3569 MLX5_QP_OPTPAR_RAE | 3570 MLX5_QP_OPTPAR_RWE | 3571 MLX5_QP_OPTPAR_PM_STATE | 3572 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3573 }, 3574 }, 3575 [MLX5_QP_STATE_RTS] = { 3576 [MLX5_QP_STATE_RTS] = { 3577 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3578 MLX5_QP_OPTPAR_RAE | 3579 MLX5_QP_OPTPAR_RWE | 3580 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3581 MLX5_QP_OPTPAR_PM_STATE | 3582 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3583 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3584 MLX5_QP_OPTPAR_PM_STATE | 3585 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3586 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3587 MLX5_QP_OPTPAR_SRQN | 3588 MLX5_QP_OPTPAR_CQN_RCV, 3589 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3590 MLX5_QP_OPTPAR_RAE | 3591 MLX5_QP_OPTPAR_RWE | 3592 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3593 MLX5_QP_OPTPAR_PM_STATE | 3594 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3595 }, 3596 }, 3597 [MLX5_QP_STATE_SQER] = { 3598 [MLX5_QP_STATE_RTS] = { 3599 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3600 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3601 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3602 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3603 MLX5_QP_OPTPAR_RWE | 3604 MLX5_QP_OPTPAR_RAE | 3605 MLX5_QP_OPTPAR_RRE, 3606 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3607 MLX5_QP_OPTPAR_RWE | 3608 MLX5_QP_OPTPAR_RAE | 3609 MLX5_QP_OPTPAR_RRE, 3610 }, 3611 }, 3612 [MLX5_QP_STATE_SQD] = { 3613 [MLX5_QP_STATE_RTS] = { 3614 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3615 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3616 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3617 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3618 MLX5_QP_OPTPAR_RWE | 3619 MLX5_QP_OPTPAR_RAE | 3620 MLX5_QP_OPTPAR_RRE, 3621 }, 3622 }, 3623 }; 3624 3625 static int ib_nr_to_mlx5_nr(int ib_mask) 3626 { 3627 switch (ib_mask) { 3628 case IB_QP_STATE: 3629 return 0; 3630 case IB_QP_CUR_STATE: 3631 return 0; 3632 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3633 return 0; 3634 case IB_QP_ACCESS_FLAGS: 3635 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3636 MLX5_QP_OPTPAR_RAE; 3637 case IB_QP_PKEY_INDEX: 3638 return MLX5_QP_OPTPAR_PKEY_INDEX; 3639 case IB_QP_PORT: 3640 return MLX5_QP_OPTPAR_PRI_PORT; 3641 case IB_QP_QKEY: 3642 return MLX5_QP_OPTPAR_Q_KEY; 3643 case IB_QP_AV: 3644 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3645 MLX5_QP_OPTPAR_PRI_PORT; 3646 case IB_QP_PATH_MTU: 3647 return 0; 3648 case IB_QP_TIMEOUT: 3649 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3650 case IB_QP_RETRY_CNT: 3651 return MLX5_QP_OPTPAR_RETRY_COUNT; 3652 case IB_QP_RNR_RETRY: 3653 return MLX5_QP_OPTPAR_RNR_RETRY; 3654 case IB_QP_RQ_PSN: 3655 return 0; 3656 case IB_QP_MAX_QP_RD_ATOMIC: 3657 return MLX5_QP_OPTPAR_SRA_MAX; 3658 case IB_QP_ALT_PATH: 3659 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3660 case IB_QP_MIN_RNR_TIMER: 3661 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3662 case IB_QP_SQ_PSN: 3663 return 0; 3664 case IB_QP_MAX_DEST_RD_ATOMIC: 3665 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3666 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3667 case IB_QP_PATH_MIG_STATE: 3668 return MLX5_QP_OPTPAR_PM_STATE; 3669 case IB_QP_CAP: 3670 return 0; 3671 case IB_QP_DEST_QPN: 3672 return 0; 3673 } 3674 return 0; 3675 } 3676 3677 static int ib_mask_to_mlx5_opt(int ib_mask) 3678 { 3679 int result = 0; 3680 int i; 3681 3682 for (i = 0; i < 8 * sizeof(int); i++) { 3683 if ((1 << i) & ib_mask) 3684 result |= ib_nr_to_mlx5_nr(1 << i); 3685 } 3686 3687 return result; 3688 } 3689 3690 static int modify_raw_packet_qp_rq( 3691 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3692 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3693 { 3694 void *in; 3695 void *rqc; 3696 int inlen; 3697 int err; 3698 3699 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3700 in = kvzalloc(inlen, GFP_KERNEL); 3701 if (!in) 3702 return -ENOMEM; 3703 3704 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3705 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3706 3707 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3708 MLX5_SET(rqc, rqc, state, new_state); 3709 3710 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3711 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3712 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3713 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3714 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3715 } else 3716 dev_info_once( 3717 &dev->ib_dev.dev, 3718 "RAW PACKET QP counters are not supported on current FW\n"); 3719 } 3720 3721 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3722 if (err) 3723 goto out; 3724 3725 rq->state = new_state; 3726 3727 out: 3728 kvfree(in); 3729 return err; 3730 } 3731 3732 static int modify_raw_packet_qp_sq( 3733 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3734 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3735 { 3736 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3737 struct mlx5_rate_limit old_rl = ibqp->rl; 3738 struct mlx5_rate_limit new_rl = old_rl; 3739 bool new_rate_added = false; 3740 u16 rl_index = 0; 3741 void *in; 3742 void *sqc; 3743 int inlen; 3744 int err; 3745 3746 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3747 in = kvzalloc(inlen, GFP_KERNEL); 3748 if (!in) 3749 return -ENOMEM; 3750 3751 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3752 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3753 3754 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3755 MLX5_SET(sqc, sqc, state, new_state); 3756 3757 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3758 if (new_state != MLX5_SQC_STATE_RDY) 3759 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3760 __func__); 3761 else 3762 new_rl = raw_qp_param->rl; 3763 } 3764 3765 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3766 if (new_rl.rate) { 3767 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3768 if (err) { 3769 pr_err("Failed configuring rate limit(err %d): \ 3770 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3771 err, new_rl.rate, new_rl.max_burst_sz, 3772 new_rl.typical_pkt_sz); 3773 3774 goto out; 3775 } 3776 new_rate_added = true; 3777 } 3778 3779 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3780 /* index 0 means no limit */ 3781 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3782 } 3783 3784 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3785 if (err) { 3786 /* Remove new rate from table if failed */ 3787 if (new_rate_added) 3788 mlx5_rl_remove_rate(dev, &new_rl); 3789 goto out; 3790 } 3791 3792 /* Only remove the old rate after new rate was set */ 3793 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3794 (new_state != MLX5_SQC_STATE_RDY)) { 3795 mlx5_rl_remove_rate(dev, &old_rl); 3796 if (new_state != MLX5_SQC_STATE_RDY) 3797 memset(&new_rl, 0, sizeof(new_rl)); 3798 } 3799 3800 ibqp->rl = new_rl; 3801 sq->state = new_state; 3802 3803 out: 3804 kvfree(in); 3805 return err; 3806 } 3807 3808 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3809 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3810 u8 tx_affinity) 3811 { 3812 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3813 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3814 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3815 int modify_rq = !!qp->rq.wqe_cnt; 3816 int modify_sq = !!qp->sq.wqe_cnt; 3817 int rq_state; 3818 int sq_state; 3819 int err; 3820 3821 switch (raw_qp_param->operation) { 3822 case MLX5_CMD_OP_RST2INIT_QP: 3823 rq_state = MLX5_RQC_STATE_RDY; 3824 sq_state = MLX5_SQC_STATE_RST; 3825 break; 3826 case MLX5_CMD_OP_2ERR_QP: 3827 rq_state = MLX5_RQC_STATE_ERR; 3828 sq_state = MLX5_SQC_STATE_ERR; 3829 break; 3830 case MLX5_CMD_OP_2RST_QP: 3831 rq_state = MLX5_RQC_STATE_RST; 3832 sq_state = MLX5_SQC_STATE_RST; 3833 break; 3834 case MLX5_CMD_OP_RTR2RTS_QP: 3835 case MLX5_CMD_OP_RTS2RTS_QP: 3836 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3837 return -EINVAL; 3838 3839 modify_rq = 0; 3840 sq_state = MLX5_SQC_STATE_RDY; 3841 break; 3842 case MLX5_CMD_OP_INIT2INIT_QP: 3843 case MLX5_CMD_OP_INIT2RTR_QP: 3844 if (raw_qp_param->set_mask) 3845 return -EINVAL; 3846 else 3847 return 0; 3848 default: 3849 WARN_ON(1); 3850 return -EINVAL; 3851 } 3852 3853 if (modify_rq) { 3854 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3855 qp->ibqp.pd); 3856 if (err) 3857 return err; 3858 } 3859 3860 if (modify_sq) { 3861 struct mlx5_flow_handle *flow_rule; 3862 3863 if (tx_affinity) { 3864 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3865 tx_affinity, 3866 qp->ibqp.pd); 3867 if (err) 3868 return err; 3869 } 3870 3871 flow_rule = create_flow_rule_vport_sq(dev, sq, 3872 raw_qp_param->port); 3873 if (IS_ERR(flow_rule)) 3874 return PTR_ERR(flow_rule); 3875 3876 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3877 raw_qp_param, qp->ibqp.pd); 3878 if (err) { 3879 if (flow_rule) 3880 mlx5_del_flow_rules(flow_rule); 3881 return err; 3882 } 3883 3884 if (flow_rule) { 3885 destroy_flow_rule_vport_sq(sq); 3886 sq->flow_rule = flow_rule; 3887 } 3888 3889 return err; 3890 } 3891 3892 return 0; 3893 } 3894 3895 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3896 struct ib_udata *udata) 3897 { 3898 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3899 udata, struct mlx5_ib_ucontext, ibucontext); 3900 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3901 atomic_t *tx_port_affinity; 3902 3903 if (ucontext) 3904 tx_port_affinity = &ucontext->tx_port_affinity; 3905 else 3906 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3907 3908 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3909 MLX5_MAX_PORTS + 1; 3910 } 3911 3912 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3913 { 3914 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3915 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3916 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3917 (qp->type == MLX5_IB_QPT_DCI)) 3918 return true; 3919 return false; 3920 } 3921 3922 static unsigned int get_tx_affinity(struct ib_qp *qp, 3923 const struct ib_qp_attr *attr, 3924 int attr_mask, u8 init, 3925 struct ib_udata *udata) 3926 { 3927 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3928 udata, struct mlx5_ib_ucontext, ibucontext); 3929 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3930 struct mlx5_ib_qp *mqp = to_mqp(qp); 3931 struct mlx5_ib_qp_base *qp_base; 3932 unsigned int tx_affinity; 3933 3934 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 3935 qp_supports_affinity(mqp))) 3936 return 0; 3937 3938 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3939 tx_affinity = mqp->gsi_lag_port; 3940 else if (init) 3941 tx_affinity = get_tx_affinity_rr(dev, udata); 3942 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 3943 tx_affinity = 3944 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 3945 else 3946 return 0; 3947 3948 qp_base = &mqp->trans_qp.base; 3949 if (ucontext) 3950 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3951 tx_affinity, qp_base->mqp.qpn, ucontext); 3952 else 3953 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3954 tx_affinity, qp_base->mqp.qpn); 3955 return tx_affinity; 3956 } 3957 3958 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3959 struct rdma_counter *counter) 3960 { 3961 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3962 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 3963 struct mlx5_ib_qp *mqp = to_mqp(qp); 3964 struct mlx5_ib_qp_base *base; 3965 u32 set_id; 3966 u32 *qpc; 3967 3968 if (counter) 3969 set_id = counter->id; 3970 else 3971 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3972 3973 base = &mqp->trans_qp.base; 3974 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 3975 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 3976 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 3977 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 3978 MLX5_QP_OPTPAR_COUNTER_SET_ID); 3979 3980 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 3981 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3982 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 3983 } 3984 3985 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3986 const struct ib_qp_attr *attr, int attr_mask, 3987 enum ib_qp_state cur_state, 3988 enum ib_qp_state new_state, 3989 const struct mlx5_ib_modify_qp *ucmd, 3990 struct mlx5_ib_modify_qp_resp *resp, 3991 struct ib_udata *udata) 3992 { 3993 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3994 [MLX5_QP_STATE_RST] = { 3995 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3996 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3997 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3998 }, 3999 [MLX5_QP_STATE_INIT] = { 4000 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4001 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4002 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 4003 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 4004 }, 4005 [MLX5_QP_STATE_RTR] = { 4006 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4007 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4008 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 4009 }, 4010 [MLX5_QP_STATE_RTS] = { 4011 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4012 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4013 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 4014 }, 4015 [MLX5_QP_STATE_SQD] = { 4016 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4017 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4018 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD_RTS_QP, 4019 }, 4020 [MLX5_QP_STATE_SQER] = { 4021 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4022 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4023 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 4024 }, 4025 [MLX5_QP_STATE_ERR] = { 4026 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4027 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4028 } 4029 }; 4030 4031 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4032 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4033 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 4034 struct mlx5_ib_cq *send_cq, *recv_cq; 4035 struct mlx5_ib_pd *pd; 4036 enum mlx5_qp_state mlx5_cur, mlx5_new; 4037 void *qpc, *pri_path, *alt_path; 4038 enum mlx5_qp_optpar optpar = 0; 4039 u32 set_id = 0; 4040 int mlx5_st; 4041 int err; 4042 u16 op; 4043 u8 tx_affinity = 0; 4044 4045 mlx5_st = to_mlx5_st(qp->type); 4046 if (mlx5_st < 0) 4047 return -EINVAL; 4048 4049 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 4050 if (!qpc) 4051 return -ENOMEM; 4052 4053 pd = to_mpd(qp->ibqp.pd); 4054 MLX5_SET(qpc, qpc, st, mlx5_st); 4055 4056 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 4057 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4058 } else { 4059 switch (attr->path_mig_state) { 4060 case IB_MIG_MIGRATED: 4061 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4062 break; 4063 case IB_MIG_REARM: 4064 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 4065 break; 4066 case IB_MIG_ARMED: 4067 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 4068 break; 4069 } 4070 } 4071 4072 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 4073 cur_state == IB_QPS_RESET && 4074 new_state == IB_QPS_INIT, udata); 4075 4076 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 4077 if (tx_affinity && new_state == IB_QPS_RTR && 4078 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 4079 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 4080 4081 if (is_sqp(qp->type)) { 4082 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 4083 MLX5_SET(qpc, qpc, log_msg_max, 8); 4084 } else if ((qp->type == IB_QPT_UD && 4085 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 4086 qp->type == MLX5_IB_QPT_REG_UMR) { 4087 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 4088 MLX5_SET(qpc, qpc, log_msg_max, 12); 4089 } else if (attr_mask & IB_QP_PATH_MTU) { 4090 if (attr->path_mtu < IB_MTU_256 || 4091 attr->path_mtu > IB_MTU_4096) { 4092 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 4093 err = -EINVAL; 4094 goto out; 4095 } 4096 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 4097 MLX5_SET(qpc, qpc, log_msg_max, 4098 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 4099 } 4100 4101 if (attr_mask & IB_QP_DEST_QPN) 4102 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 4103 4104 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4105 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4106 4107 if (attr_mask & IB_QP_PKEY_INDEX) 4108 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 4109 4110 /* todo implement counter_index functionality */ 4111 4112 if (is_sqp(qp->type)) 4113 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 4114 4115 if (attr_mask & IB_QP_PORT) 4116 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 4117 4118 if (attr_mask & IB_QP_AV) { 4119 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 4120 attr_mask & IB_QP_PORT ? attr->port_num : 4121 qp->port, 4122 attr_mask, 0, attr, false); 4123 if (err) 4124 goto out; 4125 } 4126 4127 if (attr_mask & IB_QP_TIMEOUT) 4128 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 4129 4130 if (attr_mask & IB_QP_ALT_PATH) { 4131 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 4132 attr->alt_port_num, 4133 attr_mask | IB_QP_PKEY_INDEX | 4134 IB_QP_TIMEOUT, 4135 0, attr, true); 4136 if (err) 4137 goto out; 4138 } 4139 4140 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 4141 &send_cq, &recv_cq); 4142 4143 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 4144 if (send_cq) 4145 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 4146 if (recv_cq) 4147 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 4148 4149 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 4150 4151 if (attr_mask & IB_QP_RNR_RETRY) 4152 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 4153 4154 if (attr_mask & IB_QP_RETRY_CNT) 4155 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 4156 4157 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 4158 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 4159 4160 if (attr_mask & IB_QP_SQ_PSN) 4161 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 4162 4163 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 4164 MLX5_SET(qpc, qpc, log_rra_max, 4165 ilog2(attr->max_dest_rd_atomic)); 4166 4167 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4168 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4169 if (err) 4170 goto out; 4171 } 4172 4173 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4174 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4175 4176 if (attr_mask & IB_QP_RQ_PSN) 4177 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4178 4179 if (attr_mask & IB_QP_QKEY) 4180 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4181 4182 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4183 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4184 4185 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4186 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4187 qp->port) - 1; 4188 4189 /* Underlay port should be used - index 0 function per port */ 4190 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4191 port_num = 0; 4192 4193 if (ibqp->counter) 4194 set_id = ibqp->counter->id; 4195 else 4196 set_id = mlx5_ib_get_counters_id(dev, port_num); 4197 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4198 } 4199 4200 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4201 MLX5_SET(qpc, qpc, rlky, 1); 4202 4203 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4204 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4205 4206 mlx5_cur = to_mlx5_state(cur_state); 4207 mlx5_new = to_mlx5_state(new_state); 4208 4209 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4210 !optab[mlx5_cur][mlx5_new]) { 4211 err = -EINVAL; 4212 goto out; 4213 } 4214 4215 op = optab[mlx5_cur][mlx5_new]; 4216 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4217 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4218 4219 if (qp->type == IB_QPT_RAW_PACKET || 4220 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4221 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4222 4223 raw_qp_param.operation = op; 4224 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4225 raw_qp_param.rq_q_ctr_id = set_id; 4226 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4227 } 4228 4229 if (attr_mask & IB_QP_PORT) 4230 raw_qp_param.port = attr->port_num; 4231 4232 if (attr_mask & IB_QP_RATE_LIMIT) { 4233 raw_qp_param.rl.rate = attr->rate_limit; 4234 4235 if (ucmd->burst_info.max_burst_sz) { 4236 if (attr->rate_limit && 4237 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4238 raw_qp_param.rl.max_burst_sz = 4239 ucmd->burst_info.max_burst_sz; 4240 } else { 4241 err = -EINVAL; 4242 goto out; 4243 } 4244 } 4245 4246 if (ucmd->burst_info.typical_pkt_sz) { 4247 if (attr->rate_limit && 4248 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4249 raw_qp_param.rl.typical_pkt_sz = 4250 ucmd->burst_info.typical_pkt_sz; 4251 } else { 4252 err = -EINVAL; 4253 goto out; 4254 } 4255 } 4256 4257 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4258 } 4259 4260 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4261 } else { 4262 if (udata) { 4263 /* For the kernel flows, the resp will stay zero */ 4264 resp->ece_options = 4265 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4266 ucmd->ece_options : 0; 4267 resp->response_length = sizeof(*resp); 4268 } 4269 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4270 &resp->ece_options); 4271 } 4272 4273 if (err) 4274 goto out; 4275 4276 qp->state = new_state; 4277 4278 if (attr_mask & IB_QP_ACCESS_FLAGS) 4279 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4280 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4281 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4282 if (attr_mask & IB_QP_PORT) 4283 qp->port = attr->port_num; 4284 if (attr_mask & IB_QP_ALT_PATH) 4285 qp->trans_qp.alt_port = attr->alt_port_num; 4286 4287 /* 4288 * If we moved a kernel QP to RESET, clean up all old CQ 4289 * entries and reinitialize the QP. 4290 */ 4291 if (new_state == IB_QPS_RESET && 4292 !ibqp->uobject && qp->type != IB_QPT_XRC_TGT) { 4293 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4294 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4295 if (send_cq != recv_cq) 4296 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4297 4298 qp->rq.head = 0; 4299 qp->rq.tail = 0; 4300 qp->sq.head = 0; 4301 qp->sq.tail = 0; 4302 qp->sq.cur_post = 0; 4303 if (qp->sq.wqe_cnt) 4304 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4305 qp->sq.last_poll = 0; 4306 qp->db.db[MLX5_RCV_DBR] = 0; 4307 qp->db.db[MLX5_SND_DBR] = 0; 4308 } 4309 4310 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4311 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4312 if (!err) 4313 qp->counter_pending = 0; 4314 } 4315 4316 out: 4317 kfree(qpc); 4318 return err; 4319 } 4320 4321 static inline bool is_valid_mask(int mask, int req, int opt) 4322 { 4323 if ((mask & req) != req) 4324 return false; 4325 4326 if (mask & ~(req | opt)) 4327 return false; 4328 4329 return true; 4330 } 4331 4332 /* check valid transition for driver QP types 4333 * for now the only QP type that this function supports is DCI 4334 */ 4335 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4336 enum ib_qp_attr_mask attr_mask) 4337 { 4338 int req = IB_QP_STATE; 4339 int opt = 0; 4340 4341 if (new_state == IB_QPS_RESET) { 4342 return is_valid_mask(attr_mask, req, opt); 4343 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4344 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4345 return is_valid_mask(attr_mask, req, opt); 4346 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4347 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4348 return is_valid_mask(attr_mask, req, opt); 4349 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4350 req |= IB_QP_PATH_MTU; 4351 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4352 return is_valid_mask(attr_mask, req, opt); 4353 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4354 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4355 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4356 opt = IB_QP_MIN_RNR_TIMER; 4357 return is_valid_mask(attr_mask, req, opt); 4358 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4359 opt = IB_QP_MIN_RNR_TIMER; 4360 return is_valid_mask(attr_mask, req, opt); 4361 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4362 return is_valid_mask(attr_mask, req, opt); 4363 } 4364 return false; 4365 } 4366 4367 /* mlx5_ib_modify_dct: modify a DCT QP 4368 * valid transitions are: 4369 * RESET to INIT: must set access_flags, pkey_index and port 4370 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4371 * mtu, gid_index and hop_limit 4372 * Other transitions and attributes are illegal 4373 */ 4374 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4375 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4376 struct ib_udata *udata) 4377 { 4378 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4379 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4380 enum ib_qp_state cur_state, new_state; 4381 int required = IB_QP_STATE; 4382 void *dctc; 4383 int err; 4384 4385 if (!(attr_mask & IB_QP_STATE)) 4386 return -EINVAL; 4387 4388 cur_state = qp->state; 4389 new_state = attr->qp_state; 4390 4391 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4392 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4393 /* 4394 * DCT doesn't initialize QP till modify command is executed, 4395 * so we need to overwrite previously set ECE field if user 4396 * provided any value except zero, which means not set/not 4397 * valid. 4398 */ 4399 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4400 4401 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4402 u16 set_id; 4403 4404 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4405 if (!is_valid_mask(attr_mask, required, 0)) 4406 return -EINVAL; 4407 4408 if (attr->port_num == 0 || 4409 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4410 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4411 attr->port_num, dev->num_ports); 4412 return -EINVAL; 4413 } 4414 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4415 MLX5_SET(dctc, dctc, rre, 1); 4416 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4417 MLX5_SET(dctc, dctc, rwe, 1); 4418 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4419 int atomic_mode; 4420 4421 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4422 if (atomic_mode < 0) 4423 return -EOPNOTSUPP; 4424 4425 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4426 MLX5_SET(dctc, dctc, rae, 1); 4427 } 4428 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4429 if (mlx5_lag_is_active(dev->mdev)) 4430 MLX5_SET(dctc, dctc, port, 4431 get_tx_affinity_rr(dev, udata)); 4432 else 4433 MLX5_SET(dctc, dctc, port, attr->port_num); 4434 4435 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4436 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4437 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4438 struct mlx5_ib_modify_qp_resp resp = {}; 4439 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4440 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4441 4442 if (udata->outlen < min_resp_len) 4443 return -EINVAL; 4444 /* 4445 * If we don't have enough space for the ECE options, 4446 * simply indicate it with resp.response_length. 4447 */ 4448 resp.response_length = (udata->outlen < sizeof(resp)) ? 4449 min_resp_len : 4450 sizeof(resp); 4451 4452 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4453 if (!is_valid_mask(attr_mask, required, 0)) 4454 return -EINVAL; 4455 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4456 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4457 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4458 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4459 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4460 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4461 4462 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4463 MLX5_ST_SZ_BYTES(create_dct_in), out, 4464 sizeof(out)); 4465 if (err) 4466 return err; 4467 resp.dctn = qp->dct.mdct.mqp.qpn; 4468 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4469 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4470 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4471 if (err) { 4472 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4473 return err; 4474 } 4475 } else { 4476 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4477 return -EINVAL; 4478 } 4479 4480 qp->state = new_state; 4481 return 0; 4482 } 4483 4484 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4485 struct mlx5_ib_qp *qp) 4486 { 4487 if (dev->profile != &raw_eth_profile) 4488 return true; 4489 4490 if (qp->type == IB_QPT_RAW_PACKET || qp->type == MLX5_IB_QPT_REG_UMR) 4491 return true; 4492 4493 /* Internal QP used for wc testing, with NOPs in wq */ 4494 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 4495 return true; 4496 4497 return false; 4498 } 4499 4500 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4501 int attr_mask, struct ib_udata *udata) 4502 { 4503 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4504 struct mlx5_ib_modify_qp_resp resp = {}; 4505 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4506 struct mlx5_ib_modify_qp ucmd = {}; 4507 enum ib_qp_type qp_type; 4508 enum ib_qp_state cur_state, new_state; 4509 int err = -EINVAL; 4510 4511 if (!mlx5_ib_modify_qp_allowed(dev, qp)) 4512 return -EOPNOTSUPP; 4513 4514 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4515 return -EOPNOTSUPP; 4516 4517 if (ibqp->rwq_ind_tbl) 4518 return -ENOSYS; 4519 4520 if (udata && udata->inlen) { 4521 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4522 return -EINVAL; 4523 4524 if (udata->inlen > sizeof(ucmd) && 4525 !ib_is_udata_cleared(udata, sizeof(ucmd), 4526 udata->inlen - sizeof(ucmd))) 4527 return -EOPNOTSUPP; 4528 4529 if (ib_copy_from_udata(&ucmd, udata, 4530 min(udata->inlen, sizeof(ucmd)))) 4531 return -EFAULT; 4532 4533 if (ucmd.comp_mask || 4534 memchr_inv(&ucmd.burst_info.reserved, 0, 4535 sizeof(ucmd.burst_info.reserved))) 4536 return -EOPNOTSUPP; 4537 4538 } 4539 4540 if (qp->type == IB_QPT_GSI) 4541 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4542 4543 qp_type = (qp->type == MLX5_IB_QPT_HW_GSI) ? IB_QPT_GSI : qp->type; 4544 4545 if (qp_type == MLX5_IB_QPT_DCT) 4546 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4547 4548 mutex_lock(&qp->mutex); 4549 4550 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4551 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4552 4553 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4554 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4555 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4556 attr_mask); 4557 goto out; 4558 } 4559 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4560 qp_type != MLX5_IB_QPT_DCI && 4561 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4562 attr_mask)) { 4563 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4564 cur_state, new_state, qp->type, attr_mask); 4565 goto out; 4566 } else if (qp_type == MLX5_IB_QPT_DCI && 4567 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4568 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4569 cur_state, new_state, qp_type, attr_mask); 4570 goto out; 4571 } 4572 4573 if ((attr_mask & IB_QP_PORT) && 4574 (attr->port_num == 0 || 4575 attr->port_num > dev->num_ports)) { 4576 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4577 attr->port_num, dev->num_ports); 4578 goto out; 4579 } 4580 4581 if ((attr_mask & IB_QP_PKEY_INDEX) && 4582 attr->pkey_index >= dev->pkey_table_len) { 4583 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4584 goto out; 4585 } 4586 4587 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4588 attr->max_rd_atomic > 4589 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4590 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4591 attr->max_rd_atomic); 4592 goto out; 4593 } 4594 4595 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4596 attr->max_dest_rd_atomic > 4597 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4598 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4599 attr->max_dest_rd_atomic); 4600 goto out; 4601 } 4602 4603 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4604 err = 0; 4605 goto out; 4606 } 4607 4608 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4609 new_state, &ucmd, &resp, udata); 4610 4611 /* resp.response_length is set in ECE supported flows only */ 4612 if (!err && resp.response_length && 4613 udata->outlen >= resp.response_length) 4614 /* Return -EFAULT to the user and expect him to destroy QP. */ 4615 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4616 4617 out: 4618 mutex_unlock(&qp->mutex); 4619 return err; 4620 } 4621 4622 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4623 { 4624 switch (mlx5_state) { 4625 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4626 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4627 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4628 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4629 case MLX5_QP_STATE_SQ_DRAINING: 4630 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4631 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4632 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4633 default: return -1; 4634 } 4635 } 4636 4637 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4638 { 4639 switch (mlx5_mig_state) { 4640 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4641 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4642 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4643 default: return -1; 4644 } 4645 } 4646 4647 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4648 struct rdma_ah_attr *ah_attr, void *path) 4649 { 4650 int port = MLX5_GET(ads, path, vhca_port_num); 4651 int static_rate; 4652 4653 memset(ah_attr, 0, sizeof(*ah_attr)); 4654 4655 if (!port || port > ibdev->num_ports) 4656 return; 4657 4658 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4659 4660 rdma_ah_set_port_num(ah_attr, port); 4661 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4662 4663 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4664 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4665 4666 static_rate = MLX5_GET(ads, path, stat_rate); 4667 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4668 if (MLX5_GET(ads, path, grh) || 4669 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4670 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4671 MLX5_GET(ads, path, src_addr_index), 4672 MLX5_GET(ads, path, hop_limit), 4673 MLX5_GET(ads, path, tclass)); 4674 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4675 } 4676 } 4677 4678 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4679 struct mlx5_ib_sq *sq, 4680 u8 *sq_state) 4681 { 4682 int err; 4683 4684 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4685 if (err) 4686 goto out; 4687 sq->state = *sq_state; 4688 4689 out: 4690 return err; 4691 } 4692 4693 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4694 struct mlx5_ib_rq *rq, 4695 u8 *rq_state) 4696 { 4697 void *out; 4698 void *rqc; 4699 int inlen; 4700 int err; 4701 4702 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4703 out = kvzalloc(inlen, GFP_KERNEL); 4704 if (!out) 4705 return -ENOMEM; 4706 4707 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4708 if (err) 4709 goto out; 4710 4711 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4712 *rq_state = MLX5_GET(rqc, rqc, state); 4713 rq->state = *rq_state; 4714 4715 out: 4716 kvfree(out); 4717 return err; 4718 } 4719 4720 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4721 struct mlx5_ib_qp *qp, u8 *qp_state) 4722 { 4723 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4724 [MLX5_RQC_STATE_RST] = { 4725 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4726 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4727 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4728 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4729 }, 4730 [MLX5_RQC_STATE_RDY] = { 4731 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4732 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4733 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4734 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4735 }, 4736 [MLX5_RQC_STATE_ERR] = { 4737 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4738 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4739 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4740 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4741 }, 4742 [MLX5_RQ_STATE_NA] = { 4743 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4744 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4745 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4746 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4747 }, 4748 }; 4749 4750 *qp_state = sqrq_trans[rq_state][sq_state]; 4751 4752 if (*qp_state == MLX5_QP_STATE_BAD) { 4753 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4754 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4755 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4756 return -EINVAL; 4757 } 4758 4759 if (*qp_state == MLX5_QP_STATE) 4760 *qp_state = qp->state; 4761 4762 return 0; 4763 } 4764 4765 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4766 struct mlx5_ib_qp *qp, 4767 u8 *raw_packet_qp_state) 4768 { 4769 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4770 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4771 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4772 int err; 4773 u8 sq_state = MLX5_SQ_STATE_NA; 4774 u8 rq_state = MLX5_RQ_STATE_NA; 4775 4776 if (qp->sq.wqe_cnt) { 4777 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4778 if (err) 4779 return err; 4780 } 4781 4782 if (qp->rq.wqe_cnt) { 4783 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4784 if (err) 4785 return err; 4786 } 4787 4788 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4789 raw_packet_qp_state); 4790 } 4791 4792 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4793 struct ib_qp_attr *qp_attr) 4794 { 4795 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4796 void *qpc, *pri_path, *alt_path; 4797 u32 *outb; 4798 int err; 4799 4800 outb = kzalloc(outlen, GFP_KERNEL); 4801 if (!outb) 4802 return -ENOMEM; 4803 4804 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 4805 if (err) 4806 goto out; 4807 4808 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4809 4810 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4811 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4812 qp_attr->sq_draining = 1; 4813 4814 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4815 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4816 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4817 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4818 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4819 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4820 4821 if (MLX5_GET(qpc, qpc, rre)) 4822 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4823 if (MLX5_GET(qpc, qpc, rwe)) 4824 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4825 if (MLX5_GET(qpc, qpc, rae)) 4826 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4827 4828 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4829 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4830 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4831 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4832 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4833 4834 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4835 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4836 4837 if (qp->type == IB_QPT_RC || qp->type == IB_QPT_UC || 4838 qp->type == IB_QPT_XRC_INI || qp->type == IB_QPT_XRC_TGT) { 4839 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4840 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4841 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4842 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4843 } 4844 4845 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4846 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4847 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4848 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4849 4850 out: 4851 kfree(outb); 4852 return err; 4853 } 4854 4855 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4856 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4857 struct ib_qp_init_attr *qp_init_attr) 4858 { 4859 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4860 u32 *out; 4861 u32 access_flags = 0; 4862 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4863 void *dctc; 4864 int err; 4865 int supported_mask = IB_QP_STATE | 4866 IB_QP_ACCESS_FLAGS | 4867 IB_QP_PORT | 4868 IB_QP_MIN_RNR_TIMER | 4869 IB_QP_AV | 4870 IB_QP_PATH_MTU | 4871 IB_QP_PKEY_INDEX; 4872 4873 if (qp_attr_mask & ~supported_mask) 4874 return -EINVAL; 4875 if (mqp->state != IB_QPS_RTR) 4876 return -EINVAL; 4877 4878 out = kzalloc(outlen, GFP_KERNEL); 4879 if (!out) 4880 return -ENOMEM; 4881 4882 err = mlx5_core_dct_query(dev, dct, out, outlen); 4883 if (err) 4884 goto out; 4885 4886 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4887 4888 if (qp_attr_mask & IB_QP_STATE) 4889 qp_attr->qp_state = IB_QPS_RTR; 4890 4891 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4892 if (MLX5_GET(dctc, dctc, rre)) 4893 access_flags |= IB_ACCESS_REMOTE_READ; 4894 if (MLX5_GET(dctc, dctc, rwe)) 4895 access_flags |= IB_ACCESS_REMOTE_WRITE; 4896 if (MLX5_GET(dctc, dctc, rae)) 4897 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4898 qp_attr->qp_access_flags = access_flags; 4899 } 4900 4901 if (qp_attr_mask & IB_QP_PORT) 4902 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4903 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4904 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4905 if (qp_attr_mask & IB_QP_AV) { 4906 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4907 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4908 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4909 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4910 } 4911 if (qp_attr_mask & IB_QP_PATH_MTU) 4912 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4913 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4914 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4915 out: 4916 kfree(out); 4917 return err; 4918 } 4919 4920 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4921 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4922 { 4923 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4924 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4925 int err = 0; 4926 u8 raw_packet_qp_state; 4927 4928 if (ibqp->rwq_ind_tbl) 4929 return -ENOSYS; 4930 4931 if (qp->type == IB_QPT_GSI) 4932 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4933 qp_init_attr); 4934 4935 /* Not all of output fields are applicable, make sure to zero them */ 4936 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4937 memset(qp_attr, 0, sizeof(*qp_attr)); 4938 4939 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 4940 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4941 qp_attr_mask, qp_init_attr); 4942 4943 mutex_lock(&qp->mutex); 4944 4945 if (qp->type == IB_QPT_RAW_PACKET || 4946 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4947 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4948 if (err) 4949 goto out; 4950 qp->state = raw_packet_qp_state; 4951 qp_attr->port_num = 1; 4952 } else { 4953 err = query_qp_attr(dev, qp, qp_attr); 4954 if (err) 4955 goto out; 4956 } 4957 4958 qp_attr->qp_state = qp->state; 4959 qp_attr->cur_qp_state = qp_attr->qp_state; 4960 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4961 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4962 4963 if (!ibqp->uobject) { 4964 qp_attr->cap.max_send_wr = qp->sq.max_post; 4965 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4966 qp_init_attr->qp_context = ibqp->qp_context; 4967 } else { 4968 qp_attr->cap.max_send_wr = 0; 4969 qp_attr->cap.max_send_sge = 0; 4970 } 4971 4972 qp_init_attr->qp_type = qp->type; 4973 qp_init_attr->recv_cq = ibqp->recv_cq; 4974 qp_init_attr->send_cq = ibqp->send_cq; 4975 qp_init_attr->srq = ibqp->srq; 4976 qp_attr->cap.max_inline_data = qp->max_inline_data; 4977 4978 qp_init_attr->cap = qp_attr->cap; 4979 4980 qp_init_attr->create_flags = qp->flags; 4981 4982 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4983 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4984 4985 out: 4986 mutex_unlock(&qp->mutex); 4987 return err; 4988 } 4989 4990 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 4991 { 4992 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 4993 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 4994 4995 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4996 return -EOPNOTSUPP; 4997 4998 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 4999 } 5000 5001 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5002 { 5003 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5004 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5005 5006 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5007 } 5008 5009 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5010 { 5011 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5012 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5013 struct ib_event event; 5014 5015 if (rwq->ibwq.event_handler) { 5016 event.device = rwq->ibwq.device; 5017 event.element.wq = &rwq->ibwq; 5018 switch (type) { 5019 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5020 event.event = IB_EVENT_WQ_FATAL; 5021 break; 5022 default: 5023 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5024 return; 5025 } 5026 5027 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5028 } 5029 } 5030 5031 static int set_delay_drop(struct mlx5_ib_dev *dev) 5032 { 5033 int err = 0; 5034 5035 mutex_lock(&dev->delay_drop.lock); 5036 if (dev->delay_drop.activate) 5037 goto out; 5038 5039 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 5040 if (err) 5041 goto out; 5042 5043 dev->delay_drop.activate = true; 5044 out: 5045 mutex_unlock(&dev->delay_drop.lock); 5046 5047 if (!err) 5048 atomic_inc(&dev->delay_drop.rqs_cnt); 5049 return err; 5050 } 5051 5052 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5053 struct ib_wq_init_attr *init_attr) 5054 { 5055 struct mlx5_ib_dev *dev; 5056 int has_net_offloads; 5057 __be64 *rq_pas0; 5058 int ts_format; 5059 void *in; 5060 void *rqc; 5061 void *wq; 5062 int inlen; 5063 int err; 5064 5065 dev = to_mdev(pd->device); 5066 5067 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 5068 if (ts_format < 0) 5069 return ts_format; 5070 5071 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5072 in = kvzalloc(inlen, GFP_KERNEL); 5073 if (!in) 5074 return -ENOMEM; 5075 5076 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5077 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5078 MLX5_SET(rqc, rqc, mem_rq_type, 5079 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5080 MLX5_SET(rqc, rqc, ts_format, ts_format); 5081 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5082 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5083 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5084 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5085 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5086 MLX5_SET(wq, wq, wq_type, 5087 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5088 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5089 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5090 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5091 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5092 err = -EOPNOTSUPP; 5093 goto out; 5094 } else { 5095 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5096 } 5097 } 5098 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5099 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5100 /* 5101 * In Firmware number of strides in each WQE is: 5102 * "512 * 2^single_wqe_log_num_of_strides" 5103 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 5104 * accepted as 0 to 9 5105 */ 5106 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 5107 2, 3, 4, 5, 6, 7, 8, 9 }; 5108 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5109 MLX5_SET(wq, wq, log_wqe_stride_size, 5110 rwq->single_stride_log_num_of_bytes - 5111 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5112 MLX5_SET(wq, wq, log_wqe_num_of_strides, 5113 fw_map[rwq->log_num_strides - 5114 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 5115 } 5116 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5117 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5118 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5119 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5120 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5121 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5122 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5123 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5124 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5125 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5126 err = -EOPNOTSUPP; 5127 goto out; 5128 } 5129 } else { 5130 MLX5_SET(rqc, rqc, vsd, 1); 5131 } 5132 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5133 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5134 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5135 err = -EOPNOTSUPP; 5136 goto out; 5137 } 5138 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5139 } 5140 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5141 if (!(dev->ib_dev.attrs.raw_packet_caps & 5142 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5143 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5144 err = -EOPNOTSUPP; 5145 goto out; 5146 } 5147 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5148 } 5149 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5150 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 5151 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 5152 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5153 err = set_delay_drop(dev); 5154 if (err) { 5155 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5156 err); 5157 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5158 } else { 5159 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5160 } 5161 } 5162 out: 5163 kvfree(in); 5164 return err; 5165 } 5166 5167 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5168 struct ib_wq_init_attr *wq_init_attr, 5169 struct mlx5_ib_create_wq *ucmd, 5170 struct mlx5_ib_rwq *rwq) 5171 { 5172 /* Sanity check RQ size before proceeding */ 5173 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5174 return -EINVAL; 5175 5176 if (!ucmd->rq_wqe_count) 5177 return -EINVAL; 5178 5179 rwq->wqe_count = ucmd->rq_wqe_count; 5180 rwq->wqe_shift = ucmd->rq_wqe_shift; 5181 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5182 return -EINVAL; 5183 5184 rwq->log_rq_stride = rwq->wqe_shift; 5185 rwq->log_rq_size = ilog2(rwq->wqe_count); 5186 return 0; 5187 } 5188 5189 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5190 { 5191 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5192 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5193 return false; 5194 5195 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5196 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5197 return false; 5198 5199 return true; 5200 } 5201 5202 static int prepare_user_rq(struct ib_pd *pd, 5203 struct ib_wq_init_attr *init_attr, 5204 struct ib_udata *udata, 5205 struct mlx5_ib_rwq *rwq) 5206 { 5207 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5208 struct mlx5_ib_create_wq ucmd = {}; 5209 int err; 5210 size_t required_cmd_sz; 5211 5212 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 5213 single_stride_log_num_of_bytes); 5214 if (udata->inlen < required_cmd_sz) { 5215 mlx5_ib_dbg(dev, "invalid inlen\n"); 5216 return -EINVAL; 5217 } 5218 5219 if (udata->inlen > sizeof(ucmd) && 5220 !ib_is_udata_cleared(udata, sizeof(ucmd), 5221 udata->inlen - sizeof(ucmd))) { 5222 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5223 return -EOPNOTSUPP; 5224 } 5225 5226 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5227 mlx5_ib_dbg(dev, "copy failed\n"); 5228 return -EFAULT; 5229 } 5230 5231 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5232 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5233 return -EOPNOTSUPP; 5234 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5235 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5236 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5237 return -EOPNOTSUPP; 5238 } 5239 if ((ucmd.single_stride_log_num_of_bytes < 5240 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5241 (ucmd.single_stride_log_num_of_bytes > 5242 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5243 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5244 ucmd.single_stride_log_num_of_bytes, 5245 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5246 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5247 return -EINVAL; 5248 } 5249 if (!log_of_strides_valid(dev, 5250 ucmd.single_wqe_log_num_of_strides)) { 5251 mlx5_ib_dbg( 5252 dev, 5253 "Invalid log num strides (%u. Range is %u - %u)\n", 5254 ucmd.single_wqe_log_num_of_strides, 5255 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5256 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5257 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5258 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5259 return -EINVAL; 5260 } 5261 rwq->single_stride_log_num_of_bytes = 5262 ucmd.single_stride_log_num_of_bytes; 5263 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5264 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5265 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5266 } 5267 5268 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5269 if (err) { 5270 mlx5_ib_dbg(dev, "err %d\n", err); 5271 return err; 5272 } 5273 5274 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5275 if (err) { 5276 mlx5_ib_dbg(dev, "err %d\n", err); 5277 return err; 5278 } 5279 5280 rwq->user_index = ucmd.user_index; 5281 return 0; 5282 } 5283 5284 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5285 struct ib_wq_init_attr *init_attr, 5286 struct ib_udata *udata) 5287 { 5288 struct mlx5_ib_dev *dev; 5289 struct mlx5_ib_rwq *rwq; 5290 struct mlx5_ib_create_wq_resp resp = {}; 5291 size_t min_resp_len; 5292 int err; 5293 5294 if (!udata) 5295 return ERR_PTR(-ENOSYS); 5296 5297 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5298 if (udata->outlen && udata->outlen < min_resp_len) 5299 return ERR_PTR(-EINVAL); 5300 5301 if (!capable(CAP_SYS_RAWIO) && 5302 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5303 return ERR_PTR(-EPERM); 5304 5305 dev = to_mdev(pd->device); 5306 switch (init_attr->wq_type) { 5307 case IB_WQT_RQ: 5308 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5309 if (!rwq) 5310 return ERR_PTR(-ENOMEM); 5311 err = prepare_user_rq(pd, init_attr, udata, rwq); 5312 if (err) 5313 goto err; 5314 err = create_rq(rwq, pd, init_attr); 5315 if (err) 5316 goto err_user_rq; 5317 break; 5318 default: 5319 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5320 init_attr->wq_type); 5321 return ERR_PTR(-EINVAL); 5322 } 5323 5324 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5325 rwq->ibwq.state = IB_WQS_RESET; 5326 if (udata->outlen) { 5327 resp.response_length = offsetofend( 5328 struct mlx5_ib_create_wq_resp, response_length); 5329 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5330 if (err) 5331 goto err_copy; 5332 } 5333 5334 rwq->core_qp.event = mlx5_ib_wq_event; 5335 rwq->ibwq.event_handler = init_attr->event_handler; 5336 return &rwq->ibwq; 5337 5338 err_copy: 5339 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5340 err_user_rq: 5341 destroy_user_rq(dev, pd, rwq, udata); 5342 err: 5343 kfree(rwq); 5344 return ERR_PTR(err); 5345 } 5346 5347 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5348 { 5349 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5350 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5351 int ret; 5352 5353 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5354 if (ret) 5355 return ret; 5356 destroy_user_rq(dev, wq->pd, rwq, udata); 5357 kfree(rwq); 5358 return 0; 5359 } 5360 5361 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5362 struct ib_rwq_ind_table_init_attr *init_attr, 5363 struct ib_udata *udata) 5364 { 5365 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5366 to_mrwq_ind_table(ib_rwq_ind_table); 5367 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5368 int sz = 1 << init_attr->log_ind_tbl_size; 5369 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5370 size_t min_resp_len; 5371 int inlen; 5372 int err; 5373 int i; 5374 u32 *in; 5375 void *rqtc; 5376 5377 if (udata->inlen > 0 && 5378 !ib_is_udata_cleared(udata, 0, 5379 udata->inlen)) 5380 return -EOPNOTSUPP; 5381 5382 if (init_attr->log_ind_tbl_size > 5383 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5384 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5385 init_attr->log_ind_tbl_size, 5386 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5387 return -EINVAL; 5388 } 5389 5390 min_resp_len = 5391 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5392 if (udata->outlen && udata->outlen < min_resp_len) 5393 return -EINVAL; 5394 5395 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5396 in = kvzalloc(inlen, GFP_KERNEL); 5397 if (!in) 5398 return -ENOMEM; 5399 5400 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5401 5402 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5403 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5404 5405 for (i = 0; i < sz; i++) 5406 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5407 5408 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5409 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5410 5411 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5412 kvfree(in); 5413 if (err) 5414 return err; 5415 5416 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5417 if (udata->outlen) { 5418 resp.response_length = 5419 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5420 response_length); 5421 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5422 if (err) 5423 goto err_copy; 5424 } 5425 5426 return 0; 5427 5428 err_copy: 5429 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5430 return err; 5431 } 5432 5433 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5434 { 5435 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5436 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5437 5438 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5439 } 5440 5441 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5442 u32 wq_attr_mask, struct ib_udata *udata) 5443 { 5444 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5445 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5446 struct mlx5_ib_modify_wq ucmd = {}; 5447 size_t required_cmd_sz; 5448 int curr_wq_state; 5449 int wq_state; 5450 int inlen; 5451 int err; 5452 void *rqc; 5453 void *in; 5454 5455 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5456 if (udata->inlen < required_cmd_sz) 5457 return -EINVAL; 5458 5459 if (udata->inlen > sizeof(ucmd) && 5460 !ib_is_udata_cleared(udata, sizeof(ucmd), 5461 udata->inlen - sizeof(ucmd))) 5462 return -EOPNOTSUPP; 5463 5464 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5465 return -EFAULT; 5466 5467 if (ucmd.comp_mask || ucmd.reserved) 5468 return -EOPNOTSUPP; 5469 5470 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5471 in = kvzalloc(inlen, GFP_KERNEL); 5472 if (!in) 5473 return -ENOMEM; 5474 5475 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5476 5477 curr_wq_state = wq_attr->curr_wq_state; 5478 wq_state = wq_attr->wq_state; 5479 if (curr_wq_state == IB_WQS_ERR) 5480 curr_wq_state = MLX5_RQC_STATE_ERR; 5481 if (wq_state == IB_WQS_ERR) 5482 wq_state = MLX5_RQC_STATE_ERR; 5483 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5484 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5485 MLX5_SET(rqc, rqc, state, wq_state); 5486 5487 if (wq_attr_mask & IB_WQ_FLAGS) { 5488 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5489 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5490 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5491 mlx5_ib_dbg(dev, "VLAN offloads are not " 5492 "supported\n"); 5493 err = -EOPNOTSUPP; 5494 goto out; 5495 } 5496 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5497 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5498 MLX5_SET(rqc, rqc, vsd, 5499 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5500 } 5501 5502 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5503 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5504 err = -EOPNOTSUPP; 5505 goto out; 5506 } 5507 } 5508 5509 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5510 u16 set_id; 5511 5512 set_id = mlx5_ib_get_counters_id(dev, 0); 5513 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5514 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5515 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5516 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5517 } else 5518 dev_info_once( 5519 &dev->ib_dev.dev, 5520 "Receive WQ counters are not supported on current FW\n"); 5521 } 5522 5523 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5524 if (!err) 5525 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5526 5527 out: 5528 kvfree(in); 5529 return err; 5530 } 5531 5532 struct mlx5_ib_drain_cqe { 5533 struct ib_cqe cqe; 5534 struct completion done; 5535 }; 5536 5537 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5538 { 5539 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5540 struct mlx5_ib_drain_cqe, 5541 cqe); 5542 5543 complete(&cqe->done); 5544 } 5545 5546 /* This function returns only once the drained WR was completed */ 5547 static void handle_drain_completion(struct ib_cq *cq, 5548 struct mlx5_ib_drain_cqe *sdrain, 5549 struct mlx5_ib_dev *dev) 5550 { 5551 struct mlx5_core_dev *mdev = dev->mdev; 5552 5553 if (cq->poll_ctx == IB_POLL_DIRECT) { 5554 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5555 ib_process_cq_direct(cq, -1); 5556 return; 5557 } 5558 5559 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5560 struct mlx5_ib_cq *mcq = to_mcq(cq); 5561 bool triggered = false; 5562 unsigned long flags; 5563 5564 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5565 /* Make sure that the CQ handler won't run if wasn't run yet */ 5566 if (!mcq->mcq.reset_notify_added) 5567 mcq->mcq.reset_notify_added = 1; 5568 else 5569 triggered = true; 5570 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5571 5572 if (triggered) { 5573 /* Wait for any scheduled/running task to be ended */ 5574 switch (cq->poll_ctx) { 5575 case IB_POLL_SOFTIRQ: 5576 irq_poll_disable(&cq->iop); 5577 irq_poll_enable(&cq->iop); 5578 break; 5579 case IB_POLL_WORKQUEUE: 5580 cancel_work_sync(&cq->work); 5581 break; 5582 default: 5583 WARN_ON_ONCE(1); 5584 } 5585 } 5586 5587 /* Run the CQ handler - this makes sure that the drain WR will 5588 * be processed if wasn't processed yet. 5589 */ 5590 mcq->mcq.comp(&mcq->mcq, NULL); 5591 } 5592 5593 wait_for_completion(&sdrain->done); 5594 } 5595 5596 void mlx5_ib_drain_sq(struct ib_qp *qp) 5597 { 5598 struct ib_cq *cq = qp->send_cq; 5599 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5600 struct mlx5_ib_drain_cqe sdrain; 5601 const struct ib_send_wr *bad_swr; 5602 struct ib_rdma_wr swr = { 5603 .wr = { 5604 .next = NULL, 5605 { .wr_cqe = &sdrain.cqe, }, 5606 .opcode = IB_WR_RDMA_WRITE, 5607 }, 5608 }; 5609 int ret; 5610 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5611 struct mlx5_core_dev *mdev = dev->mdev; 5612 5613 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5614 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5615 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5616 return; 5617 } 5618 5619 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5620 init_completion(&sdrain.done); 5621 5622 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5623 if (ret) { 5624 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5625 return; 5626 } 5627 5628 handle_drain_completion(cq, &sdrain, dev); 5629 } 5630 5631 void mlx5_ib_drain_rq(struct ib_qp *qp) 5632 { 5633 struct ib_cq *cq = qp->recv_cq; 5634 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5635 struct mlx5_ib_drain_cqe rdrain; 5636 struct ib_recv_wr rwr = {}; 5637 const struct ib_recv_wr *bad_rwr; 5638 int ret; 5639 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5640 struct mlx5_core_dev *mdev = dev->mdev; 5641 5642 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5643 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5644 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5645 return; 5646 } 5647 5648 rwr.wr_cqe = &rdrain.cqe; 5649 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5650 init_completion(&rdrain.done); 5651 5652 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5653 if (ret) { 5654 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5655 return; 5656 } 5657 5658 handle_drain_completion(cq, &rdrain, dev); 5659 } 5660 5661 /* 5662 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5663 * the default counter 5664 */ 5665 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5666 { 5667 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5668 struct mlx5_ib_qp *mqp = to_mqp(qp); 5669 int err = 0; 5670 5671 mutex_lock(&mqp->mutex); 5672 if (mqp->state == IB_QPS_RESET) { 5673 qp->counter = counter; 5674 goto out; 5675 } 5676 5677 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5678 err = -EOPNOTSUPP; 5679 goto out; 5680 } 5681 5682 if (mqp->state == IB_QPS_RTS) { 5683 err = __mlx5_ib_qp_set_counter(qp, counter); 5684 if (!err) 5685 qp->counter = counter; 5686 5687 goto out; 5688 } 5689 5690 mqp->counter_pending = 1; 5691 qp->counter = counter; 5692 5693 out: 5694 mutex_unlock(&mqp->mutex); 5695 return err; 5696 } 5697