1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 #include "cmd.h" 41 42 /* not supported currently */ 43 static int wq_signature; 44 45 enum { 46 MLX5_IB_ACK_REQ_FREQ = 8, 47 }; 48 49 enum { 50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 52 MLX5_IB_LINK_TYPE_IB = 0, 53 MLX5_IB_LINK_TYPE_ETH = 1 54 }; 55 56 enum { 57 MLX5_IB_SQ_STRIDE = 6, 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 59 }; 60 61 static const u32 mlx5_ib_opcode[] = { 62 [IB_WR_SEND] = MLX5_OPCODE_SEND, 63 [IB_WR_LSO] = MLX5_OPCODE_LSO, 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 76 }; 77 78 struct mlx5_wqe_eth_pad { 79 u8 rsvd0[16]; 80 }; 81 82 enum raw_qp_set_mask_map { 83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 85 }; 86 87 struct mlx5_modify_raw_qp_param { 88 u16 operation; 89 90 u32 set_mask; /* raw_qp_set_mask_map */ 91 92 struct mlx5_rate_limit rl; 93 94 u8 rq_q_ctr_id; 95 }; 96 97 static void get_cqs(enum ib_qp_type qp_type, 98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 100 101 static int is_qp0(enum ib_qp_type qp_type) 102 { 103 return qp_type == IB_QPT_SMI; 104 } 105 106 static int is_sqp(enum ib_qp_type qp_type) 107 { 108 return is_qp0(qp_type) || is_qp1(qp_type); 109 } 110 111 /** 112 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 113 * 114 * @qp: QP to copy from. 115 * @send: copy from the send queue when non-zero, use the receive queue 116 * otherwise. 117 * @wqe_index: index to start copying from. For send work queues, the 118 * wqe_index is in units of MLX5_SEND_WQE_BB. 119 * For receive work queue, it is the number of work queue 120 * element in the queue. 121 * @buffer: destination buffer. 122 * @length: maximum number of bytes to copy. 123 * 124 * Copies at least a single WQE, but may copy more data. 125 * 126 * Return: the number of bytes copied, or an error code. 127 */ 128 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 129 void *buffer, u32 length, 130 struct mlx5_ib_qp_base *base) 131 { 132 struct ib_device *ibdev = qp->ibqp.device; 133 struct mlx5_ib_dev *dev = to_mdev(ibdev); 134 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 135 size_t offset; 136 size_t wq_end; 137 struct ib_umem *umem = base->ubuffer.umem; 138 u32 first_copy_length; 139 int wqe_length; 140 int ret; 141 142 if (wq->wqe_cnt == 0) { 143 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 144 qp->ibqp.qp_type); 145 return -EINVAL; 146 } 147 148 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 149 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 150 151 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 152 return -EINVAL; 153 154 if (offset > umem->length || 155 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 156 return -EINVAL; 157 158 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 159 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 160 if (ret) 161 return ret; 162 163 if (send) { 164 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 165 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 166 167 wqe_length = ds * MLX5_WQE_DS_UNITS; 168 } else { 169 wqe_length = 1 << wq->wqe_shift; 170 } 171 172 if (wqe_length <= first_copy_length) 173 return first_copy_length; 174 175 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 176 wqe_length - first_copy_length); 177 if (ret) 178 return ret; 179 180 return wqe_length; 181 } 182 183 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 184 { 185 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 186 struct ib_event event; 187 188 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 189 /* This event is only valid for trans_qps */ 190 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 191 } 192 193 if (ibqp->event_handler) { 194 event.device = ibqp->device; 195 event.element.qp = ibqp; 196 switch (type) { 197 case MLX5_EVENT_TYPE_PATH_MIG: 198 event.event = IB_EVENT_PATH_MIG; 199 break; 200 case MLX5_EVENT_TYPE_COMM_EST: 201 event.event = IB_EVENT_COMM_EST; 202 break; 203 case MLX5_EVENT_TYPE_SQ_DRAINED: 204 event.event = IB_EVENT_SQ_DRAINED; 205 break; 206 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 207 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 208 break; 209 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 210 event.event = IB_EVENT_QP_FATAL; 211 break; 212 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 213 event.event = IB_EVENT_PATH_MIG_ERR; 214 break; 215 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 216 event.event = IB_EVENT_QP_REQ_ERR; 217 break; 218 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 219 event.event = IB_EVENT_QP_ACCESS_ERR; 220 break; 221 default: 222 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 223 return; 224 } 225 226 ibqp->event_handler(&event, ibqp->qp_context); 227 } 228 } 229 230 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 231 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 232 { 233 int wqe_size; 234 int wq_size; 235 236 /* Sanity check RQ size before proceeding */ 237 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 238 return -EINVAL; 239 240 if (!has_rq) { 241 qp->rq.max_gs = 0; 242 qp->rq.wqe_cnt = 0; 243 qp->rq.wqe_shift = 0; 244 cap->max_recv_wr = 0; 245 cap->max_recv_sge = 0; 246 } else { 247 if (ucmd) { 248 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 249 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 250 return -EINVAL; 251 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 252 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 253 return -EINVAL; 254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 255 qp->rq.max_post = qp->rq.wqe_cnt; 256 } else { 257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 259 wqe_size = roundup_pow_of_two(wqe_size); 260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 262 qp->rq.wqe_cnt = wq_size / wqe_size; 263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 265 wqe_size, 266 MLX5_CAP_GEN(dev->mdev, 267 max_wqe_sz_rq)); 268 return -EINVAL; 269 } 270 qp->rq.wqe_shift = ilog2(wqe_size); 271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 272 qp->rq.max_post = qp->rq.wqe_cnt; 273 } 274 } 275 276 return 0; 277 } 278 279 static int sq_overhead(struct ib_qp_init_attr *attr) 280 { 281 int size = 0; 282 283 switch (attr->qp_type) { 284 case IB_QPT_XRC_INI: 285 size += sizeof(struct mlx5_wqe_xrc_seg); 286 /* fall through */ 287 case IB_QPT_RC: 288 size += sizeof(struct mlx5_wqe_ctrl_seg) + 289 max(sizeof(struct mlx5_wqe_atomic_seg) + 290 sizeof(struct mlx5_wqe_raddr_seg), 291 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 292 sizeof(struct mlx5_mkey_seg) + 293 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 294 MLX5_IB_UMR_OCTOWORD); 295 break; 296 297 case IB_QPT_XRC_TGT: 298 return 0; 299 300 case IB_QPT_UC: 301 size += sizeof(struct mlx5_wqe_ctrl_seg) + 302 max(sizeof(struct mlx5_wqe_raddr_seg), 303 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 304 sizeof(struct mlx5_mkey_seg)); 305 break; 306 307 case IB_QPT_UD: 308 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 309 size += sizeof(struct mlx5_wqe_eth_pad) + 310 sizeof(struct mlx5_wqe_eth_seg); 311 /* fall through */ 312 case IB_QPT_SMI: 313 case MLX5_IB_QPT_HW_GSI: 314 size += sizeof(struct mlx5_wqe_ctrl_seg) + 315 sizeof(struct mlx5_wqe_datagram_seg); 316 break; 317 318 case MLX5_IB_QPT_REG_UMR: 319 size += sizeof(struct mlx5_wqe_ctrl_seg) + 320 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 321 sizeof(struct mlx5_mkey_seg); 322 break; 323 324 default: 325 return -EINVAL; 326 } 327 328 return size; 329 } 330 331 static int calc_send_wqe(struct ib_qp_init_attr *attr) 332 { 333 int inl_size = 0; 334 int size; 335 336 size = sq_overhead(attr); 337 if (size < 0) 338 return size; 339 340 if (attr->cap.max_inline_data) { 341 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 342 attr->cap.max_inline_data; 343 } 344 345 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 346 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 347 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 348 return MLX5_SIG_WQE_SIZE; 349 else 350 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 351 } 352 353 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 354 { 355 int max_sge; 356 357 if (attr->qp_type == IB_QPT_RC) 358 max_sge = (min_t(int, wqe_size, 512) - 359 sizeof(struct mlx5_wqe_ctrl_seg) - 360 sizeof(struct mlx5_wqe_raddr_seg)) / 361 sizeof(struct mlx5_wqe_data_seg); 362 else if (attr->qp_type == IB_QPT_XRC_INI) 363 max_sge = (min_t(int, wqe_size, 512) - 364 sizeof(struct mlx5_wqe_ctrl_seg) - 365 sizeof(struct mlx5_wqe_xrc_seg) - 366 sizeof(struct mlx5_wqe_raddr_seg)) / 367 sizeof(struct mlx5_wqe_data_seg); 368 else 369 max_sge = (wqe_size - sq_overhead(attr)) / 370 sizeof(struct mlx5_wqe_data_seg); 371 372 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 373 sizeof(struct mlx5_wqe_data_seg)); 374 } 375 376 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 377 struct mlx5_ib_qp *qp) 378 { 379 int wqe_size; 380 int wq_size; 381 382 if (!attr->cap.max_send_wr) 383 return 0; 384 385 wqe_size = calc_send_wqe(attr); 386 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 387 if (wqe_size < 0) 388 return wqe_size; 389 390 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 391 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 392 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 393 return -EINVAL; 394 } 395 396 qp->max_inline_data = wqe_size - sq_overhead(attr) - 397 sizeof(struct mlx5_wqe_inline_seg); 398 attr->cap.max_inline_data = qp->max_inline_data; 399 400 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 401 qp->signature_en = true; 402 403 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 404 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 405 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 406 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 407 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 408 qp->sq.wqe_cnt, 409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 410 return -ENOMEM; 411 } 412 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 413 qp->sq.max_gs = get_send_sge(attr, wqe_size); 414 if (qp->sq.max_gs < attr->cap.max_send_sge) 415 return -ENOMEM; 416 417 attr->cap.max_send_sge = qp->sq.max_gs; 418 qp->sq.max_post = wq_size / wqe_size; 419 attr->cap.max_send_wr = qp->sq.max_post; 420 421 return wq_size; 422 } 423 424 static int set_user_buf_size(struct mlx5_ib_dev *dev, 425 struct mlx5_ib_qp *qp, 426 struct mlx5_ib_create_qp *ucmd, 427 struct mlx5_ib_qp_base *base, 428 struct ib_qp_init_attr *attr) 429 { 430 int desc_sz = 1 << qp->sq.wqe_shift; 431 432 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 433 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 434 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 435 return -EINVAL; 436 } 437 438 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 439 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 440 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 441 return -EINVAL; 442 } 443 444 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 445 446 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 447 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 448 qp->sq.wqe_cnt, 449 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 450 return -EINVAL; 451 } 452 453 if (attr->qp_type == IB_QPT_RAW_PACKET || 454 qp->flags & MLX5_IB_QP_UNDERLAY) { 455 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 456 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 457 } else { 458 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 459 (qp->sq.wqe_cnt << 6); 460 } 461 462 return 0; 463 } 464 465 static int qp_has_rq(struct ib_qp_init_attr *attr) 466 { 467 if (attr->qp_type == IB_QPT_XRC_INI || 468 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 469 attr->qp_type == MLX5_IB_QPT_REG_UMR || 470 !attr->cap.max_recv_wr) 471 return 0; 472 473 return 1; 474 } 475 476 enum { 477 /* this is the first blue flame register in the array of bfregs assigned 478 * to a processes. Since we do not use it for blue flame but rather 479 * regular 64 bit doorbells, we do not need a lock for maintaiing 480 * "odd/even" order 481 */ 482 NUM_NON_BLUE_FLAME_BFREGS = 1, 483 }; 484 485 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 486 { 487 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 488 } 489 490 static int num_med_bfreg(struct mlx5_ib_dev *dev, 491 struct mlx5_bfreg_info *bfregi) 492 { 493 int n; 494 495 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 496 NUM_NON_BLUE_FLAME_BFREGS; 497 498 return n >= 0 ? n : 0; 499 } 500 501 static int first_med_bfreg(struct mlx5_ib_dev *dev, 502 struct mlx5_bfreg_info *bfregi) 503 { 504 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 505 } 506 507 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 508 struct mlx5_bfreg_info *bfregi) 509 { 510 int med; 511 512 med = num_med_bfreg(dev, bfregi); 513 return ++med; 514 } 515 516 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 517 struct mlx5_bfreg_info *bfregi) 518 { 519 int i; 520 521 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 522 if (!bfregi->count[i]) { 523 bfregi->count[i]++; 524 return i; 525 } 526 } 527 528 return -ENOMEM; 529 } 530 531 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 532 struct mlx5_bfreg_info *bfregi) 533 { 534 int minidx = first_med_bfreg(dev, bfregi); 535 int i; 536 537 if (minidx < 0) 538 return minidx; 539 540 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 541 if (bfregi->count[i] < bfregi->count[minidx]) 542 minidx = i; 543 if (!bfregi->count[minidx]) 544 break; 545 } 546 547 bfregi->count[minidx]++; 548 return minidx; 549 } 550 551 static int alloc_bfreg(struct mlx5_ib_dev *dev, 552 struct mlx5_bfreg_info *bfregi) 553 { 554 int bfregn = -ENOMEM; 555 556 mutex_lock(&bfregi->lock); 557 if (bfregi->ver >= 2) { 558 bfregn = alloc_high_class_bfreg(dev, bfregi); 559 if (bfregn < 0) 560 bfregn = alloc_med_class_bfreg(dev, bfregi); 561 } 562 563 if (bfregn < 0) { 564 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 565 bfregn = 0; 566 bfregi->count[bfregn]++; 567 } 568 mutex_unlock(&bfregi->lock); 569 570 return bfregn; 571 } 572 573 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 574 { 575 mutex_lock(&bfregi->lock); 576 bfregi->count[bfregn]--; 577 mutex_unlock(&bfregi->lock); 578 } 579 580 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 581 { 582 switch (state) { 583 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 584 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 585 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 586 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 587 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 588 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 589 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 590 default: return -1; 591 } 592 } 593 594 static int to_mlx5_st(enum ib_qp_type type) 595 { 596 switch (type) { 597 case IB_QPT_RC: return MLX5_QP_ST_RC; 598 case IB_QPT_UC: return MLX5_QP_ST_UC; 599 case IB_QPT_UD: return MLX5_QP_ST_UD; 600 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 601 case IB_QPT_XRC_INI: 602 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 603 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 604 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 605 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 606 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 607 case IB_QPT_RAW_PACKET: 608 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 609 case IB_QPT_MAX: 610 default: return -EINVAL; 611 } 612 } 613 614 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 615 struct mlx5_ib_cq *recv_cq); 616 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 617 struct mlx5_ib_cq *recv_cq); 618 619 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 620 struct mlx5_bfreg_info *bfregi, u32 bfregn, 621 bool dyn_bfreg) 622 { 623 unsigned int bfregs_per_sys_page; 624 u32 index_of_sys_page; 625 u32 offset; 626 627 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 628 MLX5_NON_FP_BFREGS_PER_UAR; 629 index_of_sys_page = bfregn / bfregs_per_sys_page; 630 631 if (dyn_bfreg) { 632 index_of_sys_page += bfregi->num_static_sys_pages; 633 634 if (index_of_sys_page >= bfregi->num_sys_pages) 635 return -EINVAL; 636 637 if (bfregn > bfregi->num_dyn_bfregs || 638 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 639 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 640 return -EINVAL; 641 } 642 } 643 644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 645 return bfregi->sys_pages[index_of_sys_page] + offset; 646 } 647 648 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 649 struct ib_pd *pd, 650 unsigned long addr, size_t size, 651 struct ib_umem **umem, 652 int *npages, int *page_shift, int *ncont, 653 u32 *offset) 654 { 655 int err; 656 657 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 658 if (IS_ERR(*umem)) { 659 mlx5_ib_dbg(dev, "umem_get failed\n"); 660 return PTR_ERR(*umem); 661 } 662 663 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 664 665 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 666 if (err) { 667 mlx5_ib_warn(dev, "bad offset\n"); 668 goto err_umem; 669 } 670 671 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 672 addr, size, *npages, *page_shift, *ncont, *offset); 673 674 return 0; 675 676 err_umem: 677 ib_umem_release(*umem); 678 *umem = NULL; 679 680 return err; 681 } 682 683 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 684 struct mlx5_ib_rwq *rwq) 685 { 686 struct mlx5_ib_ucontext *context; 687 688 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 689 atomic_dec(&dev->delay_drop.rqs_cnt); 690 691 context = to_mucontext(pd->uobject->context); 692 mlx5_ib_db_unmap_user(context, &rwq->db); 693 if (rwq->umem) 694 ib_umem_release(rwq->umem); 695 } 696 697 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 698 struct mlx5_ib_rwq *rwq, 699 struct mlx5_ib_create_wq *ucmd) 700 { 701 struct mlx5_ib_ucontext *context; 702 int page_shift = 0; 703 int npages; 704 u32 offset = 0; 705 int ncont = 0; 706 int err; 707 708 if (!ucmd->buf_addr) 709 return -EINVAL; 710 711 context = to_mucontext(pd->uobject->context); 712 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 713 rwq->buf_size, 0, 0); 714 if (IS_ERR(rwq->umem)) { 715 mlx5_ib_dbg(dev, "umem_get failed\n"); 716 err = PTR_ERR(rwq->umem); 717 return err; 718 } 719 720 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 721 &ncont, NULL); 722 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 723 &rwq->rq_page_offset); 724 if (err) { 725 mlx5_ib_warn(dev, "bad offset\n"); 726 goto err_umem; 727 } 728 729 rwq->rq_num_pas = ncont; 730 rwq->page_shift = page_shift; 731 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 732 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 733 734 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 735 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 736 npages, page_shift, ncont, offset); 737 738 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 739 if (err) { 740 mlx5_ib_dbg(dev, "map failed\n"); 741 goto err_umem; 742 } 743 744 rwq->create_type = MLX5_WQ_USER; 745 return 0; 746 747 err_umem: 748 ib_umem_release(rwq->umem); 749 return err; 750 } 751 752 static int adjust_bfregn(struct mlx5_ib_dev *dev, 753 struct mlx5_bfreg_info *bfregi, int bfregn) 754 { 755 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 756 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 757 } 758 759 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 760 struct mlx5_ib_qp *qp, struct ib_udata *udata, 761 struct ib_qp_init_attr *attr, 762 u32 **in, 763 struct mlx5_ib_create_qp_resp *resp, int *inlen, 764 struct mlx5_ib_qp_base *base) 765 { 766 struct mlx5_ib_ucontext *context; 767 struct mlx5_ib_create_qp ucmd; 768 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 769 int page_shift = 0; 770 int uar_index = 0; 771 int npages; 772 u32 offset = 0; 773 int bfregn; 774 int ncont = 0; 775 __be64 *pas; 776 void *qpc; 777 int err; 778 u16 uid; 779 780 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 781 if (err) { 782 mlx5_ib_dbg(dev, "copy failed\n"); 783 return err; 784 } 785 786 context = to_mucontext(pd->uobject->context); 787 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 788 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 789 ucmd.bfreg_index, true); 790 if (uar_index < 0) 791 return uar_index; 792 793 bfregn = MLX5_IB_INVALID_BFREG; 794 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 795 /* 796 * TBD: should come from the verbs when we have the API 797 */ 798 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 799 bfregn = MLX5_CROSS_CHANNEL_BFREG; 800 } 801 else { 802 bfregn = alloc_bfreg(dev, &context->bfregi); 803 if (bfregn < 0) 804 return bfregn; 805 } 806 807 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 808 if (bfregn != MLX5_IB_INVALID_BFREG) 809 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 810 false); 811 812 qp->rq.offset = 0; 813 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 814 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 815 816 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 817 if (err) 818 goto err_bfreg; 819 820 if (ucmd.buf_addr && ubuffer->buf_size) { 821 ubuffer->buf_addr = ucmd.buf_addr; 822 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 823 ubuffer->buf_size, 824 &ubuffer->umem, &npages, &page_shift, 825 &ncont, &offset); 826 if (err) 827 goto err_bfreg; 828 } else { 829 ubuffer->umem = NULL; 830 } 831 832 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 833 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 834 *in = kvzalloc(*inlen, GFP_KERNEL); 835 if (!*in) { 836 err = -ENOMEM; 837 goto err_umem; 838 } 839 840 uid = (attr->qp_type != IB_QPT_XRC_TGT) ? to_mpd(pd)->uid : 0; 841 MLX5_SET(create_qp_in, *in, uid, uid); 842 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 843 if (ubuffer->umem) 844 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 845 846 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 847 848 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 849 MLX5_SET(qpc, qpc, page_offset, offset); 850 851 MLX5_SET(qpc, qpc, uar_page, uar_index); 852 if (bfregn != MLX5_IB_INVALID_BFREG) 853 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 854 else 855 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 856 qp->bfregn = bfregn; 857 858 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 859 if (err) { 860 mlx5_ib_dbg(dev, "map failed\n"); 861 goto err_free; 862 } 863 864 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 865 if (err) { 866 mlx5_ib_dbg(dev, "copy failed\n"); 867 goto err_unmap; 868 } 869 qp->create_type = MLX5_QP_USER; 870 871 return 0; 872 873 err_unmap: 874 mlx5_ib_db_unmap_user(context, &qp->db); 875 876 err_free: 877 kvfree(*in); 878 879 err_umem: 880 if (ubuffer->umem) 881 ib_umem_release(ubuffer->umem); 882 883 err_bfreg: 884 if (bfregn != MLX5_IB_INVALID_BFREG) 885 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 886 return err; 887 } 888 889 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 890 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 891 { 892 struct mlx5_ib_ucontext *context; 893 894 context = to_mucontext(pd->uobject->context); 895 mlx5_ib_db_unmap_user(context, &qp->db); 896 if (base->ubuffer.umem) 897 ib_umem_release(base->ubuffer.umem); 898 899 /* 900 * Free only the BFREGs which are handled by the kernel. 901 * BFREGs of UARs allocated dynamically are handled by user. 902 */ 903 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 904 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 905 } 906 907 /* get_sq_edge - Get the next nearby edge. 908 * 909 * An 'edge' is defined as the first following address after the end 910 * of the fragment or the SQ. Accordingly, during the WQE construction 911 * which repetitively increases the pointer to write the next data, it 912 * simply should check if it gets to an edge. 913 * 914 * @sq - SQ buffer. 915 * @idx - Stride index in the SQ buffer. 916 * 917 * Return: 918 * The new edge. 919 */ 920 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) 921 { 922 void *fragment_end; 923 924 fragment_end = mlx5_frag_buf_get_wqe 925 (&sq->fbc, 926 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); 927 928 return fragment_end + MLX5_SEND_WQE_BB; 929 } 930 931 static int create_kernel_qp(struct mlx5_ib_dev *dev, 932 struct ib_qp_init_attr *init_attr, 933 struct mlx5_ib_qp *qp, 934 u32 **in, int *inlen, 935 struct mlx5_ib_qp_base *base) 936 { 937 int uar_index; 938 void *qpc; 939 int err; 940 941 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 942 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 943 IB_QP_CREATE_IPOIB_UD_LSO | 944 IB_QP_CREATE_NETIF_QP | 945 mlx5_ib_create_qp_sqpn_qp1())) 946 return -EINVAL; 947 948 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 949 qp->bf.bfreg = &dev->fp_bfreg; 950 else 951 qp->bf.bfreg = &dev->bfreg; 952 953 /* We need to divide by two since each register is comprised of 954 * two buffers of identical size, namely odd and even 955 */ 956 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 957 uar_index = qp->bf.bfreg->index; 958 959 err = calc_sq_size(dev, init_attr, qp); 960 if (err < 0) { 961 mlx5_ib_dbg(dev, "err %d\n", err); 962 return err; 963 } 964 965 qp->rq.offset = 0; 966 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 967 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 968 969 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 970 &qp->buf, dev->mdev->priv.numa_node); 971 if (err) { 972 mlx5_ib_dbg(dev, "err %d\n", err); 973 return err; 974 } 975 976 if (qp->rq.wqe_cnt) 977 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 978 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 979 980 if (qp->sq.wqe_cnt) { 981 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 982 MLX5_SEND_WQE_BB; 983 mlx5_init_fbc_offset(qp->buf.frags + 984 (qp->sq.offset / PAGE_SIZE), 985 ilog2(MLX5_SEND_WQE_BB), 986 ilog2(qp->sq.wqe_cnt), 987 sq_strides_offset, &qp->sq.fbc); 988 989 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 990 } 991 992 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 993 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 994 *in = kvzalloc(*inlen, GFP_KERNEL); 995 if (!*in) { 996 err = -ENOMEM; 997 goto err_buf; 998 } 999 1000 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1001 MLX5_SET(qpc, qpc, uar_page, uar_index); 1002 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1003 1004 /* Set "fast registration enabled" for all kernel QPs */ 1005 MLX5_SET(qpc, qpc, fre, 1); 1006 MLX5_SET(qpc, qpc, rlky, 1); 1007 1008 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 1009 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1010 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1011 } 1012 1013 mlx5_fill_page_frag_array(&qp->buf, 1014 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1015 *in, pas)); 1016 1017 err = mlx5_db_alloc(dev->mdev, &qp->db); 1018 if (err) { 1019 mlx5_ib_dbg(dev, "err %d\n", err); 1020 goto err_free; 1021 } 1022 1023 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1024 sizeof(*qp->sq.wrid), GFP_KERNEL); 1025 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1026 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1027 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1028 sizeof(*qp->rq.wrid), GFP_KERNEL); 1029 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1030 sizeof(*qp->sq.w_list), GFP_KERNEL); 1031 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1032 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1033 1034 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1035 !qp->sq.w_list || !qp->sq.wqe_head) { 1036 err = -ENOMEM; 1037 goto err_wrid; 1038 } 1039 qp->create_type = MLX5_QP_KERNEL; 1040 1041 return 0; 1042 1043 err_wrid: 1044 kvfree(qp->sq.wqe_head); 1045 kvfree(qp->sq.w_list); 1046 kvfree(qp->sq.wrid); 1047 kvfree(qp->sq.wr_data); 1048 kvfree(qp->rq.wrid); 1049 mlx5_db_free(dev->mdev, &qp->db); 1050 1051 err_free: 1052 kvfree(*in); 1053 1054 err_buf: 1055 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1056 return err; 1057 } 1058 1059 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1060 { 1061 kvfree(qp->sq.wqe_head); 1062 kvfree(qp->sq.w_list); 1063 kvfree(qp->sq.wrid); 1064 kvfree(qp->sq.wr_data); 1065 kvfree(qp->rq.wrid); 1066 mlx5_db_free(dev->mdev, &qp->db); 1067 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1068 } 1069 1070 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1071 { 1072 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1073 (attr->qp_type == MLX5_IB_QPT_DCI) || 1074 (attr->qp_type == IB_QPT_XRC_INI)) 1075 return MLX5_SRQ_RQ; 1076 else if (!qp->has_rq) 1077 return MLX5_ZERO_LEN_RQ; 1078 else 1079 return MLX5_NON_ZERO_RQ; 1080 } 1081 1082 static int is_connected(enum ib_qp_type qp_type) 1083 { 1084 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || 1085 qp_type == MLX5_IB_QPT_DCI) 1086 return 1; 1087 1088 return 0; 1089 } 1090 1091 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1092 struct mlx5_ib_qp *qp, 1093 struct mlx5_ib_sq *sq, u32 tdn, 1094 struct ib_pd *pd) 1095 { 1096 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1097 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1098 1099 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1100 MLX5_SET(tisc, tisc, transport_domain, tdn); 1101 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1102 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1103 1104 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1105 } 1106 1107 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1108 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1109 { 1110 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1111 } 1112 1113 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1114 struct mlx5_ib_sq *sq) 1115 { 1116 if (sq->flow_rule) 1117 mlx5_del_flow_rules(sq->flow_rule); 1118 } 1119 1120 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1121 struct mlx5_ib_sq *sq, void *qpin, 1122 struct ib_pd *pd) 1123 { 1124 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1125 __be64 *pas; 1126 void *in; 1127 void *sqc; 1128 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1129 void *wq; 1130 int inlen; 1131 int err; 1132 int page_shift = 0; 1133 int npages; 1134 int ncont = 0; 1135 u32 offset = 0; 1136 1137 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1138 &sq->ubuffer.umem, &npages, &page_shift, 1139 &ncont, &offset); 1140 if (err) 1141 return err; 1142 1143 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1144 in = kvzalloc(inlen, GFP_KERNEL); 1145 if (!in) { 1146 err = -ENOMEM; 1147 goto err_umem; 1148 } 1149 1150 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1151 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1152 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1153 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1154 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1155 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1156 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1157 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1158 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1159 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1160 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1161 MLX5_CAP_ETH(dev->mdev, swp)) 1162 MLX5_SET(sqc, sqc, allow_swp, 1); 1163 1164 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1165 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1166 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1167 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1168 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1169 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1170 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1171 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1172 MLX5_SET(wq, wq, page_offset, offset); 1173 1174 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1175 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1176 1177 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1178 1179 kvfree(in); 1180 1181 if (err) 1182 goto err_umem; 1183 1184 err = create_flow_rule_vport_sq(dev, sq); 1185 if (err) 1186 goto err_flow; 1187 1188 return 0; 1189 1190 err_flow: 1191 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1192 1193 err_umem: 1194 ib_umem_release(sq->ubuffer.umem); 1195 sq->ubuffer.umem = NULL; 1196 1197 return err; 1198 } 1199 1200 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1201 struct mlx5_ib_sq *sq) 1202 { 1203 destroy_flow_rule_vport_sq(dev, sq); 1204 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1205 ib_umem_release(sq->ubuffer.umem); 1206 } 1207 1208 static size_t get_rq_pas_size(void *qpc) 1209 { 1210 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1211 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1212 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1213 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1214 u32 po_quanta = 1 << (log_page_size - 6); 1215 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1216 u32 page_size = 1 << log_page_size; 1217 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1218 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1219 1220 return rq_num_pas * sizeof(u64); 1221 } 1222 1223 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1224 struct mlx5_ib_rq *rq, void *qpin, 1225 size_t qpinlen, struct ib_pd *pd) 1226 { 1227 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1228 __be64 *pas; 1229 __be64 *qp_pas; 1230 void *in; 1231 void *rqc; 1232 void *wq; 1233 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1234 size_t rq_pas_size = get_rq_pas_size(qpc); 1235 size_t inlen; 1236 int err; 1237 1238 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1239 return -EINVAL; 1240 1241 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1242 in = kvzalloc(inlen, GFP_KERNEL); 1243 if (!in) 1244 return -ENOMEM; 1245 1246 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1247 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1248 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1249 MLX5_SET(rqc, rqc, vsd, 1); 1250 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1251 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1252 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1253 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1254 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1255 1256 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1257 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1258 1259 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1260 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1261 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1262 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1263 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1264 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1265 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1266 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1267 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1268 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1269 1270 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1271 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1272 memcpy(pas, qp_pas, rq_pas_size); 1273 1274 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1275 1276 kvfree(in); 1277 1278 return err; 1279 } 1280 1281 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1282 struct mlx5_ib_rq *rq) 1283 { 1284 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1285 } 1286 1287 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1288 { 1289 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1290 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1291 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1292 } 1293 1294 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1295 struct mlx5_ib_rq *rq, 1296 u32 qp_flags_en, 1297 struct ib_pd *pd) 1298 { 1299 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1300 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1301 mlx5_ib_disable_lb(dev, false, true); 1302 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1303 } 1304 1305 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1306 struct mlx5_ib_rq *rq, u32 tdn, 1307 u32 *qp_flags_en, 1308 struct ib_pd *pd) 1309 { 1310 u8 lb_flag = 0; 1311 u32 *in; 1312 void *tirc; 1313 int inlen; 1314 int err; 1315 1316 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1317 in = kvzalloc(inlen, GFP_KERNEL); 1318 if (!in) 1319 return -ENOMEM; 1320 1321 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1322 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1323 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1324 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1325 MLX5_SET(tirc, tirc, transport_domain, tdn); 1326 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1327 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1328 1329 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1330 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1331 1332 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1333 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1334 1335 if (dev->rep) { 1336 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1337 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1338 } 1339 1340 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1341 1342 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1343 1344 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1345 err = mlx5_ib_enable_lb(dev, false, true); 1346 1347 if (err) 1348 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1349 } 1350 kvfree(in); 1351 1352 return err; 1353 } 1354 1355 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1356 u32 *in, size_t inlen, 1357 struct ib_pd *pd, 1358 struct ib_udata *udata, 1359 struct mlx5_ib_create_qp_resp *resp) 1360 { 1361 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1362 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1363 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1364 struct ib_uobject *uobj = pd->uobject; 1365 struct ib_ucontext *ucontext = uobj->context; 1366 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1367 int err; 1368 u32 tdn = mucontext->tdn; 1369 u16 uid = to_mpd(pd)->uid; 1370 1371 if (qp->sq.wqe_cnt) { 1372 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1373 if (err) 1374 return err; 1375 1376 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1377 if (err) 1378 goto err_destroy_tis; 1379 1380 if (uid) { 1381 resp->tisn = sq->tisn; 1382 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1383 resp->sqn = sq->base.mqp.qpn; 1384 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1385 } 1386 1387 sq->base.container_mibqp = qp; 1388 sq->base.mqp.event = mlx5_ib_qp_event; 1389 } 1390 1391 if (qp->rq.wqe_cnt) { 1392 rq->base.container_mibqp = qp; 1393 1394 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1395 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1396 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1397 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1398 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1399 if (err) 1400 goto err_destroy_sq; 1401 1402 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd); 1403 if (err) 1404 goto err_destroy_rq; 1405 1406 if (uid) { 1407 resp->rqn = rq->base.mqp.qpn; 1408 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1409 resp->tirn = rq->tirn; 1410 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1411 } 1412 } 1413 1414 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1415 rq->base.mqp.qpn; 1416 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1417 if (err) 1418 goto err_destroy_tir; 1419 1420 return 0; 1421 1422 err_destroy_tir: 1423 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); 1424 err_destroy_rq: 1425 destroy_raw_packet_qp_rq(dev, rq); 1426 err_destroy_sq: 1427 if (!qp->sq.wqe_cnt) 1428 return err; 1429 destroy_raw_packet_qp_sq(dev, sq); 1430 err_destroy_tis: 1431 destroy_raw_packet_qp_tis(dev, sq, pd); 1432 1433 return err; 1434 } 1435 1436 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1437 struct mlx5_ib_qp *qp) 1438 { 1439 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1440 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1441 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1442 1443 if (qp->rq.wqe_cnt) { 1444 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1445 destroy_raw_packet_qp_rq(dev, rq); 1446 } 1447 1448 if (qp->sq.wqe_cnt) { 1449 destroy_raw_packet_qp_sq(dev, sq); 1450 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1451 } 1452 } 1453 1454 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1455 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1456 { 1457 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1458 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1459 1460 sq->sq = &qp->sq; 1461 rq->rq = &qp->rq; 1462 sq->doorbell = &qp->db; 1463 rq->doorbell = &qp->db; 1464 } 1465 1466 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1467 { 1468 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1469 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1470 mlx5_ib_disable_lb(dev, false, true); 1471 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1472 to_mpd(qp->ibqp.pd)->uid); 1473 } 1474 1475 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1476 struct ib_pd *pd, 1477 struct ib_qp_init_attr *init_attr, 1478 struct ib_udata *udata) 1479 { 1480 struct ib_uobject *uobj = pd->uobject; 1481 struct ib_ucontext *ucontext = uobj->context; 1482 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1483 struct mlx5_ib_create_qp_resp resp = {}; 1484 int inlen; 1485 int err; 1486 u32 *in; 1487 void *tirc; 1488 void *hfso; 1489 u32 selected_fields = 0; 1490 u32 outer_l4; 1491 size_t min_resp_len; 1492 u32 tdn = mucontext->tdn; 1493 struct mlx5_ib_create_qp_rss ucmd = {}; 1494 size_t required_cmd_sz; 1495 u8 lb_flag = 0; 1496 1497 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1498 return -EOPNOTSUPP; 1499 1500 if (init_attr->create_flags || init_attr->send_cq) 1501 return -EINVAL; 1502 1503 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1504 if (udata->outlen < min_resp_len) 1505 return -EINVAL; 1506 1507 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1508 if (udata->inlen < required_cmd_sz) { 1509 mlx5_ib_dbg(dev, "invalid inlen\n"); 1510 return -EINVAL; 1511 } 1512 1513 if (udata->inlen > sizeof(ucmd) && 1514 !ib_is_udata_cleared(udata, sizeof(ucmd), 1515 udata->inlen - sizeof(ucmd))) { 1516 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1517 return -EOPNOTSUPP; 1518 } 1519 1520 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1521 mlx5_ib_dbg(dev, "copy failed\n"); 1522 return -EFAULT; 1523 } 1524 1525 if (ucmd.comp_mask) { 1526 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1527 return -EOPNOTSUPP; 1528 } 1529 1530 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1531 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1532 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { 1533 mlx5_ib_dbg(dev, "invalid flags\n"); 1534 return -EOPNOTSUPP; 1535 } 1536 1537 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1538 !tunnel_offload_supported(dev->mdev)) { 1539 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1540 return -EOPNOTSUPP; 1541 } 1542 1543 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1544 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1545 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1546 return -EOPNOTSUPP; 1547 } 1548 1549 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) { 1550 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1551 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1552 } 1553 1554 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1555 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1556 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1557 } 1558 1559 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1560 if (err) { 1561 mlx5_ib_dbg(dev, "copy failed\n"); 1562 return -EINVAL; 1563 } 1564 1565 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1566 in = kvzalloc(inlen, GFP_KERNEL); 1567 if (!in) 1568 return -ENOMEM; 1569 1570 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1571 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1572 MLX5_SET(tirc, tirc, disp_type, 1573 MLX5_TIRC_DISP_TYPE_INDIRECT); 1574 MLX5_SET(tirc, tirc, indirect_table, 1575 init_attr->rwq_ind_tbl->ind_tbl_num); 1576 MLX5_SET(tirc, tirc, transport_domain, tdn); 1577 1578 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1579 1580 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1581 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1582 1583 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1584 1585 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1586 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1587 else 1588 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1589 1590 switch (ucmd.rx_hash_function) { 1591 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1592 { 1593 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1594 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1595 1596 if (len != ucmd.rx_key_len) { 1597 err = -EINVAL; 1598 goto err; 1599 } 1600 1601 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1602 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1603 memcpy(rss_key, ucmd.rx_hash_key, len); 1604 break; 1605 } 1606 default: 1607 err = -EOPNOTSUPP; 1608 goto err; 1609 } 1610 1611 if (!ucmd.rx_hash_fields_mask) { 1612 /* special case when this TIR serves as steering entry without hashing */ 1613 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1614 goto create_tir; 1615 err = -EINVAL; 1616 goto err; 1617 } 1618 1619 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1620 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1621 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1622 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1623 err = -EINVAL; 1624 goto err; 1625 } 1626 1627 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1628 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1629 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1630 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1631 MLX5_L3_PROT_TYPE_IPV4); 1632 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1633 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1634 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1635 MLX5_L3_PROT_TYPE_IPV6); 1636 1637 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1638 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1639 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1640 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1641 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1642 1643 /* Check that only one l4 protocol is set */ 1644 if (outer_l4 & (outer_l4 - 1)) { 1645 err = -EINVAL; 1646 goto err; 1647 } 1648 1649 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1650 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1651 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1652 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1653 MLX5_L4_PROT_TYPE_TCP); 1654 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1655 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1656 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1657 MLX5_L4_PROT_TYPE_UDP); 1658 1659 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1660 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1661 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1662 1663 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1664 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1665 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1666 1667 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1668 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1669 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1670 1671 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1672 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1673 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1674 1675 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1676 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1677 1678 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1679 1680 create_tir: 1681 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1682 1683 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1684 err = mlx5_ib_enable_lb(dev, false, true); 1685 1686 if (err) 1687 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1688 to_mpd(pd)->uid); 1689 } 1690 1691 if (err) 1692 goto err; 1693 1694 if (mucontext->devx_uid) { 1695 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1696 resp.tirn = qp->rss_qp.tirn; 1697 } 1698 1699 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1700 if (err) 1701 goto err_copy; 1702 1703 kvfree(in); 1704 /* qpn is reserved for that QP */ 1705 qp->trans_qp.base.mqp.qpn = 0; 1706 qp->flags |= MLX5_IB_QP_RSS; 1707 return 0; 1708 1709 err_copy: 1710 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); 1711 err: 1712 kvfree(in); 1713 return err; 1714 } 1715 1716 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, 1717 void *qpc) 1718 { 1719 int rcqe_sz; 1720 1721 if (init_attr->qp_type == MLX5_IB_QPT_DCI) 1722 return; 1723 1724 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1725 1726 if (rcqe_sz == 128) { 1727 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1728 return; 1729 } 1730 1731 if (init_attr->qp_type != MLX5_IB_QPT_DCT) 1732 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1733 } 1734 1735 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1736 struct ib_qp_init_attr *init_attr, 1737 struct mlx5_ib_create_qp *ucmd, 1738 void *qpc) 1739 { 1740 enum ib_qp_type qpt = init_attr->qp_type; 1741 int scqe_sz; 1742 bool allow_scat_cqe = 0; 1743 1744 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) 1745 return; 1746 1747 if (ucmd) 1748 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1749 1750 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1751 return; 1752 1753 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1754 if (scqe_sz == 128) { 1755 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1756 return; 1757 } 1758 1759 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1760 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1761 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1762 } 1763 1764 static int atomic_size_to_mode(int size_mask) 1765 { 1766 /* driver does not support atomic_size > 256B 1767 * and does not know how to translate bigger sizes 1768 */ 1769 int supported_size_mask = size_mask & 0x1ff; 1770 int log_max_size; 1771 1772 if (!supported_size_mask) 1773 return -EOPNOTSUPP; 1774 1775 log_max_size = __fls(supported_size_mask); 1776 1777 if (log_max_size > 3) 1778 return log_max_size; 1779 1780 return MLX5_ATOMIC_MODE_8B; 1781 } 1782 1783 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1784 enum ib_qp_type qp_type) 1785 { 1786 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1787 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1788 int atomic_mode = -EOPNOTSUPP; 1789 int atomic_size_mask; 1790 1791 if (!atomic) 1792 return -EOPNOTSUPP; 1793 1794 if (qp_type == MLX5_IB_QPT_DCT) 1795 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1796 else 1797 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1798 1799 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1800 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1801 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1802 1803 if (atomic_mode <= 0 && 1804 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1805 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1806 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1807 1808 return atomic_mode; 1809 } 1810 1811 static inline bool check_flags_mask(uint64_t input, uint64_t supported) 1812 { 1813 return (input & ~supported) == 0; 1814 } 1815 1816 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1817 struct ib_qp_init_attr *init_attr, 1818 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1819 { 1820 struct mlx5_ib_resources *devr = &dev->devr; 1821 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1822 struct mlx5_core_dev *mdev = dev->mdev; 1823 struct mlx5_ib_create_qp_resp resp = {}; 1824 struct mlx5_ib_cq *send_cq; 1825 struct mlx5_ib_cq *recv_cq; 1826 unsigned long flags; 1827 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1828 struct mlx5_ib_create_qp ucmd; 1829 struct mlx5_ib_qp_base *base; 1830 int mlx5_st; 1831 void *qpc; 1832 u32 *in; 1833 int err; 1834 1835 mutex_init(&qp->mutex); 1836 spin_lock_init(&qp->sq.lock); 1837 spin_lock_init(&qp->rq.lock); 1838 1839 mlx5_st = to_mlx5_st(init_attr->qp_type); 1840 if (mlx5_st < 0) 1841 return -EINVAL; 1842 1843 if (init_attr->rwq_ind_tbl) { 1844 if (!udata) 1845 return -ENOSYS; 1846 1847 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1848 return err; 1849 } 1850 1851 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1852 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1853 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1854 return -EINVAL; 1855 } else { 1856 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1857 } 1858 } 1859 1860 if (init_attr->create_flags & 1861 (IB_QP_CREATE_CROSS_CHANNEL | 1862 IB_QP_CREATE_MANAGED_SEND | 1863 IB_QP_CREATE_MANAGED_RECV)) { 1864 if (!MLX5_CAP_GEN(mdev, cd)) { 1865 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1866 return -EINVAL; 1867 } 1868 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1869 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1870 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1871 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1872 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1873 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1874 } 1875 1876 if (init_attr->qp_type == IB_QPT_UD && 1877 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1878 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1879 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1880 return -EOPNOTSUPP; 1881 } 1882 1883 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1884 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1885 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1886 return -EOPNOTSUPP; 1887 } 1888 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1889 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1890 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1891 return -EOPNOTSUPP; 1892 } 1893 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1894 } 1895 1896 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1897 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1898 1899 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1900 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1901 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1902 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1903 return -EOPNOTSUPP; 1904 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1905 } 1906 1907 if (udata) { 1908 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1909 mlx5_ib_dbg(dev, "copy failed\n"); 1910 return -EFAULT; 1911 } 1912 1913 if (!check_flags_mask(ucmd.flags, 1914 MLX5_QP_FLAG_SIGNATURE | 1915 MLX5_QP_FLAG_SCATTER_CQE | 1916 MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1917 MLX5_QP_FLAG_BFREG_INDEX | 1918 MLX5_QP_FLAG_TYPE_DCT | 1919 MLX5_QP_FLAG_TYPE_DCI | 1920 MLX5_QP_FLAG_ALLOW_SCATTER_CQE | 1921 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)) 1922 return -EINVAL; 1923 1924 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1925 &ucmd, udata->inlen, &uidx); 1926 if (err) 1927 return err; 1928 1929 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1930 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) 1931 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1932 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1933 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1934 !tunnel_offload_supported(mdev)) { 1935 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1936 return -EOPNOTSUPP; 1937 } 1938 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; 1939 } 1940 1941 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { 1942 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1943 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); 1944 return -EOPNOTSUPP; 1945 } 1946 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1947 } 1948 1949 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1950 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1951 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); 1952 return -EOPNOTSUPP; 1953 } 1954 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1955 } 1956 1957 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { 1958 if (init_attr->qp_type != IB_QPT_RC || 1959 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { 1960 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); 1961 return -EOPNOTSUPP; 1962 } 1963 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; 1964 } 1965 1966 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1967 if (init_attr->qp_type != IB_QPT_UD || 1968 (MLX5_CAP_GEN(dev->mdev, port_type) != 1969 MLX5_CAP_PORT_TYPE_IB) || 1970 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1971 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1972 return -EOPNOTSUPP; 1973 } 1974 1975 qp->flags |= MLX5_IB_QP_UNDERLAY; 1976 qp->underlay_qpn = init_attr->source_qpn; 1977 } 1978 } else { 1979 qp->wq_sig = !!wq_signature; 1980 } 1981 1982 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1983 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1984 &qp->raw_packet_qp.rq.base : 1985 &qp->trans_qp.base; 1986 1987 qp->has_rq = qp_has_rq(init_attr); 1988 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1989 qp, udata ? &ucmd : NULL); 1990 if (err) { 1991 mlx5_ib_dbg(dev, "err %d\n", err); 1992 return err; 1993 } 1994 1995 if (pd) { 1996 if (udata) { 1997 __u32 max_wqes = 1998 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1999 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 2000 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 2001 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 2002 mlx5_ib_dbg(dev, "invalid rq params\n"); 2003 return -EINVAL; 2004 } 2005 if (ucmd.sq_wqe_count > max_wqes) { 2006 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 2007 ucmd.sq_wqe_count, max_wqes); 2008 return -EINVAL; 2009 } 2010 if (init_attr->create_flags & 2011 mlx5_ib_create_qp_sqpn_qp1()) { 2012 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 2013 return -EINVAL; 2014 } 2015 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 2016 &resp, &inlen, base); 2017 if (err) 2018 mlx5_ib_dbg(dev, "err %d\n", err); 2019 } else { 2020 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 2021 base); 2022 if (err) 2023 mlx5_ib_dbg(dev, "err %d\n", err); 2024 } 2025 2026 if (err) 2027 return err; 2028 } else { 2029 in = kvzalloc(inlen, GFP_KERNEL); 2030 if (!in) 2031 return -ENOMEM; 2032 2033 qp->create_type = MLX5_QP_EMPTY; 2034 } 2035 2036 if (is_sqp(init_attr->qp_type)) 2037 qp->port = init_attr->port_num; 2038 2039 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2040 2041 MLX5_SET(qpc, qpc, st, mlx5_st); 2042 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2043 2044 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 2045 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2046 else 2047 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2048 2049 2050 if (qp->wq_sig) 2051 MLX5_SET(qpc, qpc, wq_signature, 1); 2052 2053 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2054 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2055 2056 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 2057 MLX5_SET(qpc, qpc, cd_master, 1); 2058 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 2059 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2060 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 2061 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2062 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) 2063 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2064 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 2065 configure_responder_scat_cqe(init_attr, qpc); 2066 configure_requester_scat_cqe(dev, init_attr, 2067 udata ? &ucmd : NULL, 2068 qpc); 2069 } 2070 2071 if (qp->rq.wqe_cnt) { 2072 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2073 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2074 } 2075 2076 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2077 2078 if (qp->sq.wqe_cnt) { 2079 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2080 } else { 2081 MLX5_SET(qpc, qpc, no_sq, 1); 2082 if (init_attr->srq && 2083 init_attr->srq->srq_type == IB_SRQT_TM) 2084 MLX5_SET(qpc, qpc, offload_type, 2085 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2086 } 2087 2088 /* Set default resources */ 2089 switch (init_attr->qp_type) { 2090 case IB_QPT_XRC_TGT: 2091 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2092 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2093 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2094 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 2095 break; 2096 case IB_QPT_XRC_INI: 2097 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2098 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2099 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2100 break; 2101 default: 2102 if (init_attr->srq) { 2103 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2104 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2105 } else { 2106 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2107 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2108 } 2109 } 2110 2111 if (init_attr->send_cq) 2112 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2113 2114 if (init_attr->recv_cq) 2115 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2116 2117 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2118 2119 /* 0xffffff means we ask to work with cqe version 0 */ 2120 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2121 MLX5_SET(qpc, qpc, user_index, uidx); 2122 2123 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2124 if (init_attr->qp_type == IB_QPT_UD && 2125 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 2126 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2127 qp->flags |= MLX5_IB_QP_LSO; 2128 } 2129 2130 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2131 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 2132 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 2133 err = -EOPNOTSUPP; 2134 goto err; 2135 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2136 MLX5_SET(qpc, qpc, end_padding_mode, 2137 MLX5_WQ_END_PAD_MODE_ALIGN); 2138 } else { 2139 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 2140 } 2141 } 2142 2143 if (inlen < 0) { 2144 err = -EINVAL; 2145 goto err; 2146 } 2147 2148 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2149 qp->flags & MLX5_IB_QP_UNDERLAY) { 2150 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 2151 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2152 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2153 &resp); 2154 } else { 2155 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 2156 } 2157 2158 if (err) { 2159 mlx5_ib_dbg(dev, "create qp failed\n"); 2160 goto err_create; 2161 } 2162 2163 kvfree(in); 2164 2165 base->container_mibqp = qp; 2166 base->mqp.event = mlx5_ib_qp_event; 2167 2168 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 2169 &send_cq, &recv_cq); 2170 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2171 mlx5_ib_lock_cqs(send_cq, recv_cq); 2172 /* Maintain device to QPs access, needed for further handling via reset 2173 * flow 2174 */ 2175 list_add_tail(&qp->qps_list, &dev->qp_list); 2176 /* Maintain CQ to QPs access, needed for further handling via reset flow 2177 */ 2178 if (send_cq) 2179 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2180 if (recv_cq) 2181 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2182 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2183 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2184 2185 return 0; 2186 2187 err_create: 2188 if (qp->create_type == MLX5_QP_USER) 2189 destroy_qp_user(dev, pd, qp, base); 2190 else if (qp->create_type == MLX5_QP_KERNEL) 2191 destroy_qp_kernel(dev, qp); 2192 2193 err: 2194 kvfree(in); 2195 return err; 2196 } 2197 2198 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2199 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2200 { 2201 if (send_cq) { 2202 if (recv_cq) { 2203 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2204 spin_lock(&send_cq->lock); 2205 spin_lock_nested(&recv_cq->lock, 2206 SINGLE_DEPTH_NESTING); 2207 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2208 spin_lock(&send_cq->lock); 2209 __acquire(&recv_cq->lock); 2210 } else { 2211 spin_lock(&recv_cq->lock); 2212 spin_lock_nested(&send_cq->lock, 2213 SINGLE_DEPTH_NESTING); 2214 } 2215 } else { 2216 spin_lock(&send_cq->lock); 2217 __acquire(&recv_cq->lock); 2218 } 2219 } else if (recv_cq) { 2220 spin_lock(&recv_cq->lock); 2221 __acquire(&send_cq->lock); 2222 } else { 2223 __acquire(&send_cq->lock); 2224 __acquire(&recv_cq->lock); 2225 } 2226 } 2227 2228 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2229 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2230 { 2231 if (send_cq) { 2232 if (recv_cq) { 2233 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2234 spin_unlock(&recv_cq->lock); 2235 spin_unlock(&send_cq->lock); 2236 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2237 __release(&recv_cq->lock); 2238 spin_unlock(&send_cq->lock); 2239 } else { 2240 spin_unlock(&send_cq->lock); 2241 spin_unlock(&recv_cq->lock); 2242 } 2243 } else { 2244 __release(&recv_cq->lock); 2245 spin_unlock(&send_cq->lock); 2246 } 2247 } else if (recv_cq) { 2248 __release(&send_cq->lock); 2249 spin_unlock(&recv_cq->lock); 2250 } else { 2251 __release(&recv_cq->lock); 2252 __release(&send_cq->lock); 2253 } 2254 } 2255 2256 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2257 { 2258 return to_mpd(qp->ibqp.pd); 2259 } 2260 2261 static void get_cqs(enum ib_qp_type qp_type, 2262 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2263 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2264 { 2265 switch (qp_type) { 2266 case IB_QPT_XRC_TGT: 2267 *send_cq = NULL; 2268 *recv_cq = NULL; 2269 break; 2270 case MLX5_IB_QPT_REG_UMR: 2271 case IB_QPT_XRC_INI: 2272 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2273 *recv_cq = NULL; 2274 break; 2275 2276 case IB_QPT_SMI: 2277 case MLX5_IB_QPT_HW_GSI: 2278 case IB_QPT_RC: 2279 case IB_QPT_UC: 2280 case IB_QPT_UD: 2281 case IB_QPT_RAW_IPV6: 2282 case IB_QPT_RAW_ETHERTYPE: 2283 case IB_QPT_RAW_PACKET: 2284 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2285 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2286 break; 2287 2288 case IB_QPT_MAX: 2289 default: 2290 *send_cq = NULL; 2291 *recv_cq = NULL; 2292 break; 2293 } 2294 } 2295 2296 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2297 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2298 u8 lag_tx_affinity); 2299 2300 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2301 { 2302 struct mlx5_ib_cq *send_cq, *recv_cq; 2303 struct mlx5_ib_qp_base *base; 2304 unsigned long flags; 2305 int err; 2306 2307 if (qp->ibqp.rwq_ind_tbl) { 2308 destroy_rss_raw_qp_tir(dev, qp); 2309 return; 2310 } 2311 2312 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2313 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2314 &qp->raw_packet_qp.rq.base : 2315 &qp->trans_qp.base; 2316 2317 if (qp->state != IB_QPS_RESET) { 2318 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2319 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2320 err = mlx5_core_qp_modify(dev->mdev, 2321 MLX5_CMD_OP_2RST_QP, 0, 2322 NULL, &base->mqp); 2323 } else { 2324 struct mlx5_modify_raw_qp_param raw_qp_param = { 2325 .operation = MLX5_CMD_OP_2RST_QP 2326 }; 2327 2328 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2329 } 2330 if (err) 2331 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2332 base->mqp.qpn); 2333 } 2334 2335 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2336 &send_cq, &recv_cq); 2337 2338 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2339 mlx5_ib_lock_cqs(send_cq, recv_cq); 2340 /* del from lists under both locks above to protect reset flow paths */ 2341 list_del(&qp->qps_list); 2342 if (send_cq) 2343 list_del(&qp->cq_send_list); 2344 2345 if (recv_cq) 2346 list_del(&qp->cq_recv_list); 2347 2348 if (qp->create_type == MLX5_QP_KERNEL) { 2349 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2350 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2351 if (send_cq != recv_cq) 2352 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2353 NULL); 2354 } 2355 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2356 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2357 2358 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2359 qp->flags & MLX5_IB_QP_UNDERLAY) { 2360 destroy_raw_packet_qp(dev, qp); 2361 } else { 2362 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2363 if (err) 2364 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2365 base->mqp.qpn); 2366 } 2367 2368 if (qp->create_type == MLX5_QP_KERNEL) 2369 destroy_qp_kernel(dev, qp); 2370 else if (qp->create_type == MLX5_QP_USER) 2371 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2372 } 2373 2374 static const char *ib_qp_type_str(enum ib_qp_type type) 2375 { 2376 switch (type) { 2377 case IB_QPT_SMI: 2378 return "IB_QPT_SMI"; 2379 case IB_QPT_GSI: 2380 return "IB_QPT_GSI"; 2381 case IB_QPT_RC: 2382 return "IB_QPT_RC"; 2383 case IB_QPT_UC: 2384 return "IB_QPT_UC"; 2385 case IB_QPT_UD: 2386 return "IB_QPT_UD"; 2387 case IB_QPT_RAW_IPV6: 2388 return "IB_QPT_RAW_IPV6"; 2389 case IB_QPT_RAW_ETHERTYPE: 2390 return "IB_QPT_RAW_ETHERTYPE"; 2391 case IB_QPT_XRC_INI: 2392 return "IB_QPT_XRC_INI"; 2393 case IB_QPT_XRC_TGT: 2394 return "IB_QPT_XRC_TGT"; 2395 case IB_QPT_RAW_PACKET: 2396 return "IB_QPT_RAW_PACKET"; 2397 case MLX5_IB_QPT_REG_UMR: 2398 return "MLX5_IB_QPT_REG_UMR"; 2399 case IB_QPT_DRIVER: 2400 return "IB_QPT_DRIVER"; 2401 case IB_QPT_MAX: 2402 default: 2403 return "Invalid QP type"; 2404 } 2405 } 2406 2407 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2408 struct ib_qp_init_attr *attr, 2409 struct mlx5_ib_create_qp *ucmd) 2410 { 2411 struct mlx5_ib_qp *qp; 2412 int err = 0; 2413 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2414 void *dctc; 2415 2416 if (!attr->srq || !attr->recv_cq) 2417 return ERR_PTR(-EINVAL); 2418 2419 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2420 ucmd, sizeof(*ucmd), &uidx); 2421 if (err) 2422 return ERR_PTR(err); 2423 2424 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2425 if (!qp) 2426 return ERR_PTR(-ENOMEM); 2427 2428 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2429 if (!qp->dct.in) { 2430 err = -ENOMEM; 2431 goto err_free; 2432 } 2433 2434 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2435 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2436 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2437 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2438 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2439 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2440 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2441 MLX5_SET(dctc, dctc, user_index, uidx); 2442 2443 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) 2444 configure_responder_scat_cqe(attr, dctc); 2445 2446 qp->state = IB_QPS_RESET; 2447 2448 return &qp->ibqp; 2449 err_free: 2450 kfree(qp); 2451 return ERR_PTR(err); 2452 } 2453 2454 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2455 struct ib_qp_init_attr *init_attr, 2456 struct mlx5_ib_create_qp *ucmd, 2457 struct ib_udata *udata) 2458 { 2459 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2460 int err; 2461 2462 if (!udata) 2463 return -EINVAL; 2464 2465 if (udata->inlen < sizeof(*ucmd)) { 2466 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2467 return -EINVAL; 2468 } 2469 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2470 if (err) 2471 return err; 2472 2473 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2474 init_attr->qp_type = MLX5_IB_QPT_DCI; 2475 } else { 2476 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2477 init_attr->qp_type = MLX5_IB_QPT_DCT; 2478 } else { 2479 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2480 return -EINVAL; 2481 } 2482 } 2483 2484 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2485 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2486 return -EOPNOTSUPP; 2487 } 2488 2489 return 0; 2490 } 2491 2492 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2493 struct ib_qp_init_attr *verbs_init_attr, 2494 struct ib_udata *udata) 2495 { 2496 struct mlx5_ib_dev *dev; 2497 struct mlx5_ib_qp *qp; 2498 u16 xrcdn = 0; 2499 int err; 2500 struct ib_qp_init_attr mlx_init_attr; 2501 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2502 2503 if (pd) { 2504 dev = to_mdev(pd->device); 2505 2506 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2507 if (!udata) { 2508 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2509 return ERR_PTR(-EINVAL); 2510 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2511 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2512 return ERR_PTR(-EINVAL); 2513 } 2514 } 2515 } else { 2516 /* being cautious here */ 2517 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2518 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2519 pr_warn("%s: no PD for transport %s\n", __func__, 2520 ib_qp_type_str(init_attr->qp_type)); 2521 return ERR_PTR(-EINVAL); 2522 } 2523 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2524 } 2525 2526 if (init_attr->qp_type == IB_QPT_DRIVER) { 2527 struct mlx5_ib_create_qp ucmd; 2528 2529 init_attr = &mlx_init_attr; 2530 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2531 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2532 if (err) 2533 return ERR_PTR(err); 2534 2535 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2536 if (init_attr->cap.max_recv_wr || 2537 init_attr->cap.max_recv_sge) { 2538 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2539 return ERR_PTR(-EINVAL); 2540 } 2541 } else { 2542 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2543 } 2544 } 2545 2546 switch (init_attr->qp_type) { 2547 case IB_QPT_XRC_TGT: 2548 case IB_QPT_XRC_INI: 2549 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2550 mlx5_ib_dbg(dev, "XRC not supported\n"); 2551 return ERR_PTR(-ENOSYS); 2552 } 2553 init_attr->recv_cq = NULL; 2554 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2555 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2556 init_attr->send_cq = NULL; 2557 } 2558 2559 /* fall through */ 2560 case IB_QPT_RAW_PACKET: 2561 case IB_QPT_RC: 2562 case IB_QPT_UC: 2563 case IB_QPT_UD: 2564 case IB_QPT_SMI: 2565 case MLX5_IB_QPT_HW_GSI: 2566 case MLX5_IB_QPT_REG_UMR: 2567 case MLX5_IB_QPT_DCI: 2568 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2569 if (!qp) 2570 return ERR_PTR(-ENOMEM); 2571 2572 err = create_qp_common(dev, pd, init_attr, udata, qp); 2573 if (err) { 2574 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2575 kfree(qp); 2576 return ERR_PTR(err); 2577 } 2578 2579 if (is_qp0(init_attr->qp_type)) 2580 qp->ibqp.qp_num = 0; 2581 else if (is_qp1(init_attr->qp_type)) 2582 qp->ibqp.qp_num = 1; 2583 else 2584 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2585 2586 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2587 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2588 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2589 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2590 2591 qp->trans_qp.xrcdn = xrcdn; 2592 2593 break; 2594 2595 case IB_QPT_GSI: 2596 return mlx5_ib_gsi_create_qp(pd, init_attr); 2597 2598 case IB_QPT_RAW_IPV6: 2599 case IB_QPT_RAW_ETHERTYPE: 2600 case IB_QPT_MAX: 2601 default: 2602 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2603 init_attr->qp_type); 2604 /* Don't support raw QPs */ 2605 return ERR_PTR(-EINVAL); 2606 } 2607 2608 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2609 qp->qp_sub_type = init_attr->qp_type; 2610 2611 return &qp->ibqp; 2612 } 2613 2614 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2615 { 2616 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2617 2618 if (mqp->state == IB_QPS_RTR) { 2619 int err; 2620 2621 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2622 if (err) { 2623 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2624 return err; 2625 } 2626 } 2627 2628 kfree(mqp->dct.in); 2629 kfree(mqp); 2630 return 0; 2631 } 2632 2633 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2634 { 2635 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2636 struct mlx5_ib_qp *mqp = to_mqp(qp); 2637 2638 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2639 return mlx5_ib_gsi_destroy_qp(qp); 2640 2641 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2642 return mlx5_ib_destroy_dct(mqp); 2643 2644 destroy_qp_common(dev, mqp); 2645 2646 kfree(mqp); 2647 2648 return 0; 2649 } 2650 2651 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2652 const struct ib_qp_attr *attr, 2653 int attr_mask, __be32 *hw_access_flags) 2654 { 2655 u8 dest_rd_atomic; 2656 u32 access_flags; 2657 2658 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2659 2660 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2661 dest_rd_atomic = attr->max_dest_rd_atomic; 2662 else 2663 dest_rd_atomic = qp->trans_qp.resp_depth; 2664 2665 if (attr_mask & IB_QP_ACCESS_FLAGS) 2666 access_flags = attr->qp_access_flags; 2667 else 2668 access_flags = qp->trans_qp.atomic_rd_en; 2669 2670 if (!dest_rd_atomic) 2671 access_flags &= IB_ACCESS_REMOTE_WRITE; 2672 2673 if (access_flags & IB_ACCESS_REMOTE_READ) 2674 *hw_access_flags |= MLX5_QP_BIT_RRE; 2675 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2676 int atomic_mode; 2677 2678 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2679 if (atomic_mode < 0) 2680 return -EOPNOTSUPP; 2681 2682 *hw_access_flags |= MLX5_QP_BIT_RAE; 2683 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; 2684 } 2685 2686 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2687 *hw_access_flags |= MLX5_QP_BIT_RWE; 2688 2689 *hw_access_flags = cpu_to_be32(*hw_access_flags); 2690 2691 return 0; 2692 } 2693 2694 enum { 2695 MLX5_PATH_FLAG_FL = 1 << 0, 2696 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2697 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2698 }; 2699 2700 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2701 { 2702 if (rate == IB_RATE_PORT_CURRENT) 2703 return 0; 2704 2705 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 2706 return -EINVAL; 2707 2708 while (rate != IB_RATE_PORT_CURRENT && 2709 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2710 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2711 --rate; 2712 2713 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2714 } 2715 2716 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2717 struct mlx5_ib_sq *sq, u8 sl, 2718 struct ib_pd *pd) 2719 { 2720 void *in; 2721 void *tisc; 2722 int inlen; 2723 int err; 2724 2725 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2726 in = kvzalloc(inlen, GFP_KERNEL); 2727 if (!in) 2728 return -ENOMEM; 2729 2730 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2731 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2732 2733 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2734 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2735 2736 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2737 2738 kvfree(in); 2739 2740 return err; 2741 } 2742 2743 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2744 struct mlx5_ib_sq *sq, u8 tx_affinity, 2745 struct ib_pd *pd) 2746 { 2747 void *in; 2748 void *tisc; 2749 int inlen; 2750 int err; 2751 2752 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2753 in = kvzalloc(inlen, GFP_KERNEL); 2754 if (!in) 2755 return -ENOMEM; 2756 2757 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2758 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2759 2760 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2761 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2762 2763 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2764 2765 kvfree(in); 2766 2767 return err; 2768 } 2769 2770 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2771 const struct rdma_ah_attr *ah, 2772 struct mlx5_qp_path *path, u8 port, int attr_mask, 2773 u32 path_flags, const struct ib_qp_attr *attr, 2774 bool alt) 2775 { 2776 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2777 int err; 2778 enum ib_gid_type gid_type; 2779 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2780 u8 sl = rdma_ah_get_sl(ah); 2781 2782 if (attr_mask & IB_QP_PKEY_INDEX) 2783 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2784 attr->pkey_index); 2785 2786 if (ah_flags & IB_AH_GRH) { 2787 if (grh->sgid_index >= 2788 dev->mdev->port_caps[port - 1].gid_table_len) { 2789 pr_err("sgid_index (%u) too large. max is %d\n", 2790 grh->sgid_index, 2791 dev->mdev->port_caps[port - 1].gid_table_len); 2792 return -EINVAL; 2793 } 2794 } 2795 2796 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2797 if (!(ah_flags & IB_AH_GRH)) 2798 return -EINVAL; 2799 2800 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2801 if (qp->ibqp.qp_type == IB_QPT_RC || 2802 qp->ibqp.qp_type == IB_QPT_UC || 2803 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2804 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2805 path->udp_sport = 2806 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); 2807 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2808 gid_type = ah->grh.sgid_attr->gid_type; 2809 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2810 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2811 } else { 2812 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2813 path->fl_free_ar |= 2814 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2815 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2816 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2817 if (ah_flags & IB_AH_GRH) 2818 path->grh_mlid |= 1 << 7; 2819 path->dci_cfi_prio_sl = sl & 0xf; 2820 } 2821 2822 if (ah_flags & IB_AH_GRH) { 2823 path->mgid_index = grh->sgid_index; 2824 path->hop_limit = grh->hop_limit; 2825 path->tclass_flowlabel = 2826 cpu_to_be32((grh->traffic_class << 20) | 2827 (grh->flow_label)); 2828 memcpy(path->rgid, grh->dgid.raw, 16); 2829 } 2830 2831 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2832 if (err < 0) 2833 return err; 2834 path->static_rate = err; 2835 path->port = port; 2836 2837 if (attr_mask & IB_QP_TIMEOUT) 2838 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2839 2840 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2841 return modify_raw_packet_eth_prio(dev->mdev, 2842 &qp->raw_packet_qp.sq, 2843 sl & 0xf, qp->ibqp.pd); 2844 2845 return 0; 2846 } 2847 2848 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2849 [MLX5_QP_STATE_INIT] = { 2850 [MLX5_QP_STATE_INIT] = { 2851 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2852 MLX5_QP_OPTPAR_RAE | 2853 MLX5_QP_OPTPAR_RWE | 2854 MLX5_QP_OPTPAR_PKEY_INDEX | 2855 MLX5_QP_OPTPAR_PRI_PORT, 2856 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2857 MLX5_QP_OPTPAR_PKEY_INDEX | 2858 MLX5_QP_OPTPAR_PRI_PORT, 2859 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2860 MLX5_QP_OPTPAR_Q_KEY | 2861 MLX5_QP_OPTPAR_PRI_PORT, 2862 }, 2863 [MLX5_QP_STATE_RTR] = { 2864 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2865 MLX5_QP_OPTPAR_RRE | 2866 MLX5_QP_OPTPAR_RAE | 2867 MLX5_QP_OPTPAR_RWE | 2868 MLX5_QP_OPTPAR_PKEY_INDEX, 2869 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2870 MLX5_QP_OPTPAR_RWE | 2871 MLX5_QP_OPTPAR_PKEY_INDEX, 2872 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2873 MLX5_QP_OPTPAR_Q_KEY, 2874 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2875 MLX5_QP_OPTPAR_Q_KEY, 2876 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2877 MLX5_QP_OPTPAR_RRE | 2878 MLX5_QP_OPTPAR_RAE | 2879 MLX5_QP_OPTPAR_RWE | 2880 MLX5_QP_OPTPAR_PKEY_INDEX, 2881 }, 2882 }, 2883 [MLX5_QP_STATE_RTR] = { 2884 [MLX5_QP_STATE_RTS] = { 2885 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2886 MLX5_QP_OPTPAR_RRE | 2887 MLX5_QP_OPTPAR_RAE | 2888 MLX5_QP_OPTPAR_RWE | 2889 MLX5_QP_OPTPAR_PM_STATE | 2890 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2891 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2892 MLX5_QP_OPTPAR_RWE | 2893 MLX5_QP_OPTPAR_PM_STATE, 2894 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2895 }, 2896 }, 2897 [MLX5_QP_STATE_RTS] = { 2898 [MLX5_QP_STATE_RTS] = { 2899 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2900 MLX5_QP_OPTPAR_RAE | 2901 MLX5_QP_OPTPAR_RWE | 2902 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2903 MLX5_QP_OPTPAR_PM_STATE | 2904 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2905 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2906 MLX5_QP_OPTPAR_PM_STATE | 2907 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2908 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2909 MLX5_QP_OPTPAR_SRQN | 2910 MLX5_QP_OPTPAR_CQN_RCV, 2911 }, 2912 }, 2913 [MLX5_QP_STATE_SQER] = { 2914 [MLX5_QP_STATE_RTS] = { 2915 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2916 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2917 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2918 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2919 MLX5_QP_OPTPAR_RWE | 2920 MLX5_QP_OPTPAR_RAE | 2921 MLX5_QP_OPTPAR_RRE, 2922 }, 2923 }, 2924 }; 2925 2926 static int ib_nr_to_mlx5_nr(int ib_mask) 2927 { 2928 switch (ib_mask) { 2929 case IB_QP_STATE: 2930 return 0; 2931 case IB_QP_CUR_STATE: 2932 return 0; 2933 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2934 return 0; 2935 case IB_QP_ACCESS_FLAGS: 2936 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2937 MLX5_QP_OPTPAR_RAE; 2938 case IB_QP_PKEY_INDEX: 2939 return MLX5_QP_OPTPAR_PKEY_INDEX; 2940 case IB_QP_PORT: 2941 return MLX5_QP_OPTPAR_PRI_PORT; 2942 case IB_QP_QKEY: 2943 return MLX5_QP_OPTPAR_Q_KEY; 2944 case IB_QP_AV: 2945 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2946 MLX5_QP_OPTPAR_PRI_PORT; 2947 case IB_QP_PATH_MTU: 2948 return 0; 2949 case IB_QP_TIMEOUT: 2950 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2951 case IB_QP_RETRY_CNT: 2952 return MLX5_QP_OPTPAR_RETRY_COUNT; 2953 case IB_QP_RNR_RETRY: 2954 return MLX5_QP_OPTPAR_RNR_RETRY; 2955 case IB_QP_RQ_PSN: 2956 return 0; 2957 case IB_QP_MAX_QP_RD_ATOMIC: 2958 return MLX5_QP_OPTPAR_SRA_MAX; 2959 case IB_QP_ALT_PATH: 2960 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2961 case IB_QP_MIN_RNR_TIMER: 2962 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2963 case IB_QP_SQ_PSN: 2964 return 0; 2965 case IB_QP_MAX_DEST_RD_ATOMIC: 2966 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2967 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2968 case IB_QP_PATH_MIG_STATE: 2969 return MLX5_QP_OPTPAR_PM_STATE; 2970 case IB_QP_CAP: 2971 return 0; 2972 case IB_QP_DEST_QPN: 2973 return 0; 2974 } 2975 return 0; 2976 } 2977 2978 static int ib_mask_to_mlx5_opt(int ib_mask) 2979 { 2980 int result = 0; 2981 int i; 2982 2983 for (i = 0; i < 8 * sizeof(int); i++) { 2984 if ((1 << i) & ib_mask) 2985 result |= ib_nr_to_mlx5_nr(1 << i); 2986 } 2987 2988 return result; 2989 } 2990 2991 static int modify_raw_packet_qp_rq( 2992 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 2993 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 2994 { 2995 void *in; 2996 void *rqc; 2997 int inlen; 2998 int err; 2999 3000 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3001 in = kvzalloc(inlen, GFP_KERNEL); 3002 if (!in) 3003 return -ENOMEM; 3004 3005 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3006 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3007 3008 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3009 MLX5_SET(rqc, rqc, state, new_state); 3010 3011 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3012 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3013 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3014 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3015 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3016 } else 3017 dev_info_once( 3018 &dev->ib_dev.dev, 3019 "RAW PACKET QP counters are not supported on current FW\n"); 3020 } 3021 3022 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 3023 if (err) 3024 goto out; 3025 3026 rq->state = new_state; 3027 3028 out: 3029 kvfree(in); 3030 return err; 3031 } 3032 3033 static int modify_raw_packet_qp_sq( 3034 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3035 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3036 { 3037 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3038 struct mlx5_rate_limit old_rl = ibqp->rl; 3039 struct mlx5_rate_limit new_rl = old_rl; 3040 bool new_rate_added = false; 3041 u16 rl_index = 0; 3042 void *in; 3043 void *sqc; 3044 int inlen; 3045 int err; 3046 3047 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3048 in = kvzalloc(inlen, GFP_KERNEL); 3049 if (!in) 3050 return -ENOMEM; 3051 3052 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3053 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3054 3055 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3056 MLX5_SET(sqc, sqc, state, new_state); 3057 3058 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3059 if (new_state != MLX5_SQC_STATE_RDY) 3060 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3061 __func__); 3062 else 3063 new_rl = raw_qp_param->rl; 3064 } 3065 3066 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3067 if (new_rl.rate) { 3068 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3069 if (err) { 3070 pr_err("Failed configuring rate limit(err %d): \ 3071 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3072 err, new_rl.rate, new_rl.max_burst_sz, 3073 new_rl.typical_pkt_sz); 3074 3075 goto out; 3076 } 3077 new_rate_added = true; 3078 } 3079 3080 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3081 /* index 0 means no limit */ 3082 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3083 } 3084 3085 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 3086 if (err) { 3087 /* Remove new rate from table if failed */ 3088 if (new_rate_added) 3089 mlx5_rl_remove_rate(dev, &new_rl); 3090 goto out; 3091 } 3092 3093 /* Only remove the old rate after new rate was set */ 3094 if ((old_rl.rate && 3095 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3096 (new_state != MLX5_SQC_STATE_RDY)) 3097 mlx5_rl_remove_rate(dev, &old_rl); 3098 3099 ibqp->rl = new_rl; 3100 sq->state = new_state; 3101 3102 out: 3103 kvfree(in); 3104 return err; 3105 } 3106 3107 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3108 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3109 u8 tx_affinity) 3110 { 3111 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3112 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3113 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3114 int modify_rq = !!qp->rq.wqe_cnt; 3115 int modify_sq = !!qp->sq.wqe_cnt; 3116 int rq_state; 3117 int sq_state; 3118 int err; 3119 3120 switch (raw_qp_param->operation) { 3121 case MLX5_CMD_OP_RST2INIT_QP: 3122 rq_state = MLX5_RQC_STATE_RDY; 3123 sq_state = MLX5_SQC_STATE_RDY; 3124 break; 3125 case MLX5_CMD_OP_2ERR_QP: 3126 rq_state = MLX5_RQC_STATE_ERR; 3127 sq_state = MLX5_SQC_STATE_ERR; 3128 break; 3129 case MLX5_CMD_OP_2RST_QP: 3130 rq_state = MLX5_RQC_STATE_RST; 3131 sq_state = MLX5_SQC_STATE_RST; 3132 break; 3133 case MLX5_CMD_OP_RTR2RTS_QP: 3134 case MLX5_CMD_OP_RTS2RTS_QP: 3135 if (raw_qp_param->set_mask == 3136 MLX5_RAW_QP_RATE_LIMIT) { 3137 modify_rq = 0; 3138 sq_state = sq->state; 3139 } else { 3140 return raw_qp_param->set_mask ? -EINVAL : 0; 3141 } 3142 break; 3143 case MLX5_CMD_OP_INIT2INIT_QP: 3144 case MLX5_CMD_OP_INIT2RTR_QP: 3145 if (raw_qp_param->set_mask) 3146 return -EINVAL; 3147 else 3148 return 0; 3149 default: 3150 WARN_ON(1); 3151 return -EINVAL; 3152 } 3153 3154 if (modify_rq) { 3155 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3156 qp->ibqp.pd); 3157 if (err) 3158 return err; 3159 } 3160 3161 if (modify_sq) { 3162 if (tx_affinity) { 3163 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3164 tx_affinity, 3165 qp->ibqp.pd); 3166 if (err) 3167 return err; 3168 } 3169 3170 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3171 raw_qp_param, qp->ibqp.pd); 3172 } 3173 3174 return 0; 3175 } 3176 3177 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, 3178 struct mlx5_ib_pd *pd, 3179 struct mlx5_ib_qp_base *qp_base, 3180 u8 port_num) 3181 { 3182 struct mlx5_ib_ucontext *ucontext = NULL; 3183 unsigned int tx_port_affinity; 3184 3185 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context) 3186 ucontext = to_mucontext(pd->ibpd.uobject->context); 3187 3188 if (ucontext) { 3189 tx_port_affinity = (unsigned int)atomic_add_return( 3190 1, &ucontext->tx_port_affinity) % 3191 MLX5_MAX_PORTS + 3192 1; 3193 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3194 tx_port_affinity, qp_base->mqp.qpn, ucontext); 3195 } else { 3196 tx_port_affinity = 3197 (unsigned int)atomic_add_return( 3198 1, &dev->roce[port_num].tx_port_affinity) % 3199 MLX5_MAX_PORTS + 3200 1; 3201 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3202 tx_port_affinity, qp_base->mqp.qpn); 3203 } 3204 3205 return tx_port_affinity; 3206 } 3207 3208 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3209 const struct ib_qp_attr *attr, int attr_mask, 3210 enum ib_qp_state cur_state, enum ib_qp_state new_state, 3211 const struct mlx5_ib_modify_qp *ucmd) 3212 { 3213 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3214 [MLX5_QP_STATE_RST] = { 3215 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3216 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3217 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3218 }, 3219 [MLX5_QP_STATE_INIT] = { 3220 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3221 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3222 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3223 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3224 }, 3225 [MLX5_QP_STATE_RTR] = { 3226 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3227 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3228 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3229 }, 3230 [MLX5_QP_STATE_RTS] = { 3231 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3232 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3233 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3234 }, 3235 [MLX5_QP_STATE_SQD] = { 3236 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3237 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3238 }, 3239 [MLX5_QP_STATE_SQER] = { 3240 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3241 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3242 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3243 }, 3244 [MLX5_QP_STATE_ERR] = { 3245 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3246 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3247 } 3248 }; 3249 3250 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3251 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3252 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3253 struct mlx5_ib_cq *send_cq, *recv_cq; 3254 struct mlx5_qp_context *context; 3255 struct mlx5_ib_pd *pd; 3256 struct mlx5_ib_port *mibport = NULL; 3257 enum mlx5_qp_state mlx5_cur, mlx5_new; 3258 enum mlx5_qp_optpar optpar; 3259 int mlx5_st; 3260 int err; 3261 u16 op; 3262 u8 tx_affinity = 0; 3263 3264 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3265 qp->qp_sub_type : ibqp->qp_type); 3266 if (mlx5_st < 0) 3267 return -EINVAL; 3268 3269 context = kzalloc(sizeof(*context), GFP_KERNEL); 3270 if (!context) 3271 return -ENOMEM; 3272 3273 pd = get_pd(qp); 3274 context->flags = cpu_to_be32(mlx5_st << 16); 3275 3276 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3277 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3278 } else { 3279 switch (attr->path_mig_state) { 3280 case IB_MIG_MIGRATED: 3281 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3282 break; 3283 case IB_MIG_REARM: 3284 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3285 break; 3286 case IB_MIG_ARMED: 3287 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3288 break; 3289 } 3290 } 3291 3292 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3293 if ((ibqp->qp_type == IB_QPT_RC) || 3294 (ibqp->qp_type == IB_QPT_UD && 3295 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3296 (ibqp->qp_type == IB_QPT_UC) || 3297 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3298 (ibqp->qp_type == IB_QPT_XRC_INI) || 3299 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3300 if (dev->lag_active) { 3301 u8 p = mlx5_core_native_port_num(dev->mdev); 3302 tx_affinity = get_tx_affinity(dev, pd, base, p); 3303 context->flags |= cpu_to_be32(tx_affinity << 24); 3304 } 3305 } 3306 } 3307 3308 if (is_sqp(ibqp->qp_type)) { 3309 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3310 } else if ((ibqp->qp_type == IB_QPT_UD && 3311 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3312 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3313 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3314 } else if (attr_mask & IB_QP_PATH_MTU) { 3315 if (attr->path_mtu < IB_MTU_256 || 3316 attr->path_mtu > IB_MTU_4096) { 3317 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3318 err = -EINVAL; 3319 goto out; 3320 } 3321 context->mtu_msgmax = (attr->path_mtu << 5) | 3322 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3323 } 3324 3325 if (attr_mask & IB_QP_DEST_QPN) 3326 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3327 3328 if (attr_mask & IB_QP_PKEY_INDEX) 3329 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3330 3331 /* todo implement counter_index functionality */ 3332 3333 if (is_sqp(ibqp->qp_type)) 3334 context->pri_path.port = qp->port; 3335 3336 if (attr_mask & IB_QP_PORT) 3337 context->pri_path.port = attr->port_num; 3338 3339 if (attr_mask & IB_QP_AV) { 3340 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3341 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3342 attr_mask, 0, attr, false); 3343 if (err) 3344 goto out; 3345 } 3346 3347 if (attr_mask & IB_QP_TIMEOUT) 3348 context->pri_path.ackto_lt |= attr->timeout << 3; 3349 3350 if (attr_mask & IB_QP_ALT_PATH) { 3351 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3352 &context->alt_path, 3353 attr->alt_port_num, 3354 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3355 0, attr, true); 3356 if (err) 3357 goto out; 3358 } 3359 3360 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3361 &send_cq, &recv_cq); 3362 3363 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3364 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3365 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3366 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3367 3368 if (attr_mask & IB_QP_RNR_RETRY) 3369 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3370 3371 if (attr_mask & IB_QP_RETRY_CNT) 3372 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3373 3374 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3375 if (attr->max_rd_atomic) 3376 context->params1 |= 3377 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3378 } 3379 3380 if (attr_mask & IB_QP_SQ_PSN) 3381 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3382 3383 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3384 if (attr->max_dest_rd_atomic) 3385 context->params2 |= 3386 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3387 } 3388 3389 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3390 __be32 access_flags = 0; 3391 3392 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 3393 if (err) 3394 goto out; 3395 3396 context->params2 |= access_flags; 3397 } 3398 3399 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3400 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3401 3402 if (attr_mask & IB_QP_RQ_PSN) 3403 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3404 3405 if (attr_mask & IB_QP_QKEY) 3406 context->qkey = cpu_to_be32(attr->qkey); 3407 3408 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3409 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3410 3411 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3412 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3413 qp->port) - 1; 3414 3415 /* Underlay port should be used - index 0 function per port */ 3416 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3417 port_num = 0; 3418 3419 mibport = &dev->port[port_num]; 3420 context->qp_counter_set_usr_page |= 3421 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3422 } 3423 3424 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3425 context->sq_crq_size |= cpu_to_be16(1 << 4); 3426 3427 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3428 context->deth_sqpn = cpu_to_be32(1); 3429 3430 mlx5_cur = to_mlx5_state(cur_state); 3431 mlx5_new = to_mlx5_state(new_state); 3432 3433 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3434 !optab[mlx5_cur][mlx5_new]) { 3435 err = -EINVAL; 3436 goto out; 3437 } 3438 3439 op = optab[mlx5_cur][mlx5_new]; 3440 optpar = ib_mask_to_mlx5_opt(attr_mask); 3441 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3442 3443 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3444 qp->flags & MLX5_IB_QP_UNDERLAY) { 3445 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3446 3447 raw_qp_param.operation = op; 3448 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3449 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3450 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3451 } 3452 3453 if (attr_mask & IB_QP_RATE_LIMIT) { 3454 raw_qp_param.rl.rate = attr->rate_limit; 3455 3456 if (ucmd->burst_info.max_burst_sz) { 3457 if (attr->rate_limit && 3458 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3459 raw_qp_param.rl.max_burst_sz = 3460 ucmd->burst_info.max_burst_sz; 3461 } else { 3462 err = -EINVAL; 3463 goto out; 3464 } 3465 } 3466 3467 if (ucmd->burst_info.typical_pkt_sz) { 3468 if (attr->rate_limit && 3469 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3470 raw_qp_param.rl.typical_pkt_sz = 3471 ucmd->burst_info.typical_pkt_sz; 3472 } else { 3473 err = -EINVAL; 3474 goto out; 3475 } 3476 } 3477 3478 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3479 } 3480 3481 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3482 } else { 3483 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3484 &base->mqp); 3485 } 3486 3487 if (err) 3488 goto out; 3489 3490 qp->state = new_state; 3491 3492 if (attr_mask & IB_QP_ACCESS_FLAGS) 3493 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3494 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3495 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3496 if (attr_mask & IB_QP_PORT) 3497 qp->port = attr->port_num; 3498 if (attr_mask & IB_QP_ALT_PATH) 3499 qp->trans_qp.alt_port = attr->alt_port_num; 3500 3501 /* 3502 * If we moved a kernel QP to RESET, clean up all old CQ 3503 * entries and reinitialize the QP. 3504 */ 3505 if (new_state == IB_QPS_RESET && 3506 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3507 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3508 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3509 if (send_cq != recv_cq) 3510 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3511 3512 qp->rq.head = 0; 3513 qp->rq.tail = 0; 3514 qp->sq.head = 0; 3515 qp->sq.tail = 0; 3516 qp->sq.cur_post = 0; 3517 if (qp->sq.wqe_cnt) 3518 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 3519 qp->db.db[MLX5_RCV_DBR] = 0; 3520 qp->db.db[MLX5_SND_DBR] = 0; 3521 } 3522 3523 out: 3524 kfree(context); 3525 return err; 3526 } 3527 3528 static inline bool is_valid_mask(int mask, int req, int opt) 3529 { 3530 if ((mask & req) != req) 3531 return false; 3532 3533 if (mask & ~(req | opt)) 3534 return false; 3535 3536 return true; 3537 } 3538 3539 /* check valid transition for driver QP types 3540 * for now the only QP type that this function supports is DCI 3541 */ 3542 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3543 enum ib_qp_attr_mask attr_mask) 3544 { 3545 int req = IB_QP_STATE; 3546 int opt = 0; 3547 3548 if (new_state == IB_QPS_RESET) { 3549 return is_valid_mask(attr_mask, req, opt); 3550 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3551 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3552 return is_valid_mask(attr_mask, req, opt); 3553 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3554 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3555 return is_valid_mask(attr_mask, req, opt); 3556 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3557 req |= IB_QP_PATH_MTU; 3558 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 3559 return is_valid_mask(attr_mask, req, opt); 3560 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3561 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3562 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3563 opt = IB_QP_MIN_RNR_TIMER; 3564 return is_valid_mask(attr_mask, req, opt); 3565 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3566 opt = IB_QP_MIN_RNR_TIMER; 3567 return is_valid_mask(attr_mask, req, opt); 3568 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3569 return is_valid_mask(attr_mask, req, opt); 3570 } 3571 return false; 3572 } 3573 3574 /* mlx5_ib_modify_dct: modify a DCT QP 3575 * valid transitions are: 3576 * RESET to INIT: must set access_flags, pkey_index and port 3577 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3578 * mtu, gid_index and hop_limit 3579 * Other transitions and attributes are illegal 3580 */ 3581 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3582 int attr_mask, struct ib_udata *udata) 3583 { 3584 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3585 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3586 enum ib_qp_state cur_state, new_state; 3587 int err = 0; 3588 int required = IB_QP_STATE; 3589 void *dctc; 3590 3591 if (!(attr_mask & IB_QP_STATE)) 3592 return -EINVAL; 3593 3594 cur_state = qp->state; 3595 new_state = attr->qp_state; 3596 3597 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3598 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3599 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3600 if (!is_valid_mask(attr_mask, required, 0)) 3601 return -EINVAL; 3602 3603 if (attr->port_num == 0 || 3604 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3605 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3606 attr->port_num, dev->num_ports); 3607 return -EINVAL; 3608 } 3609 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3610 MLX5_SET(dctc, dctc, rre, 1); 3611 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3612 MLX5_SET(dctc, dctc, rwe, 1); 3613 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3614 int atomic_mode; 3615 3616 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 3617 if (atomic_mode < 0) 3618 return -EOPNOTSUPP; 3619 3620 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 3621 MLX5_SET(dctc, dctc, rae, 1); 3622 } 3623 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3624 MLX5_SET(dctc, dctc, port, attr->port_num); 3625 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3626 3627 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3628 struct mlx5_ib_modify_qp_resp resp = {}; 3629 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3630 sizeof(resp.dctn); 3631 3632 if (udata->outlen < min_resp_len) 3633 return -EINVAL; 3634 resp.response_length = min_resp_len; 3635 3636 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3637 if (!is_valid_mask(attr_mask, required, 0)) 3638 return -EINVAL; 3639 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3640 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3641 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3642 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3643 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3644 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3645 3646 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3647 MLX5_ST_SZ_BYTES(create_dct_in)); 3648 if (err) 3649 return err; 3650 resp.dctn = qp->dct.mdct.mqp.qpn; 3651 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3652 if (err) { 3653 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3654 return err; 3655 } 3656 } else { 3657 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3658 return -EINVAL; 3659 } 3660 if (err) 3661 qp->state = IB_QPS_ERR; 3662 else 3663 qp->state = new_state; 3664 return err; 3665 } 3666 3667 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3668 int attr_mask, struct ib_udata *udata) 3669 { 3670 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3671 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3672 struct mlx5_ib_modify_qp ucmd = {}; 3673 enum ib_qp_type qp_type; 3674 enum ib_qp_state cur_state, new_state; 3675 size_t required_cmd_sz; 3676 int err = -EINVAL; 3677 int port; 3678 3679 if (ibqp->rwq_ind_tbl) 3680 return -ENOSYS; 3681 3682 if (udata && udata->inlen) { 3683 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3684 sizeof(ucmd.reserved); 3685 if (udata->inlen < required_cmd_sz) 3686 return -EINVAL; 3687 3688 if (udata->inlen > sizeof(ucmd) && 3689 !ib_is_udata_cleared(udata, sizeof(ucmd), 3690 udata->inlen - sizeof(ucmd))) 3691 return -EOPNOTSUPP; 3692 3693 if (ib_copy_from_udata(&ucmd, udata, 3694 min(udata->inlen, sizeof(ucmd)))) 3695 return -EFAULT; 3696 3697 if (ucmd.comp_mask || 3698 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3699 memchr_inv(&ucmd.burst_info.reserved, 0, 3700 sizeof(ucmd.burst_info.reserved))) 3701 return -EOPNOTSUPP; 3702 } 3703 3704 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3705 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3706 3707 if (ibqp->qp_type == IB_QPT_DRIVER) 3708 qp_type = qp->qp_sub_type; 3709 else 3710 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3711 IB_QPT_GSI : ibqp->qp_type; 3712 3713 if (qp_type == MLX5_IB_QPT_DCT) 3714 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3715 3716 mutex_lock(&qp->mutex); 3717 3718 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3719 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3720 3721 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3722 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3723 } 3724 3725 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3726 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3727 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3728 attr_mask); 3729 goto out; 3730 } 3731 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3732 qp_type != MLX5_IB_QPT_DCI && 3733 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 3734 attr_mask)) { 3735 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3736 cur_state, new_state, ibqp->qp_type, attr_mask); 3737 goto out; 3738 } else if (qp_type == MLX5_IB_QPT_DCI && 3739 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3740 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3741 cur_state, new_state, qp_type, attr_mask); 3742 goto out; 3743 } 3744 3745 if ((attr_mask & IB_QP_PORT) && 3746 (attr->port_num == 0 || 3747 attr->port_num > dev->num_ports)) { 3748 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3749 attr->port_num, dev->num_ports); 3750 goto out; 3751 } 3752 3753 if (attr_mask & IB_QP_PKEY_INDEX) { 3754 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3755 if (attr->pkey_index >= 3756 dev->mdev->port_caps[port - 1].pkey_table_len) { 3757 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3758 attr->pkey_index); 3759 goto out; 3760 } 3761 } 3762 3763 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3764 attr->max_rd_atomic > 3765 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3766 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3767 attr->max_rd_atomic); 3768 goto out; 3769 } 3770 3771 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3772 attr->max_dest_rd_atomic > 3773 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3774 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3775 attr->max_dest_rd_atomic); 3776 goto out; 3777 } 3778 3779 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3780 err = 0; 3781 goto out; 3782 } 3783 3784 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3785 new_state, &ucmd); 3786 3787 out: 3788 mutex_unlock(&qp->mutex); 3789 return err; 3790 } 3791 3792 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3793 u32 wqe_sz, void **cur_edge) 3794 { 3795 u32 idx; 3796 3797 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); 3798 *cur_edge = get_sq_edge(sq, idx); 3799 3800 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); 3801 } 3802 3803 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the 3804 * next nearby edge and get new address translation for current WQE position. 3805 * @sq - SQ buffer. 3806 * @seg: Current WQE position (16B aligned). 3807 * @wqe_sz: Total current WQE size [16B]. 3808 * @cur_edge: Updated current edge. 3809 */ 3810 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3811 u32 wqe_sz, void **cur_edge) 3812 { 3813 if (likely(*seg != *cur_edge)) 3814 return; 3815 3816 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); 3817 } 3818 3819 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's 3820 * pointers. At the end @seg is aligned to 16B regardless the copied size. 3821 * @sq - SQ buffer. 3822 * @cur_edge: Updated current edge. 3823 * @seg: Current WQE position (16B aligned). 3824 * @wqe_sz: Total current WQE size [16B]. 3825 * @src: Pointer to copy from. 3826 * @n: Number of bytes to copy. 3827 */ 3828 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, 3829 void **seg, u32 *wqe_sz, const void *src, 3830 size_t n) 3831 { 3832 while (likely(n)) { 3833 size_t leftlen = *cur_edge - *seg; 3834 size_t copysz = min_t(size_t, leftlen, n); 3835 size_t stride; 3836 3837 memcpy(*seg, src, copysz); 3838 3839 n -= copysz; 3840 src += copysz; 3841 stride = !n ? ALIGN(copysz, 16) : copysz; 3842 *seg += stride; 3843 *wqe_sz += stride >> 4; 3844 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); 3845 } 3846 } 3847 3848 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3849 { 3850 struct mlx5_ib_cq *cq; 3851 unsigned cur; 3852 3853 cur = wq->head - wq->tail; 3854 if (likely(cur + nreq < wq->max_post)) 3855 return 0; 3856 3857 cq = to_mcq(ib_cq); 3858 spin_lock(&cq->lock); 3859 cur = wq->head - wq->tail; 3860 spin_unlock(&cq->lock); 3861 3862 return cur + nreq >= wq->max_post; 3863 } 3864 3865 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3866 u64 remote_addr, u32 rkey) 3867 { 3868 rseg->raddr = cpu_to_be64(remote_addr); 3869 rseg->rkey = cpu_to_be32(rkey); 3870 rseg->reserved = 0; 3871 } 3872 3873 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 3874 void **seg, int *size, void **cur_edge) 3875 { 3876 struct mlx5_wqe_eth_seg *eseg = *seg; 3877 3878 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3879 3880 if (wr->send_flags & IB_SEND_IP_CSUM) 3881 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3882 MLX5_ETH_WQE_L4_CSUM; 3883 3884 if (wr->opcode == IB_WR_LSO) { 3885 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3886 size_t left, copysz; 3887 void *pdata = ud_wr->header; 3888 size_t stride; 3889 3890 left = ud_wr->hlen; 3891 eseg->mss = cpu_to_be16(ud_wr->mss); 3892 eseg->inline_hdr.sz = cpu_to_be16(left); 3893 3894 /* memcpy_send_wqe should get a 16B align address. Hence, we 3895 * first copy up to the current edge and then, if needed, 3896 * fall-through to memcpy_send_wqe. 3897 */ 3898 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, 3899 left); 3900 memcpy(eseg->inline_hdr.start, pdata, copysz); 3901 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - 3902 sizeof(eseg->inline_hdr.start) + copysz, 16); 3903 *size += stride / 16; 3904 *seg += stride; 3905 3906 if (copysz < left) { 3907 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 3908 left -= copysz; 3909 pdata += copysz; 3910 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, 3911 left); 3912 } 3913 3914 return; 3915 } 3916 3917 *seg += sizeof(struct mlx5_wqe_eth_seg); 3918 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3919 } 3920 3921 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3922 const struct ib_send_wr *wr) 3923 { 3924 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3925 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3926 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3927 } 3928 3929 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3930 { 3931 dseg->byte_count = cpu_to_be32(sg->length); 3932 dseg->lkey = cpu_to_be32(sg->lkey); 3933 dseg->addr = cpu_to_be64(sg->addr); 3934 } 3935 3936 static u64 get_xlt_octo(u64 bytes) 3937 { 3938 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3939 MLX5_IB_UMR_OCTOWORD; 3940 } 3941 3942 static __be64 frwr_mkey_mask(void) 3943 { 3944 u64 result; 3945 3946 result = MLX5_MKEY_MASK_LEN | 3947 MLX5_MKEY_MASK_PAGE_SIZE | 3948 MLX5_MKEY_MASK_START_ADDR | 3949 MLX5_MKEY_MASK_EN_RINVAL | 3950 MLX5_MKEY_MASK_KEY | 3951 MLX5_MKEY_MASK_LR | 3952 MLX5_MKEY_MASK_LW | 3953 MLX5_MKEY_MASK_RR | 3954 MLX5_MKEY_MASK_RW | 3955 MLX5_MKEY_MASK_A | 3956 MLX5_MKEY_MASK_SMALL_FENCE | 3957 MLX5_MKEY_MASK_FREE; 3958 3959 return cpu_to_be64(result); 3960 } 3961 3962 static __be64 sig_mkey_mask(void) 3963 { 3964 u64 result; 3965 3966 result = MLX5_MKEY_MASK_LEN | 3967 MLX5_MKEY_MASK_PAGE_SIZE | 3968 MLX5_MKEY_MASK_START_ADDR | 3969 MLX5_MKEY_MASK_EN_SIGERR | 3970 MLX5_MKEY_MASK_EN_RINVAL | 3971 MLX5_MKEY_MASK_KEY | 3972 MLX5_MKEY_MASK_LR | 3973 MLX5_MKEY_MASK_LW | 3974 MLX5_MKEY_MASK_RR | 3975 MLX5_MKEY_MASK_RW | 3976 MLX5_MKEY_MASK_SMALL_FENCE | 3977 MLX5_MKEY_MASK_FREE | 3978 MLX5_MKEY_MASK_BSF_EN; 3979 3980 return cpu_to_be64(result); 3981 } 3982 3983 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3984 struct mlx5_ib_mr *mr, bool umr_inline) 3985 { 3986 int size = mr->ndescs * mr->desc_size; 3987 3988 memset(umr, 0, sizeof(*umr)); 3989 3990 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3991 if (umr_inline) 3992 umr->flags |= MLX5_UMR_INLINE; 3993 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3994 umr->mkey_mask = frwr_mkey_mask(); 3995 } 3996 3997 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3998 { 3999 memset(umr, 0, sizeof(*umr)); 4000 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 4001 umr->flags = MLX5_UMR_INLINE; 4002 } 4003 4004 static __be64 get_umr_enable_mr_mask(void) 4005 { 4006 u64 result; 4007 4008 result = MLX5_MKEY_MASK_KEY | 4009 MLX5_MKEY_MASK_FREE; 4010 4011 return cpu_to_be64(result); 4012 } 4013 4014 static __be64 get_umr_disable_mr_mask(void) 4015 { 4016 u64 result; 4017 4018 result = MLX5_MKEY_MASK_FREE; 4019 4020 return cpu_to_be64(result); 4021 } 4022 4023 static __be64 get_umr_update_translation_mask(void) 4024 { 4025 u64 result; 4026 4027 result = MLX5_MKEY_MASK_LEN | 4028 MLX5_MKEY_MASK_PAGE_SIZE | 4029 MLX5_MKEY_MASK_START_ADDR; 4030 4031 return cpu_to_be64(result); 4032 } 4033 4034 static __be64 get_umr_update_access_mask(int atomic) 4035 { 4036 u64 result; 4037 4038 result = MLX5_MKEY_MASK_LR | 4039 MLX5_MKEY_MASK_LW | 4040 MLX5_MKEY_MASK_RR | 4041 MLX5_MKEY_MASK_RW; 4042 4043 if (atomic) 4044 result |= MLX5_MKEY_MASK_A; 4045 4046 return cpu_to_be64(result); 4047 } 4048 4049 static __be64 get_umr_update_pd_mask(void) 4050 { 4051 u64 result; 4052 4053 result = MLX5_MKEY_MASK_PD; 4054 4055 return cpu_to_be64(result); 4056 } 4057 4058 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 4059 { 4060 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 4061 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 4062 (mask & MLX5_MKEY_MASK_A && 4063 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 4064 return -EPERM; 4065 return 0; 4066 } 4067 4068 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 4069 struct mlx5_wqe_umr_ctrl_seg *umr, 4070 const struct ib_send_wr *wr, int atomic) 4071 { 4072 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4073 4074 memset(umr, 0, sizeof(*umr)); 4075 4076 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 4077 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 4078 else 4079 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 4080 4081 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 4082 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 4083 u64 offset = get_xlt_octo(umrwr->offset); 4084 4085 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 4086 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 4087 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 4088 } 4089 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 4090 umr->mkey_mask |= get_umr_update_translation_mask(); 4091 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 4092 umr->mkey_mask |= get_umr_update_access_mask(atomic); 4093 umr->mkey_mask |= get_umr_update_pd_mask(); 4094 } 4095 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 4096 umr->mkey_mask |= get_umr_enable_mr_mask(); 4097 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4098 umr->mkey_mask |= get_umr_disable_mr_mask(); 4099 4100 if (!wr->num_sge) 4101 umr->flags |= MLX5_UMR_INLINE; 4102 4103 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 4104 } 4105 4106 static u8 get_umr_flags(int acc) 4107 { 4108 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 4109 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 4110 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 4111 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 4112 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 4113 } 4114 4115 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 4116 struct mlx5_ib_mr *mr, 4117 u32 key, int access) 4118 { 4119 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 4120 4121 memset(seg, 0, sizeof(*seg)); 4122 4123 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 4124 seg->log2_page_size = ilog2(mr->ibmr.page_size); 4125 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 4126 /* KLMs take twice the size of MTTs */ 4127 ndescs *= 2; 4128 4129 seg->flags = get_umr_flags(access) | mr->access_mode; 4130 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 4131 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 4132 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 4133 seg->len = cpu_to_be64(mr->ibmr.length); 4134 seg->xlt_oct_size = cpu_to_be32(ndescs); 4135 } 4136 4137 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 4138 { 4139 memset(seg, 0, sizeof(*seg)); 4140 seg->status = MLX5_MKEY_STATUS_FREE; 4141 } 4142 4143 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, 4144 const struct ib_send_wr *wr) 4145 { 4146 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4147 4148 memset(seg, 0, sizeof(*seg)); 4149 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4150 seg->status = MLX5_MKEY_STATUS_FREE; 4151 4152 seg->flags = convert_access(umrwr->access_flags); 4153 if (umrwr->pd) 4154 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 4155 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 4156 !umrwr->length) 4157 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 4158 4159 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 4160 seg->len = cpu_to_be64(umrwr->length); 4161 seg->log2_page_size = umrwr->page_shift; 4162 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 4163 mlx5_mkey_variant(umrwr->mkey)); 4164 } 4165 4166 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 4167 struct mlx5_ib_mr *mr, 4168 struct mlx5_ib_pd *pd) 4169 { 4170 int bcount = mr->desc_size * mr->ndescs; 4171 4172 dseg->addr = cpu_to_be64(mr->desc_map); 4173 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 4174 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 4175 } 4176 4177 static __be32 send_ieth(const struct ib_send_wr *wr) 4178 { 4179 switch (wr->opcode) { 4180 case IB_WR_SEND_WITH_IMM: 4181 case IB_WR_RDMA_WRITE_WITH_IMM: 4182 return wr->ex.imm_data; 4183 4184 case IB_WR_SEND_WITH_INV: 4185 return cpu_to_be32(wr->ex.invalidate_rkey); 4186 4187 default: 4188 return 0; 4189 } 4190 } 4191 4192 static u8 calc_sig(void *wqe, int size) 4193 { 4194 u8 *p = wqe; 4195 u8 res = 0; 4196 int i; 4197 4198 for (i = 0; i < size; i++) 4199 res ^= p[i]; 4200 4201 return ~res; 4202 } 4203 4204 static u8 wq_sig(void *wqe) 4205 { 4206 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 4207 } 4208 4209 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 4210 void **wqe, int *wqe_sz, void **cur_edge) 4211 { 4212 struct mlx5_wqe_inline_seg *seg; 4213 size_t offset; 4214 int inl = 0; 4215 int i; 4216 4217 seg = *wqe; 4218 *wqe += sizeof(*seg); 4219 offset = sizeof(*seg); 4220 4221 for (i = 0; i < wr->num_sge; i++) { 4222 size_t len = wr->sg_list[i].length; 4223 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); 4224 4225 inl += len; 4226 4227 if (unlikely(inl > qp->max_inline_data)) 4228 return -ENOMEM; 4229 4230 while (likely(len)) { 4231 size_t leftlen; 4232 size_t copysz; 4233 4234 handle_post_send_edge(&qp->sq, wqe, 4235 *wqe_sz + (offset >> 4), 4236 cur_edge); 4237 4238 leftlen = *cur_edge - *wqe; 4239 copysz = min_t(size_t, leftlen, len); 4240 4241 memcpy(*wqe, addr, copysz); 4242 len -= copysz; 4243 addr += copysz; 4244 *wqe += copysz; 4245 offset += copysz; 4246 } 4247 } 4248 4249 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 4250 4251 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 4252 4253 return 0; 4254 } 4255 4256 static u16 prot_field_size(enum ib_signature_type type) 4257 { 4258 switch (type) { 4259 case IB_SIG_TYPE_T10_DIF: 4260 return MLX5_DIF_SIZE; 4261 default: 4262 return 0; 4263 } 4264 } 4265 4266 static u8 bs_selector(int block_size) 4267 { 4268 switch (block_size) { 4269 case 512: return 0x1; 4270 case 520: return 0x2; 4271 case 4096: return 0x3; 4272 case 4160: return 0x4; 4273 case 1073741824: return 0x5; 4274 default: return 0; 4275 } 4276 } 4277 4278 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 4279 struct mlx5_bsf_inl *inl) 4280 { 4281 /* Valid inline section and allow BSF refresh */ 4282 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 4283 MLX5_BSF_REFRESH_DIF); 4284 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 4285 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 4286 /* repeating block */ 4287 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 4288 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 4289 MLX5_DIF_CRC : MLX5_DIF_IPCS; 4290 4291 if (domain->sig.dif.ref_remap) 4292 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 4293 4294 if (domain->sig.dif.app_escape) { 4295 if (domain->sig.dif.ref_escape) 4296 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 4297 else 4298 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 4299 } 4300 4301 inl->dif_app_bitmask_check = 4302 cpu_to_be16(domain->sig.dif.apptag_check_mask); 4303 } 4304 4305 static int mlx5_set_bsf(struct ib_mr *sig_mr, 4306 struct ib_sig_attrs *sig_attrs, 4307 struct mlx5_bsf *bsf, u32 data_size) 4308 { 4309 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 4310 struct mlx5_bsf_basic *basic = &bsf->basic; 4311 struct ib_sig_domain *mem = &sig_attrs->mem; 4312 struct ib_sig_domain *wire = &sig_attrs->wire; 4313 4314 memset(bsf, 0, sizeof(*bsf)); 4315 4316 /* Basic + Extended + Inline */ 4317 basic->bsf_size_sbs = 1 << 7; 4318 /* Input domain check byte mask */ 4319 basic->check_byte_mask = sig_attrs->check_mask; 4320 basic->raw_data_size = cpu_to_be32(data_size); 4321 4322 /* Memory domain */ 4323 switch (sig_attrs->mem.sig_type) { 4324 case IB_SIG_TYPE_NONE: 4325 break; 4326 case IB_SIG_TYPE_T10_DIF: 4327 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4328 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4329 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4330 break; 4331 default: 4332 return -EINVAL; 4333 } 4334 4335 /* Wire domain */ 4336 switch (sig_attrs->wire.sig_type) { 4337 case IB_SIG_TYPE_NONE: 4338 break; 4339 case IB_SIG_TYPE_T10_DIF: 4340 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4341 mem->sig_type == wire->sig_type) { 4342 /* Same block structure */ 4343 basic->bsf_size_sbs |= 1 << 4; 4344 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4345 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4346 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4347 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4348 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4349 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4350 } else 4351 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4352 4353 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4354 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4355 break; 4356 default: 4357 return -EINVAL; 4358 } 4359 4360 return 0; 4361 } 4362 4363 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 4364 struct mlx5_ib_qp *qp, void **seg, 4365 int *size, void **cur_edge) 4366 { 4367 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4368 struct ib_mr *sig_mr = wr->sig_mr; 4369 struct mlx5_bsf *bsf; 4370 u32 data_len = wr->wr.sg_list->length; 4371 u32 data_key = wr->wr.sg_list->lkey; 4372 u64 data_va = wr->wr.sg_list->addr; 4373 int ret; 4374 int wqe_size; 4375 4376 if (!wr->prot || 4377 (data_key == wr->prot->lkey && 4378 data_va == wr->prot->addr && 4379 data_len == wr->prot->length)) { 4380 /** 4381 * Source domain doesn't contain signature information 4382 * or data and protection are interleaved in memory. 4383 * So need construct: 4384 * ------------------ 4385 * | data_klm | 4386 * ------------------ 4387 * | BSF | 4388 * ------------------ 4389 **/ 4390 struct mlx5_klm *data_klm = *seg; 4391 4392 data_klm->bcount = cpu_to_be32(data_len); 4393 data_klm->key = cpu_to_be32(data_key); 4394 data_klm->va = cpu_to_be64(data_va); 4395 wqe_size = ALIGN(sizeof(*data_klm), 64); 4396 } else { 4397 /** 4398 * Source domain contains signature information 4399 * So need construct a strided block format: 4400 * --------------------------- 4401 * | stride_block_ctrl | 4402 * --------------------------- 4403 * | data_klm | 4404 * --------------------------- 4405 * | prot_klm | 4406 * --------------------------- 4407 * | BSF | 4408 * --------------------------- 4409 **/ 4410 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4411 struct mlx5_stride_block_entry *data_sentry; 4412 struct mlx5_stride_block_entry *prot_sentry; 4413 u32 prot_key = wr->prot->lkey; 4414 u64 prot_va = wr->prot->addr; 4415 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4416 int prot_size; 4417 4418 sblock_ctrl = *seg; 4419 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4420 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4421 4422 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4423 if (!prot_size) { 4424 pr_err("Bad block size given: %u\n", block_size); 4425 return -EINVAL; 4426 } 4427 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4428 prot_size); 4429 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4430 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4431 sblock_ctrl->num_entries = cpu_to_be16(2); 4432 4433 data_sentry->bcount = cpu_to_be16(block_size); 4434 data_sentry->key = cpu_to_be32(data_key); 4435 data_sentry->va = cpu_to_be64(data_va); 4436 data_sentry->stride = cpu_to_be16(block_size); 4437 4438 prot_sentry->bcount = cpu_to_be16(prot_size); 4439 prot_sentry->key = cpu_to_be32(prot_key); 4440 prot_sentry->va = cpu_to_be64(prot_va); 4441 prot_sentry->stride = cpu_to_be16(prot_size); 4442 4443 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4444 sizeof(*prot_sentry), 64); 4445 } 4446 4447 *seg += wqe_size; 4448 *size += wqe_size / 16; 4449 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4450 4451 bsf = *seg; 4452 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4453 if (ret) 4454 return -EINVAL; 4455 4456 *seg += sizeof(*bsf); 4457 *size += sizeof(*bsf) / 16; 4458 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4459 4460 return 0; 4461 } 4462 4463 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4464 const struct ib_sig_handover_wr *wr, u32 size, 4465 u32 length, u32 pdn) 4466 { 4467 struct ib_mr *sig_mr = wr->sig_mr; 4468 u32 sig_key = sig_mr->rkey; 4469 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4470 4471 memset(seg, 0, sizeof(*seg)); 4472 4473 seg->flags = get_umr_flags(wr->access_flags) | 4474 MLX5_MKC_ACCESS_MODE_KLMS; 4475 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4476 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4477 MLX5_MKEY_BSF_EN | pdn); 4478 seg->len = cpu_to_be64(length); 4479 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4480 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4481 } 4482 4483 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4484 u32 size) 4485 { 4486 memset(umr, 0, sizeof(*umr)); 4487 4488 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4489 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4490 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4491 umr->mkey_mask = sig_mkey_mask(); 4492 } 4493 4494 4495 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, 4496 struct mlx5_ib_qp *qp, void **seg, int *size, 4497 void **cur_edge) 4498 { 4499 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4500 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4501 u32 pdn = get_pd(qp)->pdn; 4502 u32 xlt_size; 4503 int region_len, ret; 4504 4505 if (unlikely(wr->wr.num_sge != 1) || 4506 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4507 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4508 unlikely(!sig_mr->sig->sig_status_checked)) 4509 return -EINVAL; 4510 4511 /* length of the protected region, data + protection */ 4512 region_len = wr->wr.sg_list->length; 4513 if (wr->prot && 4514 (wr->prot->lkey != wr->wr.sg_list->lkey || 4515 wr->prot->addr != wr->wr.sg_list->addr || 4516 wr->prot->length != wr->wr.sg_list->length)) 4517 region_len += wr->prot->length; 4518 4519 /** 4520 * KLM octoword size - if protection was provided 4521 * then we use strided block format (3 octowords), 4522 * else we use single KLM (1 octoword) 4523 **/ 4524 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4525 4526 set_sig_umr_segment(*seg, xlt_size); 4527 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4528 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4529 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4530 4531 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4532 *seg += sizeof(struct mlx5_mkey_seg); 4533 *size += sizeof(struct mlx5_mkey_seg) / 16; 4534 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4535 4536 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge); 4537 if (ret) 4538 return ret; 4539 4540 sig_mr->sig->sig_status_checked = false; 4541 return 0; 4542 } 4543 4544 static int set_psv_wr(struct ib_sig_domain *domain, 4545 u32 psv_idx, void **seg, int *size) 4546 { 4547 struct mlx5_seg_set_psv *psv_seg = *seg; 4548 4549 memset(psv_seg, 0, sizeof(*psv_seg)); 4550 psv_seg->psv_num = cpu_to_be32(psv_idx); 4551 switch (domain->sig_type) { 4552 case IB_SIG_TYPE_NONE: 4553 break; 4554 case IB_SIG_TYPE_T10_DIF: 4555 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4556 domain->sig.dif.app_tag); 4557 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4558 break; 4559 default: 4560 pr_err("Bad signature type (%d) is given.\n", 4561 domain->sig_type); 4562 return -EINVAL; 4563 } 4564 4565 *seg += sizeof(*psv_seg); 4566 *size += sizeof(*psv_seg) / 16; 4567 4568 return 0; 4569 } 4570 4571 static int set_reg_wr(struct mlx5_ib_qp *qp, 4572 const struct ib_reg_wr *wr, 4573 void **seg, int *size, void **cur_edge) 4574 { 4575 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4576 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4577 size_t mr_list_size = mr->ndescs * mr->desc_size; 4578 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4579 4580 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4581 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4582 "Invalid IB_SEND_INLINE send flag\n"); 4583 return -EINVAL; 4584 } 4585 4586 set_reg_umr_seg(*seg, mr, umr_inline); 4587 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4588 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4589 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4590 4591 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4592 *seg += sizeof(struct mlx5_mkey_seg); 4593 *size += sizeof(struct mlx5_mkey_seg) / 16; 4594 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4595 4596 if (umr_inline) { 4597 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, 4598 mr_list_size); 4599 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); 4600 } else { 4601 set_reg_data_seg(*seg, mr, pd); 4602 *seg += sizeof(struct mlx5_wqe_data_seg); 4603 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4604 } 4605 return 0; 4606 } 4607 4608 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, 4609 void **cur_edge) 4610 { 4611 set_linv_umr_seg(*seg); 4612 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4613 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4614 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4615 set_linv_mkey_seg(*seg); 4616 *seg += sizeof(struct mlx5_mkey_seg); 4617 *size += sizeof(struct mlx5_mkey_seg) / 16; 4618 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4619 } 4620 4621 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) 4622 { 4623 __be32 *p = NULL; 4624 u32 tidx = idx; 4625 int i, j; 4626 4627 pr_debug("dump WQE index %u:\n", idx); 4628 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4629 if ((i & 0xf) == 0) { 4630 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4631 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx); 4632 pr_debug("WQBB at %p:\n", (void *)p); 4633 j = 0; 4634 } 4635 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4636 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4637 be32_to_cpu(p[j + 3])); 4638 } 4639 } 4640 4641 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4642 struct mlx5_wqe_ctrl_seg **ctrl, 4643 const struct ib_send_wr *wr, unsigned int *idx, 4644 int *size, void **cur_edge, int nreq, 4645 bool send_signaled, bool solicited) 4646 { 4647 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4648 return -ENOMEM; 4649 4650 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4651 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); 4652 *ctrl = *seg; 4653 *(uint32_t *)(*seg + 8) = 0; 4654 (*ctrl)->imm = send_ieth(wr); 4655 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4656 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4657 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 4658 4659 *seg += sizeof(**ctrl); 4660 *size = sizeof(**ctrl) / 16; 4661 *cur_edge = qp->sq.cur_edge; 4662 4663 return 0; 4664 } 4665 4666 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4667 struct mlx5_wqe_ctrl_seg **ctrl, 4668 const struct ib_send_wr *wr, unsigned *idx, 4669 int *size, void **cur_edge, int nreq) 4670 { 4671 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, 4672 wr->send_flags & IB_SEND_SIGNALED, 4673 wr->send_flags & IB_SEND_SOLICITED); 4674 } 4675 4676 static void finish_wqe(struct mlx5_ib_qp *qp, 4677 struct mlx5_wqe_ctrl_seg *ctrl, 4678 void *seg, u8 size, void *cur_edge, 4679 unsigned int idx, u64 wr_id, int nreq, u8 fence, 4680 u32 mlx5_opcode) 4681 { 4682 u8 opmod = 0; 4683 4684 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4685 mlx5_opcode | ((u32)opmod << 24)); 4686 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4687 ctrl->fm_ce_se |= fence; 4688 if (unlikely(qp->wq_sig)) 4689 ctrl->signature = wq_sig(ctrl); 4690 4691 qp->sq.wrid[idx] = wr_id; 4692 qp->sq.w_list[idx].opcode = mlx5_opcode; 4693 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4694 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4695 qp->sq.w_list[idx].next = qp->sq.cur_post; 4696 4697 /* We save the edge which was possibly updated during the WQE 4698 * construction, into SQ's cache. 4699 */ 4700 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); 4701 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? 4702 get_sq_edge(&qp->sq, qp->sq.cur_post & 4703 (qp->sq.wqe_cnt - 1)) : 4704 cur_edge; 4705 } 4706 4707 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 4708 const struct ib_send_wr **bad_wr, bool drain) 4709 { 4710 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4711 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4712 struct mlx5_core_dev *mdev = dev->mdev; 4713 struct mlx5_ib_qp *qp; 4714 struct mlx5_ib_mr *mr; 4715 struct mlx5_wqe_xrc_seg *xrc; 4716 struct mlx5_bf *bf; 4717 void *cur_edge; 4718 int uninitialized_var(size); 4719 unsigned long flags; 4720 unsigned idx; 4721 int err = 0; 4722 int num_sge; 4723 void *seg; 4724 int nreq; 4725 int i; 4726 u8 next_fence = 0; 4727 u8 fence; 4728 4729 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 4730 !drain)) { 4731 *bad_wr = wr; 4732 return -EIO; 4733 } 4734 4735 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4736 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4737 4738 qp = to_mqp(ibqp); 4739 bf = &qp->bf; 4740 4741 spin_lock_irqsave(&qp->sq.lock, flags); 4742 4743 for (nreq = 0; wr; nreq++, wr = wr->next) { 4744 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4745 mlx5_ib_warn(dev, "\n"); 4746 err = -EINVAL; 4747 *bad_wr = wr; 4748 goto out; 4749 } 4750 4751 num_sge = wr->num_sge; 4752 if (unlikely(num_sge > qp->sq.max_gs)) { 4753 mlx5_ib_warn(dev, "\n"); 4754 err = -EINVAL; 4755 *bad_wr = wr; 4756 goto out; 4757 } 4758 4759 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, 4760 nreq); 4761 if (err) { 4762 mlx5_ib_warn(dev, "\n"); 4763 err = -ENOMEM; 4764 *bad_wr = wr; 4765 goto out; 4766 } 4767 4768 if (wr->opcode == IB_WR_REG_MR) { 4769 fence = dev->umr_fence; 4770 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4771 } else { 4772 if (wr->send_flags & IB_SEND_FENCE) { 4773 if (qp->next_fence) 4774 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4775 else 4776 fence = MLX5_FENCE_MODE_FENCE; 4777 } else { 4778 fence = qp->next_fence; 4779 } 4780 } 4781 4782 switch (ibqp->qp_type) { 4783 case IB_QPT_XRC_INI: 4784 xrc = seg; 4785 seg += sizeof(*xrc); 4786 size += sizeof(*xrc) / 16; 4787 /* fall through */ 4788 case IB_QPT_RC: 4789 switch (wr->opcode) { 4790 case IB_WR_RDMA_READ: 4791 case IB_WR_RDMA_WRITE: 4792 case IB_WR_RDMA_WRITE_WITH_IMM: 4793 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4794 rdma_wr(wr)->rkey); 4795 seg += sizeof(struct mlx5_wqe_raddr_seg); 4796 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4797 break; 4798 4799 case IB_WR_ATOMIC_CMP_AND_SWP: 4800 case IB_WR_ATOMIC_FETCH_AND_ADD: 4801 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4802 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4803 err = -ENOSYS; 4804 *bad_wr = wr; 4805 goto out; 4806 4807 case IB_WR_LOCAL_INV: 4808 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4809 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4810 set_linv_wr(qp, &seg, &size, &cur_edge); 4811 num_sge = 0; 4812 break; 4813 4814 case IB_WR_REG_MR: 4815 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4816 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4817 err = set_reg_wr(qp, reg_wr(wr), &seg, &size, 4818 &cur_edge); 4819 if (err) { 4820 *bad_wr = wr; 4821 goto out; 4822 } 4823 num_sge = 0; 4824 break; 4825 4826 case IB_WR_REG_SIG_MR: 4827 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4828 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4829 4830 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4831 err = set_sig_umr_wr(wr, qp, &seg, &size, 4832 &cur_edge); 4833 if (err) { 4834 mlx5_ib_warn(dev, "\n"); 4835 *bad_wr = wr; 4836 goto out; 4837 } 4838 4839 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4840 wr->wr_id, nreq, fence, 4841 MLX5_OPCODE_UMR); 4842 /* 4843 * SET_PSV WQEs are not signaled and solicited 4844 * on error 4845 */ 4846 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4847 &size, &cur_edge, nreq, false, 4848 true); 4849 if (err) { 4850 mlx5_ib_warn(dev, "\n"); 4851 err = -ENOMEM; 4852 *bad_wr = wr; 4853 goto out; 4854 } 4855 4856 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4857 mr->sig->psv_memory.psv_idx, &seg, 4858 &size); 4859 if (err) { 4860 mlx5_ib_warn(dev, "\n"); 4861 *bad_wr = wr; 4862 goto out; 4863 } 4864 4865 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4866 wr->wr_id, nreq, fence, 4867 MLX5_OPCODE_SET_PSV); 4868 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4869 &size, &cur_edge, nreq, false, 4870 true); 4871 if (err) { 4872 mlx5_ib_warn(dev, "\n"); 4873 err = -ENOMEM; 4874 *bad_wr = wr; 4875 goto out; 4876 } 4877 4878 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4879 mr->sig->psv_wire.psv_idx, &seg, 4880 &size); 4881 if (err) { 4882 mlx5_ib_warn(dev, "\n"); 4883 *bad_wr = wr; 4884 goto out; 4885 } 4886 4887 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4888 wr->wr_id, nreq, fence, 4889 MLX5_OPCODE_SET_PSV); 4890 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4891 num_sge = 0; 4892 goto skip_psv; 4893 4894 default: 4895 break; 4896 } 4897 break; 4898 4899 case IB_QPT_UC: 4900 switch (wr->opcode) { 4901 case IB_WR_RDMA_WRITE: 4902 case IB_WR_RDMA_WRITE_WITH_IMM: 4903 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4904 rdma_wr(wr)->rkey); 4905 seg += sizeof(struct mlx5_wqe_raddr_seg); 4906 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4907 break; 4908 4909 default: 4910 break; 4911 } 4912 break; 4913 4914 case IB_QPT_SMI: 4915 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4916 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4917 err = -EPERM; 4918 *bad_wr = wr; 4919 goto out; 4920 } 4921 /* fall through */ 4922 case MLX5_IB_QPT_HW_GSI: 4923 set_datagram_seg(seg, wr); 4924 seg += sizeof(struct mlx5_wqe_datagram_seg); 4925 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4926 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4927 4928 break; 4929 case IB_QPT_UD: 4930 set_datagram_seg(seg, wr); 4931 seg += sizeof(struct mlx5_wqe_datagram_seg); 4932 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4933 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4934 4935 /* handle qp that supports ud offload */ 4936 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4937 struct mlx5_wqe_eth_pad *pad; 4938 4939 pad = seg; 4940 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4941 seg += sizeof(struct mlx5_wqe_eth_pad); 4942 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4943 set_eth_seg(wr, qp, &seg, &size, &cur_edge); 4944 handle_post_send_edge(&qp->sq, &seg, size, 4945 &cur_edge); 4946 } 4947 break; 4948 case MLX5_IB_QPT_REG_UMR: 4949 if (wr->opcode != MLX5_IB_WR_UMR) { 4950 err = -EINVAL; 4951 mlx5_ib_warn(dev, "bad opcode\n"); 4952 goto out; 4953 } 4954 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4955 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4956 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4957 if (unlikely(err)) 4958 goto out; 4959 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4960 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4961 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4962 set_reg_mkey_segment(seg, wr); 4963 seg += sizeof(struct mlx5_mkey_seg); 4964 size += sizeof(struct mlx5_mkey_seg) / 16; 4965 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4966 break; 4967 4968 default: 4969 break; 4970 } 4971 4972 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4973 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); 4974 if (unlikely(err)) { 4975 mlx5_ib_warn(dev, "\n"); 4976 *bad_wr = wr; 4977 goto out; 4978 } 4979 } else { 4980 for (i = 0; i < num_sge; i++) { 4981 handle_post_send_edge(&qp->sq, &seg, size, 4982 &cur_edge); 4983 if (likely(wr->sg_list[i].length)) { 4984 set_data_ptr_seg 4985 ((struct mlx5_wqe_data_seg *)seg, 4986 wr->sg_list + i); 4987 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4988 seg += sizeof(struct mlx5_wqe_data_seg); 4989 } 4990 } 4991 } 4992 4993 qp->next_fence = next_fence; 4994 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, 4995 fence, mlx5_ib_opcode[wr->opcode]); 4996 skip_psv: 4997 if (0) 4998 dump_wqe(qp, idx, size); 4999 } 5000 5001 out: 5002 if (likely(nreq)) { 5003 qp->sq.head += nreq; 5004 5005 /* Make sure that descriptors are written before 5006 * updating doorbell record and ringing the doorbell 5007 */ 5008 wmb(); 5009 5010 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 5011 5012 /* Make sure doorbell record is visible to the HCA before 5013 * we hit doorbell */ 5014 wmb(); 5015 5016 /* currently we support only regular doorbells */ 5017 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 5018 /* Make sure doorbells don't leak out of SQ spinlock 5019 * and reach the HCA out of order. 5020 */ 5021 mmiowb(); 5022 bf->offset ^= bf->buf_size; 5023 } 5024 5025 spin_unlock_irqrestore(&qp->sq.lock, flags); 5026 5027 return err; 5028 } 5029 5030 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5031 const struct ib_send_wr **bad_wr) 5032 { 5033 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); 5034 } 5035 5036 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 5037 { 5038 sig->signature = calc_sig(sig, size); 5039 } 5040 5041 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5042 const struct ib_recv_wr **bad_wr, bool drain) 5043 { 5044 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5045 struct mlx5_wqe_data_seg *scat; 5046 struct mlx5_rwqe_sig *sig; 5047 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5048 struct mlx5_core_dev *mdev = dev->mdev; 5049 unsigned long flags; 5050 int err = 0; 5051 int nreq; 5052 int ind; 5053 int i; 5054 5055 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5056 !drain)) { 5057 *bad_wr = wr; 5058 return -EIO; 5059 } 5060 5061 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5062 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 5063 5064 spin_lock_irqsave(&qp->rq.lock, flags); 5065 5066 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 5067 5068 for (nreq = 0; wr; nreq++, wr = wr->next) { 5069 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 5070 err = -ENOMEM; 5071 *bad_wr = wr; 5072 goto out; 5073 } 5074 5075 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 5076 err = -EINVAL; 5077 *bad_wr = wr; 5078 goto out; 5079 } 5080 5081 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); 5082 if (qp->wq_sig) 5083 scat++; 5084 5085 for (i = 0; i < wr->num_sge; i++) 5086 set_data_ptr_seg(scat + i, wr->sg_list + i); 5087 5088 if (i < qp->rq.max_gs) { 5089 scat[i].byte_count = 0; 5090 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 5091 scat[i].addr = 0; 5092 } 5093 5094 if (qp->wq_sig) { 5095 sig = (struct mlx5_rwqe_sig *)scat; 5096 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 5097 } 5098 5099 qp->rq.wrid[ind] = wr->wr_id; 5100 5101 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 5102 } 5103 5104 out: 5105 if (likely(nreq)) { 5106 qp->rq.head += nreq; 5107 5108 /* Make sure that descriptors are written before 5109 * doorbell record. 5110 */ 5111 wmb(); 5112 5113 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 5114 } 5115 5116 spin_unlock_irqrestore(&qp->rq.lock, flags); 5117 5118 return err; 5119 } 5120 5121 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5122 const struct ib_recv_wr **bad_wr) 5123 { 5124 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); 5125 } 5126 5127 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 5128 { 5129 switch (mlx5_state) { 5130 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 5131 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 5132 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 5133 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 5134 case MLX5_QP_STATE_SQ_DRAINING: 5135 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 5136 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 5137 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 5138 default: return -1; 5139 } 5140 } 5141 5142 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 5143 { 5144 switch (mlx5_mig_state) { 5145 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 5146 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 5147 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 5148 default: return -1; 5149 } 5150 } 5151 5152 static int to_ib_qp_access_flags(int mlx5_flags) 5153 { 5154 int ib_flags = 0; 5155 5156 if (mlx5_flags & MLX5_QP_BIT_RRE) 5157 ib_flags |= IB_ACCESS_REMOTE_READ; 5158 if (mlx5_flags & MLX5_QP_BIT_RWE) 5159 ib_flags |= IB_ACCESS_REMOTE_WRITE; 5160 if (mlx5_flags & MLX5_QP_BIT_RAE) 5161 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 5162 5163 return ib_flags; 5164 } 5165 5166 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 5167 struct rdma_ah_attr *ah_attr, 5168 struct mlx5_qp_path *path) 5169 { 5170 5171 memset(ah_attr, 0, sizeof(*ah_attr)); 5172 5173 if (!path->port || path->port > ibdev->num_ports) 5174 return; 5175 5176 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 5177 5178 rdma_ah_set_port_num(ah_attr, path->port); 5179 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 5180 5181 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 5182 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 5183 rdma_ah_set_static_rate(ah_attr, 5184 path->static_rate ? path->static_rate - 5 : 0); 5185 if (path->grh_mlid & (1 << 7)) { 5186 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 5187 5188 rdma_ah_set_grh(ah_attr, NULL, 5189 tc_fl & 0xfffff, 5190 path->mgid_index, 5191 path->hop_limit, 5192 (tc_fl >> 20) & 0xff); 5193 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 5194 } 5195 } 5196 5197 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 5198 struct mlx5_ib_sq *sq, 5199 u8 *sq_state) 5200 { 5201 int err; 5202 5203 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 5204 if (err) 5205 goto out; 5206 sq->state = *sq_state; 5207 5208 out: 5209 return err; 5210 } 5211 5212 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 5213 struct mlx5_ib_rq *rq, 5214 u8 *rq_state) 5215 { 5216 void *out; 5217 void *rqc; 5218 int inlen; 5219 int err; 5220 5221 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 5222 out = kvzalloc(inlen, GFP_KERNEL); 5223 if (!out) 5224 return -ENOMEM; 5225 5226 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 5227 if (err) 5228 goto out; 5229 5230 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 5231 *rq_state = MLX5_GET(rqc, rqc, state); 5232 rq->state = *rq_state; 5233 5234 out: 5235 kvfree(out); 5236 return err; 5237 } 5238 5239 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 5240 struct mlx5_ib_qp *qp, u8 *qp_state) 5241 { 5242 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 5243 [MLX5_RQC_STATE_RST] = { 5244 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5245 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5246 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 5247 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 5248 }, 5249 [MLX5_RQC_STATE_RDY] = { 5250 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5251 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5252 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 5253 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 5254 }, 5255 [MLX5_RQC_STATE_ERR] = { 5256 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5257 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5258 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 5259 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 5260 }, 5261 [MLX5_RQ_STATE_NA] = { 5262 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5263 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5264 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 5265 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 5266 }, 5267 }; 5268 5269 *qp_state = sqrq_trans[rq_state][sq_state]; 5270 5271 if (*qp_state == MLX5_QP_STATE_BAD) { 5272 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 5273 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 5274 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 5275 return -EINVAL; 5276 } 5277 5278 if (*qp_state == MLX5_QP_STATE) 5279 *qp_state = qp->state; 5280 5281 return 0; 5282 } 5283 5284 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 5285 struct mlx5_ib_qp *qp, 5286 u8 *raw_packet_qp_state) 5287 { 5288 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 5289 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 5290 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 5291 int err; 5292 u8 sq_state = MLX5_SQ_STATE_NA; 5293 u8 rq_state = MLX5_RQ_STATE_NA; 5294 5295 if (qp->sq.wqe_cnt) { 5296 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 5297 if (err) 5298 return err; 5299 } 5300 5301 if (qp->rq.wqe_cnt) { 5302 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 5303 if (err) 5304 return err; 5305 } 5306 5307 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 5308 raw_packet_qp_state); 5309 } 5310 5311 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 5312 struct ib_qp_attr *qp_attr) 5313 { 5314 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 5315 struct mlx5_qp_context *context; 5316 int mlx5_state; 5317 u32 *outb; 5318 int err = 0; 5319 5320 outb = kzalloc(outlen, GFP_KERNEL); 5321 if (!outb) 5322 return -ENOMEM; 5323 5324 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 5325 outlen); 5326 if (err) 5327 goto out; 5328 5329 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 5330 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 5331 5332 mlx5_state = be32_to_cpu(context->flags) >> 28; 5333 5334 qp->state = to_ib_qp_state(mlx5_state); 5335 qp_attr->path_mtu = context->mtu_msgmax >> 5; 5336 qp_attr->path_mig_state = 5337 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 5338 qp_attr->qkey = be32_to_cpu(context->qkey); 5339 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 5340 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 5341 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 5342 qp_attr->qp_access_flags = 5343 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 5344 5345 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 5346 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 5347 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5348 qp_attr->alt_pkey_index = 5349 be16_to_cpu(context->alt_path.pkey_index); 5350 qp_attr->alt_port_num = 5351 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5352 } 5353 5354 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5355 qp_attr->port_num = context->pri_path.port; 5356 5357 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5358 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5359 5360 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5361 5362 qp_attr->max_dest_rd_atomic = 5363 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5364 qp_attr->min_rnr_timer = 5365 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5366 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5367 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5368 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5369 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5370 5371 out: 5372 kfree(outb); 5373 return err; 5374 } 5375 5376 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5377 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5378 struct ib_qp_init_attr *qp_init_attr) 5379 { 5380 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5381 u32 *out; 5382 u32 access_flags = 0; 5383 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5384 void *dctc; 5385 int err; 5386 int supported_mask = IB_QP_STATE | 5387 IB_QP_ACCESS_FLAGS | 5388 IB_QP_PORT | 5389 IB_QP_MIN_RNR_TIMER | 5390 IB_QP_AV | 5391 IB_QP_PATH_MTU | 5392 IB_QP_PKEY_INDEX; 5393 5394 if (qp_attr_mask & ~supported_mask) 5395 return -EINVAL; 5396 if (mqp->state != IB_QPS_RTR) 5397 return -EINVAL; 5398 5399 out = kzalloc(outlen, GFP_KERNEL); 5400 if (!out) 5401 return -ENOMEM; 5402 5403 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5404 if (err) 5405 goto out; 5406 5407 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5408 5409 if (qp_attr_mask & IB_QP_STATE) 5410 qp_attr->qp_state = IB_QPS_RTR; 5411 5412 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5413 if (MLX5_GET(dctc, dctc, rre)) 5414 access_flags |= IB_ACCESS_REMOTE_READ; 5415 if (MLX5_GET(dctc, dctc, rwe)) 5416 access_flags |= IB_ACCESS_REMOTE_WRITE; 5417 if (MLX5_GET(dctc, dctc, rae)) 5418 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5419 qp_attr->qp_access_flags = access_flags; 5420 } 5421 5422 if (qp_attr_mask & IB_QP_PORT) 5423 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5424 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5425 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5426 if (qp_attr_mask & IB_QP_AV) { 5427 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5428 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5429 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5430 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5431 } 5432 if (qp_attr_mask & IB_QP_PATH_MTU) 5433 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5434 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5435 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5436 out: 5437 kfree(out); 5438 return err; 5439 } 5440 5441 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5442 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5443 { 5444 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5445 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5446 int err = 0; 5447 u8 raw_packet_qp_state; 5448 5449 if (ibqp->rwq_ind_tbl) 5450 return -ENOSYS; 5451 5452 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5453 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5454 qp_init_attr); 5455 5456 /* Not all of output fields are applicable, make sure to zero them */ 5457 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5458 memset(qp_attr, 0, sizeof(*qp_attr)); 5459 5460 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5461 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5462 qp_attr_mask, qp_init_attr); 5463 5464 mutex_lock(&qp->mutex); 5465 5466 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5467 qp->flags & MLX5_IB_QP_UNDERLAY) { 5468 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5469 if (err) 5470 goto out; 5471 qp->state = raw_packet_qp_state; 5472 qp_attr->port_num = 1; 5473 } else { 5474 err = query_qp_attr(dev, qp, qp_attr); 5475 if (err) 5476 goto out; 5477 } 5478 5479 qp_attr->qp_state = qp->state; 5480 qp_attr->cur_qp_state = qp_attr->qp_state; 5481 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5482 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5483 5484 if (!ibqp->uobject) { 5485 qp_attr->cap.max_send_wr = qp->sq.max_post; 5486 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5487 qp_init_attr->qp_context = ibqp->qp_context; 5488 } else { 5489 qp_attr->cap.max_send_wr = 0; 5490 qp_attr->cap.max_send_sge = 0; 5491 } 5492 5493 qp_init_attr->qp_type = ibqp->qp_type; 5494 qp_init_attr->recv_cq = ibqp->recv_cq; 5495 qp_init_attr->send_cq = ibqp->send_cq; 5496 qp_init_attr->srq = ibqp->srq; 5497 qp_attr->cap.max_inline_data = qp->max_inline_data; 5498 5499 qp_init_attr->cap = qp_attr->cap; 5500 5501 qp_init_attr->create_flags = 0; 5502 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5503 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5504 5505 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5506 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5507 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5508 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5509 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5510 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5511 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5512 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5513 5514 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5515 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5516 5517 out: 5518 mutex_unlock(&qp->mutex); 5519 return err; 5520 } 5521 5522 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5523 struct ib_ucontext *context, 5524 struct ib_udata *udata) 5525 { 5526 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5527 struct mlx5_ib_xrcd *xrcd; 5528 int err; 5529 5530 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5531 return ERR_PTR(-ENOSYS); 5532 5533 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5534 if (!xrcd) 5535 return ERR_PTR(-ENOMEM); 5536 5537 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5538 if (err) { 5539 kfree(xrcd); 5540 return ERR_PTR(-ENOMEM); 5541 } 5542 5543 return &xrcd->ibxrcd; 5544 } 5545 5546 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5547 { 5548 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5549 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5550 int err; 5551 5552 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5553 if (err) 5554 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5555 5556 kfree(xrcd); 5557 return 0; 5558 } 5559 5560 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5561 { 5562 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5563 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5564 struct ib_event event; 5565 5566 if (rwq->ibwq.event_handler) { 5567 event.device = rwq->ibwq.device; 5568 event.element.wq = &rwq->ibwq; 5569 switch (type) { 5570 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5571 event.event = IB_EVENT_WQ_FATAL; 5572 break; 5573 default: 5574 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5575 return; 5576 } 5577 5578 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5579 } 5580 } 5581 5582 static int set_delay_drop(struct mlx5_ib_dev *dev) 5583 { 5584 int err = 0; 5585 5586 mutex_lock(&dev->delay_drop.lock); 5587 if (dev->delay_drop.activate) 5588 goto out; 5589 5590 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5591 if (err) 5592 goto out; 5593 5594 dev->delay_drop.activate = true; 5595 out: 5596 mutex_unlock(&dev->delay_drop.lock); 5597 5598 if (!err) 5599 atomic_inc(&dev->delay_drop.rqs_cnt); 5600 return err; 5601 } 5602 5603 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5604 struct ib_wq_init_attr *init_attr) 5605 { 5606 struct mlx5_ib_dev *dev; 5607 int has_net_offloads; 5608 __be64 *rq_pas0; 5609 void *in; 5610 void *rqc; 5611 void *wq; 5612 int inlen; 5613 int err; 5614 5615 dev = to_mdev(pd->device); 5616 5617 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5618 in = kvzalloc(inlen, GFP_KERNEL); 5619 if (!in) 5620 return -ENOMEM; 5621 5622 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5623 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5624 MLX5_SET(rqc, rqc, mem_rq_type, 5625 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5626 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5627 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5628 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5629 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5630 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5631 MLX5_SET(wq, wq, wq_type, 5632 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5633 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5634 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5635 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5636 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5637 err = -EOPNOTSUPP; 5638 goto out; 5639 } else { 5640 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5641 } 5642 } 5643 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5644 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5645 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5646 MLX5_SET(wq, wq, log_wqe_stride_size, 5647 rwq->single_stride_log_num_of_bytes - 5648 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5649 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5650 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5651 } 5652 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5653 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5654 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5655 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5656 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5657 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5658 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5659 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5660 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5661 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5662 err = -EOPNOTSUPP; 5663 goto out; 5664 } 5665 } else { 5666 MLX5_SET(rqc, rqc, vsd, 1); 5667 } 5668 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5669 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5670 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5671 err = -EOPNOTSUPP; 5672 goto out; 5673 } 5674 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5675 } 5676 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5677 if (!(dev->ib_dev.attrs.raw_packet_caps & 5678 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5679 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5680 err = -EOPNOTSUPP; 5681 goto out; 5682 } 5683 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5684 } 5685 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5686 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5687 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5688 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5689 err = set_delay_drop(dev); 5690 if (err) { 5691 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5692 err); 5693 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5694 } else { 5695 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5696 } 5697 } 5698 out: 5699 kvfree(in); 5700 return err; 5701 } 5702 5703 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5704 struct ib_wq_init_attr *wq_init_attr, 5705 struct mlx5_ib_create_wq *ucmd, 5706 struct mlx5_ib_rwq *rwq) 5707 { 5708 /* Sanity check RQ size before proceeding */ 5709 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5710 return -EINVAL; 5711 5712 if (!ucmd->rq_wqe_count) 5713 return -EINVAL; 5714 5715 rwq->wqe_count = ucmd->rq_wqe_count; 5716 rwq->wqe_shift = ucmd->rq_wqe_shift; 5717 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5718 return -EINVAL; 5719 5720 rwq->log_rq_stride = rwq->wqe_shift; 5721 rwq->log_rq_size = ilog2(rwq->wqe_count); 5722 return 0; 5723 } 5724 5725 static int prepare_user_rq(struct ib_pd *pd, 5726 struct ib_wq_init_attr *init_attr, 5727 struct ib_udata *udata, 5728 struct mlx5_ib_rwq *rwq) 5729 { 5730 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5731 struct mlx5_ib_create_wq ucmd = {}; 5732 int err; 5733 size_t required_cmd_sz; 5734 5735 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5736 + sizeof(ucmd.single_stride_log_num_of_bytes); 5737 if (udata->inlen < required_cmd_sz) { 5738 mlx5_ib_dbg(dev, "invalid inlen\n"); 5739 return -EINVAL; 5740 } 5741 5742 if (udata->inlen > sizeof(ucmd) && 5743 !ib_is_udata_cleared(udata, sizeof(ucmd), 5744 udata->inlen - sizeof(ucmd))) { 5745 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5746 return -EOPNOTSUPP; 5747 } 5748 5749 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5750 mlx5_ib_dbg(dev, "copy failed\n"); 5751 return -EFAULT; 5752 } 5753 5754 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5755 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5756 return -EOPNOTSUPP; 5757 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5758 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5759 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5760 return -EOPNOTSUPP; 5761 } 5762 if ((ucmd.single_stride_log_num_of_bytes < 5763 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5764 (ucmd.single_stride_log_num_of_bytes > 5765 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5766 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5767 ucmd.single_stride_log_num_of_bytes, 5768 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5769 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5770 return -EINVAL; 5771 } 5772 if ((ucmd.single_wqe_log_num_of_strides > 5773 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5774 (ucmd.single_wqe_log_num_of_strides < 5775 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5776 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5777 ucmd.single_wqe_log_num_of_strides, 5778 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5779 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5780 return -EINVAL; 5781 } 5782 rwq->single_stride_log_num_of_bytes = 5783 ucmd.single_stride_log_num_of_bytes; 5784 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5785 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5786 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5787 } 5788 5789 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5790 if (err) { 5791 mlx5_ib_dbg(dev, "err %d\n", err); 5792 return err; 5793 } 5794 5795 err = create_user_rq(dev, pd, rwq, &ucmd); 5796 if (err) { 5797 mlx5_ib_dbg(dev, "err %d\n", err); 5798 return err; 5799 } 5800 5801 rwq->user_index = ucmd.user_index; 5802 return 0; 5803 } 5804 5805 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5806 struct ib_wq_init_attr *init_attr, 5807 struct ib_udata *udata) 5808 { 5809 struct mlx5_ib_dev *dev; 5810 struct mlx5_ib_rwq *rwq; 5811 struct mlx5_ib_create_wq_resp resp = {}; 5812 size_t min_resp_len; 5813 int err; 5814 5815 if (!udata) 5816 return ERR_PTR(-ENOSYS); 5817 5818 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5819 if (udata->outlen && udata->outlen < min_resp_len) 5820 return ERR_PTR(-EINVAL); 5821 5822 dev = to_mdev(pd->device); 5823 switch (init_attr->wq_type) { 5824 case IB_WQT_RQ: 5825 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5826 if (!rwq) 5827 return ERR_PTR(-ENOMEM); 5828 err = prepare_user_rq(pd, init_attr, udata, rwq); 5829 if (err) 5830 goto err; 5831 err = create_rq(rwq, pd, init_attr); 5832 if (err) 5833 goto err_user_rq; 5834 break; 5835 default: 5836 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5837 init_attr->wq_type); 5838 return ERR_PTR(-EINVAL); 5839 } 5840 5841 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5842 rwq->ibwq.state = IB_WQS_RESET; 5843 if (udata->outlen) { 5844 resp.response_length = offsetof(typeof(resp), response_length) + 5845 sizeof(resp.response_length); 5846 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5847 if (err) 5848 goto err_copy; 5849 } 5850 5851 rwq->core_qp.event = mlx5_ib_wq_event; 5852 rwq->ibwq.event_handler = init_attr->event_handler; 5853 return &rwq->ibwq; 5854 5855 err_copy: 5856 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5857 err_user_rq: 5858 destroy_user_rq(dev, pd, rwq); 5859 err: 5860 kfree(rwq); 5861 return ERR_PTR(err); 5862 } 5863 5864 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5865 { 5866 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5867 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5868 5869 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5870 destroy_user_rq(dev, wq->pd, rwq); 5871 kfree(rwq); 5872 5873 return 0; 5874 } 5875 5876 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5877 struct ib_rwq_ind_table_init_attr *init_attr, 5878 struct ib_udata *udata) 5879 { 5880 struct mlx5_ib_dev *dev = to_mdev(device); 5881 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5882 int sz = 1 << init_attr->log_ind_tbl_size; 5883 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5884 size_t min_resp_len; 5885 int inlen; 5886 int err; 5887 int i; 5888 u32 *in; 5889 void *rqtc; 5890 5891 if (udata->inlen > 0 && 5892 !ib_is_udata_cleared(udata, 0, 5893 udata->inlen)) 5894 return ERR_PTR(-EOPNOTSUPP); 5895 5896 if (init_attr->log_ind_tbl_size > 5897 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5898 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5899 init_attr->log_ind_tbl_size, 5900 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5901 return ERR_PTR(-EINVAL); 5902 } 5903 5904 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5905 if (udata->outlen && udata->outlen < min_resp_len) 5906 return ERR_PTR(-EINVAL); 5907 5908 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5909 if (!rwq_ind_tbl) 5910 return ERR_PTR(-ENOMEM); 5911 5912 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5913 in = kvzalloc(inlen, GFP_KERNEL); 5914 if (!in) { 5915 err = -ENOMEM; 5916 goto err; 5917 } 5918 5919 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5920 5921 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5922 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5923 5924 for (i = 0; i < sz; i++) 5925 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5926 5927 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5928 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5929 5930 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5931 kvfree(in); 5932 5933 if (err) 5934 goto err; 5935 5936 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5937 if (udata->outlen) { 5938 resp.response_length = offsetof(typeof(resp), response_length) + 5939 sizeof(resp.response_length); 5940 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5941 if (err) 5942 goto err_copy; 5943 } 5944 5945 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5946 5947 err_copy: 5948 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5949 err: 5950 kfree(rwq_ind_tbl); 5951 return ERR_PTR(err); 5952 } 5953 5954 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5955 { 5956 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5957 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5958 5959 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5960 5961 kfree(rwq_ind_tbl); 5962 return 0; 5963 } 5964 5965 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5966 u32 wq_attr_mask, struct ib_udata *udata) 5967 { 5968 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5969 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5970 struct mlx5_ib_modify_wq ucmd = {}; 5971 size_t required_cmd_sz; 5972 int curr_wq_state; 5973 int wq_state; 5974 int inlen; 5975 int err; 5976 void *rqc; 5977 void *in; 5978 5979 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5980 if (udata->inlen < required_cmd_sz) 5981 return -EINVAL; 5982 5983 if (udata->inlen > sizeof(ucmd) && 5984 !ib_is_udata_cleared(udata, sizeof(ucmd), 5985 udata->inlen - sizeof(ucmd))) 5986 return -EOPNOTSUPP; 5987 5988 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5989 return -EFAULT; 5990 5991 if (ucmd.comp_mask || ucmd.reserved) 5992 return -EOPNOTSUPP; 5993 5994 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5995 in = kvzalloc(inlen, GFP_KERNEL); 5996 if (!in) 5997 return -ENOMEM; 5998 5999 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 6000 6001 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 6002 wq_attr->curr_wq_state : wq->state; 6003 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 6004 wq_attr->wq_state : curr_wq_state; 6005 if (curr_wq_state == IB_WQS_ERR) 6006 curr_wq_state = MLX5_RQC_STATE_ERR; 6007 if (wq_state == IB_WQS_ERR) 6008 wq_state = MLX5_RQC_STATE_ERR; 6009 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 6010 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 6011 MLX5_SET(rqc, rqc, state, wq_state); 6012 6013 if (wq_attr_mask & IB_WQ_FLAGS) { 6014 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6015 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 6016 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6017 mlx5_ib_dbg(dev, "VLAN offloads are not " 6018 "supported\n"); 6019 err = -EOPNOTSUPP; 6020 goto out; 6021 } 6022 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6023 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 6024 MLX5_SET(rqc, rqc, vsd, 6025 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 6026 } 6027 6028 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6029 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 6030 err = -EOPNOTSUPP; 6031 goto out; 6032 } 6033 } 6034 6035 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 6036 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 6037 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6038 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 6039 MLX5_SET(rqc, rqc, counter_set_id, 6040 dev->port->cnts.set_id); 6041 } else 6042 dev_info_once( 6043 &dev->ib_dev.dev, 6044 "Receive WQ counters are not supported on current FW\n"); 6045 } 6046 6047 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 6048 if (!err) 6049 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 6050 6051 out: 6052 kvfree(in); 6053 return err; 6054 } 6055 6056 struct mlx5_ib_drain_cqe { 6057 struct ib_cqe cqe; 6058 struct completion done; 6059 }; 6060 6061 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 6062 { 6063 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 6064 struct mlx5_ib_drain_cqe, 6065 cqe); 6066 6067 complete(&cqe->done); 6068 } 6069 6070 /* This function returns only once the drained WR was completed */ 6071 static void handle_drain_completion(struct ib_cq *cq, 6072 struct mlx5_ib_drain_cqe *sdrain, 6073 struct mlx5_ib_dev *dev) 6074 { 6075 struct mlx5_core_dev *mdev = dev->mdev; 6076 6077 if (cq->poll_ctx == IB_POLL_DIRECT) { 6078 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 6079 ib_process_cq_direct(cq, -1); 6080 return; 6081 } 6082 6083 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6084 struct mlx5_ib_cq *mcq = to_mcq(cq); 6085 bool triggered = false; 6086 unsigned long flags; 6087 6088 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 6089 /* Make sure that the CQ handler won't run if wasn't run yet */ 6090 if (!mcq->mcq.reset_notify_added) 6091 mcq->mcq.reset_notify_added = 1; 6092 else 6093 triggered = true; 6094 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 6095 6096 if (triggered) { 6097 /* Wait for any scheduled/running task to be ended */ 6098 switch (cq->poll_ctx) { 6099 case IB_POLL_SOFTIRQ: 6100 irq_poll_disable(&cq->iop); 6101 irq_poll_enable(&cq->iop); 6102 break; 6103 case IB_POLL_WORKQUEUE: 6104 cancel_work_sync(&cq->work); 6105 break; 6106 default: 6107 WARN_ON_ONCE(1); 6108 } 6109 } 6110 6111 /* Run the CQ handler - this makes sure that the drain WR will 6112 * be processed if wasn't processed yet. 6113 */ 6114 mcq->mcq.comp(&mcq->mcq); 6115 } 6116 6117 wait_for_completion(&sdrain->done); 6118 } 6119 6120 void mlx5_ib_drain_sq(struct ib_qp *qp) 6121 { 6122 struct ib_cq *cq = qp->send_cq; 6123 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6124 struct mlx5_ib_drain_cqe sdrain; 6125 const struct ib_send_wr *bad_swr; 6126 struct ib_rdma_wr swr = { 6127 .wr = { 6128 .next = NULL, 6129 { .wr_cqe = &sdrain.cqe, }, 6130 .opcode = IB_WR_RDMA_WRITE, 6131 }, 6132 }; 6133 int ret; 6134 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6135 struct mlx5_core_dev *mdev = dev->mdev; 6136 6137 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6138 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6139 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6140 return; 6141 } 6142 6143 sdrain.cqe.done = mlx5_ib_drain_qp_done; 6144 init_completion(&sdrain.done); 6145 6146 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); 6147 if (ret) { 6148 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6149 return; 6150 } 6151 6152 handle_drain_completion(cq, &sdrain, dev); 6153 } 6154 6155 void mlx5_ib_drain_rq(struct ib_qp *qp) 6156 { 6157 struct ib_cq *cq = qp->recv_cq; 6158 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6159 struct mlx5_ib_drain_cqe rdrain; 6160 struct ib_recv_wr rwr = {}; 6161 const struct ib_recv_wr *bad_rwr; 6162 int ret; 6163 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6164 struct mlx5_core_dev *mdev = dev->mdev; 6165 6166 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6167 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6168 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6169 return; 6170 } 6171 6172 rwr.wr_cqe = &rdrain.cqe; 6173 rdrain.cqe.done = mlx5_ib_drain_qp_done; 6174 init_completion(&rdrain.done); 6175 6176 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); 6177 if (ret) { 6178 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6179 return; 6180 } 6181 6182 handle_drain_completion(cq, &rdrain, dev); 6183 } 6184