1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include "mlx5_ib.h" 38 #include "user.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 MLX5_IB_CACHE_LINE_SIZE = 64, 57 }; 58 59 static const u32 mlx5_ib_opcode[] = { 60 [IB_WR_SEND] = MLX5_OPCODE_SEND, 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 73 }; 74 75 76 static int is_qp0(enum ib_qp_type qp_type) 77 { 78 return qp_type == IB_QPT_SMI; 79 } 80 81 static int is_sqp(enum ib_qp_type qp_type) 82 { 83 return is_qp0(qp_type) || is_qp1(qp_type); 84 } 85 86 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 87 { 88 return mlx5_buf_offset(&qp->buf, offset); 89 } 90 91 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 92 { 93 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 94 } 95 96 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 97 { 98 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 99 } 100 101 /** 102 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 103 * 104 * @qp: QP to copy from. 105 * @send: copy from the send queue when non-zero, use the receive queue 106 * otherwise. 107 * @wqe_index: index to start copying from. For send work queues, the 108 * wqe_index is in units of MLX5_SEND_WQE_BB. 109 * For receive work queue, it is the number of work queue 110 * element in the queue. 111 * @buffer: destination buffer. 112 * @length: maximum number of bytes to copy. 113 * 114 * Copies at least a single WQE, but may copy more data. 115 * 116 * Return: the number of bytes copied, or an error code. 117 */ 118 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 119 void *buffer, u32 length, 120 struct mlx5_ib_qp_base *base) 121 { 122 struct ib_device *ibdev = qp->ibqp.device; 123 struct mlx5_ib_dev *dev = to_mdev(ibdev); 124 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 125 size_t offset; 126 size_t wq_end; 127 struct ib_umem *umem = base->ubuffer.umem; 128 u32 first_copy_length; 129 int wqe_length; 130 int ret; 131 132 if (wq->wqe_cnt == 0) { 133 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 134 qp->ibqp.qp_type); 135 return -EINVAL; 136 } 137 138 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 139 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 140 141 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 142 return -EINVAL; 143 144 if (offset > umem->length || 145 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 146 return -EINVAL; 147 148 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 149 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 150 if (ret) 151 return ret; 152 153 if (send) { 154 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 155 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 156 157 wqe_length = ds * MLX5_WQE_DS_UNITS; 158 } else { 159 wqe_length = 1 << wq->wqe_shift; 160 } 161 162 if (wqe_length <= first_copy_length) 163 return first_copy_length; 164 165 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 166 wqe_length - first_copy_length); 167 if (ret) 168 return ret; 169 170 return wqe_length; 171 } 172 173 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 174 { 175 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 176 struct ib_event event; 177 178 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 179 /* This event is only valid for trans_qps */ 180 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 181 } 182 183 if (ibqp->event_handler) { 184 event.device = ibqp->device; 185 event.element.qp = ibqp; 186 switch (type) { 187 case MLX5_EVENT_TYPE_PATH_MIG: 188 event.event = IB_EVENT_PATH_MIG; 189 break; 190 case MLX5_EVENT_TYPE_COMM_EST: 191 event.event = IB_EVENT_COMM_EST; 192 break; 193 case MLX5_EVENT_TYPE_SQ_DRAINED: 194 event.event = IB_EVENT_SQ_DRAINED; 195 break; 196 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 197 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 198 break; 199 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 200 event.event = IB_EVENT_QP_FATAL; 201 break; 202 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 203 event.event = IB_EVENT_PATH_MIG_ERR; 204 break; 205 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 206 event.event = IB_EVENT_QP_REQ_ERR; 207 break; 208 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 209 event.event = IB_EVENT_QP_ACCESS_ERR; 210 break; 211 default: 212 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 213 return; 214 } 215 216 ibqp->event_handler(&event, ibqp->qp_context); 217 } 218 } 219 220 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 221 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 222 { 223 int wqe_size; 224 int wq_size; 225 226 /* Sanity check RQ size before proceeding */ 227 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 228 return -EINVAL; 229 230 if (!has_rq) { 231 qp->rq.max_gs = 0; 232 qp->rq.wqe_cnt = 0; 233 qp->rq.wqe_shift = 0; 234 } else { 235 if (ucmd) { 236 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 237 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 238 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 239 qp->rq.max_post = qp->rq.wqe_cnt; 240 } else { 241 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 242 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 243 wqe_size = roundup_pow_of_two(wqe_size); 244 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 245 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 246 qp->rq.wqe_cnt = wq_size / wqe_size; 247 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 248 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 249 wqe_size, 250 MLX5_CAP_GEN(dev->mdev, 251 max_wqe_sz_rq)); 252 return -EINVAL; 253 } 254 qp->rq.wqe_shift = ilog2(wqe_size); 255 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 256 qp->rq.max_post = qp->rq.wqe_cnt; 257 } 258 } 259 260 return 0; 261 } 262 263 static int sq_overhead(enum ib_qp_type qp_type) 264 { 265 int size = 0; 266 267 switch (qp_type) { 268 case IB_QPT_XRC_INI: 269 size += sizeof(struct mlx5_wqe_xrc_seg); 270 /* fall through */ 271 case IB_QPT_RC: 272 size += sizeof(struct mlx5_wqe_ctrl_seg) + 273 sizeof(struct mlx5_wqe_atomic_seg) + 274 sizeof(struct mlx5_wqe_raddr_seg); 275 break; 276 277 case IB_QPT_XRC_TGT: 278 return 0; 279 280 case IB_QPT_UC: 281 size += sizeof(struct mlx5_wqe_ctrl_seg) + 282 sizeof(struct mlx5_wqe_raddr_seg) + 283 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 284 sizeof(struct mlx5_mkey_seg); 285 break; 286 287 case IB_QPT_UD: 288 case IB_QPT_SMI: 289 case IB_QPT_GSI: 290 size += sizeof(struct mlx5_wqe_ctrl_seg) + 291 sizeof(struct mlx5_wqe_datagram_seg); 292 break; 293 294 case MLX5_IB_QPT_REG_UMR: 295 size += sizeof(struct mlx5_wqe_ctrl_seg) + 296 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 297 sizeof(struct mlx5_mkey_seg); 298 break; 299 300 default: 301 return -EINVAL; 302 } 303 304 return size; 305 } 306 307 static int calc_send_wqe(struct ib_qp_init_attr *attr) 308 { 309 int inl_size = 0; 310 int size; 311 312 size = sq_overhead(attr->qp_type); 313 if (size < 0) 314 return size; 315 316 if (attr->cap.max_inline_data) { 317 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 318 attr->cap.max_inline_data; 319 } 320 321 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 322 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 323 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 324 return MLX5_SIG_WQE_SIZE; 325 else 326 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 327 } 328 329 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 330 struct mlx5_ib_qp *qp) 331 { 332 int wqe_size; 333 int wq_size; 334 335 if (!attr->cap.max_send_wr) 336 return 0; 337 338 wqe_size = calc_send_wqe(attr); 339 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 340 if (wqe_size < 0) 341 return wqe_size; 342 343 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 344 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 345 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 346 return -EINVAL; 347 } 348 349 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) - 350 sizeof(struct mlx5_wqe_inline_seg); 351 attr->cap.max_inline_data = qp->max_inline_data; 352 353 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 354 qp->signature_en = true; 355 356 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 357 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 358 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 359 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 360 qp->sq.wqe_cnt, 361 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 362 return -ENOMEM; 363 } 364 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 365 qp->sq.max_gs = attr->cap.max_send_sge; 366 qp->sq.max_post = wq_size / wqe_size; 367 attr->cap.max_send_wr = qp->sq.max_post; 368 369 return wq_size; 370 } 371 372 static int set_user_buf_size(struct mlx5_ib_dev *dev, 373 struct mlx5_ib_qp *qp, 374 struct mlx5_ib_create_qp *ucmd, 375 struct mlx5_ib_qp_base *base, 376 struct ib_qp_init_attr *attr) 377 { 378 int desc_sz = 1 << qp->sq.wqe_shift; 379 380 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 381 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 382 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 383 return -EINVAL; 384 } 385 386 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 387 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 388 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 389 return -EINVAL; 390 } 391 392 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 393 394 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 395 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 396 qp->sq.wqe_cnt, 397 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 398 return -EINVAL; 399 } 400 401 if (attr->qp_type == IB_QPT_RAW_PACKET) { 402 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 403 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 404 } else { 405 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 406 (qp->sq.wqe_cnt << 6); 407 } 408 409 return 0; 410 } 411 412 static int qp_has_rq(struct ib_qp_init_attr *attr) 413 { 414 if (attr->qp_type == IB_QPT_XRC_INI || 415 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 416 attr->qp_type == MLX5_IB_QPT_REG_UMR || 417 !attr->cap.max_recv_wr) 418 return 0; 419 420 return 1; 421 } 422 423 static int first_med_uuar(void) 424 { 425 return 1; 426 } 427 428 static int next_uuar(int n) 429 { 430 n++; 431 432 while (((n % 4) & 2)) 433 n++; 434 435 return n; 436 } 437 438 static int num_med_uuar(struct mlx5_uuar_info *uuari) 439 { 440 int n; 441 442 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 443 uuari->num_low_latency_uuars - 1; 444 445 return n >= 0 ? n : 0; 446 } 447 448 static int max_uuari(struct mlx5_uuar_info *uuari) 449 { 450 return uuari->num_uars * 4; 451 } 452 453 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 454 { 455 int med; 456 int i; 457 int t; 458 459 med = num_med_uuar(uuari); 460 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 461 t++; 462 if (t == med) 463 return next_uuar(i); 464 } 465 466 return 0; 467 } 468 469 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 470 { 471 int i; 472 473 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 474 if (!test_bit(i, uuari->bitmap)) { 475 set_bit(i, uuari->bitmap); 476 uuari->count[i]++; 477 return i; 478 } 479 } 480 481 return -ENOMEM; 482 } 483 484 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 485 { 486 int minidx = first_med_uuar(); 487 int i; 488 489 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 490 if (uuari->count[i] < uuari->count[minidx]) 491 minidx = i; 492 } 493 494 uuari->count[minidx]++; 495 return minidx; 496 } 497 498 static int alloc_uuar(struct mlx5_uuar_info *uuari, 499 enum mlx5_ib_latency_class lat) 500 { 501 int uuarn = -EINVAL; 502 503 mutex_lock(&uuari->lock); 504 switch (lat) { 505 case MLX5_IB_LATENCY_CLASS_LOW: 506 uuarn = 0; 507 uuari->count[uuarn]++; 508 break; 509 510 case MLX5_IB_LATENCY_CLASS_MEDIUM: 511 if (uuari->ver < 2) 512 uuarn = -ENOMEM; 513 else 514 uuarn = alloc_med_class_uuar(uuari); 515 break; 516 517 case MLX5_IB_LATENCY_CLASS_HIGH: 518 if (uuari->ver < 2) 519 uuarn = -ENOMEM; 520 else 521 uuarn = alloc_high_class_uuar(uuari); 522 break; 523 524 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 525 uuarn = 2; 526 break; 527 } 528 mutex_unlock(&uuari->lock); 529 530 return uuarn; 531 } 532 533 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 534 { 535 clear_bit(uuarn, uuari->bitmap); 536 --uuari->count[uuarn]; 537 } 538 539 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 540 { 541 clear_bit(uuarn, uuari->bitmap); 542 --uuari->count[uuarn]; 543 } 544 545 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 546 { 547 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 548 int high_uuar = nuuars - uuari->num_low_latency_uuars; 549 550 mutex_lock(&uuari->lock); 551 if (uuarn == 0) { 552 --uuari->count[uuarn]; 553 goto out; 554 } 555 556 if (uuarn < high_uuar) { 557 free_med_class_uuar(uuari, uuarn); 558 goto out; 559 } 560 561 free_high_class_uuar(uuari, uuarn); 562 563 out: 564 mutex_unlock(&uuari->lock); 565 } 566 567 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 568 { 569 switch (state) { 570 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 571 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 572 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 573 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 574 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 575 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 576 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 577 default: return -1; 578 } 579 } 580 581 static int to_mlx5_st(enum ib_qp_type type) 582 { 583 switch (type) { 584 case IB_QPT_RC: return MLX5_QP_ST_RC; 585 case IB_QPT_UC: return MLX5_QP_ST_UC; 586 case IB_QPT_UD: return MLX5_QP_ST_UD; 587 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 588 case IB_QPT_XRC_INI: 589 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 590 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 591 case IB_QPT_GSI: return MLX5_QP_ST_QP1; 592 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 593 case IB_QPT_RAW_PACKET: 594 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 595 case IB_QPT_MAX: 596 default: return -EINVAL; 597 } 598 } 599 600 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 601 { 602 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 603 } 604 605 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 606 struct ib_pd *pd, 607 unsigned long addr, size_t size, 608 struct ib_umem **umem, 609 int *npages, int *page_shift, int *ncont, 610 u32 *offset) 611 { 612 int err; 613 614 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 615 if (IS_ERR(*umem)) { 616 mlx5_ib_dbg(dev, "umem_get failed\n"); 617 return PTR_ERR(*umem); 618 } 619 620 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL); 621 622 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 623 if (err) { 624 mlx5_ib_warn(dev, "bad offset\n"); 625 goto err_umem; 626 } 627 628 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 629 addr, size, *npages, *page_shift, *ncont, *offset); 630 631 return 0; 632 633 err_umem: 634 ib_umem_release(*umem); 635 *umem = NULL; 636 637 return err; 638 } 639 640 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 641 struct mlx5_ib_qp *qp, struct ib_udata *udata, 642 struct ib_qp_init_attr *attr, 643 struct mlx5_create_qp_mbox_in **in, 644 struct mlx5_ib_create_qp_resp *resp, int *inlen, 645 struct mlx5_ib_qp_base *base) 646 { 647 struct mlx5_ib_ucontext *context; 648 struct mlx5_ib_create_qp ucmd; 649 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 650 int page_shift = 0; 651 int uar_index; 652 int npages; 653 u32 offset = 0; 654 int uuarn; 655 int ncont = 0; 656 int err; 657 658 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 659 if (err) { 660 mlx5_ib_dbg(dev, "copy failed\n"); 661 return err; 662 } 663 664 context = to_mucontext(pd->uobject->context); 665 /* 666 * TBD: should come from the verbs when we have the API 667 */ 668 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 669 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 670 uuarn = MLX5_CROSS_CHANNEL_UUAR; 671 else { 672 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 673 if (uuarn < 0) { 674 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 675 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 676 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 677 if (uuarn < 0) { 678 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 679 mlx5_ib_dbg(dev, "reverting to high latency\n"); 680 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 681 if (uuarn < 0) { 682 mlx5_ib_warn(dev, "uuar allocation failed\n"); 683 return uuarn; 684 } 685 } 686 } 687 } 688 689 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 690 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 691 692 qp->rq.offset = 0; 693 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 694 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 695 696 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 697 if (err) 698 goto err_uuar; 699 700 if (ucmd.buf_addr && ubuffer->buf_size) { 701 ubuffer->buf_addr = ucmd.buf_addr; 702 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 703 ubuffer->buf_size, 704 &ubuffer->umem, &npages, &page_shift, 705 &ncont, &offset); 706 if (err) 707 goto err_uuar; 708 } else { 709 ubuffer->umem = NULL; 710 } 711 712 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont; 713 *in = mlx5_vzalloc(*inlen); 714 if (!*in) { 715 err = -ENOMEM; 716 goto err_umem; 717 } 718 if (ubuffer->umem) 719 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, 720 (*in)->pas, 0); 721 (*in)->ctx.log_pg_sz_remote_qpn = 722 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 723 (*in)->ctx.params2 = cpu_to_be32(offset << 6); 724 725 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 726 resp->uuar_index = uuarn; 727 qp->uuarn = uuarn; 728 729 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 730 if (err) { 731 mlx5_ib_dbg(dev, "map failed\n"); 732 goto err_free; 733 } 734 735 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 736 if (err) { 737 mlx5_ib_dbg(dev, "copy failed\n"); 738 goto err_unmap; 739 } 740 qp->create_type = MLX5_QP_USER; 741 742 return 0; 743 744 err_unmap: 745 mlx5_ib_db_unmap_user(context, &qp->db); 746 747 err_free: 748 kvfree(*in); 749 750 err_umem: 751 if (ubuffer->umem) 752 ib_umem_release(ubuffer->umem); 753 754 err_uuar: 755 free_uuar(&context->uuari, uuarn); 756 return err; 757 } 758 759 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp, 760 struct mlx5_ib_qp_base *base) 761 { 762 struct mlx5_ib_ucontext *context; 763 764 context = to_mucontext(pd->uobject->context); 765 mlx5_ib_db_unmap_user(context, &qp->db); 766 if (base->ubuffer.umem) 767 ib_umem_release(base->ubuffer.umem); 768 free_uuar(&context->uuari, qp->uuarn); 769 } 770 771 static int create_kernel_qp(struct mlx5_ib_dev *dev, 772 struct ib_qp_init_attr *init_attr, 773 struct mlx5_ib_qp *qp, 774 struct mlx5_create_qp_mbox_in **in, int *inlen, 775 struct mlx5_ib_qp_base *base) 776 { 777 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 778 struct mlx5_uuar_info *uuari; 779 int uar_index; 780 int uuarn; 781 int err; 782 783 uuari = &dev->mdev->priv.uuari; 784 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)) 785 return -EINVAL; 786 787 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 788 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 789 790 uuarn = alloc_uuar(uuari, lc); 791 if (uuarn < 0) { 792 mlx5_ib_dbg(dev, "\n"); 793 return -ENOMEM; 794 } 795 796 qp->bf = &uuari->bfs[uuarn]; 797 uar_index = qp->bf->uar->index; 798 799 err = calc_sq_size(dev, init_attr, qp); 800 if (err < 0) { 801 mlx5_ib_dbg(dev, "err %d\n", err); 802 goto err_uuar; 803 } 804 805 qp->rq.offset = 0; 806 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 807 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 808 809 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 810 if (err) { 811 mlx5_ib_dbg(dev, "err %d\n", err); 812 goto err_uuar; 813 } 814 815 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 816 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages; 817 *in = mlx5_vzalloc(*inlen); 818 if (!*in) { 819 err = -ENOMEM; 820 goto err_buf; 821 } 822 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 823 (*in)->ctx.log_pg_sz_remote_qpn = 824 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 825 /* Set "fast registration enabled" for all kernel QPs */ 826 (*in)->ctx.params1 |= cpu_to_be32(1 << 11); 827 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4); 828 829 mlx5_fill_page_array(&qp->buf, (*in)->pas); 830 831 err = mlx5_db_alloc(dev->mdev, &qp->db); 832 if (err) { 833 mlx5_ib_dbg(dev, "err %d\n", err); 834 goto err_free; 835 } 836 837 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 838 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 839 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 840 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 841 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 842 843 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 844 !qp->sq.w_list || !qp->sq.wqe_head) { 845 err = -ENOMEM; 846 goto err_wrid; 847 } 848 qp->create_type = MLX5_QP_KERNEL; 849 850 return 0; 851 852 err_wrid: 853 mlx5_db_free(dev->mdev, &qp->db); 854 kfree(qp->sq.wqe_head); 855 kfree(qp->sq.w_list); 856 kfree(qp->sq.wrid); 857 kfree(qp->sq.wr_data); 858 kfree(qp->rq.wrid); 859 860 err_free: 861 kvfree(*in); 862 863 err_buf: 864 mlx5_buf_free(dev->mdev, &qp->buf); 865 866 err_uuar: 867 free_uuar(&dev->mdev->priv.uuari, uuarn); 868 return err; 869 } 870 871 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 872 { 873 mlx5_db_free(dev->mdev, &qp->db); 874 kfree(qp->sq.wqe_head); 875 kfree(qp->sq.w_list); 876 kfree(qp->sq.wrid); 877 kfree(qp->sq.wr_data); 878 kfree(qp->rq.wrid); 879 mlx5_buf_free(dev->mdev, &qp->buf); 880 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn); 881 } 882 883 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 884 { 885 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 886 (attr->qp_type == IB_QPT_XRC_INI)) 887 return cpu_to_be32(MLX5_SRQ_RQ); 888 else if (!qp->has_rq) 889 return cpu_to_be32(MLX5_ZERO_LEN_RQ); 890 else 891 return cpu_to_be32(MLX5_NON_ZERO_RQ); 892 } 893 894 static int is_connected(enum ib_qp_type qp_type) 895 { 896 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 897 return 1; 898 899 return 0; 900 } 901 902 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 903 struct mlx5_ib_sq *sq, u32 tdn) 904 { 905 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 906 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 907 908 memset(in, 0, sizeof(in)); 909 910 MLX5_SET(tisc, tisc, transport_domain, tdn); 911 912 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 913 } 914 915 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 916 struct mlx5_ib_sq *sq) 917 { 918 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 919 } 920 921 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 922 struct mlx5_ib_sq *sq, void *qpin, 923 struct ib_pd *pd) 924 { 925 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 926 __be64 *pas; 927 void *in; 928 void *sqc; 929 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 930 void *wq; 931 int inlen; 932 int err; 933 int page_shift = 0; 934 int npages; 935 int ncont = 0; 936 u32 offset = 0; 937 938 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 939 &sq->ubuffer.umem, &npages, &page_shift, 940 &ncont, &offset); 941 if (err) 942 return err; 943 944 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 945 in = mlx5_vzalloc(inlen); 946 if (!in) { 947 err = -ENOMEM; 948 goto err_umem; 949 } 950 951 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 952 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 953 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 954 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 955 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 956 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 957 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 958 959 wq = MLX5_ADDR_OF(sqc, sqc, wq); 960 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 961 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 962 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 963 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 964 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 965 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 966 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 967 MLX5_SET(wq, wq, page_offset, offset); 968 969 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 970 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 971 972 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 973 974 kvfree(in); 975 976 if (err) 977 goto err_umem; 978 979 return 0; 980 981 err_umem: 982 ib_umem_release(sq->ubuffer.umem); 983 sq->ubuffer.umem = NULL; 984 985 return err; 986 } 987 988 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 989 struct mlx5_ib_sq *sq) 990 { 991 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 992 ib_umem_release(sq->ubuffer.umem); 993 } 994 995 static int get_rq_pas_size(void *qpc) 996 { 997 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 998 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 999 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1000 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1001 u32 po_quanta = 1 << (log_page_size - 6); 1002 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1003 u32 page_size = 1 << log_page_size; 1004 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1005 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1006 1007 return rq_num_pas * sizeof(u64); 1008 } 1009 1010 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1011 struct mlx5_ib_rq *rq, void *qpin) 1012 { 1013 __be64 *pas; 1014 __be64 *qp_pas; 1015 void *in; 1016 void *rqc; 1017 void *wq; 1018 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1019 int inlen; 1020 int err; 1021 u32 rq_pas_size = get_rq_pas_size(qpc); 1022 1023 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1024 in = mlx5_vzalloc(inlen); 1025 if (!in) 1026 return -ENOMEM; 1027 1028 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1029 MLX5_SET(rqc, rqc, vsd, 1); 1030 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1031 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1032 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1033 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1034 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1035 1036 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1037 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1038 MLX5_SET(wq, wq, end_padding_mode, 1039 MLX5_GET64(qpc, qpc, end_padding_mode)); 1040 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1041 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1042 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1043 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1044 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1045 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1046 1047 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1048 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1049 memcpy(pas, qp_pas, rq_pas_size); 1050 1051 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1052 1053 kvfree(in); 1054 1055 return err; 1056 } 1057 1058 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1059 struct mlx5_ib_rq *rq) 1060 { 1061 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1062 } 1063 1064 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1065 struct mlx5_ib_rq *rq, u32 tdn) 1066 { 1067 u32 *in; 1068 void *tirc; 1069 int inlen; 1070 int err; 1071 1072 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1073 in = mlx5_vzalloc(inlen); 1074 if (!in) 1075 return -ENOMEM; 1076 1077 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1078 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1079 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1080 MLX5_SET(tirc, tirc, transport_domain, tdn); 1081 1082 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1083 1084 kvfree(in); 1085 1086 return err; 1087 } 1088 1089 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1090 struct mlx5_ib_rq *rq) 1091 { 1092 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1093 } 1094 1095 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1096 struct mlx5_create_qp_mbox_in *in, 1097 struct ib_pd *pd) 1098 { 1099 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1100 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1101 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1102 struct ib_uobject *uobj = pd->uobject; 1103 struct ib_ucontext *ucontext = uobj->context; 1104 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1105 int err; 1106 u32 tdn = mucontext->tdn; 1107 1108 if (qp->sq.wqe_cnt) { 1109 err = create_raw_packet_qp_tis(dev, sq, tdn); 1110 if (err) 1111 return err; 1112 1113 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1114 if (err) 1115 goto err_destroy_tis; 1116 1117 sq->base.container_mibqp = qp; 1118 } 1119 1120 if (qp->rq.wqe_cnt) { 1121 err = create_raw_packet_qp_rq(dev, rq, in); 1122 if (err) 1123 goto err_destroy_sq; 1124 1125 rq->base.container_mibqp = qp; 1126 1127 err = create_raw_packet_qp_tir(dev, rq, tdn); 1128 if (err) 1129 goto err_destroy_rq; 1130 } 1131 1132 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1133 rq->base.mqp.qpn; 1134 1135 return 0; 1136 1137 err_destroy_rq: 1138 destroy_raw_packet_qp_rq(dev, rq); 1139 err_destroy_sq: 1140 if (!qp->sq.wqe_cnt) 1141 return err; 1142 destroy_raw_packet_qp_sq(dev, sq); 1143 err_destroy_tis: 1144 destroy_raw_packet_qp_tis(dev, sq); 1145 1146 return err; 1147 } 1148 1149 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1150 struct mlx5_ib_qp *qp) 1151 { 1152 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1153 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1154 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1155 1156 if (qp->rq.wqe_cnt) { 1157 destroy_raw_packet_qp_tir(dev, rq); 1158 destroy_raw_packet_qp_rq(dev, rq); 1159 } 1160 1161 if (qp->sq.wqe_cnt) { 1162 destroy_raw_packet_qp_sq(dev, sq); 1163 destroy_raw_packet_qp_tis(dev, sq); 1164 } 1165 } 1166 1167 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1168 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1169 { 1170 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1171 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1172 1173 sq->sq = &qp->sq; 1174 rq->rq = &qp->rq; 1175 sq->doorbell = &qp->db; 1176 rq->doorbell = &qp->db; 1177 } 1178 1179 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1180 struct ib_qp_init_attr *init_attr, 1181 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1182 { 1183 struct mlx5_ib_resources *devr = &dev->devr; 1184 struct mlx5_core_dev *mdev = dev->mdev; 1185 struct mlx5_ib_qp_base *base; 1186 struct mlx5_ib_create_qp_resp resp; 1187 struct mlx5_create_qp_mbox_in *in; 1188 struct mlx5_ib_create_qp ucmd; 1189 int inlen = sizeof(*in); 1190 int err; 1191 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1192 void *qpc; 1193 1194 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1195 &qp->raw_packet_qp.rq.base : 1196 &qp->trans_qp.base; 1197 1198 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1199 mlx5_ib_odp_create_qp(qp); 1200 1201 mutex_init(&qp->mutex); 1202 spin_lock_init(&qp->sq.lock); 1203 spin_lock_init(&qp->rq.lock); 1204 1205 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1206 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1207 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1208 return -EINVAL; 1209 } else { 1210 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1211 } 1212 } 1213 1214 if (init_attr->create_flags & 1215 (IB_QP_CREATE_CROSS_CHANNEL | 1216 IB_QP_CREATE_MANAGED_SEND | 1217 IB_QP_CREATE_MANAGED_RECV)) { 1218 if (!MLX5_CAP_GEN(mdev, cd)) { 1219 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1220 return -EINVAL; 1221 } 1222 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1223 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1224 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1225 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1226 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1227 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1228 } 1229 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1230 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1231 1232 if (pd && pd->uobject) { 1233 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1234 mlx5_ib_dbg(dev, "copy failed\n"); 1235 return -EFAULT; 1236 } 1237 1238 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1239 &ucmd, udata->inlen, &uidx); 1240 if (err) 1241 return err; 1242 1243 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1244 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1245 } else { 1246 qp->wq_sig = !!wq_signature; 1247 } 1248 1249 qp->has_rq = qp_has_rq(init_attr); 1250 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1251 qp, (pd && pd->uobject) ? &ucmd : NULL); 1252 if (err) { 1253 mlx5_ib_dbg(dev, "err %d\n", err); 1254 return err; 1255 } 1256 1257 if (pd) { 1258 if (pd->uobject) { 1259 __u32 max_wqes = 1260 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1261 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1262 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1263 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1264 mlx5_ib_dbg(dev, "invalid rq params\n"); 1265 return -EINVAL; 1266 } 1267 if (ucmd.sq_wqe_count > max_wqes) { 1268 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1269 ucmd.sq_wqe_count, max_wqes); 1270 return -EINVAL; 1271 } 1272 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1273 &resp, &inlen, base); 1274 if (err) 1275 mlx5_ib_dbg(dev, "err %d\n", err); 1276 } else { 1277 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1278 base); 1279 if (err) 1280 mlx5_ib_dbg(dev, "err %d\n", err); 1281 } 1282 1283 if (err) 1284 return err; 1285 } else { 1286 in = mlx5_vzalloc(sizeof(*in)); 1287 if (!in) 1288 return -ENOMEM; 1289 1290 qp->create_type = MLX5_QP_EMPTY; 1291 } 1292 1293 if (is_sqp(init_attr->qp_type)) 1294 qp->port = init_attr->port_num; 1295 1296 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 | 1297 MLX5_QP_PM_MIGRATED << 11); 1298 1299 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1300 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn); 1301 else 1302 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE); 1303 1304 if (qp->wq_sig) 1305 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG); 1306 1307 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1308 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST); 1309 1310 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1311 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER); 1312 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1313 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND); 1314 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1315 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV); 1316 1317 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1318 int rcqe_sz; 1319 int scqe_sz; 1320 1321 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1322 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1323 1324 if (rcqe_sz == 128) 1325 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE; 1326 else 1327 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE; 1328 1329 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1330 if (scqe_sz == 128) 1331 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE; 1332 else 1333 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE; 1334 } 1335 } 1336 1337 if (qp->rq.wqe_cnt) { 1338 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4); 1339 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3; 1340 } 1341 1342 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr); 1343 1344 if (qp->sq.wqe_cnt) 1345 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11); 1346 else 1347 in->ctx.sq_crq_size |= cpu_to_be16(0x8000); 1348 1349 /* Set default resources */ 1350 switch (init_attr->qp_type) { 1351 case IB_QPT_XRC_TGT: 1352 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1353 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1354 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1355 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn); 1356 break; 1357 case IB_QPT_XRC_INI: 1358 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1359 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1360 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1361 break; 1362 default: 1363 if (init_attr->srq) { 1364 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn); 1365 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn); 1366 } else { 1367 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1368 in->ctx.rq_type_srqn |= 1369 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn); 1370 } 1371 } 1372 1373 if (init_attr->send_cq) 1374 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn); 1375 1376 if (init_attr->recv_cq) 1377 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn); 1378 1379 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma); 1380 1381 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) { 1382 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1383 /* 0xffffff means we ask to work with cqe version 0 */ 1384 MLX5_SET(qpc, qpc, user_index, uidx); 1385 } 1386 1387 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1388 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1389 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1390 err = create_raw_packet_qp(dev, qp, in, pd); 1391 } else { 1392 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1393 } 1394 1395 if (err) { 1396 mlx5_ib_dbg(dev, "create qp failed\n"); 1397 goto err_create; 1398 } 1399 1400 kvfree(in); 1401 1402 base->container_mibqp = qp; 1403 base->mqp.event = mlx5_ib_qp_event; 1404 1405 return 0; 1406 1407 err_create: 1408 if (qp->create_type == MLX5_QP_USER) 1409 destroy_qp_user(pd, qp, base); 1410 else if (qp->create_type == MLX5_QP_KERNEL) 1411 destroy_qp_kernel(dev, qp); 1412 1413 kvfree(in); 1414 return err; 1415 } 1416 1417 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1418 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1419 { 1420 if (send_cq) { 1421 if (recv_cq) { 1422 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1423 spin_lock_irq(&send_cq->lock); 1424 spin_lock_nested(&recv_cq->lock, 1425 SINGLE_DEPTH_NESTING); 1426 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1427 spin_lock_irq(&send_cq->lock); 1428 __acquire(&recv_cq->lock); 1429 } else { 1430 spin_lock_irq(&recv_cq->lock); 1431 spin_lock_nested(&send_cq->lock, 1432 SINGLE_DEPTH_NESTING); 1433 } 1434 } else { 1435 spin_lock_irq(&send_cq->lock); 1436 __acquire(&recv_cq->lock); 1437 } 1438 } else if (recv_cq) { 1439 spin_lock_irq(&recv_cq->lock); 1440 __acquire(&send_cq->lock); 1441 } else { 1442 __acquire(&send_cq->lock); 1443 __acquire(&recv_cq->lock); 1444 } 1445 } 1446 1447 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1448 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1449 { 1450 if (send_cq) { 1451 if (recv_cq) { 1452 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1453 spin_unlock(&recv_cq->lock); 1454 spin_unlock_irq(&send_cq->lock); 1455 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1456 __release(&recv_cq->lock); 1457 spin_unlock_irq(&send_cq->lock); 1458 } else { 1459 spin_unlock(&send_cq->lock); 1460 spin_unlock_irq(&recv_cq->lock); 1461 } 1462 } else { 1463 __release(&recv_cq->lock); 1464 spin_unlock_irq(&send_cq->lock); 1465 } 1466 } else if (recv_cq) { 1467 __release(&send_cq->lock); 1468 spin_unlock_irq(&recv_cq->lock); 1469 } else { 1470 __release(&recv_cq->lock); 1471 __release(&send_cq->lock); 1472 } 1473 } 1474 1475 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1476 { 1477 return to_mpd(qp->ibqp.pd); 1478 } 1479 1480 static void get_cqs(struct mlx5_ib_qp *qp, 1481 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1482 { 1483 switch (qp->ibqp.qp_type) { 1484 case IB_QPT_XRC_TGT: 1485 *send_cq = NULL; 1486 *recv_cq = NULL; 1487 break; 1488 case MLX5_IB_QPT_REG_UMR: 1489 case IB_QPT_XRC_INI: 1490 *send_cq = to_mcq(qp->ibqp.send_cq); 1491 *recv_cq = NULL; 1492 break; 1493 1494 case IB_QPT_SMI: 1495 case IB_QPT_GSI: 1496 case IB_QPT_RC: 1497 case IB_QPT_UC: 1498 case IB_QPT_UD: 1499 case IB_QPT_RAW_IPV6: 1500 case IB_QPT_RAW_ETHERTYPE: 1501 case IB_QPT_RAW_PACKET: 1502 *send_cq = to_mcq(qp->ibqp.send_cq); 1503 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1504 break; 1505 1506 case IB_QPT_MAX: 1507 default: 1508 *send_cq = NULL; 1509 *recv_cq = NULL; 1510 break; 1511 } 1512 } 1513 1514 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1515 u16 operation); 1516 1517 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1518 { 1519 struct mlx5_ib_cq *send_cq, *recv_cq; 1520 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1521 struct mlx5_modify_qp_mbox_in *in; 1522 int err; 1523 1524 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 1525 &qp->raw_packet_qp.rq.base : 1526 &qp->trans_qp.base; 1527 1528 in = kzalloc(sizeof(*in), GFP_KERNEL); 1529 if (!in) 1530 return; 1531 1532 if (qp->state != IB_QPS_RESET) { 1533 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 1534 mlx5_ib_qp_disable_pagefaults(qp); 1535 err = mlx5_core_qp_modify(dev->mdev, 1536 MLX5_CMD_OP_2RST_QP, in, 0, 1537 &base->mqp); 1538 } else { 1539 err = modify_raw_packet_qp(dev, qp, 1540 MLX5_CMD_OP_2RST_QP); 1541 } 1542 if (err) 1543 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1544 base->mqp.qpn); 1545 } 1546 1547 get_cqs(qp, &send_cq, &recv_cq); 1548 1549 if (qp->create_type == MLX5_QP_KERNEL) { 1550 mlx5_ib_lock_cqs(send_cq, recv_cq); 1551 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 1552 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1553 if (send_cq != recv_cq) 1554 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 1555 NULL); 1556 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1557 } 1558 1559 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1560 destroy_raw_packet_qp(dev, qp); 1561 } else { 1562 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 1563 if (err) 1564 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 1565 base->mqp.qpn); 1566 } 1567 1568 kfree(in); 1569 1570 if (qp->create_type == MLX5_QP_KERNEL) 1571 destroy_qp_kernel(dev, qp); 1572 else if (qp->create_type == MLX5_QP_USER) 1573 destroy_qp_user(&get_pd(qp)->ibpd, qp, base); 1574 } 1575 1576 static const char *ib_qp_type_str(enum ib_qp_type type) 1577 { 1578 switch (type) { 1579 case IB_QPT_SMI: 1580 return "IB_QPT_SMI"; 1581 case IB_QPT_GSI: 1582 return "IB_QPT_GSI"; 1583 case IB_QPT_RC: 1584 return "IB_QPT_RC"; 1585 case IB_QPT_UC: 1586 return "IB_QPT_UC"; 1587 case IB_QPT_UD: 1588 return "IB_QPT_UD"; 1589 case IB_QPT_RAW_IPV6: 1590 return "IB_QPT_RAW_IPV6"; 1591 case IB_QPT_RAW_ETHERTYPE: 1592 return "IB_QPT_RAW_ETHERTYPE"; 1593 case IB_QPT_XRC_INI: 1594 return "IB_QPT_XRC_INI"; 1595 case IB_QPT_XRC_TGT: 1596 return "IB_QPT_XRC_TGT"; 1597 case IB_QPT_RAW_PACKET: 1598 return "IB_QPT_RAW_PACKET"; 1599 case MLX5_IB_QPT_REG_UMR: 1600 return "MLX5_IB_QPT_REG_UMR"; 1601 case IB_QPT_MAX: 1602 default: 1603 return "Invalid QP type"; 1604 } 1605 } 1606 1607 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1608 struct ib_qp_init_attr *init_attr, 1609 struct ib_udata *udata) 1610 { 1611 struct mlx5_ib_dev *dev; 1612 struct mlx5_ib_qp *qp; 1613 u16 xrcdn = 0; 1614 int err; 1615 1616 if (pd) { 1617 dev = to_mdev(pd->device); 1618 } else { 1619 /* being cautious here */ 1620 if (init_attr->qp_type != IB_QPT_XRC_TGT && 1621 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 1622 pr_warn("%s: no PD for transport %s\n", __func__, 1623 ib_qp_type_str(init_attr->qp_type)); 1624 return ERR_PTR(-EINVAL); 1625 } 1626 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 1627 1628 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1629 if (!pd->uobject) { 1630 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 1631 return ERR_PTR(-EINVAL); 1632 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 1633 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 1634 return ERR_PTR(-EINVAL); 1635 } 1636 } 1637 } 1638 1639 switch (init_attr->qp_type) { 1640 case IB_QPT_XRC_TGT: 1641 case IB_QPT_XRC_INI: 1642 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 1643 mlx5_ib_dbg(dev, "XRC not supported\n"); 1644 return ERR_PTR(-ENOSYS); 1645 } 1646 init_attr->recv_cq = NULL; 1647 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 1648 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1649 init_attr->send_cq = NULL; 1650 } 1651 1652 /* fall through */ 1653 case IB_QPT_RAW_PACKET: 1654 case IB_QPT_RC: 1655 case IB_QPT_UC: 1656 case IB_QPT_UD: 1657 case IB_QPT_SMI: 1658 case IB_QPT_GSI: 1659 case MLX5_IB_QPT_REG_UMR: 1660 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1661 if (!qp) 1662 return ERR_PTR(-ENOMEM); 1663 1664 err = create_qp_common(dev, pd, init_attr, udata, qp); 1665 if (err) { 1666 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 1667 kfree(qp); 1668 return ERR_PTR(err); 1669 } 1670 1671 if (is_qp0(init_attr->qp_type)) 1672 qp->ibqp.qp_num = 0; 1673 else if (is_qp1(init_attr->qp_type)) 1674 qp->ibqp.qp_num = 1; 1675 else 1676 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 1677 1678 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 1679 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 1680 to_mcq(init_attr->recv_cq)->mcq.cqn, 1681 to_mcq(init_attr->send_cq)->mcq.cqn); 1682 1683 qp->trans_qp.xrcdn = xrcdn; 1684 1685 break; 1686 1687 case IB_QPT_RAW_IPV6: 1688 case IB_QPT_RAW_ETHERTYPE: 1689 case IB_QPT_MAX: 1690 default: 1691 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 1692 init_attr->qp_type); 1693 /* Don't support raw QPs */ 1694 return ERR_PTR(-EINVAL); 1695 } 1696 1697 return &qp->ibqp; 1698 } 1699 1700 int mlx5_ib_destroy_qp(struct ib_qp *qp) 1701 { 1702 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1703 struct mlx5_ib_qp *mqp = to_mqp(qp); 1704 1705 destroy_qp_common(dev, mqp); 1706 1707 kfree(mqp); 1708 1709 return 0; 1710 } 1711 1712 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 1713 int attr_mask) 1714 { 1715 u32 hw_access_flags = 0; 1716 u8 dest_rd_atomic; 1717 u32 access_flags; 1718 1719 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1720 dest_rd_atomic = attr->max_dest_rd_atomic; 1721 else 1722 dest_rd_atomic = qp->trans_qp.resp_depth; 1723 1724 if (attr_mask & IB_QP_ACCESS_FLAGS) 1725 access_flags = attr->qp_access_flags; 1726 else 1727 access_flags = qp->trans_qp.atomic_rd_en; 1728 1729 if (!dest_rd_atomic) 1730 access_flags &= IB_ACCESS_REMOTE_WRITE; 1731 1732 if (access_flags & IB_ACCESS_REMOTE_READ) 1733 hw_access_flags |= MLX5_QP_BIT_RRE; 1734 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1735 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 1736 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1737 hw_access_flags |= MLX5_QP_BIT_RWE; 1738 1739 return cpu_to_be32(hw_access_flags); 1740 } 1741 1742 enum { 1743 MLX5_PATH_FLAG_FL = 1 << 0, 1744 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 1745 MLX5_PATH_FLAG_COUNTER = 1 << 2, 1746 }; 1747 1748 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 1749 { 1750 if (rate == IB_RATE_PORT_CURRENT) { 1751 return 0; 1752 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 1753 return -EINVAL; 1754 } else { 1755 while (rate != IB_RATE_2_5_GBPS && 1756 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 1757 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 1758 --rate; 1759 } 1760 1761 return rate + MLX5_STAT_RATE_OFFSET; 1762 } 1763 1764 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 1765 struct mlx5_ib_sq *sq, u8 sl) 1766 { 1767 void *in; 1768 void *tisc; 1769 int inlen; 1770 int err; 1771 1772 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 1773 in = mlx5_vzalloc(inlen); 1774 if (!in) 1775 return -ENOMEM; 1776 1777 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 1778 1779 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 1780 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 1781 1782 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 1783 1784 kvfree(in); 1785 1786 return err; 1787 } 1788 1789 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1790 const struct ib_ah_attr *ah, 1791 struct mlx5_qp_path *path, u8 port, int attr_mask, 1792 u32 path_flags, const struct ib_qp_attr *attr) 1793 { 1794 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 1795 int err; 1796 1797 if (attr_mask & IB_QP_PKEY_INDEX) 1798 path->pkey_index = attr->pkey_index; 1799 1800 if (ah->ah_flags & IB_AH_GRH) { 1801 if (ah->grh.sgid_index >= 1802 dev->mdev->port_caps[port - 1].gid_table_len) { 1803 pr_err("sgid_index (%u) too large. max is %d\n", 1804 ah->grh.sgid_index, 1805 dev->mdev->port_caps[port - 1].gid_table_len); 1806 return -EINVAL; 1807 } 1808 } 1809 1810 if (ll == IB_LINK_LAYER_ETHERNET) { 1811 if (!(ah->ah_flags & IB_AH_GRH)) 1812 return -EINVAL; 1813 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 1814 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 1815 ah->grh.sgid_index); 1816 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 1817 } else { 1818 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 1819 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 1820 0; 1821 path->rlid = cpu_to_be16(ah->dlid); 1822 path->grh_mlid = ah->src_path_bits & 0x7f; 1823 if (ah->ah_flags & IB_AH_GRH) 1824 path->grh_mlid |= 1 << 7; 1825 path->dci_cfi_prio_sl = ah->sl & 0xf; 1826 } 1827 1828 if (ah->ah_flags & IB_AH_GRH) { 1829 path->mgid_index = ah->grh.sgid_index; 1830 path->hop_limit = ah->grh.hop_limit; 1831 path->tclass_flowlabel = 1832 cpu_to_be32((ah->grh.traffic_class << 20) | 1833 (ah->grh.flow_label)); 1834 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1835 } 1836 1837 err = ib_rate_to_mlx5(dev, ah->static_rate); 1838 if (err < 0) 1839 return err; 1840 path->static_rate = err; 1841 path->port = port; 1842 1843 if (attr_mask & IB_QP_TIMEOUT) 1844 path->ackto_lt = attr->timeout << 3; 1845 1846 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 1847 return modify_raw_packet_eth_prio(dev->mdev, 1848 &qp->raw_packet_qp.sq, 1849 ah->sl & 0xf); 1850 1851 return 0; 1852 } 1853 1854 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 1855 [MLX5_QP_STATE_INIT] = { 1856 [MLX5_QP_STATE_INIT] = { 1857 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1858 MLX5_QP_OPTPAR_RAE | 1859 MLX5_QP_OPTPAR_RWE | 1860 MLX5_QP_OPTPAR_PKEY_INDEX | 1861 MLX5_QP_OPTPAR_PRI_PORT, 1862 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1863 MLX5_QP_OPTPAR_PKEY_INDEX | 1864 MLX5_QP_OPTPAR_PRI_PORT, 1865 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1866 MLX5_QP_OPTPAR_Q_KEY | 1867 MLX5_QP_OPTPAR_PRI_PORT, 1868 }, 1869 [MLX5_QP_STATE_RTR] = { 1870 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1871 MLX5_QP_OPTPAR_RRE | 1872 MLX5_QP_OPTPAR_RAE | 1873 MLX5_QP_OPTPAR_RWE | 1874 MLX5_QP_OPTPAR_PKEY_INDEX, 1875 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1876 MLX5_QP_OPTPAR_RWE | 1877 MLX5_QP_OPTPAR_PKEY_INDEX, 1878 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1879 MLX5_QP_OPTPAR_Q_KEY, 1880 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 1881 MLX5_QP_OPTPAR_Q_KEY, 1882 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1883 MLX5_QP_OPTPAR_RRE | 1884 MLX5_QP_OPTPAR_RAE | 1885 MLX5_QP_OPTPAR_RWE | 1886 MLX5_QP_OPTPAR_PKEY_INDEX, 1887 }, 1888 }, 1889 [MLX5_QP_STATE_RTR] = { 1890 [MLX5_QP_STATE_RTS] = { 1891 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1892 MLX5_QP_OPTPAR_RRE | 1893 MLX5_QP_OPTPAR_RAE | 1894 MLX5_QP_OPTPAR_RWE | 1895 MLX5_QP_OPTPAR_PM_STATE | 1896 MLX5_QP_OPTPAR_RNR_TIMEOUT, 1897 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1898 MLX5_QP_OPTPAR_RWE | 1899 MLX5_QP_OPTPAR_PM_STATE, 1900 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1901 }, 1902 }, 1903 [MLX5_QP_STATE_RTS] = { 1904 [MLX5_QP_STATE_RTS] = { 1905 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1906 MLX5_QP_OPTPAR_RAE | 1907 MLX5_QP_OPTPAR_RWE | 1908 MLX5_QP_OPTPAR_RNR_TIMEOUT | 1909 MLX5_QP_OPTPAR_PM_STATE | 1910 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1911 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1912 MLX5_QP_OPTPAR_PM_STATE | 1913 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1914 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 1915 MLX5_QP_OPTPAR_SRQN | 1916 MLX5_QP_OPTPAR_CQN_RCV, 1917 }, 1918 }, 1919 [MLX5_QP_STATE_SQER] = { 1920 [MLX5_QP_STATE_RTS] = { 1921 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1922 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 1923 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 1924 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 1925 MLX5_QP_OPTPAR_RWE | 1926 MLX5_QP_OPTPAR_RAE | 1927 MLX5_QP_OPTPAR_RRE, 1928 }, 1929 }, 1930 }; 1931 1932 static int ib_nr_to_mlx5_nr(int ib_mask) 1933 { 1934 switch (ib_mask) { 1935 case IB_QP_STATE: 1936 return 0; 1937 case IB_QP_CUR_STATE: 1938 return 0; 1939 case IB_QP_EN_SQD_ASYNC_NOTIFY: 1940 return 0; 1941 case IB_QP_ACCESS_FLAGS: 1942 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 1943 MLX5_QP_OPTPAR_RAE; 1944 case IB_QP_PKEY_INDEX: 1945 return MLX5_QP_OPTPAR_PKEY_INDEX; 1946 case IB_QP_PORT: 1947 return MLX5_QP_OPTPAR_PRI_PORT; 1948 case IB_QP_QKEY: 1949 return MLX5_QP_OPTPAR_Q_KEY; 1950 case IB_QP_AV: 1951 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 1952 MLX5_QP_OPTPAR_PRI_PORT; 1953 case IB_QP_PATH_MTU: 1954 return 0; 1955 case IB_QP_TIMEOUT: 1956 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 1957 case IB_QP_RETRY_CNT: 1958 return MLX5_QP_OPTPAR_RETRY_COUNT; 1959 case IB_QP_RNR_RETRY: 1960 return MLX5_QP_OPTPAR_RNR_RETRY; 1961 case IB_QP_RQ_PSN: 1962 return 0; 1963 case IB_QP_MAX_QP_RD_ATOMIC: 1964 return MLX5_QP_OPTPAR_SRA_MAX; 1965 case IB_QP_ALT_PATH: 1966 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 1967 case IB_QP_MIN_RNR_TIMER: 1968 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 1969 case IB_QP_SQ_PSN: 1970 return 0; 1971 case IB_QP_MAX_DEST_RD_ATOMIC: 1972 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 1973 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 1974 case IB_QP_PATH_MIG_STATE: 1975 return MLX5_QP_OPTPAR_PM_STATE; 1976 case IB_QP_CAP: 1977 return 0; 1978 case IB_QP_DEST_QPN: 1979 return 0; 1980 } 1981 return 0; 1982 } 1983 1984 static int ib_mask_to_mlx5_opt(int ib_mask) 1985 { 1986 int result = 0; 1987 int i; 1988 1989 for (i = 0; i < 8 * sizeof(int); i++) { 1990 if ((1 << i) & ib_mask) 1991 result |= ib_nr_to_mlx5_nr(1 << i); 1992 } 1993 1994 return result; 1995 } 1996 1997 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev, 1998 struct mlx5_ib_rq *rq, int new_state) 1999 { 2000 void *in; 2001 void *rqc; 2002 int inlen; 2003 int err; 2004 2005 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2006 in = mlx5_vzalloc(inlen); 2007 if (!in) 2008 return -ENOMEM; 2009 2010 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2011 2012 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2013 MLX5_SET(rqc, rqc, state, new_state); 2014 2015 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen); 2016 if (err) 2017 goto out; 2018 2019 rq->state = new_state; 2020 2021 out: 2022 kvfree(in); 2023 return err; 2024 } 2025 2026 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2027 struct mlx5_ib_sq *sq, int new_state) 2028 { 2029 void *in; 2030 void *sqc; 2031 int inlen; 2032 int err; 2033 2034 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2035 in = mlx5_vzalloc(inlen); 2036 if (!in) 2037 return -ENOMEM; 2038 2039 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2040 2041 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2042 MLX5_SET(sqc, sqc, state, new_state); 2043 2044 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2045 if (err) 2046 goto out; 2047 2048 sq->state = new_state; 2049 2050 out: 2051 kvfree(in); 2052 return err; 2053 } 2054 2055 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2056 u16 operation) 2057 { 2058 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2059 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2060 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2061 int rq_state; 2062 int sq_state; 2063 int err; 2064 2065 switch (operation) { 2066 case MLX5_CMD_OP_RST2INIT_QP: 2067 rq_state = MLX5_RQC_STATE_RDY; 2068 sq_state = MLX5_SQC_STATE_RDY; 2069 break; 2070 case MLX5_CMD_OP_2ERR_QP: 2071 rq_state = MLX5_RQC_STATE_ERR; 2072 sq_state = MLX5_SQC_STATE_ERR; 2073 break; 2074 case MLX5_CMD_OP_2RST_QP: 2075 rq_state = MLX5_RQC_STATE_RST; 2076 sq_state = MLX5_SQC_STATE_RST; 2077 break; 2078 case MLX5_CMD_OP_INIT2INIT_QP: 2079 case MLX5_CMD_OP_INIT2RTR_QP: 2080 case MLX5_CMD_OP_RTR2RTS_QP: 2081 case MLX5_CMD_OP_RTS2RTS_QP: 2082 /* Nothing to do here... */ 2083 return 0; 2084 default: 2085 WARN_ON(1); 2086 return -EINVAL; 2087 } 2088 2089 if (qp->rq.wqe_cnt) { 2090 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state); 2091 if (err) 2092 return err; 2093 } 2094 2095 if (qp->sq.wqe_cnt) 2096 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state); 2097 2098 return 0; 2099 } 2100 2101 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2102 const struct ib_qp_attr *attr, int attr_mask, 2103 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2104 { 2105 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2106 [MLX5_QP_STATE_RST] = { 2107 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2108 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2109 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2110 }, 2111 [MLX5_QP_STATE_INIT] = { 2112 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2113 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2114 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2115 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2116 }, 2117 [MLX5_QP_STATE_RTR] = { 2118 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2119 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2120 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2121 }, 2122 [MLX5_QP_STATE_RTS] = { 2123 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2124 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2125 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2126 }, 2127 [MLX5_QP_STATE_SQD] = { 2128 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2129 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2130 }, 2131 [MLX5_QP_STATE_SQER] = { 2132 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2133 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2134 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2135 }, 2136 [MLX5_QP_STATE_ERR] = { 2137 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2138 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2139 } 2140 }; 2141 2142 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2143 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2144 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2145 struct mlx5_ib_cq *send_cq, *recv_cq; 2146 struct mlx5_qp_context *context; 2147 struct mlx5_modify_qp_mbox_in *in; 2148 struct mlx5_ib_pd *pd; 2149 enum mlx5_qp_state mlx5_cur, mlx5_new; 2150 enum mlx5_qp_optpar optpar; 2151 int sqd_event; 2152 int mlx5_st; 2153 int err; 2154 u16 op; 2155 2156 in = kzalloc(sizeof(*in), GFP_KERNEL); 2157 if (!in) 2158 return -ENOMEM; 2159 2160 context = &in->ctx; 2161 err = to_mlx5_st(ibqp->qp_type); 2162 if (err < 0) 2163 goto out; 2164 2165 context->flags = cpu_to_be32(err << 16); 2166 2167 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2168 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2169 } else { 2170 switch (attr->path_mig_state) { 2171 case IB_MIG_MIGRATED: 2172 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2173 break; 2174 case IB_MIG_REARM: 2175 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2176 break; 2177 case IB_MIG_ARMED: 2178 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2179 break; 2180 } 2181 } 2182 2183 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) { 2184 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2185 } else if (ibqp->qp_type == IB_QPT_UD || 2186 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2187 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2188 } else if (attr_mask & IB_QP_PATH_MTU) { 2189 if (attr->path_mtu < IB_MTU_256 || 2190 attr->path_mtu > IB_MTU_4096) { 2191 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2192 err = -EINVAL; 2193 goto out; 2194 } 2195 context->mtu_msgmax = (attr->path_mtu << 5) | 2196 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2197 } 2198 2199 if (attr_mask & IB_QP_DEST_QPN) 2200 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2201 2202 if (attr_mask & IB_QP_PKEY_INDEX) 2203 context->pri_path.pkey_index = attr->pkey_index; 2204 2205 /* todo implement counter_index functionality */ 2206 2207 if (is_sqp(ibqp->qp_type)) 2208 context->pri_path.port = qp->port; 2209 2210 if (attr_mask & IB_QP_PORT) 2211 context->pri_path.port = attr->port_num; 2212 2213 if (attr_mask & IB_QP_AV) { 2214 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2215 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2216 attr_mask, 0, attr); 2217 if (err) 2218 goto out; 2219 } 2220 2221 if (attr_mask & IB_QP_TIMEOUT) 2222 context->pri_path.ackto_lt |= attr->timeout << 3; 2223 2224 if (attr_mask & IB_QP_ALT_PATH) { 2225 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2226 &context->alt_path, 2227 attr->alt_port_num, attr_mask, 0, attr); 2228 if (err) 2229 goto out; 2230 } 2231 2232 pd = get_pd(qp); 2233 get_cqs(qp, &send_cq, &recv_cq); 2234 2235 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2236 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2237 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2238 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2239 2240 if (attr_mask & IB_QP_RNR_RETRY) 2241 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2242 2243 if (attr_mask & IB_QP_RETRY_CNT) 2244 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2245 2246 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2247 if (attr->max_rd_atomic) 2248 context->params1 |= 2249 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2250 } 2251 2252 if (attr_mask & IB_QP_SQ_PSN) 2253 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2254 2255 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2256 if (attr->max_dest_rd_atomic) 2257 context->params2 |= 2258 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2259 } 2260 2261 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2262 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2263 2264 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2265 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2266 2267 if (attr_mask & IB_QP_RQ_PSN) 2268 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2269 2270 if (attr_mask & IB_QP_QKEY) 2271 context->qkey = cpu_to_be32(attr->qkey); 2272 2273 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2274 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2275 2276 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2277 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2278 sqd_event = 1; 2279 else 2280 sqd_event = 0; 2281 2282 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2283 context->sq_crq_size |= cpu_to_be16(1 << 4); 2284 2285 2286 mlx5_cur = to_mlx5_state(cur_state); 2287 mlx5_new = to_mlx5_state(new_state); 2288 mlx5_st = to_mlx5_st(ibqp->qp_type); 2289 if (mlx5_st < 0) 2290 goto out; 2291 2292 /* If moving to a reset or error state, we must disable page faults on 2293 * this QP and flush all current page faults. Otherwise a stale page 2294 * fault may attempt to work on this QP after it is reset and moved 2295 * again to RTS, and may cause the driver and the device to get out of 2296 * sync. */ 2297 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2298 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2299 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2300 mlx5_ib_qp_disable_pagefaults(qp); 2301 2302 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2303 !optab[mlx5_cur][mlx5_new]) 2304 goto out; 2305 2306 op = optab[mlx5_cur][mlx5_new]; 2307 optpar = ib_mask_to_mlx5_opt(attr_mask); 2308 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2309 in->optparam = cpu_to_be32(optpar); 2310 2311 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) 2312 err = modify_raw_packet_qp(dev, qp, op); 2313 else 2314 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event, 2315 &base->mqp); 2316 if (err) 2317 goto out; 2318 2319 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2320 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2321 mlx5_ib_qp_enable_pagefaults(qp); 2322 2323 qp->state = new_state; 2324 2325 if (attr_mask & IB_QP_ACCESS_FLAGS) 2326 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2327 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2328 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2329 if (attr_mask & IB_QP_PORT) 2330 qp->port = attr->port_num; 2331 if (attr_mask & IB_QP_ALT_PATH) 2332 qp->trans_qp.alt_port = attr->alt_port_num; 2333 2334 /* 2335 * If we moved a kernel QP to RESET, clean up all old CQ 2336 * entries and reinitialize the QP. 2337 */ 2338 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2339 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2340 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2341 if (send_cq != recv_cq) 2342 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2343 2344 qp->rq.head = 0; 2345 qp->rq.tail = 0; 2346 qp->sq.head = 0; 2347 qp->sq.tail = 0; 2348 qp->sq.cur_post = 0; 2349 qp->sq.last_poll = 0; 2350 qp->db.db[MLX5_RCV_DBR] = 0; 2351 qp->db.db[MLX5_SND_DBR] = 0; 2352 } 2353 2354 out: 2355 kfree(in); 2356 return err; 2357 } 2358 2359 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2360 int attr_mask, struct ib_udata *udata) 2361 { 2362 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2363 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2364 enum ib_qp_state cur_state, new_state; 2365 int err = -EINVAL; 2366 int port; 2367 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2368 2369 mutex_lock(&qp->mutex); 2370 2371 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2372 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2373 2374 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 2375 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2376 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 2377 } 2378 2379 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR && 2380 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask, 2381 ll)) 2382 goto out; 2383 2384 if ((attr_mask & IB_QP_PORT) && 2385 (attr->port_num == 0 || 2386 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) 2387 goto out; 2388 2389 if (attr_mask & IB_QP_PKEY_INDEX) { 2390 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2391 if (attr->pkey_index >= 2392 dev->mdev->port_caps[port - 1].pkey_table_len) 2393 goto out; 2394 } 2395 2396 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2397 attr->max_rd_atomic > 2398 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) 2399 goto out; 2400 2401 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2402 attr->max_dest_rd_atomic > 2403 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) 2404 goto out; 2405 2406 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2407 err = 0; 2408 goto out; 2409 } 2410 2411 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2412 2413 out: 2414 mutex_unlock(&qp->mutex); 2415 return err; 2416 } 2417 2418 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2419 { 2420 struct mlx5_ib_cq *cq; 2421 unsigned cur; 2422 2423 cur = wq->head - wq->tail; 2424 if (likely(cur + nreq < wq->max_post)) 2425 return 0; 2426 2427 cq = to_mcq(ib_cq); 2428 spin_lock(&cq->lock); 2429 cur = wq->head - wq->tail; 2430 spin_unlock(&cq->lock); 2431 2432 return cur + nreq >= wq->max_post; 2433 } 2434 2435 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 2436 u64 remote_addr, u32 rkey) 2437 { 2438 rseg->raddr = cpu_to_be64(remote_addr); 2439 rseg->rkey = cpu_to_be32(rkey); 2440 rseg->reserved = 0; 2441 } 2442 2443 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 2444 struct ib_send_wr *wr) 2445 { 2446 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 2447 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 2448 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 2449 } 2450 2451 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 2452 { 2453 dseg->byte_count = cpu_to_be32(sg->length); 2454 dseg->lkey = cpu_to_be32(sg->lkey); 2455 dseg->addr = cpu_to_be64(sg->addr); 2456 } 2457 2458 static __be16 get_klm_octo(int npages) 2459 { 2460 return cpu_to_be16(ALIGN(npages, 8) / 2); 2461 } 2462 2463 static __be64 frwr_mkey_mask(void) 2464 { 2465 u64 result; 2466 2467 result = MLX5_MKEY_MASK_LEN | 2468 MLX5_MKEY_MASK_PAGE_SIZE | 2469 MLX5_MKEY_MASK_START_ADDR | 2470 MLX5_MKEY_MASK_EN_RINVAL | 2471 MLX5_MKEY_MASK_KEY | 2472 MLX5_MKEY_MASK_LR | 2473 MLX5_MKEY_MASK_LW | 2474 MLX5_MKEY_MASK_RR | 2475 MLX5_MKEY_MASK_RW | 2476 MLX5_MKEY_MASK_A | 2477 MLX5_MKEY_MASK_SMALL_FENCE | 2478 MLX5_MKEY_MASK_FREE; 2479 2480 return cpu_to_be64(result); 2481 } 2482 2483 static __be64 sig_mkey_mask(void) 2484 { 2485 u64 result; 2486 2487 result = MLX5_MKEY_MASK_LEN | 2488 MLX5_MKEY_MASK_PAGE_SIZE | 2489 MLX5_MKEY_MASK_START_ADDR | 2490 MLX5_MKEY_MASK_EN_SIGERR | 2491 MLX5_MKEY_MASK_EN_RINVAL | 2492 MLX5_MKEY_MASK_KEY | 2493 MLX5_MKEY_MASK_LR | 2494 MLX5_MKEY_MASK_LW | 2495 MLX5_MKEY_MASK_RR | 2496 MLX5_MKEY_MASK_RW | 2497 MLX5_MKEY_MASK_SMALL_FENCE | 2498 MLX5_MKEY_MASK_FREE | 2499 MLX5_MKEY_MASK_BSF_EN; 2500 2501 return cpu_to_be64(result); 2502 } 2503 2504 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 2505 struct mlx5_ib_mr *mr) 2506 { 2507 int ndescs = mr->ndescs; 2508 2509 memset(umr, 0, sizeof(*umr)); 2510 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 2511 umr->klm_octowords = get_klm_octo(ndescs); 2512 umr->mkey_mask = frwr_mkey_mask(); 2513 } 2514 2515 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 2516 { 2517 memset(umr, 0, sizeof(*umr)); 2518 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 2519 umr->flags = 1 << 7; 2520 } 2521 2522 static __be64 get_umr_reg_mr_mask(void) 2523 { 2524 u64 result; 2525 2526 result = MLX5_MKEY_MASK_LEN | 2527 MLX5_MKEY_MASK_PAGE_SIZE | 2528 MLX5_MKEY_MASK_START_ADDR | 2529 MLX5_MKEY_MASK_PD | 2530 MLX5_MKEY_MASK_LR | 2531 MLX5_MKEY_MASK_LW | 2532 MLX5_MKEY_MASK_KEY | 2533 MLX5_MKEY_MASK_RR | 2534 MLX5_MKEY_MASK_RW | 2535 MLX5_MKEY_MASK_A | 2536 MLX5_MKEY_MASK_FREE; 2537 2538 return cpu_to_be64(result); 2539 } 2540 2541 static __be64 get_umr_unreg_mr_mask(void) 2542 { 2543 u64 result; 2544 2545 result = MLX5_MKEY_MASK_FREE; 2546 2547 return cpu_to_be64(result); 2548 } 2549 2550 static __be64 get_umr_update_mtt_mask(void) 2551 { 2552 u64 result; 2553 2554 result = MLX5_MKEY_MASK_FREE; 2555 2556 return cpu_to_be64(result); 2557 } 2558 2559 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 2560 struct ib_send_wr *wr) 2561 { 2562 struct mlx5_umr_wr *umrwr = umr_wr(wr); 2563 2564 memset(umr, 0, sizeof(*umr)); 2565 2566 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 2567 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 2568 else 2569 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 2570 2571 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 2572 umr->klm_octowords = get_klm_octo(umrwr->npages); 2573 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 2574 umr->mkey_mask = get_umr_update_mtt_mask(); 2575 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 2576 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 2577 } else { 2578 umr->mkey_mask = get_umr_reg_mr_mask(); 2579 } 2580 } else { 2581 umr->mkey_mask = get_umr_unreg_mr_mask(); 2582 } 2583 2584 if (!wr->num_sge) 2585 umr->flags |= MLX5_UMR_INLINE; 2586 } 2587 2588 static u8 get_umr_flags(int acc) 2589 { 2590 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 2591 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 2592 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 2593 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 2594 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 2595 } 2596 2597 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 2598 struct mlx5_ib_mr *mr, 2599 u32 key, int access) 2600 { 2601 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 2602 2603 memset(seg, 0, sizeof(*seg)); 2604 seg->flags = get_umr_flags(access) | MLX5_ACCESS_MODE_MTT; 2605 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 2606 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 2607 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 2608 seg->len = cpu_to_be64(mr->ibmr.length); 2609 seg->xlt_oct_size = cpu_to_be32(ndescs); 2610 seg->log2_page_size = ilog2(mr->ibmr.page_size); 2611 } 2612 2613 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 2614 { 2615 memset(seg, 0, sizeof(*seg)); 2616 seg->status = MLX5_MKEY_STATUS_FREE; 2617 } 2618 2619 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 2620 { 2621 struct mlx5_umr_wr *umrwr = umr_wr(wr); 2622 2623 memset(seg, 0, sizeof(*seg)); 2624 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 2625 seg->status = MLX5_MKEY_STATUS_FREE; 2626 return; 2627 } 2628 2629 seg->flags = convert_access(umrwr->access_flags); 2630 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 2631 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 2632 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 2633 } 2634 seg->len = cpu_to_be64(umrwr->length); 2635 seg->log2_page_size = umrwr->page_shift; 2636 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 2637 mlx5_mkey_variant(umrwr->mkey)); 2638 } 2639 2640 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 2641 struct mlx5_ib_mr *mr, 2642 struct mlx5_ib_pd *pd) 2643 { 2644 int bcount = mr->desc_size * mr->ndescs; 2645 2646 dseg->addr = cpu_to_be64(mr->desc_map); 2647 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 2648 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 2649 } 2650 2651 static __be32 send_ieth(struct ib_send_wr *wr) 2652 { 2653 switch (wr->opcode) { 2654 case IB_WR_SEND_WITH_IMM: 2655 case IB_WR_RDMA_WRITE_WITH_IMM: 2656 return wr->ex.imm_data; 2657 2658 case IB_WR_SEND_WITH_INV: 2659 return cpu_to_be32(wr->ex.invalidate_rkey); 2660 2661 default: 2662 return 0; 2663 } 2664 } 2665 2666 static u8 calc_sig(void *wqe, int size) 2667 { 2668 u8 *p = wqe; 2669 u8 res = 0; 2670 int i; 2671 2672 for (i = 0; i < size; i++) 2673 res ^= p[i]; 2674 2675 return ~res; 2676 } 2677 2678 static u8 wq_sig(void *wqe) 2679 { 2680 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 2681 } 2682 2683 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 2684 void *wqe, int *sz) 2685 { 2686 struct mlx5_wqe_inline_seg *seg; 2687 void *qend = qp->sq.qend; 2688 void *addr; 2689 int inl = 0; 2690 int copy; 2691 int len; 2692 int i; 2693 2694 seg = wqe; 2695 wqe += sizeof(*seg); 2696 for (i = 0; i < wr->num_sge; i++) { 2697 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 2698 len = wr->sg_list[i].length; 2699 inl += len; 2700 2701 if (unlikely(inl > qp->max_inline_data)) 2702 return -ENOMEM; 2703 2704 if (unlikely(wqe + len > qend)) { 2705 copy = qend - wqe; 2706 memcpy(wqe, addr, copy); 2707 addr += copy; 2708 len -= copy; 2709 wqe = mlx5_get_send_wqe(qp, 0); 2710 } 2711 memcpy(wqe, addr, len); 2712 wqe += len; 2713 } 2714 2715 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 2716 2717 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 2718 2719 return 0; 2720 } 2721 2722 static u16 prot_field_size(enum ib_signature_type type) 2723 { 2724 switch (type) { 2725 case IB_SIG_TYPE_T10_DIF: 2726 return MLX5_DIF_SIZE; 2727 default: 2728 return 0; 2729 } 2730 } 2731 2732 static u8 bs_selector(int block_size) 2733 { 2734 switch (block_size) { 2735 case 512: return 0x1; 2736 case 520: return 0x2; 2737 case 4096: return 0x3; 2738 case 4160: return 0x4; 2739 case 1073741824: return 0x5; 2740 default: return 0; 2741 } 2742 } 2743 2744 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 2745 struct mlx5_bsf_inl *inl) 2746 { 2747 /* Valid inline section and allow BSF refresh */ 2748 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 2749 MLX5_BSF_REFRESH_DIF); 2750 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 2751 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 2752 /* repeating block */ 2753 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 2754 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 2755 MLX5_DIF_CRC : MLX5_DIF_IPCS; 2756 2757 if (domain->sig.dif.ref_remap) 2758 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 2759 2760 if (domain->sig.dif.app_escape) { 2761 if (domain->sig.dif.ref_escape) 2762 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 2763 else 2764 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 2765 } 2766 2767 inl->dif_app_bitmask_check = 2768 cpu_to_be16(domain->sig.dif.apptag_check_mask); 2769 } 2770 2771 static int mlx5_set_bsf(struct ib_mr *sig_mr, 2772 struct ib_sig_attrs *sig_attrs, 2773 struct mlx5_bsf *bsf, u32 data_size) 2774 { 2775 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 2776 struct mlx5_bsf_basic *basic = &bsf->basic; 2777 struct ib_sig_domain *mem = &sig_attrs->mem; 2778 struct ib_sig_domain *wire = &sig_attrs->wire; 2779 2780 memset(bsf, 0, sizeof(*bsf)); 2781 2782 /* Basic + Extended + Inline */ 2783 basic->bsf_size_sbs = 1 << 7; 2784 /* Input domain check byte mask */ 2785 basic->check_byte_mask = sig_attrs->check_mask; 2786 basic->raw_data_size = cpu_to_be32(data_size); 2787 2788 /* Memory domain */ 2789 switch (sig_attrs->mem.sig_type) { 2790 case IB_SIG_TYPE_NONE: 2791 break; 2792 case IB_SIG_TYPE_T10_DIF: 2793 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 2794 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 2795 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 2796 break; 2797 default: 2798 return -EINVAL; 2799 } 2800 2801 /* Wire domain */ 2802 switch (sig_attrs->wire.sig_type) { 2803 case IB_SIG_TYPE_NONE: 2804 break; 2805 case IB_SIG_TYPE_T10_DIF: 2806 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 2807 mem->sig_type == wire->sig_type) { 2808 /* Same block structure */ 2809 basic->bsf_size_sbs |= 1 << 4; 2810 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 2811 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 2812 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 2813 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 2814 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 2815 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 2816 } else 2817 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 2818 2819 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 2820 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 2821 break; 2822 default: 2823 return -EINVAL; 2824 } 2825 2826 return 0; 2827 } 2828 2829 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 2830 struct mlx5_ib_qp *qp, void **seg, int *size) 2831 { 2832 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 2833 struct ib_mr *sig_mr = wr->sig_mr; 2834 struct mlx5_bsf *bsf; 2835 u32 data_len = wr->wr.sg_list->length; 2836 u32 data_key = wr->wr.sg_list->lkey; 2837 u64 data_va = wr->wr.sg_list->addr; 2838 int ret; 2839 int wqe_size; 2840 2841 if (!wr->prot || 2842 (data_key == wr->prot->lkey && 2843 data_va == wr->prot->addr && 2844 data_len == wr->prot->length)) { 2845 /** 2846 * Source domain doesn't contain signature information 2847 * or data and protection are interleaved in memory. 2848 * So need construct: 2849 * ------------------ 2850 * | data_klm | 2851 * ------------------ 2852 * | BSF | 2853 * ------------------ 2854 **/ 2855 struct mlx5_klm *data_klm = *seg; 2856 2857 data_klm->bcount = cpu_to_be32(data_len); 2858 data_klm->key = cpu_to_be32(data_key); 2859 data_klm->va = cpu_to_be64(data_va); 2860 wqe_size = ALIGN(sizeof(*data_klm), 64); 2861 } else { 2862 /** 2863 * Source domain contains signature information 2864 * So need construct a strided block format: 2865 * --------------------------- 2866 * | stride_block_ctrl | 2867 * --------------------------- 2868 * | data_klm | 2869 * --------------------------- 2870 * | prot_klm | 2871 * --------------------------- 2872 * | BSF | 2873 * --------------------------- 2874 **/ 2875 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 2876 struct mlx5_stride_block_entry *data_sentry; 2877 struct mlx5_stride_block_entry *prot_sentry; 2878 u32 prot_key = wr->prot->lkey; 2879 u64 prot_va = wr->prot->addr; 2880 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 2881 int prot_size; 2882 2883 sblock_ctrl = *seg; 2884 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 2885 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 2886 2887 prot_size = prot_field_size(sig_attrs->mem.sig_type); 2888 if (!prot_size) { 2889 pr_err("Bad block size given: %u\n", block_size); 2890 return -EINVAL; 2891 } 2892 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 2893 prot_size); 2894 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 2895 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 2896 sblock_ctrl->num_entries = cpu_to_be16(2); 2897 2898 data_sentry->bcount = cpu_to_be16(block_size); 2899 data_sentry->key = cpu_to_be32(data_key); 2900 data_sentry->va = cpu_to_be64(data_va); 2901 data_sentry->stride = cpu_to_be16(block_size); 2902 2903 prot_sentry->bcount = cpu_to_be16(prot_size); 2904 prot_sentry->key = cpu_to_be32(prot_key); 2905 prot_sentry->va = cpu_to_be64(prot_va); 2906 prot_sentry->stride = cpu_to_be16(prot_size); 2907 2908 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 2909 sizeof(*prot_sentry), 64); 2910 } 2911 2912 *seg += wqe_size; 2913 *size += wqe_size / 16; 2914 if (unlikely((*seg == qp->sq.qend))) 2915 *seg = mlx5_get_send_wqe(qp, 0); 2916 2917 bsf = *seg; 2918 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 2919 if (ret) 2920 return -EINVAL; 2921 2922 *seg += sizeof(*bsf); 2923 *size += sizeof(*bsf) / 16; 2924 if (unlikely((*seg == qp->sq.qend))) 2925 *seg = mlx5_get_send_wqe(qp, 0); 2926 2927 return 0; 2928 } 2929 2930 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 2931 struct ib_sig_handover_wr *wr, u32 nelements, 2932 u32 length, u32 pdn) 2933 { 2934 struct ib_mr *sig_mr = wr->sig_mr; 2935 u32 sig_key = sig_mr->rkey; 2936 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 2937 2938 memset(seg, 0, sizeof(*seg)); 2939 2940 seg->flags = get_umr_flags(wr->access_flags) | 2941 MLX5_ACCESS_MODE_KLM; 2942 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 2943 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 2944 MLX5_MKEY_BSF_EN | pdn); 2945 seg->len = cpu_to_be64(length); 2946 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 2947 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 2948 } 2949 2950 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 2951 u32 nelements) 2952 { 2953 memset(umr, 0, sizeof(*umr)); 2954 2955 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 2956 umr->klm_octowords = get_klm_octo(nelements); 2957 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 2958 umr->mkey_mask = sig_mkey_mask(); 2959 } 2960 2961 2962 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 2963 void **seg, int *size) 2964 { 2965 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 2966 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 2967 u32 pdn = get_pd(qp)->pdn; 2968 u32 klm_oct_size; 2969 int region_len, ret; 2970 2971 if (unlikely(wr->wr.num_sge != 1) || 2972 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 2973 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 2974 unlikely(!sig_mr->sig->sig_status_checked)) 2975 return -EINVAL; 2976 2977 /* length of the protected region, data + protection */ 2978 region_len = wr->wr.sg_list->length; 2979 if (wr->prot && 2980 (wr->prot->lkey != wr->wr.sg_list->lkey || 2981 wr->prot->addr != wr->wr.sg_list->addr || 2982 wr->prot->length != wr->wr.sg_list->length)) 2983 region_len += wr->prot->length; 2984 2985 /** 2986 * KLM octoword size - if protection was provided 2987 * then we use strided block format (3 octowords), 2988 * else we use single KLM (1 octoword) 2989 **/ 2990 klm_oct_size = wr->prot ? 3 : 1; 2991 2992 set_sig_umr_segment(*seg, klm_oct_size); 2993 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2994 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2995 if (unlikely((*seg == qp->sq.qend))) 2996 *seg = mlx5_get_send_wqe(qp, 0); 2997 2998 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 2999 *seg += sizeof(struct mlx5_mkey_seg); 3000 *size += sizeof(struct mlx5_mkey_seg) / 16; 3001 if (unlikely((*seg == qp->sq.qend))) 3002 *seg = mlx5_get_send_wqe(qp, 0); 3003 3004 ret = set_sig_data_segment(wr, qp, seg, size); 3005 if (ret) 3006 return ret; 3007 3008 sig_mr->sig->sig_status_checked = false; 3009 return 0; 3010 } 3011 3012 static int set_psv_wr(struct ib_sig_domain *domain, 3013 u32 psv_idx, void **seg, int *size) 3014 { 3015 struct mlx5_seg_set_psv *psv_seg = *seg; 3016 3017 memset(psv_seg, 0, sizeof(*psv_seg)); 3018 psv_seg->psv_num = cpu_to_be32(psv_idx); 3019 switch (domain->sig_type) { 3020 case IB_SIG_TYPE_NONE: 3021 break; 3022 case IB_SIG_TYPE_T10_DIF: 3023 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3024 domain->sig.dif.app_tag); 3025 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3026 break; 3027 default: 3028 pr_err("Bad signature type given.\n"); 3029 return 1; 3030 } 3031 3032 *seg += sizeof(*psv_seg); 3033 *size += sizeof(*psv_seg) / 16; 3034 3035 return 0; 3036 } 3037 3038 static int set_reg_wr(struct mlx5_ib_qp *qp, 3039 struct ib_reg_wr *wr, 3040 void **seg, int *size) 3041 { 3042 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3043 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3044 3045 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3046 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3047 "Invalid IB_SEND_INLINE send flag\n"); 3048 return -EINVAL; 3049 } 3050 3051 set_reg_umr_seg(*seg, mr); 3052 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3053 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3054 if (unlikely((*seg == qp->sq.qend))) 3055 *seg = mlx5_get_send_wqe(qp, 0); 3056 3057 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3058 *seg += sizeof(struct mlx5_mkey_seg); 3059 *size += sizeof(struct mlx5_mkey_seg) / 16; 3060 if (unlikely((*seg == qp->sq.qend))) 3061 *seg = mlx5_get_send_wqe(qp, 0); 3062 3063 set_reg_data_seg(*seg, mr, pd); 3064 *seg += sizeof(struct mlx5_wqe_data_seg); 3065 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3066 3067 return 0; 3068 } 3069 3070 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3071 { 3072 set_linv_umr_seg(*seg); 3073 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3074 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3075 if (unlikely((*seg == qp->sq.qend))) 3076 *seg = mlx5_get_send_wqe(qp, 0); 3077 set_linv_mkey_seg(*seg); 3078 *seg += sizeof(struct mlx5_mkey_seg); 3079 *size += sizeof(struct mlx5_mkey_seg) / 16; 3080 if (unlikely((*seg == qp->sq.qend))) 3081 *seg = mlx5_get_send_wqe(qp, 0); 3082 } 3083 3084 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3085 { 3086 __be32 *p = NULL; 3087 int tidx = idx; 3088 int i, j; 3089 3090 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3091 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3092 if ((i & 0xf) == 0) { 3093 void *buf = mlx5_get_send_wqe(qp, tidx); 3094 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3095 p = buf; 3096 j = 0; 3097 } 3098 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3099 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3100 be32_to_cpu(p[j + 3])); 3101 } 3102 } 3103 3104 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 3105 unsigned bytecnt, struct mlx5_ib_qp *qp) 3106 { 3107 while (bytecnt > 0) { 3108 __iowrite64_copy(dst++, src++, 8); 3109 __iowrite64_copy(dst++, src++, 8); 3110 __iowrite64_copy(dst++, src++, 8); 3111 __iowrite64_copy(dst++, src++, 8); 3112 __iowrite64_copy(dst++, src++, 8); 3113 __iowrite64_copy(dst++, src++, 8); 3114 __iowrite64_copy(dst++, src++, 8); 3115 __iowrite64_copy(dst++, src++, 8); 3116 bytecnt -= 64; 3117 if (unlikely(src == qp->sq.qend)) 3118 src = mlx5_get_send_wqe(qp, 0); 3119 } 3120 } 3121 3122 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 3123 { 3124 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3125 wr->send_flags & IB_SEND_FENCE)) 3126 return MLX5_FENCE_MODE_STRONG_ORDERING; 3127 3128 if (unlikely(fence)) { 3129 if (wr->send_flags & IB_SEND_FENCE) 3130 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3131 else 3132 return fence; 3133 3134 } else { 3135 return 0; 3136 } 3137 } 3138 3139 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3140 struct mlx5_wqe_ctrl_seg **ctrl, 3141 struct ib_send_wr *wr, unsigned *idx, 3142 int *size, int nreq) 3143 { 3144 int err = 0; 3145 3146 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) { 3147 err = -ENOMEM; 3148 return err; 3149 } 3150 3151 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3152 *seg = mlx5_get_send_wqe(qp, *idx); 3153 *ctrl = *seg; 3154 *(uint32_t *)(*seg + 8) = 0; 3155 (*ctrl)->imm = send_ieth(wr); 3156 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3157 (wr->send_flags & IB_SEND_SIGNALED ? 3158 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3159 (wr->send_flags & IB_SEND_SOLICITED ? 3160 MLX5_WQE_CTRL_SOLICITED : 0); 3161 3162 *seg += sizeof(**ctrl); 3163 *size = sizeof(**ctrl) / 16; 3164 3165 return err; 3166 } 3167 3168 static void finish_wqe(struct mlx5_ib_qp *qp, 3169 struct mlx5_wqe_ctrl_seg *ctrl, 3170 u8 size, unsigned idx, u64 wr_id, 3171 int nreq, u8 fence, u8 next_fence, 3172 u32 mlx5_opcode) 3173 { 3174 u8 opmod = 0; 3175 3176 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3177 mlx5_opcode | ((u32)opmod << 24)); 3178 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3179 ctrl->fm_ce_se |= fence; 3180 qp->fm_cache = next_fence; 3181 if (unlikely(qp->wq_sig)) 3182 ctrl->signature = wq_sig(ctrl); 3183 3184 qp->sq.wrid[idx] = wr_id; 3185 qp->sq.w_list[idx].opcode = mlx5_opcode; 3186 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3187 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3188 qp->sq.w_list[idx].next = qp->sq.cur_post; 3189 } 3190 3191 3192 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3193 struct ib_send_wr **bad_wr) 3194 { 3195 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3196 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3197 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3198 struct mlx5_ib_mr *mr; 3199 struct mlx5_wqe_data_seg *dpseg; 3200 struct mlx5_wqe_xrc_seg *xrc; 3201 struct mlx5_bf *bf = qp->bf; 3202 int uninitialized_var(size); 3203 void *qend = qp->sq.qend; 3204 unsigned long flags; 3205 unsigned idx; 3206 int err = 0; 3207 int inl = 0; 3208 int num_sge; 3209 void *seg; 3210 int nreq; 3211 int i; 3212 u8 next_fence = 0; 3213 u8 fence; 3214 3215 spin_lock_irqsave(&qp->sq.lock, flags); 3216 3217 for (nreq = 0; wr; nreq++, wr = wr->next) { 3218 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3219 mlx5_ib_warn(dev, "\n"); 3220 err = -EINVAL; 3221 *bad_wr = wr; 3222 goto out; 3223 } 3224 3225 fence = qp->fm_cache; 3226 num_sge = wr->num_sge; 3227 if (unlikely(num_sge > qp->sq.max_gs)) { 3228 mlx5_ib_warn(dev, "\n"); 3229 err = -ENOMEM; 3230 *bad_wr = wr; 3231 goto out; 3232 } 3233 3234 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3235 if (err) { 3236 mlx5_ib_warn(dev, "\n"); 3237 err = -ENOMEM; 3238 *bad_wr = wr; 3239 goto out; 3240 } 3241 3242 switch (ibqp->qp_type) { 3243 case IB_QPT_XRC_INI: 3244 xrc = seg; 3245 seg += sizeof(*xrc); 3246 size += sizeof(*xrc) / 16; 3247 /* fall through */ 3248 case IB_QPT_RC: 3249 switch (wr->opcode) { 3250 case IB_WR_RDMA_READ: 3251 case IB_WR_RDMA_WRITE: 3252 case IB_WR_RDMA_WRITE_WITH_IMM: 3253 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3254 rdma_wr(wr)->rkey); 3255 seg += sizeof(struct mlx5_wqe_raddr_seg); 3256 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3257 break; 3258 3259 case IB_WR_ATOMIC_CMP_AND_SWP: 3260 case IB_WR_ATOMIC_FETCH_AND_ADD: 3261 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3262 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3263 err = -ENOSYS; 3264 *bad_wr = wr; 3265 goto out; 3266 3267 case IB_WR_LOCAL_INV: 3268 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3269 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3270 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3271 set_linv_wr(qp, &seg, &size); 3272 num_sge = 0; 3273 break; 3274 3275 case IB_WR_REG_MR: 3276 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3277 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3278 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3279 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3280 if (err) { 3281 *bad_wr = wr; 3282 goto out; 3283 } 3284 num_sge = 0; 3285 break; 3286 3287 case IB_WR_REG_SIG_MR: 3288 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3289 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3290 3291 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3292 err = set_sig_umr_wr(wr, qp, &seg, &size); 3293 if (err) { 3294 mlx5_ib_warn(dev, "\n"); 3295 *bad_wr = wr; 3296 goto out; 3297 } 3298 3299 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3300 nreq, get_fence(fence, wr), 3301 next_fence, MLX5_OPCODE_UMR); 3302 /* 3303 * SET_PSV WQEs are not signaled and solicited 3304 * on error 3305 */ 3306 wr->send_flags &= ~IB_SEND_SIGNALED; 3307 wr->send_flags |= IB_SEND_SOLICITED; 3308 err = begin_wqe(qp, &seg, &ctrl, wr, 3309 &idx, &size, nreq); 3310 if (err) { 3311 mlx5_ib_warn(dev, "\n"); 3312 err = -ENOMEM; 3313 *bad_wr = wr; 3314 goto out; 3315 } 3316 3317 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 3318 mr->sig->psv_memory.psv_idx, &seg, 3319 &size); 3320 if (err) { 3321 mlx5_ib_warn(dev, "\n"); 3322 *bad_wr = wr; 3323 goto out; 3324 } 3325 3326 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3327 nreq, get_fence(fence, wr), 3328 next_fence, MLX5_OPCODE_SET_PSV); 3329 err = begin_wqe(qp, &seg, &ctrl, wr, 3330 &idx, &size, nreq); 3331 if (err) { 3332 mlx5_ib_warn(dev, "\n"); 3333 err = -ENOMEM; 3334 *bad_wr = wr; 3335 goto out; 3336 } 3337 3338 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3339 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 3340 mr->sig->psv_wire.psv_idx, &seg, 3341 &size); 3342 if (err) { 3343 mlx5_ib_warn(dev, "\n"); 3344 *bad_wr = wr; 3345 goto out; 3346 } 3347 3348 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3349 nreq, get_fence(fence, wr), 3350 next_fence, MLX5_OPCODE_SET_PSV); 3351 num_sge = 0; 3352 goto skip_psv; 3353 3354 default: 3355 break; 3356 } 3357 break; 3358 3359 case IB_QPT_UC: 3360 switch (wr->opcode) { 3361 case IB_WR_RDMA_WRITE: 3362 case IB_WR_RDMA_WRITE_WITH_IMM: 3363 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3364 rdma_wr(wr)->rkey); 3365 seg += sizeof(struct mlx5_wqe_raddr_seg); 3366 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3367 break; 3368 3369 default: 3370 break; 3371 } 3372 break; 3373 3374 case IB_QPT_UD: 3375 case IB_QPT_SMI: 3376 case IB_QPT_GSI: 3377 set_datagram_seg(seg, wr); 3378 seg += sizeof(struct mlx5_wqe_datagram_seg); 3379 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 3380 if (unlikely((seg == qend))) 3381 seg = mlx5_get_send_wqe(qp, 0); 3382 break; 3383 3384 case MLX5_IB_QPT_REG_UMR: 3385 if (wr->opcode != MLX5_IB_WR_UMR) { 3386 err = -EINVAL; 3387 mlx5_ib_warn(dev, "bad opcode\n"); 3388 goto out; 3389 } 3390 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 3391 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 3392 set_reg_umr_segment(seg, wr); 3393 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3394 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3395 if (unlikely((seg == qend))) 3396 seg = mlx5_get_send_wqe(qp, 0); 3397 set_reg_mkey_segment(seg, wr); 3398 seg += sizeof(struct mlx5_mkey_seg); 3399 size += sizeof(struct mlx5_mkey_seg) / 16; 3400 if (unlikely((seg == qend))) 3401 seg = mlx5_get_send_wqe(qp, 0); 3402 break; 3403 3404 default: 3405 break; 3406 } 3407 3408 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 3409 int uninitialized_var(sz); 3410 3411 err = set_data_inl_seg(qp, wr, seg, &sz); 3412 if (unlikely(err)) { 3413 mlx5_ib_warn(dev, "\n"); 3414 *bad_wr = wr; 3415 goto out; 3416 } 3417 inl = 1; 3418 size += sz; 3419 } else { 3420 dpseg = seg; 3421 for (i = 0; i < num_sge; i++) { 3422 if (unlikely(dpseg == qend)) { 3423 seg = mlx5_get_send_wqe(qp, 0); 3424 dpseg = seg; 3425 } 3426 if (likely(wr->sg_list[i].length)) { 3427 set_data_ptr_seg(dpseg, wr->sg_list + i); 3428 size += sizeof(struct mlx5_wqe_data_seg) / 16; 3429 dpseg++; 3430 } 3431 } 3432 } 3433 3434 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3435 get_fence(fence, wr), next_fence, 3436 mlx5_ib_opcode[wr->opcode]); 3437 skip_psv: 3438 if (0) 3439 dump_wqe(qp, idx, size); 3440 } 3441 3442 out: 3443 if (likely(nreq)) { 3444 qp->sq.head += nreq; 3445 3446 /* Make sure that descriptors are written before 3447 * updating doorbell record and ringing the doorbell 3448 */ 3449 wmb(); 3450 3451 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 3452 3453 /* Make sure doorbell record is visible to the HCA before 3454 * we hit doorbell */ 3455 wmb(); 3456 3457 if (bf->need_lock) 3458 spin_lock(&bf->lock); 3459 else 3460 __acquire(&bf->lock); 3461 3462 /* TBD enable WC */ 3463 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 3464 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 3465 /* wc_wmb(); */ 3466 } else { 3467 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 3468 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 3469 /* Make sure doorbells don't leak out of SQ spinlock 3470 * and reach the HCA out of order. 3471 */ 3472 mmiowb(); 3473 } 3474 bf->offset ^= bf->buf_size; 3475 if (bf->need_lock) 3476 spin_unlock(&bf->lock); 3477 else 3478 __release(&bf->lock); 3479 } 3480 3481 spin_unlock_irqrestore(&qp->sq.lock, flags); 3482 3483 return err; 3484 } 3485 3486 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 3487 { 3488 sig->signature = calc_sig(sig, size); 3489 } 3490 3491 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 3492 struct ib_recv_wr **bad_wr) 3493 { 3494 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3495 struct mlx5_wqe_data_seg *scat; 3496 struct mlx5_rwqe_sig *sig; 3497 unsigned long flags; 3498 int err = 0; 3499 int nreq; 3500 int ind; 3501 int i; 3502 3503 spin_lock_irqsave(&qp->rq.lock, flags); 3504 3505 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3506 3507 for (nreq = 0; wr; nreq++, wr = wr->next) { 3508 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3509 err = -ENOMEM; 3510 *bad_wr = wr; 3511 goto out; 3512 } 3513 3514 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3515 err = -EINVAL; 3516 *bad_wr = wr; 3517 goto out; 3518 } 3519 3520 scat = get_recv_wqe(qp, ind); 3521 if (qp->wq_sig) 3522 scat++; 3523 3524 for (i = 0; i < wr->num_sge; i++) 3525 set_data_ptr_seg(scat + i, wr->sg_list + i); 3526 3527 if (i < qp->rq.max_gs) { 3528 scat[i].byte_count = 0; 3529 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 3530 scat[i].addr = 0; 3531 } 3532 3533 if (qp->wq_sig) { 3534 sig = (struct mlx5_rwqe_sig *)scat; 3535 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 3536 } 3537 3538 qp->rq.wrid[ind] = wr->wr_id; 3539 3540 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3541 } 3542 3543 out: 3544 if (likely(nreq)) { 3545 qp->rq.head += nreq; 3546 3547 /* Make sure that descriptors are written before 3548 * doorbell record. 3549 */ 3550 wmb(); 3551 3552 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3553 } 3554 3555 spin_unlock_irqrestore(&qp->rq.lock, flags); 3556 3557 return err; 3558 } 3559 3560 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 3561 { 3562 switch (mlx5_state) { 3563 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 3564 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 3565 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 3566 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 3567 case MLX5_QP_STATE_SQ_DRAINING: 3568 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 3569 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 3570 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 3571 default: return -1; 3572 } 3573 } 3574 3575 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 3576 { 3577 switch (mlx5_mig_state) { 3578 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 3579 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 3580 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3581 default: return -1; 3582 } 3583 } 3584 3585 static int to_ib_qp_access_flags(int mlx5_flags) 3586 { 3587 int ib_flags = 0; 3588 3589 if (mlx5_flags & MLX5_QP_BIT_RRE) 3590 ib_flags |= IB_ACCESS_REMOTE_READ; 3591 if (mlx5_flags & MLX5_QP_BIT_RWE) 3592 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3593 if (mlx5_flags & MLX5_QP_BIT_RAE) 3594 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3595 3596 return ib_flags; 3597 } 3598 3599 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 3600 struct mlx5_qp_path *path) 3601 { 3602 struct mlx5_core_dev *dev = ibdev->mdev; 3603 3604 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 3605 ib_ah_attr->port_num = path->port; 3606 3607 if (ib_ah_attr->port_num == 0 || 3608 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 3609 return; 3610 3611 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 3612 3613 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3614 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 3615 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3616 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 3617 if (ib_ah_attr->ah_flags) { 3618 ib_ah_attr->grh.sgid_index = path->mgid_index; 3619 ib_ah_attr->grh.hop_limit = path->hop_limit; 3620 ib_ah_attr->grh.traffic_class = 3621 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3622 ib_ah_attr->grh.flow_label = 3623 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3624 memcpy(ib_ah_attr->grh.dgid.raw, 3625 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 3626 } 3627 } 3628 3629 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 3630 struct mlx5_ib_sq *sq, 3631 u8 *sq_state) 3632 { 3633 void *out; 3634 void *sqc; 3635 int inlen; 3636 int err; 3637 3638 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 3639 out = mlx5_vzalloc(inlen); 3640 if (!out) 3641 return -ENOMEM; 3642 3643 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 3644 if (err) 3645 goto out; 3646 3647 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 3648 *sq_state = MLX5_GET(sqc, sqc, state); 3649 sq->state = *sq_state; 3650 3651 out: 3652 kvfree(out); 3653 return err; 3654 } 3655 3656 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 3657 struct mlx5_ib_rq *rq, 3658 u8 *rq_state) 3659 { 3660 void *out; 3661 void *rqc; 3662 int inlen; 3663 int err; 3664 3665 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 3666 out = mlx5_vzalloc(inlen); 3667 if (!out) 3668 return -ENOMEM; 3669 3670 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 3671 if (err) 3672 goto out; 3673 3674 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 3675 *rq_state = MLX5_GET(rqc, rqc, state); 3676 rq->state = *rq_state; 3677 3678 out: 3679 kvfree(out); 3680 return err; 3681 } 3682 3683 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 3684 struct mlx5_ib_qp *qp, u8 *qp_state) 3685 { 3686 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 3687 [MLX5_RQC_STATE_RST] = { 3688 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 3689 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 3690 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 3691 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 3692 }, 3693 [MLX5_RQC_STATE_RDY] = { 3694 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 3695 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 3696 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 3697 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 3698 }, 3699 [MLX5_RQC_STATE_ERR] = { 3700 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 3701 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 3702 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 3703 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 3704 }, 3705 [MLX5_RQ_STATE_NA] = { 3706 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 3707 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 3708 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 3709 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 3710 }, 3711 }; 3712 3713 *qp_state = sqrq_trans[rq_state][sq_state]; 3714 3715 if (*qp_state == MLX5_QP_STATE_BAD) { 3716 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 3717 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 3718 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 3719 return -EINVAL; 3720 } 3721 3722 if (*qp_state == MLX5_QP_STATE) 3723 *qp_state = qp->state; 3724 3725 return 0; 3726 } 3727 3728 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 3729 struct mlx5_ib_qp *qp, 3730 u8 *raw_packet_qp_state) 3731 { 3732 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3733 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3734 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3735 int err; 3736 u8 sq_state = MLX5_SQ_STATE_NA; 3737 u8 rq_state = MLX5_RQ_STATE_NA; 3738 3739 if (qp->sq.wqe_cnt) { 3740 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 3741 if (err) 3742 return err; 3743 } 3744 3745 if (qp->rq.wqe_cnt) { 3746 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 3747 if (err) 3748 return err; 3749 } 3750 3751 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 3752 raw_packet_qp_state); 3753 } 3754 3755 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3756 struct ib_qp_attr *qp_attr) 3757 { 3758 struct mlx5_query_qp_mbox_out *outb; 3759 struct mlx5_qp_context *context; 3760 int mlx5_state; 3761 int err = 0; 3762 3763 outb = kzalloc(sizeof(*outb), GFP_KERNEL); 3764 if (!outb) 3765 return -ENOMEM; 3766 3767 context = &outb->ctx; 3768 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 3769 sizeof(*outb)); 3770 if (err) 3771 goto out; 3772 3773 mlx5_state = be32_to_cpu(context->flags) >> 28; 3774 3775 qp->state = to_ib_qp_state(mlx5_state); 3776 qp_attr->path_mtu = context->mtu_msgmax >> 5; 3777 qp_attr->path_mig_state = 3778 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 3779 qp_attr->qkey = be32_to_cpu(context->qkey); 3780 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 3781 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 3782 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 3783 qp_attr->qp_access_flags = 3784 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 3785 3786 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3787 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 3788 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 3789 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f; 3790 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 3791 } 3792 3793 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f; 3794 qp_attr->port_num = context->pri_path.port; 3795 3796 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3797 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 3798 3799 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 3800 3801 qp_attr->max_dest_rd_atomic = 3802 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 3803 qp_attr->min_rnr_timer = 3804 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 3805 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 3806 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 3807 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 3808 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 3809 3810 out: 3811 kfree(outb); 3812 return err; 3813 } 3814 3815 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 3816 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 3817 { 3818 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3819 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3820 int err = 0; 3821 u8 raw_packet_qp_state; 3822 3823 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 3824 /* 3825 * Wait for any outstanding page faults, in case the user frees memory 3826 * based upon this query's result. 3827 */ 3828 flush_workqueue(mlx5_ib_page_fault_wq); 3829 #endif 3830 3831 mutex_lock(&qp->mutex); 3832 3833 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 3834 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 3835 if (err) 3836 goto out; 3837 qp->state = raw_packet_qp_state; 3838 qp_attr->port_num = 1; 3839 } else { 3840 err = query_qp_attr(dev, qp, qp_attr); 3841 if (err) 3842 goto out; 3843 } 3844 3845 qp_attr->qp_state = qp->state; 3846 qp_attr->cur_qp_state = qp_attr->qp_state; 3847 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3848 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3849 3850 if (!ibqp->uobject) { 3851 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3852 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3853 } else { 3854 qp_attr->cap.max_send_wr = 0; 3855 qp_attr->cap.max_send_sge = 0; 3856 } 3857 3858 /* We don't support inline sends for kernel QPs (yet), and we 3859 * don't know what userspace's value should be. 3860 */ 3861 qp_attr->cap.max_inline_data = 0; 3862 3863 qp_init_attr->cap = qp_attr->cap; 3864 3865 qp_init_attr->create_flags = 0; 3866 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3867 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3868 3869 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 3870 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 3871 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 3872 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 3873 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 3874 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 3875 3876 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 3877 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3878 3879 out: 3880 mutex_unlock(&qp->mutex); 3881 return err; 3882 } 3883 3884 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 3885 struct ib_ucontext *context, 3886 struct ib_udata *udata) 3887 { 3888 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3889 struct mlx5_ib_xrcd *xrcd; 3890 int err; 3891 3892 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3893 return ERR_PTR(-ENOSYS); 3894 3895 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 3896 if (!xrcd) 3897 return ERR_PTR(-ENOMEM); 3898 3899 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 3900 if (err) { 3901 kfree(xrcd); 3902 return ERR_PTR(-ENOMEM); 3903 } 3904 3905 return &xrcd->ibxrcd; 3906 } 3907 3908 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 3909 { 3910 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 3911 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 3912 int err; 3913 3914 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 3915 if (err) { 3916 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 3917 return err; 3918 } 3919 3920 kfree(xrcd); 3921 3922 return 0; 3923 } 3924