1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "cmd.h" 42 #include "qp.h" 43 44 /* not supported currently */ 45 static int wq_signature; 46 47 enum { 48 MLX5_IB_ACK_REQ_FREQ = 8, 49 }; 50 51 enum { 52 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 53 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 54 MLX5_IB_LINK_TYPE_IB = 0, 55 MLX5_IB_LINK_TYPE_ETH = 1 56 }; 57 58 enum { 59 MLX5_IB_SQ_STRIDE = 6, 60 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 61 }; 62 63 static const u32 mlx5_ib_opcode[] = { 64 [IB_WR_SEND] = MLX5_OPCODE_SEND, 65 [IB_WR_LSO] = MLX5_OPCODE_LSO, 66 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 67 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 68 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 69 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 70 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 71 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 72 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 73 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 74 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 75 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 76 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 77 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 78 }; 79 80 struct mlx5_wqe_eth_pad { 81 u8 rsvd0[16]; 82 }; 83 84 enum raw_qp_set_mask_map { 85 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 86 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 87 }; 88 89 struct mlx5_modify_raw_qp_param { 90 u16 operation; 91 92 u32 set_mask; /* raw_qp_set_mask_map */ 93 94 struct mlx5_rate_limit rl; 95 96 u8 rq_q_ctr_id; 97 u16 port; 98 }; 99 100 static void get_cqs(enum ib_qp_type qp_type, 101 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 102 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 103 104 static int is_qp0(enum ib_qp_type qp_type) 105 { 106 return qp_type == IB_QPT_SMI; 107 } 108 109 static int is_sqp(enum ib_qp_type qp_type) 110 { 111 return is_qp0(qp_type) || is_qp1(qp_type); 112 } 113 114 /** 115 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 116 * to kernel buffer 117 * 118 * @umem: User space memory where the WQ is 119 * @buffer: buffer to copy to 120 * @buflen: buffer length 121 * @wqe_index: index of WQE to copy from 122 * @wq_offset: offset to start of WQ 123 * @wq_wqe_cnt: number of WQEs in WQ 124 * @wq_wqe_shift: log2 of WQE size 125 * @bcnt: number of bytes to copy 126 * @bytes_copied: number of bytes to copy (return value) 127 * 128 * Copies from start of WQE bcnt or less bytes. 129 * Does not gurantee to copy the entire WQE. 130 * 131 * Return: zero on success, or an error code. 132 */ 133 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 134 size_t buflen, int wqe_index, 135 int wq_offset, int wq_wqe_cnt, 136 int wq_wqe_shift, int bcnt, 137 size_t *bytes_copied) 138 { 139 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 140 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 141 size_t copy_length; 142 int ret; 143 144 /* don't copy more than requested, more than buffer length or 145 * beyond WQ end 146 */ 147 copy_length = min_t(u32, buflen, wq_end - offset); 148 copy_length = min_t(u32, copy_length, bcnt); 149 150 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 151 if (ret) 152 return ret; 153 154 if (!ret && bytes_copied) 155 *bytes_copied = copy_length; 156 157 return 0; 158 } 159 160 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 161 void *buffer, size_t buflen, size_t *bc) 162 { 163 struct mlx5_wqe_ctrl_seg *ctrl; 164 size_t bytes_copied = 0; 165 size_t wqe_length; 166 void *p; 167 int ds; 168 169 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 170 171 /* read the control segment first */ 172 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 173 ctrl = p; 174 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 175 wqe_length = ds * MLX5_WQE_DS_UNITS; 176 177 /* read rest of WQE if it spreads over more than one stride */ 178 while (bytes_copied < wqe_length) { 179 size_t copy_length = 180 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 181 182 if (!copy_length) 183 break; 184 185 memcpy(buffer + bytes_copied, p, copy_length); 186 bytes_copied += copy_length; 187 188 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 189 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 190 } 191 *bc = bytes_copied; 192 return 0; 193 } 194 195 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 196 void *buffer, size_t buflen, size_t *bc) 197 { 198 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 199 struct ib_umem *umem = base->ubuffer.umem; 200 struct mlx5_ib_wq *wq = &qp->sq; 201 struct mlx5_wqe_ctrl_seg *ctrl; 202 size_t bytes_copied; 203 size_t bytes_copied2; 204 size_t wqe_length; 205 int ret; 206 int ds; 207 208 /* at first read as much as possible */ 209 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 210 wq->offset, wq->wqe_cnt, 211 wq->wqe_shift, buflen, 212 &bytes_copied); 213 if (ret) 214 return ret; 215 216 /* we need at least control segment size to proceed */ 217 if (bytes_copied < sizeof(*ctrl)) 218 return -EINVAL; 219 220 ctrl = buffer; 221 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 222 wqe_length = ds * MLX5_WQE_DS_UNITS; 223 224 /* if we copied enough then we are done */ 225 if (bytes_copied >= wqe_length) { 226 *bc = bytes_copied; 227 return 0; 228 } 229 230 /* otherwise this a wrapped around wqe 231 * so read the remaining bytes starting 232 * from wqe_index 0 233 */ 234 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 235 buflen - bytes_copied, 0, wq->offset, 236 wq->wqe_cnt, wq->wqe_shift, 237 wqe_length - bytes_copied, 238 &bytes_copied2); 239 240 if (ret) 241 return ret; 242 *bc = bytes_copied + bytes_copied2; 243 return 0; 244 } 245 246 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 247 size_t buflen, size_t *bc) 248 { 249 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 250 struct ib_umem *umem = base->ubuffer.umem; 251 252 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 253 return -EINVAL; 254 255 if (!umem) 256 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 257 buflen, bc); 258 259 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 260 } 261 262 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 263 void *buffer, size_t buflen, size_t *bc) 264 { 265 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 266 struct ib_umem *umem = base->ubuffer.umem; 267 struct mlx5_ib_wq *wq = &qp->rq; 268 size_t bytes_copied; 269 int ret; 270 271 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 272 wq->offset, wq->wqe_cnt, 273 wq->wqe_shift, buflen, 274 &bytes_copied); 275 276 if (ret) 277 return ret; 278 *bc = bytes_copied; 279 return 0; 280 } 281 282 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 283 size_t buflen, size_t *bc) 284 { 285 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 286 struct ib_umem *umem = base->ubuffer.umem; 287 struct mlx5_ib_wq *wq = &qp->rq; 288 size_t wqe_size = 1 << wq->wqe_shift; 289 290 if (buflen < wqe_size) 291 return -EINVAL; 292 293 if (!umem) 294 return -EOPNOTSUPP; 295 296 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 297 } 298 299 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 300 void *buffer, size_t buflen, size_t *bc) 301 { 302 struct ib_umem *umem = srq->umem; 303 size_t bytes_copied; 304 int ret; 305 306 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 307 srq->msrq.max, srq->msrq.wqe_shift, 308 buflen, &bytes_copied); 309 310 if (ret) 311 return ret; 312 *bc = bytes_copied; 313 return 0; 314 } 315 316 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 317 size_t buflen, size_t *bc) 318 { 319 struct ib_umem *umem = srq->umem; 320 size_t wqe_size = 1 << srq->msrq.wqe_shift; 321 322 if (buflen < wqe_size) 323 return -EINVAL; 324 325 if (!umem) 326 return -EOPNOTSUPP; 327 328 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 329 } 330 331 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 332 { 333 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 334 struct ib_event event; 335 336 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 337 /* This event is only valid for trans_qps */ 338 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 339 } 340 341 if (ibqp->event_handler) { 342 event.device = ibqp->device; 343 event.element.qp = ibqp; 344 switch (type) { 345 case MLX5_EVENT_TYPE_PATH_MIG: 346 event.event = IB_EVENT_PATH_MIG; 347 break; 348 case MLX5_EVENT_TYPE_COMM_EST: 349 event.event = IB_EVENT_COMM_EST; 350 break; 351 case MLX5_EVENT_TYPE_SQ_DRAINED: 352 event.event = IB_EVENT_SQ_DRAINED; 353 break; 354 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 355 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 356 break; 357 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 358 event.event = IB_EVENT_QP_FATAL; 359 break; 360 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 361 event.event = IB_EVENT_PATH_MIG_ERR; 362 break; 363 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 364 event.event = IB_EVENT_QP_REQ_ERR; 365 break; 366 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 367 event.event = IB_EVENT_QP_ACCESS_ERR; 368 break; 369 default: 370 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 371 return; 372 } 373 374 ibqp->event_handler(&event, ibqp->qp_context); 375 } 376 } 377 378 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 379 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 380 { 381 int wqe_size; 382 int wq_size; 383 384 /* Sanity check RQ size before proceeding */ 385 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 386 return -EINVAL; 387 388 if (!has_rq) { 389 qp->rq.max_gs = 0; 390 qp->rq.wqe_cnt = 0; 391 qp->rq.wqe_shift = 0; 392 cap->max_recv_wr = 0; 393 cap->max_recv_sge = 0; 394 } else { 395 if (ucmd) { 396 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 397 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 398 return -EINVAL; 399 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 400 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 401 return -EINVAL; 402 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 403 qp->rq.max_post = qp->rq.wqe_cnt; 404 } else { 405 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 406 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 407 wqe_size = roundup_pow_of_two(wqe_size); 408 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 409 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 410 qp->rq.wqe_cnt = wq_size / wqe_size; 411 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 412 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 413 wqe_size, 414 MLX5_CAP_GEN(dev->mdev, 415 max_wqe_sz_rq)); 416 return -EINVAL; 417 } 418 qp->rq.wqe_shift = ilog2(wqe_size); 419 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 420 qp->rq.max_post = qp->rq.wqe_cnt; 421 } 422 } 423 424 return 0; 425 } 426 427 static int sq_overhead(struct ib_qp_init_attr *attr) 428 { 429 int size = 0; 430 431 switch (attr->qp_type) { 432 case IB_QPT_XRC_INI: 433 size += sizeof(struct mlx5_wqe_xrc_seg); 434 /* fall through */ 435 case IB_QPT_RC: 436 size += sizeof(struct mlx5_wqe_ctrl_seg) + 437 max(sizeof(struct mlx5_wqe_atomic_seg) + 438 sizeof(struct mlx5_wqe_raddr_seg), 439 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 440 sizeof(struct mlx5_mkey_seg) + 441 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 442 MLX5_IB_UMR_OCTOWORD); 443 break; 444 445 case IB_QPT_XRC_TGT: 446 return 0; 447 448 case IB_QPT_UC: 449 size += sizeof(struct mlx5_wqe_ctrl_seg) + 450 max(sizeof(struct mlx5_wqe_raddr_seg), 451 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 452 sizeof(struct mlx5_mkey_seg)); 453 break; 454 455 case IB_QPT_UD: 456 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 457 size += sizeof(struct mlx5_wqe_eth_pad) + 458 sizeof(struct mlx5_wqe_eth_seg); 459 /* fall through */ 460 case IB_QPT_SMI: 461 case MLX5_IB_QPT_HW_GSI: 462 size += sizeof(struct mlx5_wqe_ctrl_seg) + 463 sizeof(struct mlx5_wqe_datagram_seg); 464 break; 465 466 case MLX5_IB_QPT_REG_UMR: 467 size += sizeof(struct mlx5_wqe_ctrl_seg) + 468 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 469 sizeof(struct mlx5_mkey_seg); 470 break; 471 472 default: 473 return -EINVAL; 474 } 475 476 return size; 477 } 478 479 static int calc_send_wqe(struct ib_qp_init_attr *attr) 480 { 481 int inl_size = 0; 482 int size; 483 484 size = sq_overhead(attr); 485 if (size < 0) 486 return size; 487 488 if (attr->cap.max_inline_data) { 489 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 490 attr->cap.max_inline_data; 491 } 492 493 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 494 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 495 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 496 return MLX5_SIG_WQE_SIZE; 497 else 498 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 499 } 500 501 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 502 { 503 int max_sge; 504 505 if (attr->qp_type == IB_QPT_RC) 506 max_sge = (min_t(int, wqe_size, 512) - 507 sizeof(struct mlx5_wqe_ctrl_seg) - 508 sizeof(struct mlx5_wqe_raddr_seg)) / 509 sizeof(struct mlx5_wqe_data_seg); 510 else if (attr->qp_type == IB_QPT_XRC_INI) 511 max_sge = (min_t(int, wqe_size, 512) - 512 sizeof(struct mlx5_wqe_ctrl_seg) - 513 sizeof(struct mlx5_wqe_xrc_seg) - 514 sizeof(struct mlx5_wqe_raddr_seg)) / 515 sizeof(struct mlx5_wqe_data_seg); 516 else 517 max_sge = (wqe_size - sq_overhead(attr)) / 518 sizeof(struct mlx5_wqe_data_seg); 519 520 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 521 sizeof(struct mlx5_wqe_data_seg)); 522 } 523 524 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 525 struct mlx5_ib_qp *qp) 526 { 527 int wqe_size; 528 int wq_size; 529 530 if (!attr->cap.max_send_wr) 531 return 0; 532 533 wqe_size = calc_send_wqe(attr); 534 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 535 if (wqe_size < 0) 536 return wqe_size; 537 538 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 539 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 540 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 541 return -EINVAL; 542 } 543 544 qp->max_inline_data = wqe_size - sq_overhead(attr) - 545 sizeof(struct mlx5_wqe_inline_seg); 546 attr->cap.max_inline_data = qp->max_inline_data; 547 548 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 549 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 550 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 551 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 552 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 553 qp->sq.wqe_cnt, 554 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 555 return -ENOMEM; 556 } 557 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 558 qp->sq.max_gs = get_send_sge(attr, wqe_size); 559 if (qp->sq.max_gs < attr->cap.max_send_sge) 560 return -ENOMEM; 561 562 attr->cap.max_send_sge = qp->sq.max_gs; 563 qp->sq.max_post = wq_size / wqe_size; 564 attr->cap.max_send_wr = qp->sq.max_post; 565 566 return wq_size; 567 } 568 569 static int set_user_buf_size(struct mlx5_ib_dev *dev, 570 struct mlx5_ib_qp *qp, 571 struct mlx5_ib_create_qp *ucmd, 572 struct mlx5_ib_qp_base *base, 573 struct ib_qp_init_attr *attr) 574 { 575 int desc_sz = 1 << qp->sq.wqe_shift; 576 577 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 578 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 579 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 580 return -EINVAL; 581 } 582 583 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 584 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 585 ucmd->sq_wqe_count); 586 return -EINVAL; 587 } 588 589 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 590 591 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 592 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 593 qp->sq.wqe_cnt, 594 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 595 return -EINVAL; 596 } 597 598 if (attr->qp_type == IB_QPT_RAW_PACKET || 599 qp->flags & MLX5_IB_QP_UNDERLAY) { 600 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 601 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 602 } else { 603 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 604 (qp->sq.wqe_cnt << 6); 605 } 606 607 return 0; 608 } 609 610 static int qp_has_rq(struct ib_qp_init_attr *attr) 611 { 612 if (attr->qp_type == IB_QPT_XRC_INI || 613 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 614 attr->qp_type == MLX5_IB_QPT_REG_UMR || 615 !attr->cap.max_recv_wr) 616 return 0; 617 618 return 1; 619 } 620 621 enum { 622 /* this is the first blue flame register in the array of bfregs assigned 623 * to a processes. Since we do not use it for blue flame but rather 624 * regular 64 bit doorbells, we do not need a lock for maintaiing 625 * "odd/even" order 626 */ 627 NUM_NON_BLUE_FLAME_BFREGS = 1, 628 }; 629 630 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 631 { 632 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 633 } 634 635 static int num_med_bfreg(struct mlx5_ib_dev *dev, 636 struct mlx5_bfreg_info *bfregi) 637 { 638 int n; 639 640 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 641 NUM_NON_BLUE_FLAME_BFREGS; 642 643 return n >= 0 ? n : 0; 644 } 645 646 static int first_med_bfreg(struct mlx5_ib_dev *dev, 647 struct mlx5_bfreg_info *bfregi) 648 { 649 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 650 } 651 652 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 653 struct mlx5_bfreg_info *bfregi) 654 { 655 int med; 656 657 med = num_med_bfreg(dev, bfregi); 658 return ++med; 659 } 660 661 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 662 struct mlx5_bfreg_info *bfregi) 663 { 664 int i; 665 666 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 667 if (!bfregi->count[i]) { 668 bfregi->count[i]++; 669 return i; 670 } 671 } 672 673 return -ENOMEM; 674 } 675 676 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 677 struct mlx5_bfreg_info *bfregi) 678 { 679 int minidx = first_med_bfreg(dev, bfregi); 680 int i; 681 682 if (minidx < 0) 683 return minidx; 684 685 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 686 if (bfregi->count[i] < bfregi->count[minidx]) 687 minidx = i; 688 if (!bfregi->count[minidx]) 689 break; 690 } 691 692 bfregi->count[minidx]++; 693 return minidx; 694 } 695 696 static int alloc_bfreg(struct mlx5_ib_dev *dev, 697 struct mlx5_bfreg_info *bfregi) 698 { 699 int bfregn = -ENOMEM; 700 701 if (bfregi->lib_uar_dyn) 702 return -EINVAL; 703 704 mutex_lock(&bfregi->lock); 705 if (bfregi->ver >= 2) { 706 bfregn = alloc_high_class_bfreg(dev, bfregi); 707 if (bfregn < 0) 708 bfregn = alloc_med_class_bfreg(dev, bfregi); 709 } 710 711 if (bfregn < 0) { 712 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 713 bfregn = 0; 714 bfregi->count[bfregn]++; 715 } 716 mutex_unlock(&bfregi->lock); 717 718 return bfregn; 719 } 720 721 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 722 { 723 mutex_lock(&bfregi->lock); 724 bfregi->count[bfregn]--; 725 mutex_unlock(&bfregi->lock); 726 } 727 728 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 729 { 730 switch (state) { 731 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 732 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 733 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 734 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 735 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 736 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 737 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 738 default: return -1; 739 } 740 } 741 742 static int to_mlx5_st(enum ib_qp_type type) 743 { 744 switch (type) { 745 case IB_QPT_RC: return MLX5_QP_ST_RC; 746 case IB_QPT_UC: return MLX5_QP_ST_UC; 747 case IB_QPT_UD: return MLX5_QP_ST_UD; 748 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 749 case IB_QPT_XRC_INI: 750 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 751 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 752 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 753 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 754 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 755 case IB_QPT_RAW_PACKET: 756 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 757 case IB_QPT_MAX: 758 default: return -EINVAL; 759 } 760 } 761 762 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 763 struct mlx5_ib_cq *recv_cq); 764 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 765 struct mlx5_ib_cq *recv_cq); 766 767 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 768 struct mlx5_bfreg_info *bfregi, u32 bfregn, 769 bool dyn_bfreg) 770 { 771 unsigned int bfregs_per_sys_page; 772 u32 index_of_sys_page; 773 u32 offset; 774 775 if (bfregi->lib_uar_dyn) 776 return -EINVAL; 777 778 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 779 MLX5_NON_FP_BFREGS_PER_UAR; 780 index_of_sys_page = bfregn / bfregs_per_sys_page; 781 782 if (dyn_bfreg) { 783 index_of_sys_page += bfregi->num_static_sys_pages; 784 785 if (index_of_sys_page >= bfregi->num_sys_pages) 786 return -EINVAL; 787 788 if (bfregn > bfregi->num_dyn_bfregs || 789 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 790 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 791 return -EINVAL; 792 } 793 } 794 795 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 796 return bfregi->sys_pages[index_of_sys_page] + offset; 797 } 798 799 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, 800 unsigned long addr, size_t size, 801 struct ib_umem **umem, int *npages, int *page_shift, 802 int *ncont, u32 *offset) 803 { 804 int err; 805 806 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0); 807 if (IS_ERR(*umem)) { 808 mlx5_ib_dbg(dev, "umem_get failed\n"); 809 return PTR_ERR(*umem); 810 } 811 812 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 813 814 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 815 if (err) { 816 mlx5_ib_warn(dev, "bad offset\n"); 817 goto err_umem; 818 } 819 820 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 821 addr, size, *npages, *page_shift, *ncont, *offset); 822 823 return 0; 824 825 err_umem: 826 ib_umem_release(*umem); 827 *umem = NULL; 828 829 return err; 830 } 831 832 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 833 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 834 { 835 struct mlx5_ib_ucontext *context = 836 rdma_udata_to_drv_context( 837 udata, 838 struct mlx5_ib_ucontext, 839 ibucontext); 840 841 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 842 atomic_dec(&dev->delay_drop.rqs_cnt); 843 844 mlx5_ib_db_unmap_user(context, &rwq->db); 845 ib_umem_release(rwq->umem); 846 } 847 848 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 849 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 850 struct mlx5_ib_create_wq *ucmd) 851 { 852 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 853 udata, struct mlx5_ib_ucontext, ibucontext); 854 int page_shift = 0; 855 int npages; 856 u32 offset = 0; 857 int ncont = 0; 858 int err; 859 860 if (!ucmd->buf_addr) 861 return -EINVAL; 862 863 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 864 if (IS_ERR(rwq->umem)) { 865 mlx5_ib_dbg(dev, "umem_get failed\n"); 866 err = PTR_ERR(rwq->umem); 867 return err; 868 } 869 870 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 871 &ncont, NULL); 872 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 873 &rwq->rq_page_offset); 874 if (err) { 875 mlx5_ib_warn(dev, "bad offset\n"); 876 goto err_umem; 877 } 878 879 rwq->rq_num_pas = ncont; 880 rwq->page_shift = page_shift; 881 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 882 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 883 884 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 885 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 886 npages, page_shift, ncont, offset); 887 888 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 889 if (err) { 890 mlx5_ib_dbg(dev, "map failed\n"); 891 goto err_umem; 892 } 893 894 rwq->create_type = MLX5_WQ_USER; 895 return 0; 896 897 err_umem: 898 ib_umem_release(rwq->umem); 899 return err; 900 } 901 902 static int adjust_bfregn(struct mlx5_ib_dev *dev, 903 struct mlx5_bfreg_info *bfregi, int bfregn) 904 { 905 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 906 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 907 } 908 909 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 910 struct mlx5_ib_qp *qp, struct ib_udata *udata, 911 struct ib_qp_init_attr *attr, 912 u32 **in, 913 struct mlx5_ib_create_qp_resp *resp, int *inlen, 914 struct mlx5_ib_qp_base *base) 915 { 916 struct mlx5_ib_ucontext *context; 917 struct mlx5_ib_create_qp ucmd; 918 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 919 int page_shift = 0; 920 int uar_index = 0; 921 int npages; 922 u32 offset = 0; 923 int bfregn; 924 int ncont = 0; 925 __be64 *pas; 926 void *qpc; 927 int err; 928 u16 uid; 929 u32 uar_flags; 930 931 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 932 if (err) { 933 mlx5_ib_dbg(dev, "copy failed\n"); 934 return err; 935 } 936 937 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 938 ibucontext); 939 uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX | 940 MLX5_QP_FLAG_BFREG_INDEX); 941 switch (uar_flags) { 942 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 943 uar_index = ucmd.bfreg_index; 944 bfregn = MLX5_IB_INVALID_BFREG; 945 break; 946 case MLX5_QP_FLAG_BFREG_INDEX: 947 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 948 ucmd.bfreg_index, true); 949 if (uar_index < 0) 950 return uar_index; 951 bfregn = MLX5_IB_INVALID_BFREG; 952 break; 953 case 0: 954 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 955 return -EINVAL; 956 bfregn = alloc_bfreg(dev, &context->bfregi); 957 if (bfregn < 0) 958 return bfregn; 959 break; 960 default: 961 return -EINVAL; 962 } 963 964 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 965 if (bfregn != MLX5_IB_INVALID_BFREG) 966 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 967 false); 968 969 qp->rq.offset = 0; 970 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 971 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 972 973 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 974 if (err) 975 goto err_bfreg; 976 977 if (ucmd.buf_addr && ubuffer->buf_size) { 978 ubuffer->buf_addr = ucmd.buf_addr; 979 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, 980 ubuffer->buf_size, &ubuffer->umem, 981 &npages, &page_shift, &ncont, &offset); 982 if (err) 983 goto err_bfreg; 984 } else { 985 ubuffer->umem = NULL; 986 } 987 988 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 989 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 990 *in = kvzalloc(*inlen, GFP_KERNEL); 991 if (!*in) { 992 err = -ENOMEM; 993 goto err_umem; 994 } 995 996 uid = (attr->qp_type != IB_QPT_XRC_TGT && 997 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 998 MLX5_SET(create_qp_in, *in, uid, uid); 999 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 1000 if (ubuffer->umem) 1001 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 1002 1003 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1004 1005 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1006 MLX5_SET(qpc, qpc, page_offset, offset); 1007 1008 MLX5_SET(qpc, qpc, uar_page, uar_index); 1009 if (bfregn != MLX5_IB_INVALID_BFREG) 1010 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 1011 else 1012 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 1013 qp->bfregn = bfregn; 1014 1015 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db); 1016 if (err) { 1017 mlx5_ib_dbg(dev, "map failed\n"); 1018 goto err_free; 1019 } 1020 1021 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1022 if (err) { 1023 mlx5_ib_dbg(dev, "copy failed\n"); 1024 goto err_unmap; 1025 } 1026 qp->create_type = MLX5_QP_USER; 1027 1028 return 0; 1029 1030 err_unmap: 1031 mlx5_ib_db_unmap_user(context, &qp->db); 1032 1033 err_free: 1034 kvfree(*in); 1035 1036 err_umem: 1037 ib_umem_release(ubuffer->umem); 1038 1039 err_bfreg: 1040 if (bfregn != MLX5_IB_INVALID_BFREG) 1041 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1042 return err; 1043 } 1044 1045 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1046 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base, 1047 struct ib_udata *udata) 1048 { 1049 struct mlx5_ib_ucontext *context = 1050 rdma_udata_to_drv_context( 1051 udata, 1052 struct mlx5_ib_ucontext, 1053 ibucontext); 1054 1055 mlx5_ib_db_unmap_user(context, &qp->db); 1056 ib_umem_release(base->ubuffer.umem); 1057 1058 /* 1059 * Free only the BFREGs which are handled by the kernel. 1060 * BFREGs of UARs allocated dynamically are handled by user. 1061 */ 1062 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1063 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1064 } 1065 1066 /* get_sq_edge - Get the next nearby edge. 1067 * 1068 * An 'edge' is defined as the first following address after the end 1069 * of the fragment or the SQ. Accordingly, during the WQE construction 1070 * which repetitively increases the pointer to write the next data, it 1071 * simply should check if it gets to an edge. 1072 * 1073 * @sq - SQ buffer. 1074 * @idx - Stride index in the SQ buffer. 1075 * 1076 * Return: 1077 * The new edge. 1078 */ 1079 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) 1080 { 1081 void *fragment_end; 1082 1083 fragment_end = mlx5_frag_buf_get_wqe 1084 (&sq->fbc, 1085 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); 1086 1087 return fragment_end + MLX5_SEND_WQE_BB; 1088 } 1089 1090 static int create_kernel_qp(struct mlx5_ib_dev *dev, 1091 struct ib_qp_init_attr *init_attr, 1092 struct mlx5_ib_qp *qp, 1093 u32 **in, int *inlen, 1094 struct mlx5_ib_qp_base *base) 1095 { 1096 int uar_index; 1097 void *qpc; 1098 int err; 1099 1100 if (init_attr->create_flags & ~(IB_QP_CREATE_INTEGRITY_EN | 1101 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 1102 IB_QP_CREATE_IPOIB_UD_LSO | 1103 IB_QP_CREATE_NETIF_QP | 1104 MLX5_IB_QP_CREATE_SQPN_QP1 | 1105 MLX5_IB_QP_CREATE_WC_TEST)) 1106 return -EINVAL; 1107 1108 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1109 qp->bf.bfreg = &dev->fp_bfreg; 1110 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) 1111 qp->bf.bfreg = &dev->wc_bfreg; 1112 else 1113 qp->bf.bfreg = &dev->bfreg; 1114 1115 /* We need to divide by two since each register is comprised of 1116 * two buffers of identical size, namely odd and even 1117 */ 1118 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1119 uar_index = qp->bf.bfreg->index; 1120 1121 err = calc_sq_size(dev, init_attr, qp); 1122 if (err < 0) { 1123 mlx5_ib_dbg(dev, "err %d\n", err); 1124 return err; 1125 } 1126 1127 qp->rq.offset = 0; 1128 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1129 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1130 1131 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1132 &qp->buf, dev->mdev->priv.numa_node); 1133 if (err) { 1134 mlx5_ib_dbg(dev, "err %d\n", err); 1135 return err; 1136 } 1137 1138 if (qp->rq.wqe_cnt) 1139 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1140 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1141 1142 if (qp->sq.wqe_cnt) { 1143 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1144 MLX5_SEND_WQE_BB; 1145 mlx5_init_fbc_offset(qp->buf.frags + 1146 (qp->sq.offset / PAGE_SIZE), 1147 ilog2(MLX5_SEND_WQE_BB), 1148 ilog2(qp->sq.wqe_cnt), 1149 sq_strides_offset, &qp->sq.fbc); 1150 1151 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1152 } 1153 1154 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1155 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1156 *in = kvzalloc(*inlen, GFP_KERNEL); 1157 if (!*in) { 1158 err = -ENOMEM; 1159 goto err_buf; 1160 } 1161 1162 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1163 MLX5_SET(qpc, qpc, uar_page, uar_index); 1164 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1165 1166 /* Set "fast registration enabled" for all kernel QPs */ 1167 MLX5_SET(qpc, qpc, fre, 1); 1168 MLX5_SET(qpc, qpc, rlky, 1); 1169 1170 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { 1171 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1172 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1173 } 1174 1175 mlx5_fill_page_frag_array(&qp->buf, 1176 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1177 *in, pas)); 1178 1179 err = mlx5_db_alloc(dev->mdev, &qp->db); 1180 if (err) { 1181 mlx5_ib_dbg(dev, "err %d\n", err); 1182 goto err_free; 1183 } 1184 1185 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1186 sizeof(*qp->sq.wrid), GFP_KERNEL); 1187 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1188 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1189 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1190 sizeof(*qp->rq.wrid), GFP_KERNEL); 1191 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1192 sizeof(*qp->sq.w_list), GFP_KERNEL); 1193 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1194 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1195 1196 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1197 !qp->sq.w_list || !qp->sq.wqe_head) { 1198 err = -ENOMEM; 1199 goto err_wrid; 1200 } 1201 qp->create_type = MLX5_QP_KERNEL; 1202 1203 return 0; 1204 1205 err_wrid: 1206 kvfree(qp->sq.wqe_head); 1207 kvfree(qp->sq.w_list); 1208 kvfree(qp->sq.wrid); 1209 kvfree(qp->sq.wr_data); 1210 kvfree(qp->rq.wrid); 1211 mlx5_db_free(dev->mdev, &qp->db); 1212 1213 err_free: 1214 kvfree(*in); 1215 1216 err_buf: 1217 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1218 return err; 1219 } 1220 1221 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1222 { 1223 kvfree(qp->sq.wqe_head); 1224 kvfree(qp->sq.w_list); 1225 kvfree(qp->sq.wrid); 1226 kvfree(qp->sq.wr_data); 1227 kvfree(qp->rq.wrid); 1228 mlx5_db_free(dev->mdev, &qp->db); 1229 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1230 } 1231 1232 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1233 { 1234 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1235 (attr->qp_type == MLX5_IB_QPT_DCI) || 1236 (attr->qp_type == IB_QPT_XRC_INI)) 1237 return MLX5_SRQ_RQ; 1238 else if (!qp->has_rq) 1239 return MLX5_ZERO_LEN_RQ; 1240 else 1241 return MLX5_NON_ZERO_RQ; 1242 } 1243 1244 static int is_connected(enum ib_qp_type qp_type) 1245 { 1246 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || 1247 qp_type == MLX5_IB_QPT_DCI) 1248 return 1; 1249 1250 return 0; 1251 } 1252 1253 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1254 struct mlx5_ib_qp *qp, 1255 struct mlx5_ib_sq *sq, u32 tdn, 1256 struct ib_pd *pd) 1257 { 1258 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1259 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1260 1261 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1262 MLX5_SET(tisc, tisc, transport_domain, tdn); 1263 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1264 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1265 1266 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1267 } 1268 1269 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1270 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1271 { 1272 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1273 } 1274 1275 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1276 { 1277 if (sq->flow_rule) 1278 mlx5_del_flow_rules(sq->flow_rule); 1279 sq->flow_rule = NULL; 1280 } 1281 1282 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1283 struct ib_udata *udata, 1284 struct mlx5_ib_sq *sq, void *qpin, 1285 struct ib_pd *pd) 1286 { 1287 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1288 __be64 *pas; 1289 void *in; 1290 void *sqc; 1291 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1292 void *wq; 1293 int inlen; 1294 int err; 1295 int page_shift = 0; 1296 int npages; 1297 int ncont = 0; 1298 u32 offset = 0; 1299 1300 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, 1301 &sq->ubuffer.umem, &npages, &page_shift, &ncont, 1302 &offset); 1303 if (err) 1304 return err; 1305 1306 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1307 in = kvzalloc(inlen, GFP_KERNEL); 1308 if (!in) { 1309 err = -ENOMEM; 1310 goto err_umem; 1311 } 1312 1313 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1314 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1315 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1316 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1317 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1318 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1319 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1320 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1321 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1322 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1323 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1324 MLX5_CAP_ETH(dev->mdev, swp)) 1325 MLX5_SET(sqc, sqc, allow_swp, 1); 1326 1327 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1328 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1329 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1330 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1331 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1332 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1333 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1334 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1335 MLX5_SET(wq, wq, page_offset, offset); 1336 1337 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1338 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1339 1340 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1341 1342 kvfree(in); 1343 1344 if (err) 1345 goto err_umem; 1346 1347 return 0; 1348 1349 err_umem: 1350 ib_umem_release(sq->ubuffer.umem); 1351 sq->ubuffer.umem = NULL; 1352 1353 return err; 1354 } 1355 1356 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1357 struct mlx5_ib_sq *sq) 1358 { 1359 destroy_flow_rule_vport_sq(sq); 1360 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1361 ib_umem_release(sq->ubuffer.umem); 1362 } 1363 1364 static size_t get_rq_pas_size(void *qpc) 1365 { 1366 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1367 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1368 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1369 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1370 u32 po_quanta = 1 << (log_page_size - 6); 1371 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1372 u32 page_size = 1 << log_page_size; 1373 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1374 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1375 1376 return rq_num_pas * sizeof(u64); 1377 } 1378 1379 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1380 struct mlx5_ib_rq *rq, void *qpin, 1381 size_t qpinlen, struct ib_pd *pd) 1382 { 1383 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1384 __be64 *pas; 1385 __be64 *qp_pas; 1386 void *in; 1387 void *rqc; 1388 void *wq; 1389 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1390 size_t rq_pas_size = get_rq_pas_size(qpc); 1391 size_t inlen; 1392 int err; 1393 1394 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1395 return -EINVAL; 1396 1397 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1398 in = kvzalloc(inlen, GFP_KERNEL); 1399 if (!in) 1400 return -ENOMEM; 1401 1402 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1403 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1404 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1405 MLX5_SET(rqc, rqc, vsd, 1); 1406 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1407 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1408 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1409 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1410 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1411 1412 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1413 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1414 1415 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1416 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1417 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1418 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1419 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1420 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1421 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1422 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1423 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1424 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1425 1426 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1427 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1428 memcpy(pas, qp_pas, rq_pas_size); 1429 1430 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1431 1432 kvfree(in); 1433 1434 return err; 1435 } 1436 1437 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1438 struct mlx5_ib_rq *rq) 1439 { 1440 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1441 } 1442 1443 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1444 { 1445 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1446 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1447 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1448 } 1449 1450 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1451 struct mlx5_ib_rq *rq, 1452 u32 qp_flags_en, 1453 struct ib_pd *pd) 1454 { 1455 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1456 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1457 mlx5_ib_disable_lb(dev, false, true); 1458 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1459 } 1460 1461 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1462 struct mlx5_ib_rq *rq, u32 tdn, 1463 u32 *qp_flags_en, struct ib_pd *pd, 1464 u32 *out) 1465 { 1466 u8 lb_flag = 0; 1467 u32 *in; 1468 void *tirc; 1469 int inlen; 1470 int err; 1471 1472 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1473 in = kvzalloc(inlen, GFP_KERNEL); 1474 if (!in) 1475 return -ENOMEM; 1476 1477 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1478 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1479 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1480 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1481 MLX5_SET(tirc, tirc, transport_domain, tdn); 1482 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1483 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1484 1485 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1486 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1487 1488 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1489 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1490 1491 if (dev->is_rep) { 1492 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1493 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1494 } 1495 1496 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1497 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1498 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1499 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1500 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1501 err = mlx5_ib_enable_lb(dev, false, true); 1502 1503 if (err) 1504 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1505 } 1506 kvfree(in); 1507 1508 return err; 1509 } 1510 1511 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1512 u32 *in, size_t inlen, 1513 struct ib_pd *pd, 1514 struct ib_udata *udata, 1515 struct mlx5_ib_create_qp_resp *resp) 1516 { 1517 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1518 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1519 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1520 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1521 udata, struct mlx5_ib_ucontext, ibucontext); 1522 int err; 1523 u32 tdn = mucontext->tdn; 1524 u16 uid = to_mpd(pd)->uid; 1525 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1526 1527 if (qp->sq.wqe_cnt) { 1528 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1529 if (err) 1530 return err; 1531 1532 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); 1533 if (err) 1534 goto err_destroy_tis; 1535 1536 if (uid) { 1537 resp->tisn = sq->tisn; 1538 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1539 resp->sqn = sq->base.mqp.qpn; 1540 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1541 } 1542 1543 sq->base.container_mibqp = qp; 1544 sq->base.mqp.event = mlx5_ib_qp_event; 1545 } 1546 1547 if (qp->rq.wqe_cnt) { 1548 rq->base.container_mibqp = qp; 1549 1550 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1551 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1552 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1553 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1554 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1555 if (err) 1556 goto err_destroy_sq; 1557 1558 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1559 out); 1560 if (err) 1561 goto err_destroy_rq; 1562 1563 if (uid) { 1564 resp->rqn = rq->base.mqp.qpn; 1565 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1566 resp->tirn = rq->tirn; 1567 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1568 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1569 resp->tir_icm_addr = MLX5_GET( 1570 create_tir_out, out, icm_address_31_0); 1571 resp->tir_icm_addr |= 1572 (u64)MLX5_GET(create_tir_out, out, 1573 icm_address_39_32) 1574 << 32; 1575 resp->tir_icm_addr |= 1576 (u64)MLX5_GET(create_tir_out, out, 1577 icm_address_63_40) 1578 << 40; 1579 resp->comp_mask |= 1580 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1581 } 1582 } 1583 } 1584 1585 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1586 rq->base.mqp.qpn; 1587 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1588 if (err) 1589 goto err_destroy_tir; 1590 1591 return 0; 1592 1593 err_destroy_tir: 1594 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); 1595 err_destroy_rq: 1596 destroy_raw_packet_qp_rq(dev, rq); 1597 err_destroy_sq: 1598 if (!qp->sq.wqe_cnt) 1599 return err; 1600 destroy_raw_packet_qp_sq(dev, sq); 1601 err_destroy_tis: 1602 destroy_raw_packet_qp_tis(dev, sq, pd); 1603 1604 return err; 1605 } 1606 1607 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1608 struct mlx5_ib_qp *qp) 1609 { 1610 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1611 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1612 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1613 1614 if (qp->rq.wqe_cnt) { 1615 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1616 destroy_raw_packet_qp_rq(dev, rq); 1617 } 1618 1619 if (qp->sq.wqe_cnt) { 1620 destroy_raw_packet_qp_sq(dev, sq); 1621 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1622 } 1623 } 1624 1625 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1626 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1627 { 1628 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1629 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1630 1631 sq->sq = &qp->sq; 1632 rq->rq = &qp->rq; 1633 sq->doorbell = &qp->db; 1634 rq->doorbell = &qp->db; 1635 } 1636 1637 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1638 { 1639 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1640 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1641 mlx5_ib_disable_lb(dev, false, true); 1642 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1643 to_mpd(qp->ibqp.pd)->uid); 1644 } 1645 1646 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1647 struct ib_pd *pd, 1648 struct ib_qp_init_attr *init_attr, 1649 struct ib_udata *udata) 1650 { 1651 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1652 udata, struct mlx5_ib_ucontext, ibucontext); 1653 struct mlx5_ib_create_qp_resp resp = {}; 1654 int inlen; 1655 int outlen; 1656 int err; 1657 u32 *in; 1658 u32 *out; 1659 void *tirc; 1660 void *hfso; 1661 u32 selected_fields = 0; 1662 u32 outer_l4; 1663 size_t min_resp_len; 1664 u32 tdn = mucontext->tdn; 1665 struct mlx5_ib_create_qp_rss ucmd = {}; 1666 size_t required_cmd_sz; 1667 u8 lb_flag = 0; 1668 1669 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1670 return -EOPNOTSUPP; 1671 1672 if (init_attr->create_flags || init_attr->send_cq) 1673 return -EINVAL; 1674 1675 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1676 if (udata->outlen < min_resp_len) 1677 return -EINVAL; 1678 1679 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1680 if (udata->inlen < required_cmd_sz) { 1681 mlx5_ib_dbg(dev, "invalid inlen\n"); 1682 return -EINVAL; 1683 } 1684 1685 if (udata->inlen > sizeof(ucmd) && 1686 !ib_is_udata_cleared(udata, sizeof(ucmd), 1687 udata->inlen - sizeof(ucmd))) { 1688 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1689 return -EOPNOTSUPP; 1690 } 1691 1692 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1693 mlx5_ib_dbg(dev, "copy failed\n"); 1694 return -EFAULT; 1695 } 1696 1697 if (ucmd.comp_mask) { 1698 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1699 return -EOPNOTSUPP; 1700 } 1701 1702 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1703 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1704 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { 1705 mlx5_ib_dbg(dev, "invalid flags\n"); 1706 return -EOPNOTSUPP; 1707 } 1708 1709 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1710 !tunnel_offload_supported(dev->mdev)) { 1711 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1712 return -EOPNOTSUPP; 1713 } 1714 1715 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1716 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1717 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1718 return -EOPNOTSUPP; 1719 } 1720 1721 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) { 1722 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1723 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1724 } 1725 1726 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1727 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1728 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1729 } 1730 1731 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1732 if (err) { 1733 mlx5_ib_dbg(dev, "copy failed\n"); 1734 return -EINVAL; 1735 } 1736 1737 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1738 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1739 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1740 if (!in) 1741 return -ENOMEM; 1742 1743 out = in + MLX5_ST_SZ_DW(create_tir_in); 1744 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1745 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1746 MLX5_SET(tirc, tirc, disp_type, 1747 MLX5_TIRC_DISP_TYPE_INDIRECT); 1748 MLX5_SET(tirc, tirc, indirect_table, 1749 init_attr->rwq_ind_tbl->ind_tbl_num); 1750 MLX5_SET(tirc, tirc, transport_domain, tdn); 1751 1752 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1753 1754 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1755 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1756 1757 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1758 1759 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1760 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1761 else 1762 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1763 1764 switch (ucmd.rx_hash_function) { 1765 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1766 { 1767 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1768 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1769 1770 if (len != ucmd.rx_key_len) { 1771 err = -EINVAL; 1772 goto err; 1773 } 1774 1775 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1776 memcpy(rss_key, ucmd.rx_hash_key, len); 1777 break; 1778 } 1779 default: 1780 err = -EOPNOTSUPP; 1781 goto err; 1782 } 1783 1784 if (!ucmd.rx_hash_fields_mask) { 1785 /* special case when this TIR serves as steering entry without hashing */ 1786 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1787 goto create_tir; 1788 err = -EINVAL; 1789 goto err; 1790 } 1791 1792 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1793 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1794 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1795 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1796 err = -EINVAL; 1797 goto err; 1798 } 1799 1800 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1801 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1802 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1803 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1804 MLX5_L3_PROT_TYPE_IPV4); 1805 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1806 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1807 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1808 MLX5_L3_PROT_TYPE_IPV6); 1809 1810 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1811 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1812 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1813 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1814 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1815 1816 /* Check that only one l4 protocol is set */ 1817 if (outer_l4 & (outer_l4 - 1)) { 1818 err = -EINVAL; 1819 goto err; 1820 } 1821 1822 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1823 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1824 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1825 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1826 MLX5_L4_PROT_TYPE_TCP); 1827 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1828 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1829 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1830 MLX5_L4_PROT_TYPE_UDP); 1831 1832 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1833 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1834 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1835 1836 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1837 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1838 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1839 1840 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1841 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1842 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1843 1844 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1845 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1846 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1847 1848 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1849 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1850 1851 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1852 1853 create_tir: 1854 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1855 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1856 1857 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1858 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1859 err = mlx5_ib_enable_lb(dev, false, true); 1860 1861 if (err) 1862 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1863 to_mpd(pd)->uid); 1864 } 1865 1866 if (err) 1867 goto err; 1868 1869 if (mucontext->devx_uid) { 1870 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1871 resp.tirn = qp->rss_qp.tirn; 1872 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1873 resp.tir_icm_addr = 1874 MLX5_GET(create_tir_out, out, icm_address_31_0); 1875 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, 1876 icm_address_39_32) 1877 << 32; 1878 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, 1879 icm_address_63_40) 1880 << 40; 1881 resp.comp_mask |= 1882 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1883 } 1884 } 1885 1886 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1887 if (err) 1888 goto err_copy; 1889 1890 kvfree(in); 1891 /* qpn is reserved for that QP */ 1892 qp->trans_qp.base.mqp.qpn = 0; 1893 qp->flags |= MLX5_IB_QP_RSS; 1894 return 0; 1895 1896 err_copy: 1897 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); 1898 err: 1899 kvfree(in); 1900 return err; 1901 } 1902 1903 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, 1904 void *qpc) 1905 { 1906 int rcqe_sz; 1907 1908 if (init_attr->qp_type == MLX5_IB_QPT_DCI) 1909 return; 1910 1911 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1912 1913 if (init_attr->qp_type == MLX5_IB_QPT_DCT) { 1914 if (rcqe_sz == 128) 1915 MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1916 1917 return; 1918 } 1919 1920 MLX5_SET(qpc, qpc, cs_res, 1921 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 1922 MLX5_RES_SCAT_DATA32_CQE); 1923 } 1924 1925 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1926 struct ib_qp_init_attr *init_attr, 1927 struct mlx5_ib_create_qp *ucmd, 1928 void *qpc) 1929 { 1930 enum ib_qp_type qpt = init_attr->qp_type; 1931 int scqe_sz; 1932 bool allow_scat_cqe = false; 1933 1934 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) 1935 return; 1936 1937 if (ucmd) 1938 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1939 1940 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1941 return; 1942 1943 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1944 if (scqe_sz == 128) { 1945 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1946 return; 1947 } 1948 1949 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1950 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1951 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1952 } 1953 1954 static int atomic_size_to_mode(int size_mask) 1955 { 1956 /* driver does not support atomic_size > 256B 1957 * and does not know how to translate bigger sizes 1958 */ 1959 int supported_size_mask = size_mask & 0x1ff; 1960 int log_max_size; 1961 1962 if (!supported_size_mask) 1963 return -EOPNOTSUPP; 1964 1965 log_max_size = __fls(supported_size_mask); 1966 1967 if (log_max_size > 3) 1968 return log_max_size; 1969 1970 return MLX5_ATOMIC_MODE_8B; 1971 } 1972 1973 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1974 enum ib_qp_type qp_type) 1975 { 1976 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1977 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1978 int atomic_mode = -EOPNOTSUPP; 1979 int atomic_size_mask; 1980 1981 if (!atomic) 1982 return -EOPNOTSUPP; 1983 1984 if (qp_type == MLX5_IB_QPT_DCT) 1985 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1986 else 1987 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1988 1989 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1990 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1991 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1992 1993 if (atomic_mode <= 0 && 1994 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1995 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1996 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1997 1998 return atomic_mode; 1999 } 2000 2001 static inline bool check_flags_mask(uint64_t input, uint64_t supported) 2002 { 2003 return (input & ~supported) == 0; 2004 } 2005 2006 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2007 struct ib_qp_init_attr *init_attr, 2008 struct ib_udata *udata, struct mlx5_ib_qp *qp) 2009 { 2010 struct mlx5_ib_resources *devr = &dev->devr; 2011 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2012 struct mlx5_core_dev *mdev = dev->mdev; 2013 struct mlx5_ib_create_qp_resp resp = {}; 2014 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2015 udata, struct mlx5_ib_ucontext, ibucontext); 2016 struct mlx5_ib_cq *send_cq; 2017 struct mlx5_ib_cq *recv_cq; 2018 unsigned long flags; 2019 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2020 struct mlx5_ib_create_qp ucmd; 2021 struct mlx5_ib_qp_base *base; 2022 int mlx5_st; 2023 void *qpc; 2024 u32 *in; 2025 int err; 2026 2027 mutex_init(&qp->mutex); 2028 spin_lock_init(&qp->sq.lock); 2029 spin_lock_init(&qp->rq.lock); 2030 2031 mlx5_st = to_mlx5_st(init_attr->qp_type); 2032 if (mlx5_st < 0) 2033 return -EINVAL; 2034 2035 if (init_attr->rwq_ind_tbl) { 2036 if (!udata) 2037 return -ENOSYS; 2038 2039 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 2040 return err; 2041 } 2042 2043 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 2044 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 2045 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 2046 return -EINVAL; 2047 } else { 2048 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 2049 } 2050 } 2051 2052 if (init_attr->create_flags & 2053 (IB_QP_CREATE_CROSS_CHANNEL | 2054 IB_QP_CREATE_MANAGED_SEND | 2055 IB_QP_CREATE_MANAGED_RECV)) { 2056 if (!MLX5_CAP_GEN(mdev, cd)) { 2057 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 2058 return -EINVAL; 2059 } 2060 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 2061 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 2062 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 2063 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 2064 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 2065 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 2066 } 2067 2068 if (init_attr->qp_type == IB_QPT_UD && 2069 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 2070 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 2071 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 2072 return -EOPNOTSUPP; 2073 } 2074 2075 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 2076 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2077 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 2078 return -EOPNOTSUPP; 2079 } 2080 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 2081 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 2082 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 2083 return -EOPNOTSUPP; 2084 } 2085 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 2086 } 2087 2088 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2089 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2090 2091 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 2092 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 2093 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 2094 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 2095 return -EOPNOTSUPP; 2096 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 2097 } 2098 2099 if (udata) { 2100 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 2101 mlx5_ib_dbg(dev, "copy failed\n"); 2102 return -EFAULT; 2103 } 2104 2105 if (!check_flags_mask(ucmd.flags, 2106 MLX5_QP_FLAG_ALLOW_SCATTER_CQE | 2107 MLX5_QP_FLAG_BFREG_INDEX | 2108 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE | 2109 MLX5_QP_FLAG_SCATTER_CQE | 2110 MLX5_QP_FLAG_SIGNATURE | 2111 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC | 2112 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2113 MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2114 MLX5_QP_FLAG_UAR_PAGE_INDEX | 2115 MLX5_QP_FLAG_TYPE_DCI | 2116 MLX5_QP_FLAG_TYPE_DCT)) 2117 return -EINVAL; 2118 2119 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx); 2120 if (err) 2121 return err; 2122 2123 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 2124 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) 2125 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 2126 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 2127 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 2128 !tunnel_offload_supported(mdev)) { 2129 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 2130 return -EOPNOTSUPP; 2131 } 2132 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; 2133 } 2134 2135 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { 2136 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2137 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); 2138 return -EOPNOTSUPP; 2139 } 2140 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 2141 } 2142 2143 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 2144 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2145 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); 2146 return -EOPNOTSUPP; 2147 } 2148 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 2149 } 2150 2151 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { 2152 if (init_attr->qp_type != IB_QPT_RC || 2153 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { 2154 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); 2155 return -EOPNOTSUPP; 2156 } 2157 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; 2158 } 2159 2160 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 2161 if (init_attr->qp_type != IB_QPT_UD || 2162 (MLX5_CAP_GEN(dev->mdev, port_type) != 2163 MLX5_CAP_PORT_TYPE_IB) || 2164 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 2165 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 2166 return -EOPNOTSUPP; 2167 } 2168 2169 qp->flags |= MLX5_IB_QP_UNDERLAY; 2170 qp->underlay_qpn = init_attr->source_qpn; 2171 } 2172 } else { 2173 qp->wq_sig = !!wq_signature; 2174 } 2175 2176 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2177 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2178 &qp->raw_packet_qp.rq.base : 2179 &qp->trans_qp.base; 2180 2181 qp->has_rq = qp_has_rq(init_attr); 2182 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 2183 qp, udata ? &ucmd : NULL); 2184 if (err) { 2185 mlx5_ib_dbg(dev, "err %d\n", err); 2186 return err; 2187 } 2188 2189 if (pd) { 2190 if (udata) { 2191 __u32 max_wqes = 2192 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 2193 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 2194 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 2195 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 2196 mlx5_ib_dbg(dev, "invalid rq params\n"); 2197 return -EINVAL; 2198 } 2199 if (ucmd.sq_wqe_count > max_wqes) { 2200 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 2201 ucmd.sq_wqe_count, max_wqes); 2202 return -EINVAL; 2203 } 2204 if (init_attr->create_flags & 2205 MLX5_IB_QP_CREATE_SQPN_QP1) { 2206 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 2207 return -EINVAL; 2208 } 2209 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 2210 &resp, &inlen, base); 2211 if (err) 2212 mlx5_ib_dbg(dev, "err %d\n", err); 2213 } else { 2214 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 2215 base); 2216 if (err) 2217 mlx5_ib_dbg(dev, "err %d\n", err); 2218 } 2219 2220 if (err) 2221 return err; 2222 } else { 2223 in = kvzalloc(inlen, GFP_KERNEL); 2224 if (!in) 2225 return -ENOMEM; 2226 2227 qp->create_type = MLX5_QP_EMPTY; 2228 } 2229 2230 if (is_sqp(init_attr->qp_type)) 2231 qp->port = init_attr->port_num; 2232 2233 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2234 2235 MLX5_SET(qpc, qpc, st, mlx5_st); 2236 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2237 2238 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 2239 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2240 else 2241 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2242 2243 2244 if (qp->wq_sig) 2245 MLX5_SET(qpc, qpc, wq_signature, 1); 2246 2247 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2248 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2249 2250 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 2251 MLX5_SET(qpc, qpc, cd_master, 1); 2252 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 2253 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2254 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 2255 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2256 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) 2257 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2258 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 2259 configure_responder_scat_cqe(init_attr, qpc); 2260 configure_requester_scat_cqe(dev, init_attr, 2261 udata ? &ucmd : NULL, 2262 qpc); 2263 } 2264 2265 if (qp->rq.wqe_cnt) { 2266 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2267 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2268 } 2269 2270 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2271 2272 if (qp->sq.wqe_cnt) { 2273 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2274 } else { 2275 MLX5_SET(qpc, qpc, no_sq, 1); 2276 if (init_attr->srq && 2277 init_attr->srq->srq_type == IB_SRQT_TM) 2278 MLX5_SET(qpc, qpc, offload_type, 2279 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2280 } 2281 2282 /* Set default resources */ 2283 switch (init_attr->qp_type) { 2284 case IB_QPT_XRC_TGT: 2285 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2286 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2287 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2288 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 2289 break; 2290 case IB_QPT_XRC_INI: 2291 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2292 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2293 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2294 break; 2295 default: 2296 if (init_attr->srq) { 2297 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2298 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2299 } else { 2300 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2301 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2302 } 2303 } 2304 2305 if (init_attr->send_cq) 2306 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2307 2308 if (init_attr->recv_cq) 2309 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2310 2311 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2312 2313 /* 0xffffff means we ask to work with cqe version 0 */ 2314 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2315 MLX5_SET(qpc, qpc, user_index, uidx); 2316 2317 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2318 if (init_attr->qp_type == IB_QPT_UD && 2319 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 2320 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2321 qp->flags |= MLX5_IB_QP_LSO; 2322 } 2323 2324 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2325 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 2326 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 2327 err = -EOPNOTSUPP; 2328 goto err; 2329 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2330 MLX5_SET(qpc, qpc, end_padding_mode, 2331 MLX5_WQ_END_PAD_MODE_ALIGN); 2332 } else { 2333 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 2334 } 2335 } 2336 2337 if (inlen < 0) { 2338 err = -EINVAL; 2339 goto err; 2340 } 2341 2342 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2343 qp->flags & MLX5_IB_QP_UNDERLAY) { 2344 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 2345 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2346 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2347 &resp); 2348 } else { 2349 err = mlx5_core_create_qp(dev, &base->mqp, in, inlen); 2350 } 2351 2352 if (err) { 2353 mlx5_ib_dbg(dev, "create qp failed\n"); 2354 goto err_create; 2355 } 2356 2357 kvfree(in); 2358 2359 base->container_mibqp = qp; 2360 base->mqp.event = mlx5_ib_qp_event; 2361 2362 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 2363 &send_cq, &recv_cq); 2364 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2365 mlx5_ib_lock_cqs(send_cq, recv_cq); 2366 /* Maintain device to QPs access, needed for further handling via reset 2367 * flow 2368 */ 2369 list_add_tail(&qp->qps_list, &dev->qp_list); 2370 /* Maintain CQ to QPs access, needed for further handling via reset flow 2371 */ 2372 if (send_cq) 2373 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2374 if (recv_cq) 2375 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2376 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2377 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2378 2379 return 0; 2380 2381 err_create: 2382 if (qp->create_type == MLX5_QP_USER) 2383 destroy_qp_user(dev, pd, qp, base, udata); 2384 else if (qp->create_type == MLX5_QP_KERNEL) 2385 destroy_qp_kernel(dev, qp); 2386 2387 err: 2388 kvfree(in); 2389 return err; 2390 } 2391 2392 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2393 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2394 { 2395 if (send_cq) { 2396 if (recv_cq) { 2397 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2398 spin_lock(&send_cq->lock); 2399 spin_lock_nested(&recv_cq->lock, 2400 SINGLE_DEPTH_NESTING); 2401 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2402 spin_lock(&send_cq->lock); 2403 __acquire(&recv_cq->lock); 2404 } else { 2405 spin_lock(&recv_cq->lock); 2406 spin_lock_nested(&send_cq->lock, 2407 SINGLE_DEPTH_NESTING); 2408 } 2409 } else { 2410 spin_lock(&send_cq->lock); 2411 __acquire(&recv_cq->lock); 2412 } 2413 } else if (recv_cq) { 2414 spin_lock(&recv_cq->lock); 2415 __acquire(&send_cq->lock); 2416 } else { 2417 __acquire(&send_cq->lock); 2418 __acquire(&recv_cq->lock); 2419 } 2420 } 2421 2422 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2423 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2424 { 2425 if (send_cq) { 2426 if (recv_cq) { 2427 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2428 spin_unlock(&recv_cq->lock); 2429 spin_unlock(&send_cq->lock); 2430 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2431 __release(&recv_cq->lock); 2432 spin_unlock(&send_cq->lock); 2433 } else { 2434 spin_unlock(&send_cq->lock); 2435 spin_unlock(&recv_cq->lock); 2436 } 2437 } else { 2438 __release(&recv_cq->lock); 2439 spin_unlock(&send_cq->lock); 2440 } 2441 } else if (recv_cq) { 2442 __release(&send_cq->lock); 2443 spin_unlock(&recv_cq->lock); 2444 } else { 2445 __release(&recv_cq->lock); 2446 __release(&send_cq->lock); 2447 } 2448 } 2449 2450 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2451 { 2452 return to_mpd(qp->ibqp.pd); 2453 } 2454 2455 static void get_cqs(enum ib_qp_type qp_type, 2456 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2457 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2458 { 2459 switch (qp_type) { 2460 case IB_QPT_XRC_TGT: 2461 *send_cq = NULL; 2462 *recv_cq = NULL; 2463 break; 2464 case MLX5_IB_QPT_REG_UMR: 2465 case IB_QPT_XRC_INI: 2466 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2467 *recv_cq = NULL; 2468 break; 2469 2470 case IB_QPT_SMI: 2471 case MLX5_IB_QPT_HW_GSI: 2472 case IB_QPT_RC: 2473 case IB_QPT_UC: 2474 case IB_QPT_UD: 2475 case IB_QPT_RAW_IPV6: 2476 case IB_QPT_RAW_ETHERTYPE: 2477 case IB_QPT_RAW_PACKET: 2478 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2479 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2480 break; 2481 2482 case IB_QPT_MAX: 2483 default: 2484 *send_cq = NULL; 2485 *recv_cq = NULL; 2486 break; 2487 } 2488 } 2489 2490 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2491 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2492 u8 lag_tx_affinity); 2493 2494 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2495 struct ib_udata *udata) 2496 { 2497 struct mlx5_ib_cq *send_cq, *recv_cq; 2498 struct mlx5_ib_qp_base *base; 2499 unsigned long flags; 2500 int err; 2501 2502 if (qp->ibqp.rwq_ind_tbl) { 2503 destroy_rss_raw_qp_tir(dev, qp); 2504 return; 2505 } 2506 2507 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2508 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2509 &qp->raw_packet_qp.rq.base : 2510 &qp->trans_qp.base; 2511 2512 if (qp->state != IB_QPS_RESET) { 2513 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2514 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2515 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2516 NULL, &base->mqp); 2517 } else { 2518 struct mlx5_modify_raw_qp_param raw_qp_param = { 2519 .operation = MLX5_CMD_OP_2RST_QP 2520 }; 2521 2522 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2523 } 2524 if (err) 2525 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2526 base->mqp.qpn); 2527 } 2528 2529 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2530 &send_cq, &recv_cq); 2531 2532 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2533 mlx5_ib_lock_cqs(send_cq, recv_cq); 2534 /* del from lists under both locks above to protect reset flow paths */ 2535 list_del(&qp->qps_list); 2536 if (send_cq) 2537 list_del(&qp->cq_send_list); 2538 2539 if (recv_cq) 2540 list_del(&qp->cq_recv_list); 2541 2542 if (qp->create_type == MLX5_QP_KERNEL) { 2543 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2544 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2545 if (send_cq != recv_cq) 2546 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2547 NULL); 2548 } 2549 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2550 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2551 2552 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2553 qp->flags & MLX5_IB_QP_UNDERLAY) { 2554 destroy_raw_packet_qp(dev, qp); 2555 } else { 2556 err = mlx5_core_destroy_qp(dev, &base->mqp); 2557 if (err) 2558 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2559 base->mqp.qpn); 2560 } 2561 2562 if (qp->create_type == MLX5_QP_KERNEL) 2563 destroy_qp_kernel(dev, qp); 2564 else if (qp->create_type == MLX5_QP_USER) 2565 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); 2566 } 2567 2568 static const char *ib_qp_type_str(enum ib_qp_type type) 2569 { 2570 switch (type) { 2571 case IB_QPT_SMI: 2572 return "IB_QPT_SMI"; 2573 case IB_QPT_GSI: 2574 return "IB_QPT_GSI"; 2575 case IB_QPT_RC: 2576 return "IB_QPT_RC"; 2577 case IB_QPT_UC: 2578 return "IB_QPT_UC"; 2579 case IB_QPT_UD: 2580 return "IB_QPT_UD"; 2581 case IB_QPT_RAW_IPV6: 2582 return "IB_QPT_RAW_IPV6"; 2583 case IB_QPT_RAW_ETHERTYPE: 2584 return "IB_QPT_RAW_ETHERTYPE"; 2585 case IB_QPT_XRC_INI: 2586 return "IB_QPT_XRC_INI"; 2587 case IB_QPT_XRC_TGT: 2588 return "IB_QPT_XRC_TGT"; 2589 case IB_QPT_RAW_PACKET: 2590 return "IB_QPT_RAW_PACKET"; 2591 case MLX5_IB_QPT_REG_UMR: 2592 return "MLX5_IB_QPT_REG_UMR"; 2593 case IB_QPT_DRIVER: 2594 return "IB_QPT_DRIVER"; 2595 case IB_QPT_MAX: 2596 default: 2597 return "Invalid QP type"; 2598 } 2599 } 2600 2601 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2602 struct ib_qp_init_attr *attr, 2603 struct mlx5_ib_create_qp *ucmd, 2604 struct ib_udata *udata) 2605 { 2606 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2607 udata, struct mlx5_ib_ucontext, ibucontext); 2608 struct mlx5_ib_qp *qp; 2609 int err = 0; 2610 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2611 void *dctc; 2612 2613 if (!attr->srq || !attr->recv_cq) 2614 return ERR_PTR(-EINVAL); 2615 2616 err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx); 2617 if (err) 2618 return ERR_PTR(err); 2619 2620 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2621 if (!qp) 2622 return ERR_PTR(-ENOMEM); 2623 2624 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2625 if (!qp->dct.in) { 2626 err = -ENOMEM; 2627 goto err_free; 2628 } 2629 2630 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2631 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2632 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2633 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2634 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2635 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2636 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2637 MLX5_SET(dctc, dctc, user_index, uidx); 2638 2639 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) 2640 configure_responder_scat_cqe(attr, dctc); 2641 2642 qp->state = IB_QPS_RESET; 2643 2644 return &qp->ibqp; 2645 err_free: 2646 kfree(qp); 2647 return ERR_PTR(err); 2648 } 2649 2650 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2651 struct ib_qp_init_attr *init_attr, 2652 struct mlx5_ib_create_qp *ucmd, 2653 struct ib_udata *udata) 2654 { 2655 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2656 int err; 2657 2658 if (!udata) 2659 return -EINVAL; 2660 2661 if (udata->inlen < sizeof(*ucmd)) { 2662 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2663 return -EINVAL; 2664 } 2665 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2666 if (err) 2667 return err; 2668 2669 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2670 init_attr->qp_type = MLX5_IB_QPT_DCI; 2671 } else { 2672 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2673 init_attr->qp_type = MLX5_IB_QPT_DCT; 2674 } else { 2675 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2676 return -EINVAL; 2677 } 2678 } 2679 2680 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2681 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2682 return -EOPNOTSUPP; 2683 } 2684 2685 return 0; 2686 } 2687 2688 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2689 struct ib_qp_init_attr *verbs_init_attr, 2690 struct ib_udata *udata) 2691 { 2692 struct mlx5_ib_dev *dev; 2693 struct mlx5_ib_qp *qp; 2694 u16 xrcdn = 0; 2695 int err; 2696 struct ib_qp_init_attr mlx_init_attr; 2697 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2698 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2699 udata, struct mlx5_ib_ucontext, ibucontext); 2700 2701 if (pd) { 2702 dev = to_mdev(pd->device); 2703 2704 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2705 if (!ucontext) { 2706 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2707 return ERR_PTR(-EINVAL); 2708 } else if (!ucontext->cqe_version) { 2709 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2710 return ERR_PTR(-EINVAL); 2711 } 2712 } 2713 } else { 2714 /* being cautious here */ 2715 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2716 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2717 pr_warn("%s: no PD for transport %s\n", __func__, 2718 ib_qp_type_str(init_attr->qp_type)); 2719 return ERR_PTR(-EINVAL); 2720 } 2721 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2722 } 2723 2724 if (init_attr->qp_type == IB_QPT_DRIVER) { 2725 struct mlx5_ib_create_qp ucmd; 2726 2727 init_attr = &mlx_init_attr; 2728 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2729 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2730 if (err) 2731 return ERR_PTR(err); 2732 2733 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2734 if (init_attr->cap.max_recv_wr || 2735 init_attr->cap.max_recv_sge) { 2736 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2737 return ERR_PTR(-EINVAL); 2738 } 2739 } else { 2740 return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata); 2741 } 2742 } 2743 2744 switch (init_attr->qp_type) { 2745 case IB_QPT_XRC_TGT: 2746 case IB_QPT_XRC_INI: 2747 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2748 mlx5_ib_dbg(dev, "XRC not supported\n"); 2749 return ERR_PTR(-ENOSYS); 2750 } 2751 init_attr->recv_cq = NULL; 2752 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2753 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2754 init_attr->send_cq = NULL; 2755 } 2756 2757 /* fall through */ 2758 case IB_QPT_RAW_PACKET: 2759 case IB_QPT_RC: 2760 case IB_QPT_UC: 2761 case IB_QPT_UD: 2762 case IB_QPT_SMI: 2763 case MLX5_IB_QPT_HW_GSI: 2764 case MLX5_IB_QPT_REG_UMR: 2765 case MLX5_IB_QPT_DCI: 2766 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2767 if (!qp) 2768 return ERR_PTR(-ENOMEM); 2769 2770 err = create_qp_common(dev, pd, init_attr, udata, qp); 2771 if (err) { 2772 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2773 kfree(qp); 2774 return ERR_PTR(err); 2775 } 2776 2777 if (is_qp0(init_attr->qp_type)) 2778 qp->ibqp.qp_num = 0; 2779 else if (is_qp1(init_attr->qp_type)) 2780 qp->ibqp.qp_num = 1; 2781 else 2782 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2783 2784 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2785 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2786 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2787 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2788 2789 qp->trans_qp.xrcdn = xrcdn; 2790 2791 break; 2792 2793 case IB_QPT_GSI: 2794 return mlx5_ib_gsi_create_qp(pd, init_attr); 2795 2796 case IB_QPT_RAW_IPV6: 2797 case IB_QPT_RAW_ETHERTYPE: 2798 case IB_QPT_MAX: 2799 default: 2800 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2801 init_attr->qp_type); 2802 /* Don't support raw QPs */ 2803 return ERR_PTR(-EOPNOTSUPP); 2804 } 2805 2806 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2807 qp->qp_sub_type = init_attr->qp_type; 2808 2809 return &qp->ibqp; 2810 } 2811 2812 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2813 { 2814 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2815 2816 if (mqp->state == IB_QPS_RTR) { 2817 int err; 2818 2819 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 2820 if (err) { 2821 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2822 return err; 2823 } 2824 } 2825 2826 kfree(mqp->dct.in); 2827 kfree(mqp); 2828 return 0; 2829 } 2830 2831 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2832 { 2833 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2834 struct mlx5_ib_qp *mqp = to_mqp(qp); 2835 2836 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2837 return mlx5_ib_gsi_destroy_qp(qp); 2838 2839 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2840 return mlx5_ib_destroy_dct(mqp); 2841 2842 destroy_qp_common(dev, mqp, udata); 2843 2844 kfree(mqp); 2845 2846 return 0; 2847 } 2848 2849 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2850 const struct ib_qp_attr *attr, 2851 int attr_mask, __be32 *hw_access_flags_be) 2852 { 2853 u8 dest_rd_atomic; 2854 u32 access_flags, hw_access_flags = 0; 2855 2856 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2857 2858 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2859 dest_rd_atomic = attr->max_dest_rd_atomic; 2860 else 2861 dest_rd_atomic = qp->trans_qp.resp_depth; 2862 2863 if (attr_mask & IB_QP_ACCESS_FLAGS) 2864 access_flags = attr->qp_access_flags; 2865 else 2866 access_flags = qp->trans_qp.atomic_rd_en; 2867 2868 if (!dest_rd_atomic) 2869 access_flags &= IB_ACCESS_REMOTE_WRITE; 2870 2871 if (access_flags & IB_ACCESS_REMOTE_READ) 2872 hw_access_flags |= MLX5_QP_BIT_RRE; 2873 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2874 int atomic_mode; 2875 2876 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2877 if (atomic_mode < 0) 2878 return -EOPNOTSUPP; 2879 2880 hw_access_flags |= MLX5_QP_BIT_RAE; 2881 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; 2882 } 2883 2884 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2885 hw_access_flags |= MLX5_QP_BIT_RWE; 2886 2887 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2888 2889 return 0; 2890 } 2891 2892 enum { 2893 MLX5_PATH_FLAG_FL = 1 << 0, 2894 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2895 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2896 }; 2897 2898 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2899 { 2900 if (rate == IB_RATE_PORT_CURRENT) 2901 return 0; 2902 2903 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 2904 return -EINVAL; 2905 2906 while (rate != IB_RATE_PORT_CURRENT && 2907 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2908 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2909 --rate; 2910 2911 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2912 } 2913 2914 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2915 struct mlx5_ib_sq *sq, u8 sl, 2916 struct ib_pd *pd) 2917 { 2918 void *in; 2919 void *tisc; 2920 int inlen; 2921 int err; 2922 2923 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2924 in = kvzalloc(inlen, GFP_KERNEL); 2925 if (!in) 2926 return -ENOMEM; 2927 2928 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2929 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2930 2931 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2932 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2933 2934 err = mlx5_core_modify_tis(dev, sq->tisn, in); 2935 2936 kvfree(in); 2937 2938 return err; 2939 } 2940 2941 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2942 struct mlx5_ib_sq *sq, u8 tx_affinity, 2943 struct ib_pd *pd) 2944 { 2945 void *in; 2946 void *tisc; 2947 int inlen; 2948 int err; 2949 2950 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2951 in = kvzalloc(inlen, GFP_KERNEL); 2952 if (!in) 2953 return -ENOMEM; 2954 2955 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2956 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2957 2958 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2959 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2960 2961 err = mlx5_core_modify_tis(dev, sq->tisn, in); 2962 2963 kvfree(in); 2964 2965 return err; 2966 } 2967 2968 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2969 const struct rdma_ah_attr *ah, 2970 struct mlx5_qp_path *path, u8 port, int attr_mask, 2971 u32 path_flags, const struct ib_qp_attr *attr, 2972 bool alt) 2973 { 2974 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2975 int err; 2976 enum ib_gid_type gid_type; 2977 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2978 u8 sl = rdma_ah_get_sl(ah); 2979 2980 if (attr_mask & IB_QP_PKEY_INDEX) 2981 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2982 attr->pkey_index); 2983 2984 if (ah_flags & IB_AH_GRH) { 2985 if (grh->sgid_index >= 2986 dev->mdev->port_caps[port - 1].gid_table_len) { 2987 pr_err("sgid_index (%u) too large. max is %d\n", 2988 grh->sgid_index, 2989 dev->mdev->port_caps[port - 1].gid_table_len); 2990 return -EINVAL; 2991 } 2992 } 2993 2994 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2995 if (!(ah_flags & IB_AH_GRH)) 2996 return -EINVAL; 2997 2998 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2999 if (qp->ibqp.qp_type == IB_QPT_RC || 3000 qp->ibqp.qp_type == IB_QPT_UC || 3001 qp->ibqp.qp_type == IB_QPT_XRC_INI || 3002 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 3003 path->udp_sport = 3004 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); 3005 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 3006 gid_type = ah->grh.sgid_attr->gid_type; 3007 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3008 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 3009 } else { 3010 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 3011 path->fl_free_ar |= 3012 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 3013 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 3014 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 3015 if (ah_flags & IB_AH_GRH) 3016 path->grh_mlid |= 1 << 7; 3017 path->dci_cfi_prio_sl = sl & 0xf; 3018 } 3019 3020 if (ah_flags & IB_AH_GRH) { 3021 path->mgid_index = grh->sgid_index; 3022 path->hop_limit = grh->hop_limit; 3023 path->tclass_flowlabel = 3024 cpu_to_be32((grh->traffic_class << 20) | 3025 (grh->flow_label)); 3026 memcpy(path->rgid, grh->dgid.raw, 16); 3027 } 3028 3029 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3030 if (err < 0) 3031 return err; 3032 path->static_rate = err; 3033 path->port = port; 3034 3035 if (attr_mask & IB_QP_TIMEOUT) 3036 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 3037 3038 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3039 return modify_raw_packet_eth_prio(dev->mdev, 3040 &qp->raw_packet_qp.sq, 3041 sl & 0xf, qp->ibqp.pd); 3042 3043 return 0; 3044 } 3045 3046 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3047 [MLX5_QP_STATE_INIT] = { 3048 [MLX5_QP_STATE_INIT] = { 3049 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3050 MLX5_QP_OPTPAR_RAE | 3051 MLX5_QP_OPTPAR_RWE | 3052 MLX5_QP_OPTPAR_PKEY_INDEX | 3053 MLX5_QP_OPTPAR_PRI_PORT, 3054 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3055 MLX5_QP_OPTPAR_PKEY_INDEX | 3056 MLX5_QP_OPTPAR_PRI_PORT, 3057 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3058 MLX5_QP_OPTPAR_Q_KEY | 3059 MLX5_QP_OPTPAR_PRI_PORT, 3060 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3061 MLX5_QP_OPTPAR_RAE | 3062 MLX5_QP_OPTPAR_RWE | 3063 MLX5_QP_OPTPAR_PKEY_INDEX | 3064 MLX5_QP_OPTPAR_PRI_PORT, 3065 }, 3066 [MLX5_QP_STATE_RTR] = { 3067 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3068 MLX5_QP_OPTPAR_RRE | 3069 MLX5_QP_OPTPAR_RAE | 3070 MLX5_QP_OPTPAR_RWE | 3071 MLX5_QP_OPTPAR_PKEY_INDEX, 3072 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3073 MLX5_QP_OPTPAR_RWE | 3074 MLX5_QP_OPTPAR_PKEY_INDEX, 3075 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3076 MLX5_QP_OPTPAR_Q_KEY, 3077 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3078 MLX5_QP_OPTPAR_Q_KEY, 3079 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3080 MLX5_QP_OPTPAR_RRE | 3081 MLX5_QP_OPTPAR_RAE | 3082 MLX5_QP_OPTPAR_RWE | 3083 MLX5_QP_OPTPAR_PKEY_INDEX, 3084 }, 3085 }, 3086 [MLX5_QP_STATE_RTR] = { 3087 [MLX5_QP_STATE_RTS] = { 3088 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3089 MLX5_QP_OPTPAR_RRE | 3090 MLX5_QP_OPTPAR_RAE | 3091 MLX5_QP_OPTPAR_RWE | 3092 MLX5_QP_OPTPAR_PM_STATE | 3093 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3094 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3095 MLX5_QP_OPTPAR_RWE | 3096 MLX5_QP_OPTPAR_PM_STATE, 3097 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3098 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3099 MLX5_QP_OPTPAR_RRE | 3100 MLX5_QP_OPTPAR_RAE | 3101 MLX5_QP_OPTPAR_RWE | 3102 MLX5_QP_OPTPAR_PM_STATE | 3103 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3104 }, 3105 }, 3106 [MLX5_QP_STATE_RTS] = { 3107 [MLX5_QP_STATE_RTS] = { 3108 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3109 MLX5_QP_OPTPAR_RAE | 3110 MLX5_QP_OPTPAR_RWE | 3111 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3112 MLX5_QP_OPTPAR_PM_STATE | 3113 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3114 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3115 MLX5_QP_OPTPAR_PM_STATE | 3116 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3117 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3118 MLX5_QP_OPTPAR_SRQN | 3119 MLX5_QP_OPTPAR_CQN_RCV, 3120 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3121 MLX5_QP_OPTPAR_RAE | 3122 MLX5_QP_OPTPAR_RWE | 3123 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3124 MLX5_QP_OPTPAR_PM_STATE | 3125 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3126 }, 3127 }, 3128 [MLX5_QP_STATE_SQER] = { 3129 [MLX5_QP_STATE_RTS] = { 3130 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3131 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3132 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3133 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3134 MLX5_QP_OPTPAR_RWE | 3135 MLX5_QP_OPTPAR_RAE | 3136 MLX5_QP_OPTPAR_RRE, 3137 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3138 MLX5_QP_OPTPAR_RWE | 3139 MLX5_QP_OPTPAR_RAE | 3140 MLX5_QP_OPTPAR_RRE, 3141 }, 3142 }, 3143 }; 3144 3145 static int ib_nr_to_mlx5_nr(int ib_mask) 3146 { 3147 switch (ib_mask) { 3148 case IB_QP_STATE: 3149 return 0; 3150 case IB_QP_CUR_STATE: 3151 return 0; 3152 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3153 return 0; 3154 case IB_QP_ACCESS_FLAGS: 3155 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3156 MLX5_QP_OPTPAR_RAE; 3157 case IB_QP_PKEY_INDEX: 3158 return MLX5_QP_OPTPAR_PKEY_INDEX; 3159 case IB_QP_PORT: 3160 return MLX5_QP_OPTPAR_PRI_PORT; 3161 case IB_QP_QKEY: 3162 return MLX5_QP_OPTPAR_Q_KEY; 3163 case IB_QP_AV: 3164 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3165 MLX5_QP_OPTPAR_PRI_PORT; 3166 case IB_QP_PATH_MTU: 3167 return 0; 3168 case IB_QP_TIMEOUT: 3169 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3170 case IB_QP_RETRY_CNT: 3171 return MLX5_QP_OPTPAR_RETRY_COUNT; 3172 case IB_QP_RNR_RETRY: 3173 return MLX5_QP_OPTPAR_RNR_RETRY; 3174 case IB_QP_RQ_PSN: 3175 return 0; 3176 case IB_QP_MAX_QP_RD_ATOMIC: 3177 return MLX5_QP_OPTPAR_SRA_MAX; 3178 case IB_QP_ALT_PATH: 3179 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3180 case IB_QP_MIN_RNR_TIMER: 3181 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3182 case IB_QP_SQ_PSN: 3183 return 0; 3184 case IB_QP_MAX_DEST_RD_ATOMIC: 3185 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3186 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3187 case IB_QP_PATH_MIG_STATE: 3188 return MLX5_QP_OPTPAR_PM_STATE; 3189 case IB_QP_CAP: 3190 return 0; 3191 case IB_QP_DEST_QPN: 3192 return 0; 3193 } 3194 return 0; 3195 } 3196 3197 static int ib_mask_to_mlx5_opt(int ib_mask) 3198 { 3199 int result = 0; 3200 int i; 3201 3202 for (i = 0; i < 8 * sizeof(int); i++) { 3203 if ((1 << i) & ib_mask) 3204 result |= ib_nr_to_mlx5_nr(1 << i); 3205 } 3206 3207 return result; 3208 } 3209 3210 static int modify_raw_packet_qp_rq( 3211 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3212 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3213 { 3214 void *in; 3215 void *rqc; 3216 int inlen; 3217 int err; 3218 3219 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3220 in = kvzalloc(inlen, GFP_KERNEL); 3221 if (!in) 3222 return -ENOMEM; 3223 3224 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3225 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3226 3227 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3228 MLX5_SET(rqc, rqc, state, new_state); 3229 3230 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3231 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3232 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3233 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3234 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3235 } else 3236 dev_info_once( 3237 &dev->ib_dev.dev, 3238 "RAW PACKET QP counters are not supported on current FW\n"); 3239 } 3240 3241 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3242 if (err) 3243 goto out; 3244 3245 rq->state = new_state; 3246 3247 out: 3248 kvfree(in); 3249 return err; 3250 } 3251 3252 static int modify_raw_packet_qp_sq( 3253 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3254 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3255 { 3256 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3257 struct mlx5_rate_limit old_rl = ibqp->rl; 3258 struct mlx5_rate_limit new_rl = old_rl; 3259 bool new_rate_added = false; 3260 u16 rl_index = 0; 3261 void *in; 3262 void *sqc; 3263 int inlen; 3264 int err; 3265 3266 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3267 in = kvzalloc(inlen, GFP_KERNEL); 3268 if (!in) 3269 return -ENOMEM; 3270 3271 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3272 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3273 3274 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3275 MLX5_SET(sqc, sqc, state, new_state); 3276 3277 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3278 if (new_state != MLX5_SQC_STATE_RDY) 3279 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3280 __func__); 3281 else 3282 new_rl = raw_qp_param->rl; 3283 } 3284 3285 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3286 if (new_rl.rate) { 3287 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3288 if (err) { 3289 pr_err("Failed configuring rate limit(err %d): \ 3290 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3291 err, new_rl.rate, new_rl.max_burst_sz, 3292 new_rl.typical_pkt_sz); 3293 3294 goto out; 3295 } 3296 new_rate_added = true; 3297 } 3298 3299 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3300 /* index 0 means no limit */ 3301 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3302 } 3303 3304 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3305 if (err) { 3306 /* Remove new rate from table if failed */ 3307 if (new_rate_added) 3308 mlx5_rl_remove_rate(dev, &new_rl); 3309 goto out; 3310 } 3311 3312 /* Only remove the old rate after new rate was set */ 3313 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3314 (new_state != MLX5_SQC_STATE_RDY)) { 3315 mlx5_rl_remove_rate(dev, &old_rl); 3316 if (new_state != MLX5_SQC_STATE_RDY) 3317 memset(&new_rl, 0, sizeof(new_rl)); 3318 } 3319 3320 ibqp->rl = new_rl; 3321 sq->state = new_state; 3322 3323 out: 3324 kvfree(in); 3325 return err; 3326 } 3327 3328 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3329 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3330 u8 tx_affinity) 3331 { 3332 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3333 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3334 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3335 int modify_rq = !!qp->rq.wqe_cnt; 3336 int modify_sq = !!qp->sq.wqe_cnt; 3337 int rq_state; 3338 int sq_state; 3339 int err; 3340 3341 switch (raw_qp_param->operation) { 3342 case MLX5_CMD_OP_RST2INIT_QP: 3343 rq_state = MLX5_RQC_STATE_RDY; 3344 sq_state = MLX5_SQC_STATE_RDY; 3345 break; 3346 case MLX5_CMD_OP_2ERR_QP: 3347 rq_state = MLX5_RQC_STATE_ERR; 3348 sq_state = MLX5_SQC_STATE_ERR; 3349 break; 3350 case MLX5_CMD_OP_2RST_QP: 3351 rq_state = MLX5_RQC_STATE_RST; 3352 sq_state = MLX5_SQC_STATE_RST; 3353 break; 3354 case MLX5_CMD_OP_RTR2RTS_QP: 3355 case MLX5_CMD_OP_RTS2RTS_QP: 3356 if (raw_qp_param->set_mask == 3357 MLX5_RAW_QP_RATE_LIMIT) { 3358 modify_rq = 0; 3359 sq_state = sq->state; 3360 } else { 3361 return raw_qp_param->set_mask ? -EINVAL : 0; 3362 } 3363 break; 3364 case MLX5_CMD_OP_INIT2INIT_QP: 3365 case MLX5_CMD_OP_INIT2RTR_QP: 3366 if (raw_qp_param->set_mask) 3367 return -EINVAL; 3368 else 3369 return 0; 3370 default: 3371 WARN_ON(1); 3372 return -EINVAL; 3373 } 3374 3375 if (modify_rq) { 3376 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3377 qp->ibqp.pd); 3378 if (err) 3379 return err; 3380 } 3381 3382 if (modify_sq) { 3383 struct mlx5_flow_handle *flow_rule; 3384 3385 if (tx_affinity) { 3386 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3387 tx_affinity, 3388 qp->ibqp.pd); 3389 if (err) 3390 return err; 3391 } 3392 3393 flow_rule = create_flow_rule_vport_sq(dev, sq, 3394 raw_qp_param->port); 3395 if (IS_ERR(flow_rule)) 3396 return PTR_ERR(flow_rule); 3397 3398 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3399 raw_qp_param, qp->ibqp.pd); 3400 if (err) { 3401 if (flow_rule) 3402 mlx5_del_flow_rules(flow_rule); 3403 return err; 3404 } 3405 3406 if (flow_rule) { 3407 destroy_flow_rule_vport_sq(sq); 3408 sq->flow_rule = flow_rule; 3409 } 3410 3411 return err; 3412 } 3413 3414 return 0; 3415 } 3416 3417 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, 3418 struct mlx5_ib_pd *pd, 3419 struct mlx5_ib_qp_base *qp_base, 3420 u8 port_num, struct ib_udata *udata) 3421 { 3422 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3423 udata, struct mlx5_ib_ucontext, ibucontext); 3424 unsigned int tx_port_affinity; 3425 3426 if (ucontext) { 3427 tx_port_affinity = (unsigned int)atomic_add_return( 3428 1, &ucontext->tx_port_affinity) % 3429 MLX5_MAX_PORTS + 3430 1; 3431 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3432 tx_port_affinity, qp_base->mqp.qpn, ucontext); 3433 } else { 3434 tx_port_affinity = 3435 (unsigned int)atomic_add_return( 3436 1, &dev->port[port_num].roce.tx_port_affinity) % 3437 MLX5_MAX_PORTS + 3438 1; 3439 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3440 tx_port_affinity, qp_base->mqp.qpn); 3441 } 3442 3443 return tx_port_affinity; 3444 } 3445 3446 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3447 struct rdma_counter *counter) 3448 { 3449 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3450 struct mlx5_ib_qp *mqp = to_mqp(qp); 3451 struct mlx5_qp_context context = {}; 3452 struct mlx5_ib_qp_base *base; 3453 u32 set_id; 3454 3455 if (counter) 3456 set_id = counter->id; 3457 else 3458 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3459 3460 base = &mqp->trans_qp.base; 3461 context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff); 3462 context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24); 3463 return mlx5_core_qp_modify(dev, MLX5_CMD_OP_RTS2RTS_QP, 3464 MLX5_QP_OPTPAR_COUNTER_SET_ID, &context, 3465 &base->mqp); 3466 } 3467 3468 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3469 const struct ib_qp_attr *attr, int attr_mask, 3470 enum ib_qp_state cur_state, 3471 enum ib_qp_state new_state, 3472 const struct mlx5_ib_modify_qp *ucmd, 3473 struct ib_udata *udata) 3474 { 3475 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3476 [MLX5_QP_STATE_RST] = { 3477 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3478 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3479 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3480 }, 3481 [MLX5_QP_STATE_INIT] = { 3482 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3483 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3484 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3485 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3486 }, 3487 [MLX5_QP_STATE_RTR] = { 3488 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3489 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3490 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3491 }, 3492 [MLX5_QP_STATE_RTS] = { 3493 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3494 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3495 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3496 }, 3497 [MLX5_QP_STATE_SQD] = { 3498 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3499 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3500 }, 3501 [MLX5_QP_STATE_SQER] = { 3502 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3503 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3504 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3505 }, 3506 [MLX5_QP_STATE_ERR] = { 3507 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3508 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3509 } 3510 }; 3511 3512 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3513 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3514 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3515 struct mlx5_ib_cq *send_cq, *recv_cq; 3516 struct mlx5_qp_context *context; 3517 struct mlx5_ib_pd *pd; 3518 enum mlx5_qp_state mlx5_cur, mlx5_new; 3519 enum mlx5_qp_optpar optpar; 3520 u32 set_id = 0; 3521 int mlx5_st; 3522 int err; 3523 u16 op; 3524 u8 tx_affinity = 0; 3525 3526 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3527 qp->qp_sub_type : ibqp->qp_type); 3528 if (mlx5_st < 0) 3529 return -EINVAL; 3530 3531 context = kzalloc(sizeof(*context), GFP_KERNEL); 3532 if (!context) 3533 return -ENOMEM; 3534 3535 pd = get_pd(qp); 3536 context->flags = cpu_to_be32(mlx5_st << 16); 3537 3538 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3539 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3540 } else { 3541 switch (attr->path_mig_state) { 3542 case IB_MIG_MIGRATED: 3543 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3544 break; 3545 case IB_MIG_REARM: 3546 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3547 break; 3548 case IB_MIG_ARMED: 3549 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3550 break; 3551 } 3552 } 3553 3554 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3555 if ((ibqp->qp_type == IB_QPT_RC) || 3556 (ibqp->qp_type == IB_QPT_UD && 3557 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3558 (ibqp->qp_type == IB_QPT_UC) || 3559 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3560 (ibqp->qp_type == IB_QPT_XRC_INI) || 3561 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3562 if (dev->lag_active) { 3563 u8 p = mlx5_core_native_port_num(dev->mdev) - 1; 3564 tx_affinity = get_tx_affinity(dev, pd, base, p, 3565 udata); 3566 context->flags |= cpu_to_be32(tx_affinity << 24); 3567 } 3568 } 3569 } 3570 3571 if (is_sqp(ibqp->qp_type)) { 3572 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3573 } else if ((ibqp->qp_type == IB_QPT_UD && 3574 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3575 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3576 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3577 } else if (attr_mask & IB_QP_PATH_MTU) { 3578 if (attr->path_mtu < IB_MTU_256 || 3579 attr->path_mtu > IB_MTU_4096) { 3580 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3581 err = -EINVAL; 3582 goto out; 3583 } 3584 context->mtu_msgmax = (attr->path_mtu << 5) | 3585 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3586 } 3587 3588 if (attr_mask & IB_QP_DEST_QPN) 3589 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3590 3591 if (attr_mask & IB_QP_PKEY_INDEX) 3592 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3593 3594 /* todo implement counter_index functionality */ 3595 3596 if (is_sqp(ibqp->qp_type)) 3597 context->pri_path.port = qp->port; 3598 3599 if (attr_mask & IB_QP_PORT) 3600 context->pri_path.port = attr->port_num; 3601 3602 if (attr_mask & IB_QP_AV) { 3603 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3604 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3605 attr_mask, 0, attr, false); 3606 if (err) 3607 goto out; 3608 } 3609 3610 if (attr_mask & IB_QP_TIMEOUT) 3611 context->pri_path.ackto_lt |= attr->timeout << 3; 3612 3613 if (attr_mask & IB_QP_ALT_PATH) { 3614 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3615 &context->alt_path, 3616 attr->alt_port_num, 3617 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3618 0, attr, true); 3619 if (err) 3620 goto out; 3621 } 3622 3623 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3624 &send_cq, &recv_cq); 3625 3626 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3627 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3628 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3629 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3630 3631 if (attr_mask & IB_QP_RNR_RETRY) 3632 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3633 3634 if (attr_mask & IB_QP_RETRY_CNT) 3635 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3636 3637 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3638 if (attr->max_rd_atomic) 3639 context->params1 |= 3640 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3641 } 3642 3643 if (attr_mask & IB_QP_SQ_PSN) 3644 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3645 3646 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3647 if (attr->max_dest_rd_atomic) 3648 context->params2 |= 3649 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3650 } 3651 3652 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3653 __be32 access_flags; 3654 3655 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 3656 if (err) 3657 goto out; 3658 3659 context->params2 |= access_flags; 3660 } 3661 3662 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3663 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3664 3665 if (attr_mask & IB_QP_RQ_PSN) 3666 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3667 3668 if (attr_mask & IB_QP_QKEY) 3669 context->qkey = cpu_to_be32(attr->qkey); 3670 3671 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3672 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3673 3674 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3675 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3676 qp->port) - 1; 3677 3678 /* Underlay port should be used - index 0 function per port */ 3679 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3680 port_num = 0; 3681 3682 if (ibqp->counter) 3683 set_id = ibqp->counter->id; 3684 else 3685 set_id = mlx5_ib_get_counters_id(dev, port_num); 3686 context->qp_counter_set_usr_page |= 3687 cpu_to_be32(set_id << 24); 3688 } 3689 3690 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3691 context->sq_crq_size |= cpu_to_be16(1 << 4); 3692 3693 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3694 context->deth_sqpn = cpu_to_be32(1); 3695 3696 mlx5_cur = to_mlx5_state(cur_state); 3697 mlx5_new = to_mlx5_state(new_state); 3698 3699 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3700 !optab[mlx5_cur][mlx5_new]) { 3701 err = -EINVAL; 3702 goto out; 3703 } 3704 3705 op = optab[mlx5_cur][mlx5_new]; 3706 optpar = ib_mask_to_mlx5_opt(attr_mask); 3707 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3708 3709 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3710 qp->flags & MLX5_IB_QP_UNDERLAY) { 3711 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3712 3713 raw_qp_param.operation = op; 3714 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3715 raw_qp_param.rq_q_ctr_id = set_id; 3716 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3717 } 3718 3719 if (attr_mask & IB_QP_PORT) 3720 raw_qp_param.port = attr->port_num; 3721 3722 if (attr_mask & IB_QP_RATE_LIMIT) { 3723 raw_qp_param.rl.rate = attr->rate_limit; 3724 3725 if (ucmd->burst_info.max_burst_sz) { 3726 if (attr->rate_limit && 3727 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3728 raw_qp_param.rl.max_burst_sz = 3729 ucmd->burst_info.max_burst_sz; 3730 } else { 3731 err = -EINVAL; 3732 goto out; 3733 } 3734 } 3735 3736 if (ucmd->burst_info.typical_pkt_sz) { 3737 if (attr->rate_limit && 3738 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3739 raw_qp_param.rl.typical_pkt_sz = 3740 ucmd->burst_info.typical_pkt_sz; 3741 } else { 3742 err = -EINVAL; 3743 goto out; 3744 } 3745 } 3746 3747 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3748 } 3749 3750 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3751 } else { 3752 err = mlx5_core_qp_modify(dev, op, optpar, context, &base->mqp); 3753 } 3754 3755 if (err) 3756 goto out; 3757 3758 qp->state = new_state; 3759 3760 if (attr_mask & IB_QP_ACCESS_FLAGS) 3761 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3762 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3763 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3764 if (attr_mask & IB_QP_PORT) 3765 qp->port = attr->port_num; 3766 if (attr_mask & IB_QP_ALT_PATH) 3767 qp->trans_qp.alt_port = attr->alt_port_num; 3768 3769 /* 3770 * If we moved a kernel QP to RESET, clean up all old CQ 3771 * entries and reinitialize the QP. 3772 */ 3773 if (new_state == IB_QPS_RESET && 3774 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3775 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3776 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3777 if (send_cq != recv_cq) 3778 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3779 3780 qp->rq.head = 0; 3781 qp->rq.tail = 0; 3782 qp->sq.head = 0; 3783 qp->sq.tail = 0; 3784 qp->sq.cur_post = 0; 3785 if (qp->sq.wqe_cnt) 3786 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 3787 qp->sq.last_poll = 0; 3788 qp->db.db[MLX5_RCV_DBR] = 0; 3789 qp->db.db[MLX5_SND_DBR] = 0; 3790 } 3791 3792 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 3793 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 3794 if (!err) 3795 qp->counter_pending = 0; 3796 } 3797 3798 out: 3799 kfree(context); 3800 return err; 3801 } 3802 3803 static inline bool is_valid_mask(int mask, int req, int opt) 3804 { 3805 if ((mask & req) != req) 3806 return false; 3807 3808 if (mask & ~(req | opt)) 3809 return false; 3810 3811 return true; 3812 } 3813 3814 /* check valid transition for driver QP types 3815 * for now the only QP type that this function supports is DCI 3816 */ 3817 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3818 enum ib_qp_attr_mask attr_mask) 3819 { 3820 int req = IB_QP_STATE; 3821 int opt = 0; 3822 3823 if (new_state == IB_QPS_RESET) { 3824 return is_valid_mask(attr_mask, req, opt); 3825 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3826 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3827 return is_valid_mask(attr_mask, req, opt); 3828 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3829 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3830 return is_valid_mask(attr_mask, req, opt); 3831 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3832 req |= IB_QP_PATH_MTU; 3833 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 3834 return is_valid_mask(attr_mask, req, opt); 3835 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3836 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3837 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3838 opt = IB_QP_MIN_RNR_TIMER; 3839 return is_valid_mask(attr_mask, req, opt); 3840 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3841 opt = IB_QP_MIN_RNR_TIMER; 3842 return is_valid_mask(attr_mask, req, opt); 3843 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3844 return is_valid_mask(attr_mask, req, opt); 3845 } 3846 return false; 3847 } 3848 3849 /* mlx5_ib_modify_dct: modify a DCT QP 3850 * valid transitions are: 3851 * RESET to INIT: must set access_flags, pkey_index and port 3852 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3853 * mtu, gid_index and hop_limit 3854 * Other transitions and attributes are illegal 3855 */ 3856 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3857 int attr_mask, struct ib_udata *udata) 3858 { 3859 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3860 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3861 enum ib_qp_state cur_state, new_state; 3862 int err = 0; 3863 int required = IB_QP_STATE; 3864 void *dctc; 3865 3866 if (!(attr_mask & IB_QP_STATE)) 3867 return -EINVAL; 3868 3869 cur_state = qp->state; 3870 new_state = attr->qp_state; 3871 3872 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3873 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3874 u16 set_id; 3875 3876 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3877 if (!is_valid_mask(attr_mask, required, 0)) 3878 return -EINVAL; 3879 3880 if (attr->port_num == 0 || 3881 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3882 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3883 attr->port_num, dev->num_ports); 3884 return -EINVAL; 3885 } 3886 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3887 MLX5_SET(dctc, dctc, rre, 1); 3888 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3889 MLX5_SET(dctc, dctc, rwe, 1); 3890 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3891 int atomic_mode; 3892 3893 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 3894 if (atomic_mode < 0) 3895 return -EOPNOTSUPP; 3896 3897 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 3898 MLX5_SET(dctc, dctc, rae, 1); 3899 } 3900 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3901 MLX5_SET(dctc, dctc, port, attr->port_num); 3902 3903 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 3904 MLX5_SET(dctc, dctc, counter_set_id, set_id); 3905 3906 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3907 struct mlx5_ib_modify_qp_resp resp = {}; 3908 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0}; 3909 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3910 sizeof(resp.dctn); 3911 3912 if (udata->outlen < min_resp_len) 3913 return -EINVAL; 3914 resp.response_length = min_resp_len; 3915 3916 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3917 if (!is_valid_mask(attr_mask, required, 0)) 3918 return -EINVAL; 3919 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3920 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3921 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3922 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3923 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3924 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3925 3926 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 3927 MLX5_ST_SZ_BYTES(create_dct_in), out, 3928 sizeof(out)); 3929 if (err) 3930 return err; 3931 resp.dctn = qp->dct.mdct.mqp.qpn; 3932 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3933 if (err) { 3934 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 3935 return err; 3936 } 3937 } else { 3938 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3939 return -EINVAL; 3940 } 3941 if (err) 3942 qp->state = IB_QPS_ERR; 3943 else 3944 qp->state = new_state; 3945 return err; 3946 } 3947 3948 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3949 int attr_mask, struct ib_udata *udata) 3950 { 3951 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3952 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3953 struct mlx5_ib_modify_qp ucmd = {}; 3954 enum ib_qp_type qp_type; 3955 enum ib_qp_state cur_state, new_state; 3956 size_t required_cmd_sz; 3957 int err = -EINVAL; 3958 int port; 3959 3960 if (ibqp->rwq_ind_tbl) 3961 return -ENOSYS; 3962 3963 if (udata && udata->inlen) { 3964 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3965 sizeof(ucmd.reserved); 3966 if (udata->inlen < required_cmd_sz) 3967 return -EINVAL; 3968 3969 if (udata->inlen > sizeof(ucmd) && 3970 !ib_is_udata_cleared(udata, sizeof(ucmd), 3971 udata->inlen - sizeof(ucmd))) 3972 return -EOPNOTSUPP; 3973 3974 if (ib_copy_from_udata(&ucmd, udata, 3975 min(udata->inlen, sizeof(ucmd)))) 3976 return -EFAULT; 3977 3978 if (ucmd.comp_mask || 3979 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3980 memchr_inv(&ucmd.burst_info.reserved, 0, 3981 sizeof(ucmd.burst_info.reserved))) 3982 return -EOPNOTSUPP; 3983 } 3984 3985 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3986 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3987 3988 if (ibqp->qp_type == IB_QPT_DRIVER) 3989 qp_type = qp->qp_sub_type; 3990 else 3991 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3992 IB_QPT_GSI : ibqp->qp_type; 3993 3994 if (qp_type == MLX5_IB_QPT_DCT) 3995 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3996 3997 mutex_lock(&qp->mutex); 3998 3999 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4000 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4001 4002 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 4003 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 4004 } 4005 4006 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 4007 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4008 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4009 attr_mask); 4010 goto out; 4011 } 4012 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4013 qp_type != MLX5_IB_QPT_DCI && 4014 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4015 attr_mask)) { 4016 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4017 cur_state, new_state, ibqp->qp_type, attr_mask); 4018 goto out; 4019 } else if (qp_type == MLX5_IB_QPT_DCI && 4020 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4021 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4022 cur_state, new_state, qp_type, attr_mask); 4023 goto out; 4024 } 4025 4026 if ((attr_mask & IB_QP_PORT) && 4027 (attr->port_num == 0 || 4028 attr->port_num > dev->num_ports)) { 4029 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4030 attr->port_num, dev->num_ports); 4031 goto out; 4032 } 4033 4034 if (attr_mask & IB_QP_PKEY_INDEX) { 4035 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 4036 if (attr->pkey_index >= 4037 dev->mdev->port_caps[port - 1].pkey_table_len) { 4038 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 4039 attr->pkey_index); 4040 goto out; 4041 } 4042 } 4043 4044 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4045 attr->max_rd_atomic > 4046 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4047 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4048 attr->max_rd_atomic); 4049 goto out; 4050 } 4051 4052 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4053 attr->max_dest_rd_atomic > 4054 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4055 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4056 attr->max_dest_rd_atomic); 4057 goto out; 4058 } 4059 4060 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4061 err = 0; 4062 goto out; 4063 } 4064 4065 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4066 new_state, &ucmd, udata); 4067 4068 out: 4069 mutex_unlock(&qp->mutex); 4070 return err; 4071 } 4072 4073 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 4074 u32 wqe_sz, void **cur_edge) 4075 { 4076 u32 idx; 4077 4078 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); 4079 *cur_edge = get_sq_edge(sq, idx); 4080 4081 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); 4082 } 4083 4084 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the 4085 * next nearby edge and get new address translation for current WQE position. 4086 * @sq - SQ buffer. 4087 * @seg: Current WQE position (16B aligned). 4088 * @wqe_sz: Total current WQE size [16B]. 4089 * @cur_edge: Updated current edge. 4090 */ 4091 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 4092 u32 wqe_sz, void **cur_edge) 4093 { 4094 if (likely(*seg != *cur_edge)) 4095 return; 4096 4097 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); 4098 } 4099 4100 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's 4101 * pointers. At the end @seg is aligned to 16B regardless the copied size. 4102 * @sq - SQ buffer. 4103 * @cur_edge: Updated current edge. 4104 * @seg: Current WQE position (16B aligned). 4105 * @wqe_sz: Total current WQE size [16B]. 4106 * @src: Pointer to copy from. 4107 * @n: Number of bytes to copy. 4108 */ 4109 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, 4110 void **seg, u32 *wqe_sz, const void *src, 4111 size_t n) 4112 { 4113 while (likely(n)) { 4114 size_t leftlen = *cur_edge - *seg; 4115 size_t copysz = min_t(size_t, leftlen, n); 4116 size_t stride; 4117 4118 memcpy(*seg, src, copysz); 4119 4120 n -= copysz; 4121 src += copysz; 4122 stride = !n ? ALIGN(copysz, 16) : copysz; 4123 *seg += stride; 4124 *wqe_sz += stride >> 4; 4125 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); 4126 } 4127 } 4128 4129 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 4130 { 4131 struct mlx5_ib_cq *cq; 4132 unsigned cur; 4133 4134 cur = wq->head - wq->tail; 4135 if (likely(cur + nreq < wq->max_post)) 4136 return 0; 4137 4138 cq = to_mcq(ib_cq); 4139 spin_lock(&cq->lock); 4140 cur = wq->head - wq->tail; 4141 spin_unlock(&cq->lock); 4142 4143 return cur + nreq >= wq->max_post; 4144 } 4145 4146 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 4147 u64 remote_addr, u32 rkey) 4148 { 4149 rseg->raddr = cpu_to_be64(remote_addr); 4150 rseg->rkey = cpu_to_be32(rkey); 4151 rseg->reserved = 0; 4152 } 4153 4154 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 4155 void **seg, int *size, void **cur_edge) 4156 { 4157 struct mlx5_wqe_eth_seg *eseg = *seg; 4158 4159 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 4160 4161 if (wr->send_flags & IB_SEND_IP_CSUM) 4162 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 4163 MLX5_ETH_WQE_L4_CSUM; 4164 4165 if (wr->opcode == IB_WR_LSO) { 4166 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 4167 size_t left, copysz; 4168 void *pdata = ud_wr->header; 4169 size_t stride; 4170 4171 left = ud_wr->hlen; 4172 eseg->mss = cpu_to_be16(ud_wr->mss); 4173 eseg->inline_hdr.sz = cpu_to_be16(left); 4174 4175 /* memcpy_send_wqe should get a 16B align address. Hence, we 4176 * first copy up to the current edge and then, if needed, 4177 * fall-through to memcpy_send_wqe. 4178 */ 4179 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, 4180 left); 4181 memcpy(eseg->inline_hdr.start, pdata, copysz); 4182 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - 4183 sizeof(eseg->inline_hdr.start) + copysz, 16); 4184 *size += stride / 16; 4185 *seg += stride; 4186 4187 if (copysz < left) { 4188 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4189 left -= copysz; 4190 pdata += copysz; 4191 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, 4192 left); 4193 } 4194 4195 return; 4196 } 4197 4198 *seg += sizeof(struct mlx5_wqe_eth_seg); 4199 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 4200 } 4201 4202 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 4203 const struct ib_send_wr *wr) 4204 { 4205 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 4206 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 4207 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 4208 } 4209 4210 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 4211 { 4212 dseg->byte_count = cpu_to_be32(sg->length); 4213 dseg->lkey = cpu_to_be32(sg->lkey); 4214 dseg->addr = cpu_to_be64(sg->addr); 4215 } 4216 4217 static u64 get_xlt_octo(u64 bytes) 4218 { 4219 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 4220 MLX5_IB_UMR_OCTOWORD; 4221 } 4222 4223 static __be64 frwr_mkey_mask(bool atomic) 4224 { 4225 u64 result; 4226 4227 result = MLX5_MKEY_MASK_LEN | 4228 MLX5_MKEY_MASK_PAGE_SIZE | 4229 MLX5_MKEY_MASK_START_ADDR | 4230 MLX5_MKEY_MASK_EN_RINVAL | 4231 MLX5_MKEY_MASK_KEY | 4232 MLX5_MKEY_MASK_LR | 4233 MLX5_MKEY_MASK_LW | 4234 MLX5_MKEY_MASK_RR | 4235 MLX5_MKEY_MASK_RW | 4236 MLX5_MKEY_MASK_SMALL_FENCE | 4237 MLX5_MKEY_MASK_FREE; 4238 4239 if (atomic) 4240 result |= MLX5_MKEY_MASK_A; 4241 4242 return cpu_to_be64(result); 4243 } 4244 4245 static __be64 sig_mkey_mask(void) 4246 { 4247 u64 result; 4248 4249 result = MLX5_MKEY_MASK_LEN | 4250 MLX5_MKEY_MASK_PAGE_SIZE | 4251 MLX5_MKEY_MASK_START_ADDR | 4252 MLX5_MKEY_MASK_EN_SIGERR | 4253 MLX5_MKEY_MASK_EN_RINVAL | 4254 MLX5_MKEY_MASK_KEY | 4255 MLX5_MKEY_MASK_LR | 4256 MLX5_MKEY_MASK_LW | 4257 MLX5_MKEY_MASK_RR | 4258 MLX5_MKEY_MASK_RW | 4259 MLX5_MKEY_MASK_SMALL_FENCE | 4260 MLX5_MKEY_MASK_FREE | 4261 MLX5_MKEY_MASK_BSF_EN; 4262 4263 return cpu_to_be64(result); 4264 } 4265 4266 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 4267 struct mlx5_ib_mr *mr, u8 flags, bool atomic) 4268 { 4269 int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size; 4270 4271 memset(umr, 0, sizeof(*umr)); 4272 4273 umr->flags = flags; 4274 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4275 umr->mkey_mask = frwr_mkey_mask(atomic); 4276 } 4277 4278 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 4279 { 4280 memset(umr, 0, sizeof(*umr)); 4281 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 4282 umr->flags = MLX5_UMR_INLINE; 4283 } 4284 4285 static __be64 get_umr_enable_mr_mask(void) 4286 { 4287 u64 result; 4288 4289 result = MLX5_MKEY_MASK_KEY | 4290 MLX5_MKEY_MASK_FREE; 4291 4292 return cpu_to_be64(result); 4293 } 4294 4295 static __be64 get_umr_disable_mr_mask(void) 4296 { 4297 u64 result; 4298 4299 result = MLX5_MKEY_MASK_FREE; 4300 4301 return cpu_to_be64(result); 4302 } 4303 4304 static __be64 get_umr_update_translation_mask(void) 4305 { 4306 u64 result; 4307 4308 result = MLX5_MKEY_MASK_LEN | 4309 MLX5_MKEY_MASK_PAGE_SIZE | 4310 MLX5_MKEY_MASK_START_ADDR; 4311 4312 return cpu_to_be64(result); 4313 } 4314 4315 static __be64 get_umr_update_access_mask(int atomic) 4316 { 4317 u64 result; 4318 4319 result = MLX5_MKEY_MASK_LR | 4320 MLX5_MKEY_MASK_LW | 4321 MLX5_MKEY_MASK_RR | 4322 MLX5_MKEY_MASK_RW; 4323 4324 if (atomic) 4325 result |= MLX5_MKEY_MASK_A; 4326 4327 return cpu_to_be64(result); 4328 } 4329 4330 static __be64 get_umr_update_pd_mask(void) 4331 { 4332 u64 result; 4333 4334 result = MLX5_MKEY_MASK_PD; 4335 4336 return cpu_to_be64(result); 4337 } 4338 4339 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 4340 { 4341 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 4342 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 4343 (mask & MLX5_MKEY_MASK_A && 4344 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 4345 return -EPERM; 4346 return 0; 4347 } 4348 4349 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 4350 struct mlx5_wqe_umr_ctrl_seg *umr, 4351 const struct ib_send_wr *wr, int atomic) 4352 { 4353 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4354 4355 memset(umr, 0, sizeof(*umr)); 4356 4357 if (!umrwr->ignore_free_state) { 4358 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 4359 /* fail if free */ 4360 umr->flags = MLX5_UMR_CHECK_FREE; 4361 else 4362 /* fail if not free */ 4363 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 4364 } 4365 4366 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 4367 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 4368 u64 offset = get_xlt_octo(umrwr->offset); 4369 4370 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 4371 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 4372 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 4373 } 4374 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 4375 umr->mkey_mask |= get_umr_update_translation_mask(); 4376 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 4377 umr->mkey_mask |= get_umr_update_access_mask(atomic); 4378 umr->mkey_mask |= get_umr_update_pd_mask(); 4379 } 4380 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 4381 umr->mkey_mask |= get_umr_enable_mr_mask(); 4382 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4383 umr->mkey_mask |= get_umr_disable_mr_mask(); 4384 4385 if (!wr->num_sge) 4386 umr->flags |= MLX5_UMR_INLINE; 4387 4388 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 4389 } 4390 4391 static u8 get_umr_flags(int acc) 4392 { 4393 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 4394 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 4395 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 4396 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 4397 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 4398 } 4399 4400 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 4401 struct mlx5_ib_mr *mr, 4402 u32 key, int access) 4403 { 4404 int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1; 4405 4406 memset(seg, 0, sizeof(*seg)); 4407 4408 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 4409 seg->log2_page_size = ilog2(mr->ibmr.page_size); 4410 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 4411 /* KLMs take twice the size of MTTs */ 4412 ndescs *= 2; 4413 4414 seg->flags = get_umr_flags(access) | mr->access_mode; 4415 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 4416 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 4417 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 4418 seg->len = cpu_to_be64(mr->ibmr.length); 4419 seg->xlt_oct_size = cpu_to_be32(ndescs); 4420 } 4421 4422 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 4423 { 4424 memset(seg, 0, sizeof(*seg)); 4425 seg->status = MLX5_MKEY_STATUS_FREE; 4426 } 4427 4428 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, 4429 const struct ib_send_wr *wr) 4430 { 4431 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4432 4433 memset(seg, 0, sizeof(*seg)); 4434 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4435 seg->status = MLX5_MKEY_STATUS_FREE; 4436 4437 seg->flags = convert_access(umrwr->access_flags); 4438 if (umrwr->pd) 4439 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 4440 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 4441 !umrwr->length) 4442 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 4443 4444 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 4445 seg->len = cpu_to_be64(umrwr->length); 4446 seg->log2_page_size = umrwr->page_shift; 4447 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 4448 mlx5_mkey_variant(umrwr->mkey)); 4449 } 4450 4451 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 4452 struct mlx5_ib_mr *mr, 4453 struct mlx5_ib_pd *pd) 4454 { 4455 int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs); 4456 4457 dseg->addr = cpu_to_be64(mr->desc_map); 4458 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 4459 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 4460 } 4461 4462 static __be32 send_ieth(const struct ib_send_wr *wr) 4463 { 4464 switch (wr->opcode) { 4465 case IB_WR_SEND_WITH_IMM: 4466 case IB_WR_RDMA_WRITE_WITH_IMM: 4467 return wr->ex.imm_data; 4468 4469 case IB_WR_SEND_WITH_INV: 4470 return cpu_to_be32(wr->ex.invalidate_rkey); 4471 4472 default: 4473 return 0; 4474 } 4475 } 4476 4477 static u8 calc_sig(void *wqe, int size) 4478 { 4479 u8 *p = wqe; 4480 u8 res = 0; 4481 int i; 4482 4483 for (i = 0; i < size; i++) 4484 res ^= p[i]; 4485 4486 return ~res; 4487 } 4488 4489 static u8 wq_sig(void *wqe) 4490 { 4491 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 4492 } 4493 4494 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 4495 void **wqe, int *wqe_sz, void **cur_edge) 4496 { 4497 struct mlx5_wqe_inline_seg *seg; 4498 size_t offset; 4499 int inl = 0; 4500 int i; 4501 4502 seg = *wqe; 4503 *wqe += sizeof(*seg); 4504 offset = sizeof(*seg); 4505 4506 for (i = 0; i < wr->num_sge; i++) { 4507 size_t len = wr->sg_list[i].length; 4508 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); 4509 4510 inl += len; 4511 4512 if (unlikely(inl > qp->max_inline_data)) 4513 return -ENOMEM; 4514 4515 while (likely(len)) { 4516 size_t leftlen; 4517 size_t copysz; 4518 4519 handle_post_send_edge(&qp->sq, wqe, 4520 *wqe_sz + (offset >> 4), 4521 cur_edge); 4522 4523 leftlen = *cur_edge - *wqe; 4524 copysz = min_t(size_t, leftlen, len); 4525 4526 memcpy(*wqe, addr, copysz); 4527 len -= copysz; 4528 addr += copysz; 4529 *wqe += copysz; 4530 offset += copysz; 4531 } 4532 } 4533 4534 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 4535 4536 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 4537 4538 return 0; 4539 } 4540 4541 static u16 prot_field_size(enum ib_signature_type type) 4542 { 4543 switch (type) { 4544 case IB_SIG_TYPE_T10_DIF: 4545 return MLX5_DIF_SIZE; 4546 default: 4547 return 0; 4548 } 4549 } 4550 4551 static u8 bs_selector(int block_size) 4552 { 4553 switch (block_size) { 4554 case 512: return 0x1; 4555 case 520: return 0x2; 4556 case 4096: return 0x3; 4557 case 4160: return 0x4; 4558 case 1073741824: return 0x5; 4559 default: return 0; 4560 } 4561 } 4562 4563 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 4564 struct mlx5_bsf_inl *inl) 4565 { 4566 /* Valid inline section and allow BSF refresh */ 4567 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 4568 MLX5_BSF_REFRESH_DIF); 4569 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 4570 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 4571 /* repeating block */ 4572 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 4573 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 4574 MLX5_DIF_CRC : MLX5_DIF_IPCS; 4575 4576 if (domain->sig.dif.ref_remap) 4577 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 4578 4579 if (domain->sig.dif.app_escape) { 4580 if (domain->sig.dif.ref_escape) 4581 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 4582 else 4583 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 4584 } 4585 4586 inl->dif_app_bitmask_check = 4587 cpu_to_be16(domain->sig.dif.apptag_check_mask); 4588 } 4589 4590 static int mlx5_set_bsf(struct ib_mr *sig_mr, 4591 struct ib_sig_attrs *sig_attrs, 4592 struct mlx5_bsf *bsf, u32 data_size) 4593 { 4594 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 4595 struct mlx5_bsf_basic *basic = &bsf->basic; 4596 struct ib_sig_domain *mem = &sig_attrs->mem; 4597 struct ib_sig_domain *wire = &sig_attrs->wire; 4598 4599 memset(bsf, 0, sizeof(*bsf)); 4600 4601 /* Basic + Extended + Inline */ 4602 basic->bsf_size_sbs = 1 << 7; 4603 /* Input domain check byte mask */ 4604 basic->check_byte_mask = sig_attrs->check_mask; 4605 basic->raw_data_size = cpu_to_be32(data_size); 4606 4607 /* Memory domain */ 4608 switch (sig_attrs->mem.sig_type) { 4609 case IB_SIG_TYPE_NONE: 4610 break; 4611 case IB_SIG_TYPE_T10_DIF: 4612 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4613 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4614 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4615 break; 4616 default: 4617 return -EINVAL; 4618 } 4619 4620 /* Wire domain */ 4621 switch (sig_attrs->wire.sig_type) { 4622 case IB_SIG_TYPE_NONE: 4623 break; 4624 case IB_SIG_TYPE_T10_DIF: 4625 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4626 mem->sig_type == wire->sig_type) { 4627 /* Same block structure */ 4628 basic->bsf_size_sbs |= 1 << 4; 4629 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4630 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4631 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4632 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4633 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4634 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4635 } else 4636 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4637 4638 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4639 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4640 break; 4641 default: 4642 return -EINVAL; 4643 } 4644 4645 return 0; 4646 } 4647 4648 static int set_sig_data_segment(const struct ib_send_wr *send_wr, 4649 struct ib_mr *sig_mr, 4650 struct ib_sig_attrs *sig_attrs, 4651 struct mlx5_ib_qp *qp, void **seg, int *size, 4652 void **cur_edge) 4653 { 4654 struct mlx5_bsf *bsf; 4655 u32 data_len; 4656 u32 data_key; 4657 u64 data_va; 4658 u32 prot_len = 0; 4659 u32 prot_key = 0; 4660 u64 prot_va = 0; 4661 bool prot = false; 4662 int ret; 4663 int wqe_size; 4664 struct mlx5_ib_mr *mr = to_mmr(sig_mr); 4665 struct mlx5_ib_mr *pi_mr = mr->pi_mr; 4666 4667 data_len = pi_mr->data_length; 4668 data_key = pi_mr->ibmr.lkey; 4669 data_va = pi_mr->data_iova; 4670 if (pi_mr->meta_ndescs) { 4671 prot_len = pi_mr->meta_length; 4672 prot_key = pi_mr->ibmr.lkey; 4673 prot_va = pi_mr->pi_iova; 4674 prot = true; 4675 } 4676 4677 if (!prot || (data_key == prot_key && data_va == prot_va && 4678 data_len == prot_len)) { 4679 /** 4680 * Source domain doesn't contain signature information 4681 * or data and protection are interleaved in memory. 4682 * So need construct: 4683 * ------------------ 4684 * | data_klm | 4685 * ------------------ 4686 * | BSF | 4687 * ------------------ 4688 **/ 4689 struct mlx5_klm *data_klm = *seg; 4690 4691 data_klm->bcount = cpu_to_be32(data_len); 4692 data_klm->key = cpu_to_be32(data_key); 4693 data_klm->va = cpu_to_be64(data_va); 4694 wqe_size = ALIGN(sizeof(*data_klm), 64); 4695 } else { 4696 /** 4697 * Source domain contains signature information 4698 * So need construct a strided block format: 4699 * --------------------------- 4700 * | stride_block_ctrl | 4701 * --------------------------- 4702 * | data_klm | 4703 * --------------------------- 4704 * | prot_klm | 4705 * --------------------------- 4706 * | BSF | 4707 * --------------------------- 4708 **/ 4709 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4710 struct mlx5_stride_block_entry *data_sentry; 4711 struct mlx5_stride_block_entry *prot_sentry; 4712 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4713 int prot_size; 4714 4715 sblock_ctrl = *seg; 4716 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4717 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4718 4719 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4720 if (!prot_size) { 4721 pr_err("Bad block size given: %u\n", block_size); 4722 return -EINVAL; 4723 } 4724 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4725 prot_size); 4726 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4727 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4728 sblock_ctrl->num_entries = cpu_to_be16(2); 4729 4730 data_sentry->bcount = cpu_to_be16(block_size); 4731 data_sentry->key = cpu_to_be32(data_key); 4732 data_sentry->va = cpu_to_be64(data_va); 4733 data_sentry->stride = cpu_to_be16(block_size); 4734 4735 prot_sentry->bcount = cpu_to_be16(prot_size); 4736 prot_sentry->key = cpu_to_be32(prot_key); 4737 prot_sentry->va = cpu_to_be64(prot_va); 4738 prot_sentry->stride = cpu_to_be16(prot_size); 4739 4740 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4741 sizeof(*prot_sentry), 64); 4742 } 4743 4744 *seg += wqe_size; 4745 *size += wqe_size / 16; 4746 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4747 4748 bsf = *seg; 4749 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4750 if (ret) 4751 return -EINVAL; 4752 4753 *seg += sizeof(*bsf); 4754 *size += sizeof(*bsf) / 16; 4755 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4756 4757 return 0; 4758 } 4759 4760 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4761 struct ib_mr *sig_mr, int access_flags, 4762 u32 size, u32 length, u32 pdn) 4763 { 4764 u32 sig_key = sig_mr->rkey; 4765 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4766 4767 memset(seg, 0, sizeof(*seg)); 4768 4769 seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS; 4770 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4771 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4772 MLX5_MKEY_BSF_EN | pdn); 4773 seg->len = cpu_to_be64(length); 4774 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4775 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4776 } 4777 4778 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4779 u32 size) 4780 { 4781 memset(umr, 0, sizeof(*umr)); 4782 4783 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4784 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4785 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4786 umr->mkey_mask = sig_mkey_mask(); 4787 } 4788 4789 static int set_pi_umr_wr(const struct ib_send_wr *send_wr, 4790 struct mlx5_ib_qp *qp, void **seg, int *size, 4791 void **cur_edge) 4792 { 4793 const struct ib_reg_wr *wr = reg_wr(send_wr); 4794 struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr); 4795 struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr; 4796 struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs; 4797 u32 pdn = get_pd(qp)->pdn; 4798 u32 xlt_size; 4799 int region_len, ret; 4800 4801 if (unlikely(send_wr->num_sge != 0) || 4802 unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) || 4803 unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) || 4804 unlikely(!sig_mr->sig->sig_status_checked)) 4805 return -EINVAL; 4806 4807 /* length of the protected region, data + protection */ 4808 region_len = pi_mr->ibmr.length; 4809 4810 /** 4811 * KLM octoword size - if protection was provided 4812 * then we use strided block format (3 octowords), 4813 * else we use single KLM (1 octoword) 4814 **/ 4815 if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE) 4816 xlt_size = 0x30; 4817 else 4818 xlt_size = sizeof(struct mlx5_klm); 4819 4820 set_sig_umr_segment(*seg, xlt_size); 4821 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4822 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4823 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4824 4825 set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len, 4826 pdn); 4827 *seg += sizeof(struct mlx5_mkey_seg); 4828 *size += sizeof(struct mlx5_mkey_seg) / 16; 4829 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4830 4831 ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size, 4832 cur_edge); 4833 if (ret) 4834 return ret; 4835 4836 sig_mr->sig->sig_status_checked = false; 4837 return 0; 4838 } 4839 4840 static int set_psv_wr(struct ib_sig_domain *domain, 4841 u32 psv_idx, void **seg, int *size) 4842 { 4843 struct mlx5_seg_set_psv *psv_seg = *seg; 4844 4845 memset(psv_seg, 0, sizeof(*psv_seg)); 4846 psv_seg->psv_num = cpu_to_be32(psv_idx); 4847 switch (domain->sig_type) { 4848 case IB_SIG_TYPE_NONE: 4849 break; 4850 case IB_SIG_TYPE_T10_DIF: 4851 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4852 domain->sig.dif.app_tag); 4853 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4854 break; 4855 default: 4856 pr_err("Bad signature type (%d) is given.\n", 4857 domain->sig_type); 4858 return -EINVAL; 4859 } 4860 4861 *seg += sizeof(*psv_seg); 4862 *size += sizeof(*psv_seg) / 16; 4863 4864 return 0; 4865 } 4866 4867 static int set_reg_wr(struct mlx5_ib_qp *qp, 4868 const struct ib_reg_wr *wr, 4869 void **seg, int *size, void **cur_edge, 4870 bool check_not_free) 4871 { 4872 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4873 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4874 struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device); 4875 int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size; 4876 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4877 bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC; 4878 u8 flags = 0; 4879 4880 if (!mlx5_ib_can_use_umr(dev, atomic, wr->access)) { 4881 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4882 "Fast update of %s for MR is disabled\n", 4883 (MLX5_CAP_GEN(dev->mdev, 4884 umr_modify_entity_size_disabled)) ? 4885 "entity size" : 4886 "atomic access"); 4887 return -EINVAL; 4888 } 4889 4890 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4891 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4892 "Invalid IB_SEND_INLINE send flag\n"); 4893 return -EINVAL; 4894 } 4895 4896 if (check_not_free) 4897 flags |= MLX5_UMR_CHECK_NOT_FREE; 4898 if (umr_inline) 4899 flags |= MLX5_UMR_INLINE; 4900 4901 set_reg_umr_seg(*seg, mr, flags, atomic); 4902 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4903 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4904 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4905 4906 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4907 *seg += sizeof(struct mlx5_mkey_seg); 4908 *size += sizeof(struct mlx5_mkey_seg) / 16; 4909 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4910 4911 if (umr_inline) { 4912 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, 4913 mr_list_size); 4914 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); 4915 } else { 4916 set_reg_data_seg(*seg, mr, pd); 4917 *seg += sizeof(struct mlx5_wqe_data_seg); 4918 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4919 } 4920 return 0; 4921 } 4922 4923 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, 4924 void **cur_edge) 4925 { 4926 set_linv_umr_seg(*seg); 4927 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4928 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4929 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4930 set_linv_mkey_seg(*seg); 4931 *seg += sizeof(struct mlx5_mkey_seg); 4932 *size += sizeof(struct mlx5_mkey_seg) / 16; 4933 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4934 } 4935 4936 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) 4937 { 4938 __be32 *p = NULL; 4939 int i, j; 4940 4941 pr_debug("dump WQE index %u:\n", idx); 4942 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4943 if ((i & 0xf) == 0) { 4944 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx); 4945 pr_debug("WQBB at %p:\n", (void *)p); 4946 j = 0; 4947 idx = (idx + 1) & (qp->sq.wqe_cnt - 1); 4948 } 4949 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4950 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4951 be32_to_cpu(p[j + 3])); 4952 } 4953 } 4954 4955 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4956 struct mlx5_wqe_ctrl_seg **ctrl, 4957 const struct ib_send_wr *wr, unsigned int *idx, 4958 int *size, void **cur_edge, int nreq, 4959 bool send_signaled, bool solicited) 4960 { 4961 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4962 return -ENOMEM; 4963 4964 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4965 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); 4966 *ctrl = *seg; 4967 *(uint32_t *)(*seg + 8) = 0; 4968 (*ctrl)->imm = send_ieth(wr); 4969 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4970 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4971 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 4972 4973 *seg += sizeof(**ctrl); 4974 *size = sizeof(**ctrl) / 16; 4975 *cur_edge = qp->sq.cur_edge; 4976 4977 return 0; 4978 } 4979 4980 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4981 struct mlx5_wqe_ctrl_seg **ctrl, 4982 const struct ib_send_wr *wr, unsigned *idx, 4983 int *size, void **cur_edge, int nreq) 4984 { 4985 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, 4986 wr->send_flags & IB_SEND_SIGNALED, 4987 wr->send_flags & IB_SEND_SOLICITED); 4988 } 4989 4990 static void finish_wqe(struct mlx5_ib_qp *qp, 4991 struct mlx5_wqe_ctrl_seg *ctrl, 4992 void *seg, u8 size, void *cur_edge, 4993 unsigned int idx, u64 wr_id, int nreq, u8 fence, 4994 u32 mlx5_opcode) 4995 { 4996 u8 opmod = 0; 4997 4998 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4999 mlx5_opcode | ((u32)opmod << 24)); 5000 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 5001 ctrl->fm_ce_se |= fence; 5002 if (unlikely(qp->wq_sig)) 5003 ctrl->signature = wq_sig(ctrl); 5004 5005 qp->sq.wrid[idx] = wr_id; 5006 qp->sq.w_list[idx].opcode = mlx5_opcode; 5007 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 5008 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 5009 qp->sq.w_list[idx].next = qp->sq.cur_post; 5010 5011 /* We save the edge which was possibly updated during the WQE 5012 * construction, into SQ's cache. 5013 */ 5014 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); 5015 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? 5016 get_sq_edge(&qp->sq, qp->sq.cur_post & 5017 (qp->sq.wqe_cnt - 1)) : 5018 cur_edge; 5019 } 5020 5021 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5022 const struct ib_send_wr **bad_wr, bool drain) 5023 { 5024 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 5025 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5026 struct mlx5_core_dev *mdev = dev->mdev; 5027 struct ib_reg_wr reg_pi_wr; 5028 struct mlx5_ib_qp *qp; 5029 struct mlx5_ib_mr *mr; 5030 struct mlx5_ib_mr *pi_mr; 5031 struct mlx5_ib_mr pa_pi_mr; 5032 struct ib_sig_attrs *sig_attrs; 5033 struct mlx5_wqe_xrc_seg *xrc; 5034 struct mlx5_bf *bf; 5035 void *cur_edge; 5036 int uninitialized_var(size); 5037 unsigned long flags; 5038 unsigned idx; 5039 int err = 0; 5040 int num_sge; 5041 void *seg; 5042 int nreq; 5043 int i; 5044 u8 next_fence = 0; 5045 u8 fence; 5046 5047 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5048 !drain)) { 5049 *bad_wr = wr; 5050 return -EIO; 5051 } 5052 5053 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5054 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 5055 5056 qp = to_mqp(ibqp); 5057 bf = &qp->bf; 5058 5059 spin_lock_irqsave(&qp->sq.lock, flags); 5060 5061 for (nreq = 0; wr; nreq++, wr = wr->next) { 5062 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 5063 mlx5_ib_warn(dev, "\n"); 5064 err = -EINVAL; 5065 *bad_wr = wr; 5066 goto out; 5067 } 5068 5069 num_sge = wr->num_sge; 5070 if (unlikely(num_sge > qp->sq.max_gs)) { 5071 mlx5_ib_warn(dev, "\n"); 5072 err = -EINVAL; 5073 *bad_wr = wr; 5074 goto out; 5075 } 5076 5077 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, 5078 nreq); 5079 if (err) { 5080 mlx5_ib_warn(dev, "\n"); 5081 err = -ENOMEM; 5082 *bad_wr = wr; 5083 goto out; 5084 } 5085 5086 if (wr->opcode == IB_WR_REG_MR || 5087 wr->opcode == IB_WR_REG_MR_INTEGRITY) { 5088 fence = dev->umr_fence; 5089 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 5090 } else { 5091 if (wr->send_flags & IB_SEND_FENCE) { 5092 if (qp->next_fence) 5093 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 5094 else 5095 fence = MLX5_FENCE_MODE_FENCE; 5096 } else { 5097 fence = qp->next_fence; 5098 } 5099 } 5100 5101 switch (ibqp->qp_type) { 5102 case IB_QPT_XRC_INI: 5103 xrc = seg; 5104 seg += sizeof(*xrc); 5105 size += sizeof(*xrc) / 16; 5106 /* fall through */ 5107 case IB_QPT_RC: 5108 switch (wr->opcode) { 5109 case IB_WR_RDMA_READ: 5110 case IB_WR_RDMA_WRITE: 5111 case IB_WR_RDMA_WRITE_WITH_IMM: 5112 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 5113 rdma_wr(wr)->rkey); 5114 seg += sizeof(struct mlx5_wqe_raddr_seg); 5115 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 5116 break; 5117 5118 case IB_WR_ATOMIC_CMP_AND_SWP: 5119 case IB_WR_ATOMIC_FETCH_AND_ADD: 5120 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 5121 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 5122 err = -ENOSYS; 5123 *bad_wr = wr; 5124 goto out; 5125 5126 case IB_WR_LOCAL_INV: 5127 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 5128 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 5129 set_linv_wr(qp, &seg, &size, &cur_edge); 5130 num_sge = 0; 5131 break; 5132 5133 case IB_WR_REG_MR: 5134 qp->sq.wr_data[idx] = IB_WR_REG_MR; 5135 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 5136 err = set_reg_wr(qp, reg_wr(wr), &seg, &size, 5137 &cur_edge, true); 5138 if (err) { 5139 *bad_wr = wr; 5140 goto out; 5141 } 5142 num_sge = 0; 5143 break; 5144 5145 case IB_WR_REG_MR_INTEGRITY: 5146 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY; 5147 5148 mr = to_mmr(reg_wr(wr)->mr); 5149 pi_mr = mr->pi_mr; 5150 5151 if (pi_mr) { 5152 memset(®_pi_wr, 0, 5153 sizeof(struct ib_reg_wr)); 5154 5155 reg_pi_wr.mr = &pi_mr->ibmr; 5156 reg_pi_wr.access = reg_wr(wr)->access; 5157 reg_pi_wr.key = pi_mr->ibmr.rkey; 5158 5159 ctrl->imm = cpu_to_be32(reg_pi_wr.key); 5160 /* UMR for data + prot registration */ 5161 err = set_reg_wr(qp, ®_pi_wr, &seg, 5162 &size, &cur_edge, 5163 false); 5164 if (err) { 5165 *bad_wr = wr; 5166 goto out; 5167 } 5168 finish_wqe(qp, ctrl, seg, size, 5169 cur_edge, idx, wr->wr_id, 5170 nreq, fence, 5171 MLX5_OPCODE_UMR); 5172 5173 err = begin_wqe(qp, &seg, &ctrl, wr, 5174 &idx, &size, &cur_edge, 5175 nreq); 5176 if (err) { 5177 mlx5_ib_warn(dev, "\n"); 5178 err = -ENOMEM; 5179 *bad_wr = wr; 5180 goto out; 5181 } 5182 } else { 5183 memset(&pa_pi_mr, 0, 5184 sizeof(struct mlx5_ib_mr)); 5185 /* No UMR, use local_dma_lkey */ 5186 pa_pi_mr.ibmr.lkey = 5187 mr->ibmr.pd->local_dma_lkey; 5188 5189 pa_pi_mr.ndescs = mr->ndescs; 5190 pa_pi_mr.data_length = mr->data_length; 5191 pa_pi_mr.data_iova = mr->data_iova; 5192 if (mr->meta_ndescs) { 5193 pa_pi_mr.meta_ndescs = 5194 mr->meta_ndescs; 5195 pa_pi_mr.meta_length = 5196 mr->meta_length; 5197 pa_pi_mr.pi_iova = mr->pi_iova; 5198 } 5199 5200 pa_pi_mr.ibmr.length = mr->ibmr.length; 5201 mr->pi_mr = &pa_pi_mr; 5202 } 5203 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 5204 /* UMR for sig MR */ 5205 err = set_pi_umr_wr(wr, qp, &seg, &size, 5206 &cur_edge); 5207 if (err) { 5208 mlx5_ib_warn(dev, "\n"); 5209 *bad_wr = wr; 5210 goto out; 5211 } 5212 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5213 wr->wr_id, nreq, fence, 5214 MLX5_OPCODE_UMR); 5215 5216 /* 5217 * SET_PSV WQEs are not signaled and solicited 5218 * on error 5219 */ 5220 sig_attrs = mr->ibmr.sig_attrs; 5221 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 5222 &size, &cur_edge, nreq, false, 5223 true); 5224 if (err) { 5225 mlx5_ib_warn(dev, "\n"); 5226 err = -ENOMEM; 5227 *bad_wr = wr; 5228 goto out; 5229 } 5230 err = set_psv_wr(&sig_attrs->mem, 5231 mr->sig->psv_memory.psv_idx, 5232 &seg, &size); 5233 if (err) { 5234 mlx5_ib_warn(dev, "\n"); 5235 *bad_wr = wr; 5236 goto out; 5237 } 5238 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5239 wr->wr_id, nreq, next_fence, 5240 MLX5_OPCODE_SET_PSV); 5241 5242 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 5243 &size, &cur_edge, nreq, false, 5244 true); 5245 if (err) { 5246 mlx5_ib_warn(dev, "\n"); 5247 err = -ENOMEM; 5248 *bad_wr = wr; 5249 goto out; 5250 } 5251 err = set_psv_wr(&sig_attrs->wire, 5252 mr->sig->psv_wire.psv_idx, 5253 &seg, &size); 5254 if (err) { 5255 mlx5_ib_warn(dev, "\n"); 5256 *bad_wr = wr; 5257 goto out; 5258 } 5259 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5260 wr->wr_id, nreq, next_fence, 5261 MLX5_OPCODE_SET_PSV); 5262 5263 qp->next_fence = 5264 MLX5_FENCE_MODE_INITIATOR_SMALL; 5265 num_sge = 0; 5266 goto skip_psv; 5267 5268 default: 5269 break; 5270 } 5271 break; 5272 5273 case IB_QPT_UC: 5274 switch (wr->opcode) { 5275 case IB_WR_RDMA_WRITE: 5276 case IB_WR_RDMA_WRITE_WITH_IMM: 5277 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 5278 rdma_wr(wr)->rkey); 5279 seg += sizeof(struct mlx5_wqe_raddr_seg); 5280 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 5281 break; 5282 5283 default: 5284 break; 5285 } 5286 break; 5287 5288 case IB_QPT_SMI: 5289 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 5290 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 5291 err = -EPERM; 5292 *bad_wr = wr; 5293 goto out; 5294 } 5295 /* fall through */ 5296 case MLX5_IB_QPT_HW_GSI: 5297 set_datagram_seg(seg, wr); 5298 seg += sizeof(struct mlx5_wqe_datagram_seg); 5299 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5300 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5301 5302 break; 5303 case IB_QPT_UD: 5304 set_datagram_seg(seg, wr); 5305 seg += sizeof(struct mlx5_wqe_datagram_seg); 5306 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5307 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5308 5309 /* handle qp that supports ud offload */ 5310 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 5311 struct mlx5_wqe_eth_pad *pad; 5312 5313 pad = seg; 5314 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 5315 seg += sizeof(struct mlx5_wqe_eth_pad); 5316 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 5317 set_eth_seg(wr, qp, &seg, &size, &cur_edge); 5318 handle_post_send_edge(&qp->sq, &seg, size, 5319 &cur_edge); 5320 } 5321 break; 5322 case MLX5_IB_QPT_REG_UMR: 5323 if (wr->opcode != MLX5_IB_WR_UMR) { 5324 err = -EINVAL; 5325 mlx5_ib_warn(dev, "bad opcode\n"); 5326 goto out; 5327 } 5328 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 5329 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 5330 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 5331 if (unlikely(err)) 5332 goto out; 5333 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 5334 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 5335 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5336 set_reg_mkey_segment(seg, wr); 5337 seg += sizeof(struct mlx5_mkey_seg); 5338 size += sizeof(struct mlx5_mkey_seg) / 16; 5339 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5340 break; 5341 5342 default: 5343 break; 5344 } 5345 5346 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 5347 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); 5348 if (unlikely(err)) { 5349 mlx5_ib_warn(dev, "\n"); 5350 *bad_wr = wr; 5351 goto out; 5352 } 5353 } else { 5354 for (i = 0; i < num_sge; i++) { 5355 handle_post_send_edge(&qp->sq, &seg, size, 5356 &cur_edge); 5357 if (likely(wr->sg_list[i].length)) { 5358 set_data_ptr_seg 5359 ((struct mlx5_wqe_data_seg *)seg, 5360 wr->sg_list + i); 5361 size += sizeof(struct mlx5_wqe_data_seg) / 16; 5362 seg += sizeof(struct mlx5_wqe_data_seg); 5363 } 5364 } 5365 } 5366 5367 qp->next_fence = next_fence; 5368 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, 5369 fence, mlx5_ib_opcode[wr->opcode]); 5370 skip_psv: 5371 if (0) 5372 dump_wqe(qp, idx, size); 5373 } 5374 5375 out: 5376 if (likely(nreq)) { 5377 qp->sq.head += nreq; 5378 5379 /* Make sure that descriptors are written before 5380 * updating doorbell record and ringing the doorbell 5381 */ 5382 wmb(); 5383 5384 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 5385 5386 /* Make sure doorbell record is visible to the HCA before 5387 * we hit doorbell */ 5388 wmb(); 5389 5390 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset); 5391 /* Make sure doorbells don't leak out of SQ spinlock 5392 * and reach the HCA out of order. 5393 */ 5394 bf->offset ^= bf->buf_size; 5395 } 5396 5397 spin_unlock_irqrestore(&qp->sq.lock, flags); 5398 5399 return err; 5400 } 5401 5402 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5403 const struct ib_send_wr **bad_wr) 5404 { 5405 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); 5406 } 5407 5408 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 5409 { 5410 sig->signature = calc_sig(sig, size); 5411 } 5412 5413 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5414 const struct ib_recv_wr **bad_wr, bool drain) 5415 { 5416 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5417 struct mlx5_wqe_data_seg *scat; 5418 struct mlx5_rwqe_sig *sig; 5419 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5420 struct mlx5_core_dev *mdev = dev->mdev; 5421 unsigned long flags; 5422 int err = 0; 5423 int nreq; 5424 int ind; 5425 int i; 5426 5427 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5428 !drain)) { 5429 *bad_wr = wr; 5430 return -EIO; 5431 } 5432 5433 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5434 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 5435 5436 spin_lock_irqsave(&qp->rq.lock, flags); 5437 5438 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 5439 5440 for (nreq = 0; wr; nreq++, wr = wr->next) { 5441 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 5442 err = -ENOMEM; 5443 *bad_wr = wr; 5444 goto out; 5445 } 5446 5447 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 5448 err = -EINVAL; 5449 *bad_wr = wr; 5450 goto out; 5451 } 5452 5453 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); 5454 if (qp->wq_sig) 5455 scat++; 5456 5457 for (i = 0; i < wr->num_sge; i++) 5458 set_data_ptr_seg(scat + i, wr->sg_list + i); 5459 5460 if (i < qp->rq.max_gs) { 5461 scat[i].byte_count = 0; 5462 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 5463 scat[i].addr = 0; 5464 } 5465 5466 if (qp->wq_sig) { 5467 sig = (struct mlx5_rwqe_sig *)scat; 5468 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 5469 } 5470 5471 qp->rq.wrid[ind] = wr->wr_id; 5472 5473 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 5474 } 5475 5476 out: 5477 if (likely(nreq)) { 5478 qp->rq.head += nreq; 5479 5480 /* Make sure that descriptors are written before 5481 * doorbell record. 5482 */ 5483 wmb(); 5484 5485 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 5486 } 5487 5488 spin_unlock_irqrestore(&qp->rq.lock, flags); 5489 5490 return err; 5491 } 5492 5493 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5494 const struct ib_recv_wr **bad_wr) 5495 { 5496 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); 5497 } 5498 5499 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 5500 { 5501 switch (mlx5_state) { 5502 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 5503 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 5504 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 5505 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 5506 case MLX5_QP_STATE_SQ_DRAINING: 5507 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 5508 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 5509 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 5510 default: return -1; 5511 } 5512 } 5513 5514 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 5515 { 5516 switch (mlx5_mig_state) { 5517 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 5518 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 5519 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 5520 default: return -1; 5521 } 5522 } 5523 5524 static int to_ib_qp_access_flags(int mlx5_flags) 5525 { 5526 int ib_flags = 0; 5527 5528 if (mlx5_flags & MLX5_QP_BIT_RRE) 5529 ib_flags |= IB_ACCESS_REMOTE_READ; 5530 if (mlx5_flags & MLX5_QP_BIT_RWE) 5531 ib_flags |= IB_ACCESS_REMOTE_WRITE; 5532 if (mlx5_flags & MLX5_QP_BIT_RAE) 5533 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 5534 5535 return ib_flags; 5536 } 5537 5538 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 5539 struct rdma_ah_attr *ah_attr, 5540 struct mlx5_qp_path *path) 5541 { 5542 5543 memset(ah_attr, 0, sizeof(*ah_attr)); 5544 5545 if (!path->port || path->port > ibdev->num_ports) 5546 return; 5547 5548 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 5549 5550 rdma_ah_set_port_num(ah_attr, path->port); 5551 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 5552 5553 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 5554 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 5555 rdma_ah_set_static_rate(ah_attr, 5556 path->static_rate ? path->static_rate - 5 : 0); 5557 5558 if (path->grh_mlid & (1 << 7) || 5559 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 5560 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 5561 5562 rdma_ah_set_grh(ah_attr, NULL, 5563 tc_fl & 0xfffff, 5564 path->mgid_index, 5565 path->hop_limit, 5566 (tc_fl >> 20) & 0xff); 5567 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 5568 } 5569 } 5570 5571 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 5572 struct mlx5_ib_sq *sq, 5573 u8 *sq_state) 5574 { 5575 int err; 5576 5577 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 5578 if (err) 5579 goto out; 5580 sq->state = *sq_state; 5581 5582 out: 5583 return err; 5584 } 5585 5586 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 5587 struct mlx5_ib_rq *rq, 5588 u8 *rq_state) 5589 { 5590 void *out; 5591 void *rqc; 5592 int inlen; 5593 int err; 5594 5595 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 5596 out = kvzalloc(inlen, GFP_KERNEL); 5597 if (!out) 5598 return -ENOMEM; 5599 5600 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 5601 if (err) 5602 goto out; 5603 5604 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 5605 *rq_state = MLX5_GET(rqc, rqc, state); 5606 rq->state = *rq_state; 5607 5608 out: 5609 kvfree(out); 5610 return err; 5611 } 5612 5613 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 5614 struct mlx5_ib_qp *qp, u8 *qp_state) 5615 { 5616 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 5617 [MLX5_RQC_STATE_RST] = { 5618 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5619 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5620 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 5621 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 5622 }, 5623 [MLX5_RQC_STATE_RDY] = { 5624 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5625 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5626 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 5627 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 5628 }, 5629 [MLX5_RQC_STATE_ERR] = { 5630 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5631 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5632 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 5633 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 5634 }, 5635 [MLX5_RQ_STATE_NA] = { 5636 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5637 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5638 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 5639 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 5640 }, 5641 }; 5642 5643 *qp_state = sqrq_trans[rq_state][sq_state]; 5644 5645 if (*qp_state == MLX5_QP_STATE_BAD) { 5646 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 5647 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 5648 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 5649 return -EINVAL; 5650 } 5651 5652 if (*qp_state == MLX5_QP_STATE) 5653 *qp_state = qp->state; 5654 5655 return 0; 5656 } 5657 5658 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 5659 struct mlx5_ib_qp *qp, 5660 u8 *raw_packet_qp_state) 5661 { 5662 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 5663 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 5664 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 5665 int err; 5666 u8 sq_state = MLX5_SQ_STATE_NA; 5667 u8 rq_state = MLX5_RQ_STATE_NA; 5668 5669 if (qp->sq.wqe_cnt) { 5670 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 5671 if (err) 5672 return err; 5673 } 5674 5675 if (qp->rq.wqe_cnt) { 5676 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 5677 if (err) 5678 return err; 5679 } 5680 5681 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 5682 raw_packet_qp_state); 5683 } 5684 5685 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 5686 struct ib_qp_attr *qp_attr) 5687 { 5688 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 5689 struct mlx5_qp_context *context; 5690 int mlx5_state; 5691 u32 *outb; 5692 int err = 0; 5693 5694 outb = kzalloc(outlen, GFP_KERNEL); 5695 if (!outb) 5696 return -ENOMEM; 5697 5698 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 5699 if (err) 5700 goto out; 5701 5702 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 5703 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 5704 5705 mlx5_state = be32_to_cpu(context->flags) >> 28; 5706 5707 qp->state = to_ib_qp_state(mlx5_state); 5708 qp_attr->path_mtu = context->mtu_msgmax >> 5; 5709 qp_attr->path_mig_state = 5710 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 5711 qp_attr->qkey = be32_to_cpu(context->qkey); 5712 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 5713 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 5714 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 5715 qp_attr->qp_access_flags = 5716 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 5717 5718 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 5719 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 5720 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5721 qp_attr->alt_pkey_index = 5722 be16_to_cpu(context->alt_path.pkey_index); 5723 qp_attr->alt_port_num = 5724 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5725 } 5726 5727 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5728 qp_attr->port_num = context->pri_path.port; 5729 5730 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5731 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5732 5733 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5734 5735 qp_attr->max_dest_rd_atomic = 5736 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5737 qp_attr->min_rnr_timer = 5738 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5739 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5740 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5741 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5742 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5743 5744 out: 5745 kfree(outb); 5746 return err; 5747 } 5748 5749 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5750 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5751 struct ib_qp_init_attr *qp_init_attr) 5752 { 5753 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5754 u32 *out; 5755 u32 access_flags = 0; 5756 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5757 void *dctc; 5758 int err; 5759 int supported_mask = IB_QP_STATE | 5760 IB_QP_ACCESS_FLAGS | 5761 IB_QP_PORT | 5762 IB_QP_MIN_RNR_TIMER | 5763 IB_QP_AV | 5764 IB_QP_PATH_MTU | 5765 IB_QP_PKEY_INDEX; 5766 5767 if (qp_attr_mask & ~supported_mask) 5768 return -EINVAL; 5769 if (mqp->state != IB_QPS_RTR) 5770 return -EINVAL; 5771 5772 out = kzalloc(outlen, GFP_KERNEL); 5773 if (!out) 5774 return -ENOMEM; 5775 5776 err = mlx5_core_dct_query(dev, dct, out, outlen); 5777 if (err) 5778 goto out; 5779 5780 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5781 5782 if (qp_attr_mask & IB_QP_STATE) 5783 qp_attr->qp_state = IB_QPS_RTR; 5784 5785 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5786 if (MLX5_GET(dctc, dctc, rre)) 5787 access_flags |= IB_ACCESS_REMOTE_READ; 5788 if (MLX5_GET(dctc, dctc, rwe)) 5789 access_flags |= IB_ACCESS_REMOTE_WRITE; 5790 if (MLX5_GET(dctc, dctc, rae)) 5791 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5792 qp_attr->qp_access_flags = access_flags; 5793 } 5794 5795 if (qp_attr_mask & IB_QP_PORT) 5796 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5797 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5798 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5799 if (qp_attr_mask & IB_QP_AV) { 5800 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5801 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5802 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5803 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5804 } 5805 if (qp_attr_mask & IB_QP_PATH_MTU) 5806 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5807 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5808 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5809 out: 5810 kfree(out); 5811 return err; 5812 } 5813 5814 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5815 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5816 { 5817 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5818 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5819 int err = 0; 5820 u8 raw_packet_qp_state; 5821 5822 if (ibqp->rwq_ind_tbl) 5823 return -ENOSYS; 5824 5825 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5826 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5827 qp_init_attr); 5828 5829 /* Not all of output fields are applicable, make sure to zero them */ 5830 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5831 memset(qp_attr, 0, sizeof(*qp_attr)); 5832 5833 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5834 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5835 qp_attr_mask, qp_init_attr); 5836 5837 mutex_lock(&qp->mutex); 5838 5839 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5840 qp->flags & MLX5_IB_QP_UNDERLAY) { 5841 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5842 if (err) 5843 goto out; 5844 qp->state = raw_packet_qp_state; 5845 qp_attr->port_num = 1; 5846 } else { 5847 err = query_qp_attr(dev, qp, qp_attr); 5848 if (err) 5849 goto out; 5850 } 5851 5852 qp_attr->qp_state = qp->state; 5853 qp_attr->cur_qp_state = qp_attr->qp_state; 5854 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5855 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5856 5857 if (!ibqp->uobject) { 5858 qp_attr->cap.max_send_wr = qp->sq.max_post; 5859 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5860 qp_init_attr->qp_context = ibqp->qp_context; 5861 } else { 5862 qp_attr->cap.max_send_wr = 0; 5863 qp_attr->cap.max_send_sge = 0; 5864 } 5865 5866 qp_init_attr->qp_type = ibqp->qp_type; 5867 qp_init_attr->recv_cq = ibqp->recv_cq; 5868 qp_init_attr->send_cq = ibqp->send_cq; 5869 qp_init_attr->srq = ibqp->srq; 5870 qp_attr->cap.max_inline_data = qp->max_inline_data; 5871 5872 qp_init_attr->cap = qp_attr->cap; 5873 5874 qp_init_attr->create_flags = 0; 5875 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5876 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5877 5878 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5879 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5880 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5881 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5882 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5883 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5884 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5885 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; 5886 5887 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5888 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5889 5890 out: 5891 mutex_unlock(&qp->mutex); 5892 return err; 5893 } 5894 5895 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5896 struct ib_udata *udata) 5897 { 5898 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5899 struct mlx5_ib_xrcd *xrcd; 5900 int err; 5901 5902 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5903 return ERR_PTR(-ENOSYS); 5904 5905 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5906 if (!xrcd) 5907 return ERR_PTR(-ENOMEM); 5908 5909 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5910 if (err) { 5911 kfree(xrcd); 5912 return ERR_PTR(-ENOMEM); 5913 } 5914 5915 return &xrcd->ibxrcd; 5916 } 5917 5918 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5919 { 5920 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5921 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5922 int err; 5923 5924 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5925 if (err) 5926 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5927 5928 kfree(xrcd); 5929 return 0; 5930 } 5931 5932 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5933 { 5934 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5935 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5936 struct ib_event event; 5937 5938 if (rwq->ibwq.event_handler) { 5939 event.device = rwq->ibwq.device; 5940 event.element.wq = &rwq->ibwq; 5941 switch (type) { 5942 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5943 event.event = IB_EVENT_WQ_FATAL; 5944 break; 5945 default: 5946 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5947 return; 5948 } 5949 5950 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5951 } 5952 } 5953 5954 static int set_delay_drop(struct mlx5_ib_dev *dev) 5955 { 5956 int err = 0; 5957 5958 mutex_lock(&dev->delay_drop.lock); 5959 if (dev->delay_drop.activate) 5960 goto out; 5961 5962 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 5963 if (err) 5964 goto out; 5965 5966 dev->delay_drop.activate = true; 5967 out: 5968 mutex_unlock(&dev->delay_drop.lock); 5969 5970 if (!err) 5971 atomic_inc(&dev->delay_drop.rqs_cnt); 5972 return err; 5973 } 5974 5975 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5976 struct ib_wq_init_attr *init_attr) 5977 { 5978 struct mlx5_ib_dev *dev; 5979 int has_net_offloads; 5980 __be64 *rq_pas0; 5981 void *in; 5982 void *rqc; 5983 void *wq; 5984 int inlen; 5985 int err; 5986 5987 dev = to_mdev(pd->device); 5988 5989 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5990 in = kvzalloc(inlen, GFP_KERNEL); 5991 if (!in) 5992 return -ENOMEM; 5993 5994 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5995 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5996 MLX5_SET(rqc, rqc, mem_rq_type, 5997 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5998 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5999 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 6000 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 6001 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 6002 wq = MLX5_ADDR_OF(rqc, rqc, wq); 6003 MLX5_SET(wq, wq, wq_type, 6004 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 6005 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 6006 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6007 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 6008 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 6009 err = -EOPNOTSUPP; 6010 goto out; 6011 } else { 6012 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 6013 } 6014 } 6015 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 6016 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 6017 /* 6018 * In Firmware number of strides in each WQE is: 6019 * "512 * 2^single_wqe_log_num_of_strides" 6020 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 6021 * accepted as 0 to 9 6022 */ 6023 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 6024 2, 3, 4, 5, 6, 7, 8, 9 }; 6025 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 6026 MLX5_SET(wq, wq, log_wqe_stride_size, 6027 rwq->single_stride_log_num_of_bytes - 6028 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 6029 MLX5_SET(wq, wq, log_wqe_num_of_strides, 6030 fw_map[rwq->log_num_strides - 6031 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 6032 } 6033 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 6034 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 6035 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 6036 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 6037 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 6038 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 6039 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 6040 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6041 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6042 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 6043 err = -EOPNOTSUPP; 6044 goto out; 6045 } 6046 } else { 6047 MLX5_SET(rqc, rqc, vsd, 1); 6048 } 6049 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 6050 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 6051 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 6052 err = -EOPNOTSUPP; 6053 goto out; 6054 } 6055 MLX5_SET(rqc, rqc, scatter_fcs, 1); 6056 } 6057 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 6058 if (!(dev->ib_dev.attrs.raw_packet_caps & 6059 IB_RAW_PACKET_CAP_DELAY_DROP)) { 6060 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 6061 err = -EOPNOTSUPP; 6062 goto out; 6063 } 6064 MLX5_SET(rqc, rqc, delay_drop_en, 1); 6065 } 6066 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 6067 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 6068 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 6069 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 6070 err = set_delay_drop(dev); 6071 if (err) { 6072 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 6073 err); 6074 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 6075 } else { 6076 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 6077 } 6078 } 6079 out: 6080 kvfree(in); 6081 return err; 6082 } 6083 6084 static int set_user_rq_size(struct mlx5_ib_dev *dev, 6085 struct ib_wq_init_attr *wq_init_attr, 6086 struct mlx5_ib_create_wq *ucmd, 6087 struct mlx5_ib_rwq *rwq) 6088 { 6089 /* Sanity check RQ size before proceeding */ 6090 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 6091 return -EINVAL; 6092 6093 if (!ucmd->rq_wqe_count) 6094 return -EINVAL; 6095 6096 rwq->wqe_count = ucmd->rq_wqe_count; 6097 rwq->wqe_shift = ucmd->rq_wqe_shift; 6098 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 6099 return -EINVAL; 6100 6101 rwq->log_rq_stride = rwq->wqe_shift; 6102 rwq->log_rq_size = ilog2(rwq->wqe_count); 6103 return 0; 6104 } 6105 6106 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 6107 { 6108 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 6109 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 6110 return false; 6111 6112 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 6113 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 6114 return false; 6115 6116 return true; 6117 } 6118 6119 static int prepare_user_rq(struct ib_pd *pd, 6120 struct ib_wq_init_attr *init_attr, 6121 struct ib_udata *udata, 6122 struct mlx5_ib_rwq *rwq) 6123 { 6124 struct mlx5_ib_dev *dev = to_mdev(pd->device); 6125 struct mlx5_ib_create_wq ucmd = {}; 6126 int err; 6127 size_t required_cmd_sz; 6128 6129 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 6130 + sizeof(ucmd.single_stride_log_num_of_bytes); 6131 if (udata->inlen < required_cmd_sz) { 6132 mlx5_ib_dbg(dev, "invalid inlen\n"); 6133 return -EINVAL; 6134 } 6135 6136 if (udata->inlen > sizeof(ucmd) && 6137 !ib_is_udata_cleared(udata, sizeof(ucmd), 6138 udata->inlen - sizeof(ucmd))) { 6139 mlx5_ib_dbg(dev, "inlen is not supported\n"); 6140 return -EOPNOTSUPP; 6141 } 6142 6143 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 6144 mlx5_ib_dbg(dev, "copy failed\n"); 6145 return -EFAULT; 6146 } 6147 6148 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 6149 mlx5_ib_dbg(dev, "invalid comp mask\n"); 6150 return -EOPNOTSUPP; 6151 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 6152 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 6153 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 6154 return -EOPNOTSUPP; 6155 } 6156 if ((ucmd.single_stride_log_num_of_bytes < 6157 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 6158 (ucmd.single_stride_log_num_of_bytes > 6159 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 6160 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 6161 ucmd.single_stride_log_num_of_bytes, 6162 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 6163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 6164 return -EINVAL; 6165 } 6166 if (!log_of_strides_valid(dev, 6167 ucmd.single_wqe_log_num_of_strides)) { 6168 mlx5_ib_dbg( 6169 dev, 6170 "Invalid log num strides (%u. Range is %u - %u)\n", 6171 ucmd.single_wqe_log_num_of_strides, 6172 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 6173 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 6174 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 6175 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 6176 return -EINVAL; 6177 } 6178 rwq->single_stride_log_num_of_bytes = 6179 ucmd.single_stride_log_num_of_bytes; 6180 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 6181 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 6182 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 6183 } 6184 6185 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 6186 if (err) { 6187 mlx5_ib_dbg(dev, "err %d\n", err); 6188 return err; 6189 } 6190 6191 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 6192 if (err) { 6193 mlx5_ib_dbg(dev, "err %d\n", err); 6194 return err; 6195 } 6196 6197 rwq->user_index = ucmd.user_index; 6198 return 0; 6199 } 6200 6201 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 6202 struct ib_wq_init_attr *init_attr, 6203 struct ib_udata *udata) 6204 { 6205 struct mlx5_ib_dev *dev; 6206 struct mlx5_ib_rwq *rwq; 6207 struct mlx5_ib_create_wq_resp resp = {}; 6208 size_t min_resp_len; 6209 int err; 6210 6211 if (!udata) 6212 return ERR_PTR(-ENOSYS); 6213 6214 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 6215 if (udata->outlen && udata->outlen < min_resp_len) 6216 return ERR_PTR(-EINVAL); 6217 6218 if (!capable(CAP_SYS_RAWIO) && 6219 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 6220 return ERR_PTR(-EPERM); 6221 6222 dev = to_mdev(pd->device); 6223 switch (init_attr->wq_type) { 6224 case IB_WQT_RQ: 6225 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 6226 if (!rwq) 6227 return ERR_PTR(-ENOMEM); 6228 err = prepare_user_rq(pd, init_attr, udata, rwq); 6229 if (err) 6230 goto err; 6231 err = create_rq(rwq, pd, init_attr); 6232 if (err) 6233 goto err_user_rq; 6234 break; 6235 default: 6236 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 6237 init_attr->wq_type); 6238 return ERR_PTR(-EINVAL); 6239 } 6240 6241 rwq->ibwq.wq_num = rwq->core_qp.qpn; 6242 rwq->ibwq.state = IB_WQS_RESET; 6243 if (udata->outlen) { 6244 resp.response_length = offsetof(typeof(resp), response_length) + 6245 sizeof(resp.response_length); 6246 err = ib_copy_to_udata(udata, &resp, resp.response_length); 6247 if (err) 6248 goto err_copy; 6249 } 6250 6251 rwq->core_qp.event = mlx5_ib_wq_event; 6252 rwq->ibwq.event_handler = init_attr->event_handler; 6253 return &rwq->ibwq; 6254 6255 err_copy: 6256 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 6257 err_user_rq: 6258 destroy_user_rq(dev, pd, rwq, udata); 6259 err: 6260 kfree(rwq); 6261 return ERR_PTR(err); 6262 } 6263 6264 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 6265 { 6266 struct mlx5_ib_dev *dev = to_mdev(wq->device); 6267 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 6268 6269 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 6270 destroy_user_rq(dev, wq->pd, rwq, udata); 6271 kfree(rwq); 6272 } 6273 6274 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 6275 struct ib_rwq_ind_table_init_attr *init_attr, 6276 struct ib_udata *udata) 6277 { 6278 struct mlx5_ib_dev *dev = to_mdev(device); 6279 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 6280 int sz = 1 << init_attr->log_ind_tbl_size; 6281 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 6282 size_t min_resp_len; 6283 int inlen; 6284 int err; 6285 int i; 6286 u32 *in; 6287 void *rqtc; 6288 6289 if (udata->inlen > 0 && 6290 !ib_is_udata_cleared(udata, 0, 6291 udata->inlen)) 6292 return ERR_PTR(-EOPNOTSUPP); 6293 6294 if (init_attr->log_ind_tbl_size > 6295 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 6296 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 6297 init_attr->log_ind_tbl_size, 6298 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 6299 return ERR_PTR(-EINVAL); 6300 } 6301 6302 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 6303 if (udata->outlen && udata->outlen < min_resp_len) 6304 return ERR_PTR(-EINVAL); 6305 6306 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 6307 if (!rwq_ind_tbl) 6308 return ERR_PTR(-ENOMEM); 6309 6310 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 6311 in = kvzalloc(inlen, GFP_KERNEL); 6312 if (!in) { 6313 err = -ENOMEM; 6314 goto err; 6315 } 6316 6317 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 6318 6319 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 6320 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 6321 6322 for (i = 0; i < sz; i++) 6323 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 6324 6325 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 6326 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 6327 6328 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 6329 kvfree(in); 6330 6331 if (err) 6332 goto err; 6333 6334 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 6335 if (udata->outlen) { 6336 resp.response_length = offsetof(typeof(resp), response_length) + 6337 sizeof(resp.response_length); 6338 err = ib_copy_to_udata(udata, &resp, resp.response_length); 6339 if (err) 6340 goto err_copy; 6341 } 6342 6343 return &rwq_ind_tbl->ib_rwq_ind_tbl; 6344 6345 err_copy: 6346 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6347 err: 6348 kfree(rwq_ind_tbl); 6349 return ERR_PTR(err); 6350 } 6351 6352 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 6353 { 6354 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 6355 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 6356 6357 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6358 6359 kfree(rwq_ind_tbl); 6360 return 0; 6361 } 6362 6363 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 6364 u32 wq_attr_mask, struct ib_udata *udata) 6365 { 6366 struct mlx5_ib_dev *dev = to_mdev(wq->device); 6367 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 6368 struct mlx5_ib_modify_wq ucmd = {}; 6369 size_t required_cmd_sz; 6370 int curr_wq_state; 6371 int wq_state; 6372 int inlen; 6373 int err; 6374 void *rqc; 6375 void *in; 6376 6377 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 6378 if (udata->inlen < required_cmd_sz) 6379 return -EINVAL; 6380 6381 if (udata->inlen > sizeof(ucmd) && 6382 !ib_is_udata_cleared(udata, sizeof(ucmd), 6383 udata->inlen - sizeof(ucmd))) 6384 return -EOPNOTSUPP; 6385 6386 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 6387 return -EFAULT; 6388 6389 if (ucmd.comp_mask || ucmd.reserved) 6390 return -EOPNOTSUPP; 6391 6392 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 6393 in = kvzalloc(inlen, GFP_KERNEL); 6394 if (!in) 6395 return -ENOMEM; 6396 6397 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 6398 6399 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 6400 wq_attr->curr_wq_state : wq->state; 6401 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 6402 wq_attr->wq_state : curr_wq_state; 6403 if (curr_wq_state == IB_WQS_ERR) 6404 curr_wq_state = MLX5_RQC_STATE_ERR; 6405 if (wq_state == IB_WQS_ERR) 6406 wq_state = MLX5_RQC_STATE_ERR; 6407 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 6408 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 6409 MLX5_SET(rqc, rqc, state, wq_state); 6410 6411 if (wq_attr_mask & IB_WQ_FLAGS) { 6412 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6413 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 6414 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6415 mlx5_ib_dbg(dev, "VLAN offloads are not " 6416 "supported\n"); 6417 err = -EOPNOTSUPP; 6418 goto out; 6419 } 6420 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6421 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 6422 MLX5_SET(rqc, rqc, vsd, 6423 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 6424 } 6425 6426 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6427 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 6428 err = -EOPNOTSUPP; 6429 goto out; 6430 } 6431 } 6432 6433 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 6434 u16 set_id; 6435 6436 set_id = mlx5_ib_get_counters_id(dev, 0); 6437 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 6438 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6439 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 6440 MLX5_SET(rqc, rqc, counter_set_id, set_id); 6441 } else 6442 dev_info_once( 6443 &dev->ib_dev.dev, 6444 "Receive WQ counters are not supported on current FW\n"); 6445 } 6446 6447 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 6448 if (!err) 6449 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 6450 6451 out: 6452 kvfree(in); 6453 return err; 6454 } 6455 6456 struct mlx5_ib_drain_cqe { 6457 struct ib_cqe cqe; 6458 struct completion done; 6459 }; 6460 6461 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 6462 { 6463 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 6464 struct mlx5_ib_drain_cqe, 6465 cqe); 6466 6467 complete(&cqe->done); 6468 } 6469 6470 /* This function returns only once the drained WR was completed */ 6471 static void handle_drain_completion(struct ib_cq *cq, 6472 struct mlx5_ib_drain_cqe *sdrain, 6473 struct mlx5_ib_dev *dev) 6474 { 6475 struct mlx5_core_dev *mdev = dev->mdev; 6476 6477 if (cq->poll_ctx == IB_POLL_DIRECT) { 6478 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 6479 ib_process_cq_direct(cq, -1); 6480 return; 6481 } 6482 6483 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6484 struct mlx5_ib_cq *mcq = to_mcq(cq); 6485 bool triggered = false; 6486 unsigned long flags; 6487 6488 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 6489 /* Make sure that the CQ handler won't run if wasn't run yet */ 6490 if (!mcq->mcq.reset_notify_added) 6491 mcq->mcq.reset_notify_added = 1; 6492 else 6493 triggered = true; 6494 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 6495 6496 if (triggered) { 6497 /* Wait for any scheduled/running task to be ended */ 6498 switch (cq->poll_ctx) { 6499 case IB_POLL_SOFTIRQ: 6500 irq_poll_disable(&cq->iop); 6501 irq_poll_enable(&cq->iop); 6502 break; 6503 case IB_POLL_WORKQUEUE: 6504 cancel_work_sync(&cq->work); 6505 break; 6506 default: 6507 WARN_ON_ONCE(1); 6508 } 6509 } 6510 6511 /* Run the CQ handler - this makes sure that the drain WR will 6512 * be processed if wasn't processed yet. 6513 */ 6514 mcq->mcq.comp(&mcq->mcq, NULL); 6515 } 6516 6517 wait_for_completion(&sdrain->done); 6518 } 6519 6520 void mlx5_ib_drain_sq(struct ib_qp *qp) 6521 { 6522 struct ib_cq *cq = qp->send_cq; 6523 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6524 struct mlx5_ib_drain_cqe sdrain; 6525 const struct ib_send_wr *bad_swr; 6526 struct ib_rdma_wr swr = { 6527 .wr = { 6528 .next = NULL, 6529 { .wr_cqe = &sdrain.cqe, }, 6530 .opcode = IB_WR_RDMA_WRITE, 6531 }, 6532 }; 6533 int ret; 6534 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6535 struct mlx5_core_dev *mdev = dev->mdev; 6536 6537 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6538 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6539 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6540 return; 6541 } 6542 6543 sdrain.cqe.done = mlx5_ib_drain_qp_done; 6544 init_completion(&sdrain.done); 6545 6546 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); 6547 if (ret) { 6548 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6549 return; 6550 } 6551 6552 handle_drain_completion(cq, &sdrain, dev); 6553 } 6554 6555 void mlx5_ib_drain_rq(struct ib_qp *qp) 6556 { 6557 struct ib_cq *cq = qp->recv_cq; 6558 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6559 struct mlx5_ib_drain_cqe rdrain; 6560 struct ib_recv_wr rwr = {}; 6561 const struct ib_recv_wr *bad_rwr; 6562 int ret; 6563 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6564 struct mlx5_core_dev *mdev = dev->mdev; 6565 6566 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6567 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6568 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6569 return; 6570 } 6571 6572 rwr.wr_cqe = &rdrain.cqe; 6573 rdrain.cqe.done = mlx5_ib_drain_qp_done; 6574 init_completion(&rdrain.done); 6575 6576 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); 6577 if (ret) { 6578 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6579 return; 6580 } 6581 6582 handle_drain_completion(cq, &rdrain, dev); 6583 } 6584 6585 /** 6586 * Bind a qp to a counter. If @counter is NULL then bind the qp to 6587 * the default counter 6588 */ 6589 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 6590 { 6591 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6592 struct mlx5_ib_qp *mqp = to_mqp(qp); 6593 int err = 0; 6594 6595 mutex_lock(&mqp->mutex); 6596 if (mqp->state == IB_QPS_RESET) { 6597 qp->counter = counter; 6598 goto out; 6599 } 6600 6601 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 6602 err = -EOPNOTSUPP; 6603 goto out; 6604 } 6605 6606 if (mqp->state == IB_QPS_RTS) { 6607 err = __mlx5_ib_qp_set_counter(qp, counter); 6608 if (!err) 6609 qp->counter = counter; 6610 6611 goto out; 6612 } 6613 6614 mqp->counter_pending = 1; 6615 qp->counter = counter; 6616 6617 out: 6618 mutex_unlock(&mqp->mutex); 6619 return err; 6620 } 6621