1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 #include "cmd.h" 41 42 /* not supported currently */ 43 static int wq_signature; 44 45 enum { 46 MLX5_IB_ACK_REQ_FREQ = 8, 47 }; 48 49 enum { 50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 52 MLX5_IB_LINK_TYPE_IB = 0, 53 MLX5_IB_LINK_TYPE_ETH = 1 54 }; 55 56 enum { 57 MLX5_IB_SQ_STRIDE = 6, 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 59 }; 60 61 static const u32 mlx5_ib_opcode[] = { 62 [IB_WR_SEND] = MLX5_OPCODE_SEND, 63 [IB_WR_LSO] = MLX5_OPCODE_LSO, 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 76 }; 77 78 struct mlx5_wqe_eth_pad { 79 u8 rsvd0[16]; 80 }; 81 82 enum raw_qp_set_mask_map { 83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 85 }; 86 87 struct mlx5_modify_raw_qp_param { 88 u16 operation; 89 90 u32 set_mask; /* raw_qp_set_mask_map */ 91 92 struct mlx5_rate_limit rl; 93 94 u8 rq_q_ctr_id; 95 }; 96 97 static void get_cqs(enum ib_qp_type qp_type, 98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 100 101 static int is_qp0(enum ib_qp_type qp_type) 102 { 103 return qp_type == IB_QPT_SMI; 104 } 105 106 static int is_sqp(enum ib_qp_type qp_type) 107 { 108 return is_qp0(qp_type) || is_qp1(qp_type); 109 } 110 111 /** 112 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 113 * to kernel buffer 114 * 115 * @umem: User space memory where the WQ is 116 * @buffer: buffer to copy to 117 * @buflen: buffer length 118 * @wqe_index: index of WQE to copy from 119 * @wq_offset: offset to start of WQ 120 * @wq_wqe_cnt: number of WQEs in WQ 121 * @wq_wqe_shift: log2 of WQE size 122 * @bcnt: number of bytes to copy 123 * @bytes_copied: number of bytes to copy (return value) 124 * 125 * Copies from start of WQE bcnt or less bytes. 126 * Does not gurantee to copy the entire WQE. 127 * 128 * Return: zero on success, or an error code. 129 */ 130 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, 131 void *buffer, 132 u32 buflen, 133 int wqe_index, 134 int wq_offset, 135 int wq_wqe_cnt, 136 int wq_wqe_shift, 137 int bcnt, 138 size_t *bytes_copied) 139 { 140 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 141 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 142 size_t copy_length; 143 int ret; 144 145 /* don't copy more than requested, more than buffer length or 146 * beyond WQ end 147 */ 148 copy_length = min_t(u32, buflen, wq_end - offset); 149 copy_length = min_t(u32, copy_length, bcnt); 150 151 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 152 if (ret) 153 return ret; 154 155 if (!ret && bytes_copied) 156 *bytes_copied = copy_length; 157 158 return 0; 159 } 160 161 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, 162 int wqe_index, 163 void *buffer, 164 int buflen, 165 size_t *bc) 166 { 167 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 168 struct ib_umem *umem = base->ubuffer.umem; 169 struct mlx5_ib_wq *wq = &qp->sq; 170 struct mlx5_wqe_ctrl_seg *ctrl; 171 size_t bytes_copied; 172 size_t bytes_copied2; 173 size_t wqe_length; 174 int ret; 175 int ds; 176 177 if (buflen < sizeof(*ctrl)) 178 return -EINVAL; 179 180 /* at first read as much as possible */ 181 ret = mlx5_ib_read_user_wqe_common(umem, 182 buffer, 183 buflen, 184 wqe_index, 185 wq->offset, 186 wq->wqe_cnt, 187 wq->wqe_shift, 188 buflen, 189 &bytes_copied); 190 if (ret) 191 return ret; 192 193 /* we need at least control segment size to proceed */ 194 if (bytes_copied < sizeof(*ctrl)) 195 return -EINVAL; 196 197 ctrl = buffer; 198 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 199 wqe_length = ds * MLX5_WQE_DS_UNITS; 200 201 /* if we copied enough then we are done */ 202 if (bytes_copied >= wqe_length) { 203 *bc = bytes_copied; 204 return 0; 205 } 206 207 /* otherwise this a wrapped around wqe 208 * so read the remaining bytes starting 209 * from wqe_index 0 210 */ 211 ret = mlx5_ib_read_user_wqe_common(umem, 212 buffer + bytes_copied, 213 buflen - bytes_copied, 214 0, 215 wq->offset, 216 wq->wqe_cnt, 217 wq->wqe_shift, 218 wqe_length - bytes_copied, 219 &bytes_copied2); 220 221 if (ret) 222 return ret; 223 *bc = bytes_copied + bytes_copied2; 224 return 0; 225 } 226 227 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, 228 int wqe_index, 229 void *buffer, 230 int buflen, 231 size_t *bc) 232 { 233 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 234 struct ib_umem *umem = base->ubuffer.umem; 235 struct mlx5_ib_wq *wq = &qp->rq; 236 size_t bytes_copied; 237 int ret; 238 239 ret = mlx5_ib_read_user_wqe_common(umem, 240 buffer, 241 buflen, 242 wqe_index, 243 wq->offset, 244 wq->wqe_cnt, 245 wq->wqe_shift, 246 buflen, 247 &bytes_copied); 248 249 if (ret) 250 return ret; 251 *bc = bytes_copied; 252 return 0; 253 } 254 255 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, 256 int wqe_index, 257 void *buffer, 258 int buflen, 259 size_t *bc) 260 { 261 struct ib_umem *umem = srq->umem; 262 size_t bytes_copied; 263 int ret; 264 265 ret = mlx5_ib_read_user_wqe_common(umem, 266 buffer, 267 buflen, 268 wqe_index, 269 0, 270 srq->msrq.max, 271 srq->msrq.wqe_shift, 272 buflen, 273 &bytes_copied); 274 275 if (ret) 276 return ret; 277 *bc = bytes_copied; 278 return 0; 279 } 280 281 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 282 { 283 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 284 struct ib_event event; 285 286 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 287 /* This event is only valid for trans_qps */ 288 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 289 } 290 291 if (ibqp->event_handler) { 292 event.device = ibqp->device; 293 event.element.qp = ibqp; 294 switch (type) { 295 case MLX5_EVENT_TYPE_PATH_MIG: 296 event.event = IB_EVENT_PATH_MIG; 297 break; 298 case MLX5_EVENT_TYPE_COMM_EST: 299 event.event = IB_EVENT_COMM_EST; 300 break; 301 case MLX5_EVENT_TYPE_SQ_DRAINED: 302 event.event = IB_EVENT_SQ_DRAINED; 303 break; 304 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 305 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 306 break; 307 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 308 event.event = IB_EVENT_QP_FATAL; 309 break; 310 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 311 event.event = IB_EVENT_PATH_MIG_ERR; 312 break; 313 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 314 event.event = IB_EVENT_QP_REQ_ERR; 315 break; 316 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 317 event.event = IB_EVENT_QP_ACCESS_ERR; 318 break; 319 default: 320 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 321 return; 322 } 323 324 ibqp->event_handler(&event, ibqp->qp_context); 325 } 326 } 327 328 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 329 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 330 { 331 int wqe_size; 332 int wq_size; 333 334 /* Sanity check RQ size before proceeding */ 335 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 336 return -EINVAL; 337 338 if (!has_rq) { 339 qp->rq.max_gs = 0; 340 qp->rq.wqe_cnt = 0; 341 qp->rq.wqe_shift = 0; 342 cap->max_recv_wr = 0; 343 cap->max_recv_sge = 0; 344 } else { 345 if (ucmd) { 346 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 347 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 348 return -EINVAL; 349 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 350 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 351 return -EINVAL; 352 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 353 qp->rq.max_post = qp->rq.wqe_cnt; 354 } else { 355 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 356 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 357 wqe_size = roundup_pow_of_two(wqe_size); 358 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 359 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 360 qp->rq.wqe_cnt = wq_size / wqe_size; 361 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 362 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 363 wqe_size, 364 MLX5_CAP_GEN(dev->mdev, 365 max_wqe_sz_rq)); 366 return -EINVAL; 367 } 368 qp->rq.wqe_shift = ilog2(wqe_size); 369 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 370 qp->rq.max_post = qp->rq.wqe_cnt; 371 } 372 } 373 374 return 0; 375 } 376 377 static int sq_overhead(struct ib_qp_init_attr *attr) 378 { 379 int size = 0; 380 381 switch (attr->qp_type) { 382 case IB_QPT_XRC_INI: 383 size += sizeof(struct mlx5_wqe_xrc_seg); 384 /* fall through */ 385 case IB_QPT_RC: 386 size += sizeof(struct mlx5_wqe_ctrl_seg) + 387 max(sizeof(struct mlx5_wqe_atomic_seg) + 388 sizeof(struct mlx5_wqe_raddr_seg), 389 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 390 sizeof(struct mlx5_mkey_seg) + 391 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 392 MLX5_IB_UMR_OCTOWORD); 393 break; 394 395 case IB_QPT_XRC_TGT: 396 return 0; 397 398 case IB_QPT_UC: 399 size += sizeof(struct mlx5_wqe_ctrl_seg) + 400 max(sizeof(struct mlx5_wqe_raddr_seg), 401 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 402 sizeof(struct mlx5_mkey_seg)); 403 break; 404 405 case IB_QPT_UD: 406 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 407 size += sizeof(struct mlx5_wqe_eth_pad) + 408 sizeof(struct mlx5_wqe_eth_seg); 409 /* fall through */ 410 case IB_QPT_SMI: 411 case MLX5_IB_QPT_HW_GSI: 412 size += sizeof(struct mlx5_wqe_ctrl_seg) + 413 sizeof(struct mlx5_wqe_datagram_seg); 414 break; 415 416 case MLX5_IB_QPT_REG_UMR: 417 size += sizeof(struct mlx5_wqe_ctrl_seg) + 418 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 419 sizeof(struct mlx5_mkey_seg); 420 break; 421 422 default: 423 return -EINVAL; 424 } 425 426 return size; 427 } 428 429 static int calc_send_wqe(struct ib_qp_init_attr *attr) 430 { 431 int inl_size = 0; 432 int size; 433 434 size = sq_overhead(attr); 435 if (size < 0) 436 return size; 437 438 if (attr->cap.max_inline_data) { 439 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 440 attr->cap.max_inline_data; 441 } 442 443 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 444 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 445 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 446 return MLX5_SIG_WQE_SIZE; 447 else 448 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 449 } 450 451 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 452 { 453 int max_sge; 454 455 if (attr->qp_type == IB_QPT_RC) 456 max_sge = (min_t(int, wqe_size, 512) - 457 sizeof(struct mlx5_wqe_ctrl_seg) - 458 sizeof(struct mlx5_wqe_raddr_seg)) / 459 sizeof(struct mlx5_wqe_data_seg); 460 else if (attr->qp_type == IB_QPT_XRC_INI) 461 max_sge = (min_t(int, wqe_size, 512) - 462 sizeof(struct mlx5_wqe_ctrl_seg) - 463 sizeof(struct mlx5_wqe_xrc_seg) - 464 sizeof(struct mlx5_wqe_raddr_seg)) / 465 sizeof(struct mlx5_wqe_data_seg); 466 else 467 max_sge = (wqe_size - sq_overhead(attr)) / 468 sizeof(struct mlx5_wqe_data_seg); 469 470 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 471 sizeof(struct mlx5_wqe_data_seg)); 472 } 473 474 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 475 struct mlx5_ib_qp *qp) 476 { 477 int wqe_size; 478 int wq_size; 479 480 if (!attr->cap.max_send_wr) 481 return 0; 482 483 wqe_size = calc_send_wqe(attr); 484 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 485 if (wqe_size < 0) 486 return wqe_size; 487 488 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 489 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 490 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 491 return -EINVAL; 492 } 493 494 qp->max_inline_data = wqe_size - sq_overhead(attr) - 495 sizeof(struct mlx5_wqe_inline_seg); 496 attr->cap.max_inline_data = qp->max_inline_data; 497 498 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 499 qp->signature_en = true; 500 501 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 502 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 503 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 504 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 505 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 506 qp->sq.wqe_cnt, 507 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 508 return -ENOMEM; 509 } 510 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 511 qp->sq.max_gs = get_send_sge(attr, wqe_size); 512 if (qp->sq.max_gs < attr->cap.max_send_sge) 513 return -ENOMEM; 514 515 attr->cap.max_send_sge = qp->sq.max_gs; 516 qp->sq.max_post = wq_size / wqe_size; 517 attr->cap.max_send_wr = qp->sq.max_post; 518 519 return wq_size; 520 } 521 522 static int set_user_buf_size(struct mlx5_ib_dev *dev, 523 struct mlx5_ib_qp *qp, 524 struct mlx5_ib_create_qp *ucmd, 525 struct mlx5_ib_qp_base *base, 526 struct ib_qp_init_attr *attr) 527 { 528 int desc_sz = 1 << qp->sq.wqe_shift; 529 530 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 531 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 532 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 533 return -EINVAL; 534 } 535 536 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 537 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 538 ucmd->sq_wqe_count); 539 return -EINVAL; 540 } 541 542 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 543 544 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 545 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 546 qp->sq.wqe_cnt, 547 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 548 return -EINVAL; 549 } 550 551 if (attr->qp_type == IB_QPT_RAW_PACKET || 552 qp->flags & MLX5_IB_QP_UNDERLAY) { 553 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 554 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 555 } else { 556 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 557 (qp->sq.wqe_cnt << 6); 558 } 559 560 return 0; 561 } 562 563 static int qp_has_rq(struct ib_qp_init_attr *attr) 564 { 565 if (attr->qp_type == IB_QPT_XRC_INI || 566 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 567 attr->qp_type == MLX5_IB_QPT_REG_UMR || 568 !attr->cap.max_recv_wr) 569 return 0; 570 571 return 1; 572 } 573 574 enum { 575 /* this is the first blue flame register in the array of bfregs assigned 576 * to a processes. Since we do not use it for blue flame but rather 577 * regular 64 bit doorbells, we do not need a lock for maintaiing 578 * "odd/even" order 579 */ 580 NUM_NON_BLUE_FLAME_BFREGS = 1, 581 }; 582 583 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 584 { 585 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 586 } 587 588 static int num_med_bfreg(struct mlx5_ib_dev *dev, 589 struct mlx5_bfreg_info *bfregi) 590 { 591 int n; 592 593 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 594 NUM_NON_BLUE_FLAME_BFREGS; 595 596 return n >= 0 ? n : 0; 597 } 598 599 static int first_med_bfreg(struct mlx5_ib_dev *dev, 600 struct mlx5_bfreg_info *bfregi) 601 { 602 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 603 } 604 605 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 606 struct mlx5_bfreg_info *bfregi) 607 { 608 int med; 609 610 med = num_med_bfreg(dev, bfregi); 611 return ++med; 612 } 613 614 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 615 struct mlx5_bfreg_info *bfregi) 616 { 617 int i; 618 619 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 620 if (!bfregi->count[i]) { 621 bfregi->count[i]++; 622 return i; 623 } 624 } 625 626 return -ENOMEM; 627 } 628 629 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 630 struct mlx5_bfreg_info *bfregi) 631 { 632 int minidx = first_med_bfreg(dev, bfregi); 633 int i; 634 635 if (minidx < 0) 636 return minidx; 637 638 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 639 if (bfregi->count[i] < bfregi->count[minidx]) 640 minidx = i; 641 if (!bfregi->count[minidx]) 642 break; 643 } 644 645 bfregi->count[minidx]++; 646 return minidx; 647 } 648 649 static int alloc_bfreg(struct mlx5_ib_dev *dev, 650 struct mlx5_bfreg_info *bfregi) 651 { 652 int bfregn = -ENOMEM; 653 654 mutex_lock(&bfregi->lock); 655 if (bfregi->ver >= 2) { 656 bfregn = alloc_high_class_bfreg(dev, bfregi); 657 if (bfregn < 0) 658 bfregn = alloc_med_class_bfreg(dev, bfregi); 659 } 660 661 if (bfregn < 0) { 662 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 663 bfregn = 0; 664 bfregi->count[bfregn]++; 665 } 666 mutex_unlock(&bfregi->lock); 667 668 return bfregn; 669 } 670 671 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 672 { 673 mutex_lock(&bfregi->lock); 674 bfregi->count[bfregn]--; 675 mutex_unlock(&bfregi->lock); 676 } 677 678 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 679 { 680 switch (state) { 681 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 682 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 683 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 684 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 685 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 686 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 687 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 688 default: return -1; 689 } 690 } 691 692 static int to_mlx5_st(enum ib_qp_type type) 693 { 694 switch (type) { 695 case IB_QPT_RC: return MLX5_QP_ST_RC; 696 case IB_QPT_UC: return MLX5_QP_ST_UC; 697 case IB_QPT_UD: return MLX5_QP_ST_UD; 698 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 699 case IB_QPT_XRC_INI: 700 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 701 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 702 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 703 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 704 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 705 case IB_QPT_RAW_PACKET: 706 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 707 case IB_QPT_MAX: 708 default: return -EINVAL; 709 } 710 } 711 712 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 713 struct mlx5_ib_cq *recv_cq); 714 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 715 struct mlx5_ib_cq *recv_cq); 716 717 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 718 struct mlx5_bfreg_info *bfregi, u32 bfregn, 719 bool dyn_bfreg) 720 { 721 unsigned int bfregs_per_sys_page; 722 u32 index_of_sys_page; 723 u32 offset; 724 725 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 726 MLX5_NON_FP_BFREGS_PER_UAR; 727 index_of_sys_page = bfregn / bfregs_per_sys_page; 728 729 if (dyn_bfreg) { 730 index_of_sys_page += bfregi->num_static_sys_pages; 731 732 if (index_of_sys_page >= bfregi->num_sys_pages) 733 return -EINVAL; 734 735 if (bfregn > bfregi->num_dyn_bfregs || 736 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 737 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 738 return -EINVAL; 739 } 740 } 741 742 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 743 return bfregi->sys_pages[index_of_sys_page] + offset; 744 } 745 746 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, 747 unsigned long addr, size_t size, 748 struct ib_umem **umem, int *npages, int *page_shift, 749 int *ncont, u32 *offset) 750 { 751 int err; 752 753 *umem = ib_umem_get(udata, addr, size, 0, 0); 754 if (IS_ERR(*umem)) { 755 mlx5_ib_dbg(dev, "umem_get failed\n"); 756 return PTR_ERR(*umem); 757 } 758 759 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 760 761 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 762 if (err) { 763 mlx5_ib_warn(dev, "bad offset\n"); 764 goto err_umem; 765 } 766 767 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 768 addr, size, *npages, *page_shift, *ncont, *offset); 769 770 return 0; 771 772 err_umem: 773 ib_umem_release(*umem); 774 *umem = NULL; 775 776 return err; 777 } 778 779 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 780 struct mlx5_ib_rwq *rwq) 781 { 782 struct mlx5_ib_ucontext *context; 783 784 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 785 atomic_dec(&dev->delay_drop.rqs_cnt); 786 787 context = to_mucontext(pd->uobject->context); 788 mlx5_ib_db_unmap_user(context, &rwq->db); 789 if (rwq->umem) 790 ib_umem_release(rwq->umem); 791 } 792 793 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 794 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 795 struct mlx5_ib_create_wq *ucmd) 796 { 797 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 798 udata, struct mlx5_ib_ucontext, ibucontext); 799 int page_shift = 0; 800 int npages; 801 u32 offset = 0; 802 int ncont = 0; 803 int err; 804 805 if (!ucmd->buf_addr) 806 return -EINVAL; 807 808 rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0); 809 if (IS_ERR(rwq->umem)) { 810 mlx5_ib_dbg(dev, "umem_get failed\n"); 811 err = PTR_ERR(rwq->umem); 812 return err; 813 } 814 815 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 816 &ncont, NULL); 817 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 818 &rwq->rq_page_offset); 819 if (err) { 820 mlx5_ib_warn(dev, "bad offset\n"); 821 goto err_umem; 822 } 823 824 rwq->rq_num_pas = ncont; 825 rwq->page_shift = page_shift; 826 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 827 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 828 829 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 830 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 831 npages, page_shift, ncont, offset); 832 833 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 834 if (err) { 835 mlx5_ib_dbg(dev, "map failed\n"); 836 goto err_umem; 837 } 838 839 rwq->create_type = MLX5_WQ_USER; 840 return 0; 841 842 err_umem: 843 ib_umem_release(rwq->umem); 844 return err; 845 } 846 847 static int adjust_bfregn(struct mlx5_ib_dev *dev, 848 struct mlx5_bfreg_info *bfregi, int bfregn) 849 { 850 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 851 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 852 } 853 854 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 855 struct mlx5_ib_qp *qp, struct ib_udata *udata, 856 struct ib_qp_init_attr *attr, 857 u32 **in, 858 struct mlx5_ib_create_qp_resp *resp, int *inlen, 859 struct mlx5_ib_qp_base *base) 860 { 861 struct mlx5_ib_ucontext *context; 862 struct mlx5_ib_create_qp ucmd; 863 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 864 int page_shift = 0; 865 int uar_index = 0; 866 int npages; 867 u32 offset = 0; 868 int bfregn; 869 int ncont = 0; 870 __be64 *pas; 871 void *qpc; 872 int err; 873 u16 uid; 874 875 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 876 if (err) { 877 mlx5_ib_dbg(dev, "copy failed\n"); 878 return err; 879 } 880 881 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 882 ibucontext); 883 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 884 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 885 ucmd.bfreg_index, true); 886 if (uar_index < 0) 887 return uar_index; 888 889 bfregn = MLX5_IB_INVALID_BFREG; 890 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 891 /* 892 * TBD: should come from the verbs when we have the API 893 */ 894 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 895 bfregn = MLX5_CROSS_CHANNEL_BFREG; 896 } 897 else { 898 bfregn = alloc_bfreg(dev, &context->bfregi); 899 if (bfregn < 0) 900 return bfregn; 901 } 902 903 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 904 if (bfregn != MLX5_IB_INVALID_BFREG) 905 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 906 false); 907 908 qp->rq.offset = 0; 909 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 910 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 911 912 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 913 if (err) 914 goto err_bfreg; 915 916 if (ucmd.buf_addr && ubuffer->buf_size) { 917 ubuffer->buf_addr = ucmd.buf_addr; 918 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, 919 ubuffer->buf_size, &ubuffer->umem, 920 &npages, &page_shift, &ncont, &offset); 921 if (err) 922 goto err_bfreg; 923 } else { 924 ubuffer->umem = NULL; 925 } 926 927 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 928 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 929 *in = kvzalloc(*inlen, GFP_KERNEL); 930 if (!*in) { 931 err = -ENOMEM; 932 goto err_umem; 933 } 934 935 uid = (attr->qp_type != IB_QPT_XRC_TGT && 936 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 937 MLX5_SET(create_qp_in, *in, uid, uid); 938 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 939 if (ubuffer->umem) 940 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 941 942 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 943 944 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 945 MLX5_SET(qpc, qpc, page_offset, offset); 946 947 MLX5_SET(qpc, qpc, uar_page, uar_index); 948 if (bfregn != MLX5_IB_INVALID_BFREG) 949 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 950 else 951 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 952 qp->bfregn = bfregn; 953 954 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db); 955 if (err) { 956 mlx5_ib_dbg(dev, "map failed\n"); 957 goto err_free; 958 } 959 960 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 961 if (err) { 962 mlx5_ib_dbg(dev, "copy failed\n"); 963 goto err_unmap; 964 } 965 qp->create_type = MLX5_QP_USER; 966 967 return 0; 968 969 err_unmap: 970 mlx5_ib_db_unmap_user(context, &qp->db); 971 972 err_free: 973 kvfree(*in); 974 975 err_umem: 976 if (ubuffer->umem) 977 ib_umem_release(ubuffer->umem); 978 979 err_bfreg: 980 if (bfregn != MLX5_IB_INVALID_BFREG) 981 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 982 return err; 983 } 984 985 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 986 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 987 { 988 struct mlx5_ib_ucontext *context; 989 990 context = to_mucontext(pd->uobject->context); 991 mlx5_ib_db_unmap_user(context, &qp->db); 992 if (base->ubuffer.umem) 993 ib_umem_release(base->ubuffer.umem); 994 995 /* 996 * Free only the BFREGs which are handled by the kernel. 997 * BFREGs of UARs allocated dynamically are handled by user. 998 */ 999 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1000 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1001 } 1002 1003 /* get_sq_edge - Get the next nearby edge. 1004 * 1005 * An 'edge' is defined as the first following address after the end 1006 * of the fragment or the SQ. Accordingly, during the WQE construction 1007 * which repetitively increases the pointer to write the next data, it 1008 * simply should check if it gets to an edge. 1009 * 1010 * @sq - SQ buffer. 1011 * @idx - Stride index in the SQ buffer. 1012 * 1013 * Return: 1014 * The new edge. 1015 */ 1016 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) 1017 { 1018 void *fragment_end; 1019 1020 fragment_end = mlx5_frag_buf_get_wqe 1021 (&sq->fbc, 1022 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); 1023 1024 return fragment_end + MLX5_SEND_WQE_BB; 1025 } 1026 1027 static int create_kernel_qp(struct mlx5_ib_dev *dev, 1028 struct ib_qp_init_attr *init_attr, 1029 struct mlx5_ib_qp *qp, 1030 u32 **in, int *inlen, 1031 struct mlx5_ib_qp_base *base) 1032 { 1033 int uar_index; 1034 void *qpc; 1035 int err; 1036 1037 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 1038 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 1039 IB_QP_CREATE_IPOIB_UD_LSO | 1040 IB_QP_CREATE_NETIF_QP | 1041 mlx5_ib_create_qp_sqpn_qp1())) 1042 return -EINVAL; 1043 1044 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1045 qp->bf.bfreg = &dev->fp_bfreg; 1046 else 1047 qp->bf.bfreg = &dev->bfreg; 1048 1049 /* We need to divide by two since each register is comprised of 1050 * two buffers of identical size, namely odd and even 1051 */ 1052 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1053 uar_index = qp->bf.bfreg->index; 1054 1055 err = calc_sq_size(dev, init_attr, qp); 1056 if (err < 0) { 1057 mlx5_ib_dbg(dev, "err %d\n", err); 1058 return err; 1059 } 1060 1061 qp->rq.offset = 0; 1062 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1063 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1064 1065 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1066 &qp->buf, dev->mdev->priv.numa_node); 1067 if (err) { 1068 mlx5_ib_dbg(dev, "err %d\n", err); 1069 return err; 1070 } 1071 1072 if (qp->rq.wqe_cnt) 1073 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1074 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1075 1076 if (qp->sq.wqe_cnt) { 1077 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1078 MLX5_SEND_WQE_BB; 1079 mlx5_init_fbc_offset(qp->buf.frags + 1080 (qp->sq.offset / PAGE_SIZE), 1081 ilog2(MLX5_SEND_WQE_BB), 1082 ilog2(qp->sq.wqe_cnt), 1083 sq_strides_offset, &qp->sq.fbc); 1084 1085 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1086 } 1087 1088 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1089 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1090 *in = kvzalloc(*inlen, GFP_KERNEL); 1091 if (!*in) { 1092 err = -ENOMEM; 1093 goto err_buf; 1094 } 1095 1096 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1097 MLX5_SET(qpc, qpc, uar_page, uar_index); 1098 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1099 1100 /* Set "fast registration enabled" for all kernel QPs */ 1101 MLX5_SET(qpc, qpc, fre, 1); 1102 MLX5_SET(qpc, qpc, rlky, 1); 1103 1104 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 1105 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1106 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1107 } 1108 1109 mlx5_fill_page_frag_array(&qp->buf, 1110 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1111 *in, pas)); 1112 1113 err = mlx5_db_alloc(dev->mdev, &qp->db); 1114 if (err) { 1115 mlx5_ib_dbg(dev, "err %d\n", err); 1116 goto err_free; 1117 } 1118 1119 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1120 sizeof(*qp->sq.wrid), GFP_KERNEL); 1121 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1122 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1123 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1124 sizeof(*qp->rq.wrid), GFP_KERNEL); 1125 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1126 sizeof(*qp->sq.w_list), GFP_KERNEL); 1127 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1128 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1129 1130 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1131 !qp->sq.w_list || !qp->sq.wqe_head) { 1132 err = -ENOMEM; 1133 goto err_wrid; 1134 } 1135 qp->create_type = MLX5_QP_KERNEL; 1136 1137 return 0; 1138 1139 err_wrid: 1140 kvfree(qp->sq.wqe_head); 1141 kvfree(qp->sq.w_list); 1142 kvfree(qp->sq.wrid); 1143 kvfree(qp->sq.wr_data); 1144 kvfree(qp->rq.wrid); 1145 mlx5_db_free(dev->mdev, &qp->db); 1146 1147 err_free: 1148 kvfree(*in); 1149 1150 err_buf: 1151 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1152 return err; 1153 } 1154 1155 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1156 { 1157 kvfree(qp->sq.wqe_head); 1158 kvfree(qp->sq.w_list); 1159 kvfree(qp->sq.wrid); 1160 kvfree(qp->sq.wr_data); 1161 kvfree(qp->rq.wrid); 1162 mlx5_db_free(dev->mdev, &qp->db); 1163 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1164 } 1165 1166 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1167 { 1168 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1169 (attr->qp_type == MLX5_IB_QPT_DCI) || 1170 (attr->qp_type == IB_QPT_XRC_INI)) 1171 return MLX5_SRQ_RQ; 1172 else if (!qp->has_rq) 1173 return MLX5_ZERO_LEN_RQ; 1174 else 1175 return MLX5_NON_ZERO_RQ; 1176 } 1177 1178 static int is_connected(enum ib_qp_type qp_type) 1179 { 1180 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || 1181 qp_type == MLX5_IB_QPT_DCI) 1182 return 1; 1183 1184 return 0; 1185 } 1186 1187 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1188 struct mlx5_ib_qp *qp, 1189 struct mlx5_ib_sq *sq, u32 tdn, 1190 struct ib_pd *pd) 1191 { 1192 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1193 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1194 1195 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1196 MLX5_SET(tisc, tisc, transport_domain, tdn); 1197 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1198 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1199 1200 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1201 } 1202 1203 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1204 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1205 { 1206 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1207 } 1208 1209 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1210 struct mlx5_ib_sq *sq) 1211 { 1212 if (sq->flow_rule) 1213 mlx5_del_flow_rules(sq->flow_rule); 1214 } 1215 1216 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1217 struct ib_udata *udata, 1218 struct mlx5_ib_sq *sq, void *qpin, 1219 struct ib_pd *pd) 1220 { 1221 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1222 __be64 *pas; 1223 void *in; 1224 void *sqc; 1225 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1226 void *wq; 1227 int inlen; 1228 int err; 1229 int page_shift = 0; 1230 int npages; 1231 int ncont = 0; 1232 u32 offset = 0; 1233 1234 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, 1235 &sq->ubuffer.umem, &npages, &page_shift, &ncont, 1236 &offset); 1237 if (err) 1238 return err; 1239 1240 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1241 in = kvzalloc(inlen, GFP_KERNEL); 1242 if (!in) { 1243 err = -ENOMEM; 1244 goto err_umem; 1245 } 1246 1247 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1248 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1249 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1250 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1251 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1252 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1253 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1254 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1255 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1256 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1257 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1258 MLX5_CAP_ETH(dev->mdev, swp)) 1259 MLX5_SET(sqc, sqc, allow_swp, 1); 1260 1261 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1262 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1263 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1264 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1265 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1266 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1267 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1268 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1269 MLX5_SET(wq, wq, page_offset, offset); 1270 1271 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1272 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1273 1274 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1275 1276 kvfree(in); 1277 1278 if (err) 1279 goto err_umem; 1280 1281 err = create_flow_rule_vport_sq(dev, sq); 1282 if (err) 1283 goto err_flow; 1284 1285 return 0; 1286 1287 err_flow: 1288 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1289 1290 err_umem: 1291 ib_umem_release(sq->ubuffer.umem); 1292 sq->ubuffer.umem = NULL; 1293 1294 return err; 1295 } 1296 1297 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1298 struct mlx5_ib_sq *sq) 1299 { 1300 destroy_flow_rule_vport_sq(dev, sq); 1301 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1302 ib_umem_release(sq->ubuffer.umem); 1303 } 1304 1305 static size_t get_rq_pas_size(void *qpc) 1306 { 1307 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1308 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1309 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1310 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1311 u32 po_quanta = 1 << (log_page_size - 6); 1312 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1313 u32 page_size = 1 << log_page_size; 1314 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1315 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1316 1317 return rq_num_pas * sizeof(u64); 1318 } 1319 1320 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1321 struct mlx5_ib_rq *rq, void *qpin, 1322 size_t qpinlen, struct ib_pd *pd) 1323 { 1324 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1325 __be64 *pas; 1326 __be64 *qp_pas; 1327 void *in; 1328 void *rqc; 1329 void *wq; 1330 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1331 size_t rq_pas_size = get_rq_pas_size(qpc); 1332 size_t inlen; 1333 int err; 1334 1335 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1336 return -EINVAL; 1337 1338 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1339 in = kvzalloc(inlen, GFP_KERNEL); 1340 if (!in) 1341 return -ENOMEM; 1342 1343 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1344 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1345 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1346 MLX5_SET(rqc, rqc, vsd, 1); 1347 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1348 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1349 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1350 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1351 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1352 1353 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1354 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1355 1356 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1357 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1358 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1359 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1360 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1361 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1362 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1363 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1364 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1365 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1366 1367 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1368 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1369 memcpy(pas, qp_pas, rq_pas_size); 1370 1371 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1372 1373 kvfree(in); 1374 1375 return err; 1376 } 1377 1378 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1379 struct mlx5_ib_rq *rq) 1380 { 1381 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1382 } 1383 1384 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1385 { 1386 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1387 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1388 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1389 } 1390 1391 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1392 struct mlx5_ib_rq *rq, 1393 u32 qp_flags_en, 1394 struct ib_pd *pd) 1395 { 1396 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1397 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1398 mlx5_ib_disable_lb(dev, false, true); 1399 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1400 } 1401 1402 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1403 struct mlx5_ib_rq *rq, u32 tdn, 1404 u32 *qp_flags_en, 1405 struct ib_pd *pd) 1406 { 1407 u8 lb_flag = 0; 1408 u32 *in; 1409 void *tirc; 1410 int inlen; 1411 int err; 1412 1413 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1414 in = kvzalloc(inlen, GFP_KERNEL); 1415 if (!in) 1416 return -ENOMEM; 1417 1418 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1419 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1420 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1421 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1422 MLX5_SET(tirc, tirc, transport_domain, tdn); 1423 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1424 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1425 1426 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1427 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1428 1429 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1430 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1431 1432 if (dev->rep) { 1433 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1434 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1435 } 1436 1437 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1438 1439 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1440 1441 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1442 err = mlx5_ib_enable_lb(dev, false, true); 1443 1444 if (err) 1445 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1446 } 1447 kvfree(in); 1448 1449 return err; 1450 } 1451 1452 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1453 u32 *in, size_t inlen, 1454 struct ib_pd *pd, 1455 struct ib_udata *udata, 1456 struct mlx5_ib_create_qp_resp *resp) 1457 { 1458 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1459 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1460 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1461 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1462 udata, struct mlx5_ib_ucontext, ibucontext); 1463 int err; 1464 u32 tdn = mucontext->tdn; 1465 u16 uid = to_mpd(pd)->uid; 1466 1467 if (qp->sq.wqe_cnt) { 1468 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1469 if (err) 1470 return err; 1471 1472 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); 1473 if (err) 1474 goto err_destroy_tis; 1475 1476 if (uid) { 1477 resp->tisn = sq->tisn; 1478 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1479 resp->sqn = sq->base.mqp.qpn; 1480 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1481 } 1482 1483 sq->base.container_mibqp = qp; 1484 sq->base.mqp.event = mlx5_ib_qp_event; 1485 } 1486 1487 if (qp->rq.wqe_cnt) { 1488 rq->base.container_mibqp = qp; 1489 1490 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1491 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1492 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1493 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1494 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1495 if (err) 1496 goto err_destroy_sq; 1497 1498 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd); 1499 if (err) 1500 goto err_destroy_rq; 1501 1502 if (uid) { 1503 resp->rqn = rq->base.mqp.qpn; 1504 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1505 resp->tirn = rq->tirn; 1506 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1507 } 1508 } 1509 1510 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1511 rq->base.mqp.qpn; 1512 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1513 if (err) 1514 goto err_destroy_tir; 1515 1516 return 0; 1517 1518 err_destroy_tir: 1519 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); 1520 err_destroy_rq: 1521 destroy_raw_packet_qp_rq(dev, rq); 1522 err_destroy_sq: 1523 if (!qp->sq.wqe_cnt) 1524 return err; 1525 destroy_raw_packet_qp_sq(dev, sq); 1526 err_destroy_tis: 1527 destroy_raw_packet_qp_tis(dev, sq, pd); 1528 1529 return err; 1530 } 1531 1532 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1533 struct mlx5_ib_qp *qp) 1534 { 1535 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1536 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1537 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1538 1539 if (qp->rq.wqe_cnt) { 1540 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1541 destroy_raw_packet_qp_rq(dev, rq); 1542 } 1543 1544 if (qp->sq.wqe_cnt) { 1545 destroy_raw_packet_qp_sq(dev, sq); 1546 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1547 } 1548 } 1549 1550 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1551 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1552 { 1553 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1554 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1555 1556 sq->sq = &qp->sq; 1557 rq->rq = &qp->rq; 1558 sq->doorbell = &qp->db; 1559 rq->doorbell = &qp->db; 1560 } 1561 1562 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1563 { 1564 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1565 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1566 mlx5_ib_disable_lb(dev, false, true); 1567 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1568 to_mpd(qp->ibqp.pd)->uid); 1569 } 1570 1571 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1572 struct ib_pd *pd, 1573 struct ib_qp_init_attr *init_attr, 1574 struct ib_udata *udata) 1575 { 1576 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1577 udata, struct mlx5_ib_ucontext, ibucontext); 1578 struct mlx5_ib_create_qp_resp resp = {}; 1579 int inlen; 1580 int err; 1581 u32 *in; 1582 void *tirc; 1583 void *hfso; 1584 u32 selected_fields = 0; 1585 u32 outer_l4; 1586 size_t min_resp_len; 1587 u32 tdn = mucontext->tdn; 1588 struct mlx5_ib_create_qp_rss ucmd = {}; 1589 size_t required_cmd_sz; 1590 u8 lb_flag = 0; 1591 1592 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1593 return -EOPNOTSUPP; 1594 1595 if (init_attr->create_flags || init_attr->send_cq) 1596 return -EINVAL; 1597 1598 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1599 if (udata->outlen < min_resp_len) 1600 return -EINVAL; 1601 1602 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1603 if (udata->inlen < required_cmd_sz) { 1604 mlx5_ib_dbg(dev, "invalid inlen\n"); 1605 return -EINVAL; 1606 } 1607 1608 if (udata->inlen > sizeof(ucmd) && 1609 !ib_is_udata_cleared(udata, sizeof(ucmd), 1610 udata->inlen - sizeof(ucmd))) { 1611 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1612 return -EOPNOTSUPP; 1613 } 1614 1615 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1616 mlx5_ib_dbg(dev, "copy failed\n"); 1617 return -EFAULT; 1618 } 1619 1620 if (ucmd.comp_mask) { 1621 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1622 return -EOPNOTSUPP; 1623 } 1624 1625 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1626 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1627 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { 1628 mlx5_ib_dbg(dev, "invalid flags\n"); 1629 return -EOPNOTSUPP; 1630 } 1631 1632 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1633 !tunnel_offload_supported(dev->mdev)) { 1634 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1635 return -EOPNOTSUPP; 1636 } 1637 1638 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1639 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1640 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1641 return -EOPNOTSUPP; 1642 } 1643 1644 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) { 1645 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1646 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1647 } 1648 1649 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1650 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1651 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1652 } 1653 1654 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1655 if (err) { 1656 mlx5_ib_dbg(dev, "copy failed\n"); 1657 return -EINVAL; 1658 } 1659 1660 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1661 in = kvzalloc(inlen, GFP_KERNEL); 1662 if (!in) 1663 return -ENOMEM; 1664 1665 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1666 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1667 MLX5_SET(tirc, tirc, disp_type, 1668 MLX5_TIRC_DISP_TYPE_INDIRECT); 1669 MLX5_SET(tirc, tirc, indirect_table, 1670 init_attr->rwq_ind_tbl->ind_tbl_num); 1671 MLX5_SET(tirc, tirc, transport_domain, tdn); 1672 1673 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1674 1675 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1676 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1677 1678 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1679 1680 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1681 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1682 else 1683 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1684 1685 switch (ucmd.rx_hash_function) { 1686 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1687 { 1688 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1689 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1690 1691 if (len != ucmd.rx_key_len) { 1692 err = -EINVAL; 1693 goto err; 1694 } 1695 1696 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1697 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1698 memcpy(rss_key, ucmd.rx_hash_key, len); 1699 break; 1700 } 1701 default: 1702 err = -EOPNOTSUPP; 1703 goto err; 1704 } 1705 1706 if (!ucmd.rx_hash_fields_mask) { 1707 /* special case when this TIR serves as steering entry without hashing */ 1708 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1709 goto create_tir; 1710 err = -EINVAL; 1711 goto err; 1712 } 1713 1714 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1715 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1716 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1717 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1718 err = -EINVAL; 1719 goto err; 1720 } 1721 1722 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1723 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1724 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1725 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1726 MLX5_L3_PROT_TYPE_IPV4); 1727 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1728 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1729 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1730 MLX5_L3_PROT_TYPE_IPV6); 1731 1732 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1733 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1734 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1735 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1736 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1737 1738 /* Check that only one l4 protocol is set */ 1739 if (outer_l4 & (outer_l4 - 1)) { 1740 err = -EINVAL; 1741 goto err; 1742 } 1743 1744 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1745 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1746 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1747 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1748 MLX5_L4_PROT_TYPE_TCP); 1749 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1750 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1751 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1752 MLX5_L4_PROT_TYPE_UDP); 1753 1754 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1755 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1756 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1757 1758 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1759 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1760 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1761 1762 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1763 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1764 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1765 1766 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1767 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1768 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1769 1770 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1771 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1772 1773 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1774 1775 create_tir: 1776 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1777 1778 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1779 err = mlx5_ib_enable_lb(dev, false, true); 1780 1781 if (err) 1782 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1783 to_mpd(pd)->uid); 1784 } 1785 1786 if (err) 1787 goto err; 1788 1789 if (mucontext->devx_uid) { 1790 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1791 resp.tirn = qp->rss_qp.tirn; 1792 } 1793 1794 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1795 if (err) 1796 goto err_copy; 1797 1798 kvfree(in); 1799 /* qpn is reserved for that QP */ 1800 qp->trans_qp.base.mqp.qpn = 0; 1801 qp->flags |= MLX5_IB_QP_RSS; 1802 return 0; 1803 1804 err_copy: 1805 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); 1806 err: 1807 kvfree(in); 1808 return err; 1809 } 1810 1811 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, 1812 void *qpc) 1813 { 1814 int rcqe_sz; 1815 1816 if (init_attr->qp_type == MLX5_IB_QPT_DCI) 1817 return; 1818 1819 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1820 1821 if (init_attr->qp_type == MLX5_IB_QPT_DCT) { 1822 if (rcqe_sz == 128) 1823 MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1824 1825 return; 1826 } 1827 1828 MLX5_SET(qpc, qpc, cs_res, 1829 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 1830 MLX5_RES_SCAT_DATA32_CQE); 1831 } 1832 1833 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1834 struct ib_qp_init_attr *init_attr, 1835 struct mlx5_ib_create_qp *ucmd, 1836 void *qpc) 1837 { 1838 enum ib_qp_type qpt = init_attr->qp_type; 1839 int scqe_sz; 1840 bool allow_scat_cqe = 0; 1841 1842 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) 1843 return; 1844 1845 if (ucmd) 1846 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1847 1848 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1849 return; 1850 1851 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1852 if (scqe_sz == 128) { 1853 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1854 return; 1855 } 1856 1857 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1858 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1859 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1860 } 1861 1862 static int atomic_size_to_mode(int size_mask) 1863 { 1864 /* driver does not support atomic_size > 256B 1865 * and does not know how to translate bigger sizes 1866 */ 1867 int supported_size_mask = size_mask & 0x1ff; 1868 int log_max_size; 1869 1870 if (!supported_size_mask) 1871 return -EOPNOTSUPP; 1872 1873 log_max_size = __fls(supported_size_mask); 1874 1875 if (log_max_size > 3) 1876 return log_max_size; 1877 1878 return MLX5_ATOMIC_MODE_8B; 1879 } 1880 1881 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1882 enum ib_qp_type qp_type) 1883 { 1884 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1885 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1886 int atomic_mode = -EOPNOTSUPP; 1887 int atomic_size_mask; 1888 1889 if (!atomic) 1890 return -EOPNOTSUPP; 1891 1892 if (qp_type == MLX5_IB_QPT_DCT) 1893 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1894 else 1895 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1896 1897 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1898 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1899 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1900 1901 if (atomic_mode <= 0 && 1902 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1903 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1904 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1905 1906 return atomic_mode; 1907 } 1908 1909 static inline bool check_flags_mask(uint64_t input, uint64_t supported) 1910 { 1911 return (input & ~supported) == 0; 1912 } 1913 1914 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1915 struct ib_qp_init_attr *init_attr, 1916 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1917 { 1918 struct mlx5_ib_resources *devr = &dev->devr; 1919 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1920 struct mlx5_core_dev *mdev = dev->mdev; 1921 struct mlx5_ib_create_qp_resp resp = {}; 1922 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 1923 udata, struct mlx5_ib_ucontext, ibucontext); 1924 struct mlx5_ib_cq *send_cq; 1925 struct mlx5_ib_cq *recv_cq; 1926 unsigned long flags; 1927 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1928 struct mlx5_ib_create_qp ucmd; 1929 struct mlx5_ib_qp_base *base; 1930 int mlx5_st; 1931 void *qpc; 1932 u32 *in; 1933 int err; 1934 1935 mutex_init(&qp->mutex); 1936 spin_lock_init(&qp->sq.lock); 1937 spin_lock_init(&qp->rq.lock); 1938 1939 mlx5_st = to_mlx5_st(init_attr->qp_type); 1940 if (mlx5_st < 0) 1941 return -EINVAL; 1942 1943 if (init_attr->rwq_ind_tbl) { 1944 if (!udata) 1945 return -ENOSYS; 1946 1947 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1948 return err; 1949 } 1950 1951 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1952 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1953 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1954 return -EINVAL; 1955 } else { 1956 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1957 } 1958 } 1959 1960 if (init_attr->create_flags & 1961 (IB_QP_CREATE_CROSS_CHANNEL | 1962 IB_QP_CREATE_MANAGED_SEND | 1963 IB_QP_CREATE_MANAGED_RECV)) { 1964 if (!MLX5_CAP_GEN(mdev, cd)) { 1965 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1966 return -EINVAL; 1967 } 1968 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1969 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1970 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1971 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1972 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1973 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1974 } 1975 1976 if (init_attr->qp_type == IB_QPT_UD && 1977 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1978 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1979 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1980 return -EOPNOTSUPP; 1981 } 1982 1983 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1984 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1985 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1986 return -EOPNOTSUPP; 1987 } 1988 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1989 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1990 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1991 return -EOPNOTSUPP; 1992 } 1993 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1994 } 1995 1996 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1997 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1998 1999 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 2000 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 2001 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 2002 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 2003 return -EOPNOTSUPP; 2004 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 2005 } 2006 2007 if (udata) { 2008 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 2009 mlx5_ib_dbg(dev, "copy failed\n"); 2010 return -EFAULT; 2011 } 2012 2013 if (!check_flags_mask(ucmd.flags, 2014 MLX5_QP_FLAG_ALLOW_SCATTER_CQE | 2015 MLX5_QP_FLAG_BFREG_INDEX | 2016 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE | 2017 MLX5_QP_FLAG_SCATTER_CQE | 2018 MLX5_QP_FLAG_SIGNATURE | 2019 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC | 2020 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2021 MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2022 MLX5_QP_FLAG_TYPE_DCI | 2023 MLX5_QP_FLAG_TYPE_DCT)) 2024 return -EINVAL; 2025 2026 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx); 2027 if (err) 2028 return err; 2029 2030 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 2031 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) 2032 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 2033 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 2034 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 2035 !tunnel_offload_supported(mdev)) { 2036 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 2037 return -EOPNOTSUPP; 2038 } 2039 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; 2040 } 2041 2042 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { 2043 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2044 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); 2045 return -EOPNOTSUPP; 2046 } 2047 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 2048 } 2049 2050 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 2051 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2052 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); 2053 return -EOPNOTSUPP; 2054 } 2055 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 2056 } 2057 2058 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { 2059 if (init_attr->qp_type != IB_QPT_RC || 2060 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { 2061 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); 2062 return -EOPNOTSUPP; 2063 } 2064 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; 2065 } 2066 2067 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 2068 if (init_attr->qp_type != IB_QPT_UD || 2069 (MLX5_CAP_GEN(dev->mdev, port_type) != 2070 MLX5_CAP_PORT_TYPE_IB) || 2071 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 2072 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 2073 return -EOPNOTSUPP; 2074 } 2075 2076 qp->flags |= MLX5_IB_QP_UNDERLAY; 2077 qp->underlay_qpn = init_attr->source_qpn; 2078 } 2079 } else { 2080 qp->wq_sig = !!wq_signature; 2081 } 2082 2083 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2084 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2085 &qp->raw_packet_qp.rq.base : 2086 &qp->trans_qp.base; 2087 2088 qp->has_rq = qp_has_rq(init_attr); 2089 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 2090 qp, udata ? &ucmd : NULL); 2091 if (err) { 2092 mlx5_ib_dbg(dev, "err %d\n", err); 2093 return err; 2094 } 2095 2096 if (pd) { 2097 if (udata) { 2098 __u32 max_wqes = 2099 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 2100 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 2101 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 2102 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 2103 mlx5_ib_dbg(dev, "invalid rq params\n"); 2104 return -EINVAL; 2105 } 2106 if (ucmd.sq_wqe_count > max_wqes) { 2107 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 2108 ucmd.sq_wqe_count, max_wqes); 2109 return -EINVAL; 2110 } 2111 if (init_attr->create_flags & 2112 mlx5_ib_create_qp_sqpn_qp1()) { 2113 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 2114 return -EINVAL; 2115 } 2116 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 2117 &resp, &inlen, base); 2118 if (err) 2119 mlx5_ib_dbg(dev, "err %d\n", err); 2120 } else { 2121 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 2122 base); 2123 if (err) 2124 mlx5_ib_dbg(dev, "err %d\n", err); 2125 } 2126 2127 if (err) 2128 return err; 2129 } else { 2130 in = kvzalloc(inlen, GFP_KERNEL); 2131 if (!in) 2132 return -ENOMEM; 2133 2134 qp->create_type = MLX5_QP_EMPTY; 2135 } 2136 2137 if (is_sqp(init_attr->qp_type)) 2138 qp->port = init_attr->port_num; 2139 2140 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2141 2142 MLX5_SET(qpc, qpc, st, mlx5_st); 2143 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2144 2145 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 2146 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2147 else 2148 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2149 2150 2151 if (qp->wq_sig) 2152 MLX5_SET(qpc, qpc, wq_signature, 1); 2153 2154 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2155 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2156 2157 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 2158 MLX5_SET(qpc, qpc, cd_master, 1); 2159 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 2160 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2161 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 2162 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2163 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) 2164 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2165 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 2166 configure_responder_scat_cqe(init_attr, qpc); 2167 configure_requester_scat_cqe(dev, init_attr, 2168 udata ? &ucmd : NULL, 2169 qpc); 2170 } 2171 2172 if (qp->rq.wqe_cnt) { 2173 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2174 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2175 } 2176 2177 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2178 2179 if (qp->sq.wqe_cnt) { 2180 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2181 } else { 2182 MLX5_SET(qpc, qpc, no_sq, 1); 2183 if (init_attr->srq && 2184 init_attr->srq->srq_type == IB_SRQT_TM) 2185 MLX5_SET(qpc, qpc, offload_type, 2186 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2187 } 2188 2189 /* Set default resources */ 2190 switch (init_attr->qp_type) { 2191 case IB_QPT_XRC_TGT: 2192 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2193 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2194 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2195 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 2196 break; 2197 case IB_QPT_XRC_INI: 2198 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2199 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2200 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2201 break; 2202 default: 2203 if (init_attr->srq) { 2204 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2205 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2206 } else { 2207 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2208 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2209 } 2210 } 2211 2212 if (init_attr->send_cq) 2213 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2214 2215 if (init_attr->recv_cq) 2216 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2217 2218 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2219 2220 /* 0xffffff means we ask to work with cqe version 0 */ 2221 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2222 MLX5_SET(qpc, qpc, user_index, uidx); 2223 2224 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2225 if (init_attr->qp_type == IB_QPT_UD && 2226 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 2227 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2228 qp->flags |= MLX5_IB_QP_LSO; 2229 } 2230 2231 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2232 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 2233 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 2234 err = -EOPNOTSUPP; 2235 goto err; 2236 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2237 MLX5_SET(qpc, qpc, end_padding_mode, 2238 MLX5_WQ_END_PAD_MODE_ALIGN); 2239 } else { 2240 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 2241 } 2242 } 2243 2244 if (inlen < 0) { 2245 err = -EINVAL; 2246 goto err; 2247 } 2248 2249 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2250 qp->flags & MLX5_IB_QP_UNDERLAY) { 2251 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 2252 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2253 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2254 &resp); 2255 } else { 2256 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 2257 } 2258 2259 if (err) { 2260 mlx5_ib_dbg(dev, "create qp failed\n"); 2261 goto err_create; 2262 } 2263 2264 kvfree(in); 2265 2266 base->container_mibqp = qp; 2267 base->mqp.event = mlx5_ib_qp_event; 2268 2269 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 2270 &send_cq, &recv_cq); 2271 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2272 mlx5_ib_lock_cqs(send_cq, recv_cq); 2273 /* Maintain device to QPs access, needed for further handling via reset 2274 * flow 2275 */ 2276 list_add_tail(&qp->qps_list, &dev->qp_list); 2277 /* Maintain CQ to QPs access, needed for further handling via reset flow 2278 */ 2279 if (send_cq) 2280 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2281 if (recv_cq) 2282 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2283 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2284 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2285 2286 return 0; 2287 2288 err_create: 2289 if (qp->create_type == MLX5_QP_USER) 2290 destroy_qp_user(dev, pd, qp, base); 2291 else if (qp->create_type == MLX5_QP_KERNEL) 2292 destroy_qp_kernel(dev, qp); 2293 2294 err: 2295 kvfree(in); 2296 return err; 2297 } 2298 2299 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2300 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2301 { 2302 if (send_cq) { 2303 if (recv_cq) { 2304 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2305 spin_lock(&send_cq->lock); 2306 spin_lock_nested(&recv_cq->lock, 2307 SINGLE_DEPTH_NESTING); 2308 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2309 spin_lock(&send_cq->lock); 2310 __acquire(&recv_cq->lock); 2311 } else { 2312 spin_lock(&recv_cq->lock); 2313 spin_lock_nested(&send_cq->lock, 2314 SINGLE_DEPTH_NESTING); 2315 } 2316 } else { 2317 spin_lock(&send_cq->lock); 2318 __acquire(&recv_cq->lock); 2319 } 2320 } else if (recv_cq) { 2321 spin_lock(&recv_cq->lock); 2322 __acquire(&send_cq->lock); 2323 } else { 2324 __acquire(&send_cq->lock); 2325 __acquire(&recv_cq->lock); 2326 } 2327 } 2328 2329 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2330 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2331 { 2332 if (send_cq) { 2333 if (recv_cq) { 2334 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2335 spin_unlock(&recv_cq->lock); 2336 spin_unlock(&send_cq->lock); 2337 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2338 __release(&recv_cq->lock); 2339 spin_unlock(&send_cq->lock); 2340 } else { 2341 spin_unlock(&send_cq->lock); 2342 spin_unlock(&recv_cq->lock); 2343 } 2344 } else { 2345 __release(&recv_cq->lock); 2346 spin_unlock(&send_cq->lock); 2347 } 2348 } else if (recv_cq) { 2349 __release(&send_cq->lock); 2350 spin_unlock(&recv_cq->lock); 2351 } else { 2352 __release(&recv_cq->lock); 2353 __release(&send_cq->lock); 2354 } 2355 } 2356 2357 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2358 { 2359 return to_mpd(qp->ibqp.pd); 2360 } 2361 2362 static void get_cqs(enum ib_qp_type qp_type, 2363 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2364 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2365 { 2366 switch (qp_type) { 2367 case IB_QPT_XRC_TGT: 2368 *send_cq = NULL; 2369 *recv_cq = NULL; 2370 break; 2371 case MLX5_IB_QPT_REG_UMR: 2372 case IB_QPT_XRC_INI: 2373 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2374 *recv_cq = NULL; 2375 break; 2376 2377 case IB_QPT_SMI: 2378 case MLX5_IB_QPT_HW_GSI: 2379 case IB_QPT_RC: 2380 case IB_QPT_UC: 2381 case IB_QPT_UD: 2382 case IB_QPT_RAW_IPV6: 2383 case IB_QPT_RAW_ETHERTYPE: 2384 case IB_QPT_RAW_PACKET: 2385 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2386 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2387 break; 2388 2389 case IB_QPT_MAX: 2390 default: 2391 *send_cq = NULL; 2392 *recv_cq = NULL; 2393 break; 2394 } 2395 } 2396 2397 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2398 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2399 u8 lag_tx_affinity); 2400 2401 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2402 { 2403 struct mlx5_ib_cq *send_cq, *recv_cq; 2404 struct mlx5_ib_qp_base *base; 2405 unsigned long flags; 2406 int err; 2407 2408 if (qp->ibqp.rwq_ind_tbl) { 2409 destroy_rss_raw_qp_tir(dev, qp); 2410 return; 2411 } 2412 2413 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2414 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2415 &qp->raw_packet_qp.rq.base : 2416 &qp->trans_qp.base; 2417 2418 if (qp->state != IB_QPS_RESET) { 2419 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2420 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2421 err = mlx5_core_qp_modify(dev->mdev, 2422 MLX5_CMD_OP_2RST_QP, 0, 2423 NULL, &base->mqp); 2424 } else { 2425 struct mlx5_modify_raw_qp_param raw_qp_param = { 2426 .operation = MLX5_CMD_OP_2RST_QP 2427 }; 2428 2429 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2430 } 2431 if (err) 2432 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2433 base->mqp.qpn); 2434 } 2435 2436 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2437 &send_cq, &recv_cq); 2438 2439 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2440 mlx5_ib_lock_cqs(send_cq, recv_cq); 2441 /* del from lists under both locks above to protect reset flow paths */ 2442 list_del(&qp->qps_list); 2443 if (send_cq) 2444 list_del(&qp->cq_send_list); 2445 2446 if (recv_cq) 2447 list_del(&qp->cq_recv_list); 2448 2449 if (qp->create_type == MLX5_QP_KERNEL) { 2450 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2451 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2452 if (send_cq != recv_cq) 2453 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2454 NULL); 2455 } 2456 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2457 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2458 2459 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2460 qp->flags & MLX5_IB_QP_UNDERLAY) { 2461 destroy_raw_packet_qp(dev, qp); 2462 } else { 2463 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2464 if (err) 2465 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2466 base->mqp.qpn); 2467 } 2468 2469 if (qp->create_type == MLX5_QP_KERNEL) 2470 destroy_qp_kernel(dev, qp); 2471 else if (qp->create_type == MLX5_QP_USER) 2472 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2473 } 2474 2475 static const char *ib_qp_type_str(enum ib_qp_type type) 2476 { 2477 switch (type) { 2478 case IB_QPT_SMI: 2479 return "IB_QPT_SMI"; 2480 case IB_QPT_GSI: 2481 return "IB_QPT_GSI"; 2482 case IB_QPT_RC: 2483 return "IB_QPT_RC"; 2484 case IB_QPT_UC: 2485 return "IB_QPT_UC"; 2486 case IB_QPT_UD: 2487 return "IB_QPT_UD"; 2488 case IB_QPT_RAW_IPV6: 2489 return "IB_QPT_RAW_IPV6"; 2490 case IB_QPT_RAW_ETHERTYPE: 2491 return "IB_QPT_RAW_ETHERTYPE"; 2492 case IB_QPT_XRC_INI: 2493 return "IB_QPT_XRC_INI"; 2494 case IB_QPT_XRC_TGT: 2495 return "IB_QPT_XRC_TGT"; 2496 case IB_QPT_RAW_PACKET: 2497 return "IB_QPT_RAW_PACKET"; 2498 case MLX5_IB_QPT_REG_UMR: 2499 return "MLX5_IB_QPT_REG_UMR"; 2500 case IB_QPT_DRIVER: 2501 return "IB_QPT_DRIVER"; 2502 case IB_QPT_MAX: 2503 default: 2504 return "Invalid QP type"; 2505 } 2506 } 2507 2508 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2509 struct ib_qp_init_attr *attr, 2510 struct mlx5_ib_create_qp *ucmd, 2511 struct ib_udata *udata) 2512 { 2513 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2514 udata, struct mlx5_ib_ucontext, ibucontext); 2515 struct mlx5_ib_qp *qp; 2516 int err = 0; 2517 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2518 void *dctc; 2519 2520 if (!attr->srq || !attr->recv_cq) 2521 return ERR_PTR(-EINVAL); 2522 2523 err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx); 2524 if (err) 2525 return ERR_PTR(err); 2526 2527 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2528 if (!qp) 2529 return ERR_PTR(-ENOMEM); 2530 2531 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2532 if (!qp->dct.in) { 2533 err = -ENOMEM; 2534 goto err_free; 2535 } 2536 2537 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2538 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2539 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2540 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2541 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2542 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2543 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2544 MLX5_SET(dctc, dctc, user_index, uidx); 2545 2546 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) 2547 configure_responder_scat_cqe(attr, dctc); 2548 2549 qp->state = IB_QPS_RESET; 2550 2551 return &qp->ibqp; 2552 err_free: 2553 kfree(qp); 2554 return ERR_PTR(err); 2555 } 2556 2557 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2558 struct ib_qp_init_attr *init_attr, 2559 struct mlx5_ib_create_qp *ucmd, 2560 struct ib_udata *udata) 2561 { 2562 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2563 int err; 2564 2565 if (!udata) 2566 return -EINVAL; 2567 2568 if (udata->inlen < sizeof(*ucmd)) { 2569 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2570 return -EINVAL; 2571 } 2572 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2573 if (err) 2574 return err; 2575 2576 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2577 init_attr->qp_type = MLX5_IB_QPT_DCI; 2578 } else { 2579 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2580 init_attr->qp_type = MLX5_IB_QPT_DCT; 2581 } else { 2582 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2583 return -EINVAL; 2584 } 2585 } 2586 2587 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2588 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2589 return -EOPNOTSUPP; 2590 } 2591 2592 return 0; 2593 } 2594 2595 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2596 struct ib_qp_init_attr *verbs_init_attr, 2597 struct ib_udata *udata) 2598 { 2599 struct mlx5_ib_dev *dev; 2600 struct mlx5_ib_qp *qp; 2601 u16 xrcdn = 0; 2602 int err; 2603 struct ib_qp_init_attr mlx_init_attr; 2604 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2605 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2606 udata, struct mlx5_ib_ucontext, ibucontext); 2607 2608 if (pd) { 2609 dev = to_mdev(pd->device); 2610 2611 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2612 if (!ucontext) { 2613 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2614 return ERR_PTR(-EINVAL); 2615 } else if (!ucontext->cqe_version) { 2616 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2617 return ERR_PTR(-EINVAL); 2618 } 2619 } 2620 } else { 2621 /* being cautious here */ 2622 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2623 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2624 pr_warn("%s: no PD for transport %s\n", __func__, 2625 ib_qp_type_str(init_attr->qp_type)); 2626 return ERR_PTR(-EINVAL); 2627 } 2628 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2629 } 2630 2631 if (init_attr->qp_type == IB_QPT_DRIVER) { 2632 struct mlx5_ib_create_qp ucmd; 2633 2634 init_attr = &mlx_init_attr; 2635 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2636 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2637 if (err) 2638 return ERR_PTR(err); 2639 2640 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2641 if (init_attr->cap.max_recv_wr || 2642 init_attr->cap.max_recv_sge) { 2643 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2644 return ERR_PTR(-EINVAL); 2645 } 2646 } else { 2647 return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata); 2648 } 2649 } 2650 2651 switch (init_attr->qp_type) { 2652 case IB_QPT_XRC_TGT: 2653 case IB_QPT_XRC_INI: 2654 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2655 mlx5_ib_dbg(dev, "XRC not supported\n"); 2656 return ERR_PTR(-ENOSYS); 2657 } 2658 init_attr->recv_cq = NULL; 2659 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2660 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2661 init_attr->send_cq = NULL; 2662 } 2663 2664 /* fall through */ 2665 case IB_QPT_RAW_PACKET: 2666 case IB_QPT_RC: 2667 case IB_QPT_UC: 2668 case IB_QPT_UD: 2669 case IB_QPT_SMI: 2670 case MLX5_IB_QPT_HW_GSI: 2671 case MLX5_IB_QPT_REG_UMR: 2672 case MLX5_IB_QPT_DCI: 2673 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2674 if (!qp) 2675 return ERR_PTR(-ENOMEM); 2676 2677 err = create_qp_common(dev, pd, init_attr, udata, qp); 2678 if (err) { 2679 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2680 kfree(qp); 2681 return ERR_PTR(err); 2682 } 2683 2684 if (is_qp0(init_attr->qp_type)) 2685 qp->ibqp.qp_num = 0; 2686 else if (is_qp1(init_attr->qp_type)) 2687 qp->ibqp.qp_num = 1; 2688 else 2689 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2690 2691 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2692 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2693 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2694 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2695 2696 qp->trans_qp.xrcdn = xrcdn; 2697 2698 break; 2699 2700 case IB_QPT_GSI: 2701 return mlx5_ib_gsi_create_qp(pd, init_attr); 2702 2703 case IB_QPT_RAW_IPV6: 2704 case IB_QPT_RAW_ETHERTYPE: 2705 case IB_QPT_MAX: 2706 default: 2707 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2708 init_attr->qp_type); 2709 /* Don't support raw QPs */ 2710 return ERR_PTR(-EINVAL); 2711 } 2712 2713 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2714 qp->qp_sub_type = init_attr->qp_type; 2715 2716 return &qp->ibqp; 2717 } 2718 2719 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2720 { 2721 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2722 2723 if (mqp->state == IB_QPS_RTR) { 2724 int err; 2725 2726 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2727 if (err) { 2728 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2729 return err; 2730 } 2731 } 2732 2733 kfree(mqp->dct.in); 2734 kfree(mqp); 2735 return 0; 2736 } 2737 2738 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2739 { 2740 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2741 struct mlx5_ib_qp *mqp = to_mqp(qp); 2742 2743 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2744 return mlx5_ib_gsi_destroy_qp(qp); 2745 2746 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2747 return mlx5_ib_destroy_dct(mqp); 2748 2749 destroy_qp_common(dev, mqp); 2750 2751 kfree(mqp); 2752 2753 return 0; 2754 } 2755 2756 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2757 const struct ib_qp_attr *attr, 2758 int attr_mask, __be32 *hw_access_flags_be) 2759 { 2760 u8 dest_rd_atomic; 2761 u32 access_flags, hw_access_flags = 0; 2762 2763 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2764 2765 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2766 dest_rd_atomic = attr->max_dest_rd_atomic; 2767 else 2768 dest_rd_atomic = qp->trans_qp.resp_depth; 2769 2770 if (attr_mask & IB_QP_ACCESS_FLAGS) 2771 access_flags = attr->qp_access_flags; 2772 else 2773 access_flags = qp->trans_qp.atomic_rd_en; 2774 2775 if (!dest_rd_atomic) 2776 access_flags &= IB_ACCESS_REMOTE_WRITE; 2777 2778 if (access_flags & IB_ACCESS_REMOTE_READ) 2779 hw_access_flags |= MLX5_QP_BIT_RRE; 2780 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2781 int atomic_mode; 2782 2783 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2784 if (atomic_mode < 0) 2785 return -EOPNOTSUPP; 2786 2787 hw_access_flags |= MLX5_QP_BIT_RAE; 2788 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; 2789 } 2790 2791 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2792 hw_access_flags |= MLX5_QP_BIT_RWE; 2793 2794 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2795 2796 return 0; 2797 } 2798 2799 enum { 2800 MLX5_PATH_FLAG_FL = 1 << 0, 2801 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2802 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2803 }; 2804 2805 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2806 { 2807 if (rate == IB_RATE_PORT_CURRENT) 2808 return 0; 2809 2810 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 2811 return -EINVAL; 2812 2813 while (rate != IB_RATE_PORT_CURRENT && 2814 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2815 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2816 --rate; 2817 2818 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2819 } 2820 2821 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2822 struct mlx5_ib_sq *sq, u8 sl, 2823 struct ib_pd *pd) 2824 { 2825 void *in; 2826 void *tisc; 2827 int inlen; 2828 int err; 2829 2830 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2831 in = kvzalloc(inlen, GFP_KERNEL); 2832 if (!in) 2833 return -ENOMEM; 2834 2835 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2836 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2837 2838 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2839 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2840 2841 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2842 2843 kvfree(in); 2844 2845 return err; 2846 } 2847 2848 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2849 struct mlx5_ib_sq *sq, u8 tx_affinity, 2850 struct ib_pd *pd) 2851 { 2852 void *in; 2853 void *tisc; 2854 int inlen; 2855 int err; 2856 2857 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2858 in = kvzalloc(inlen, GFP_KERNEL); 2859 if (!in) 2860 return -ENOMEM; 2861 2862 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2863 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2864 2865 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2866 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2867 2868 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2869 2870 kvfree(in); 2871 2872 return err; 2873 } 2874 2875 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2876 const struct rdma_ah_attr *ah, 2877 struct mlx5_qp_path *path, u8 port, int attr_mask, 2878 u32 path_flags, const struct ib_qp_attr *attr, 2879 bool alt) 2880 { 2881 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2882 int err; 2883 enum ib_gid_type gid_type; 2884 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2885 u8 sl = rdma_ah_get_sl(ah); 2886 2887 if (attr_mask & IB_QP_PKEY_INDEX) 2888 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2889 attr->pkey_index); 2890 2891 if (ah_flags & IB_AH_GRH) { 2892 if (grh->sgid_index >= 2893 dev->mdev->port_caps[port - 1].gid_table_len) { 2894 pr_err("sgid_index (%u) too large. max is %d\n", 2895 grh->sgid_index, 2896 dev->mdev->port_caps[port - 1].gid_table_len); 2897 return -EINVAL; 2898 } 2899 } 2900 2901 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2902 if (!(ah_flags & IB_AH_GRH)) 2903 return -EINVAL; 2904 2905 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2906 if (qp->ibqp.qp_type == IB_QPT_RC || 2907 qp->ibqp.qp_type == IB_QPT_UC || 2908 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2909 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2910 path->udp_sport = 2911 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); 2912 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2913 gid_type = ah->grh.sgid_attr->gid_type; 2914 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2915 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2916 } else { 2917 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2918 path->fl_free_ar |= 2919 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2920 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2921 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2922 if (ah_flags & IB_AH_GRH) 2923 path->grh_mlid |= 1 << 7; 2924 path->dci_cfi_prio_sl = sl & 0xf; 2925 } 2926 2927 if (ah_flags & IB_AH_GRH) { 2928 path->mgid_index = grh->sgid_index; 2929 path->hop_limit = grh->hop_limit; 2930 path->tclass_flowlabel = 2931 cpu_to_be32((grh->traffic_class << 20) | 2932 (grh->flow_label)); 2933 memcpy(path->rgid, grh->dgid.raw, 16); 2934 } 2935 2936 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2937 if (err < 0) 2938 return err; 2939 path->static_rate = err; 2940 path->port = port; 2941 2942 if (attr_mask & IB_QP_TIMEOUT) 2943 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2944 2945 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2946 return modify_raw_packet_eth_prio(dev->mdev, 2947 &qp->raw_packet_qp.sq, 2948 sl & 0xf, qp->ibqp.pd); 2949 2950 return 0; 2951 } 2952 2953 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2954 [MLX5_QP_STATE_INIT] = { 2955 [MLX5_QP_STATE_INIT] = { 2956 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2957 MLX5_QP_OPTPAR_RAE | 2958 MLX5_QP_OPTPAR_RWE | 2959 MLX5_QP_OPTPAR_PKEY_INDEX | 2960 MLX5_QP_OPTPAR_PRI_PORT, 2961 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2962 MLX5_QP_OPTPAR_PKEY_INDEX | 2963 MLX5_QP_OPTPAR_PRI_PORT, 2964 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2965 MLX5_QP_OPTPAR_Q_KEY | 2966 MLX5_QP_OPTPAR_PRI_PORT, 2967 }, 2968 [MLX5_QP_STATE_RTR] = { 2969 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2970 MLX5_QP_OPTPAR_RRE | 2971 MLX5_QP_OPTPAR_RAE | 2972 MLX5_QP_OPTPAR_RWE | 2973 MLX5_QP_OPTPAR_PKEY_INDEX, 2974 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2975 MLX5_QP_OPTPAR_RWE | 2976 MLX5_QP_OPTPAR_PKEY_INDEX, 2977 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2978 MLX5_QP_OPTPAR_Q_KEY, 2979 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2980 MLX5_QP_OPTPAR_Q_KEY, 2981 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2982 MLX5_QP_OPTPAR_RRE | 2983 MLX5_QP_OPTPAR_RAE | 2984 MLX5_QP_OPTPAR_RWE | 2985 MLX5_QP_OPTPAR_PKEY_INDEX, 2986 }, 2987 }, 2988 [MLX5_QP_STATE_RTR] = { 2989 [MLX5_QP_STATE_RTS] = { 2990 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2991 MLX5_QP_OPTPAR_RRE | 2992 MLX5_QP_OPTPAR_RAE | 2993 MLX5_QP_OPTPAR_RWE | 2994 MLX5_QP_OPTPAR_PM_STATE | 2995 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2996 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2997 MLX5_QP_OPTPAR_RWE | 2998 MLX5_QP_OPTPAR_PM_STATE, 2999 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3000 }, 3001 }, 3002 [MLX5_QP_STATE_RTS] = { 3003 [MLX5_QP_STATE_RTS] = { 3004 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3005 MLX5_QP_OPTPAR_RAE | 3006 MLX5_QP_OPTPAR_RWE | 3007 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3008 MLX5_QP_OPTPAR_PM_STATE | 3009 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3010 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3011 MLX5_QP_OPTPAR_PM_STATE | 3012 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3013 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3014 MLX5_QP_OPTPAR_SRQN | 3015 MLX5_QP_OPTPAR_CQN_RCV, 3016 }, 3017 }, 3018 [MLX5_QP_STATE_SQER] = { 3019 [MLX5_QP_STATE_RTS] = { 3020 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3021 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3022 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3023 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3024 MLX5_QP_OPTPAR_RWE | 3025 MLX5_QP_OPTPAR_RAE | 3026 MLX5_QP_OPTPAR_RRE, 3027 }, 3028 }, 3029 }; 3030 3031 static int ib_nr_to_mlx5_nr(int ib_mask) 3032 { 3033 switch (ib_mask) { 3034 case IB_QP_STATE: 3035 return 0; 3036 case IB_QP_CUR_STATE: 3037 return 0; 3038 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3039 return 0; 3040 case IB_QP_ACCESS_FLAGS: 3041 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3042 MLX5_QP_OPTPAR_RAE; 3043 case IB_QP_PKEY_INDEX: 3044 return MLX5_QP_OPTPAR_PKEY_INDEX; 3045 case IB_QP_PORT: 3046 return MLX5_QP_OPTPAR_PRI_PORT; 3047 case IB_QP_QKEY: 3048 return MLX5_QP_OPTPAR_Q_KEY; 3049 case IB_QP_AV: 3050 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3051 MLX5_QP_OPTPAR_PRI_PORT; 3052 case IB_QP_PATH_MTU: 3053 return 0; 3054 case IB_QP_TIMEOUT: 3055 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3056 case IB_QP_RETRY_CNT: 3057 return MLX5_QP_OPTPAR_RETRY_COUNT; 3058 case IB_QP_RNR_RETRY: 3059 return MLX5_QP_OPTPAR_RNR_RETRY; 3060 case IB_QP_RQ_PSN: 3061 return 0; 3062 case IB_QP_MAX_QP_RD_ATOMIC: 3063 return MLX5_QP_OPTPAR_SRA_MAX; 3064 case IB_QP_ALT_PATH: 3065 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3066 case IB_QP_MIN_RNR_TIMER: 3067 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3068 case IB_QP_SQ_PSN: 3069 return 0; 3070 case IB_QP_MAX_DEST_RD_ATOMIC: 3071 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3072 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3073 case IB_QP_PATH_MIG_STATE: 3074 return MLX5_QP_OPTPAR_PM_STATE; 3075 case IB_QP_CAP: 3076 return 0; 3077 case IB_QP_DEST_QPN: 3078 return 0; 3079 } 3080 return 0; 3081 } 3082 3083 static int ib_mask_to_mlx5_opt(int ib_mask) 3084 { 3085 int result = 0; 3086 int i; 3087 3088 for (i = 0; i < 8 * sizeof(int); i++) { 3089 if ((1 << i) & ib_mask) 3090 result |= ib_nr_to_mlx5_nr(1 << i); 3091 } 3092 3093 return result; 3094 } 3095 3096 static int modify_raw_packet_qp_rq( 3097 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3098 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3099 { 3100 void *in; 3101 void *rqc; 3102 int inlen; 3103 int err; 3104 3105 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3106 in = kvzalloc(inlen, GFP_KERNEL); 3107 if (!in) 3108 return -ENOMEM; 3109 3110 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3111 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3112 3113 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3114 MLX5_SET(rqc, rqc, state, new_state); 3115 3116 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3117 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3118 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3119 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3120 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3121 } else 3122 dev_info_once( 3123 &dev->ib_dev.dev, 3124 "RAW PACKET QP counters are not supported on current FW\n"); 3125 } 3126 3127 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 3128 if (err) 3129 goto out; 3130 3131 rq->state = new_state; 3132 3133 out: 3134 kvfree(in); 3135 return err; 3136 } 3137 3138 static int modify_raw_packet_qp_sq( 3139 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3140 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3141 { 3142 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3143 struct mlx5_rate_limit old_rl = ibqp->rl; 3144 struct mlx5_rate_limit new_rl = old_rl; 3145 bool new_rate_added = false; 3146 u16 rl_index = 0; 3147 void *in; 3148 void *sqc; 3149 int inlen; 3150 int err; 3151 3152 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3153 in = kvzalloc(inlen, GFP_KERNEL); 3154 if (!in) 3155 return -ENOMEM; 3156 3157 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3158 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3159 3160 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3161 MLX5_SET(sqc, sqc, state, new_state); 3162 3163 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3164 if (new_state != MLX5_SQC_STATE_RDY) 3165 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3166 __func__); 3167 else 3168 new_rl = raw_qp_param->rl; 3169 } 3170 3171 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3172 if (new_rl.rate) { 3173 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3174 if (err) { 3175 pr_err("Failed configuring rate limit(err %d): \ 3176 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3177 err, new_rl.rate, new_rl.max_burst_sz, 3178 new_rl.typical_pkt_sz); 3179 3180 goto out; 3181 } 3182 new_rate_added = true; 3183 } 3184 3185 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3186 /* index 0 means no limit */ 3187 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3188 } 3189 3190 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 3191 if (err) { 3192 /* Remove new rate from table if failed */ 3193 if (new_rate_added) 3194 mlx5_rl_remove_rate(dev, &new_rl); 3195 goto out; 3196 } 3197 3198 /* Only remove the old rate after new rate was set */ 3199 if ((old_rl.rate && 3200 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3201 (new_state != MLX5_SQC_STATE_RDY)) 3202 mlx5_rl_remove_rate(dev, &old_rl); 3203 3204 ibqp->rl = new_rl; 3205 sq->state = new_state; 3206 3207 out: 3208 kvfree(in); 3209 return err; 3210 } 3211 3212 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3213 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3214 u8 tx_affinity) 3215 { 3216 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3217 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3218 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3219 int modify_rq = !!qp->rq.wqe_cnt; 3220 int modify_sq = !!qp->sq.wqe_cnt; 3221 int rq_state; 3222 int sq_state; 3223 int err; 3224 3225 switch (raw_qp_param->operation) { 3226 case MLX5_CMD_OP_RST2INIT_QP: 3227 rq_state = MLX5_RQC_STATE_RDY; 3228 sq_state = MLX5_SQC_STATE_RDY; 3229 break; 3230 case MLX5_CMD_OP_2ERR_QP: 3231 rq_state = MLX5_RQC_STATE_ERR; 3232 sq_state = MLX5_SQC_STATE_ERR; 3233 break; 3234 case MLX5_CMD_OP_2RST_QP: 3235 rq_state = MLX5_RQC_STATE_RST; 3236 sq_state = MLX5_SQC_STATE_RST; 3237 break; 3238 case MLX5_CMD_OP_RTR2RTS_QP: 3239 case MLX5_CMD_OP_RTS2RTS_QP: 3240 if (raw_qp_param->set_mask == 3241 MLX5_RAW_QP_RATE_LIMIT) { 3242 modify_rq = 0; 3243 sq_state = sq->state; 3244 } else { 3245 return raw_qp_param->set_mask ? -EINVAL : 0; 3246 } 3247 break; 3248 case MLX5_CMD_OP_INIT2INIT_QP: 3249 case MLX5_CMD_OP_INIT2RTR_QP: 3250 if (raw_qp_param->set_mask) 3251 return -EINVAL; 3252 else 3253 return 0; 3254 default: 3255 WARN_ON(1); 3256 return -EINVAL; 3257 } 3258 3259 if (modify_rq) { 3260 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3261 qp->ibqp.pd); 3262 if (err) 3263 return err; 3264 } 3265 3266 if (modify_sq) { 3267 if (tx_affinity) { 3268 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3269 tx_affinity, 3270 qp->ibqp.pd); 3271 if (err) 3272 return err; 3273 } 3274 3275 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3276 raw_qp_param, qp->ibqp.pd); 3277 } 3278 3279 return 0; 3280 } 3281 3282 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, 3283 struct mlx5_ib_pd *pd, 3284 struct mlx5_ib_qp_base *qp_base, 3285 u8 port_num, struct ib_udata *udata) 3286 { 3287 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3288 udata, struct mlx5_ib_ucontext, ibucontext); 3289 unsigned int tx_port_affinity; 3290 3291 if (ucontext) { 3292 tx_port_affinity = (unsigned int)atomic_add_return( 3293 1, &ucontext->tx_port_affinity) % 3294 MLX5_MAX_PORTS + 3295 1; 3296 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3297 tx_port_affinity, qp_base->mqp.qpn, ucontext); 3298 } else { 3299 tx_port_affinity = 3300 (unsigned int)atomic_add_return( 3301 1, &dev->roce[port_num].tx_port_affinity) % 3302 MLX5_MAX_PORTS + 3303 1; 3304 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3305 tx_port_affinity, qp_base->mqp.qpn); 3306 } 3307 3308 return tx_port_affinity; 3309 } 3310 3311 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3312 const struct ib_qp_attr *attr, int attr_mask, 3313 enum ib_qp_state cur_state, 3314 enum ib_qp_state new_state, 3315 const struct mlx5_ib_modify_qp *ucmd, 3316 struct ib_udata *udata) 3317 { 3318 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3319 [MLX5_QP_STATE_RST] = { 3320 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3321 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3322 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3323 }, 3324 [MLX5_QP_STATE_INIT] = { 3325 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3326 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3327 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3328 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3329 }, 3330 [MLX5_QP_STATE_RTR] = { 3331 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3332 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3333 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3334 }, 3335 [MLX5_QP_STATE_RTS] = { 3336 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3337 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3338 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3339 }, 3340 [MLX5_QP_STATE_SQD] = { 3341 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3342 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3343 }, 3344 [MLX5_QP_STATE_SQER] = { 3345 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3346 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3347 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3348 }, 3349 [MLX5_QP_STATE_ERR] = { 3350 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3351 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3352 } 3353 }; 3354 3355 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3356 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3357 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3358 struct mlx5_ib_cq *send_cq, *recv_cq; 3359 struct mlx5_qp_context *context; 3360 struct mlx5_ib_pd *pd; 3361 struct mlx5_ib_port *mibport = NULL; 3362 enum mlx5_qp_state mlx5_cur, mlx5_new; 3363 enum mlx5_qp_optpar optpar; 3364 int mlx5_st; 3365 int err; 3366 u16 op; 3367 u8 tx_affinity = 0; 3368 3369 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3370 qp->qp_sub_type : ibqp->qp_type); 3371 if (mlx5_st < 0) 3372 return -EINVAL; 3373 3374 context = kzalloc(sizeof(*context), GFP_KERNEL); 3375 if (!context) 3376 return -ENOMEM; 3377 3378 pd = get_pd(qp); 3379 context->flags = cpu_to_be32(mlx5_st << 16); 3380 3381 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3382 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3383 } else { 3384 switch (attr->path_mig_state) { 3385 case IB_MIG_MIGRATED: 3386 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3387 break; 3388 case IB_MIG_REARM: 3389 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3390 break; 3391 case IB_MIG_ARMED: 3392 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3393 break; 3394 } 3395 } 3396 3397 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3398 if ((ibqp->qp_type == IB_QPT_RC) || 3399 (ibqp->qp_type == IB_QPT_UD && 3400 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3401 (ibqp->qp_type == IB_QPT_UC) || 3402 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3403 (ibqp->qp_type == IB_QPT_XRC_INI) || 3404 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3405 if (dev->lag_active) { 3406 u8 p = mlx5_core_native_port_num(dev->mdev); 3407 tx_affinity = get_tx_affinity(dev, pd, base, p, 3408 udata); 3409 context->flags |= cpu_to_be32(tx_affinity << 24); 3410 } 3411 } 3412 } 3413 3414 if (is_sqp(ibqp->qp_type)) { 3415 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3416 } else if ((ibqp->qp_type == IB_QPT_UD && 3417 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3418 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3419 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3420 } else if (attr_mask & IB_QP_PATH_MTU) { 3421 if (attr->path_mtu < IB_MTU_256 || 3422 attr->path_mtu > IB_MTU_4096) { 3423 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3424 err = -EINVAL; 3425 goto out; 3426 } 3427 context->mtu_msgmax = (attr->path_mtu << 5) | 3428 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3429 } 3430 3431 if (attr_mask & IB_QP_DEST_QPN) 3432 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3433 3434 if (attr_mask & IB_QP_PKEY_INDEX) 3435 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3436 3437 /* todo implement counter_index functionality */ 3438 3439 if (is_sqp(ibqp->qp_type)) 3440 context->pri_path.port = qp->port; 3441 3442 if (attr_mask & IB_QP_PORT) 3443 context->pri_path.port = attr->port_num; 3444 3445 if (attr_mask & IB_QP_AV) { 3446 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3447 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3448 attr_mask, 0, attr, false); 3449 if (err) 3450 goto out; 3451 } 3452 3453 if (attr_mask & IB_QP_TIMEOUT) 3454 context->pri_path.ackto_lt |= attr->timeout << 3; 3455 3456 if (attr_mask & IB_QP_ALT_PATH) { 3457 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3458 &context->alt_path, 3459 attr->alt_port_num, 3460 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3461 0, attr, true); 3462 if (err) 3463 goto out; 3464 } 3465 3466 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3467 &send_cq, &recv_cq); 3468 3469 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3470 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3471 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3472 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3473 3474 if (attr_mask & IB_QP_RNR_RETRY) 3475 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3476 3477 if (attr_mask & IB_QP_RETRY_CNT) 3478 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3479 3480 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3481 if (attr->max_rd_atomic) 3482 context->params1 |= 3483 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3484 } 3485 3486 if (attr_mask & IB_QP_SQ_PSN) 3487 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3488 3489 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3490 if (attr->max_dest_rd_atomic) 3491 context->params2 |= 3492 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3493 } 3494 3495 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3496 __be32 access_flags; 3497 3498 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 3499 if (err) 3500 goto out; 3501 3502 context->params2 |= access_flags; 3503 } 3504 3505 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3506 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3507 3508 if (attr_mask & IB_QP_RQ_PSN) 3509 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3510 3511 if (attr_mask & IB_QP_QKEY) 3512 context->qkey = cpu_to_be32(attr->qkey); 3513 3514 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3515 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3516 3517 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3518 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3519 qp->port) - 1; 3520 3521 /* Underlay port should be used - index 0 function per port */ 3522 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3523 port_num = 0; 3524 3525 mibport = &dev->port[port_num]; 3526 context->qp_counter_set_usr_page |= 3527 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3528 } 3529 3530 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3531 context->sq_crq_size |= cpu_to_be16(1 << 4); 3532 3533 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3534 context->deth_sqpn = cpu_to_be32(1); 3535 3536 mlx5_cur = to_mlx5_state(cur_state); 3537 mlx5_new = to_mlx5_state(new_state); 3538 3539 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3540 !optab[mlx5_cur][mlx5_new]) { 3541 err = -EINVAL; 3542 goto out; 3543 } 3544 3545 op = optab[mlx5_cur][mlx5_new]; 3546 optpar = ib_mask_to_mlx5_opt(attr_mask); 3547 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3548 3549 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3550 qp->flags & MLX5_IB_QP_UNDERLAY) { 3551 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3552 3553 raw_qp_param.operation = op; 3554 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3555 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3556 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3557 } 3558 3559 if (attr_mask & IB_QP_RATE_LIMIT) { 3560 raw_qp_param.rl.rate = attr->rate_limit; 3561 3562 if (ucmd->burst_info.max_burst_sz) { 3563 if (attr->rate_limit && 3564 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3565 raw_qp_param.rl.max_burst_sz = 3566 ucmd->burst_info.max_burst_sz; 3567 } else { 3568 err = -EINVAL; 3569 goto out; 3570 } 3571 } 3572 3573 if (ucmd->burst_info.typical_pkt_sz) { 3574 if (attr->rate_limit && 3575 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3576 raw_qp_param.rl.typical_pkt_sz = 3577 ucmd->burst_info.typical_pkt_sz; 3578 } else { 3579 err = -EINVAL; 3580 goto out; 3581 } 3582 } 3583 3584 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3585 } 3586 3587 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3588 } else { 3589 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3590 &base->mqp); 3591 } 3592 3593 if (err) 3594 goto out; 3595 3596 qp->state = new_state; 3597 3598 if (attr_mask & IB_QP_ACCESS_FLAGS) 3599 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3600 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3601 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3602 if (attr_mask & IB_QP_PORT) 3603 qp->port = attr->port_num; 3604 if (attr_mask & IB_QP_ALT_PATH) 3605 qp->trans_qp.alt_port = attr->alt_port_num; 3606 3607 /* 3608 * If we moved a kernel QP to RESET, clean up all old CQ 3609 * entries and reinitialize the QP. 3610 */ 3611 if (new_state == IB_QPS_RESET && 3612 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3613 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3614 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3615 if (send_cq != recv_cq) 3616 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3617 3618 qp->rq.head = 0; 3619 qp->rq.tail = 0; 3620 qp->sq.head = 0; 3621 qp->sq.tail = 0; 3622 qp->sq.cur_post = 0; 3623 if (qp->sq.wqe_cnt) 3624 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 3625 qp->db.db[MLX5_RCV_DBR] = 0; 3626 qp->db.db[MLX5_SND_DBR] = 0; 3627 } 3628 3629 out: 3630 kfree(context); 3631 return err; 3632 } 3633 3634 static inline bool is_valid_mask(int mask, int req, int opt) 3635 { 3636 if ((mask & req) != req) 3637 return false; 3638 3639 if (mask & ~(req | opt)) 3640 return false; 3641 3642 return true; 3643 } 3644 3645 /* check valid transition for driver QP types 3646 * for now the only QP type that this function supports is DCI 3647 */ 3648 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3649 enum ib_qp_attr_mask attr_mask) 3650 { 3651 int req = IB_QP_STATE; 3652 int opt = 0; 3653 3654 if (new_state == IB_QPS_RESET) { 3655 return is_valid_mask(attr_mask, req, opt); 3656 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3657 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3658 return is_valid_mask(attr_mask, req, opt); 3659 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3660 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3661 return is_valid_mask(attr_mask, req, opt); 3662 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3663 req |= IB_QP_PATH_MTU; 3664 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 3665 return is_valid_mask(attr_mask, req, opt); 3666 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3667 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3668 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3669 opt = IB_QP_MIN_RNR_TIMER; 3670 return is_valid_mask(attr_mask, req, opt); 3671 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3672 opt = IB_QP_MIN_RNR_TIMER; 3673 return is_valid_mask(attr_mask, req, opt); 3674 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3675 return is_valid_mask(attr_mask, req, opt); 3676 } 3677 return false; 3678 } 3679 3680 /* mlx5_ib_modify_dct: modify a DCT QP 3681 * valid transitions are: 3682 * RESET to INIT: must set access_flags, pkey_index and port 3683 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3684 * mtu, gid_index and hop_limit 3685 * Other transitions and attributes are illegal 3686 */ 3687 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3688 int attr_mask, struct ib_udata *udata) 3689 { 3690 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3691 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3692 enum ib_qp_state cur_state, new_state; 3693 int err = 0; 3694 int required = IB_QP_STATE; 3695 void *dctc; 3696 3697 if (!(attr_mask & IB_QP_STATE)) 3698 return -EINVAL; 3699 3700 cur_state = qp->state; 3701 new_state = attr->qp_state; 3702 3703 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3704 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3705 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3706 if (!is_valid_mask(attr_mask, required, 0)) 3707 return -EINVAL; 3708 3709 if (attr->port_num == 0 || 3710 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3711 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3712 attr->port_num, dev->num_ports); 3713 return -EINVAL; 3714 } 3715 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3716 MLX5_SET(dctc, dctc, rre, 1); 3717 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3718 MLX5_SET(dctc, dctc, rwe, 1); 3719 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3720 int atomic_mode; 3721 3722 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 3723 if (atomic_mode < 0) 3724 return -EOPNOTSUPP; 3725 3726 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 3727 MLX5_SET(dctc, dctc, rae, 1); 3728 } 3729 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3730 MLX5_SET(dctc, dctc, port, attr->port_num); 3731 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3732 3733 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3734 struct mlx5_ib_modify_qp_resp resp = {}; 3735 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0}; 3736 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3737 sizeof(resp.dctn); 3738 3739 if (udata->outlen < min_resp_len) 3740 return -EINVAL; 3741 resp.response_length = min_resp_len; 3742 3743 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3744 if (!is_valid_mask(attr_mask, required, 0)) 3745 return -EINVAL; 3746 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3747 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3748 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3749 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3750 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3751 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3752 3753 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3754 MLX5_ST_SZ_BYTES(create_dct_in), out, 3755 sizeof(out)); 3756 if (err) 3757 return err; 3758 resp.dctn = qp->dct.mdct.mqp.qpn; 3759 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3760 if (err) { 3761 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3762 return err; 3763 } 3764 } else { 3765 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3766 return -EINVAL; 3767 } 3768 if (err) 3769 qp->state = IB_QPS_ERR; 3770 else 3771 qp->state = new_state; 3772 return err; 3773 } 3774 3775 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3776 int attr_mask, struct ib_udata *udata) 3777 { 3778 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3779 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3780 struct mlx5_ib_modify_qp ucmd = {}; 3781 enum ib_qp_type qp_type; 3782 enum ib_qp_state cur_state, new_state; 3783 size_t required_cmd_sz; 3784 int err = -EINVAL; 3785 int port; 3786 3787 if (ibqp->rwq_ind_tbl) 3788 return -ENOSYS; 3789 3790 if (udata && udata->inlen) { 3791 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3792 sizeof(ucmd.reserved); 3793 if (udata->inlen < required_cmd_sz) 3794 return -EINVAL; 3795 3796 if (udata->inlen > sizeof(ucmd) && 3797 !ib_is_udata_cleared(udata, sizeof(ucmd), 3798 udata->inlen - sizeof(ucmd))) 3799 return -EOPNOTSUPP; 3800 3801 if (ib_copy_from_udata(&ucmd, udata, 3802 min(udata->inlen, sizeof(ucmd)))) 3803 return -EFAULT; 3804 3805 if (ucmd.comp_mask || 3806 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3807 memchr_inv(&ucmd.burst_info.reserved, 0, 3808 sizeof(ucmd.burst_info.reserved))) 3809 return -EOPNOTSUPP; 3810 } 3811 3812 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3813 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3814 3815 if (ibqp->qp_type == IB_QPT_DRIVER) 3816 qp_type = qp->qp_sub_type; 3817 else 3818 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3819 IB_QPT_GSI : ibqp->qp_type; 3820 3821 if (qp_type == MLX5_IB_QPT_DCT) 3822 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3823 3824 mutex_lock(&qp->mutex); 3825 3826 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3827 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3828 3829 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3830 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3831 } 3832 3833 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3834 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3835 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3836 attr_mask); 3837 goto out; 3838 } 3839 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3840 qp_type != MLX5_IB_QPT_DCI && 3841 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 3842 attr_mask)) { 3843 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3844 cur_state, new_state, ibqp->qp_type, attr_mask); 3845 goto out; 3846 } else if (qp_type == MLX5_IB_QPT_DCI && 3847 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3848 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3849 cur_state, new_state, qp_type, attr_mask); 3850 goto out; 3851 } 3852 3853 if ((attr_mask & IB_QP_PORT) && 3854 (attr->port_num == 0 || 3855 attr->port_num > dev->num_ports)) { 3856 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3857 attr->port_num, dev->num_ports); 3858 goto out; 3859 } 3860 3861 if (attr_mask & IB_QP_PKEY_INDEX) { 3862 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3863 if (attr->pkey_index >= 3864 dev->mdev->port_caps[port - 1].pkey_table_len) { 3865 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3866 attr->pkey_index); 3867 goto out; 3868 } 3869 } 3870 3871 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3872 attr->max_rd_atomic > 3873 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3874 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3875 attr->max_rd_atomic); 3876 goto out; 3877 } 3878 3879 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3880 attr->max_dest_rd_atomic > 3881 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3882 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3883 attr->max_dest_rd_atomic); 3884 goto out; 3885 } 3886 3887 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3888 err = 0; 3889 goto out; 3890 } 3891 3892 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3893 new_state, &ucmd, udata); 3894 3895 out: 3896 mutex_unlock(&qp->mutex); 3897 return err; 3898 } 3899 3900 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3901 u32 wqe_sz, void **cur_edge) 3902 { 3903 u32 idx; 3904 3905 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); 3906 *cur_edge = get_sq_edge(sq, idx); 3907 3908 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); 3909 } 3910 3911 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the 3912 * next nearby edge and get new address translation for current WQE position. 3913 * @sq - SQ buffer. 3914 * @seg: Current WQE position (16B aligned). 3915 * @wqe_sz: Total current WQE size [16B]. 3916 * @cur_edge: Updated current edge. 3917 */ 3918 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3919 u32 wqe_sz, void **cur_edge) 3920 { 3921 if (likely(*seg != *cur_edge)) 3922 return; 3923 3924 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); 3925 } 3926 3927 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's 3928 * pointers. At the end @seg is aligned to 16B regardless the copied size. 3929 * @sq - SQ buffer. 3930 * @cur_edge: Updated current edge. 3931 * @seg: Current WQE position (16B aligned). 3932 * @wqe_sz: Total current WQE size [16B]. 3933 * @src: Pointer to copy from. 3934 * @n: Number of bytes to copy. 3935 */ 3936 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, 3937 void **seg, u32 *wqe_sz, const void *src, 3938 size_t n) 3939 { 3940 while (likely(n)) { 3941 size_t leftlen = *cur_edge - *seg; 3942 size_t copysz = min_t(size_t, leftlen, n); 3943 size_t stride; 3944 3945 memcpy(*seg, src, copysz); 3946 3947 n -= copysz; 3948 src += copysz; 3949 stride = !n ? ALIGN(copysz, 16) : copysz; 3950 *seg += stride; 3951 *wqe_sz += stride >> 4; 3952 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); 3953 } 3954 } 3955 3956 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3957 { 3958 struct mlx5_ib_cq *cq; 3959 unsigned cur; 3960 3961 cur = wq->head - wq->tail; 3962 if (likely(cur + nreq < wq->max_post)) 3963 return 0; 3964 3965 cq = to_mcq(ib_cq); 3966 spin_lock(&cq->lock); 3967 cur = wq->head - wq->tail; 3968 spin_unlock(&cq->lock); 3969 3970 return cur + nreq >= wq->max_post; 3971 } 3972 3973 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3974 u64 remote_addr, u32 rkey) 3975 { 3976 rseg->raddr = cpu_to_be64(remote_addr); 3977 rseg->rkey = cpu_to_be32(rkey); 3978 rseg->reserved = 0; 3979 } 3980 3981 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 3982 void **seg, int *size, void **cur_edge) 3983 { 3984 struct mlx5_wqe_eth_seg *eseg = *seg; 3985 3986 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3987 3988 if (wr->send_flags & IB_SEND_IP_CSUM) 3989 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3990 MLX5_ETH_WQE_L4_CSUM; 3991 3992 if (wr->opcode == IB_WR_LSO) { 3993 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3994 size_t left, copysz; 3995 void *pdata = ud_wr->header; 3996 size_t stride; 3997 3998 left = ud_wr->hlen; 3999 eseg->mss = cpu_to_be16(ud_wr->mss); 4000 eseg->inline_hdr.sz = cpu_to_be16(left); 4001 4002 /* memcpy_send_wqe should get a 16B align address. Hence, we 4003 * first copy up to the current edge and then, if needed, 4004 * fall-through to memcpy_send_wqe. 4005 */ 4006 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, 4007 left); 4008 memcpy(eseg->inline_hdr.start, pdata, copysz); 4009 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - 4010 sizeof(eseg->inline_hdr.start) + copysz, 16); 4011 *size += stride / 16; 4012 *seg += stride; 4013 4014 if (copysz < left) { 4015 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4016 left -= copysz; 4017 pdata += copysz; 4018 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, 4019 left); 4020 } 4021 4022 return; 4023 } 4024 4025 *seg += sizeof(struct mlx5_wqe_eth_seg); 4026 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 4027 } 4028 4029 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 4030 const struct ib_send_wr *wr) 4031 { 4032 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 4033 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 4034 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 4035 } 4036 4037 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 4038 { 4039 dseg->byte_count = cpu_to_be32(sg->length); 4040 dseg->lkey = cpu_to_be32(sg->lkey); 4041 dseg->addr = cpu_to_be64(sg->addr); 4042 } 4043 4044 static u64 get_xlt_octo(u64 bytes) 4045 { 4046 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 4047 MLX5_IB_UMR_OCTOWORD; 4048 } 4049 4050 static __be64 frwr_mkey_mask(void) 4051 { 4052 u64 result; 4053 4054 result = MLX5_MKEY_MASK_LEN | 4055 MLX5_MKEY_MASK_PAGE_SIZE | 4056 MLX5_MKEY_MASK_START_ADDR | 4057 MLX5_MKEY_MASK_EN_RINVAL | 4058 MLX5_MKEY_MASK_KEY | 4059 MLX5_MKEY_MASK_LR | 4060 MLX5_MKEY_MASK_LW | 4061 MLX5_MKEY_MASK_RR | 4062 MLX5_MKEY_MASK_RW | 4063 MLX5_MKEY_MASK_A | 4064 MLX5_MKEY_MASK_SMALL_FENCE | 4065 MLX5_MKEY_MASK_FREE; 4066 4067 return cpu_to_be64(result); 4068 } 4069 4070 static __be64 sig_mkey_mask(void) 4071 { 4072 u64 result; 4073 4074 result = MLX5_MKEY_MASK_LEN | 4075 MLX5_MKEY_MASK_PAGE_SIZE | 4076 MLX5_MKEY_MASK_START_ADDR | 4077 MLX5_MKEY_MASK_EN_SIGERR | 4078 MLX5_MKEY_MASK_EN_RINVAL | 4079 MLX5_MKEY_MASK_KEY | 4080 MLX5_MKEY_MASK_LR | 4081 MLX5_MKEY_MASK_LW | 4082 MLX5_MKEY_MASK_RR | 4083 MLX5_MKEY_MASK_RW | 4084 MLX5_MKEY_MASK_SMALL_FENCE | 4085 MLX5_MKEY_MASK_FREE | 4086 MLX5_MKEY_MASK_BSF_EN; 4087 4088 return cpu_to_be64(result); 4089 } 4090 4091 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 4092 struct mlx5_ib_mr *mr, bool umr_inline) 4093 { 4094 int size = mr->ndescs * mr->desc_size; 4095 4096 memset(umr, 0, sizeof(*umr)); 4097 4098 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 4099 if (umr_inline) 4100 umr->flags |= MLX5_UMR_INLINE; 4101 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4102 umr->mkey_mask = frwr_mkey_mask(); 4103 } 4104 4105 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 4106 { 4107 memset(umr, 0, sizeof(*umr)); 4108 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 4109 umr->flags = MLX5_UMR_INLINE; 4110 } 4111 4112 static __be64 get_umr_enable_mr_mask(void) 4113 { 4114 u64 result; 4115 4116 result = MLX5_MKEY_MASK_KEY | 4117 MLX5_MKEY_MASK_FREE; 4118 4119 return cpu_to_be64(result); 4120 } 4121 4122 static __be64 get_umr_disable_mr_mask(void) 4123 { 4124 u64 result; 4125 4126 result = MLX5_MKEY_MASK_FREE; 4127 4128 return cpu_to_be64(result); 4129 } 4130 4131 static __be64 get_umr_update_translation_mask(void) 4132 { 4133 u64 result; 4134 4135 result = MLX5_MKEY_MASK_LEN | 4136 MLX5_MKEY_MASK_PAGE_SIZE | 4137 MLX5_MKEY_MASK_START_ADDR; 4138 4139 return cpu_to_be64(result); 4140 } 4141 4142 static __be64 get_umr_update_access_mask(int atomic) 4143 { 4144 u64 result; 4145 4146 result = MLX5_MKEY_MASK_LR | 4147 MLX5_MKEY_MASK_LW | 4148 MLX5_MKEY_MASK_RR | 4149 MLX5_MKEY_MASK_RW; 4150 4151 if (atomic) 4152 result |= MLX5_MKEY_MASK_A; 4153 4154 return cpu_to_be64(result); 4155 } 4156 4157 static __be64 get_umr_update_pd_mask(void) 4158 { 4159 u64 result; 4160 4161 result = MLX5_MKEY_MASK_PD; 4162 4163 return cpu_to_be64(result); 4164 } 4165 4166 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 4167 { 4168 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 4169 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 4170 (mask & MLX5_MKEY_MASK_A && 4171 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 4172 return -EPERM; 4173 return 0; 4174 } 4175 4176 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 4177 struct mlx5_wqe_umr_ctrl_seg *umr, 4178 const struct ib_send_wr *wr, int atomic) 4179 { 4180 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4181 4182 memset(umr, 0, sizeof(*umr)); 4183 4184 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 4185 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 4186 else 4187 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 4188 4189 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 4190 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 4191 u64 offset = get_xlt_octo(umrwr->offset); 4192 4193 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 4194 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 4195 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 4196 } 4197 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 4198 umr->mkey_mask |= get_umr_update_translation_mask(); 4199 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 4200 umr->mkey_mask |= get_umr_update_access_mask(atomic); 4201 umr->mkey_mask |= get_umr_update_pd_mask(); 4202 } 4203 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 4204 umr->mkey_mask |= get_umr_enable_mr_mask(); 4205 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4206 umr->mkey_mask |= get_umr_disable_mr_mask(); 4207 4208 if (!wr->num_sge) 4209 umr->flags |= MLX5_UMR_INLINE; 4210 4211 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 4212 } 4213 4214 static u8 get_umr_flags(int acc) 4215 { 4216 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 4217 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 4218 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 4219 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 4220 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 4221 } 4222 4223 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 4224 struct mlx5_ib_mr *mr, 4225 u32 key, int access) 4226 { 4227 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 4228 4229 memset(seg, 0, sizeof(*seg)); 4230 4231 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 4232 seg->log2_page_size = ilog2(mr->ibmr.page_size); 4233 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 4234 /* KLMs take twice the size of MTTs */ 4235 ndescs *= 2; 4236 4237 seg->flags = get_umr_flags(access) | mr->access_mode; 4238 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 4239 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 4240 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 4241 seg->len = cpu_to_be64(mr->ibmr.length); 4242 seg->xlt_oct_size = cpu_to_be32(ndescs); 4243 } 4244 4245 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 4246 { 4247 memset(seg, 0, sizeof(*seg)); 4248 seg->status = MLX5_MKEY_STATUS_FREE; 4249 } 4250 4251 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, 4252 const struct ib_send_wr *wr) 4253 { 4254 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4255 4256 memset(seg, 0, sizeof(*seg)); 4257 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4258 seg->status = MLX5_MKEY_STATUS_FREE; 4259 4260 seg->flags = convert_access(umrwr->access_flags); 4261 if (umrwr->pd) 4262 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 4263 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 4264 !umrwr->length) 4265 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 4266 4267 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 4268 seg->len = cpu_to_be64(umrwr->length); 4269 seg->log2_page_size = umrwr->page_shift; 4270 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 4271 mlx5_mkey_variant(umrwr->mkey)); 4272 } 4273 4274 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 4275 struct mlx5_ib_mr *mr, 4276 struct mlx5_ib_pd *pd) 4277 { 4278 int bcount = mr->desc_size * mr->ndescs; 4279 4280 dseg->addr = cpu_to_be64(mr->desc_map); 4281 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 4282 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 4283 } 4284 4285 static __be32 send_ieth(const struct ib_send_wr *wr) 4286 { 4287 switch (wr->opcode) { 4288 case IB_WR_SEND_WITH_IMM: 4289 case IB_WR_RDMA_WRITE_WITH_IMM: 4290 return wr->ex.imm_data; 4291 4292 case IB_WR_SEND_WITH_INV: 4293 return cpu_to_be32(wr->ex.invalidate_rkey); 4294 4295 default: 4296 return 0; 4297 } 4298 } 4299 4300 static u8 calc_sig(void *wqe, int size) 4301 { 4302 u8 *p = wqe; 4303 u8 res = 0; 4304 int i; 4305 4306 for (i = 0; i < size; i++) 4307 res ^= p[i]; 4308 4309 return ~res; 4310 } 4311 4312 static u8 wq_sig(void *wqe) 4313 { 4314 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 4315 } 4316 4317 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 4318 void **wqe, int *wqe_sz, void **cur_edge) 4319 { 4320 struct mlx5_wqe_inline_seg *seg; 4321 size_t offset; 4322 int inl = 0; 4323 int i; 4324 4325 seg = *wqe; 4326 *wqe += sizeof(*seg); 4327 offset = sizeof(*seg); 4328 4329 for (i = 0; i < wr->num_sge; i++) { 4330 size_t len = wr->sg_list[i].length; 4331 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); 4332 4333 inl += len; 4334 4335 if (unlikely(inl > qp->max_inline_data)) 4336 return -ENOMEM; 4337 4338 while (likely(len)) { 4339 size_t leftlen; 4340 size_t copysz; 4341 4342 handle_post_send_edge(&qp->sq, wqe, 4343 *wqe_sz + (offset >> 4), 4344 cur_edge); 4345 4346 leftlen = *cur_edge - *wqe; 4347 copysz = min_t(size_t, leftlen, len); 4348 4349 memcpy(*wqe, addr, copysz); 4350 len -= copysz; 4351 addr += copysz; 4352 *wqe += copysz; 4353 offset += copysz; 4354 } 4355 } 4356 4357 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 4358 4359 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 4360 4361 return 0; 4362 } 4363 4364 static u16 prot_field_size(enum ib_signature_type type) 4365 { 4366 switch (type) { 4367 case IB_SIG_TYPE_T10_DIF: 4368 return MLX5_DIF_SIZE; 4369 default: 4370 return 0; 4371 } 4372 } 4373 4374 static u8 bs_selector(int block_size) 4375 { 4376 switch (block_size) { 4377 case 512: return 0x1; 4378 case 520: return 0x2; 4379 case 4096: return 0x3; 4380 case 4160: return 0x4; 4381 case 1073741824: return 0x5; 4382 default: return 0; 4383 } 4384 } 4385 4386 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 4387 struct mlx5_bsf_inl *inl) 4388 { 4389 /* Valid inline section and allow BSF refresh */ 4390 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 4391 MLX5_BSF_REFRESH_DIF); 4392 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 4393 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 4394 /* repeating block */ 4395 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 4396 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 4397 MLX5_DIF_CRC : MLX5_DIF_IPCS; 4398 4399 if (domain->sig.dif.ref_remap) 4400 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 4401 4402 if (domain->sig.dif.app_escape) { 4403 if (domain->sig.dif.ref_escape) 4404 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 4405 else 4406 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 4407 } 4408 4409 inl->dif_app_bitmask_check = 4410 cpu_to_be16(domain->sig.dif.apptag_check_mask); 4411 } 4412 4413 static int mlx5_set_bsf(struct ib_mr *sig_mr, 4414 struct ib_sig_attrs *sig_attrs, 4415 struct mlx5_bsf *bsf, u32 data_size) 4416 { 4417 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 4418 struct mlx5_bsf_basic *basic = &bsf->basic; 4419 struct ib_sig_domain *mem = &sig_attrs->mem; 4420 struct ib_sig_domain *wire = &sig_attrs->wire; 4421 4422 memset(bsf, 0, sizeof(*bsf)); 4423 4424 /* Basic + Extended + Inline */ 4425 basic->bsf_size_sbs = 1 << 7; 4426 /* Input domain check byte mask */ 4427 basic->check_byte_mask = sig_attrs->check_mask; 4428 basic->raw_data_size = cpu_to_be32(data_size); 4429 4430 /* Memory domain */ 4431 switch (sig_attrs->mem.sig_type) { 4432 case IB_SIG_TYPE_NONE: 4433 break; 4434 case IB_SIG_TYPE_T10_DIF: 4435 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4436 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4437 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4438 break; 4439 default: 4440 return -EINVAL; 4441 } 4442 4443 /* Wire domain */ 4444 switch (sig_attrs->wire.sig_type) { 4445 case IB_SIG_TYPE_NONE: 4446 break; 4447 case IB_SIG_TYPE_T10_DIF: 4448 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4449 mem->sig_type == wire->sig_type) { 4450 /* Same block structure */ 4451 basic->bsf_size_sbs |= 1 << 4; 4452 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4453 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4454 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4455 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4456 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4457 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4458 } else 4459 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4460 4461 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4462 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4463 break; 4464 default: 4465 return -EINVAL; 4466 } 4467 4468 return 0; 4469 } 4470 4471 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 4472 struct mlx5_ib_qp *qp, void **seg, 4473 int *size, void **cur_edge) 4474 { 4475 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4476 struct ib_mr *sig_mr = wr->sig_mr; 4477 struct mlx5_bsf *bsf; 4478 u32 data_len = wr->wr.sg_list->length; 4479 u32 data_key = wr->wr.sg_list->lkey; 4480 u64 data_va = wr->wr.sg_list->addr; 4481 int ret; 4482 int wqe_size; 4483 4484 if (!wr->prot || 4485 (data_key == wr->prot->lkey && 4486 data_va == wr->prot->addr && 4487 data_len == wr->prot->length)) { 4488 /** 4489 * Source domain doesn't contain signature information 4490 * or data and protection are interleaved in memory. 4491 * So need construct: 4492 * ------------------ 4493 * | data_klm | 4494 * ------------------ 4495 * | BSF | 4496 * ------------------ 4497 **/ 4498 struct mlx5_klm *data_klm = *seg; 4499 4500 data_klm->bcount = cpu_to_be32(data_len); 4501 data_klm->key = cpu_to_be32(data_key); 4502 data_klm->va = cpu_to_be64(data_va); 4503 wqe_size = ALIGN(sizeof(*data_klm), 64); 4504 } else { 4505 /** 4506 * Source domain contains signature information 4507 * So need construct a strided block format: 4508 * --------------------------- 4509 * | stride_block_ctrl | 4510 * --------------------------- 4511 * | data_klm | 4512 * --------------------------- 4513 * | prot_klm | 4514 * --------------------------- 4515 * | BSF | 4516 * --------------------------- 4517 **/ 4518 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4519 struct mlx5_stride_block_entry *data_sentry; 4520 struct mlx5_stride_block_entry *prot_sentry; 4521 u32 prot_key = wr->prot->lkey; 4522 u64 prot_va = wr->prot->addr; 4523 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4524 int prot_size; 4525 4526 sblock_ctrl = *seg; 4527 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4528 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4529 4530 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4531 if (!prot_size) { 4532 pr_err("Bad block size given: %u\n", block_size); 4533 return -EINVAL; 4534 } 4535 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4536 prot_size); 4537 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4538 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4539 sblock_ctrl->num_entries = cpu_to_be16(2); 4540 4541 data_sentry->bcount = cpu_to_be16(block_size); 4542 data_sentry->key = cpu_to_be32(data_key); 4543 data_sentry->va = cpu_to_be64(data_va); 4544 data_sentry->stride = cpu_to_be16(block_size); 4545 4546 prot_sentry->bcount = cpu_to_be16(prot_size); 4547 prot_sentry->key = cpu_to_be32(prot_key); 4548 prot_sentry->va = cpu_to_be64(prot_va); 4549 prot_sentry->stride = cpu_to_be16(prot_size); 4550 4551 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4552 sizeof(*prot_sentry), 64); 4553 } 4554 4555 *seg += wqe_size; 4556 *size += wqe_size / 16; 4557 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4558 4559 bsf = *seg; 4560 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4561 if (ret) 4562 return -EINVAL; 4563 4564 *seg += sizeof(*bsf); 4565 *size += sizeof(*bsf) / 16; 4566 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4567 4568 return 0; 4569 } 4570 4571 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4572 const struct ib_sig_handover_wr *wr, u32 size, 4573 u32 length, u32 pdn) 4574 { 4575 struct ib_mr *sig_mr = wr->sig_mr; 4576 u32 sig_key = sig_mr->rkey; 4577 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4578 4579 memset(seg, 0, sizeof(*seg)); 4580 4581 seg->flags = get_umr_flags(wr->access_flags) | 4582 MLX5_MKC_ACCESS_MODE_KLMS; 4583 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4584 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4585 MLX5_MKEY_BSF_EN | pdn); 4586 seg->len = cpu_to_be64(length); 4587 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4588 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4589 } 4590 4591 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4592 u32 size) 4593 { 4594 memset(umr, 0, sizeof(*umr)); 4595 4596 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4597 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4598 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4599 umr->mkey_mask = sig_mkey_mask(); 4600 } 4601 4602 4603 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, 4604 struct mlx5_ib_qp *qp, void **seg, int *size, 4605 void **cur_edge) 4606 { 4607 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4608 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4609 u32 pdn = get_pd(qp)->pdn; 4610 u32 xlt_size; 4611 int region_len, ret; 4612 4613 if (unlikely(wr->wr.num_sge != 1) || 4614 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4615 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4616 unlikely(!sig_mr->sig->sig_status_checked)) 4617 return -EINVAL; 4618 4619 /* length of the protected region, data + protection */ 4620 region_len = wr->wr.sg_list->length; 4621 if (wr->prot && 4622 (wr->prot->lkey != wr->wr.sg_list->lkey || 4623 wr->prot->addr != wr->wr.sg_list->addr || 4624 wr->prot->length != wr->wr.sg_list->length)) 4625 region_len += wr->prot->length; 4626 4627 /** 4628 * KLM octoword size - if protection was provided 4629 * then we use strided block format (3 octowords), 4630 * else we use single KLM (1 octoword) 4631 **/ 4632 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4633 4634 set_sig_umr_segment(*seg, xlt_size); 4635 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4636 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4637 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4638 4639 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4640 *seg += sizeof(struct mlx5_mkey_seg); 4641 *size += sizeof(struct mlx5_mkey_seg) / 16; 4642 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4643 4644 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge); 4645 if (ret) 4646 return ret; 4647 4648 sig_mr->sig->sig_status_checked = false; 4649 return 0; 4650 } 4651 4652 static int set_psv_wr(struct ib_sig_domain *domain, 4653 u32 psv_idx, void **seg, int *size) 4654 { 4655 struct mlx5_seg_set_psv *psv_seg = *seg; 4656 4657 memset(psv_seg, 0, sizeof(*psv_seg)); 4658 psv_seg->psv_num = cpu_to_be32(psv_idx); 4659 switch (domain->sig_type) { 4660 case IB_SIG_TYPE_NONE: 4661 break; 4662 case IB_SIG_TYPE_T10_DIF: 4663 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4664 domain->sig.dif.app_tag); 4665 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4666 break; 4667 default: 4668 pr_err("Bad signature type (%d) is given.\n", 4669 domain->sig_type); 4670 return -EINVAL; 4671 } 4672 4673 *seg += sizeof(*psv_seg); 4674 *size += sizeof(*psv_seg) / 16; 4675 4676 return 0; 4677 } 4678 4679 static int set_reg_wr(struct mlx5_ib_qp *qp, 4680 const struct ib_reg_wr *wr, 4681 void **seg, int *size, void **cur_edge) 4682 { 4683 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4684 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4685 size_t mr_list_size = mr->ndescs * mr->desc_size; 4686 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4687 4688 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4689 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4690 "Invalid IB_SEND_INLINE send flag\n"); 4691 return -EINVAL; 4692 } 4693 4694 set_reg_umr_seg(*seg, mr, umr_inline); 4695 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4696 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4697 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4698 4699 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4700 *seg += sizeof(struct mlx5_mkey_seg); 4701 *size += sizeof(struct mlx5_mkey_seg) / 16; 4702 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4703 4704 if (umr_inline) { 4705 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, 4706 mr_list_size); 4707 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); 4708 } else { 4709 set_reg_data_seg(*seg, mr, pd); 4710 *seg += sizeof(struct mlx5_wqe_data_seg); 4711 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4712 } 4713 return 0; 4714 } 4715 4716 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, 4717 void **cur_edge) 4718 { 4719 set_linv_umr_seg(*seg); 4720 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4721 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4722 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4723 set_linv_mkey_seg(*seg); 4724 *seg += sizeof(struct mlx5_mkey_seg); 4725 *size += sizeof(struct mlx5_mkey_seg) / 16; 4726 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4727 } 4728 4729 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) 4730 { 4731 __be32 *p = NULL; 4732 u32 tidx = idx; 4733 int i, j; 4734 4735 pr_debug("dump WQE index %u:\n", idx); 4736 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4737 if ((i & 0xf) == 0) { 4738 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4739 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx); 4740 pr_debug("WQBB at %p:\n", (void *)p); 4741 j = 0; 4742 } 4743 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4744 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4745 be32_to_cpu(p[j + 3])); 4746 } 4747 } 4748 4749 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4750 struct mlx5_wqe_ctrl_seg **ctrl, 4751 const struct ib_send_wr *wr, unsigned int *idx, 4752 int *size, void **cur_edge, int nreq, 4753 bool send_signaled, bool solicited) 4754 { 4755 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4756 return -ENOMEM; 4757 4758 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4759 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); 4760 *ctrl = *seg; 4761 *(uint32_t *)(*seg + 8) = 0; 4762 (*ctrl)->imm = send_ieth(wr); 4763 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4764 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4765 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 4766 4767 *seg += sizeof(**ctrl); 4768 *size = sizeof(**ctrl) / 16; 4769 *cur_edge = qp->sq.cur_edge; 4770 4771 return 0; 4772 } 4773 4774 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4775 struct mlx5_wqe_ctrl_seg **ctrl, 4776 const struct ib_send_wr *wr, unsigned *idx, 4777 int *size, void **cur_edge, int nreq) 4778 { 4779 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, 4780 wr->send_flags & IB_SEND_SIGNALED, 4781 wr->send_flags & IB_SEND_SOLICITED); 4782 } 4783 4784 static void finish_wqe(struct mlx5_ib_qp *qp, 4785 struct mlx5_wqe_ctrl_seg *ctrl, 4786 void *seg, u8 size, void *cur_edge, 4787 unsigned int idx, u64 wr_id, int nreq, u8 fence, 4788 u32 mlx5_opcode) 4789 { 4790 u8 opmod = 0; 4791 4792 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4793 mlx5_opcode | ((u32)opmod << 24)); 4794 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4795 ctrl->fm_ce_se |= fence; 4796 if (unlikely(qp->wq_sig)) 4797 ctrl->signature = wq_sig(ctrl); 4798 4799 qp->sq.wrid[idx] = wr_id; 4800 qp->sq.w_list[idx].opcode = mlx5_opcode; 4801 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4802 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4803 qp->sq.w_list[idx].next = qp->sq.cur_post; 4804 4805 /* We save the edge which was possibly updated during the WQE 4806 * construction, into SQ's cache. 4807 */ 4808 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); 4809 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? 4810 get_sq_edge(&qp->sq, qp->sq.cur_post & 4811 (qp->sq.wqe_cnt - 1)) : 4812 cur_edge; 4813 } 4814 4815 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 4816 const struct ib_send_wr **bad_wr, bool drain) 4817 { 4818 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4819 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4820 struct mlx5_core_dev *mdev = dev->mdev; 4821 struct mlx5_ib_qp *qp; 4822 struct mlx5_ib_mr *mr; 4823 struct mlx5_wqe_xrc_seg *xrc; 4824 struct mlx5_bf *bf; 4825 void *cur_edge; 4826 int uninitialized_var(size); 4827 unsigned long flags; 4828 unsigned idx; 4829 int err = 0; 4830 int num_sge; 4831 void *seg; 4832 int nreq; 4833 int i; 4834 u8 next_fence = 0; 4835 u8 fence; 4836 4837 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 4838 !drain)) { 4839 *bad_wr = wr; 4840 return -EIO; 4841 } 4842 4843 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4844 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4845 4846 qp = to_mqp(ibqp); 4847 bf = &qp->bf; 4848 4849 spin_lock_irqsave(&qp->sq.lock, flags); 4850 4851 for (nreq = 0; wr; nreq++, wr = wr->next) { 4852 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4853 mlx5_ib_warn(dev, "\n"); 4854 err = -EINVAL; 4855 *bad_wr = wr; 4856 goto out; 4857 } 4858 4859 num_sge = wr->num_sge; 4860 if (unlikely(num_sge > qp->sq.max_gs)) { 4861 mlx5_ib_warn(dev, "\n"); 4862 err = -EINVAL; 4863 *bad_wr = wr; 4864 goto out; 4865 } 4866 4867 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, 4868 nreq); 4869 if (err) { 4870 mlx5_ib_warn(dev, "\n"); 4871 err = -ENOMEM; 4872 *bad_wr = wr; 4873 goto out; 4874 } 4875 4876 if (wr->opcode == IB_WR_REG_MR) { 4877 fence = dev->umr_fence; 4878 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4879 } else { 4880 if (wr->send_flags & IB_SEND_FENCE) { 4881 if (qp->next_fence) 4882 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4883 else 4884 fence = MLX5_FENCE_MODE_FENCE; 4885 } else { 4886 fence = qp->next_fence; 4887 } 4888 } 4889 4890 switch (ibqp->qp_type) { 4891 case IB_QPT_XRC_INI: 4892 xrc = seg; 4893 seg += sizeof(*xrc); 4894 size += sizeof(*xrc) / 16; 4895 /* fall through */ 4896 case IB_QPT_RC: 4897 switch (wr->opcode) { 4898 case IB_WR_RDMA_READ: 4899 case IB_WR_RDMA_WRITE: 4900 case IB_WR_RDMA_WRITE_WITH_IMM: 4901 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4902 rdma_wr(wr)->rkey); 4903 seg += sizeof(struct mlx5_wqe_raddr_seg); 4904 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4905 break; 4906 4907 case IB_WR_ATOMIC_CMP_AND_SWP: 4908 case IB_WR_ATOMIC_FETCH_AND_ADD: 4909 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4910 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4911 err = -ENOSYS; 4912 *bad_wr = wr; 4913 goto out; 4914 4915 case IB_WR_LOCAL_INV: 4916 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4917 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4918 set_linv_wr(qp, &seg, &size, &cur_edge); 4919 num_sge = 0; 4920 break; 4921 4922 case IB_WR_REG_MR: 4923 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4924 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4925 err = set_reg_wr(qp, reg_wr(wr), &seg, &size, 4926 &cur_edge); 4927 if (err) { 4928 *bad_wr = wr; 4929 goto out; 4930 } 4931 num_sge = 0; 4932 break; 4933 4934 case IB_WR_REG_SIG_MR: 4935 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4936 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4937 4938 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4939 err = set_sig_umr_wr(wr, qp, &seg, &size, 4940 &cur_edge); 4941 if (err) { 4942 mlx5_ib_warn(dev, "\n"); 4943 *bad_wr = wr; 4944 goto out; 4945 } 4946 4947 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4948 wr->wr_id, nreq, fence, 4949 MLX5_OPCODE_UMR); 4950 /* 4951 * SET_PSV WQEs are not signaled and solicited 4952 * on error 4953 */ 4954 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4955 &size, &cur_edge, nreq, false, 4956 true); 4957 if (err) { 4958 mlx5_ib_warn(dev, "\n"); 4959 err = -ENOMEM; 4960 *bad_wr = wr; 4961 goto out; 4962 } 4963 4964 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4965 mr->sig->psv_memory.psv_idx, &seg, 4966 &size); 4967 if (err) { 4968 mlx5_ib_warn(dev, "\n"); 4969 *bad_wr = wr; 4970 goto out; 4971 } 4972 4973 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4974 wr->wr_id, nreq, fence, 4975 MLX5_OPCODE_SET_PSV); 4976 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4977 &size, &cur_edge, nreq, false, 4978 true); 4979 if (err) { 4980 mlx5_ib_warn(dev, "\n"); 4981 err = -ENOMEM; 4982 *bad_wr = wr; 4983 goto out; 4984 } 4985 4986 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4987 mr->sig->psv_wire.psv_idx, &seg, 4988 &size); 4989 if (err) { 4990 mlx5_ib_warn(dev, "\n"); 4991 *bad_wr = wr; 4992 goto out; 4993 } 4994 4995 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4996 wr->wr_id, nreq, fence, 4997 MLX5_OPCODE_SET_PSV); 4998 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4999 num_sge = 0; 5000 goto skip_psv; 5001 5002 default: 5003 break; 5004 } 5005 break; 5006 5007 case IB_QPT_UC: 5008 switch (wr->opcode) { 5009 case IB_WR_RDMA_WRITE: 5010 case IB_WR_RDMA_WRITE_WITH_IMM: 5011 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 5012 rdma_wr(wr)->rkey); 5013 seg += sizeof(struct mlx5_wqe_raddr_seg); 5014 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 5015 break; 5016 5017 default: 5018 break; 5019 } 5020 break; 5021 5022 case IB_QPT_SMI: 5023 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 5024 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 5025 err = -EPERM; 5026 *bad_wr = wr; 5027 goto out; 5028 } 5029 /* fall through */ 5030 case MLX5_IB_QPT_HW_GSI: 5031 set_datagram_seg(seg, wr); 5032 seg += sizeof(struct mlx5_wqe_datagram_seg); 5033 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5034 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5035 5036 break; 5037 case IB_QPT_UD: 5038 set_datagram_seg(seg, wr); 5039 seg += sizeof(struct mlx5_wqe_datagram_seg); 5040 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5041 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5042 5043 /* handle qp that supports ud offload */ 5044 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 5045 struct mlx5_wqe_eth_pad *pad; 5046 5047 pad = seg; 5048 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 5049 seg += sizeof(struct mlx5_wqe_eth_pad); 5050 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 5051 set_eth_seg(wr, qp, &seg, &size, &cur_edge); 5052 handle_post_send_edge(&qp->sq, &seg, size, 5053 &cur_edge); 5054 } 5055 break; 5056 case MLX5_IB_QPT_REG_UMR: 5057 if (wr->opcode != MLX5_IB_WR_UMR) { 5058 err = -EINVAL; 5059 mlx5_ib_warn(dev, "bad opcode\n"); 5060 goto out; 5061 } 5062 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 5063 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 5064 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 5065 if (unlikely(err)) 5066 goto out; 5067 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 5068 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 5069 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5070 set_reg_mkey_segment(seg, wr); 5071 seg += sizeof(struct mlx5_mkey_seg); 5072 size += sizeof(struct mlx5_mkey_seg) / 16; 5073 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5074 break; 5075 5076 default: 5077 break; 5078 } 5079 5080 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 5081 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); 5082 if (unlikely(err)) { 5083 mlx5_ib_warn(dev, "\n"); 5084 *bad_wr = wr; 5085 goto out; 5086 } 5087 } else { 5088 for (i = 0; i < num_sge; i++) { 5089 handle_post_send_edge(&qp->sq, &seg, size, 5090 &cur_edge); 5091 if (likely(wr->sg_list[i].length)) { 5092 set_data_ptr_seg 5093 ((struct mlx5_wqe_data_seg *)seg, 5094 wr->sg_list + i); 5095 size += sizeof(struct mlx5_wqe_data_seg) / 16; 5096 seg += sizeof(struct mlx5_wqe_data_seg); 5097 } 5098 } 5099 } 5100 5101 qp->next_fence = next_fence; 5102 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, 5103 fence, mlx5_ib_opcode[wr->opcode]); 5104 skip_psv: 5105 if (0) 5106 dump_wqe(qp, idx, size); 5107 } 5108 5109 out: 5110 if (likely(nreq)) { 5111 qp->sq.head += nreq; 5112 5113 /* Make sure that descriptors are written before 5114 * updating doorbell record and ringing the doorbell 5115 */ 5116 wmb(); 5117 5118 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 5119 5120 /* Make sure doorbell record is visible to the HCA before 5121 * we hit doorbell */ 5122 wmb(); 5123 5124 /* currently we support only regular doorbells */ 5125 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 5126 /* Make sure doorbells don't leak out of SQ spinlock 5127 * and reach the HCA out of order. 5128 */ 5129 mmiowb(); 5130 bf->offset ^= bf->buf_size; 5131 } 5132 5133 spin_unlock_irqrestore(&qp->sq.lock, flags); 5134 5135 return err; 5136 } 5137 5138 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5139 const struct ib_send_wr **bad_wr) 5140 { 5141 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); 5142 } 5143 5144 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 5145 { 5146 sig->signature = calc_sig(sig, size); 5147 } 5148 5149 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5150 const struct ib_recv_wr **bad_wr, bool drain) 5151 { 5152 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5153 struct mlx5_wqe_data_seg *scat; 5154 struct mlx5_rwqe_sig *sig; 5155 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5156 struct mlx5_core_dev *mdev = dev->mdev; 5157 unsigned long flags; 5158 int err = 0; 5159 int nreq; 5160 int ind; 5161 int i; 5162 5163 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5164 !drain)) { 5165 *bad_wr = wr; 5166 return -EIO; 5167 } 5168 5169 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5170 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 5171 5172 spin_lock_irqsave(&qp->rq.lock, flags); 5173 5174 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 5175 5176 for (nreq = 0; wr; nreq++, wr = wr->next) { 5177 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 5178 err = -ENOMEM; 5179 *bad_wr = wr; 5180 goto out; 5181 } 5182 5183 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 5184 err = -EINVAL; 5185 *bad_wr = wr; 5186 goto out; 5187 } 5188 5189 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); 5190 if (qp->wq_sig) 5191 scat++; 5192 5193 for (i = 0; i < wr->num_sge; i++) 5194 set_data_ptr_seg(scat + i, wr->sg_list + i); 5195 5196 if (i < qp->rq.max_gs) { 5197 scat[i].byte_count = 0; 5198 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 5199 scat[i].addr = 0; 5200 } 5201 5202 if (qp->wq_sig) { 5203 sig = (struct mlx5_rwqe_sig *)scat; 5204 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 5205 } 5206 5207 qp->rq.wrid[ind] = wr->wr_id; 5208 5209 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 5210 } 5211 5212 out: 5213 if (likely(nreq)) { 5214 qp->rq.head += nreq; 5215 5216 /* Make sure that descriptors are written before 5217 * doorbell record. 5218 */ 5219 wmb(); 5220 5221 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 5222 } 5223 5224 spin_unlock_irqrestore(&qp->rq.lock, flags); 5225 5226 return err; 5227 } 5228 5229 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5230 const struct ib_recv_wr **bad_wr) 5231 { 5232 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); 5233 } 5234 5235 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 5236 { 5237 switch (mlx5_state) { 5238 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 5239 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 5240 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 5241 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 5242 case MLX5_QP_STATE_SQ_DRAINING: 5243 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 5244 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 5245 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 5246 default: return -1; 5247 } 5248 } 5249 5250 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 5251 { 5252 switch (mlx5_mig_state) { 5253 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 5254 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 5255 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 5256 default: return -1; 5257 } 5258 } 5259 5260 static int to_ib_qp_access_flags(int mlx5_flags) 5261 { 5262 int ib_flags = 0; 5263 5264 if (mlx5_flags & MLX5_QP_BIT_RRE) 5265 ib_flags |= IB_ACCESS_REMOTE_READ; 5266 if (mlx5_flags & MLX5_QP_BIT_RWE) 5267 ib_flags |= IB_ACCESS_REMOTE_WRITE; 5268 if (mlx5_flags & MLX5_QP_BIT_RAE) 5269 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 5270 5271 return ib_flags; 5272 } 5273 5274 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 5275 struct rdma_ah_attr *ah_attr, 5276 struct mlx5_qp_path *path) 5277 { 5278 5279 memset(ah_attr, 0, sizeof(*ah_attr)); 5280 5281 if (!path->port || path->port > ibdev->num_ports) 5282 return; 5283 5284 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 5285 5286 rdma_ah_set_port_num(ah_attr, path->port); 5287 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 5288 5289 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 5290 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 5291 rdma_ah_set_static_rate(ah_attr, 5292 path->static_rate ? path->static_rate - 5 : 0); 5293 if (path->grh_mlid & (1 << 7)) { 5294 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 5295 5296 rdma_ah_set_grh(ah_attr, NULL, 5297 tc_fl & 0xfffff, 5298 path->mgid_index, 5299 path->hop_limit, 5300 (tc_fl >> 20) & 0xff); 5301 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 5302 } 5303 } 5304 5305 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 5306 struct mlx5_ib_sq *sq, 5307 u8 *sq_state) 5308 { 5309 int err; 5310 5311 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 5312 if (err) 5313 goto out; 5314 sq->state = *sq_state; 5315 5316 out: 5317 return err; 5318 } 5319 5320 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 5321 struct mlx5_ib_rq *rq, 5322 u8 *rq_state) 5323 { 5324 void *out; 5325 void *rqc; 5326 int inlen; 5327 int err; 5328 5329 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 5330 out = kvzalloc(inlen, GFP_KERNEL); 5331 if (!out) 5332 return -ENOMEM; 5333 5334 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 5335 if (err) 5336 goto out; 5337 5338 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 5339 *rq_state = MLX5_GET(rqc, rqc, state); 5340 rq->state = *rq_state; 5341 5342 out: 5343 kvfree(out); 5344 return err; 5345 } 5346 5347 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 5348 struct mlx5_ib_qp *qp, u8 *qp_state) 5349 { 5350 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 5351 [MLX5_RQC_STATE_RST] = { 5352 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5353 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5354 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 5355 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 5356 }, 5357 [MLX5_RQC_STATE_RDY] = { 5358 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5359 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5360 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 5361 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 5362 }, 5363 [MLX5_RQC_STATE_ERR] = { 5364 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5365 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5366 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 5367 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 5368 }, 5369 [MLX5_RQ_STATE_NA] = { 5370 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5371 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5372 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 5373 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 5374 }, 5375 }; 5376 5377 *qp_state = sqrq_trans[rq_state][sq_state]; 5378 5379 if (*qp_state == MLX5_QP_STATE_BAD) { 5380 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 5381 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 5382 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 5383 return -EINVAL; 5384 } 5385 5386 if (*qp_state == MLX5_QP_STATE) 5387 *qp_state = qp->state; 5388 5389 return 0; 5390 } 5391 5392 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 5393 struct mlx5_ib_qp *qp, 5394 u8 *raw_packet_qp_state) 5395 { 5396 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 5397 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 5398 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 5399 int err; 5400 u8 sq_state = MLX5_SQ_STATE_NA; 5401 u8 rq_state = MLX5_RQ_STATE_NA; 5402 5403 if (qp->sq.wqe_cnt) { 5404 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 5405 if (err) 5406 return err; 5407 } 5408 5409 if (qp->rq.wqe_cnt) { 5410 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 5411 if (err) 5412 return err; 5413 } 5414 5415 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 5416 raw_packet_qp_state); 5417 } 5418 5419 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 5420 struct ib_qp_attr *qp_attr) 5421 { 5422 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 5423 struct mlx5_qp_context *context; 5424 int mlx5_state; 5425 u32 *outb; 5426 int err = 0; 5427 5428 outb = kzalloc(outlen, GFP_KERNEL); 5429 if (!outb) 5430 return -ENOMEM; 5431 5432 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 5433 outlen); 5434 if (err) 5435 goto out; 5436 5437 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 5438 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 5439 5440 mlx5_state = be32_to_cpu(context->flags) >> 28; 5441 5442 qp->state = to_ib_qp_state(mlx5_state); 5443 qp_attr->path_mtu = context->mtu_msgmax >> 5; 5444 qp_attr->path_mig_state = 5445 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 5446 qp_attr->qkey = be32_to_cpu(context->qkey); 5447 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 5448 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 5449 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 5450 qp_attr->qp_access_flags = 5451 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 5452 5453 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 5454 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 5455 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5456 qp_attr->alt_pkey_index = 5457 be16_to_cpu(context->alt_path.pkey_index); 5458 qp_attr->alt_port_num = 5459 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5460 } 5461 5462 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5463 qp_attr->port_num = context->pri_path.port; 5464 5465 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5466 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5467 5468 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5469 5470 qp_attr->max_dest_rd_atomic = 5471 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5472 qp_attr->min_rnr_timer = 5473 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5474 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5475 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5476 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5477 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5478 5479 out: 5480 kfree(outb); 5481 return err; 5482 } 5483 5484 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5485 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5486 struct ib_qp_init_attr *qp_init_attr) 5487 { 5488 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5489 u32 *out; 5490 u32 access_flags = 0; 5491 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5492 void *dctc; 5493 int err; 5494 int supported_mask = IB_QP_STATE | 5495 IB_QP_ACCESS_FLAGS | 5496 IB_QP_PORT | 5497 IB_QP_MIN_RNR_TIMER | 5498 IB_QP_AV | 5499 IB_QP_PATH_MTU | 5500 IB_QP_PKEY_INDEX; 5501 5502 if (qp_attr_mask & ~supported_mask) 5503 return -EINVAL; 5504 if (mqp->state != IB_QPS_RTR) 5505 return -EINVAL; 5506 5507 out = kzalloc(outlen, GFP_KERNEL); 5508 if (!out) 5509 return -ENOMEM; 5510 5511 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5512 if (err) 5513 goto out; 5514 5515 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5516 5517 if (qp_attr_mask & IB_QP_STATE) 5518 qp_attr->qp_state = IB_QPS_RTR; 5519 5520 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5521 if (MLX5_GET(dctc, dctc, rre)) 5522 access_flags |= IB_ACCESS_REMOTE_READ; 5523 if (MLX5_GET(dctc, dctc, rwe)) 5524 access_flags |= IB_ACCESS_REMOTE_WRITE; 5525 if (MLX5_GET(dctc, dctc, rae)) 5526 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5527 qp_attr->qp_access_flags = access_flags; 5528 } 5529 5530 if (qp_attr_mask & IB_QP_PORT) 5531 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5532 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5533 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5534 if (qp_attr_mask & IB_QP_AV) { 5535 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5536 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5537 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5538 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5539 } 5540 if (qp_attr_mask & IB_QP_PATH_MTU) 5541 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5542 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5543 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5544 out: 5545 kfree(out); 5546 return err; 5547 } 5548 5549 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5550 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5551 { 5552 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5553 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5554 int err = 0; 5555 u8 raw_packet_qp_state; 5556 5557 if (ibqp->rwq_ind_tbl) 5558 return -ENOSYS; 5559 5560 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5561 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5562 qp_init_attr); 5563 5564 /* Not all of output fields are applicable, make sure to zero them */ 5565 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5566 memset(qp_attr, 0, sizeof(*qp_attr)); 5567 5568 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5569 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5570 qp_attr_mask, qp_init_attr); 5571 5572 mutex_lock(&qp->mutex); 5573 5574 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5575 qp->flags & MLX5_IB_QP_UNDERLAY) { 5576 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5577 if (err) 5578 goto out; 5579 qp->state = raw_packet_qp_state; 5580 qp_attr->port_num = 1; 5581 } else { 5582 err = query_qp_attr(dev, qp, qp_attr); 5583 if (err) 5584 goto out; 5585 } 5586 5587 qp_attr->qp_state = qp->state; 5588 qp_attr->cur_qp_state = qp_attr->qp_state; 5589 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5590 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5591 5592 if (!ibqp->uobject) { 5593 qp_attr->cap.max_send_wr = qp->sq.max_post; 5594 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5595 qp_init_attr->qp_context = ibqp->qp_context; 5596 } else { 5597 qp_attr->cap.max_send_wr = 0; 5598 qp_attr->cap.max_send_sge = 0; 5599 } 5600 5601 qp_init_attr->qp_type = ibqp->qp_type; 5602 qp_init_attr->recv_cq = ibqp->recv_cq; 5603 qp_init_attr->send_cq = ibqp->send_cq; 5604 qp_init_attr->srq = ibqp->srq; 5605 qp_attr->cap.max_inline_data = qp->max_inline_data; 5606 5607 qp_init_attr->cap = qp_attr->cap; 5608 5609 qp_init_attr->create_flags = 0; 5610 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5611 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5612 5613 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5614 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5615 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5616 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5617 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5618 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5619 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5620 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5621 5622 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5623 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5624 5625 out: 5626 mutex_unlock(&qp->mutex); 5627 return err; 5628 } 5629 5630 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5631 struct ib_ucontext *context, 5632 struct ib_udata *udata) 5633 { 5634 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5635 struct mlx5_ib_xrcd *xrcd; 5636 int err; 5637 5638 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5639 return ERR_PTR(-ENOSYS); 5640 5641 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5642 if (!xrcd) 5643 return ERR_PTR(-ENOMEM); 5644 5645 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5646 if (err) { 5647 kfree(xrcd); 5648 return ERR_PTR(-ENOMEM); 5649 } 5650 5651 return &xrcd->ibxrcd; 5652 } 5653 5654 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5655 { 5656 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5657 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5658 int err; 5659 5660 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5661 if (err) 5662 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5663 5664 kfree(xrcd); 5665 return 0; 5666 } 5667 5668 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5669 { 5670 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5671 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5672 struct ib_event event; 5673 5674 if (rwq->ibwq.event_handler) { 5675 event.device = rwq->ibwq.device; 5676 event.element.wq = &rwq->ibwq; 5677 switch (type) { 5678 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5679 event.event = IB_EVENT_WQ_FATAL; 5680 break; 5681 default: 5682 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5683 return; 5684 } 5685 5686 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5687 } 5688 } 5689 5690 static int set_delay_drop(struct mlx5_ib_dev *dev) 5691 { 5692 int err = 0; 5693 5694 mutex_lock(&dev->delay_drop.lock); 5695 if (dev->delay_drop.activate) 5696 goto out; 5697 5698 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5699 if (err) 5700 goto out; 5701 5702 dev->delay_drop.activate = true; 5703 out: 5704 mutex_unlock(&dev->delay_drop.lock); 5705 5706 if (!err) 5707 atomic_inc(&dev->delay_drop.rqs_cnt); 5708 return err; 5709 } 5710 5711 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5712 struct ib_wq_init_attr *init_attr) 5713 { 5714 struct mlx5_ib_dev *dev; 5715 int has_net_offloads; 5716 __be64 *rq_pas0; 5717 void *in; 5718 void *rqc; 5719 void *wq; 5720 int inlen; 5721 int err; 5722 5723 dev = to_mdev(pd->device); 5724 5725 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5726 in = kvzalloc(inlen, GFP_KERNEL); 5727 if (!in) 5728 return -ENOMEM; 5729 5730 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5731 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5732 MLX5_SET(rqc, rqc, mem_rq_type, 5733 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5734 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5735 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5736 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5737 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5738 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5739 MLX5_SET(wq, wq, wq_type, 5740 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5741 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5742 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5743 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5744 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5745 err = -EOPNOTSUPP; 5746 goto out; 5747 } else { 5748 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5749 } 5750 } 5751 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5752 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5753 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5754 MLX5_SET(wq, wq, log_wqe_stride_size, 5755 rwq->single_stride_log_num_of_bytes - 5756 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5757 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5758 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5759 } 5760 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5761 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5762 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5763 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5764 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5765 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5766 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5767 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5768 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5769 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5770 err = -EOPNOTSUPP; 5771 goto out; 5772 } 5773 } else { 5774 MLX5_SET(rqc, rqc, vsd, 1); 5775 } 5776 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5777 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5778 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5779 err = -EOPNOTSUPP; 5780 goto out; 5781 } 5782 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5783 } 5784 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5785 if (!(dev->ib_dev.attrs.raw_packet_caps & 5786 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5787 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5788 err = -EOPNOTSUPP; 5789 goto out; 5790 } 5791 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5792 } 5793 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5794 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5795 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5796 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5797 err = set_delay_drop(dev); 5798 if (err) { 5799 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5800 err); 5801 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5802 } else { 5803 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5804 } 5805 } 5806 out: 5807 kvfree(in); 5808 return err; 5809 } 5810 5811 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5812 struct ib_wq_init_attr *wq_init_attr, 5813 struct mlx5_ib_create_wq *ucmd, 5814 struct mlx5_ib_rwq *rwq) 5815 { 5816 /* Sanity check RQ size before proceeding */ 5817 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5818 return -EINVAL; 5819 5820 if (!ucmd->rq_wqe_count) 5821 return -EINVAL; 5822 5823 rwq->wqe_count = ucmd->rq_wqe_count; 5824 rwq->wqe_shift = ucmd->rq_wqe_shift; 5825 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5826 return -EINVAL; 5827 5828 rwq->log_rq_stride = rwq->wqe_shift; 5829 rwq->log_rq_size = ilog2(rwq->wqe_count); 5830 return 0; 5831 } 5832 5833 static int prepare_user_rq(struct ib_pd *pd, 5834 struct ib_wq_init_attr *init_attr, 5835 struct ib_udata *udata, 5836 struct mlx5_ib_rwq *rwq) 5837 { 5838 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5839 struct mlx5_ib_create_wq ucmd = {}; 5840 int err; 5841 size_t required_cmd_sz; 5842 5843 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5844 + sizeof(ucmd.single_stride_log_num_of_bytes); 5845 if (udata->inlen < required_cmd_sz) { 5846 mlx5_ib_dbg(dev, "invalid inlen\n"); 5847 return -EINVAL; 5848 } 5849 5850 if (udata->inlen > sizeof(ucmd) && 5851 !ib_is_udata_cleared(udata, sizeof(ucmd), 5852 udata->inlen - sizeof(ucmd))) { 5853 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5854 return -EOPNOTSUPP; 5855 } 5856 5857 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5858 mlx5_ib_dbg(dev, "copy failed\n"); 5859 return -EFAULT; 5860 } 5861 5862 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5863 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5864 return -EOPNOTSUPP; 5865 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5866 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5867 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5868 return -EOPNOTSUPP; 5869 } 5870 if ((ucmd.single_stride_log_num_of_bytes < 5871 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5872 (ucmd.single_stride_log_num_of_bytes > 5873 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5874 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5875 ucmd.single_stride_log_num_of_bytes, 5876 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5877 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5878 return -EINVAL; 5879 } 5880 if ((ucmd.single_wqe_log_num_of_strides > 5881 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5882 (ucmd.single_wqe_log_num_of_strides < 5883 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5884 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5885 ucmd.single_wqe_log_num_of_strides, 5886 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5887 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5888 return -EINVAL; 5889 } 5890 rwq->single_stride_log_num_of_bytes = 5891 ucmd.single_stride_log_num_of_bytes; 5892 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5893 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5894 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5895 } 5896 5897 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5898 if (err) { 5899 mlx5_ib_dbg(dev, "err %d\n", err); 5900 return err; 5901 } 5902 5903 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5904 if (err) { 5905 mlx5_ib_dbg(dev, "err %d\n", err); 5906 return err; 5907 } 5908 5909 rwq->user_index = ucmd.user_index; 5910 return 0; 5911 } 5912 5913 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5914 struct ib_wq_init_attr *init_attr, 5915 struct ib_udata *udata) 5916 { 5917 struct mlx5_ib_dev *dev; 5918 struct mlx5_ib_rwq *rwq; 5919 struct mlx5_ib_create_wq_resp resp = {}; 5920 size_t min_resp_len; 5921 int err; 5922 5923 if (!udata) 5924 return ERR_PTR(-ENOSYS); 5925 5926 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5927 if (udata->outlen && udata->outlen < min_resp_len) 5928 return ERR_PTR(-EINVAL); 5929 5930 dev = to_mdev(pd->device); 5931 switch (init_attr->wq_type) { 5932 case IB_WQT_RQ: 5933 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5934 if (!rwq) 5935 return ERR_PTR(-ENOMEM); 5936 err = prepare_user_rq(pd, init_attr, udata, rwq); 5937 if (err) 5938 goto err; 5939 err = create_rq(rwq, pd, init_attr); 5940 if (err) 5941 goto err_user_rq; 5942 break; 5943 default: 5944 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5945 init_attr->wq_type); 5946 return ERR_PTR(-EINVAL); 5947 } 5948 5949 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5950 rwq->ibwq.state = IB_WQS_RESET; 5951 if (udata->outlen) { 5952 resp.response_length = offsetof(typeof(resp), response_length) + 5953 sizeof(resp.response_length); 5954 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5955 if (err) 5956 goto err_copy; 5957 } 5958 5959 rwq->core_qp.event = mlx5_ib_wq_event; 5960 rwq->ibwq.event_handler = init_attr->event_handler; 5961 return &rwq->ibwq; 5962 5963 err_copy: 5964 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5965 err_user_rq: 5966 destroy_user_rq(dev, pd, rwq); 5967 err: 5968 kfree(rwq); 5969 return ERR_PTR(err); 5970 } 5971 5972 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5973 { 5974 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5975 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5976 5977 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5978 destroy_user_rq(dev, wq->pd, rwq); 5979 kfree(rwq); 5980 5981 return 0; 5982 } 5983 5984 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5985 struct ib_rwq_ind_table_init_attr *init_attr, 5986 struct ib_udata *udata) 5987 { 5988 struct mlx5_ib_dev *dev = to_mdev(device); 5989 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5990 int sz = 1 << init_attr->log_ind_tbl_size; 5991 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5992 size_t min_resp_len; 5993 int inlen; 5994 int err; 5995 int i; 5996 u32 *in; 5997 void *rqtc; 5998 5999 if (udata->inlen > 0 && 6000 !ib_is_udata_cleared(udata, 0, 6001 udata->inlen)) 6002 return ERR_PTR(-EOPNOTSUPP); 6003 6004 if (init_attr->log_ind_tbl_size > 6005 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 6006 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 6007 init_attr->log_ind_tbl_size, 6008 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 6009 return ERR_PTR(-EINVAL); 6010 } 6011 6012 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 6013 if (udata->outlen && udata->outlen < min_resp_len) 6014 return ERR_PTR(-EINVAL); 6015 6016 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 6017 if (!rwq_ind_tbl) 6018 return ERR_PTR(-ENOMEM); 6019 6020 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 6021 in = kvzalloc(inlen, GFP_KERNEL); 6022 if (!in) { 6023 err = -ENOMEM; 6024 goto err; 6025 } 6026 6027 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 6028 6029 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 6030 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 6031 6032 for (i = 0; i < sz; i++) 6033 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 6034 6035 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 6036 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 6037 6038 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 6039 kvfree(in); 6040 6041 if (err) 6042 goto err; 6043 6044 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 6045 if (udata->outlen) { 6046 resp.response_length = offsetof(typeof(resp), response_length) + 6047 sizeof(resp.response_length); 6048 err = ib_copy_to_udata(udata, &resp, resp.response_length); 6049 if (err) 6050 goto err_copy; 6051 } 6052 6053 return &rwq_ind_tbl->ib_rwq_ind_tbl; 6054 6055 err_copy: 6056 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6057 err: 6058 kfree(rwq_ind_tbl); 6059 return ERR_PTR(err); 6060 } 6061 6062 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 6063 { 6064 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 6065 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 6066 6067 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6068 6069 kfree(rwq_ind_tbl); 6070 return 0; 6071 } 6072 6073 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 6074 u32 wq_attr_mask, struct ib_udata *udata) 6075 { 6076 struct mlx5_ib_dev *dev = to_mdev(wq->device); 6077 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 6078 struct mlx5_ib_modify_wq ucmd = {}; 6079 size_t required_cmd_sz; 6080 int curr_wq_state; 6081 int wq_state; 6082 int inlen; 6083 int err; 6084 void *rqc; 6085 void *in; 6086 6087 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 6088 if (udata->inlen < required_cmd_sz) 6089 return -EINVAL; 6090 6091 if (udata->inlen > sizeof(ucmd) && 6092 !ib_is_udata_cleared(udata, sizeof(ucmd), 6093 udata->inlen - sizeof(ucmd))) 6094 return -EOPNOTSUPP; 6095 6096 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 6097 return -EFAULT; 6098 6099 if (ucmd.comp_mask || ucmd.reserved) 6100 return -EOPNOTSUPP; 6101 6102 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 6103 in = kvzalloc(inlen, GFP_KERNEL); 6104 if (!in) 6105 return -ENOMEM; 6106 6107 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 6108 6109 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 6110 wq_attr->curr_wq_state : wq->state; 6111 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 6112 wq_attr->wq_state : curr_wq_state; 6113 if (curr_wq_state == IB_WQS_ERR) 6114 curr_wq_state = MLX5_RQC_STATE_ERR; 6115 if (wq_state == IB_WQS_ERR) 6116 wq_state = MLX5_RQC_STATE_ERR; 6117 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 6118 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 6119 MLX5_SET(rqc, rqc, state, wq_state); 6120 6121 if (wq_attr_mask & IB_WQ_FLAGS) { 6122 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6123 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 6124 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6125 mlx5_ib_dbg(dev, "VLAN offloads are not " 6126 "supported\n"); 6127 err = -EOPNOTSUPP; 6128 goto out; 6129 } 6130 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6131 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 6132 MLX5_SET(rqc, rqc, vsd, 6133 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 6134 } 6135 6136 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6137 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 6138 err = -EOPNOTSUPP; 6139 goto out; 6140 } 6141 } 6142 6143 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 6144 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 6145 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6146 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 6147 MLX5_SET(rqc, rqc, counter_set_id, 6148 dev->port->cnts.set_id); 6149 } else 6150 dev_info_once( 6151 &dev->ib_dev.dev, 6152 "Receive WQ counters are not supported on current FW\n"); 6153 } 6154 6155 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 6156 if (!err) 6157 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 6158 6159 out: 6160 kvfree(in); 6161 return err; 6162 } 6163 6164 struct mlx5_ib_drain_cqe { 6165 struct ib_cqe cqe; 6166 struct completion done; 6167 }; 6168 6169 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 6170 { 6171 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 6172 struct mlx5_ib_drain_cqe, 6173 cqe); 6174 6175 complete(&cqe->done); 6176 } 6177 6178 /* This function returns only once the drained WR was completed */ 6179 static void handle_drain_completion(struct ib_cq *cq, 6180 struct mlx5_ib_drain_cqe *sdrain, 6181 struct mlx5_ib_dev *dev) 6182 { 6183 struct mlx5_core_dev *mdev = dev->mdev; 6184 6185 if (cq->poll_ctx == IB_POLL_DIRECT) { 6186 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 6187 ib_process_cq_direct(cq, -1); 6188 return; 6189 } 6190 6191 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6192 struct mlx5_ib_cq *mcq = to_mcq(cq); 6193 bool triggered = false; 6194 unsigned long flags; 6195 6196 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 6197 /* Make sure that the CQ handler won't run if wasn't run yet */ 6198 if (!mcq->mcq.reset_notify_added) 6199 mcq->mcq.reset_notify_added = 1; 6200 else 6201 triggered = true; 6202 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 6203 6204 if (triggered) { 6205 /* Wait for any scheduled/running task to be ended */ 6206 switch (cq->poll_ctx) { 6207 case IB_POLL_SOFTIRQ: 6208 irq_poll_disable(&cq->iop); 6209 irq_poll_enable(&cq->iop); 6210 break; 6211 case IB_POLL_WORKQUEUE: 6212 cancel_work_sync(&cq->work); 6213 break; 6214 default: 6215 WARN_ON_ONCE(1); 6216 } 6217 } 6218 6219 /* Run the CQ handler - this makes sure that the drain WR will 6220 * be processed if wasn't processed yet. 6221 */ 6222 mcq->mcq.comp(&mcq->mcq); 6223 } 6224 6225 wait_for_completion(&sdrain->done); 6226 } 6227 6228 void mlx5_ib_drain_sq(struct ib_qp *qp) 6229 { 6230 struct ib_cq *cq = qp->send_cq; 6231 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6232 struct mlx5_ib_drain_cqe sdrain; 6233 const struct ib_send_wr *bad_swr; 6234 struct ib_rdma_wr swr = { 6235 .wr = { 6236 .next = NULL, 6237 { .wr_cqe = &sdrain.cqe, }, 6238 .opcode = IB_WR_RDMA_WRITE, 6239 }, 6240 }; 6241 int ret; 6242 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6243 struct mlx5_core_dev *mdev = dev->mdev; 6244 6245 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6246 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6247 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6248 return; 6249 } 6250 6251 sdrain.cqe.done = mlx5_ib_drain_qp_done; 6252 init_completion(&sdrain.done); 6253 6254 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); 6255 if (ret) { 6256 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6257 return; 6258 } 6259 6260 handle_drain_completion(cq, &sdrain, dev); 6261 } 6262 6263 void mlx5_ib_drain_rq(struct ib_qp *qp) 6264 { 6265 struct ib_cq *cq = qp->recv_cq; 6266 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6267 struct mlx5_ib_drain_cqe rdrain; 6268 struct ib_recv_wr rwr = {}; 6269 const struct ib_recv_wr *bad_rwr; 6270 int ret; 6271 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6272 struct mlx5_core_dev *mdev = dev->mdev; 6273 6274 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6275 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6276 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6277 return; 6278 } 6279 6280 rwr.wr_cqe = &rdrain.cqe; 6281 rdrain.cqe.done = mlx5_ib_drain_qp_done; 6282 init_completion(&rdrain.done); 6283 6284 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); 6285 if (ret) { 6286 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6287 return; 6288 } 6289 6290 handle_drain_completion(cq, &rdrain, dev); 6291 } 6292