1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 #include "cmd.h" 41 42 /* not supported currently */ 43 static int wq_signature; 44 45 enum { 46 MLX5_IB_ACK_REQ_FREQ = 8, 47 }; 48 49 enum { 50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 52 MLX5_IB_LINK_TYPE_IB = 0, 53 MLX5_IB_LINK_TYPE_ETH = 1 54 }; 55 56 enum { 57 MLX5_IB_SQ_STRIDE = 6, 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 59 }; 60 61 static const u32 mlx5_ib_opcode[] = { 62 [IB_WR_SEND] = MLX5_OPCODE_SEND, 63 [IB_WR_LSO] = MLX5_OPCODE_LSO, 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 76 }; 77 78 struct mlx5_wqe_eth_pad { 79 u8 rsvd0[16]; 80 }; 81 82 enum raw_qp_set_mask_map { 83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 85 }; 86 87 struct mlx5_modify_raw_qp_param { 88 u16 operation; 89 90 u32 set_mask; /* raw_qp_set_mask_map */ 91 92 struct mlx5_rate_limit rl; 93 94 u8 rq_q_ctr_id; 95 u16 port; 96 }; 97 98 static void get_cqs(enum ib_qp_type qp_type, 99 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 100 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 101 102 static int is_qp0(enum ib_qp_type qp_type) 103 { 104 return qp_type == IB_QPT_SMI; 105 } 106 107 static int is_sqp(enum ib_qp_type qp_type) 108 { 109 return is_qp0(qp_type) || is_qp1(qp_type); 110 } 111 112 /** 113 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 114 * to kernel buffer 115 * 116 * @umem: User space memory where the WQ is 117 * @buffer: buffer to copy to 118 * @buflen: buffer length 119 * @wqe_index: index of WQE to copy from 120 * @wq_offset: offset to start of WQ 121 * @wq_wqe_cnt: number of WQEs in WQ 122 * @wq_wqe_shift: log2 of WQE size 123 * @bcnt: number of bytes to copy 124 * @bytes_copied: number of bytes to copy (return value) 125 * 126 * Copies from start of WQE bcnt or less bytes. 127 * Does not gurantee to copy the entire WQE. 128 * 129 * Return: zero on success, or an error code. 130 */ 131 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, 132 void *buffer, 133 u32 buflen, 134 int wqe_index, 135 int wq_offset, 136 int wq_wqe_cnt, 137 int wq_wqe_shift, 138 int bcnt, 139 size_t *bytes_copied) 140 { 141 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 142 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 143 size_t copy_length; 144 int ret; 145 146 /* don't copy more than requested, more than buffer length or 147 * beyond WQ end 148 */ 149 copy_length = min_t(u32, buflen, wq_end - offset); 150 copy_length = min_t(u32, copy_length, bcnt); 151 152 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 153 if (ret) 154 return ret; 155 156 if (!ret && bytes_copied) 157 *bytes_copied = copy_length; 158 159 return 0; 160 } 161 162 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, 163 int wqe_index, 164 void *buffer, 165 int buflen, 166 size_t *bc) 167 { 168 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 169 struct ib_umem *umem = base->ubuffer.umem; 170 struct mlx5_ib_wq *wq = &qp->sq; 171 struct mlx5_wqe_ctrl_seg *ctrl; 172 size_t bytes_copied; 173 size_t bytes_copied2; 174 size_t wqe_length; 175 int ret; 176 int ds; 177 178 if (buflen < sizeof(*ctrl)) 179 return -EINVAL; 180 181 /* at first read as much as possible */ 182 ret = mlx5_ib_read_user_wqe_common(umem, 183 buffer, 184 buflen, 185 wqe_index, 186 wq->offset, 187 wq->wqe_cnt, 188 wq->wqe_shift, 189 buflen, 190 &bytes_copied); 191 if (ret) 192 return ret; 193 194 /* we need at least control segment size to proceed */ 195 if (bytes_copied < sizeof(*ctrl)) 196 return -EINVAL; 197 198 ctrl = buffer; 199 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 200 wqe_length = ds * MLX5_WQE_DS_UNITS; 201 202 /* if we copied enough then we are done */ 203 if (bytes_copied >= wqe_length) { 204 *bc = bytes_copied; 205 return 0; 206 } 207 208 /* otherwise this a wrapped around wqe 209 * so read the remaining bytes starting 210 * from wqe_index 0 211 */ 212 ret = mlx5_ib_read_user_wqe_common(umem, 213 buffer + bytes_copied, 214 buflen - bytes_copied, 215 0, 216 wq->offset, 217 wq->wqe_cnt, 218 wq->wqe_shift, 219 wqe_length - bytes_copied, 220 &bytes_copied2); 221 222 if (ret) 223 return ret; 224 *bc = bytes_copied + bytes_copied2; 225 return 0; 226 } 227 228 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, 229 int wqe_index, 230 void *buffer, 231 int buflen, 232 size_t *bc) 233 { 234 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 235 struct ib_umem *umem = base->ubuffer.umem; 236 struct mlx5_ib_wq *wq = &qp->rq; 237 size_t bytes_copied; 238 int ret; 239 240 ret = mlx5_ib_read_user_wqe_common(umem, 241 buffer, 242 buflen, 243 wqe_index, 244 wq->offset, 245 wq->wqe_cnt, 246 wq->wqe_shift, 247 buflen, 248 &bytes_copied); 249 250 if (ret) 251 return ret; 252 *bc = bytes_copied; 253 return 0; 254 } 255 256 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, 257 int wqe_index, 258 void *buffer, 259 int buflen, 260 size_t *bc) 261 { 262 struct ib_umem *umem = srq->umem; 263 size_t bytes_copied; 264 int ret; 265 266 ret = mlx5_ib_read_user_wqe_common(umem, 267 buffer, 268 buflen, 269 wqe_index, 270 0, 271 srq->msrq.max, 272 srq->msrq.wqe_shift, 273 buflen, 274 &bytes_copied); 275 276 if (ret) 277 return ret; 278 *bc = bytes_copied; 279 return 0; 280 } 281 282 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 283 { 284 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 285 struct ib_event event; 286 287 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 288 /* This event is only valid for trans_qps */ 289 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 290 } 291 292 if (ibqp->event_handler) { 293 event.device = ibqp->device; 294 event.element.qp = ibqp; 295 switch (type) { 296 case MLX5_EVENT_TYPE_PATH_MIG: 297 event.event = IB_EVENT_PATH_MIG; 298 break; 299 case MLX5_EVENT_TYPE_COMM_EST: 300 event.event = IB_EVENT_COMM_EST; 301 break; 302 case MLX5_EVENT_TYPE_SQ_DRAINED: 303 event.event = IB_EVENT_SQ_DRAINED; 304 break; 305 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 306 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 307 break; 308 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 309 event.event = IB_EVENT_QP_FATAL; 310 break; 311 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 312 event.event = IB_EVENT_PATH_MIG_ERR; 313 break; 314 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 315 event.event = IB_EVENT_QP_REQ_ERR; 316 break; 317 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 318 event.event = IB_EVENT_QP_ACCESS_ERR; 319 break; 320 default: 321 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 322 return; 323 } 324 325 ibqp->event_handler(&event, ibqp->qp_context); 326 } 327 } 328 329 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 330 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 331 { 332 int wqe_size; 333 int wq_size; 334 335 /* Sanity check RQ size before proceeding */ 336 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 337 return -EINVAL; 338 339 if (!has_rq) { 340 qp->rq.max_gs = 0; 341 qp->rq.wqe_cnt = 0; 342 qp->rq.wqe_shift = 0; 343 cap->max_recv_wr = 0; 344 cap->max_recv_sge = 0; 345 } else { 346 if (ucmd) { 347 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 348 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 349 return -EINVAL; 350 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 351 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 352 return -EINVAL; 353 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 354 qp->rq.max_post = qp->rq.wqe_cnt; 355 } else { 356 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 357 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 358 wqe_size = roundup_pow_of_two(wqe_size); 359 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 360 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 361 qp->rq.wqe_cnt = wq_size / wqe_size; 362 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 363 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 364 wqe_size, 365 MLX5_CAP_GEN(dev->mdev, 366 max_wqe_sz_rq)); 367 return -EINVAL; 368 } 369 qp->rq.wqe_shift = ilog2(wqe_size); 370 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 371 qp->rq.max_post = qp->rq.wqe_cnt; 372 } 373 } 374 375 return 0; 376 } 377 378 static int sq_overhead(struct ib_qp_init_attr *attr) 379 { 380 int size = 0; 381 382 switch (attr->qp_type) { 383 case IB_QPT_XRC_INI: 384 size += sizeof(struct mlx5_wqe_xrc_seg); 385 /* fall through */ 386 case IB_QPT_RC: 387 size += sizeof(struct mlx5_wqe_ctrl_seg) + 388 max(sizeof(struct mlx5_wqe_atomic_seg) + 389 sizeof(struct mlx5_wqe_raddr_seg), 390 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 391 sizeof(struct mlx5_mkey_seg) + 392 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 393 MLX5_IB_UMR_OCTOWORD); 394 break; 395 396 case IB_QPT_XRC_TGT: 397 return 0; 398 399 case IB_QPT_UC: 400 size += sizeof(struct mlx5_wqe_ctrl_seg) + 401 max(sizeof(struct mlx5_wqe_raddr_seg), 402 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 403 sizeof(struct mlx5_mkey_seg)); 404 break; 405 406 case IB_QPT_UD: 407 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 408 size += sizeof(struct mlx5_wqe_eth_pad) + 409 sizeof(struct mlx5_wqe_eth_seg); 410 /* fall through */ 411 case IB_QPT_SMI: 412 case MLX5_IB_QPT_HW_GSI: 413 size += sizeof(struct mlx5_wqe_ctrl_seg) + 414 sizeof(struct mlx5_wqe_datagram_seg); 415 break; 416 417 case MLX5_IB_QPT_REG_UMR: 418 size += sizeof(struct mlx5_wqe_ctrl_seg) + 419 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 420 sizeof(struct mlx5_mkey_seg); 421 break; 422 423 default: 424 return -EINVAL; 425 } 426 427 return size; 428 } 429 430 static int calc_send_wqe(struct ib_qp_init_attr *attr) 431 { 432 int inl_size = 0; 433 int size; 434 435 size = sq_overhead(attr); 436 if (size < 0) 437 return size; 438 439 if (attr->cap.max_inline_data) { 440 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 441 attr->cap.max_inline_data; 442 } 443 444 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 445 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 446 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 447 return MLX5_SIG_WQE_SIZE; 448 else 449 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 450 } 451 452 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 453 { 454 int max_sge; 455 456 if (attr->qp_type == IB_QPT_RC) 457 max_sge = (min_t(int, wqe_size, 512) - 458 sizeof(struct mlx5_wqe_ctrl_seg) - 459 sizeof(struct mlx5_wqe_raddr_seg)) / 460 sizeof(struct mlx5_wqe_data_seg); 461 else if (attr->qp_type == IB_QPT_XRC_INI) 462 max_sge = (min_t(int, wqe_size, 512) - 463 sizeof(struct mlx5_wqe_ctrl_seg) - 464 sizeof(struct mlx5_wqe_xrc_seg) - 465 sizeof(struct mlx5_wqe_raddr_seg)) / 466 sizeof(struct mlx5_wqe_data_seg); 467 else 468 max_sge = (wqe_size - sq_overhead(attr)) / 469 sizeof(struct mlx5_wqe_data_seg); 470 471 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 472 sizeof(struct mlx5_wqe_data_seg)); 473 } 474 475 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 476 struct mlx5_ib_qp *qp) 477 { 478 int wqe_size; 479 int wq_size; 480 481 if (!attr->cap.max_send_wr) 482 return 0; 483 484 wqe_size = calc_send_wqe(attr); 485 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 486 if (wqe_size < 0) 487 return wqe_size; 488 489 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 490 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 491 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 492 return -EINVAL; 493 } 494 495 qp->max_inline_data = wqe_size - sq_overhead(attr) - 496 sizeof(struct mlx5_wqe_inline_seg); 497 attr->cap.max_inline_data = qp->max_inline_data; 498 499 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 500 qp->signature_en = true; 501 502 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 503 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 504 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 505 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 506 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 507 qp->sq.wqe_cnt, 508 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 509 return -ENOMEM; 510 } 511 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 512 qp->sq.max_gs = get_send_sge(attr, wqe_size); 513 if (qp->sq.max_gs < attr->cap.max_send_sge) 514 return -ENOMEM; 515 516 attr->cap.max_send_sge = qp->sq.max_gs; 517 qp->sq.max_post = wq_size / wqe_size; 518 attr->cap.max_send_wr = qp->sq.max_post; 519 520 return wq_size; 521 } 522 523 static int set_user_buf_size(struct mlx5_ib_dev *dev, 524 struct mlx5_ib_qp *qp, 525 struct mlx5_ib_create_qp *ucmd, 526 struct mlx5_ib_qp_base *base, 527 struct ib_qp_init_attr *attr) 528 { 529 int desc_sz = 1 << qp->sq.wqe_shift; 530 531 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 532 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 533 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 534 return -EINVAL; 535 } 536 537 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 538 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 539 ucmd->sq_wqe_count); 540 return -EINVAL; 541 } 542 543 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 544 545 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 546 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 547 qp->sq.wqe_cnt, 548 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 549 return -EINVAL; 550 } 551 552 if (attr->qp_type == IB_QPT_RAW_PACKET || 553 qp->flags & MLX5_IB_QP_UNDERLAY) { 554 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 555 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 556 } else { 557 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 558 (qp->sq.wqe_cnt << 6); 559 } 560 561 return 0; 562 } 563 564 static int qp_has_rq(struct ib_qp_init_attr *attr) 565 { 566 if (attr->qp_type == IB_QPT_XRC_INI || 567 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 568 attr->qp_type == MLX5_IB_QPT_REG_UMR || 569 !attr->cap.max_recv_wr) 570 return 0; 571 572 return 1; 573 } 574 575 enum { 576 /* this is the first blue flame register in the array of bfregs assigned 577 * to a processes. Since we do not use it for blue flame but rather 578 * regular 64 bit doorbells, we do not need a lock for maintaiing 579 * "odd/even" order 580 */ 581 NUM_NON_BLUE_FLAME_BFREGS = 1, 582 }; 583 584 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 585 { 586 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 587 } 588 589 static int num_med_bfreg(struct mlx5_ib_dev *dev, 590 struct mlx5_bfreg_info *bfregi) 591 { 592 int n; 593 594 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 595 NUM_NON_BLUE_FLAME_BFREGS; 596 597 return n >= 0 ? n : 0; 598 } 599 600 static int first_med_bfreg(struct mlx5_ib_dev *dev, 601 struct mlx5_bfreg_info *bfregi) 602 { 603 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 604 } 605 606 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 607 struct mlx5_bfreg_info *bfregi) 608 { 609 int med; 610 611 med = num_med_bfreg(dev, bfregi); 612 return ++med; 613 } 614 615 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 616 struct mlx5_bfreg_info *bfregi) 617 { 618 int i; 619 620 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 621 if (!bfregi->count[i]) { 622 bfregi->count[i]++; 623 return i; 624 } 625 } 626 627 return -ENOMEM; 628 } 629 630 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 631 struct mlx5_bfreg_info *bfregi) 632 { 633 int minidx = first_med_bfreg(dev, bfregi); 634 int i; 635 636 if (minidx < 0) 637 return minidx; 638 639 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 640 if (bfregi->count[i] < bfregi->count[minidx]) 641 minidx = i; 642 if (!bfregi->count[minidx]) 643 break; 644 } 645 646 bfregi->count[minidx]++; 647 return minidx; 648 } 649 650 static int alloc_bfreg(struct mlx5_ib_dev *dev, 651 struct mlx5_bfreg_info *bfregi) 652 { 653 int bfregn = -ENOMEM; 654 655 mutex_lock(&bfregi->lock); 656 if (bfregi->ver >= 2) { 657 bfregn = alloc_high_class_bfreg(dev, bfregi); 658 if (bfregn < 0) 659 bfregn = alloc_med_class_bfreg(dev, bfregi); 660 } 661 662 if (bfregn < 0) { 663 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 664 bfregn = 0; 665 bfregi->count[bfregn]++; 666 } 667 mutex_unlock(&bfregi->lock); 668 669 return bfregn; 670 } 671 672 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 673 { 674 mutex_lock(&bfregi->lock); 675 bfregi->count[bfregn]--; 676 mutex_unlock(&bfregi->lock); 677 } 678 679 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 680 { 681 switch (state) { 682 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 683 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 684 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 685 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 686 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 687 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 688 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 689 default: return -1; 690 } 691 } 692 693 static int to_mlx5_st(enum ib_qp_type type) 694 { 695 switch (type) { 696 case IB_QPT_RC: return MLX5_QP_ST_RC; 697 case IB_QPT_UC: return MLX5_QP_ST_UC; 698 case IB_QPT_UD: return MLX5_QP_ST_UD; 699 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 700 case IB_QPT_XRC_INI: 701 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 702 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 703 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 704 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 705 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 706 case IB_QPT_RAW_PACKET: 707 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 708 case IB_QPT_MAX: 709 default: return -EINVAL; 710 } 711 } 712 713 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 714 struct mlx5_ib_cq *recv_cq); 715 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 716 struct mlx5_ib_cq *recv_cq); 717 718 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 719 struct mlx5_bfreg_info *bfregi, u32 bfregn, 720 bool dyn_bfreg) 721 { 722 unsigned int bfregs_per_sys_page; 723 u32 index_of_sys_page; 724 u32 offset; 725 726 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 727 MLX5_NON_FP_BFREGS_PER_UAR; 728 index_of_sys_page = bfregn / bfregs_per_sys_page; 729 730 if (dyn_bfreg) { 731 index_of_sys_page += bfregi->num_static_sys_pages; 732 733 if (index_of_sys_page >= bfregi->num_sys_pages) 734 return -EINVAL; 735 736 if (bfregn > bfregi->num_dyn_bfregs || 737 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 738 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 739 return -EINVAL; 740 } 741 } 742 743 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 744 return bfregi->sys_pages[index_of_sys_page] + offset; 745 } 746 747 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, 748 unsigned long addr, size_t size, 749 struct ib_umem **umem, int *npages, int *page_shift, 750 int *ncont, u32 *offset) 751 { 752 int err; 753 754 *umem = ib_umem_get(udata, addr, size, 0, 0); 755 if (IS_ERR(*umem)) { 756 mlx5_ib_dbg(dev, "umem_get failed\n"); 757 return PTR_ERR(*umem); 758 } 759 760 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 761 762 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 763 if (err) { 764 mlx5_ib_warn(dev, "bad offset\n"); 765 goto err_umem; 766 } 767 768 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 769 addr, size, *npages, *page_shift, *ncont, *offset); 770 771 return 0; 772 773 err_umem: 774 ib_umem_release(*umem); 775 *umem = NULL; 776 777 return err; 778 } 779 780 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 781 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 782 { 783 struct mlx5_ib_ucontext *context = 784 rdma_udata_to_drv_context( 785 udata, 786 struct mlx5_ib_ucontext, 787 ibucontext); 788 789 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 790 atomic_dec(&dev->delay_drop.rqs_cnt); 791 792 mlx5_ib_db_unmap_user(context, &rwq->db); 793 if (rwq->umem) 794 ib_umem_release(rwq->umem); 795 } 796 797 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 798 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 799 struct mlx5_ib_create_wq *ucmd) 800 { 801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 802 udata, struct mlx5_ib_ucontext, ibucontext); 803 int page_shift = 0; 804 int npages; 805 u32 offset = 0; 806 int ncont = 0; 807 int err; 808 809 if (!ucmd->buf_addr) 810 return -EINVAL; 811 812 rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0); 813 if (IS_ERR(rwq->umem)) { 814 mlx5_ib_dbg(dev, "umem_get failed\n"); 815 err = PTR_ERR(rwq->umem); 816 return err; 817 } 818 819 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 820 &ncont, NULL); 821 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 822 &rwq->rq_page_offset); 823 if (err) { 824 mlx5_ib_warn(dev, "bad offset\n"); 825 goto err_umem; 826 } 827 828 rwq->rq_num_pas = ncont; 829 rwq->page_shift = page_shift; 830 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 831 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 832 833 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 834 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 835 npages, page_shift, ncont, offset); 836 837 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 838 if (err) { 839 mlx5_ib_dbg(dev, "map failed\n"); 840 goto err_umem; 841 } 842 843 rwq->create_type = MLX5_WQ_USER; 844 return 0; 845 846 err_umem: 847 ib_umem_release(rwq->umem); 848 return err; 849 } 850 851 static int adjust_bfregn(struct mlx5_ib_dev *dev, 852 struct mlx5_bfreg_info *bfregi, int bfregn) 853 { 854 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 855 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 856 } 857 858 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 859 struct mlx5_ib_qp *qp, struct ib_udata *udata, 860 struct ib_qp_init_attr *attr, 861 u32 **in, 862 struct mlx5_ib_create_qp_resp *resp, int *inlen, 863 struct mlx5_ib_qp_base *base) 864 { 865 struct mlx5_ib_ucontext *context; 866 struct mlx5_ib_create_qp ucmd; 867 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 868 int page_shift = 0; 869 int uar_index = 0; 870 int npages; 871 u32 offset = 0; 872 int bfregn; 873 int ncont = 0; 874 __be64 *pas; 875 void *qpc; 876 int err; 877 u16 uid; 878 879 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 880 if (err) { 881 mlx5_ib_dbg(dev, "copy failed\n"); 882 return err; 883 } 884 885 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 886 ibucontext); 887 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 888 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 889 ucmd.bfreg_index, true); 890 if (uar_index < 0) 891 return uar_index; 892 893 bfregn = MLX5_IB_INVALID_BFREG; 894 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 895 /* 896 * TBD: should come from the verbs when we have the API 897 */ 898 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 899 bfregn = MLX5_CROSS_CHANNEL_BFREG; 900 } 901 else { 902 bfregn = alloc_bfreg(dev, &context->bfregi); 903 if (bfregn < 0) 904 return bfregn; 905 } 906 907 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 908 if (bfregn != MLX5_IB_INVALID_BFREG) 909 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 910 false); 911 912 qp->rq.offset = 0; 913 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 914 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 915 916 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 917 if (err) 918 goto err_bfreg; 919 920 if (ucmd.buf_addr && ubuffer->buf_size) { 921 ubuffer->buf_addr = ucmd.buf_addr; 922 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, 923 ubuffer->buf_size, &ubuffer->umem, 924 &npages, &page_shift, &ncont, &offset); 925 if (err) 926 goto err_bfreg; 927 } else { 928 ubuffer->umem = NULL; 929 } 930 931 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 932 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 933 *in = kvzalloc(*inlen, GFP_KERNEL); 934 if (!*in) { 935 err = -ENOMEM; 936 goto err_umem; 937 } 938 939 uid = (attr->qp_type != IB_QPT_XRC_TGT && 940 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 941 MLX5_SET(create_qp_in, *in, uid, uid); 942 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 943 if (ubuffer->umem) 944 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 945 946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 947 948 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 949 MLX5_SET(qpc, qpc, page_offset, offset); 950 951 MLX5_SET(qpc, qpc, uar_page, uar_index); 952 if (bfregn != MLX5_IB_INVALID_BFREG) 953 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 954 else 955 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 956 qp->bfregn = bfregn; 957 958 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db); 959 if (err) { 960 mlx5_ib_dbg(dev, "map failed\n"); 961 goto err_free; 962 } 963 964 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 965 if (err) { 966 mlx5_ib_dbg(dev, "copy failed\n"); 967 goto err_unmap; 968 } 969 qp->create_type = MLX5_QP_USER; 970 971 return 0; 972 973 err_unmap: 974 mlx5_ib_db_unmap_user(context, &qp->db); 975 976 err_free: 977 kvfree(*in); 978 979 err_umem: 980 if (ubuffer->umem) 981 ib_umem_release(ubuffer->umem); 982 983 err_bfreg: 984 if (bfregn != MLX5_IB_INVALID_BFREG) 985 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 986 return err; 987 } 988 989 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 990 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base, 991 struct ib_udata *udata) 992 { 993 struct mlx5_ib_ucontext *context = 994 rdma_udata_to_drv_context( 995 udata, 996 struct mlx5_ib_ucontext, 997 ibucontext); 998 999 mlx5_ib_db_unmap_user(context, &qp->db); 1000 if (base->ubuffer.umem) 1001 ib_umem_release(base->ubuffer.umem); 1002 1003 /* 1004 * Free only the BFREGs which are handled by the kernel. 1005 * BFREGs of UARs allocated dynamically are handled by user. 1006 */ 1007 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1008 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1009 } 1010 1011 /* get_sq_edge - Get the next nearby edge. 1012 * 1013 * An 'edge' is defined as the first following address after the end 1014 * of the fragment or the SQ. Accordingly, during the WQE construction 1015 * which repetitively increases the pointer to write the next data, it 1016 * simply should check if it gets to an edge. 1017 * 1018 * @sq - SQ buffer. 1019 * @idx - Stride index in the SQ buffer. 1020 * 1021 * Return: 1022 * The new edge. 1023 */ 1024 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) 1025 { 1026 void *fragment_end; 1027 1028 fragment_end = mlx5_frag_buf_get_wqe 1029 (&sq->fbc, 1030 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); 1031 1032 return fragment_end + MLX5_SEND_WQE_BB; 1033 } 1034 1035 static int create_kernel_qp(struct mlx5_ib_dev *dev, 1036 struct ib_qp_init_attr *init_attr, 1037 struct mlx5_ib_qp *qp, 1038 u32 **in, int *inlen, 1039 struct mlx5_ib_qp_base *base) 1040 { 1041 int uar_index; 1042 void *qpc; 1043 int err; 1044 1045 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 1046 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 1047 IB_QP_CREATE_IPOIB_UD_LSO | 1048 IB_QP_CREATE_NETIF_QP | 1049 mlx5_ib_create_qp_sqpn_qp1())) 1050 return -EINVAL; 1051 1052 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1053 qp->bf.bfreg = &dev->fp_bfreg; 1054 else 1055 qp->bf.bfreg = &dev->bfreg; 1056 1057 /* We need to divide by two since each register is comprised of 1058 * two buffers of identical size, namely odd and even 1059 */ 1060 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1061 uar_index = qp->bf.bfreg->index; 1062 1063 err = calc_sq_size(dev, init_attr, qp); 1064 if (err < 0) { 1065 mlx5_ib_dbg(dev, "err %d\n", err); 1066 return err; 1067 } 1068 1069 qp->rq.offset = 0; 1070 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1071 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1072 1073 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1074 &qp->buf, dev->mdev->priv.numa_node); 1075 if (err) { 1076 mlx5_ib_dbg(dev, "err %d\n", err); 1077 return err; 1078 } 1079 1080 if (qp->rq.wqe_cnt) 1081 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1082 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1083 1084 if (qp->sq.wqe_cnt) { 1085 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1086 MLX5_SEND_WQE_BB; 1087 mlx5_init_fbc_offset(qp->buf.frags + 1088 (qp->sq.offset / PAGE_SIZE), 1089 ilog2(MLX5_SEND_WQE_BB), 1090 ilog2(qp->sq.wqe_cnt), 1091 sq_strides_offset, &qp->sq.fbc); 1092 1093 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1094 } 1095 1096 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1097 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1098 *in = kvzalloc(*inlen, GFP_KERNEL); 1099 if (!*in) { 1100 err = -ENOMEM; 1101 goto err_buf; 1102 } 1103 1104 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1105 MLX5_SET(qpc, qpc, uar_page, uar_index); 1106 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1107 1108 /* Set "fast registration enabled" for all kernel QPs */ 1109 MLX5_SET(qpc, qpc, fre, 1); 1110 MLX5_SET(qpc, qpc, rlky, 1); 1111 1112 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 1113 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1114 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1115 } 1116 1117 mlx5_fill_page_frag_array(&qp->buf, 1118 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1119 *in, pas)); 1120 1121 err = mlx5_db_alloc(dev->mdev, &qp->db); 1122 if (err) { 1123 mlx5_ib_dbg(dev, "err %d\n", err); 1124 goto err_free; 1125 } 1126 1127 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1128 sizeof(*qp->sq.wrid), GFP_KERNEL); 1129 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1130 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1131 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1132 sizeof(*qp->rq.wrid), GFP_KERNEL); 1133 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1134 sizeof(*qp->sq.w_list), GFP_KERNEL); 1135 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1136 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1137 1138 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1139 !qp->sq.w_list || !qp->sq.wqe_head) { 1140 err = -ENOMEM; 1141 goto err_wrid; 1142 } 1143 qp->create_type = MLX5_QP_KERNEL; 1144 1145 return 0; 1146 1147 err_wrid: 1148 kvfree(qp->sq.wqe_head); 1149 kvfree(qp->sq.w_list); 1150 kvfree(qp->sq.wrid); 1151 kvfree(qp->sq.wr_data); 1152 kvfree(qp->rq.wrid); 1153 mlx5_db_free(dev->mdev, &qp->db); 1154 1155 err_free: 1156 kvfree(*in); 1157 1158 err_buf: 1159 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1160 return err; 1161 } 1162 1163 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1164 { 1165 kvfree(qp->sq.wqe_head); 1166 kvfree(qp->sq.w_list); 1167 kvfree(qp->sq.wrid); 1168 kvfree(qp->sq.wr_data); 1169 kvfree(qp->rq.wrid); 1170 mlx5_db_free(dev->mdev, &qp->db); 1171 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1172 } 1173 1174 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1175 { 1176 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1177 (attr->qp_type == MLX5_IB_QPT_DCI) || 1178 (attr->qp_type == IB_QPT_XRC_INI)) 1179 return MLX5_SRQ_RQ; 1180 else if (!qp->has_rq) 1181 return MLX5_ZERO_LEN_RQ; 1182 else 1183 return MLX5_NON_ZERO_RQ; 1184 } 1185 1186 static int is_connected(enum ib_qp_type qp_type) 1187 { 1188 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || 1189 qp_type == MLX5_IB_QPT_DCI) 1190 return 1; 1191 1192 return 0; 1193 } 1194 1195 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1196 struct mlx5_ib_qp *qp, 1197 struct mlx5_ib_sq *sq, u32 tdn, 1198 struct ib_pd *pd) 1199 { 1200 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1201 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1202 1203 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1204 MLX5_SET(tisc, tisc, transport_domain, tdn); 1205 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1206 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1207 1208 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1209 } 1210 1211 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1212 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1213 { 1214 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1215 } 1216 1217 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1218 { 1219 if (sq->flow_rule) 1220 mlx5_del_flow_rules(sq->flow_rule); 1221 sq->flow_rule = NULL; 1222 } 1223 1224 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1225 struct ib_udata *udata, 1226 struct mlx5_ib_sq *sq, void *qpin, 1227 struct ib_pd *pd) 1228 { 1229 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1230 __be64 *pas; 1231 void *in; 1232 void *sqc; 1233 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1234 void *wq; 1235 int inlen; 1236 int err; 1237 int page_shift = 0; 1238 int npages; 1239 int ncont = 0; 1240 u32 offset = 0; 1241 1242 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, 1243 &sq->ubuffer.umem, &npages, &page_shift, &ncont, 1244 &offset); 1245 if (err) 1246 return err; 1247 1248 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1249 in = kvzalloc(inlen, GFP_KERNEL); 1250 if (!in) { 1251 err = -ENOMEM; 1252 goto err_umem; 1253 } 1254 1255 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1256 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1257 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1258 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1259 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1260 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1261 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1262 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1263 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1264 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1265 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1266 MLX5_CAP_ETH(dev->mdev, swp)) 1267 MLX5_SET(sqc, sqc, allow_swp, 1); 1268 1269 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1270 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1271 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1272 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1273 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1274 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1275 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1276 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1277 MLX5_SET(wq, wq, page_offset, offset); 1278 1279 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1280 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1281 1282 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1283 1284 kvfree(in); 1285 1286 if (err) 1287 goto err_umem; 1288 1289 return 0; 1290 1291 err_umem: 1292 ib_umem_release(sq->ubuffer.umem); 1293 sq->ubuffer.umem = NULL; 1294 1295 return err; 1296 } 1297 1298 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1299 struct mlx5_ib_sq *sq) 1300 { 1301 destroy_flow_rule_vport_sq(sq); 1302 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1303 ib_umem_release(sq->ubuffer.umem); 1304 } 1305 1306 static size_t get_rq_pas_size(void *qpc) 1307 { 1308 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1309 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1310 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1311 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1312 u32 po_quanta = 1 << (log_page_size - 6); 1313 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1314 u32 page_size = 1 << log_page_size; 1315 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1316 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1317 1318 return rq_num_pas * sizeof(u64); 1319 } 1320 1321 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1322 struct mlx5_ib_rq *rq, void *qpin, 1323 size_t qpinlen, struct ib_pd *pd) 1324 { 1325 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1326 __be64 *pas; 1327 __be64 *qp_pas; 1328 void *in; 1329 void *rqc; 1330 void *wq; 1331 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1332 size_t rq_pas_size = get_rq_pas_size(qpc); 1333 size_t inlen; 1334 int err; 1335 1336 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1337 return -EINVAL; 1338 1339 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1340 in = kvzalloc(inlen, GFP_KERNEL); 1341 if (!in) 1342 return -ENOMEM; 1343 1344 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1345 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1346 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1347 MLX5_SET(rqc, rqc, vsd, 1); 1348 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1349 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1350 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1351 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1352 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1353 1354 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1355 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1356 1357 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1358 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1359 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1360 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1361 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1362 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1363 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1364 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1365 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1366 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1367 1368 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1369 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1370 memcpy(pas, qp_pas, rq_pas_size); 1371 1372 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1373 1374 kvfree(in); 1375 1376 return err; 1377 } 1378 1379 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1380 struct mlx5_ib_rq *rq) 1381 { 1382 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1383 } 1384 1385 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1386 { 1387 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1388 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1389 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1390 } 1391 1392 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1393 struct mlx5_ib_rq *rq, 1394 u32 qp_flags_en, 1395 struct ib_pd *pd) 1396 { 1397 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1398 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1399 mlx5_ib_disable_lb(dev, false, true); 1400 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1401 } 1402 1403 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1404 struct mlx5_ib_rq *rq, u32 tdn, 1405 u32 *qp_flags_en, 1406 struct ib_pd *pd, 1407 u32 *out, int outlen) 1408 { 1409 u8 lb_flag = 0; 1410 u32 *in; 1411 void *tirc; 1412 int inlen; 1413 int err; 1414 1415 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1416 in = kvzalloc(inlen, GFP_KERNEL); 1417 if (!in) 1418 return -ENOMEM; 1419 1420 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1421 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1422 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1423 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1424 MLX5_SET(tirc, tirc, transport_domain, tdn); 1425 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1426 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1427 1428 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1429 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1430 1431 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1432 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1433 1434 if (dev->is_rep) { 1435 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1436 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1437 } 1438 1439 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1440 1441 err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen); 1442 1443 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1444 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1445 err = mlx5_ib_enable_lb(dev, false, true); 1446 1447 if (err) 1448 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1449 } 1450 kvfree(in); 1451 1452 return err; 1453 } 1454 1455 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1456 u32 *in, size_t inlen, 1457 struct ib_pd *pd, 1458 struct ib_udata *udata, 1459 struct mlx5_ib_create_qp_resp *resp) 1460 { 1461 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1462 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1463 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1464 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1465 udata, struct mlx5_ib_ucontext, ibucontext); 1466 int err; 1467 u32 tdn = mucontext->tdn; 1468 u16 uid = to_mpd(pd)->uid; 1469 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1470 1471 if (qp->sq.wqe_cnt) { 1472 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1473 if (err) 1474 return err; 1475 1476 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); 1477 if (err) 1478 goto err_destroy_tis; 1479 1480 if (uid) { 1481 resp->tisn = sq->tisn; 1482 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1483 resp->sqn = sq->base.mqp.qpn; 1484 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1485 } 1486 1487 sq->base.container_mibqp = qp; 1488 sq->base.mqp.event = mlx5_ib_qp_event; 1489 } 1490 1491 if (qp->rq.wqe_cnt) { 1492 rq->base.container_mibqp = qp; 1493 1494 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1495 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1496 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1497 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1498 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1499 if (err) 1500 goto err_destroy_sq; 1501 1502 err = create_raw_packet_qp_tir( 1503 dev, rq, tdn, &qp->flags_en, pd, out, 1504 MLX5_ST_SZ_BYTES(create_tir_out)); 1505 if (err) 1506 goto err_destroy_rq; 1507 1508 if (uid) { 1509 resp->rqn = rq->base.mqp.qpn; 1510 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1511 resp->tirn = rq->tirn; 1512 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1513 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1514 resp->tir_icm_addr = MLX5_GET( 1515 create_tir_out, out, icm_address_31_0); 1516 resp->tir_icm_addr |= 1517 (u64)MLX5_GET(create_tir_out, out, 1518 icm_address_39_32) 1519 << 32; 1520 resp->tir_icm_addr |= 1521 (u64)MLX5_GET(create_tir_out, out, 1522 icm_address_63_40) 1523 << 40; 1524 resp->comp_mask |= 1525 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1526 } 1527 } 1528 } 1529 1530 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1531 rq->base.mqp.qpn; 1532 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1533 if (err) 1534 goto err_destroy_tir; 1535 1536 return 0; 1537 1538 err_destroy_tir: 1539 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); 1540 err_destroy_rq: 1541 destroy_raw_packet_qp_rq(dev, rq); 1542 err_destroy_sq: 1543 if (!qp->sq.wqe_cnt) 1544 return err; 1545 destroy_raw_packet_qp_sq(dev, sq); 1546 err_destroy_tis: 1547 destroy_raw_packet_qp_tis(dev, sq, pd); 1548 1549 return err; 1550 } 1551 1552 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1553 struct mlx5_ib_qp *qp) 1554 { 1555 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1556 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1557 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1558 1559 if (qp->rq.wqe_cnt) { 1560 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1561 destroy_raw_packet_qp_rq(dev, rq); 1562 } 1563 1564 if (qp->sq.wqe_cnt) { 1565 destroy_raw_packet_qp_sq(dev, sq); 1566 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1567 } 1568 } 1569 1570 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1571 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1572 { 1573 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1574 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1575 1576 sq->sq = &qp->sq; 1577 rq->rq = &qp->rq; 1578 sq->doorbell = &qp->db; 1579 rq->doorbell = &qp->db; 1580 } 1581 1582 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1583 { 1584 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1585 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1586 mlx5_ib_disable_lb(dev, false, true); 1587 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1588 to_mpd(qp->ibqp.pd)->uid); 1589 } 1590 1591 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1592 struct ib_pd *pd, 1593 struct ib_qp_init_attr *init_attr, 1594 struct ib_udata *udata) 1595 { 1596 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1597 udata, struct mlx5_ib_ucontext, ibucontext); 1598 struct mlx5_ib_create_qp_resp resp = {}; 1599 int inlen; 1600 int outlen; 1601 int err; 1602 u32 *in; 1603 u32 *out; 1604 void *tirc; 1605 void *hfso; 1606 u32 selected_fields = 0; 1607 u32 outer_l4; 1608 size_t min_resp_len; 1609 u32 tdn = mucontext->tdn; 1610 struct mlx5_ib_create_qp_rss ucmd = {}; 1611 size_t required_cmd_sz; 1612 u8 lb_flag = 0; 1613 1614 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1615 return -EOPNOTSUPP; 1616 1617 if (init_attr->create_flags || init_attr->send_cq) 1618 return -EINVAL; 1619 1620 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1621 if (udata->outlen < min_resp_len) 1622 return -EINVAL; 1623 1624 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1625 if (udata->inlen < required_cmd_sz) { 1626 mlx5_ib_dbg(dev, "invalid inlen\n"); 1627 return -EINVAL; 1628 } 1629 1630 if (udata->inlen > sizeof(ucmd) && 1631 !ib_is_udata_cleared(udata, sizeof(ucmd), 1632 udata->inlen - sizeof(ucmd))) { 1633 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1634 return -EOPNOTSUPP; 1635 } 1636 1637 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1638 mlx5_ib_dbg(dev, "copy failed\n"); 1639 return -EFAULT; 1640 } 1641 1642 if (ucmd.comp_mask) { 1643 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1644 return -EOPNOTSUPP; 1645 } 1646 1647 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1648 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1649 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { 1650 mlx5_ib_dbg(dev, "invalid flags\n"); 1651 return -EOPNOTSUPP; 1652 } 1653 1654 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1655 !tunnel_offload_supported(dev->mdev)) { 1656 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1657 return -EOPNOTSUPP; 1658 } 1659 1660 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1661 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1662 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1663 return -EOPNOTSUPP; 1664 } 1665 1666 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) { 1667 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1668 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1669 } 1670 1671 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1672 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1673 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1674 } 1675 1676 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1677 if (err) { 1678 mlx5_ib_dbg(dev, "copy failed\n"); 1679 return -EINVAL; 1680 } 1681 1682 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1683 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1684 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1685 if (!in) 1686 return -ENOMEM; 1687 1688 out = in + MLX5_ST_SZ_DW(create_tir_in); 1689 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1690 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1691 MLX5_SET(tirc, tirc, disp_type, 1692 MLX5_TIRC_DISP_TYPE_INDIRECT); 1693 MLX5_SET(tirc, tirc, indirect_table, 1694 init_attr->rwq_ind_tbl->ind_tbl_num); 1695 MLX5_SET(tirc, tirc, transport_domain, tdn); 1696 1697 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1698 1699 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1700 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1701 1702 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1703 1704 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1705 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1706 else 1707 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1708 1709 switch (ucmd.rx_hash_function) { 1710 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1711 { 1712 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1713 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1714 1715 if (len != ucmd.rx_key_len) { 1716 err = -EINVAL; 1717 goto err; 1718 } 1719 1720 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1721 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1722 memcpy(rss_key, ucmd.rx_hash_key, len); 1723 break; 1724 } 1725 default: 1726 err = -EOPNOTSUPP; 1727 goto err; 1728 } 1729 1730 if (!ucmd.rx_hash_fields_mask) { 1731 /* special case when this TIR serves as steering entry without hashing */ 1732 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1733 goto create_tir; 1734 err = -EINVAL; 1735 goto err; 1736 } 1737 1738 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1739 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1740 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1741 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1742 err = -EINVAL; 1743 goto err; 1744 } 1745 1746 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1747 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1748 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1749 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1750 MLX5_L3_PROT_TYPE_IPV4); 1751 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1752 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1753 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1754 MLX5_L3_PROT_TYPE_IPV6); 1755 1756 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1757 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1758 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1759 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1760 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1761 1762 /* Check that only one l4 protocol is set */ 1763 if (outer_l4 & (outer_l4 - 1)) { 1764 err = -EINVAL; 1765 goto err; 1766 } 1767 1768 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1769 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1770 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1771 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1772 MLX5_L4_PROT_TYPE_TCP); 1773 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1774 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1775 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1776 MLX5_L4_PROT_TYPE_UDP); 1777 1778 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1779 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1780 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1781 1782 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1783 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1784 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1785 1786 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1787 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1788 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1789 1790 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1791 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1792 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1793 1794 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1795 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1796 1797 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1798 1799 create_tir: 1800 err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen); 1801 1802 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1803 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1804 err = mlx5_ib_enable_lb(dev, false, true); 1805 1806 if (err) 1807 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1808 to_mpd(pd)->uid); 1809 } 1810 1811 if (err) 1812 goto err; 1813 1814 if (mucontext->devx_uid) { 1815 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1816 resp.tirn = qp->rss_qp.tirn; 1817 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1818 resp.tir_icm_addr = 1819 MLX5_GET(create_tir_out, out, icm_address_31_0); 1820 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, 1821 icm_address_39_32) 1822 << 32; 1823 resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, 1824 icm_address_63_40) 1825 << 40; 1826 resp.comp_mask |= 1827 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1828 } 1829 } 1830 1831 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1832 if (err) 1833 goto err_copy; 1834 1835 kvfree(in); 1836 /* qpn is reserved for that QP */ 1837 qp->trans_qp.base.mqp.qpn = 0; 1838 qp->flags |= MLX5_IB_QP_RSS; 1839 return 0; 1840 1841 err_copy: 1842 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); 1843 err: 1844 kvfree(in); 1845 return err; 1846 } 1847 1848 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, 1849 void *qpc) 1850 { 1851 int rcqe_sz; 1852 1853 if (init_attr->qp_type == MLX5_IB_QPT_DCI) 1854 return; 1855 1856 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1857 1858 if (init_attr->qp_type == MLX5_IB_QPT_DCT) { 1859 if (rcqe_sz == 128) 1860 MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1861 1862 return; 1863 } 1864 1865 MLX5_SET(qpc, qpc, cs_res, 1866 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 1867 MLX5_RES_SCAT_DATA32_CQE); 1868 } 1869 1870 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1871 struct ib_qp_init_attr *init_attr, 1872 struct mlx5_ib_create_qp *ucmd, 1873 void *qpc) 1874 { 1875 enum ib_qp_type qpt = init_attr->qp_type; 1876 int scqe_sz; 1877 bool allow_scat_cqe = 0; 1878 1879 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) 1880 return; 1881 1882 if (ucmd) 1883 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1884 1885 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1886 return; 1887 1888 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1889 if (scqe_sz == 128) { 1890 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1891 return; 1892 } 1893 1894 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1895 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1896 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1897 } 1898 1899 static int atomic_size_to_mode(int size_mask) 1900 { 1901 /* driver does not support atomic_size > 256B 1902 * and does not know how to translate bigger sizes 1903 */ 1904 int supported_size_mask = size_mask & 0x1ff; 1905 int log_max_size; 1906 1907 if (!supported_size_mask) 1908 return -EOPNOTSUPP; 1909 1910 log_max_size = __fls(supported_size_mask); 1911 1912 if (log_max_size > 3) 1913 return log_max_size; 1914 1915 return MLX5_ATOMIC_MODE_8B; 1916 } 1917 1918 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1919 enum ib_qp_type qp_type) 1920 { 1921 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1922 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1923 int atomic_mode = -EOPNOTSUPP; 1924 int atomic_size_mask; 1925 1926 if (!atomic) 1927 return -EOPNOTSUPP; 1928 1929 if (qp_type == MLX5_IB_QPT_DCT) 1930 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1931 else 1932 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1933 1934 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1935 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1936 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1937 1938 if (atomic_mode <= 0 && 1939 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1940 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1941 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1942 1943 return atomic_mode; 1944 } 1945 1946 static inline bool check_flags_mask(uint64_t input, uint64_t supported) 1947 { 1948 return (input & ~supported) == 0; 1949 } 1950 1951 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1952 struct ib_qp_init_attr *init_attr, 1953 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1954 { 1955 struct mlx5_ib_resources *devr = &dev->devr; 1956 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1957 struct mlx5_core_dev *mdev = dev->mdev; 1958 struct mlx5_ib_create_qp_resp resp = {}; 1959 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 1960 udata, struct mlx5_ib_ucontext, ibucontext); 1961 struct mlx5_ib_cq *send_cq; 1962 struct mlx5_ib_cq *recv_cq; 1963 unsigned long flags; 1964 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1965 struct mlx5_ib_create_qp ucmd; 1966 struct mlx5_ib_qp_base *base; 1967 int mlx5_st; 1968 void *qpc; 1969 u32 *in; 1970 int err; 1971 1972 mutex_init(&qp->mutex); 1973 spin_lock_init(&qp->sq.lock); 1974 spin_lock_init(&qp->rq.lock); 1975 1976 mlx5_st = to_mlx5_st(init_attr->qp_type); 1977 if (mlx5_st < 0) 1978 return -EINVAL; 1979 1980 if (init_attr->rwq_ind_tbl) { 1981 if (!udata) 1982 return -ENOSYS; 1983 1984 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1985 return err; 1986 } 1987 1988 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1989 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1990 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1991 return -EINVAL; 1992 } else { 1993 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1994 } 1995 } 1996 1997 if (init_attr->create_flags & 1998 (IB_QP_CREATE_CROSS_CHANNEL | 1999 IB_QP_CREATE_MANAGED_SEND | 2000 IB_QP_CREATE_MANAGED_RECV)) { 2001 if (!MLX5_CAP_GEN(mdev, cd)) { 2002 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 2003 return -EINVAL; 2004 } 2005 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 2006 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 2007 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 2008 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 2009 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 2010 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 2011 } 2012 2013 if (init_attr->qp_type == IB_QPT_UD && 2014 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 2015 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 2016 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 2017 return -EOPNOTSUPP; 2018 } 2019 2020 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 2021 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2022 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 2023 return -EOPNOTSUPP; 2024 } 2025 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 2026 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 2027 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 2028 return -EOPNOTSUPP; 2029 } 2030 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 2031 } 2032 2033 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2034 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2035 2036 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 2037 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 2038 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 2039 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 2040 return -EOPNOTSUPP; 2041 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 2042 } 2043 2044 if (udata) { 2045 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 2046 mlx5_ib_dbg(dev, "copy failed\n"); 2047 return -EFAULT; 2048 } 2049 2050 if (!check_flags_mask(ucmd.flags, 2051 MLX5_QP_FLAG_ALLOW_SCATTER_CQE | 2052 MLX5_QP_FLAG_BFREG_INDEX | 2053 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE | 2054 MLX5_QP_FLAG_SCATTER_CQE | 2055 MLX5_QP_FLAG_SIGNATURE | 2056 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC | 2057 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2058 MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2059 MLX5_QP_FLAG_TYPE_DCI | 2060 MLX5_QP_FLAG_TYPE_DCT)) 2061 return -EINVAL; 2062 2063 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx); 2064 if (err) 2065 return err; 2066 2067 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 2068 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) 2069 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 2070 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 2071 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 2072 !tunnel_offload_supported(mdev)) { 2073 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 2074 return -EOPNOTSUPP; 2075 } 2076 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; 2077 } 2078 2079 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { 2080 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2081 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); 2082 return -EOPNOTSUPP; 2083 } 2084 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 2085 } 2086 2087 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 2088 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2089 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); 2090 return -EOPNOTSUPP; 2091 } 2092 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 2093 } 2094 2095 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { 2096 if (init_attr->qp_type != IB_QPT_RC || 2097 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { 2098 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); 2099 return -EOPNOTSUPP; 2100 } 2101 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; 2102 } 2103 2104 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 2105 if (init_attr->qp_type != IB_QPT_UD || 2106 (MLX5_CAP_GEN(dev->mdev, port_type) != 2107 MLX5_CAP_PORT_TYPE_IB) || 2108 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 2109 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 2110 return -EOPNOTSUPP; 2111 } 2112 2113 qp->flags |= MLX5_IB_QP_UNDERLAY; 2114 qp->underlay_qpn = init_attr->source_qpn; 2115 } 2116 } else { 2117 qp->wq_sig = !!wq_signature; 2118 } 2119 2120 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2121 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2122 &qp->raw_packet_qp.rq.base : 2123 &qp->trans_qp.base; 2124 2125 qp->has_rq = qp_has_rq(init_attr); 2126 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 2127 qp, udata ? &ucmd : NULL); 2128 if (err) { 2129 mlx5_ib_dbg(dev, "err %d\n", err); 2130 return err; 2131 } 2132 2133 if (pd) { 2134 if (udata) { 2135 __u32 max_wqes = 2136 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 2137 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 2138 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 2139 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 2140 mlx5_ib_dbg(dev, "invalid rq params\n"); 2141 return -EINVAL; 2142 } 2143 if (ucmd.sq_wqe_count > max_wqes) { 2144 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 2145 ucmd.sq_wqe_count, max_wqes); 2146 return -EINVAL; 2147 } 2148 if (init_attr->create_flags & 2149 mlx5_ib_create_qp_sqpn_qp1()) { 2150 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 2151 return -EINVAL; 2152 } 2153 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 2154 &resp, &inlen, base); 2155 if (err) 2156 mlx5_ib_dbg(dev, "err %d\n", err); 2157 } else { 2158 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 2159 base); 2160 if (err) 2161 mlx5_ib_dbg(dev, "err %d\n", err); 2162 } 2163 2164 if (err) 2165 return err; 2166 } else { 2167 in = kvzalloc(inlen, GFP_KERNEL); 2168 if (!in) 2169 return -ENOMEM; 2170 2171 qp->create_type = MLX5_QP_EMPTY; 2172 } 2173 2174 if (is_sqp(init_attr->qp_type)) 2175 qp->port = init_attr->port_num; 2176 2177 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2178 2179 MLX5_SET(qpc, qpc, st, mlx5_st); 2180 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2181 2182 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 2183 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2184 else 2185 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2186 2187 2188 if (qp->wq_sig) 2189 MLX5_SET(qpc, qpc, wq_signature, 1); 2190 2191 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2192 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2193 2194 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 2195 MLX5_SET(qpc, qpc, cd_master, 1); 2196 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 2197 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2198 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 2199 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2200 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) 2201 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2202 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 2203 configure_responder_scat_cqe(init_attr, qpc); 2204 configure_requester_scat_cqe(dev, init_attr, 2205 udata ? &ucmd : NULL, 2206 qpc); 2207 } 2208 2209 if (qp->rq.wqe_cnt) { 2210 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2211 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2212 } 2213 2214 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2215 2216 if (qp->sq.wqe_cnt) { 2217 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2218 } else { 2219 MLX5_SET(qpc, qpc, no_sq, 1); 2220 if (init_attr->srq && 2221 init_attr->srq->srq_type == IB_SRQT_TM) 2222 MLX5_SET(qpc, qpc, offload_type, 2223 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2224 } 2225 2226 /* Set default resources */ 2227 switch (init_attr->qp_type) { 2228 case IB_QPT_XRC_TGT: 2229 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2230 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2231 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2232 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 2233 break; 2234 case IB_QPT_XRC_INI: 2235 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2236 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2237 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2238 break; 2239 default: 2240 if (init_attr->srq) { 2241 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2242 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2243 } else { 2244 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2245 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2246 } 2247 } 2248 2249 if (init_attr->send_cq) 2250 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2251 2252 if (init_attr->recv_cq) 2253 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2254 2255 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2256 2257 /* 0xffffff means we ask to work with cqe version 0 */ 2258 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2259 MLX5_SET(qpc, qpc, user_index, uidx); 2260 2261 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2262 if (init_attr->qp_type == IB_QPT_UD && 2263 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 2264 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2265 qp->flags |= MLX5_IB_QP_LSO; 2266 } 2267 2268 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2269 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 2270 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 2271 err = -EOPNOTSUPP; 2272 goto err; 2273 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2274 MLX5_SET(qpc, qpc, end_padding_mode, 2275 MLX5_WQ_END_PAD_MODE_ALIGN); 2276 } else { 2277 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 2278 } 2279 } 2280 2281 if (inlen < 0) { 2282 err = -EINVAL; 2283 goto err; 2284 } 2285 2286 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2287 qp->flags & MLX5_IB_QP_UNDERLAY) { 2288 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 2289 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2290 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2291 &resp); 2292 } else { 2293 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 2294 } 2295 2296 if (err) { 2297 mlx5_ib_dbg(dev, "create qp failed\n"); 2298 goto err_create; 2299 } 2300 2301 kvfree(in); 2302 2303 base->container_mibqp = qp; 2304 base->mqp.event = mlx5_ib_qp_event; 2305 2306 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 2307 &send_cq, &recv_cq); 2308 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2309 mlx5_ib_lock_cqs(send_cq, recv_cq); 2310 /* Maintain device to QPs access, needed for further handling via reset 2311 * flow 2312 */ 2313 list_add_tail(&qp->qps_list, &dev->qp_list); 2314 /* Maintain CQ to QPs access, needed for further handling via reset flow 2315 */ 2316 if (send_cq) 2317 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2318 if (recv_cq) 2319 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2320 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2321 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2322 2323 return 0; 2324 2325 err_create: 2326 if (qp->create_type == MLX5_QP_USER) 2327 destroy_qp_user(dev, pd, qp, base, udata); 2328 else if (qp->create_type == MLX5_QP_KERNEL) 2329 destroy_qp_kernel(dev, qp); 2330 2331 err: 2332 kvfree(in); 2333 return err; 2334 } 2335 2336 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2337 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2338 { 2339 if (send_cq) { 2340 if (recv_cq) { 2341 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2342 spin_lock(&send_cq->lock); 2343 spin_lock_nested(&recv_cq->lock, 2344 SINGLE_DEPTH_NESTING); 2345 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2346 spin_lock(&send_cq->lock); 2347 __acquire(&recv_cq->lock); 2348 } else { 2349 spin_lock(&recv_cq->lock); 2350 spin_lock_nested(&send_cq->lock, 2351 SINGLE_DEPTH_NESTING); 2352 } 2353 } else { 2354 spin_lock(&send_cq->lock); 2355 __acquire(&recv_cq->lock); 2356 } 2357 } else if (recv_cq) { 2358 spin_lock(&recv_cq->lock); 2359 __acquire(&send_cq->lock); 2360 } else { 2361 __acquire(&send_cq->lock); 2362 __acquire(&recv_cq->lock); 2363 } 2364 } 2365 2366 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2367 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2368 { 2369 if (send_cq) { 2370 if (recv_cq) { 2371 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2372 spin_unlock(&recv_cq->lock); 2373 spin_unlock(&send_cq->lock); 2374 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2375 __release(&recv_cq->lock); 2376 spin_unlock(&send_cq->lock); 2377 } else { 2378 spin_unlock(&send_cq->lock); 2379 spin_unlock(&recv_cq->lock); 2380 } 2381 } else { 2382 __release(&recv_cq->lock); 2383 spin_unlock(&send_cq->lock); 2384 } 2385 } else if (recv_cq) { 2386 __release(&send_cq->lock); 2387 spin_unlock(&recv_cq->lock); 2388 } else { 2389 __release(&recv_cq->lock); 2390 __release(&send_cq->lock); 2391 } 2392 } 2393 2394 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2395 { 2396 return to_mpd(qp->ibqp.pd); 2397 } 2398 2399 static void get_cqs(enum ib_qp_type qp_type, 2400 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2401 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2402 { 2403 switch (qp_type) { 2404 case IB_QPT_XRC_TGT: 2405 *send_cq = NULL; 2406 *recv_cq = NULL; 2407 break; 2408 case MLX5_IB_QPT_REG_UMR: 2409 case IB_QPT_XRC_INI: 2410 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2411 *recv_cq = NULL; 2412 break; 2413 2414 case IB_QPT_SMI: 2415 case MLX5_IB_QPT_HW_GSI: 2416 case IB_QPT_RC: 2417 case IB_QPT_UC: 2418 case IB_QPT_UD: 2419 case IB_QPT_RAW_IPV6: 2420 case IB_QPT_RAW_ETHERTYPE: 2421 case IB_QPT_RAW_PACKET: 2422 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2423 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2424 break; 2425 2426 case IB_QPT_MAX: 2427 default: 2428 *send_cq = NULL; 2429 *recv_cq = NULL; 2430 break; 2431 } 2432 } 2433 2434 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2435 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2436 u8 lag_tx_affinity); 2437 2438 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2439 struct ib_udata *udata) 2440 { 2441 struct mlx5_ib_cq *send_cq, *recv_cq; 2442 struct mlx5_ib_qp_base *base; 2443 unsigned long flags; 2444 int err; 2445 2446 if (qp->ibqp.rwq_ind_tbl) { 2447 destroy_rss_raw_qp_tir(dev, qp); 2448 return; 2449 } 2450 2451 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2452 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2453 &qp->raw_packet_qp.rq.base : 2454 &qp->trans_qp.base; 2455 2456 if (qp->state != IB_QPS_RESET) { 2457 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2458 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2459 err = mlx5_core_qp_modify(dev->mdev, 2460 MLX5_CMD_OP_2RST_QP, 0, 2461 NULL, &base->mqp); 2462 } else { 2463 struct mlx5_modify_raw_qp_param raw_qp_param = { 2464 .operation = MLX5_CMD_OP_2RST_QP 2465 }; 2466 2467 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2468 } 2469 if (err) 2470 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2471 base->mqp.qpn); 2472 } 2473 2474 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2475 &send_cq, &recv_cq); 2476 2477 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2478 mlx5_ib_lock_cqs(send_cq, recv_cq); 2479 /* del from lists under both locks above to protect reset flow paths */ 2480 list_del(&qp->qps_list); 2481 if (send_cq) 2482 list_del(&qp->cq_send_list); 2483 2484 if (recv_cq) 2485 list_del(&qp->cq_recv_list); 2486 2487 if (qp->create_type == MLX5_QP_KERNEL) { 2488 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2489 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2490 if (send_cq != recv_cq) 2491 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2492 NULL); 2493 } 2494 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2495 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2496 2497 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2498 qp->flags & MLX5_IB_QP_UNDERLAY) { 2499 destroy_raw_packet_qp(dev, qp); 2500 } else { 2501 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2502 if (err) 2503 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2504 base->mqp.qpn); 2505 } 2506 2507 if (qp->create_type == MLX5_QP_KERNEL) 2508 destroy_qp_kernel(dev, qp); 2509 else if (qp->create_type == MLX5_QP_USER) 2510 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); 2511 } 2512 2513 static const char *ib_qp_type_str(enum ib_qp_type type) 2514 { 2515 switch (type) { 2516 case IB_QPT_SMI: 2517 return "IB_QPT_SMI"; 2518 case IB_QPT_GSI: 2519 return "IB_QPT_GSI"; 2520 case IB_QPT_RC: 2521 return "IB_QPT_RC"; 2522 case IB_QPT_UC: 2523 return "IB_QPT_UC"; 2524 case IB_QPT_UD: 2525 return "IB_QPT_UD"; 2526 case IB_QPT_RAW_IPV6: 2527 return "IB_QPT_RAW_IPV6"; 2528 case IB_QPT_RAW_ETHERTYPE: 2529 return "IB_QPT_RAW_ETHERTYPE"; 2530 case IB_QPT_XRC_INI: 2531 return "IB_QPT_XRC_INI"; 2532 case IB_QPT_XRC_TGT: 2533 return "IB_QPT_XRC_TGT"; 2534 case IB_QPT_RAW_PACKET: 2535 return "IB_QPT_RAW_PACKET"; 2536 case MLX5_IB_QPT_REG_UMR: 2537 return "MLX5_IB_QPT_REG_UMR"; 2538 case IB_QPT_DRIVER: 2539 return "IB_QPT_DRIVER"; 2540 case IB_QPT_MAX: 2541 default: 2542 return "Invalid QP type"; 2543 } 2544 } 2545 2546 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2547 struct ib_qp_init_attr *attr, 2548 struct mlx5_ib_create_qp *ucmd, 2549 struct ib_udata *udata) 2550 { 2551 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2552 udata, struct mlx5_ib_ucontext, ibucontext); 2553 struct mlx5_ib_qp *qp; 2554 int err = 0; 2555 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2556 void *dctc; 2557 2558 if (!attr->srq || !attr->recv_cq) 2559 return ERR_PTR(-EINVAL); 2560 2561 err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx); 2562 if (err) 2563 return ERR_PTR(err); 2564 2565 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2566 if (!qp) 2567 return ERR_PTR(-ENOMEM); 2568 2569 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2570 if (!qp->dct.in) { 2571 err = -ENOMEM; 2572 goto err_free; 2573 } 2574 2575 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2576 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2577 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2578 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2579 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2580 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2581 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2582 MLX5_SET(dctc, dctc, user_index, uidx); 2583 2584 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) 2585 configure_responder_scat_cqe(attr, dctc); 2586 2587 qp->state = IB_QPS_RESET; 2588 2589 return &qp->ibqp; 2590 err_free: 2591 kfree(qp); 2592 return ERR_PTR(err); 2593 } 2594 2595 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2596 struct ib_qp_init_attr *init_attr, 2597 struct mlx5_ib_create_qp *ucmd, 2598 struct ib_udata *udata) 2599 { 2600 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2601 int err; 2602 2603 if (!udata) 2604 return -EINVAL; 2605 2606 if (udata->inlen < sizeof(*ucmd)) { 2607 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2608 return -EINVAL; 2609 } 2610 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2611 if (err) 2612 return err; 2613 2614 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2615 init_attr->qp_type = MLX5_IB_QPT_DCI; 2616 } else { 2617 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2618 init_attr->qp_type = MLX5_IB_QPT_DCT; 2619 } else { 2620 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2621 return -EINVAL; 2622 } 2623 } 2624 2625 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2626 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2627 return -EOPNOTSUPP; 2628 } 2629 2630 return 0; 2631 } 2632 2633 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2634 struct ib_qp_init_attr *verbs_init_attr, 2635 struct ib_udata *udata) 2636 { 2637 struct mlx5_ib_dev *dev; 2638 struct mlx5_ib_qp *qp; 2639 u16 xrcdn = 0; 2640 int err; 2641 struct ib_qp_init_attr mlx_init_attr; 2642 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2643 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2644 udata, struct mlx5_ib_ucontext, ibucontext); 2645 2646 if (pd) { 2647 dev = to_mdev(pd->device); 2648 2649 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2650 if (!ucontext) { 2651 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2652 return ERR_PTR(-EINVAL); 2653 } else if (!ucontext->cqe_version) { 2654 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2655 return ERR_PTR(-EINVAL); 2656 } 2657 } 2658 } else { 2659 /* being cautious here */ 2660 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2661 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2662 pr_warn("%s: no PD for transport %s\n", __func__, 2663 ib_qp_type_str(init_attr->qp_type)); 2664 return ERR_PTR(-EINVAL); 2665 } 2666 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2667 } 2668 2669 if (init_attr->qp_type == IB_QPT_DRIVER) { 2670 struct mlx5_ib_create_qp ucmd; 2671 2672 init_attr = &mlx_init_attr; 2673 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2674 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2675 if (err) 2676 return ERR_PTR(err); 2677 2678 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2679 if (init_attr->cap.max_recv_wr || 2680 init_attr->cap.max_recv_sge) { 2681 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2682 return ERR_PTR(-EINVAL); 2683 } 2684 } else { 2685 return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata); 2686 } 2687 } 2688 2689 switch (init_attr->qp_type) { 2690 case IB_QPT_XRC_TGT: 2691 case IB_QPT_XRC_INI: 2692 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2693 mlx5_ib_dbg(dev, "XRC not supported\n"); 2694 return ERR_PTR(-ENOSYS); 2695 } 2696 init_attr->recv_cq = NULL; 2697 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2698 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2699 init_attr->send_cq = NULL; 2700 } 2701 2702 /* fall through */ 2703 case IB_QPT_RAW_PACKET: 2704 case IB_QPT_RC: 2705 case IB_QPT_UC: 2706 case IB_QPT_UD: 2707 case IB_QPT_SMI: 2708 case MLX5_IB_QPT_HW_GSI: 2709 case MLX5_IB_QPT_REG_UMR: 2710 case MLX5_IB_QPT_DCI: 2711 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2712 if (!qp) 2713 return ERR_PTR(-ENOMEM); 2714 2715 err = create_qp_common(dev, pd, init_attr, udata, qp); 2716 if (err) { 2717 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2718 kfree(qp); 2719 return ERR_PTR(err); 2720 } 2721 2722 if (is_qp0(init_attr->qp_type)) 2723 qp->ibqp.qp_num = 0; 2724 else if (is_qp1(init_attr->qp_type)) 2725 qp->ibqp.qp_num = 1; 2726 else 2727 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2728 2729 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2730 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2731 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2732 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2733 2734 qp->trans_qp.xrcdn = xrcdn; 2735 2736 break; 2737 2738 case IB_QPT_GSI: 2739 return mlx5_ib_gsi_create_qp(pd, init_attr); 2740 2741 case IB_QPT_RAW_IPV6: 2742 case IB_QPT_RAW_ETHERTYPE: 2743 case IB_QPT_MAX: 2744 default: 2745 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2746 init_attr->qp_type); 2747 /* Don't support raw QPs */ 2748 return ERR_PTR(-EINVAL); 2749 } 2750 2751 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2752 qp->qp_sub_type = init_attr->qp_type; 2753 2754 return &qp->ibqp; 2755 } 2756 2757 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2758 { 2759 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2760 2761 if (mqp->state == IB_QPS_RTR) { 2762 int err; 2763 2764 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2765 if (err) { 2766 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2767 return err; 2768 } 2769 } 2770 2771 kfree(mqp->dct.in); 2772 kfree(mqp); 2773 return 0; 2774 } 2775 2776 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2777 { 2778 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2779 struct mlx5_ib_qp *mqp = to_mqp(qp); 2780 2781 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2782 return mlx5_ib_gsi_destroy_qp(qp); 2783 2784 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2785 return mlx5_ib_destroy_dct(mqp); 2786 2787 destroy_qp_common(dev, mqp, udata); 2788 2789 kfree(mqp); 2790 2791 return 0; 2792 } 2793 2794 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2795 const struct ib_qp_attr *attr, 2796 int attr_mask, __be32 *hw_access_flags_be) 2797 { 2798 u8 dest_rd_atomic; 2799 u32 access_flags, hw_access_flags = 0; 2800 2801 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2802 2803 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2804 dest_rd_atomic = attr->max_dest_rd_atomic; 2805 else 2806 dest_rd_atomic = qp->trans_qp.resp_depth; 2807 2808 if (attr_mask & IB_QP_ACCESS_FLAGS) 2809 access_flags = attr->qp_access_flags; 2810 else 2811 access_flags = qp->trans_qp.atomic_rd_en; 2812 2813 if (!dest_rd_atomic) 2814 access_flags &= IB_ACCESS_REMOTE_WRITE; 2815 2816 if (access_flags & IB_ACCESS_REMOTE_READ) 2817 hw_access_flags |= MLX5_QP_BIT_RRE; 2818 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2819 int atomic_mode; 2820 2821 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2822 if (atomic_mode < 0) 2823 return -EOPNOTSUPP; 2824 2825 hw_access_flags |= MLX5_QP_BIT_RAE; 2826 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; 2827 } 2828 2829 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2830 hw_access_flags |= MLX5_QP_BIT_RWE; 2831 2832 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2833 2834 return 0; 2835 } 2836 2837 enum { 2838 MLX5_PATH_FLAG_FL = 1 << 0, 2839 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2840 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2841 }; 2842 2843 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2844 { 2845 if (rate == IB_RATE_PORT_CURRENT) 2846 return 0; 2847 2848 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 2849 return -EINVAL; 2850 2851 while (rate != IB_RATE_PORT_CURRENT && 2852 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2853 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2854 --rate; 2855 2856 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2857 } 2858 2859 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2860 struct mlx5_ib_sq *sq, u8 sl, 2861 struct ib_pd *pd) 2862 { 2863 void *in; 2864 void *tisc; 2865 int inlen; 2866 int err; 2867 2868 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2869 in = kvzalloc(inlen, GFP_KERNEL); 2870 if (!in) 2871 return -ENOMEM; 2872 2873 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2874 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2875 2876 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2877 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2878 2879 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2880 2881 kvfree(in); 2882 2883 return err; 2884 } 2885 2886 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2887 struct mlx5_ib_sq *sq, u8 tx_affinity, 2888 struct ib_pd *pd) 2889 { 2890 void *in; 2891 void *tisc; 2892 int inlen; 2893 int err; 2894 2895 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2896 in = kvzalloc(inlen, GFP_KERNEL); 2897 if (!in) 2898 return -ENOMEM; 2899 2900 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2901 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2902 2903 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2904 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2905 2906 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2907 2908 kvfree(in); 2909 2910 return err; 2911 } 2912 2913 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2914 const struct rdma_ah_attr *ah, 2915 struct mlx5_qp_path *path, u8 port, int attr_mask, 2916 u32 path_flags, const struct ib_qp_attr *attr, 2917 bool alt) 2918 { 2919 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2920 int err; 2921 enum ib_gid_type gid_type; 2922 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2923 u8 sl = rdma_ah_get_sl(ah); 2924 2925 if (attr_mask & IB_QP_PKEY_INDEX) 2926 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2927 attr->pkey_index); 2928 2929 if (ah_flags & IB_AH_GRH) { 2930 if (grh->sgid_index >= 2931 dev->mdev->port_caps[port - 1].gid_table_len) { 2932 pr_err("sgid_index (%u) too large. max is %d\n", 2933 grh->sgid_index, 2934 dev->mdev->port_caps[port - 1].gid_table_len); 2935 return -EINVAL; 2936 } 2937 } 2938 2939 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2940 if (!(ah_flags & IB_AH_GRH)) 2941 return -EINVAL; 2942 2943 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2944 if (qp->ibqp.qp_type == IB_QPT_RC || 2945 qp->ibqp.qp_type == IB_QPT_UC || 2946 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2947 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2948 path->udp_sport = 2949 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); 2950 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2951 gid_type = ah->grh.sgid_attr->gid_type; 2952 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2953 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2954 } else { 2955 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2956 path->fl_free_ar |= 2957 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2958 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2959 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2960 if (ah_flags & IB_AH_GRH) 2961 path->grh_mlid |= 1 << 7; 2962 path->dci_cfi_prio_sl = sl & 0xf; 2963 } 2964 2965 if (ah_flags & IB_AH_GRH) { 2966 path->mgid_index = grh->sgid_index; 2967 path->hop_limit = grh->hop_limit; 2968 path->tclass_flowlabel = 2969 cpu_to_be32((grh->traffic_class << 20) | 2970 (grh->flow_label)); 2971 memcpy(path->rgid, grh->dgid.raw, 16); 2972 } 2973 2974 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2975 if (err < 0) 2976 return err; 2977 path->static_rate = err; 2978 path->port = port; 2979 2980 if (attr_mask & IB_QP_TIMEOUT) 2981 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2982 2983 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2984 return modify_raw_packet_eth_prio(dev->mdev, 2985 &qp->raw_packet_qp.sq, 2986 sl & 0xf, qp->ibqp.pd); 2987 2988 return 0; 2989 } 2990 2991 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2992 [MLX5_QP_STATE_INIT] = { 2993 [MLX5_QP_STATE_INIT] = { 2994 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2995 MLX5_QP_OPTPAR_RAE | 2996 MLX5_QP_OPTPAR_RWE | 2997 MLX5_QP_OPTPAR_PKEY_INDEX | 2998 MLX5_QP_OPTPAR_PRI_PORT, 2999 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3000 MLX5_QP_OPTPAR_PKEY_INDEX | 3001 MLX5_QP_OPTPAR_PRI_PORT, 3002 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3003 MLX5_QP_OPTPAR_Q_KEY | 3004 MLX5_QP_OPTPAR_PRI_PORT, 3005 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3006 MLX5_QP_OPTPAR_RAE | 3007 MLX5_QP_OPTPAR_RWE | 3008 MLX5_QP_OPTPAR_PKEY_INDEX | 3009 MLX5_QP_OPTPAR_PRI_PORT, 3010 }, 3011 [MLX5_QP_STATE_RTR] = { 3012 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3013 MLX5_QP_OPTPAR_RRE | 3014 MLX5_QP_OPTPAR_RAE | 3015 MLX5_QP_OPTPAR_RWE | 3016 MLX5_QP_OPTPAR_PKEY_INDEX, 3017 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3018 MLX5_QP_OPTPAR_RWE | 3019 MLX5_QP_OPTPAR_PKEY_INDEX, 3020 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3021 MLX5_QP_OPTPAR_Q_KEY, 3022 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3023 MLX5_QP_OPTPAR_Q_KEY, 3024 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3025 MLX5_QP_OPTPAR_RRE | 3026 MLX5_QP_OPTPAR_RAE | 3027 MLX5_QP_OPTPAR_RWE | 3028 MLX5_QP_OPTPAR_PKEY_INDEX, 3029 }, 3030 }, 3031 [MLX5_QP_STATE_RTR] = { 3032 [MLX5_QP_STATE_RTS] = { 3033 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3034 MLX5_QP_OPTPAR_RRE | 3035 MLX5_QP_OPTPAR_RAE | 3036 MLX5_QP_OPTPAR_RWE | 3037 MLX5_QP_OPTPAR_PM_STATE | 3038 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3039 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3040 MLX5_QP_OPTPAR_RWE | 3041 MLX5_QP_OPTPAR_PM_STATE, 3042 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3043 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3044 MLX5_QP_OPTPAR_RRE | 3045 MLX5_QP_OPTPAR_RAE | 3046 MLX5_QP_OPTPAR_RWE | 3047 MLX5_QP_OPTPAR_PM_STATE | 3048 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3049 }, 3050 }, 3051 [MLX5_QP_STATE_RTS] = { 3052 [MLX5_QP_STATE_RTS] = { 3053 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3054 MLX5_QP_OPTPAR_RAE | 3055 MLX5_QP_OPTPAR_RWE | 3056 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3057 MLX5_QP_OPTPAR_PM_STATE | 3058 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3059 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3060 MLX5_QP_OPTPAR_PM_STATE | 3061 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3062 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3063 MLX5_QP_OPTPAR_SRQN | 3064 MLX5_QP_OPTPAR_CQN_RCV, 3065 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3066 MLX5_QP_OPTPAR_RAE | 3067 MLX5_QP_OPTPAR_RWE | 3068 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3069 MLX5_QP_OPTPAR_PM_STATE | 3070 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3071 }, 3072 }, 3073 [MLX5_QP_STATE_SQER] = { 3074 [MLX5_QP_STATE_RTS] = { 3075 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3076 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3077 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3078 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3079 MLX5_QP_OPTPAR_RWE | 3080 MLX5_QP_OPTPAR_RAE | 3081 MLX5_QP_OPTPAR_RRE, 3082 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3083 MLX5_QP_OPTPAR_RWE | 3084 MLX5_QP_OPTPAR_RAE | 3085 MLX5_QP_OPTPAR_RRE, 3086 }, 3087 }, 3088 }; 3089 3090 static int ib_nr_to_mlx5_nr(int ib_mask) 3091 { 3092 switch (ib_mask) { 3093 case IB_QP_STATE: 3094 return 0; 3095 case IB_QP_CUR_STATE: 3096 return 0; 3097 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3098 return 0; 3099 case IB_QP_ACCESS_FLAGS: 3100 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3101 MLX5_QP_OPTPAR_RAE; 3102 case IB_QP_PKEY_INDEX: 3103 return MLX5_QP_OPTPAR_PKEY_INDEX; 3104 case IB_QP_PORT: 3105 return MLX5_QP_OPTPAR_PRI_PORT; 3106 case IB_QP_QKEY: 3107 return MLX5_QP_OPTPAR_Q_KEY; 3108 case IB_QP_AV: 3109 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3110 MLX5_QP_OPTPAR_PRI_PORT; 3111 case IB_QP_PATH_MTU: 3112 return 0; 3113 case IB_QP_TIMEOUT: 3114 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3115 case IB_QP_RETRY_CNT: 3116 return MLX5_QP_OPTPAR_RETRY_COUNT; 3117 case IB_QP_RNR_RETRY: 3118 return MLX5_QP_OPTPAR_RNR_RETRY; 3119 case IB_QP_RQ_PSN: 3120 return 0; 3121 case IB_QP_MAX_QP_RD_ATOMIC: 3122 return MLX5_QP_OPTPAR_SRA_MAX; 3123 case IB_QP_ALT_PATH: 3124 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3125 case IB_QP_MIN_RNR_TIMER: 3126 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3127 case IB_QP_SQ_PSN: 3128 return 0; 3129 case IB_QP_MAX_DEST_RD_ATOMIC: 3130 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3131 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3132 case IB_QP_PATH_MIG_STATE: 3133 return MLX5_QP_OPTPAR_PM_STATE; 3134 case IB_QP_CAP: 3135 return 0; 3136 case IB_QP_DEST_QPN: 3137 return 0; 3138 } 3139 return 0; 3140 } 3141 3142 static int ib_mask_to_mlx5_opt(int ib_mask) 3143 { 3144 int result = 0; 3145 int i; 3146 3147 for (i = 0; i < 8 * sizeof(int); i++) { 3148 if ((1 << i) & ib_mask) 3149 result |= ib_nr_to_mlx5_nr(1 << i); 3150 } 3151 3152 return result; 3153 } 3154 3155 static int modify_raw_packet_qp_rq( 3156 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3157 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3158 { 3159 void *in; 3160 void *rqc; 3161 int inlen; 3162 int err; 3163 3164 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3165 in = kvzalloc(inlen, GFP_KERNEL); 3166 if (!in) 3167 return -ENOMEM; 3168 3169 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3170 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3171 3172 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3173 MLX5_SET(rqc, rqc, state, new_state); 3174 3175 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3176 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3177 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3178 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3179 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3180 } else 3181 dev_info_once( 3182 &dev->ib_dev.dev, 3183 "RAW PACKET QP counters are not supported on current FW\n"); 3184 } 3185 3186 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 3187 if (err) 3188 goto out; 3189 3190 rq->state = new_state; 3191 3192 out: 3193 kvfree(in); 3194 return err; 3195 } 3196 3197 static int modify_raw_packet_qp_sq( 3198 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3199 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3200 { 3201 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3202 struct mlx5_rate_limit old_rl = ibqp->rl; 3203 struct mlx5_rate_limit new_rl = old_rl; 3204 bool new_rate_added = false; 3205 u16 rl_index = 0; 3206 void *in; 3207 void *sqc; 3208 int inlen; 3209 int err; 3210 3211 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3212 in = kvzalloc(inlen, GFP_KERNEL); 3213 if (!in) 3214 return -ENOMEM; 3215 3216 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3217 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3218 3219 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3220 MLX5_SET(sqc, sqc, state, new_state); 3221 3222 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3223 if (new_state != MLX5_SQC_STATE_RDY) 3224 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3225 __func__); 3226 else 3227 new_rl = raw_qp_param->rl; 3228 } 3229 3230 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3231 if (new_rl.rate) { 3232 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3233 if (err) { 3234 pr_err("Failed configuring rate limit(err %d): \ 3235 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3236 err, new_rl.rate, new_rl.max_burst_sz, 3237 new_rl.typical_pkt_sz); 3238 3239 goto out; 3240 } 3241 new_rate_added = true; 3242 } 3243 3244 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3245 /* index 0 means no limit */ 3246 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3247 } 3248 3249 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 3250 if (err) { 3251 /* Remove new rate from table if failed */ 3252 if (new_rate_added) 3253 mlx5_rl_remove_rate(dev, &new_rl); 3254 goto out; 3255 } 3256 3257 /* Only remove the old rate after new rate was set */ 3258 if ((old_rl.rate && 3259 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3260 (new_state != MLX5_SQC_STATE_RDY)) 3261 mlx5_rl_remove_rate(dev, &old_rl); 3262 3263 ibqp->rl = new_rl; 3264 sq->state = new_state; 3265 3266 out: 3267 kvfree(in); 3268 return err; 3269 } 3270 3271 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3272 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3273 u8 tx_affinity) 3274 { 3275 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3276 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3277 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3278 int modify_rq = !!qp->rq.wqe_cnt; 3279 int modify_sq = !!qp->sq.wqe_cnt; 3280 int rq_state; 3281 int sq_state; 3282 int err; 3283 3284 switch (raw_qp_param->operation) { 3285 case MLX5_CMD_OP_RST2INIT_QP: 3286 rq_state = MLX5_RQC_STATE_RDY; 3287 sq_state = MLX5_SQC_STATE_RDY; 3288 break; 3289 case MLX5_CMD_OP_2ERR_QP: 3290 rq_state = MLX5_RQC_STATE_ERR; 3291 sq_state = MLX5_SQC_STATE_ERR; 3292 break; 3293 case MLX5_CMD_OP_2RST_QP: 3294 rq_state = MLX5_RQC_STATE_RST; 3295 sq_state = MLX5_SQC_STATE_RST; 3296 break; 3297 case MLX5_CMD_OP_RTR2RTS_QP: 3298 case MLX5_CMD_OP_RTS2RTS_QP: 3299 if (raw_qp_param->set_mask == 3300 MLX5_RAW_QP_RATE_LIMIT) { 3301 modify_rq = 0; 3302 sq_state = sq->state; 3303 } else { 3304 return raw_qp_param->set_mask ? -EINVAL : 0; 3305 } 3306 break; 3307 case MLX5_CMD_OP_INIT2INIT_QP: 3308 case MLX5_CMD_OP_INIT2RTR_QP: 3309 if (raw_qp_param->set_mask) 3310 return -EINVAL; 3311 else 3312 return 0; 3313 default: 3314 WARN_ON(1); 3315 return -EINVAL; 3316 } 3317 3318 if (modify_rq) { 3319 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3320 qp->ibqp.pd); 3321 if (err) 3322 return err; 3323 } 3324 3325 if (modify_sq) { 3326 struct mlx5_flow_handle *flow_rule; 3327 3328 if (tx_affinity) { 3329 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3330 tx_affinity, 3331 qp->ibqp.pd); 3332 if (err) 3333 return err; 3334 } 3335 3336 flow_rule = create_flow_rule_vport_sq(dev, sq, 3337 raw_qp_param->port); 3338 if (IS_ERR(flow_rule)) 3339 return PTR_ERR(flow_rule); 3340 3341 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3342 raw_qp_param, qp->ibqp.pd); 3343 if (err) { 3344 if (flow_rule) 3345 mlx5_del_flow_rules(flow_rule); 3346 return err; 3347 } 3348 3349 if (flow_rule) { 3350 destroy_flow_rule_vport_sq(sq); 3351 sq->flow_rule = flow_rule; 3352 } 3353 3354 return err; 3355 } 3356 3357 return 0; 3358 } 3359 3360 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, 3361 struct mlx5_ib_pd *pd, 3362 struct mlx5_ib_qp_base *qp_base, 3363 u8 port_num, struct ib_udata *udata) 3364 { 3365 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3366 udata, struct mlx5_ib_ucontext, ibucontext); 3367 unsigned int tx_port_affinity; 3368 3369 if (ucontext) { 3370 tx_port_affinity = (unsigned int)atomic_add_return( 3371 1, &ucontext->tx_port_affinity) % 3372 MLX5_MAX_PORTS + 3373 1; 3374 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3375 tx_port_affinity, qp_base->mqp.qpn, ucontext); 3376 } else { 3377 tx_port_affinity = 3378 (unsigned int)atomic_add_return( 3379 1, &dev->port[port_num].roce.tx_port_affinity) % 3380 MLX5_MAX_PORTS + 3381 1; 3382 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3383 tx_port_affinity, qp_base->mqp.qpn); 3384 } 3385 3386 return tx_port_affinity; 3387 } 3388 3389 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3390 const struct ib_qp_attr *attr, int attr_mask, 3391 enum ib_qp_state cur_state, 3392 enum ib_qp_state new_state, 3393 const struct mlx5_ib_modify_qp *ucmd, 3394 struct ib_udata *udata) 3395 { 3396 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3397 [MLX5_QP_STATE_RST] = { 3398 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3399 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3400 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3401 }, 3402 [MLX5_QP_STATE_INIT] = { 3403 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3404 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3405 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3406 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3407 }, 3408 [MLX5_QP_STATE_RTR] = { 3409 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3410 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3411 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3412 }, 3413 [MLX5_QP_STATE_RTS] = { 3414 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3415 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3416 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3417 }, 3418 [MLX5_QP_STATE_SQD] = { 3419 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3420 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3421 }, 3422 [MLX5_QP_STATE_SQER] = { 3423 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3424 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3425 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3426 }, 3427 [MLX5_QP_STATE_ERR] = { 3428 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3429 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3430 } 3431 }; 3432 3433 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3434 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3435 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3436 struct mlx5_ib_cq *send_cq, *recv_cq; 3437 struct mlx5_qp_context *context; 3438 struct mlx5_ib_pd *pd; 3439 struct mlx5_ib_port *mibport = NULL; 3440 enum mlx5_qp_state mlx5_cur, mlx5_new; 3441 enum mlx5_qp_optpar optpar; 3442 int mlx5_st; 3443 int err; 3444 u16 op; 3445 u8 tx_affinity = 0; 3446 3447 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3448 qp->qp_sub_type : ibqp->qp_type); 3449 if (mlx5_st < 0) 3450 return -EINVAL; 3451 3452 context = kzalloc(sizeof(*context), GFP_KERNEL); 3453 if (!context) 3454 return -ENOMEM; 3455 3456 pd = get_pd(qp); 3457 context->flags = cpu_to_be32(mlx5_st << 16); 3458 3459 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3460 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3461 } else { 3462 switch (attr->path_mig_state) { 3463 case IB_MIG_MIGRATED: 3464 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3465 break; 3466 case IB_MIG_REARM: 3467 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3468 break; 3469 case IB_MIG_ARMED: 3470 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3471 break; 3472 } 3473 } 3474 3475 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3476 if ((ibqp->qp_type == IB_QPT_RC) || 3477 (ibqp->qp_type == IB_QPT_UD && 3478 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3479 (ibqp->qp_type == IB_QPT_UC) || 3480 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3481 (ibqp->qp_type == IB_QPT_XRC_INI) || 3482 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3483 if (dev->lag_active) { 3484 u8 p = mlx5_core_native_port_num(dev->mdev) - 1; 3485 tx_affinity = get_tx_affinity(dev, pd, base, p, 3486 udata); 3487 context->flags |= cpu_to_be32(tx_affinity << 24); 3488 } 3489 } 3490 } 3491 3492 if (is_sqp(ibqp->qp_type)) { 3493 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3494 } else if ((ibqp->qp_type == IB_QPT_UD && 3495 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3496 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3497 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3498 } else if (attr_mask & IB_QP_PATH_MTU) { 3499 if (attr->path_mtu < IB_MTU_256 || 3500 attr->path_mtu > IB_MTU_4096) { 3501 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3502 err = -EINVAL; 3503 goto out; 3504 } 3505 context->mtu_msgmax = (attr->path_mtu << 5) | 3506 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3507 } 3508 3509 if (attr_mask & IB_QP_DEST_QPN) 3510 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3511 3512 if (attr_mask & IB_QP_PKEY_INDEX) 3513 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3514 3515 /* todo implement counter_index functionality */ 3516 3517 if (is_sqp(ibqp->qp_type)) 3518 context->pri_path.port = qp->port; 3519 3520 if (attr_mask & IB_QP_PORT) 3521 context->pri_path.port = attr->port_num; 3522 3523 if (attr_mask & IB_QP_AV) { 3524 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3525 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3526 attr_mask, 0, attr, false); 3527 if (err) 3528 goto out; 3529 } 3530 3531 if (attr_mask & IB_QP_TIMEOUT) 3532 context->pri_path.ackto_lt |= attr->timeout << 3; 3533 3534 if (attr_mask & IB_QP_ALT_PATH) { 3535 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3536 &context->alt_path, 3537 attr->alt_port_num, 3538 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3539 0, attr, true); 3540 if (err) 3541 goto out; 3542 } 3543 3544 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3545 &send_cq, &recv_cq); 3546 3547 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3548 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3549 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3550 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3551 3552 if (attr_mask & IB_QP_RNR_RETRY) 3553 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3554 3555 if (attr_mask & IB_QP_RETRY_CNT) 3556 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3557 3558 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3559 if (attr->max_rd_atomic) 3560 context->params1 |= 3561 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3562 } 3563 3564 if (attr_mask & IB_QP_SQ_PSN) 3565 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3566 3567 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3568 if (attr->max_dest_rd_atomic) 3569 context->params2 |= 3570 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3571 } 3572 3573 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3574 __be32 access_flags; 3575 3576 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 3577 if (err) 3578 goto out; 3579 3580 context->params2 |= access_flags; 3581 } 3582 3583 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3584 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3585 3586 if (attr_mask & IB_QP_RQ_PSN) 3587 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3588 3589 if (attr_mask & IB_QP_QKEY) 3590 context->qkey = cpu_to_be32(attr->qkey); 3591 3592 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3593 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3594 3595 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3596 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3597 qp->port) - 1; 3598 3599 /* Underlay port should be used - index 0 function per port */ 3600 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3601 port_num = 0; 3602 3603 mibport = &dev->port[port_num]; 3604 context->qp_counter_set_usr_page |= 3605 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3606 } 3607 3608 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3609 context->sq_crq_size |= cpu_to_be16(1 << 4); 3610 3611 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3612 context->deth_sqpn = cpu_to_be32(1); 3613 3614 mlx5_cur = to_mlx5_state(cur_state); 3615 mlx5_new = to_mlx5_state(new_state); 3616 3617 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3618 !optab[mlx5_cur][mlx5_new]) { 3619 err = -EINVAL; 3620 goto out; 3621 } 3622 3623 op = optab[mlx5_cur][mlx5_new]; 3624 optpar = ib_mask_to_mlx5_opt(attr_mask); 3625 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3626 3627 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3628 qp->flags & MLX5_IB_QP_UNDERLAY) { 3629 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3630 3631 raw_qp_param.operation = op; 3632 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3633 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3634 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3635 } 3636 3637 if (attr_mask & IB_QP_PORT) 3638 raw_qp_param.port = attr->port_num; 3639 3640 if (attr_mask & IB_QP_RATE_LIMIT) { 3641 raw_qp_param.rl.rate = attr->rate_limit; 3642 3643 if (ucmd->burst_info.max_burst_sz) { 3644 if (attr->rate_limit && 3645 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3646 raw_qp_param.rl.max_burst_sz = 3647 ucmd->burst_info.max_burst_sz; 3648 } else { 3649 err = -EINVAL; 3650 goto out; 3651 } 3652 } 3653 3654 if (ucmd->burst_info.typical_pkt_sz) { 3655 if (attr->rate_limit && 3656 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3657 raw_qp_param.rl.typical_pkt_sz = 3658 ucmd->burst_info.typical_pkt_sz; 3659 } else { 3660 err = -EINVAL; 3661 goto out; 3662 } 3663 } 3664 3665 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3666 } 3667 3668 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3669 } else { 3670 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3671 &base->mqp); 3672 } 3673 3674 if (err) 3675 goto out; 3676 3677 qp->state = new_state; 3678 3679 if (attr_mask & IB_QP_ACCESS_FLAGS) 3680 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3681 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3682 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3683 if (attr_mask & IB_QP_PORT) 3684 qp->port = attr->port_num; 3685 if (attr_mask & IB_QP_ALT_PATH) 3686 qp->trans_qp.alt_port = attr->alt_port_num; 3687 3688 /* 3689 * If we moved a kernel QP to RESET, clean up all old CQ 3690 * entries and reinitialize the QP. 3691 */ 3692 if (new_state == IB_QPS_RESET && 3693 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3694 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3695 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3696 if (send_cq != recv_cq) 3697 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3698 3699 qp->rq.head = 0; 3700 qp->rq.tail = 0; 3701 qp->sq.head = 0; 3702 qp->sq.tail = 0; 3703 qp->sq.cur_post = 0; 3704 if (qp->sq.wqe_cnt) 3705 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 3706 qp->db.db[MLX5_RCV_DBR] = 0; 3707 qp->db.db[MLX5_SND_DBR] = 0; 3708 } 3709 3710 out: 3711 kfree(context); 3712 return err; 3713 } 3714 3715 static inline bool is_valid_mask(int mask, int req, int opt) 3716 { 3717 if ((mask & req) != req) 3718 return false; 3719 3720 if (mask & ~(req | opt)) 3721 return false; 3722 3723 return true; 3724 } 3725 3726 /* check valid transition for driver QP types 3727 * for now the only QP type that this function supports is DCI 3728 */ 3729 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3730 enum ib_qp_attr_mask attr_mask) 3731 { 3732 int req = IB_QP_STATE; 3733 int opt = 0; 3734 3735 if (new_state == IB_QPS_RESET) { 3736 return is_valid_mask(attr_mask, req, opt); 3737 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3738 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3739 return is_valid_mask(attr_mask, req, opt); 3740 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3741 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3742 return is_valid_mask(attr_mask, req, opt); 3743 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3744 req |= IB_QP_PATH_MTU; 3745 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 3746 return is_valid_mask(attr_mask, req, opt); 3747 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3748 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3749 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3750 opt = IB_QP_MIN_RNR_TIMER; 3751 return is_valid_mask(attr_mask, req, opt); 3752 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3753 opt = IB_QP_MIN_RNR_TIMER; 3754 return is_valid_mask(attr_mask, req, opt); 3755 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3756 return is_valid_mask(attr_mask, req, opt); 3757 } 3758 return false; 3759 } 3760 3761 /* mlx5_ib_modify_dct: modify a DCT QP 3762 * valid transitions are: 3763 * RESET to INIT: must set access_flags, pkey_index and port 3764 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3765 * mtu, gid_index and hop_limit 3766 * Other transitions and attributes are illegal 3767 */ 3768 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3769 int attr_mask, struct ib_udata *udata) 3770 { 3771 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3772 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3773 enum ib_qp_state cur_state, new_state; 3774 int err = 0; 3775 int required = IB_QP_STATE; 3776 void *dctc; 3777 3778 if (!(attr_mask & IB_QP_STATE)) 3779 return -EINVAL; 3780 3781 cur_state = qp->state; 3782 new_state = attr->qp_state; 3783 3784 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3785 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3786 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3787 if (!is_valid_mask(attr_mask, required, 0)) 3788 return -EINVAL; 3789 3790 if (attr->port_num == 0 || 3791 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3792 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3793 attr->port_num, dev->num_ports); 3794 return -EINVAL; 3795 } 3796 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3797 MLX5_SET(dctc, dctc, rre, 1); 3798 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3799 MLX5_SET(dctc, dctc, rwe, 1); 3800 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3801 int atomic_mode; 3802 3803 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 3804 if (atomic_mode < 0) 3805 return -EOPNOTSUPP; 3806 3807 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 3808 MLX5_SET(dctc, dctc, rae, 1); 3809 } 3810 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3811 MLX5_SET(dctc, dctc, port, attr->port_num); 3812 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3813 3814 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3815 struct mlx5_ib_modify_qp_resp resp = {}; 3816 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0}; 3817 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3818 sizeof(resp.dctn); 3819 3820 if (udata->outlen < min_resp_len) 3821 return -EINVAL; 3822 resp.response_length = min_resp_len; 3823 3824 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3825 if (!is_valid_mask(attr_mask, required, 0)) 3826 return -EINVAL; 3827 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3828 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3829 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3830 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3831 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3832 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3833 3834 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3835 MLX5_ST_SZ_BYTES(create_dct_in), out, 3836 sizeof(out)); 3837 if (err) 3838 return err; 3839 resp.dctn = qp->dct.mdct.mqp.qpn; 3840 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3841 if (err) { 3842 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3843 return err; 3844 } 3845 } else { 3846 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3847 return -EINVAL; 3848 } 3849 if (err) 3850 qp->state = IB_QPS_ERR; 3851 else 3852 qp->state = new_state; 3853 return err; 3854 } 3855 3856 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3857 int attr_mask, struct ib_udata *udata) 3858 { 3859 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3860 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3861 struct mlx5_ib_modify_qp ucmd = {}; 3862 enum ib_qp_type qp_type; 3863 enum ib_qp_state cur_state, new_state; 3864 size_t required_cmd_sz; 3865 int err = -EINVAL; 3866 int port; 3867 3868 if (ibqp->rwq_ind_tbl) 3869 return -ENOSYS; 3870 3871 if (udata && udata->inlen) { 3872 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3873 sizeof(ucmd.reserved); 3874 if (udata->inlen < required_cmd_sz) 3875 return -EINVAL; 3876 3877 if (udata->inlen > sizeof(ucmd) && 3878 !ib_is_udata_cleared(udata, sizeof(ucmd), 3879 udata->inlen - sizeof(ucmd))) 3880 return -EOPNOTSUPP; 3881 3882 if (ib_copy_from_udata(&ucmd, udata, 3883 min(udata->inlen, sizeof(ucmd)))) 3884 return -EFAULT; 3885 3886 if (ucmd.comp_mask || 3887 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3888 memchr_inv(&ucmd.burst_info.reserved, 0, 3889 sizeof(ucmd.burst_info.reserved))) 3890 return -EOPNOTSUPP; 3891 } 3892 3893 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3894 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3895 3896 if (ibqp->qp_type == IB_QPT_DRIVER) 3897 qp_type = qp->qp_sub_type; 3898 else 3899 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3900 IB_QPT_GSI : ibqp->qp_type; 3901 3902 if (qp_type == MLX5_IB_QPT_DCT) 3903 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3904 3905 mutex_lock(&qp->mutex); 3906 3907 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3908 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3909 3910 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3911 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3912 } 3913 3914 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3915 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3916 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3917 attr_mask); 3918 goto out; 3919 } 3920 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3921 qp_type != MLX5_IB_QPT_DCI && 3922 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 3923 attr_mask)) { 3924 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3925 cur_state, new_state, ibqp->qp_type, attr_mask); 3926 goto out; 3927 } else if (qp_type == MLX5_IB_QPT_DCI && 3928 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3929 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3930 cur_state, new_state, qp_type, attr_mask); 3931 goto out; 3932 } 3933 3934 if ((attr_mask & IB_QP_PORT) && 3935 (attr->port_num == 0 || 3936 attr->port_num > dev->num_ports)) { 3937 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3938 attr->port_num, dev->num_ports); 3939 goto out; 3940 } 3941 3942 if (attr_mask & IB_QP_PKEY_INDEX) { 3943 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3944 if (attr->pkey_index >= 3945 dev->mdev->port_caps[port - 1].pkey_table_len) { 3946 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3947 attr->pkey_index); 3948 goto out; 3949 } 3950 } 3951 3952 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3953 attr->max_rd_atomic > 3954 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3955 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3956 attr->max_rd_atomic); 3957 goto out; 3958 } 3959 3960 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3961 attr->max_dest_rd_atomic > 3962 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3963 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3964 attr->max_dest_rd_atomic); 3965 goto out; 3966 } 3967 3968 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3969 err = 0; 3970 goto out; 3971 } 3972 3973 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3974 new_state, &ucmd, udata); 3975 3976 out: 3977 mutex_unlock(&qp->mutex); 3978 return err; 3979 } 3980 3981 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3982 u32 wqe_sz, void **cur_edge) 3983 { 3984 u32 idx; 3985 3986 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); 3987 *cur_edge = get_sq_edge(sq, idx); 3988 3989 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); 3990 } 3991 3992 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the 3993 * next nearby edge and get new address translation for current WQE position. 3994 * @sq - SQ buffer. 3995 * @seg: Current WQE position (16B aligned). 3996 * @wqe_sz: Total current WQE size [16B]. 3997 * @cur_edge: Updated current edge. 3998 */ 3999 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 4000 u32 wqe_sz, void **cur_edge) 4001 { 4002 if (likely(*seg != *cur_edge)) 4003 return; 4004 4005 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); 4006 } 4007 4008 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's 4009 * pointers. At the end @seg is aligned to 16B regardless the copied size. 4010 * @sq - SQ buffer. 4011 * @cur_edge: Updated current edge. 4012 * @seg: Current WQE position (16B aligned). 4013 * @wqe_sz: Total current WQE size [16B]. 4014 * @src: Pointer to copy from. 4015 * @n: Number of bytes to copy. 4016 */ 4017 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, 4018 void **seg, u32 *wqe_sz, const void *src, 4019 size_t n) 4020 { 4021 while (likely(n)) { 4022 size_t leftlen = *cur_edge - *seg; 4023 size_t copysz = min_t(size_t, leftlen, n); 4024 size_t stride; 4025 4026 memcpy(*seg, src, copysz); 4027 4028 n -= copysz; 4029 src += copysz; 4030 stride = !n ? ALIGN(copysz, 16) : copysz; 4031 *seg += stride; 4032 *wqe_sz += stride >> 4; 4033 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); 4034 } 4035 } 4036 4037 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 4038 { 4039 struct mlx5_ib_cq *cq; 4040 unsigned cur; 4041 4042 cur = wq->head - wq->tail; 4043 if (likely(cur + nreq < wq->max_post)) 4044 return 0; 4045 4046 cq = to_mcq(ib_cq); 4047 spin_lock(&cq->lock); 4048 cur = wq->head - wq->tail; 4049 spin_unlock(&cq->lock); 4050 4051 return cur + nreq >= wq->max_post; 4052 } 4053 4054 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 4055 u64 remote_addr, u32 rkey) 4056 { 4057 rseg->raddr = cpu_to_be64(remote_addr); 4058 rseg->rkey = cpu_to_be32(rkey); 4059 rseg->reserved = 0; 4060 } 4061 4062 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 4063 void **seg, int *size, void **cur_edge) 4064 { 4065 struct mlx5_wqe_eth_seg *eseg = *seg; 4066 4067 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 4068 4069 if (wr->send_flags & IB_SEND_IP_CSUM) 4070 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 4071 MLX5_ETH_WQE_L4_CSUM; 4072 4073 if (wr->opcode == IB_WR_LSO) { 4074 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 4075 size_t left, copysz; 4076 void *pdata = ud_wr->header; 4077 size_t stride; 4078 4079 left = ud_wr->hlen; 4080 eseg->mss = cpu_to_be16(ud_wr->mss); 4081 eseg->inline_hdr.sz = cpu_to_be16(left); 4082 4083 /* memcpy_send_wqe should get a 16B align address. Hence, we 4084 * first copy up to the current edge and then, if needed, 4085 * fall-through to memcpy_send_wqe. 4086 */ 4087 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, 4088 left); 4089 memcpy(eseg->inline_hdr.start, pdata, copysz); 4090 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - 4091 sizeof(eseg->inline_hdr.start) + copysz, 16); 4092 *size += stride / 16; 4093 *seg += stride; 4094 4095 if (copysz < left) { 4096 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4097 left -= copysz; 4098 pdata += copysz; 4099 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, 4100 left); 4101 } 4102 4103 return; 4104 } 4105 4106 *seg += sizeof(struct mlx5_wqe_eth_seg); 4107 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 4108 } 4109 4110 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 4111 const struct ib_send_wr *wr) 4112 { 4113 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 4114 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 4115 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 4116 } 4117 4118 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 4119 { 4120 dseg->byte_count = cpu_to_be32(sg->length); 4121 dseg->lkey = cpu_to_be32(sg->lkey); 4122 dseg->addr = cpu_to_be64(sg->addr); 4123 } 4124 4125 static u64 get_xlt_octo(u64 bytes) 4126 { 4127 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 4128 MLX5_IB_UMR_OCTOWORD; 4129 } 4130 4131 static __be64 frwr_mkey_mask(void) 4132 { 4133 u64 result; 4134 4135 result = MLX5_MKEY_MASK_LEN | 4136 MLX5_MKEY_MASK_PAGE_SIZE | 4137 MLX5_MKEY_MASK_START_ADDR | 4138 MLX5_MKEY_MASK_EN_RINVAL | 4139 MLX5_MKEY_MASK_KEY | 4140 MLX5_MKEY_MASK_LR | 4141 MLX5_MKEY_MASK_LW | 4142 MLX5_MKEY_MASK_RR | 4143 MLX5_MKEY_MASK_RW | 4144 MLX5_MKEY_MASK_A | 4145 MLX5_MKEY_MASK_SMALL_FENCE | 4146 MLX5_MKEY_MASK_FREE; 4147 4148 return cpu_to_be64(result); 4149 } 4150 4151 static __be64 sig_mkey_mask(void) 4152 { 4153 u64 result; 4154 4155 result = MLX5_MKEY_MASK_LEN | 4156 MLX5_MKEY_MASK_PAGE_SIZE | 4157 MLX5_MKEY_MASK_START_ADDR | 4158 MLX5_MKEY_MASK_EN_SIGERR | 4159 MLX5_MKEY_MASK_EN_RINVAL | 4160 MLX5_MKEY_MASK_KEY | 4161 MLX5_MKEY_MASK_LR | 4162 MLX5_MKEY_MASK_LW | 4163 MLX5_MKEY_MASK_RR | 4164 MLX5_MKEY_MASK_RW | 4165 MLX5_MKEY_MASK_SMALL_FENCE | 4166 MLX5_MKEY_MASK_FREE | 4167 MLX5_MKEY_MASK_BSF_EN; 4168 4169 return cpu_to_be64(result); 4170 } 4171 4172 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 4173 struct mlx5_ib_mr *mr, bool umr_inline) 4174 { 4175 int size = mr->ndescs * mr->desc_size; 4176 4177 memset(umr, 0, sizeof(*umr)); 4178 4179 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 4180 if (umr_inline) 4181 umr->flags |= MLX5_UMR_INLINE; 4182 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4183 umr->mkey_mask = frwr_mkey_mask(); 4184 } 4185 4186 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 4187 { 4188 memset(umr, 0, sizeof(*umr)); 4189 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 4190 umr->flags = MLX5_UMR_INLINE; 4191 } 4192 4193 static __be64 get_umr_enable_mr_mask(void) 4194 { 4195 u64 result; 4196 4197 result = MLX5_MKEY_MASK_KEY | 4198 MLX5_MKEY_MASK_FREE; 4199 4200 return cpu_to_be64(result); 4201 } 4202 4203 static __be64 get_umr_disable_mr_mask(void) 4204 { 4205 u64 result; 4206 4207 result = MLX5_MKEY_MASK_FREE; 4208 4209 return cpu_to_be64(result); 4210 } 4211 4212 static __be64 get_umr_update_translation_mask(void) 4213 { 4214 u64 result; 4215 4216 result = MLX5_MKEY_MASK_LEN | 4217 MLX5_MKEY_MASK_PAGE_SIZE | 4218 MLX5_MKEY_MASK_START_ADDR; 4219 4220 return cpu_to_be64(result); 4221 } 4222 4223 static __be64 get_umr_update_access_mask(int atomic) 4224 { 4225 u64 result; 4226 4227 result = MLX5_MKEY_MASK_LR | 4228 MLX5_MKEY_MASK_LW | 4229 MLX5_MKEY_MASK_RR | 4230 MLX5_MKEY_MASK_RW; 4231 4232 if (atomic) 4233 result |= MLX5_MKEY_MASK_A; 4234 4235 return cpu_to_be64(result); 4236 } 4237 4238 static __be64 get_umr_update_pd_mask(void) 4239 { 4240 u64 result; 4241 4242 result = MLX5_MKEY_MASK_PD; 4243 4244 return cpu_to_be64(result); 4245 } 4246 4247 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 4248 { 4249 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 4250 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 4251 (mask & MLX5_MKEY_MASK_A && 4252 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 4253 return -EPERM; 4254 return 0; 4255 } 4256 4257 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 4258 struct mlx5_wqe_umr_ctrl_seg *umr, 4259 const struct ib_send_wr *wr, int atomic) 4260 { 4261 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4262 4263 memset(umr, 0, sizeof(*umr)); 4264 4265 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 4266 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 4267 else 4268 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 4269 4270 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 4271 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 4272 u64 offset = get_xlt_octo(umrwr->offset); 4273 4274 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 4275 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 4276 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 4277 } 4278 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 4279 umr->mkey_mask |= get_umr_update_translation_mask(); 4280 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 4281 umr->mkey_mask |= get_umr_update_access_mask(atomic); 4282 umr->mkey_mask |= get_umr_update_pd_mask(); 4283 } 4284 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 4285 umr->mkey_mask |= get_umr_enable_mr_mask(); 4286 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4287 umr->mkey_mask |= get_umr_disable_mr_mask(); 4288 4289 if (!wr->num_sge) 4290 umr->flags |= MLX5_UMR_INLINE; 4291 4292 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 4293 } 4294 4295 static u8 get_umr_flags(int acc) 4296 { 4297 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 4298 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 4299 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 4300 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 4301 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 4302 } 4303 4304 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 4305 struct mlx5_ib_mr *mr, 4306 u32 key, int access) 4307 { 4308 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 4309 4310 memset(seg, 0, sizeof(*seg)); 4311 4312 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 4313 seg->log2_page_size = ilog2(mr->ibmr.page_size); 4314 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 4315 /* KLMs take twice the size of MTTs */ 4316 ndescs *= 2; 4317 4318 seg->flags = get_umr_flags(access) | mr->access_mode; 4319 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 4320 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 4321 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 4322 seg->len = cpu_to_be64(mr->ibmr.length); 4323 seg->xlt_oct_size = cpu_to_be32(ndescs); 4324 } 4325 4326 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 4327 { 4328 memset(seg, 0, sizeof(*seg)); 4329 seg->status = MLX5_MKEY_STATUS_FREE; 4330 } 4331 4332 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, 4333 const struct ib_send_wr *wr) 4334 { 4335 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4336 4337 memset(seg, 0, sizeof(*seg)); 4338 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4339 seg->status = MLX5_MKEY_STATUS_FREE; 4340 4341 seg->flags = convert_access(umrwr->access_flags); 4342 if (umrwr->pd) 4343 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 4344 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 4345 !umrwr->length) 4346 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 4347 4348 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 4349 seg->len = cpu_to_be64(umrwr->length); 4350 seg->log2_page_size = umrwr->page_shift; 4351 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 4352 mlx5_mkey_variant(umrwr->mkey)); 4353 } 4354 4355 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 4356 struct mlx5_ib_mr *mr, 4357 struct mlx5_ib_pd *pd) 4358 { 4359 int bcount = mr->desc_size * mr->ndescs; 4360 4361 dseg->addr = cpu_to_be64(mr->desc_map); 4362 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 4363 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 4364 } 4365 4366 static __be32 send_ieth(const struct ib_send_wr *wr) 4367 { 4368 switch (wr->opcode) { 4369 case IB_WR_SEND_WITH_IMM: 4370 case IB_WR_RDMA_WRITE_WITH_IMM: 4371 return wr->ex.imm_data; 4372 4373 case IB_WR_SEND_WITH_INV: 4374 return cpu_to_be32(wr->ex.invalidate_rkey); 4375 4376 default: 4377 return 0; 4378 } 4379 } 4380 4381 static u8 calc_sig(void *wqe, int size) 4382 { 4383 u8 *p = wqe; 4384 u8 res = 0; 4385 int i; 4386 4387 for (i = 0; i < size; i++) 4388 res ^= p[i]; 4389 4390 return ~res; 4391 } 4392 4393 static u8 wq_sig(void *wqe) 4394 { 4395 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 4396 } 4397 4398 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 4399 void **wqe, int *wqe_sz, void **cur_edge) 4400 { 4401 struct mlx5_wqe_inline_seg *seg; 4402 size_t offset; 4403 int inl = 0; 4404 int i; 4405 4406 seg = *wqe; 4407 *wqe += sizeof(*seg); 4408 offset = sizeof(*seg); 4409 4410 for (i = 0; i < wr->num_sge; i++) { 4411 size_t len = wr->sg_list[i].length; 4412 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); 4413 4414 inl += len; 4415 4416 if (unlikely(inl > qp->max_inline_data)) 4417 return -ENOMEM; 4418 4419 while (likely(len)) { 4420 size_t leftlen; 4421 size_t copysz; 4422 4423 handle_post_send_edge(&qp->sq, wqe, 4424 *wqe_sz + (offset >> 4), 4425 cur_edge); 4426 4427 leftlen = *cur_edge - *wqe; 4428 copysz = min_t(size_t, leftlen, len); 4429 4430 memcpy(*wqe, addr, copysz); 4431 len -= copysz; 4432 addr += copysz; 4433 *wqe += copysz; 4434 offset += copysz; 4435 } 4436 } 4437 4438 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 4439 4440 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 4441 4442 return 0; 4443 } 4444 4445 static u16 prot_field_size(enum ib_signature_type type) 4446 { 4447 switch (type) { 4448 case IB_SIG_TYPE_T10_DIF: 4449 return MLX5_DIF_SIZE; 4450 default: 4451 return 0; 4452 } 4453 } 4454 4455 static u8 bs_selector(int block_size) 4456 { 4457 switch (block_size) { 4458 case 512: return 0x1; 4459 case 520: return 0x2; 4460 case 4096: return 0x3; 4461 case 4160: return 0x4; 4462 case 1073741824: return 0x5; 4463 default: return 0; 4464 } 4465 } 4466 4467 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 4468 struct mlx5_bsf_inl *inl) 4469 { 4470 /* Valid inline section and allow BSF refresh */ 4471 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 4472 MLX5_BSF_REFRESH_DIF); 4473 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 4474 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 4475 /* repeating block */ 4476 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 4477 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 4478 MLX5_DIF_CRC : MLX5_DIF_IPCS; 4479 4480 if (domain->sig.dif.ref_remap) 4481 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 4482 4483 if (domain->sig.dif.app_escape) { 4484 if (domain->sig.dif.ref_escape) 4485 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 4486 else 4487 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 4488 } 4489 4490 inl->dif_app_bitmask_check = 4491 cpu_to_be16(domain->sig.dif.apptag_check_mask); 4492 } 4493 4494 static int mlx5_set_bsf(struct ib_mr *sig_mr, 4495 struct ib_sig_attrs *sig_attrs, 4496 struct mlx5_bsf *bsf, u32 data_size) 4497 { 4498 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 4499 struct mlx5_bsf_basic *basic = &bsf->basic; 4500 struct ib_sig_domain *mem = &sig_attrs->mem; 4501 struct ib_sig_domain *wire = &sig_attrs->wire; 4502 4503 memset(bsf, 0, sizeof(*bsf)); 4504 4505 /* Basic + Extended + Inline */ 4506 basic->bsf_size_sbs = 1 << 7; 4507 /* Input domain check byte mask */ 4508 basic->check_byte_mask = sig_attrs->check_mask; 4509 basic->raw_data_size = cpu_to_be32(data_size); 4510 4511 /* Memory domain */ 4512 switch (sig_attrs->mem.sig_type) { 4513 case IB_SIG_TYPE_NONE: 4514 break; 4515 case IB_SIG_TYPE_T10_DIF: 4516 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4517 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4518 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4519 break; 4520 default: 4521 return -EINVAL; 4522 } 4523 4524 /* Wire domain */ 4525 switch (sig_attrs->wire.sig_type) { 4526 case IB_SIG_TYPE_NONE: 4527 break; 4528 case IB_SIG_TYPE_T10_DIF: 4529 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4530 mem->sig_type == wire->sig_type) { 4531 /* Same block structure */ 4532 basic->bsf_size_sbs |= 1 << 4; 4533 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4534 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4535 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4536 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4537 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4538 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4539 } else 4540 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4541 4542 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4543 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4544 break; 4545 default: 4546 return -EINVAL; 4547 } 4548 4549 return 0; 4550 } 4551 4552 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 4553 struct mlx5_ib_qp *qp, void **seg, 4554 int *size, void **cur_edge) 4555 { 4556 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4557 struct ib_mr *sig_mr = wr->sig_mr; 4558 struct mlx5_bsf *bsf; 4559 u32 data_len = wr->wr.sg_list->length; 4560 u32 data_key = wr->wr.sg_list->lkey; 4561 u64 data_va = wr->wr.sg_list->addr; 4562 int ret; 4563 int wqe_size; 4564 4565 if (!wr->prot || 4566 (data_key == wr->prot->lkey && 4567 data_va == wr->prot->addr && 4568 data_len == wr->prot->length)) { 4569 /** 4570 * Source domain doesn't contain signature information 4571 * or data and protection are interleaved in memory. 4572 * So need construct: 4573 * ------------------ 4574 * | data_klm | 4575 * ------------------ 4576 * | BSF | 4577 * ------------------ 4578 **/ 4579 struct mlx5_klm *data_klm = *seg; 4580 4581 data_klm->bcount = cpu_to_be32(data_len); 4582 data_klm->key = cpu_to_be32(data_key); 4583 data_klm->va = cpu_to_be64(data_va); 4584 wqe_size = ALIGN(sizeof(*data_klm), 64); 4585 } else { 4586 /** 4587 * Source domain contains signature information 4588 * So need construct a strided block format: 4589 * --------------------------- 4590 * | stride_block_ctrl | 4591 * --------------------------- 4592 * | data_klm | 4593 * --------------------------- 4594 * | prot_klm | 4595 * --------------------------- 4596 * | BSF | 4597 * --------------------------- 4598 **/ 4599 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4600 struct mlx5_stride_block_entry *data_sentry; 4601 struct mlx5_stride_block_entry *prot_sentry; 4602 u32 prot_key = wr->prot->lkey; 4603 u64 prot_va = wr->prot->addr; 4604 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4605 int prot_size; 4606 4607 sblock_ctrl = *seg; 4608 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4609 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4610 4611 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4612 if (!prot_size) { 4613 pr_err("Bad block size given: %u\n", block_size); 4614 return -EINVAL; 4615 } 4616 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4617 prot_size); 4618 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4619 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4620 sblock_ctrl->num_entries = cpu_to_be16(2); 4621 4622 data_sentry->bcount = cpu_to_be16(block_size); 4623 data_sentry->key = cpu_to_be32(data_key); 4624 data_sentry->va = cpu_to_be64(data_va); 4625 data_sentry->stride = cpu_to_be16(block_size); 4626 4627 prot_sentry->bcount = cpu_to_be16(prot_size); 4628 prot_sentry->key = cpu_to_be32(prot_key); 4629 prot_sentry->va = cpu_to_be64(prot_va); 4630 prot_sentry->stride = cpu_to_be16(prot_size); 4631 4632 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4633 sizeof(*prot_sentry), 64); 4634 } 4635 4636 *seg += wqe_size; 4637 *size += wqe_size / 16; 4638 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4639 4640 bsf = *seg; 4641 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4642 if (ret) 4643 return -EINVAL; 4644 4645 *seg += sizeof(*bsf); 4646 *size += sizeof(*bsf) / 16; 4647 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4648 4649 return 0; 4650 } 4651 4652 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4653 const struct ib_sig_handover_wr *wr, u32 size, 4654 u32 length, u32 pdn) 4655 { 4656 struct ib_mr *sig_mr = wr->sig_mr; 4657 u32 sig_key = sig_mr->rkey; 4658 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4659 4660 memset(seg, 0, sizeof(*seg)); 4661 4662 seg->flags = get_umr_flags(wr->access_flags) | 4663 MLX5_MKC_ACCESS_MODE_KLMS; 4664 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4665 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4666 MLX5_MKEY_BSF_EN | pdn); 4667 seg->len = cpu_to_be64(length); 4668 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4669 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4670 } 4671 4672 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4673 u32 size) 4674 { 4675 memset(umr, 0, sizeof(*umr)); 4676 4677 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4678 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4679 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4680 umr->mkey_mask = sig_mkey_mask(); 4681 } 4682 4683 4684 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, 4685 struct mlx5_ib_qp *qp, void **seg, int *size, 4686 void **cur_edge) 4687 { 4688 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4689 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4690 u32 pdn = get_pd(qp)->pdn; 4691 u32 xlt_size; 4692 int region_len, ret; 4693 4694 if (unlikely(wr->wr.num_sge != 1) || 4695 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4696 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4697 unlikely(!sig_mr->sig->sig_status_checked)) 4698 return -EINVAL; 4699 4700 /* length of the protected region, data + protection */ 4701 region_len = wr->wr.sg_list->length; 4702 if (wr->prot && 4703 (wr->prot->lkey != wr->wr.sg_list->lkey || 4704 wr->prot->addr != wr->wr.sg_list->addr || 4705 wr->prot->length != wr->wr.sg_list->length)) 4706 region_len += wr->prot->length; 4707 4708 /** 4709 * KLM octoword size - if protection was provided 4710 * then we use strided block format (3 octowords), 4711 * else we use single KLM (1 octoword) 4712 **/ 4713 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4714 4715 set_sig_umr_segment(*seg, xlt_size); 4716 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4717 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4718 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4719 4720 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4721 *seg += sizeof(struct mlx5_mkey_seg); 4722 *size += sizeof(struct mlx5_mkey_seg) / 16; 4723 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4724 4725 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge); 4726 if (ret) 4727 return ret; 4728 4729 sig_mr->sig->sig_status_checked = false; 4730 return 0; 4731 } 4732 4733 static int set_psv_wr(struct ib_sig_domain *domain, 4734 u32 psv_idx, void **seg, int *size) 4735 { 4736 struct mlx5_seg_set_psv *psv_seg = *seg; 4737 4738 memset(psv_seg, 0, sizeof(*psv_seg)); 4739 psv_seg->psv_num = cpu_to_be32(psv_idx); 4740 switch (domain->sig_type) { 4741 case IB_SIG_TYPE_NONE: 4742 break; 4743 case IB_SIG_TYPE_T10_DIF: 4744 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4745 domain->sig.dif.app_tag); 4746 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4747 break; 4748 default: 4749 pr_err("Bad signature type (%d) is given.\n", 4750 domain->sig_type); 4751 return -EINVAL; 4752 } 4753 4754 *seg += sizeof(*psv_seg); 4755 *size += sizeof(*psv_seg) / 16; 4756 4757 return 0; 4758 } 4759 4760 static int set_reg_wr(struct mlx5_ib_qp *qp, 4761 const struct ib_reg_wr *wr, 4762 void **seg, int *size, void **cur_edge) 4763 { 4764 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4765 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4766 size_t mr_list_size = mr->ndescs * mr->desc_size; 4767 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4768 4769 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4770 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4771 "Invalid IB_SEND_INLINE send flag\n"); 4772 return -EINVAL; 4773 } 4774 4775 set_reg_umr_seg(*seg, mr, umr_inline); 4776 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4777 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4778 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4779 4780 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4781 *seg += sizeof(struct mlx5_mkey_seg); 4782 *size += sizeof(struct mlx5_mkey_seg) / 16; 4783 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4784 4785 if (umr_inline) { 4786 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, 4787 mr_list_size); 4788 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); 4789 } else { 4790 set_reg_data_seg(*seg, mr, pd); 4791 *seg += sizeof(struct mlx5_wqe_data_seg); 4792 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4793 } 4794 return 0; 4795 } 4796 4797 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, 4798 void **cur_edge) 4799 { 4800 set_linv_umr_seg(*seg); 4801 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4802 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4803 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4804 set_linv_mkey_seg(*seg); 4805 *seg += sizeof(struct mlx5_mkey_seg); 4806 *size += sizeof(struct mlx5_mkey_seg) / 16; 4807 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4808 } 4809 4810 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) 4811 { 4812 __be32 *p = NULL; 4813 int i, j; 4814 4815 pr_debug("dump WQE index %u:\n", idx); 4816 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4817 if ((i & 0xf) == 0) { 4818 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx); 4819 pr_debug("WQBB at %p:\n", (void *)p); 4820 j = 0; 4821 idx = (idx + 1) & (qp->sq.wqe_cnt - 1); 4822 } 4823 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4824 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4825 be32_to_cpu(p[j + 3])); 4826 } 4827 } 4828 4829 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4830 struct mlx5_wqe_ctrl_seg **ctrl, 4831 const struct ib_send_wr *wr, unsigned int *idx, 4832 int *size, void **cur_edge, int nreq, 4833 bool send_signaled, bool solicited) 4834 { 4835 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4836 return -ENOMEM; 4837 4838 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4839 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); 4840 *ctrl = *seg; 4841 *(uint32_t *)(*seg + 8) = 0; 4842 (*ctrl)->imm = send_ieth(wr); 4843 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4844 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4845 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 4846 4847 *seg += sizeof(**ctrl); 4848 *size = sizeof(**ctrl) / 16; 4849 *cur_edge = qp->sq.cur_edge; 4850 4851 return 0; 4852 } 4853 4854 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4855 struct mlx5_wqe_ctrl_seg **ctrl, 4856 const struct ib_send_wr *wr, unsigned *idx, 4857 int *size, void **cur_edge, int nreq) 4858 { 4859 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, 4860 wr->send_flags & IB_SEND_SIGNALED, 4861 wr->send_flags & IB_SEND_SOLICITED); 4862 } 4863 4864 static void finish_wqe(struct mlx5_ib_qp *qp, 4865 struct mlx5_wqe_ctrl_seg *ctrl, 4866 void *seg, u8 size, void *cur_edge, 4867 unsigned int idx, u64 wr_id, int nreq, u8 fence, 4868 u32 mlx5_opcode) 4869 { 4870 u8 opmod = 0; 4871 4872 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4873 mlx5_opcode | ((u32)opmod << 24)); 4874 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4875 ctrl->fm_ce_se |= fence; 4876 if (unlikely(qp->wq_sig)) 4877 ctrl->signature = wq_sig(ctrl); 4878 4879 qp->sq.wrid[idx] = wr_id; 4880 qp->sq.w_list[idx].opcode = mlx5_opcode; 4881 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4882 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4883 qp->sq.w_list[idx].next = qp->sq.cur_post; 4884 4885 /* We save the edge which was possibly updated during the WQE 4886 * construction, into SQ's cache. 4887 */ 4888 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); 4889 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? 4890 get_sq_edge(&qp->sq, qp->sq.cur_post & 4891 (qp->sq.wqe_cnt - 1)) : 4892 cur_edge; 4893 } 4894 4895 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 4896 const struct ib_send_wr **bad_wr, bool drain) 4897 { 4898 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4899 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4900 struct mlx5_core_dev *mdev = dev->mdev; 4901 struct mlx5_ib_qp *qp; 4902 struct mlx5_ib_mr *mr; 4903 struct mlx5_wqe_xrc_seg *xrc; 4904 struct mlx5_bf *bf; 4905 void *cur_edge; 4906 int uninitialized_var(size); 4907 unsigned long flags; 4908 unsigned idx; 4909 int err = 0; 4910 int num_sge; 4911 void *seg; 4912 int nreq; 4913 int i; 4914 u8 next_fence = 0; 4915 u8 fence; 4916 4917 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 4918 !drain)) { 4919 *bad_wr = wr; 4920 return -EIO; 4921 } 4922 4923 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4924 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4925 4926 qp = to_mqp(ibqp); 4927 bf = &qp->bf; 4928 4929 spin_lock_irqsave(&qp->sq.lock, flags); 4930 4931 for (nreq = 0; wr; nreq++, wr = wr->next) { 4932 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4933 mlx5_ib_warn(dev, "\n"); 4934 err = -EINVAL; 4935 *bad_wr = wr; 4936 goto out; 4937 } 4938 4939 num_sge = wr->num_sge; 4940 if (unlikely(num_sge > qp->sq.max_gs)) { 4941 mlx5_ib_warn(dev, "\n"); 4942 err = -EINVAL; 4943 *bad_wr = wr; 4944 goto out; 4945 } 4946 4947 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, 4948 nreq); 4949 if (err) { 4950 mlx5_ib_warn(dev, "\n"); 4951 err = -ENOMEM; 4952 *bad_wr = wr; 4953 goto out; 4954 } 4955 4956 if (wr->opcode == IB_WR_REG_MR) { 4957 fence = dev->umr_fence; 4958 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4959 } else { 4960 if (wr->send_flags & IB_SEND_FENCE) { 4961 if (qp->next_fence) 4962 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4963 else 4964 fence = MLX5_FENCE_MODE_FENCE; 4965 } else { 4966 fence = qp->next_fence; 4967 } 4968 } 4969 4970 switch (ibqp->qp_type) { 4971 case IB_QPT_XRC_INI: 4972 xrc = seg; 4973 seg += sizeof(*xrc); 4974 size += sizeof(*xrc) / 16; 4975 /* fall through */ 4976 case IB_QPT_RC: 4977 switch (wr->opcode) { 4978 case IB_WR_RDMA_READ: 4979 case IB_WR_RDMA_WRITE: 4980 case IB_WR_RDMA_WRITE_WITH_IMM: 4981 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4982 rdma_wr(wr)->rkey); 4983 seg += sizeof(struct mlx5_wqe_raddr_seg); 4984 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4985 break; 4986 4987 case IB_WR_ATOMIC_CMP_AND_SWP: 4988 case IB_WR_ATOMIC_FETCH_AND_ADD: 4989 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4990 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4991 err = -ENOSYS; 4992 *bad_wr = wr; 4993 goto out; 4994 4995 case IB_WR_LOCAL_INV: 4996 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4997 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4998 set_linv_wr(qp, &seg, &size, &cur_edge); 4999 num_sge = 0; 5000 break; 5001 5002 case IB_WR_REG_MR: 5003 qp->sq.wr_data[idx] = IB_WR_REG_MR; 5004 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 5005 err = set_reg_wr(qp, reg_wr(wr), &seg, &size, 5006 &cur_edge); 5007 if (err) { 5008 *bad_wr = wr; 5009 goto out; 5010 } 5011 num_sge = 0; 5012 break; 5013 5014 case IB_WR_REG_SIG_MR: 5015 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 5016 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 5017 5018 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 5019 err = set_sig_umr_wr(wr, qp, &seg, &size, 5020 &cur_edge); 5021 if (err) { 5022 mlx5_ib_warn(dev, "\n"); 5023 *bad_wr = wr; 5024 goto out; 5025 } 5026 5027 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5028 wr->wr_id, nreq, fence, 5029 MLX5_OPCODE_UMR); 5030 /* 5031 * SET_PSV WQEs are not signaled and solicited 5032 * on error 5033 */ 5034 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 5035 &size, &cur_edge, nreq, false, 5036 true); 5037 if (err) { 5038 mlx5_ib_warn(dev, "\n"); 5039 err = -ENOMEM; 5040 *bad_wr = wr; 5041 goto out; 5042 } 5043 5044 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 5045 mr->sig->psv_memory.psv_idx, &seg, 5046 &size); 5047 if (err) { 5048 mlx5_ib_warn(dev, "\n"); 5049 *bad_wr = wr; 5050 goto out; 5051 } 5052 5053 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5054 wr->wr_id, nreq, fence, 5055 MLX5_OPCODE_SET_PSV); 5056 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 5057 &size, &cur_edge, nreq, false, 5058 true); 5059 if (err) { 5060 mlx5_ib_warn(dev, "\n"); 5061 err = -ENOMEM; 5062 *bad_wr = wr; 5063 goto out; 5064 } 5065 5066 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 5067 mr->sig->psv_wire.psv_idx, &seg, 5068 &size); 5069 if (err) { 5070 mlx5_ib_warn(dev, "\n"); 5071 *bad_wr = wr; 5072 goto out; 5073 } 5074 5075 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 5076 wr->wr_id, nreq, fence, 5077 MLX5_OPCODE_SET_PSV); 5078 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 5079 num_sge = 0; 5080 goto skip_psv; 5081 5082 default: 5083 break; 5084 } 5085 break; 5086 5087 case IB_QPT_UC: 5088 switch (wr->opcode) { 5089 case IB_WR_RDMA_WRITE: 5090 case IB_WR_RDMA_WRITE_WITH_IMM: 5091 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 5092 rdma_wr(wr)->rkey); 5093 seg += sizeof(struct mlx5_wqe_raddr_seg); 5094 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 5095 break; 5096 5097 default: 5098 break; 5099 } 5100 break; 5101 5102 case IB_QPT_SMI: 5103 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 5104 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 5105 err = -EPERM; 5106 *bad_wr = wr; 5107 goto out; 5108 } 5109 /* fall through */ 5110 case MLX5_IB_QPT_HW_GSI: 5111 set_datagram_seg(seg, wr); 5112 seg += sizeof(struct mlx5_wqe_datagram_seg); 5113 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5114 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5115 5116 break; 5117 case IB_QPT_UD: 5118 set_datagram_seg(seg, wr); 5119 seg += sizeof(struct mlx5_wqe_datagram_seg); 5120 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 5121 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5122 5123 /* handle qp that supports ud offload */ 5124 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 5125 struct mlx5_wqe_eth_pad *pad; 5126 5127 pad = seg; 5128 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 5129 seg += sizeof(struct mlx5_wqe_eth_pad); 5130 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 5131 set_eth_seg(wr, qp, &seg, &size, &cur_edge); 5132 handle_post_send_edge(&qp->sq, &seg, size, 5133 &cur_edge); 5134 } 5135 break; 5136 case MLX5_IB_QPT_REG_UMR: 5137 if (wr->opcode != MLX5_IB_WR_UMR) { 5138 err = -EINVAL; 5139 mlx5_ib_warn(dev, "bad opcode\n"); 5140 goto out; 5141 } 5142 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 5143 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 5144 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 5145 if (unlikely(err)) 5146 goto out; 5147 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 5148 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 5149 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5150 set_reg_mkey_segment(seg, wr); 5151 seg += sizeof(struct mlx5_mkey_seg); 5152 size += sizeof(struct mlx5_mkey_seg) / 16; 5153 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 5154 break; 5155 5156 default: 5157 break; 5158 } 5159 5160 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 5161 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); 5162 if (unlikely(err)) { 5163 mlx5_ib_warn(dev, "\n"); 5164 *bad_wr = wr; 5165 goto out; 5166 } 5167 } else { 5168 for (i = 0; i < num_sge; i++) { 5169 handle_post_send_edge(&qp->sq, &seg, size, 5170 &cur_edge); 5171 if (likely(wr->sg_list[i].length)) { 5172 set_data_ptr_seg 5173 ((struct mlx5_wqe_data_seg *)seg, 5174 wr->sg_list + i); 5175 size += sizeof(struct mlx5_wqe_data_seg) / 16; 5176 seg += sizeof(struct mlx5_wqe_data_seg); 5177 } 5178 } 5179 } 5180 5181 qp->next_fence = next_fence; 5182 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, 5183 fence, mlx5_ib_opcode[wr->opcode]); 5184 skip_psv: 5185 if (0) 5186 dump_wqe(qp, idx, size); 5187 } 5188 5189 out: 5190 if (likely(nreq)) { 5191 qp->sq.head += nreq; 5192 5193 /* Make sure that descriptors are written before 5194 * updating doorbell record and ringing the doorbell 5195 */ 5196 wmb(); 5197 5198 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 5199 5200 /* Make sure doorbell record is visible to the HCA before 5201 * we hit doorbell */ 5202 wmb(); 5203 5204 /* currently we support only regular doorbells */ 5205 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset); 5206 /* Make sure doorbells don't leak out of SQ spinlock 5207 * and reach the HCA out of order. 5208 */ 5209 bf->offset ^= bf->buf_size; 5210 } 5211 5212 spin_unlock_irqrestore(&qp->sq.lock, flags); 5213 5214 return err; 5215 } 5216 5217 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5218 const struct ib_send_wr **bad_wr) 5219 { 5220 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); 5221 } 5222 5223 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 5224 { 5225 sig->signature = calc_sig(sig, size); 5226 } 5227 5228 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5229 const struct ib_recv_wr **bad_wr, bool drain) 5230 { 5231 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5232 struct mlx5_wqe_data_seg *scat; 5233 struct mlx5_rwqe_sig *sig; 5234 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5235 struct mlx5_core_dev *mdev = dev->mdev; 5236 unsigned long flags; 5237 int err = 0; 5238 int nreq; 5239 int ind; 5240 int i; 5241 5242 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5243 !drain)) { 5244 *bad_wr = wr; 5245 return -EIO; 5246 } 5247 5248 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5249 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 5250 5251 spin_lock_irqsave(&qp->rq.lock, flags); 5252 5253 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 5254 5255 for (nreq = 0; wr; nreq++, wr = wr->next) { 5256 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 5257 err = -ENOMEM; 5258 *bad_wr = wr; 5259 goto out; 5260 } 5261 5262 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 5263 err = -EINVAL; 5264 *bad_wr = wr; 5265 goto out; 5266 } 5267 5268 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); 5269 if (qp->wq_sig) 5270 scat++; 5271 5272 for (i = 0; i < wr->num_sge; i++) 5273 set_data_ptr_seg(scat + i, wr->sg_list + i); 5274 5275 if (i < qp->rq.max_gs) { 5276 scat[i].byte_count = 0; 5277 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 5278 scat[i].addr = 0; 5279 } 5280 5281 if (qp->wq_sig) { 5282 sig = (struct mlx5_rwqe_sig *)scat; 5283 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 5284 } 5285 5286 qp->rq.wrid[ind] = wr->wr_id; 5287 5288 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 5289 } 5290 5291 out: 5292 if (likely(nreq)) { 5293 qp->rq.head += nreq; 5294 5295 /* Make sure that descriptors are written before 5296 * doorbell record. 5297 */ 5298 wmb(); 5299 5300 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 5301 } 5302 5303 spin_unlock_irqrestore(&qp->rq.lock, flags); 5304 5305 return err; 5306 } 5307 5308 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5309 const struct ib_recv_wr **bad_wr) 5310 { 5311 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); 5312 } 5313 5314 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 5315 { 5316 switch (mlx5_state) { 5317 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 5318 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 5319 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 5320 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 5321 case MLX5_QP_STATE_SQ_DRAINING: 5322 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 5323 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 5324 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 5325 default: return -1; 5326 } 5327 } 5328 5329 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 5330 { 5331 switch (mlx5_mig_state) { 5332 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 5333 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 5334 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 5335 default: return -1; 5336 } 5337 } 5338 5339 static int to_ib_qp_access_flags(int mlx5_flags) 5340 { 5341 int ib_flags = 0; 5342 5343 if (mlx5_flags & MLX5_QP_BIT_RRE) 5344 ib_flags |= IB_ACCESS_REMOTE_READ; 5345 if (mlx5_flags & MLX5_QP_BIT_RWE) 5346 ib_flags |= IB_ACCESS_REMOTE_WRITE; 5347 if (mlx5_flags & MLX5_QP_BIT_RAE) 5348 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 5349 5350 return ib_flags; 5351 } 5352 5353 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 5354 struct rdma_ah_attr *ah_attr, 5355 struct mlx5_qp_path *path) 5356 { 5357 5358 memset(ah_attr, 0, sizeof(*ah_attr)); 5359 5360 if (!path->port || path->port > ibdev->num_ports) 5361 return; 5362 5363 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 5364 5365 rdma_ah_set_port_num(ah_attr, path->port); 5366 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 5367 5368 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 5369 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 5370 rdma_ah_set_static_rate(ah_attr, 5371 path->static_rate ? path->static_rate - 5 : 0); 5372 if (path->grh_mlid & (1 << 7)) { 5373 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 5374 5375 rdma_ah_set_grh(ah_attr, NULL, 5376 tc_fl & 0xfffff, 5377 path->mgid_index, 5378 path->hop_limit, 5379 (tc_fl >> 20) & 0xff); 5380 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 5381 } 5382 } 5383 5384 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 5385 struct mlx5_ib_sq *sq, 5386 u8 *sq_state) 5387 { 5388 int err; 5389 5390 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 5391 if (err) 5392 goto out; 5393 sq->state = *sq_state; 5394 5395 out: 5396 return err; 5397 } 5398 5399 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 5400 struct mlx5_ib_rq *rq, 5401 u8 *rq_state) 5402 { 5403 void *out; 5404 void *rqc; 5405 int inlen; 5406 int err; 5407 5408 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 5409 out = kvzalloc(inlen, GFP_KERNEL); 5410 if (!out) 5411 return -ENOMEM; 5412 5413 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 5414 if (err) 5415 goto out; 5416 5417 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 5418 *rq_state = MLX5_GET(rqc, rqc, state); 5419 rq->state = *rq_state; 5420 5421 out: 5422 kvfree(out); 5423 return err; 5424 } 5425 5426 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 5427 struct mlx5_ib_qp *qp, u8 *qp_state) 5428 { 5429 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 5430 [MLX5_RQC_STATE_RST] = { 5431 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5432 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5433 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 5434 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 5435 }, 5436 [MLX5_RQC_STATE_RDY] = { 5437 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5438 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5439 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 5440 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 5441 }, 5442 [MLX5_RQC_STATE_ERR] = { 5443 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5444 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5445 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 5446 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 5447 }, 5448 [MLX5_RQ_STATE_NA] = { 5449 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5450 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5451 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 5452 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 5453 }, 5454 }; 5455 5456 *qp_state = sqrq_trans[rq_state][sq_state]; 5457 5458 if (*qp_state == MLX5_QP_STATE_BAD) { 5459 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 5460 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 5461 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 5462 return -EINVAL; 5463 } 5464 5465 if (*qp_state == MLX5_QP_STATE) 5466 *qp_state = qp->state; 5467 5468 return 0; 5469 } 5470 5471 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 5472 struct mlx5_ib_qp *qp, 5473 u8 *raw_packet_qp_state) 5474 { 5475 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 5476 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 5477 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 5478 int err; 5479 u8 sq_state = MLX5_SQ_STATE_NA; 5480 u8 rq_state = MLX5_RQ_STATE_NA; 5481 5482 if (qp->sq.wqe_cnt) { 5483 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 5484 if (err) 5485 return err; 5486 } 5487 5488 if (qp->rq.wqe_cnt) { 5489 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 5490 if (err) 5491 return err; 5492 } 5493 5494 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 5495 raw_packet_qp_state); 5496 } 5497 5498 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 5499 struct ib_qp_attr *qp_attr) 5500 { 5501 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 5502 struct mlx5_qp_context *context; 5503 int mlx5_state; 5504 u32 *outb; 5505 int err = 0; 5506 5507 outb = kzalloc(outlen, GFP_KERNEL); 5508 if (!outb) 5509 return -ENOMEM; 5510 5511 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 5512 outlen); 5513 if (err) 5514 goto out; 5515 5516 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 5517 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 5518 5519 mlx5_state = be32_to_cpu(context->flags) >> 28; 5520 5521 qp->state = to_ib_qp_state(mlx5_state); 5522 qp_attr->path_mtu = context->mtu_msgmax >> 5; 5523 qp_attr->path_mig_state = 5524 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 5525 qp_attr->qkey = be32_to_cpu(context->qkey); 5526 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 5527 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 5528 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 5529 qp_attr->qp_access_flags = 5530 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 5531 5532 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 5533 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 5534 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5535 qp_attr->alt_pkey_index = 5536 be16_to_cpu(context->alt_path.pkey_index); 5537 qp_attr->alt_port_num = 5538 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5539 } 5540 5541 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5542 qp_attr->port_num = context->pri_path.port; 5543 5544 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5545 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5546 5547 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5548 5549 qp_attr->max_dest_rd_atomic = 5550 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5551 qp_attr->min_rnr_timer = 5552 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5553 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5554 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5555 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5556 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5557 5558 out: 5559 kfree(outb); 5560 return err; 5561 } 5562 5563 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5564 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5565 struct ib_qp_init_attr *qp_init_attr) 5566 { 5567 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5568 u32 *out; 5569 u32 access_flags = 0; 5570 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5571 void *dctc; 5572 int err; 5573 int supported_mask = IB_QP_STATE | 5574 IB_QP_ACCESS_FLAGS | 5575 IB_QP_PORT | 5576 IB_QP_MIN_RNR_TIMER | 5577 IB_QP_AV | 5578 IB_QP_PATH_MTU | 5579 IB_QP_PKEY_INDEX; 5580 5581 if (qp_attr_mask & ~supported_mask) 5582 return -EINVAL; 5583 if (mqp->state != IB_QPS_RTR) 5584 return -EINVAL; 5585 5586 out = kzalloc(outlen, GFP_KERNEL); 5587 if (!out) 5588 return -ENOMEM; 5589 5590 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5591 if (err) 5592 goto out; 5593 5594 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5595 5596 if (qp_attr_mask & IB_QP_STATE) 5597 qp_attr->qp_state = IB_QPS_RTR; 5598 5599 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5600 if (MLX5_GET(dctc, dctc, rre)) 5601 access_flags |= IB_ACCESS_REMOTE_READ; 5602 if (MLX5_GET(dctc, dctc, rwe)) 5603 access_flags |= IB_ACCESS_REMOTE_WRITE; 5604 if (MLX5_GET(dctc, dctc, rae)) 5605 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5606 qp_attr->qp_access_flags = access_flags; 5607 } 5608 5609 if (qp_attr_mask & IB_QP_PORT) 5610 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5611 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5612 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5613 if (qp_attr_mask & IB_QP_AV) { 5614 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5615 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5616 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5617 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5618 } 5619 if (qp_attr_mask & IB_QP_PATH_MTU) 5620 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5621 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5622 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5623 out: 5624 kfree(out); 5625 return err; 5626 } 5627 5628 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5629 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5630 { 5631 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5632 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5633 int err = 0; 5634 u8 raw_packet_qp_state; 5635 5636 if (ibqp->rwq_ind_tbl) 5637 return -ENOSYS; 5638 5639 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5640 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5641 qp_init_attr); 5642 5643 /* Not all of output fields are applicable, make sure to zero them */ 5644 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5645 memset(qp_attr, 0, sizeof(*qp_attr)); 5646 5647 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5648 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5649 qp_attr_mask, qp_init_attr); 5650 5651 mutex_lock(&qp->mutex); 5652 5653 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5654 qp->flags & MLX5_IB_QP_UNDERLAY) { 5655 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5656 if (err) 5657 goto out; 5658 qp->state = raw_packet_qp_state; 5659 qp_attr->port_num = 1; 5660 } else { 5661 err = query_qp_attr(dev, qp, qp_attr); 5662 if (err) 5663 goto out; 5664 } 5665 5666 qp_attr->qp_state = qp->state; 5667 qp_attr->cur_qp_state = qp_attr->qp_state; 5668 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5669 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5670 5671 if (!ibqp->uobject) { 5672 qp_attr->cap.max_send_wr = qp->sq.max_post; 5673 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5674 qp_init_attr->qp_context = ibqp->qp_context; 5675 } else { 5676 qp_attr->cap.max_send_wr = 0; 5677 qp_attr->cap.max_send_sge = 0; 5678 } 5679 5680 qp_init_attr->qp_type = ibqp->qp_type; 5681 qp_init_attr->recv_cq = ibqp->recv_cq; 5682 qp_init_attr->send_cq = ibqp->send_cq; 5683 qp_init_attr->srq = ibqp->srq; 5684 qp_attr->cap.max_inline_data = qp->max_inline_data; 5685 5686 qp_init_attr->cap = qp_attr->cap; 5687 5688 qp_init_attr->create_flags = 0; 5689 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5690 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5691 5692 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5693 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5694 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5695 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5696 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5697 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5698 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5699 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5700 5701 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5702 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5703 5704 out: 5705 mutex_unlock(&qp->mutex); 5706 return err; 5707 } 5708 5709 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5710 struct ib_udata *udata) 5711 { 5712 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5713 struct mlx5_ib_xrcd *xrcd; 5714 int err; 5715 5716 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5717 return ERR_PTR(-ENOSYS); 5718 5719 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5720 if (!xrcd) 5721 return ERR_PTR(-ENOMEM); 5722 5723 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5724 if (err) { 5725 kfree(xrcd); 5726 return ERR_PTR(-ENOMEM); 5727 } 5728 5729 return &xrcd->ibxrcd; 5730 } 5731 5732 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5733 { 5734 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5735 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5736 int err; 5737 5738 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5739 if (err) 5740 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5741 5742 kfree(xrcd); 5743 return 0; 5744 } 5745 5746 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5747 { 5748 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5749 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5750 struct ib_event event; 5751 5752 if (rwq->ibwq.event_handler) { 5753 event.device = rwq->ibwq.device; 5754 event.element.wq = &rwq->ibwq; 5755 switch (type) { 5756 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5757 event.event = IB_EVENT_WQ_FATAL; 5758 break; 5759 default: 5760 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5761 return; 5762 } 5763 5764 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5765 } 5766 } 5767 5768 static int set_delay_drop(struct mlx5_ib_dev *dev) 5769 { 5770 int err = 0; 5771 5772 mutex_lock(&dev->delay_drop.lock); 5773 if (dev->delay_drop.activate) 5774 goto out; 5775 5776 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5777 if (err) 5778 goto out; 5779 5780 dev->delay_drop.activate = true; 5781 out: 5782 mutex_unlock(&dev->delay_drop.lock); 5783 5784 if (!err) 5785 atomic_inc(&dev->delay_drop.rqs_cnt); 5786 return err; 5787 } 5788 5789 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5790 struct ib_wq_init_attr *init_attr) 5791 { 5792 struct mlx5_ib_dev *dev; 5793 int has_net_offloads; 5794 __be64 *rq_pas0; 5795 void *in; 5796 void *rqc; 5797 void *wq; 5798 int inlen; 5799 int err; 5800 5801 dev = to_mdev(pd->device); 5802 5803 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5804 in = kvzalloc(inlen, GFP_KERNEL); 5805 if (!in) 5806 return -ENOMEM; 5807 5808 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5809 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5810 MLX5_SET(rqc, rqc, mem_rq_type, 5811 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5812 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5813 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5814 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5815 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5816 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5817 MLX5_SET(wq, wq, wq_type, 5818 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5819 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5820 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5821 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5822 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5823 err = -EOPNOTSUPP; 5824 goto out; 5825 } else { 5826 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5827 } 5828 } 5829 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5830 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5831 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5832 MLX5_SET(wq, wq, log_wqe_stride_size, 5833 rwq->single_stride_log_num_of_bytes - 5834 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5835 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5836 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5837 } 5838 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5839 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5840 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5841 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5842 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5843 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5844 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5845 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5846 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5847 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5848 err = -EOPNOTSUPP; 5849 goto out; 5850 } 5851 } else { 5852 MLX5_SET(rqc, rqc, vsd, 1); 5853 } 5854 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5855 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5856 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5857 err = -EOPNOTSUPP; 5858 goto out; 5859 } 5860 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5861 } 5862 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5863 if (!(dev->ib_dev.attrs.raw_packet_caps & 5864 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5865 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5866 err = -EOPNOTSUPP; 5867 goto out; 5868 } 5869 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5870 } 5871 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5872 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5873 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5874 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5875 err = set_delay_drop(dev); 5876 if (err) { 5877 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5878 err); 5879 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5880 } else { 5881 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5882 } 5883 } 5884 out: 5885 kvfree(in); 5886 return err; 5887 } 5888 5889 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5890 struct ib_wq_init_attr *wq_init_attr, 5891 struct mlx5_ib_create_wq *ucmd, 5892 struct mlx5_ib_rwq *rwq) 5893 { 5894 /* Sanity check RQ size before proceeding */ 5895 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5896 return -EINVAL; 5897 5898 if (!ucmd->rq_wqe_count) 5899 return -EINVAL; 5900 5901 rwq->wqe_count = ucmd->rq_wqe_count; 5902 rwq->wqe_shift = ucmd->rq_wqe_shift; 5903 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5904 return -EINVAL; 5905 5906 rwq->log_rq_stride = rwq->wqe_shift; 5907 rwq->log_rq_size = ilog2(rwq->wqe_count); 5908 return 0; 5909 } 5910 5911 static int prepare_user_rq(struct ib_pd *pd, 5912 struct ib_wq_init_attr *init_attr, 5913 struct ib_udata *udata, 5914 struct mlx5_ib_rwq *rwq) 5915 { 5916 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5917 struct mlx5_ib_create_wq ucmd = {}; 5918 int err; 5919 size_t required_cmd_sz; 5920 5921 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5922 + sizeof(ucmd.single_stride_log_num_of_bytes); 5923 if (udata->inlen < required_cmd_sz) { 5924 mlx5_ib_dbg(dev, "invalid inlen\n"); 5925 return -EINVAL; 5926 } 5927 5928 if (udata->inlen > sizeof(ucmd) && 5929 !ib_is_udata_cleared(udata, sizeof(ucmd), 5930 udata->inlen - sizeof(ucmd))) { 5931 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5932 return -EOPNOTSUPP; 5933 } 5934 5935 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5936 mlx5_ib_dbg(dev, "copy failed\n"); 5937 return -EFAULT; 5938 } 5939 5940 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5941 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5942 return -EOPNOTSUPP; 5943 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5944 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5945 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5946 return -EOPNOTSUPP; 5947 } 5948 if ((ucmd.single_stride_log_num_of_bytes < 5949 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5950 (ucmd.single_stride_log_num_of_bytes > 5951 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5952 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5953 ucmd.single_stride_log_num_of_bytes, 5954 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5955 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5956 return -EINVAL; 5957 } 5958 if ((ucmd.single_wqe_log_num_of_strides > 5959 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5960 (ucmd.single_wqe_log_num_of_strides < 5961 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5962 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5963 ucmd.single_wqe_log_num_of_strides, 5964 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5965 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5966 return -EINVAL; 5967 } 5968 rwq->single_stride_log_num_of_bytes = 5969 ucmd.single_stride_log_num_of_bytes; 5970 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5971 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5972 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5973 } 5974 5975 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5976 if (err) { 5977 mlx5_ib_dbg(dev, "err %d\n", err); 5978 return err; 5979 } 5980 5981 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5982 if (err) { 5983 mlx5_ib_dbg(dev, "err %d\n", err); 5984 return err; 5985 } 5986 5987 rwq->user_index = ucmd.user_index; 5988 return 0; 5989 } 5990 5991 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5992 struct ib_wq_init_attr *init_attr, 5993 struct ib_udata *udata) 5994 { 5995 struct mlx5_ib_dev *dev; 5996 struct mlx5_ib_rwq *rwq; 5997 struct mlx5_ib_create_wq_resp resp = {}; 5998 size_t min_resp_len; 5999 int err; 6000 6001 if (!udata) 6002 return ERR_PTR(-ENOSYS); 6003 6004 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 6005 if (udata->outlen && udata->outlen < min_resp_len) 6006 return ERR_PTR(-EINVAL); 6007 6008 dev = to_mdev(pd->device); 6009 switch (init_attr->wq_type) { 6010 case IB_WQT_RQ: 6011 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 6012 if (!rwq) 6013 return ERR_PTR(-ENOMEM); 6014 err = prepare_user_rq(pd, init_attr, udata, rwq); 6015 if (err) 6016 goto err; 6017 err = create_rq(rwq, pd, init_attr); 6018 if (err) 6019 goto err_user_rq; 6020 break; 6021 default: 6022 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 6023 init_attr->wq_type); 6024 return ERR_PTR(-EINVAL); 6025 } 6026 6027 rwq->ibwq.wq_num = rwq->core_qp.qpn; 6028 rwq->ibwq.state = IB_WQS_RESET; 6029 if (udata->outlen) { 6030 resp.response_length = offsetof(typeof(resp), response_length) + 6031 sizeof(resp.response_length); 6032 err = ib_copy_to_udata(udata, &resp, resp.response_length); 6033 if (err) 6034 goto err_copy; 6035 } 6036 6037 rwq->core_qp.event = mlx5_ib_wq_event; 6038 rwq->ibwq.event_handler = init_attr->event_handler; 6039 return &rwq->ibwq; 6040 6041 err_copy: 6042 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 6043 err_user_rq: 6044 destroy_user_rq(dev, pd, rwq, udata); 6045 err: 6046 kfree(rwq); 6047 return ERR_PTR(err); 6048 } 6049 6050 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 6051 { 6052 struct mlx5_ib_dev *dev = to_mdev(wq->device); 6053 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 6054 6055 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 6056 destroy_user_rq(dev, wq->pd, rwq, udata); 6057 kfree(rwq); 6058 6059 return 0; 6060 } 6061 6062 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 6063 struct ib_rwq_ind_table_init_attr *init_attr, 6064 struct ib_udata *udata) 6065 { 6066 struct mlx5_ib_dev *dev = to_mdev(device); 6067 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 6068 int sz = 1 << init_attr->log_ind_tbl_size; 6069 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 6070 size_t min_resp_len; 6071 int inlen; 6072 int err; 6073 int i; 6074 u32 *in; 6075 void *rqtc; 6076 6077 if (udata->inlen > 0 && 6078 !ib_is_udata_cleared(udata, 0, 6079 udata->inlen)) 6080 return ERR_PTR(-EOPNOTSUPP); 6081 6082 if (init_attr->log_ind_tbl_size > 6083 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 6084 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 6085 init_attr->log_ind_tbl_size, 6086 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 6087 return ERR_PTR(-EINVAL); 6088 } 6089 6090 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 6091 if (udata->outlen && udata->outlen < min_resp_len) 6092 return ERR_PTR(-EINVAL); 6093 6094 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 6095 if (!rwq_ind_tbl) 6096 return ERR_PTR(-ENOMEM); 6097 6098 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 6099 in = kvzalloc(inlen, GFP_KERNEL); 6100 if (!in) { 6101 err = -ENOMEM; 6102 goto err; 6103 } 6104 6105 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 6106 6107 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 6108 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 6109 6110 for (i = 0; i < sz; i++) 6111 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 6112 6113 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 6114 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 6115 6116 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 6117 kvfree(in); 6118 6119 if (err) 6120 goto err; 6121 6122 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 6123 if (udata->outlen) { 6124 resp.response_length = offsetof(typeof(resp), response_length) + 6125 sizeof(resp.response_length); 6126 err = ib_copy_to_udata(udata, &resp, resp.response_length); 6127 if (err) 6128 goto err_copy; 6129 } 6130 6131 return &rwq_ind_tbl->ib_rwq_ind_tbl; 6132 6133 err_copy: 6134 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6135 err: 6136 kfree(rwq_ind_tbl); 6137 return ERR_PTR(err); 6138 } 6139 6140 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 6141 { 6142 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 6143 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 6144 6145 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 6146 6147 kfree(rwq_ind_tbl); 6148 return 0; 6149 } 6150 6151 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 6152 u32 wq_attr_mask, struct ib_udata *udata) 6153 { 6154 struct mlx5_ib_dev *dev = to_mdev(wq->device); 6155 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 6156 struct mlx5_ib_modify_wq ucmd = {}; 6157 size_t required_cmd_sz; 6158 int curr_wq_state; 6159 int wq_state; 6160 int inlen; 6161 int err; 6162 void *rqc; 6163 void *in; 6164 6165 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 6166 if (udata->inlen < required_cmd_sz) 6167 return -EINVAL; 6168 6169 if (udata->inlen > sizeof(ucmd) && 6170 !ib_is_udata_cleared(udata, sizeof(ucmd), 6171 udata->inlen - sizeof(ucmd))) 6172 return -EOPNOTSUPP; 6173 6174 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 6175 return -EFAULT; 6176 6177 if (ucmd.comp_mask || ucmd.reserved) 6178 return -EOPNOTSUPP; 6179 6180 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 6181 in = kvzalloc(inlen, GFP_KERNEL); 6182 if (!in) 6183 return -ENOMEM; 6184 6185 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 6186 6187 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 6188 wq_attr->curr_wq_state : wq->state; 6189 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 6190 wq_attr->wq_state : curr_wq_state; 6191 if (curr_wq_state == IB_WQS_ERR) 6192 curr_wq_state = MLX5_RQC_STATE_ERR; 6193 if (wq_state == IB_WQS_ERR) 6194 wq_state = MLX5_RQC_STATE_ERR; 6195 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 6196 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 6197 MLX5_SET(rqc, rqc, state, wq_state); 6198 6199 if (wq_attr_mask & IB_WQ_FLAGS) { 6200 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6201 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 6202 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6203 mlx5_ib_dbg(dev, "VLAN offloads are not " 6204 "supported\n"); 6205 err = -EOPNOTSUPP; 6206 goto out; 6207 } 6208 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6209 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 6210 MLX5_SET(rqc, rqc, vsd, 6211 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 6212 } 6213 6214 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6215 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 6216 err = -EOPNOTSUPP; 6217 goto out; 6218 } 6219 } 6220 6221 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 6222 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 6223 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6224 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 6225 MLX5_SET(rqc, rqc, counter_set_id, 6226 dev->port->cnts.set_id); 6227 } else 6228 dev_info_once( 6229 &dev->ib_dev.dev, 6230 "Receive WQ counters are not supported on current FW\n"); 6231 } 6232 6233 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 6234 if (!err) 6235 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 6236 6237 out: 6238 kvfree(in); 6239 return err; 6240 } 6241 6242 struct mlx5_ib_drain_cqe { 6243 struct ib_cqe cqe; 6244 struct completion done; 6245 }; 6246 6247 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 6248 { 6249 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 6250 struct mlx5_ib_drain_cqe, 6251 cqe); 6252 6253 complete(&cqe->done); 6254 } 6255 6256 /* This function returns only once the drained WR was completed */ 6257 static void handle_drain_completion(struct ib_cq *cq, 6258 struct mlx5_ib_drain_cqe *sdrain, 6259 struct mlx5_ib_dev *dev) 6260 { 6261 struct mlx5_core_dev *mdev = dev->mdev; 6262 6263 if (cq->poll_ctx == IB_POLL_DIRECT) { 6264 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 6265 ib_process_cq_direct(cq, -1); 6266 return; 6267 } 6268 6269 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6270 struct mlx5_ib_cq *mcq = to_mcq(cq); 6271 bool triggered = false; 6272 unsigned long flags; 6273 6274 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 6275 /* Make sure that the CQ handler won't run if wasn't run yet */ 6276 if (!mcq->mcq.reset_notify_added) 6277 mcq->mcq.reset_notify_added = 1; 6278 else 6279 triggered = true; 6280 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 6281 6282 if (triggered) { 6283 /* Wait for any scheduled/running task to be ended */ 6284 switch (cq->poll_ctx) { 6285 case IB_POLL_SOFTIRQ: 6286 irq_poll_disable(&cq->iop); 6287 irq_poll_enable(&cq->iop); 6288 break; 6289 case IB_POLL_WORKQUEUE: 6290 cancel_work_sync(&cq->work); 6291 break; 6292 default: 6293 WARN_ON_ONCE(1); 6294 } 6295 } 6296 6297 /* Run the CQ handler - this makes sure that the drain WR will 6298 * be processed if wasn't processed yet. 6299 */ 6300 mcq->mcq.comp(&mcq->mcq); 6301 } 6302 6303 wait_for_completion(&sdrain->done); 6304 } 6305 6306 void mlx5_ib_drain_sq(struct ib_qp *qp) 6307 { 6308 struct ib_cq *cq = qp->send_cq; 6309 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6310 struct mlx5_ib_drain_cqe sdrain; 6311 const struct ib_send_wr *bad_swr; 6312 struct ib_rdma_wr swr = { 6313 .wr = { 6314 .next = NULL, 6315 { .wr_cqe = &sdrain.cqe, }, 6316 .opcode = IB_WR_RDMA_WRITE, 6317 }, 6318 }; 6319 int ret; 6320 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6321 struct mlx5_core_dev *mdev = dev->mdev; 6322 6323 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6324 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6325 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6326 return; 6327 } 6328 6329 sdrain.cqe.done = mlx5_ib_drain_qp_done; 6330 init_completion(&sdrain.done); 6331 6332 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); 6333 if (ret) { 6334 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6335 return; 6336 } 6337 6338 handle_drain_completion(cq, &sdrain, dev); 6339 } 6340 6341 void mlx5_ib_drain_rq(struct ib_qp *qp) 6342 { 6343 struct ib_cq *cq = qp->recv_cq; 6344 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6345 struct mlx5_ib_drain_cqe rdrain; 6346 struct ib_recv_wr rwr = {}; 6347 const struct ib_recv_wr *bad_rwr; 6348 int ret; 6349 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6350 struct mlx5_core_dev *mdev = dev->mdev; 6351 6352 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6353 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6354 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6355 return; 6356 } 6357 6358 rwr.wr_cqe = &rdrain.cqe; 6359 rdrain.cqe.done = mlx5_ib_drain_qp_done; 6360 init_completion(&rdrain.done); 6361 6362 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); 6363 if (ret) { 6364 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6365 return; 6366 } 6367 6368 handle_drain_completion(cq, &rdrain, dev); 6369 } 6370