1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 #include "cmd.h" 41 42 /* not supported currently */ 43 static int wq_signature; 44 45 enum { 46 MLX5_IB_ACK_REQ_FREQ = 8, 47 }; 48 49 enum { 50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 52 MLX5_IB_LINK_TYPE_IB = 0, 53 MLX5_IB_LINK_TYPE_ETH = 1 54 }; 55 56 enum { 57 MLX5_IB_SQ_STRIDE = 6, 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 59 }; 60 61 static const u32 mlx5_ib_opcode[] = { 62 [IB_WR_SEND] = MLX5_OPCODE_SEND, 63 [IB_WR_LSO] = MLX5_OPCODE_LSO, 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 76 }; 77 78 struct mlx5_wqe_eth_pad { 79 u8 rsvd0[16]; 80 }; 81 82 enum raw_qp_set_mask_map { 83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 85 }; 86 87 struct mlx5_modify_raw_qp_param { 88 u16 operation; 89 90 u32 set_mask; /* raw_qp_set_mask_map */ 91 92 struct mlx5_rate_limit rl; 93 94 u8 rq_q_ctr_id; 95 }; 96 97 static void get_cqs(enum ib_qp_type qp_type, 98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 100 101 static int is_qp0(enum ib_qp_type qp_type) 102 { 103 return qp_type == IB_QPT_SMI; 104 } 105 106 static int is_sqp(enum ib_qp_type qp_type) 107 { 108 return is_qp0(qp_type) || is_qp1(qp_type); 109 } 110 111 /** 112 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 113 * 114 * @qp: QP to copy from. 115 * @send: copy from the send queue when non-zero, use the receive queue 116 * otherwise. 117 * @wqe_index: index to start copying from. For send work queues, the 118 * wqe_index is in units of MLX5_SEND_WQE_BB. 119 * For receive work queue, it is the number of work queue 120 * element in the queue. 121 * @buffer: destination buffer. 122 * @length: maximum number of bytes to copy. 123 * 124 * Copies at least a single WQE, but may copy more data. 125 * 126 * Return: the number of bytes copied, or an error code. 127 */ 128 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 129 void *buffer, u32 length, 130 struct mlx5_ib_qp_base *base) 131 { 132 struct ib_device *ibdev = qp->ibqp.device; 133 struct mlx5_ib_dev *dev = to_mdev(ibdev); 134 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 135 size_t offset; 136 size_t wq_end; 137 struct ib_umem *umem = base->ubuffer.umem; 138 u32 first_copy_length; 139 int wqe_length; 140 int ret; 141 142 if (wq->wqe_cnt == 0) { 143 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 144 qp->ibqp.qp_type); 145 return -EINVAL; 146 } 147 148 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 149 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 150 151 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 152 return -EINVAL; 153 154 if (offset > umem->length || 155 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 156 return -EINVAL; 157 158 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 159 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 160 if (ret) 161 return ret; 162 163 if (send) { 164 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 165 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 166 167 wqe_length = ds * MLX5_WQE_DS_UNITS; 168 } else { 169 wqe_length = 1 << wq->wqe_shift; 170 } 171 172 if (wqe_length <= first_copy_length) 173 return first_copy_length; 174 175 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 176 wqe_length - first_copy_length); 177 if (ret) 178 return ret; 179 180 return wqe_length; 181 } 182 183 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 184 { 185 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 186 struct ib_event event; 187 188 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 189 /* This event is only valid for trans_qps */ 190 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 191 } 192 193 if (ibqp->event_handler) { 194 event.device = ibqp->device; 195 event.element.qp = ibqp; 196 switch (type) { 197 case MLX5_EVENT_TYPE_PATH_MIG: 198 event.event = IB_EVENT_PATH_MIG; 199 break; 200 case MLX5_EVENT_TYPE_COMM_EST: 201 event.event = IB_EVENT_COMM_EST; 202 break; 203 case MLX5_EVENT_TYPE_SQ_DRAINED: 204 event.event = IB_EVENT_SQ_DRAINED; 205 break; 206 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 207 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 208 break; 209 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 210 event.event = IB_EVENT_QP_FATAL; 211 break; 212 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 213 event.event = IB_EVENT_PATH_MIG_ERR; 214 break; 215 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 216 event.event = IB_EVENT_QP_REQ_ERR; 217 break; 218 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 219 event.event = IB_EVENT_QP_ACCESS_ERR; 220 break; 221 default: 222 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 223 return; 224 } 225 226 ibqp->event_handler(&event, ibqp->qp_context); 227 } 228 } 229 230 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 231 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 232 { 233 int wqe_size; 234 int wq_size; 235 236 /* Sanity check RQ size before proceeding */ 237 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 238 return -EINVAL; 239 240 if (!has_rq) { 241 qp->rq.max_gs = 0; 242 qp->rq.wqe_cnt = 0; 243 qp->rq.wqe_shift = 0; 244 cap->max_recv_wr = 0; 245 cap->max_recv_sge = 0; 246 } else { 247 if (ucmd) { 248 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 249 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 250 return -EINVAL; 251 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 252 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 253 return -EINVAL; 254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 255 qp->rq.max_post = qp->rq.wqe_cnt; 256 } else { 257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 259 wqe_size = roundup_pow_of_two(wqe_size); 260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 262 qp->rq.wqe_cnt = wq_size / wqe_size; 263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 265 wqe_size, 266 MLX5_CAP_GEN(dev->mdev, 267 max_wqe_sz_rq)); 268 return -EINVAL; 269 } 270 qp->rq.wqe_shift = ilog2(wqe_size); 271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 272 qp->rq.max_post = qp->rq.wqe_cnt; 273 } 274 } 275 276 return 0; 277 } 278 279 static int sq_overhead(struct ib_qp_init_attr *attr) 280 { 281 int size = 0; 282 283 switch (attr->qp_type) { 284 case IB_QPT_XRC_INI: 285 size += sizeof(struct mlx5_wqe_xrc_seg); 286 /* fall through */ 287 case IB_QPT_RC: 288 size += sizeof(struct mlx5_wqe_ctrl_seg) + 289 max(sizeof(struct mlx5_wqe_atomic_seg) + 290 sizeof(struct mlx5_wqe_raddr_seg), 291 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 292 sizeof(struct mlx5_mkey_seg) + 293 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 294 MLX5_IB_UMR_OCTOWORD); 295 break; 296 297 case IB_QPT_XRC_TGT: 298 return 0; 299 300 case IB_QPT_UC: 301 size += sizeof(struct mlx5_wqe_ctrl_seg) + 302 max(sizeof(struct mlx5_wqe_raddr_seg), 303 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 304 sizeof(struct mlx5_mkey_seg)); 305 break; 306 307 case IB_QPT_UD: 308 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 309 size += sizeof(struct mlx5_wqe_eth_pad) + 310 sizeof(struct mlx5_wqe_eth_seg); 311 /* fall through */ 312 case IB_QPT_SMI: 313 case MLX5_IB_QPT_HW_GSI: 314 size += sizeof(struct mlx5_wqe_ctrl_seg) + 315 sizeof(struct mlx5_wqe_datagram_seg); 316 break; 317 318 case MLX5_IB_QPT_REG_UMR: 319 size += sizeof(struct mlx5_wqe_ctrl_seg) + 320 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 321 sizeof(struct mlx5_mkey_seg); 322 break; 323 324 default: 325 return -EINVAL; 326 } 327 328 return size; 329 } 330 331 static int calc_send_wqe(struct ib_qp_init_attr *attr) 332 { 333 int inl_size = 0; 334 int size; 335 336 size = sq_overhead(attr); 337 if (size < 0) 338 return size; 339 340 if (attr->cap.max_inline_data) { 341 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 342 attr->cap.max_inline_data; 343 } 344 345 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 346 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 347 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 348 return MLX5_SIG_WQE_SIZE; 349 else 350 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 351 } 352 353 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 354 { 355 int max_sge; 356 357 if (attr->qp_type == IB_QPT_RC) 358 max_sge = (min_t(int, wqe_size, 512) - 359 sizeof(struct mlx5_wqe_ctrl_seg) - 360 sizeof(struct mlx5_wqe_raddr_seg)) / 361 sizeof(struct mlx5_wqe_data_seg); 362 else if (attr->qp_type == IB_QPT_XRC_INI) 363 max_sge = (min_t(int, wqe_size, 512) - 364 sizeof(struct mlx5_wqe_ctrl_seg) - 365 sizeof(struct mlx5_wqe_xrc_seg) - 366 sizeof(struct mlx5_wqe_raddr_seg)) / 367 sizeof(struct mlx5_wqe_data_seg); 368 else 369 max_sge = (wqe_size - sq_overhead(attr)) / 370 sizeof(struct mlx5_wqe_data_seg); 371 372 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 373 sizeof(struct mlx5_wqe_data_seg)); 374 } 375 376 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 377 struct mlx5_ib_qp *qp) 378 { 379 int wqe_size; 380 int wq_size; 381 382 if (!attr->cap.max_send_wr) 383 return 0; 384 385 wqe_size = calc_send_wqe(attr); 386 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 387 if (wqe_size < 0) 388 return wqe_size; 389 390 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 391 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 392 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 393 return -EINVAL; 394 } 395 396 qp->max_inline_data = wqe_size - sq_overhead(attr) - 397 sizeof(struct mlx5_wqe_inline_seg); 398 attr->cap.max_inline_data = qp->max_inline_data; 399 400 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 401 qp->signature_en = true; 402 403 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 404 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 405 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 406 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 407 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 408 qp->sq.wqe_cnt, 409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 410 return -ENOMEM; 411 } 412 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 413 qp->sq.max_gs = get_send_sge(attr, wqe_size); 414 if (qp->sq.max_gs < attr->cap.max_send_sge) 415 return -ENOMEM; 416 417 attr->cap.max_send_sge = qp->sq.max_gs; 418 qp->sq.max_post = wq_size / wqe_size; 419 attr->cap.max_send_wr = qp->sq.max_post; 420 421 return wq_size; 422 } 423 424 static int set_user_buf_size(struct mlx5_ib_dev *dev, 425 struct mlx5_ib_qp *qp, 426 struct mlx5_ib_create_qp *ucmd, 427 struct mlx5_ib_qp_base *base, 428 struct ib_qp_init_attr *attr) 429 { 430 int desc_sz = 1 << qp->sq.wqe_shift; 431 432 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 433 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 434 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 435 return -EINVAL; 436 } 437 438 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 439 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 440 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 441 return -EINVAL; 442 } 443 444 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 445 446 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 447 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 448 qp->sq.wqe_cnt, 449 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 450 return -EINVAL; 451 } 452 453 if (attr->qp_type == IB_QPT_RAW_PACKET || 454 qp->flags & MLX5_IB_QP_UNDERLAY) { 455 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 456 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 457 } else { 458 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 459 (qp->sq.wqe_cnt << 6); 460 } 461 462 return 0; 463 } 464 465 static int qp_has_rq(struct ib_qp_init_attr *attr) 466 { 467 if (attr->qp_type == IB_QPT_XRC_INI || 468 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 469 attr->qp_type == MLX5_IB_QPT_REG_UMR || 470 !attr->cap.max_recv_wr) 471 return 0; 472 473 return 1; 474 } 475 476 enum { 477 /* this is the first blue flame register in the array of bfregs assigned 478 * to a processes. Since we do not use it for blue flame but rather 479 * regular 64 bit doorbells, we do not need a lock for maintaiing 480 * "odd/even" order 481 */ 482 NUM_NON_BLUE_FLAME_BFREGS = 1, 483 }; 484 485 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 486 { 487 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 488 } 489 490 static int num_med_bfreg(struct mlx5_ib_dev *dev, 491 struct mlx5_bfreg_info *bfregi) 492 { 493 int n; 494 495 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 496 NUM_NON_BLUE_FLAME_BFREGS; 497 498 return n >= 0 ? n : 0; 499 } 500 501 static int first_med_bfreg(struct mlx5_ib_dev *dev, 502 struct mlx5_bfreg_info *bfregi) 503 { 504 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 505 } 506 507 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 508 struct mlx5_bfreg_info *bfregi) 509 { 510 int med; 511 512 med = num_med_bfreg(dev, bfregi); 513 return ++med; 514 } 515 516 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 517 struct mlx5_bfreg_info *bfregi) 518 { 519 int i; 520 521 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 522 if (!bfregi->count[i]) { 523 bfregi->count[i]++; 524 return i; 525 } 526 } 527 528 return -ENOMEM; 529 } 530 531 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 532 struct mlx5_bfreg_info *bfregi) 533 { 534 int minidx = first_med_bfreg(dev, bfregi); 535 int i; 536 537 if (minidx < 0) 538 return minidx; 539 540 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 541 if (bfregi->count[i] < bfregi->count[minidx]) 542 minidx = i; 543 if (!bfregi->count[minidx]) 544 break; 545 } 546 547 bfregi->count[minidx]++; 548 return minidx; 549 } 550 551 static int alloc_bfreg(struct mlx5_ib_dev *dev, 552 struct mlx5_bfreg_info *bfregi) 553 { 554 int bfregn = -ENOMEM; 555 556 mutex_lock(&bfregi->lock); 557 if (bfregi->ver >= 2) { 558 bfregn = alloc_high_class_bfreg(dev, bfregi); 559 if (bfregn < 0) 560 bfregn = alloc_med_class_bfreg(dev, bfregi); 561 } 562 563 if (bfregn < 0) { 564 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 565 bfregn = 0; 566 bfregi->count[bfregn]++; 567 } 568 mutex_unlock(&bfregi->lock); 569 570 return bfregn; 571 } 572 573 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 574 { 575 mutex_lock(&bfregi->lock); 576 bfregi->count[bfregn]--; 577 mutex_unlock(&bfregi->lock); 578 } 579 580 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 581 { 582 switch (state) { 583 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 584 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 585 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 586 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 587 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 588 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 589 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 590 default: return -1; 591 } 592 } 593 594 static int to_mlx5_st(enum ib_qp_type type) 595 { 596 switch (type) { 597 case IB_QPT_RC: return MLX5_QP_ST_RC; 598 case IB_QPT_UC: return MLX5_QP_ST_UC; 599 case IB_QPT_UD: return MLX5_QP_ST_UD; 600 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 601 case IB_QPT_XRC_INI: 602 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 603 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 604 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 605 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 606 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 607 case IB_QPT_RAW_PACKET: 608 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 609 case IB_QPT_MAX: 610 default: return -EINVAL; 611 } 612 } 613 614 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 615 struct mlx5_ib_cq *recv_cq); 616 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 617 struct mlx5_ib_cq *recv_cq); 618 619 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 620 struct mlx5_bfreg_info *bfregi, u32 bfregn, 621 bool dyn_bfreg) 622 { 623 unsigned int bfregs_per_sys_page; 624 u32 index_of_sys_page; 625 u32 offset; 626 627 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 628 MLX5_NON_FP_BFREGS_PER_UAR; 629 index_of_sys_page = bfregn / bfregs_per_sys_page; 630 631 if (dyn_bfreg) { 632 index_of_sys_page += bfregi->num_static_sys_pages; 633 634 if (index_of_sys_page >= bfregi->num_sys_pages) 635 return -EINVAL; 636 637 if (bfregn > bfregi->num_dyn_bfregs || 638 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 639 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 640 return -EINVAL; 641 } 642 } 643 644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 645 return bfregi->sys_pages[index_of_sys_page] + offset; 646 } 647 648 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 649 struct ib_pd *pd, 650 unsigned long addr, size_t size, 651 struct ib_umem **umem, 652 int *npages, int *page_shift, int *ncont, 653 u32 *offset) 654 { 655 int err; 656 657 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 658 if (IS_ERR(*umem)) { 659 mlx5_ib_dbg(dev, "umem_get failed\n"); 660 return PTR_ERR(*umem); 661 } 662 663 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 664 665 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 666 if (err) { 667 mlx5_ib_warn(dev, "bad offset\n"); 668 goto err_umem; 669 } 670 671 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 672 addr, size, *npages, *page_shift, *ncont, *offset); 673 674 return 0; 675 676 err_umem: 677 ib_umem_release(*umem); 678 *umem = NULL; 679 680 return err; 681 } 682 683 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 684 struct mlx5_ib_rwq *rwq) 685 { 686 struct mlx5_ib_ucontext *context; 687 688 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 689 atomic_dec(&dev->delay_drop.rqs_cnt); 690 691 context = to_mucontext(pd->uobject->context); 692 mlx5_ib_db_unmap_user(context, &rwq->db); 693 if (rwq->umem) 694 ib_umem_release(rwq->umem); 695 } 696 697 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 698 struct mlx5_ib_rwq *rwq, 699 struct mlx5_ib_create_wq *ucmd) 700 { 701 struct mlx5_ib_ucontext *context; 702 int page_shift = 0; 703 int npages; 704 u32 offset = 0; 705 int ncont = 0; 706 int err; 707 708 if (!ucmd->buf_addr) 709 return -EINVAL; 710 711 context = to_mucontext(pd->uobject->context); 712 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 713 rwq->buf_size, 0, 0); 714 if (IS_ERR(rwq->umem)) { 715 mlx5_ib_dbg(dev, "umem_get failed\n"); 716 err = PTR_ERR(rwq->umem); 717 return err; 718 } 719 720 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 721 &ncont, NULL); 722 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 723 &rwq->rq_page_offset); 724 if (err) { 725 mlx5_ib_warn(dev, "bad offset\n"); 726 goto err_umem; 727 } 728 729 rwq->rq_num_pas = ncont; 730 rwq->page_shift = page_shift; 731 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 732 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 733 734 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 735 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 736 npages, page_shift, ncont, offset); 737 738 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 739 if (err) { 740 mlx5_ib_dbg(dev, "map failed\n"); 741 goto err_umem; 742 } 743 744 rwq->create_type = MLX5_WQ_USER; 745 return 0; 746 747 err_umem: 748 ib_umem_release(rwq->umem); 749 return err; 750 } 751 752 static int adjust_bfregn(struct mlx5_ib_dev *dev, 753 struct mlx5_bfreg_info *bfregi, int bfregn) 754 { 755 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 756 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 757 } 758 759 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 760 struct mlx5_ib_qp *qp, struct ib_udata *udata, 761 struct ib_qp_init_attr *attr, 762 u32 **in, 763 struct mlx5_ib_create_qp_resp *resp, int *inlen, 764 struct mlx5_ib_qp_base *base) 765 { 766 struct mlx5_ib_ucontext *context; 767 struct mlx5_ib_create_qp ucmd; 768 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 769 int page_shift = 0; 770 int uar_index = 0; 771 int npages; 772 u32 offset = 0; 773 int bfregn; 774 int ncont = 0; 775 __be64 *pas; 776 void *qpc; 777 int err; 778 u16 uid; 779 780 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 781 if (err) { 782 mlx5_ib_dbg(dev, "copy failed\n"); 783 return err; 784 } 785 786 context = to_mucontext(pd->uobject->context); 787 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 788 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 789 ucmd.bfreg_index, true); 790 if (uar_index < 0) 791 return uar_index; 792 793 bfregn = MLX5_IB_INVALID_BFREG; 794 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 795 /* 796 * TBD: should come from the verbs when we have the API 797 */ 798 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 799 bfregn = MLX5_CROSS_CHANNEL_BFREG; 800 } 801 else { 802 bfregn = alloc_bfreg(dev, &context->bfregi); 803 if (bfregn < 0) 804 return bfregn; 805 } 806 807 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 808 if (bfregn != MLX5_IB_INVALID_BFREG) 809 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 810 false); 811 812 qp->rq.offset = 0; 813 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 814 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 815 816 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 817 if (err) 818 goto err_bfreg; 819 820 if (ucmd.buf_addr && ubuffer->buf_size) { 821 ubuffer->buf_addr = ucmd.buf_addr; 822 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 823 ubuffer->buf_size, 824 &ubuffer->umem, &npages, &page_shift, 825 &ncont, &offset); 826 if (err) 827 goto err_bfreg; 828 } else { 829 ubuffer->umem = NULL; 830 } 831 832 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 833 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 834 *in = kvzalloc(*inlen, GFP_KERNEL); 835 if (!*in) { 836 err = -ENOMEM; 837 goto err_umem; 838 } 839 840 uid = (attr->qp_type != IB_QPT_XRC_TGT && 841 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 842 MLX5_SET(create_qp_in, *in, uid, uid); 843 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 844 if (ubuffer->umem) 845 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 846 847 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 848 849 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 850 MLX5_SET(qpc, qpc, page_offset, offset); 851 852 MLX5_SET(qpc, qpc, uar_page, uar_index); 853 if (bfregn != MLX5_IB_INVALID_BFREG) 854 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 855 else 856 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 857 qp->bfregn = bfregn; 858 859 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 860 if (err) { 861 mlx5_ib_dbg(dev, "map failed\n"); 862 goto err_free; 863 } 864 865 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 866 if (err) { 867 mlx5_ib_dbg(dev, "copy failed\n"); 868 goto err_unmap; 869 } 870 qp->create_type = MLX5_QP_USER; 871 872 return 0; 873 874 err_unmap: 875 mlx5_ib_db_unmap_user(context, &qp->db); 876 877 err_free: 878 kvfree(*in); 879 880 err_umem: 881 if (ubuffer->umem) 882 ib_umem_release(ubuffer->umem); 883 884 err_bfreg: 885 if (bfregn != MLX5_IB_INVALID_BFREG) 886 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 887 return err; 888 } 889 890 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 891 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 892 { 893 struct mlx5_ib_ucontext *context; 894 895 context = to_mucontext(pd->uobject->context); 896 mlx5_ib_db_unmap_user(context, &qp->db); 897 if (base->ubuffer.umem) 898 ib_umem_release(base->ubuffer.umem); 899 900 /* 901 * Free only the BFREGs which are handled by the kernel. 902 * BFREGs of UARs allocated dynamically are handled by user. 903 */ 904 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 905 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 906 } 907 908 /* get_sq_edge - Get the next nearby edge. 909 * 910 * An 'edge' is defined as the first following address after the end 911 * of the fragment or the SQ. Accordingly, during the WQE construction 912 * which repetitively increases the pointer to write the next data, it 913 * simply should check if it gets to an edge. 914 * 915 * @sq - SQ buffer. 916 * @idx - Stride index in the SQ buffer. 917 * 918 * Return: 919 * The new edge. 920 */ 921 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) 922 { 923 void *fragment_end; 924 925 fragment_end = mlx5_frag_buf_get_wqe 926 (&sq->fbc, 927 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); 928 929 return fragment_end + MLX5_SEND_WQE_BB; 930 } 931 932 static int create_kernel_qp(struct mlx5_ib_dev *dev, 933 struct ib_qp_init_attr *init_attr, 934 struct mlx5_ib_qp *qp, 935 u32 **in, int *inlen, 936 struct mlx5_ib_qp_base *base) 937 { 938 int uar_index; 939 void *qpc; 940 int err; 941 942 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 943 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 944 IB_QP_CREATE_IPOIB_UD_LSO | 945 IB_QP_CREATE_NETIF_QP | 946 mlx5_ib_create_qp_sqpn_qp1())) 947 return -EINVAL; 948 949 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 950 qp->bf.bfreg = &dev->fp_bfreg; 951 else 952 qp->bf.bfreg = &dev->bfreg; 953 954 /* We need to divide by two since each register is comprised of 955 * two buffers of identical size, namely odd and even 956 */ 957 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 958 uar_index = qp->bf.bfreg->index; 959 960 err = calc_sq_size(dev, init_attr, qp); 961 if (err < 0) { 962 mlx5_ib_dbg(dev, "err %d\n", err); 963 return err; 964 } 965 966 qp->rq.offset = 0; 967 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 968 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 969 970 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 971 &qp->buf, dev->mdev->priv.numa_node); 972 if (err) { 973 mlx5_ib_dbg(dev, "err %d\n", err); 974 return err; 975 } 976 977 if (qp->rq.wqe_cnt) 978 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 979 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 980 981 if (qp->sq.wqe_cnt) { 982 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 983 MLX5_SEND_WQE_BB; 984 mlx5_init_fbc_offset(qp->buf.frags + 985 (qp->sq.offset / PAGE_SIZE), 986 ilog2(MLX5_SEND_WQE_BB), 987 ilog2(qp->sq.wqe_cnt), 988 sq_strides_offset, &qp->sq.fbc); 989 990 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 991 } 992 993 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 994 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 995 *in = kvzalloc(*inlen, GFP_KERNEL); 996 if (!*in) { 997 err = -ENOMEM; 998 goto err_buf; 999 } 1000 1001 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1002 MLX5_SET(qpc, qpc, uar_page, uar_index); 1003 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1004 1005 /* Set "fast registration enabled" for all kernel QPs */ 1006 MLX5_SET(qpc, qpc, fre, 1); 1007 MLX5_SET(qpc, qpc, rlky, 1); 1008 1009 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 1010 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1011 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1012 } 1013 1014 mlx5_fill_page_frag_array(&qp->buf, 1015 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1016 *in, pas)); 1017 1018 err = mlx5_db_alloc(dev->mdev, &qp->db); 1019 if (err) { 1020 mlx5_ib_dbg(dev, "err %d\n", err); 1021 goto err_free; 1022 } 1023 1024 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1025 sizeof(*qp->sq.wrid), GFP_KERNEL); 1026 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1027 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1028 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1029 sizeof(*qp->rq.wrid), GFP_KERNEL); 1030 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1031 sizeof(*qp->sq.w_list), GFP_KERNEL); 1032 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1033 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1034 1035 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1036 !qp->sq.w_list || !qp->sq.wqe_head) { 1037 err = -ENOMEM; 1038 goto err_wrid; 1039 } 1040 qp->create_type = MLX5_QP_KERNEL; 1041 1042 return 0; 1043 1044 err_wrid: 1045 kvfree(qp->sq.wqe_head); 1046 kvfree(qp->sq.w_list); 1047 kvfree(qp->sq.wrid); 1048 kvfree(qp->sq.wr_data); 1049 kvfree(qp->rq.wrid); 1050 mlx5_db_free(dev->mdev, &qp->db); 1051 1052 err_free: 1053 kvfree(*in); 1054 1055 err_buf: 1056 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1057 return err; 1058 } 1059 1060 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1061 { 1062 kvfree(qp->sq.wqe_head); 1063 kvfree(qp->sq.w_list); 1064 kvfree(qp->sq.wrid); 1065 kvfree(qp->sq.wr_data); 1066 kvfree(qp->rq.wrid); 1067 mlx5_db_free(dev->mdev, &qp->db); 1068 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1069 } 1070 1071 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1072 { 1073 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1074 (attr->qp_type == MLX5_IB_QPT_DCI) || 1075 (attr->qp_type == IB_QPT_XRC_INI)) 1076 return MLX5_SRQ_RQ; 1077 else if (!qp->has_rq) 1078 return MLX5_ZERO_LEN_RQ; 1079 else 1080 return MLX5_NON_ZERO_RQ; 1081 } 1082 1083 static int is_connected(enum ib_qp_type qp_type) 1084 { 1085 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || 1086 qp_type == MLX5_IB_QPT_DCI) 1087 return 1; 1088 1089 return 0; 1090 } 1091 1092 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1093 struct mlx5_ib_qp *qp, 1094 struct mlx5_ib_sq *sq, u32 tdn, 1095 struct ib_pd *pd) 1096 { 1097 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1098 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1099 1100 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1101 MLX5_SET(tisc, tisc, transport_domain, tdn); 1102 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1103 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1104 1105 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1106 } 1107 1108 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1109 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1110 { 1111 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1112 } 1113 1114 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1115 struct mlx5_ib_sq *sq) 1116 { 1117 if (sq->flow_rule) 1118 mlx5_del_flow_rules(sq->flow_rule); 1119 } 1120 1121 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1122 struct mlx5_ib_sq *sq, void *qpin, 1123 struct ib_pd *pd) 1124 { 1125 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1126 __be64 *pas; 1127 void *in; 1128 void *sqc; 1129 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1130 void *wq; 1131 int inlen; 1132 int err; 1133 int page_shift = 0; 1134 int npages; 1135 int ncont = 0; 1136 u32 offset = 0; 1137 1138 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1139 &sq->ubuffer.umem, &npages, &page_shift, 1140 &ncont, &offset); 1141 if (err) 1142 return err; 1143 1144 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1145 in = kvzalloc(inlen, GFP_KERNEL); 1146 if (!in) { 1147 err = -ENOMEM; 1148 goto err_umem; 1149 } 1150 1151 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1152 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1153 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1154 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1155 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1156 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1157 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1158 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1159 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1160 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1161 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1162 MLX5_CAP_ETH(dev->mdev, swp)) 1163 MLX5_SET(sqc, sqc, allow_swp, 1); 1164 1165 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1166 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1167 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1168 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1169 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1170 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1171 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1172 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1173 MLX5_SET(wq, wq, page_offset, offset); 1174 1175 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1176 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1177 1178 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1179 1180 kvfree(in); 1181 1182 if (err) 1183 goto err_umem; 1184 1185 err = create_flow_rule_vport_sq(dev, sq); 1186 if (err) 1187 goto err_flow; 1188 1189 return 0; 1190 1191 err_flow: 1192 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1193 1194 err_umem: 1195 ib_umem_release(sq->ubuffer.umem); 1196 sq->ubuffer.umem = NULL; 1197 1198 return err; 1199 } 1200 1201 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1202 struct mlx5_ib_sq *sq) 1203 { 1204 destroy_flow_rule_vport_sq(dev, sq); 1205 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1206 ib_umem_release(sq->ubuffer.umem); 1207 } 1208 1209 static size_t get_rq_pas_size(void *qpc) 1210 { 1211 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1212 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1213 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1214 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1215 u32 po_quanta = 1 << (log_page_size - 6); 1216 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1217 u32 page_size = 1 << log_page_size; 1218 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1219 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1220 1221 return rq_num_pas * sizeof(u64); 1222 } 1223 1224 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1225 struct mlx5_ib_rq *rq, void *qpin, 1226 size_t qpinlen, struct ib_pd *pd) 1227 { 1228 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1229 __be64 *pas; 1230 __be64 *qp_pas; 1231 void *in; 1232 void *rqc; 1233 void *wq; 1234 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1235 size_t rq_pas_size = get_rq_pas_size(qpc); 1236 size_t inlen; 1237 int err; 1238 1239 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1240 return -EINVAL; 1241 1242 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1243 in = kvzalloc(inlen, GFP_KERNEL); 1244 if (!in) 1245 return -ENOMEM; 1246 1247 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1248 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1249 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1250 MLX5_SET(rqc, rqc, vsd, 1); 1251 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1252 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1253 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1254 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1255 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1256 1257 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1258 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1259 1260 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1261 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1262 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1263 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1264 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1265 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1266 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1267 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1268 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1269 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1270 1271 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1272 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1273 memcpy(pas, qp_pas, rq_pas_size); 1274 1275 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1276 1277 kvfree(in); 1278 1279 return err; 1280 } 1281 1282 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1283 struct mlx5_ib_rq *rq) 1284 { 1285 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1286 } 1287 1288 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1289 { 1290 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1291 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1292 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1293 } 1294 1295 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1296 struct mlx5_ib_rq *rq, 1297 u32 qp_flags_en, 1298 struct ib_pd *pd) 1299 { 1300 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1301 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1302 mlx5_ib_disable_lb(dev, false, true); 1303 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1304 } 1305 1306 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1307 struct mlx5_ib_rq *rq, u32 tdn, 1308 u32 *qp_flags_en, 1309 struct ib_pd *pd) 1310 { 1311 u8 lb_flag = 0; 1312 u32 *in; 1313 void *tirc; 1314 int inlen; 1315 int err; 1316 1317 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1318 in = kvzalloc(inlen, GFP_KERNEL); 1319 if (!in) 1320 return -ENOMEM; 1321 1322 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1323 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1324 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1325 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1326 MLX5_SET(tirc, tirc, transport_domain, tdn); 1327 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1328 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1329 1330 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1331 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1332 1333 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1334 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1335 1336 if (dev->rep) { 1337 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1338 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1339 } 1340 1341 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1342 1343 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1344 1345 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1346 err = mlx5_ib_enable_lb(dev, false, true); 1347 1348 if (err) 1349 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1350 } 1351 kvfree(in); 1352 1353 return err; 1354 } 1355 1356 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1357 u32 *in, size_t inlen, 1358 struct ib_pd *pd, 1359 struct ib_udata *udata, 1360 struct mlx5_ib_create_qp_resp *resp) 1361 { 1362 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1363 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1364 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1365 struct ib_uobject *uobj = pd->uobject; 1366 struct ib_ucontext *ucontext = uobj->context; 1367 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1368 int err; 1369 u32 tdn = mucontext->tdn; 1370 u16 uid = to_mpd(pd)->uid; 1371 1372 if (qp->sq.wqe_cnt) { 1373 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1374 if (err) 1375 return err; 1376 1377 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1378 if (err) 1379 goto err_destroy_tis; 1380 1381 if (uid) { 1382 resp->tisn = sq->tisn; 1383 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1384 resp->sqn = sq->base.mqp.qpn; 1385 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1386 } 1387 1388 sq->base.container_mibqp = qp; 1389 sq->base.mqp.event = mlx5_ib_qp_event; 1390 } 1391 1392 if (qp->rq.wqe_cnt) { 1393 rq->base.container_mibqp = qp; 1394 1395 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1396 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1397 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1398 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1399 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1400 if (err) 1401 goto err_destroy_sq; 1402 1403 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd); 1404 if (err) 1405 goto err_destroy_rq; 1406 1407 if (uid) { 1408 resp->rqn = rq->base.mqp.qpn; 1409 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1410 resp->tirn = rq->tirn; 1411 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1412 } 1413 } 1414 1415 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1416 rq->base.mqp.qpn; 1417 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1418 if (err) 1419 goto err_destroy_tir; 1420 1421 return 0; 1422 1423 err_destroy_tir: 1424 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); 1425 err_destroy_rq: 1426 destroy_raw_packet_qp_rq(dev, rq); 1427 err_destroy_sq: 1428 if (!qp->sq.wqe_cnt) 1429 return err; 1430 destroy_raw_packet_qp_sq(dev, sq); 1431 err_destroy_tis: 1432 destroy_raw_packet_qp_tis(dev, sq, pd); 1433 1434 return err; 1435 } 1436 1437 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1438 struct mlx5_ib_qp *qp) 1439 { 1440 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1441 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1442 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1443 1444 if (qp->rq.wqe_cnt) { 1445 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1446 destroy_raw_packet_qp_rq(dev, rq); 1447 } 1448 1449 if (qp->sq.wqe_cnt) { 1450 destroy_raw_packet_qp_sq(dev, sq); 1451 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1452 } 1453 } 1454 1455 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1456 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1457 { 1458 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1459 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1460 1461 sq->sq = &qp->sq; 1462 rq->rq = &qp->rq; 1463 sq->doorbell = &qp->db; 1464 rq->doorbell = &qp->db; 1465 } 1466 1467 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1468 { 1469 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1470 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1471 mlx5_ib_disable_lb(dev, false, true); 1472 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1473 to_mpd(qp->ibqp.pd)->uid); 1474 } 1475 1476 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1477 struct ib_pd *pd, 1478 struct ib_qp_init_attr *init_attr, 1479 struct ib_udata *udata) 1480 { 1481 struct ib_uobject *uobj = pd->uobject; 1482 struct ib_ucontext *ucontext = uobj->context; 1483 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1484 struct mlx5_ib_create_qp_resp resp = {}; 1485 int inlen; 1486 int err; 1487 u32 *in; 1488 void *tirc; 1489 void *hfso; 1490 u32 selected_fields = 0; 1491 u32 outer_l4; 1492 size_t min_resp_len; 1493 u32 tdn = mucontext->tdn; 1494 struct mlx5_ib_create_qp_rss ucmd = {}; 1495 size_t required_cmd_sz; 1496 u8 lb_flag = 0; 1497 1498 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1499 return -EOPNOTSUPP; 1500 1501 if (init_attr->create_flags || init_attr->send_cq) 1502 return -EINVAL; 1503 1504 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1505 if (udata->outlen < min_resp_len) 1506 return -EINVAL; 1507 1508 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1509 if (udata->inlen < required_cmd_sz) { 1510 mlx5_ib_dbg(dev, "invalid inlen\n"); 1511 return -EINVAL; 1512 } 1513 1514 if (udata->inlen > sizeof(ucmd) && 1515 !ib_is_udata_cleared(udata, sizeof(ucmd), 1516 udata->inlen - sizeof(ucmd))) { 1517 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1518 return -EOPNOTSUPP; 1519 } 1520 1521 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1522 mlx5_ib_dbg(dev, "copy failed\n"); 1523 return -EFAULT; 1524 } 1525 1526 if (ucmd.comp_mask) { 1527 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1528 return -EOPNOTSUPP; 1529 } 1530 1531 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1532 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1533 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { 1534 mlx5_ib_dbg(dev, "invalid flags\n"); 1535 return -EOPNOTSUPP; 1536 } 1537 1538 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1539 !tunnel_offload_supported(dev->mdev)) { 1540 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1541 return -EOPNOTSUPP; 1542 } 1543 1544 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1545 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1546 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1547 return -EOPNOTSUPP; 1548 } 1549 1550 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) { 1551 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1552 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1553 } 1554 1555 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1556 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1557 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1558 } 1559 1560 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1561 if (err) { 1562 mlx5_ib_dbg(dev, "copy failed\n"); 1563 return -EINVAL; 1564 } 1565 1566 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1567 in = kvzalloc(inlen, GFP_KERNEL); 1568 if (!in) 1569 return -ENOMEM; 1570 1571 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1572 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1573 MLX5_SET(tirc, tirc, disp_type, 1574 MLX5_TIRC_DISP_TYPE_INDIRECT); 1575 MLX5_SET(tirc, tirc, indirect_table, 1576 init_attr->rwq_ind_tbl->ind_tbl_num); 1577 MLX5_SET(tirc, tirc, transport_domain, tdn); 1578 1579 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1580 1581 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1582 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1583 1584 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1585 1586 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1587 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1588 else 1589 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1590 1591 switch (ucmd.rx_hash_function) { 1592 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1593 { 1594 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1595 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1596 1597 if (len != ucmd.rx_key_len) { 1598 err = -EINVAL; 1599 goto err; 1600 } 1601 1602 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1603 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1604 memcpy(rss_key, ucmd.rx_hash_key, len); 1605 break; 1606 } 1607 default: 1608 err = -EOPNOTSUPP; 1609 goto err; 1610 } 1611 1612 if (!ucmd.rx_hash_fields_mask) { 1613 /* special case when this TIR serves as steering entry without hashing */ 1614 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1615 goto create_tir; 1616 err = -EINVAL; 1617 goto err; 1618 } 1619 1620 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1621 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1622 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1623 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1624 err = -EINVAL; 1625 goto err; 1626 } 1627 1628 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1629 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1630 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1631 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1632 MLX5_L3_PROT_TYPE_IPV4); 1633 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1634 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1635 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1636 MLX5_L3_PROT_TYPE_IPV6); 1637 1638 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1639 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1640 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1641 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1642 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1643 1644 /* Check that only one l4 protocol is set */ 1645 if (outer_l4 & (outer_l4 - 1)) { 1646 err = -EINVAL; 1647 goto err; 1648 } 1649 1650 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1651 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1652 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1653 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1654 MLX5_L4_PROT_TYPE_TCP); 1655 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1656 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1657 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1658 MLX5_L4_PROT_TYPE_UDP); 1659 1660 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1661 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1662 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1663 1664 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1665 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1666 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1667 1668 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1669 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1670 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1671 1672 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1673 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1674 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1675 1676 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1677 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1678 1679 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1680 1681 create_tir: 1682 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1683 1684 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1685 err = mlx5_ib_enable_lb(dev, false, true); 1686 1687 if (err) 1688 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1689 to_mpd(pd)->uid); 1690 } 1691 1692 if (err) 1693 goto err; 1694 1695 if (mucontext->devx_uid) { 1696 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1697 resp.tirn = qp->rss_qp.tirn; 1698 } 1699 1700 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1701 if (err) 1702 goto err_copy; 1703 1704 kvfree(in); 1705 /* qpn is reserved for that QP */ 1706 qp->trans_qp.base.mqp.qpn = 0; 1707 qp->flags |= MLX5_IB_QP_RSS; 1708 return 0; 1709 1710 err_copy: 1711 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); 1712 err: 1713 kvfree(in); 1714 return err; 1715 } 1716 1717 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, 1718 void *qpc) 1719 { 1720 int rcqe_sz; 1721 1722 if (init_attr->qp_type == MLX5_IB_QPT_DCI) 1723 return; 1724 1725 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1726 1727 if (rcqe_sz == 128) { 1728 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1729 return; 1730 } 1731 1732 if (init_attr->qp_type != MLX5_IB_QPT_DCT) 1733 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1734 } 1735 1736 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1737 struct ib_qp_init_attr *init_attr, 1738 struct mlx5_ib_create_qp *ucmd, 1739 void *qpc) 1740 { 1741 enum ib_qp_type qpt = init_attr->qp_type; 1742 int scqe_sz; 1743 bool allow_scat_cqe = 0; 1744 1745 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) 1746 return; 1747 1748 if (ucmd) 1749 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1750 1751 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1752 return; 1753 1754 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1755 if (scqe_sz == 128) { 1756 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1757 return; 1758 } 1759 1760 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1761 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1762 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1763 } 1764 1765 static int atomic_size_to_mode(int size_mask) 1766 { 1767 /* driver does not support atomic_size > 256B 1768 * and does not know how to translate bigger sizes 1769 */ 1770 int supported_size_mask = size_mask & 0x1ff; 1771 int log_max_size; 1772 1773 if (!supported_size_mask) 1774 return -EOPNOTSUPP; 1775 1776 log_max_size = __fls(supported_size_mask); 1777 1778 if (log_max_size > 3) 1779 return log_max_size; 1780 1781 return MLX5_ATOMIC_MODE_8B; 1782 } 1783 1784 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1785 enum ib_qp_type qp_type) 1786 { 1787 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1788 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1789 int atomic_mode = -EOPNOTSUPP; 1790 int atomic_size_mask; 1791 1792 if (!atomic) 1793 return -EOPNOTSUPP; 1794 1795 if (qp_type == MLX5_IB_QPT_DCT) 1796 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1797 else 1798 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1799 1800 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1801 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1802 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1803 1804 if (atomic_mode <= 0 && 1805 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1806 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1807 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1808 1809 return atomic_mode; 1810 } 1811 1812 static inline bool check_flags_mask(uint64_t input, uint64_t supported) 1813 { 1814 return (input & ~supported) == 0; 1815 } 1816 1817 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1818 struct ib_qp_init_attr *init_attr, 1819 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1820 { 1821 struct mlx5_ib_resources *devr = &dev->devr; 1822 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1823 struct mlx5_core_dev *mdev = dev->mdev; 1824 struct mlx5_ib_create_qp_resp resp = {}; 1825 struct mlx5_ib_cq *send_cq; 1826 struct mlx5_ib_cq *recv_cq; 1827 unsigned long flags; 1828 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1829 struct mlx5_ib_create_qp ucmd; 1830 struct mlx5_ib_qp_base *base; 1831 int mlx5_st; 1832 void *qpc; 1833 u32 *in; 1834 int err; 1835 1836 mutex_init(&qp->mutex); 1837 spin_lock_init(&qp->sq.lock); 1838 spin_lock_init(&qp->rq.lock); 1839 1840 mlx5_st = to_mlx5_st(init_attr->qp_type); 1841 if (mlx5_st < 0) 1842 return -EINVAL; 1843 1844 if (init_attr->rwq_ind_tbl) { 1845 if (!udata) 1846 return -ENOSYS; 1847 1848 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1849 return err; 1850 } 1851 1852 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1853 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1854 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1855 return -EINVAL; 1856 } else { 1857 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1858 } 1859 } 1860 1861 if (init_attr->create_flags & 1862 (IB_QP_CREATE_CROSS_CHANNEL | 1863 IB_QP_CREATE_MANAGED_SEND | 1864 IB_QP_CREATE_MANAGED_RECV)) { 1865 if (!MLX5_CAP_GEN(mdev, cd)) { 1866 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1867 return -EINVAL; 1868 } 1869 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1870 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1871 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1872 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1873 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1874 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1875 } 1876 1877 if (init_attr->qp_type == IB_QPT_UD && 1878 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1879 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1880 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1881 return -EOPNOTSUPP; 1882 } 1883 1884 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1885 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1886 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1887 return -EOPNOTSUPP; 1888 } 1889 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1890 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1891 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1892 return -EOPNOTSUPP; 1893 } 1894 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1895 } 1896 1897 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1898 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1899 1900 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1901 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1902 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1903 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1904 return -EOPNOTSUPP; 1905 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1906 } 1907 1908 if (udata) { 1909 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1910 mlx5_ib_dbg(dev, "copy failed\n"); 1911 return -EFAULT; 1912 } 1913 1914 if (!check_flags_mask(ucmd.flags, 1915 MLX5_QP_FLAG_ALLOW_SCATTER_CQE | 1916 MLX5_QP_FLAG_BFREG_INDEX | 1917 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE | 1918 MLX5_QP_FLAG_SCATTER_CQE | 1919 MLX5_QP_FLAG_SIGNATURE | 1920 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC | 1921 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1922 MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1923 MLX5_QP_FLAG_TYPE_DCI | 1924 MLX5_QP_FLAG_TYPE_DCT)) 1925 return -EINVAL; 1926 1927 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1928 &ucmd, udata->inlen, &uidx); 1929 if (err) 1930 return err; 1931 1932 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1933 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) 1934 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1935 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1936 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1937 !tunnel_offload_supported(mdev)) { 1938 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1939 return -EOPNOTSUPP; 1940 } 1941 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; 1942 } 1943 1944 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { 1945 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1946 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); 1947 return -EOPNOTSUPP; 1948 } 1949 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1950 } 1951 1952 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1953 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1954 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); 1955 return -EOPNOTSUPP; 1956 } 1957 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1958 } 1959 1960 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { 1961 if (init_attr->qp_type != IB_QPT_RC || 1962 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { 1963 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); 1964 return -EOPNOTSUPP; 1965 } 1966 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; 1967 } 1968 1969 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1970 if (init_attr->qp_type != IB_QPT_UD || 1971 (MLX5_CAP_GEN(dev->mdev, port_type) != 1972 MLX5_CAP_PORT_TYPE_IB) || 1973 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1974 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1975 return -EOPNOTSUPP; 1976 } 1977 1978 qp->flags |= MLX5_IB_QP_UNDERLAY; 1979 qp->underlay_qpn = init_attr->source_qpn; 1980 } 1981 } else { 1982 qp->wq_sig = !!wq_signature; 1983 } 1984 1985 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1986 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1987 &qp->raw_packet_qp.rq.base : 1988 &qp->trans_qp.base; 1989 1990 qp->has_rq = qp_has_rq(init_attr); 1991 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1992 qp, udata ? &ucmd : NULL); 1993 if (err) { 1994 mlx5_ib_dbg(dev, "err %d\n", err); 1995 return err; 1996 } 1997 1998 if (pd) { 1999 if (udata) { 2000 __u32 max_wqes = 2001 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 2002 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 2003 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 2004 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 2005 mlx5_ib_dbg(dev, "invalid rq params\n"); 2006 return -EINVAL; 2007 } 2008 if (ucmd.sq_wqe_count > max_wqes) { 2009 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 2010 ucmd.sq_wqe_count, max_wqes); 2011 return -EINVAL; 2012 } 2013 if (init_attr->create_flags & 2014 mlx5_ib_create_qp_sqpn_qp1()) { 2015 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 2016 return -EINVAL; 2017 } 2018 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 2019 &resp, &inlen, base); 2020 if (err) 2021 mlx5_ib_dbg(dev, "err %d\n", err); 2022 } else { 2023 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 2024 base); 2025 if (err) 2026 mlx5_ib_dbg(dev, "err %d\n", err); 2027 } 2028 2029 if (err) 2030 return err; 2031 } else { 2032 in = kvzalloc(inlen, GFP_KERNEL); 2033 if (!in) 2034 return -ENOMEM; 2035 2036 qp->create_type = MLX5_QP_EMPTY; 2037 } 2038 2039 if (is_sqp(init_attr->qp_type)) 2040 qp->port = init_attr->port_num; 2041 2042 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2043 2044 MLX5_SET(qpc, qpc, st, mlx5_st); 2045 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2046 2047 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 2048 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2049 else 2050 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2051 2052 2053 if (qp->wq_sig) 2054 MLX5_SET(qpc, qpc, wq_signature, 1); 2055 2056 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2057 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2058 2059 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 2060 MLX5_SET(qpc, qpc, cd_master, 1); 2061 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 2062 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2063 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 2064 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2065 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) 2066 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2067 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 2068 configure_responder_scat_cqe(init_attr, qpc); 2069 configure_requester_scat_cqe(dev, init_attr, 2070 udata ? &ucmd : NULL, 2071 qpc); 2072 } 2073 2074 if (qp->rq.wqe_cnt) { 2075 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2076 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2077 } 2078 2079 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2080 2081 if (qp->sq.wqe_cnt) { 2082 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2083 } else { 2084 MLX5_SET(qpc, qpc, no_sq, 1); 2085 if (init_attr->srq && 2086 init_attr->srq->srq_type == IB_SRQT_TM) 2087 MLX5_SET(qpc, qpc, offload_type, 2088 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2089 } 2090 2091 /* Set default resources */ 2092 switch (init_attr->qp_type) { 2093 case IB_QPT_XRC_TGT: 2094 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2095 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2096 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2097 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 2098 break; 2099 case IB_QPT_XRC_INI: 2100 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2101 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2102 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2103 break; 2104 default: 2105 if (init_attr->srq) { 2106 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2107 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2108 } else { 2109 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2110 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2111 } 2112 } 2113 2114 if (init_attr->send_cq) 2115 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2116 2117 if (init_attr->recv_cq) 2118 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2119 2120 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2121 2122 /* 0xffffff means we ask to work with cqe version 0 */ 2123 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2124 MLX5_SET(qpc, qpc, user_index, uidx); 2125 2126 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2127 if (init_attr->qp_type == IB_QPT_UD && 2128 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 2129 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2130 qp->flags |= MLX5_IB_QP_LSO; 2131 } 2132 2133 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2134 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 2135 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 2136 err = -EOPNOTSUPP; 2137 goto err; 2138 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2139 MLX5_SET(qpc, qpc, end_padding_mode, 2140 MLX5_WQ_END_PAD_MODE_ALIGN); 2141 } else { 2142 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 2143 } 2144 } 2145 2146 if (inlen < 0) { 2147 err = -EINVAL; 2148 goto err; 2149 } 2150 2151 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2152 qp->flags & MLX5_IB_QP_UNDERLAY) { 2153 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 2154 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2155 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2156 &resp); 2157 } else { 2158 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 2159 } 2160 2161 if (err) { 2162 mlx5_ib_dbg(dev, "create qp failed\n"); 2163 goto err_create; 2164 } 2165 2166 kvfree(in); 2167 2168 base->container_mibqp = qp; 2169 base->mqp.event = mlx5_ib_qp_event; 2170 2171 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 2172 &send_cq, &recv_cq); 2173 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2174 mlx5_ib_lock_cqs(send_cq, recv_cq); 2175 /* Maintain device to QPs access, needed for further handling via reset 2176 * flow 2177 */ 2178 list_add_tail(&qp->qps_list, &dev->qp_list); 2179 /* Maintain CQ to QPs access, needed for further handling via reset flow 2180 */ 2181 if (send_cq) 2182 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2183 if (recv_cq) 2184 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2185 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2186 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2187 2188 return 0; 2189 2190 err_create: 2191 if (qp->create_type == MLX5_QP_USER) 2192 destroy_qp_user(dev, pd, qp, base); 2193 else if (qp->create_type == MLX5_QP_KERNEL) 2194 destroy_qp_kernel(dev, qp); 2195 2196 err: 2197 kvfree(in); 2198 return err; 2199 } 2200 2201 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2202 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2203 { 2204 if (send_cq) { 2205 if (recv_cq) { 2206 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2207 spin_lock(&send_cq->lock); 2208 spin_lock_nested(&recv_cq->lock, 2209 SINGLE_DEPTH_NESTING); 2210 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2211 spin_lock(&send_cq->lock); 2212 __acquire(&recv_cq->lock); 2213 } else { 2214 spin_lock(&recv_cq->lock); 2215 spin_lock_nested(&send_cq->lock, 2216 SINGLE_DEPTH_NESTING); 2217 } 2218 } else { 2219 spin_lock(&send_cq->lock); 2220 __acquire(&recv_cq->lock); 2221 } 2222 } else if (recv_cq) { 2223 spin_lock(&recv_cq->lock); 2224 __acquire(&send_cq->lock); 2225 } else { 2226 __acquire(&send_cq->lock); 2227 __acquire(&recv_cq->lock); 2228 } 2229 } 2230 2231 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2232 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2233 { 2234 if (send_cq) { 2235 if (recv_cq) { 2236 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2237 spin_unlock(&recv_cq->lock); 2238 spin_unlock(&send_cq->lock); 2239 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2240 __release(&recv_cq->lock); 2241 spin_unlock(&send_cq->lock); 2242 } else { 2243 spin_unlock(&send_cq->lock); 2244 spin_unlock(&recv_cq->lock); 2245 } 2246 } else { 2247 __release(&recv_cq->lock); 2248 spin_unlock(&send_cq->lock); 2249 } 2250 } else if (recv_cq) { 2251 __release(&send_cq->lock); 2252 spin_unlock(&recv_cq->lock); 2253 } else { 2254 __release(&recv_cq->lock); 2255 __release(&send_cq->lock); 2256 } 2257 } 2258 2259 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2260 { 2261 return to_mpd(qp->ibqp.pd); 2262 } 2263 2264 static void get_cqs(enum ib_qp_type qp_type, 2265 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2266 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2267 { 2268 switch (qp_type) { 2269 case IB_QPT_XRC_TGT: 2270 *send_cq = NULL; 2271 *recv_cq = NULL; 2272 break; 2273 case MLX5_IB_QPT_REG_UMR: 2274 case IB_QPT_XRC_INI: 2275 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2276 *recv_cq = NULL; 2277 break; 2278 2279 case IB_QPT_SMI: 2280 case MLX5_IB_QPT_HW_GSI: 2281 case IB_QPT_RC: 2282 case IB_QPT_UC: 2283 case IB_QPT_UD: 2284 case IB_QPT_RAW_IPV6: 2285 case IB_QPT_RAW_ETHERTYPE: 2286 case IB_QPT_RAW_PACKET: 2287 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2288 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2289 break; 2290 2291 case IB_QPT_MAX: 2292 default: 2293 *send_cq = NULL; 2294 *recv_cq = NULL; 2295 break; 2296 } 2297 } 2298 2299 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2300 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2301 u8 lag_tx_affinity); 2302 2303 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2304 { 2305 struct mlx5_ib_cq *send_cq, *recv_cq; 2306 struct mlx5_ib_qp_base *base; 2307 unsigned long flags; 2308 int err; 2309 2310 if (qp->ibqp.rwq_ind_tbl) { 2311 destroy_rss_raw_qp_tir(dev, qp); 2312 return; 2313 } 2314 2315 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2316 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2317 &qp->raw_packet_qp.rq.base : 2318 &qp->trans_qp.base; 2319 2320 if (qp->state != IB_QPS_RESET) { 2321 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2322 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2323 err = mlx5_core_qp_modify(dev->mdev, 2324 MLX5_CMD_OP_2RST_QP, 0, 2325 NULL, &base->mqp); 2326 } else { 2327 struct mlx5_modify_raw_qp_param raw_qp_param = { 2328 .operation = MLX5_CMD_OP_2RST_QP 2329 }; 2330 2331 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2332 } 2333 if (err) 2334 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2335 base->mqp.qpn); 2336 } 2337 2338 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2339 &send_cq, &recv_cq); 2340 2341 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2342 mlx5_ib_lock_cqs(send_cq, recv_cq); 2343 /* del from lists under both locks above to protect reset flow paths */ 2344 list_del(&qp->qps_list); 2345 if (send_cq) 2346 list_del(&qp->cq_send_list); 2347 2348 if (recv_cq) 2349 list_del(&qp->cq_recv_list); 2350 2351 if (qp->create_type == MLX5_QP_KERNEL) { 2352 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2353 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2354 if (send_cq != recv_cq) 2355 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2356 NULL); 2357 } 2358 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2359 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2360 2361 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2362 qp->flags & MLX5_IB_QP_UNDERLAY) { 2363 destroy_raw_packet_qp(dev, qp); 2364 } else { 2365 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2366 if (err) 2367 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2368 base->mqp.qpn); 2369 } 2370 2371 if (qp->create_type == MLX5_QP_KERNEL) 2372 destroy_qp_kernel(dev, qp); 2373 else if (qp->create_type == MLX5_QP_USER) 2374 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2375 } 2376 2377 static const char *ib_qp_type_str(enum ib_qp_type type) 2378 { 2379 switch (type) { 2380 case IB_QPT_SMI: 2381 return "IB_QPT_SMI"; 2382 case IB_QPT_GSI: 2383 return "IB_QPT_GSI"; 2384 case IB_QPT_RC: 2385 return "IB_QPT_RC"; 2386 case IB_QPT_UC: 2387 return "IB_QPT_UC"; 2388 case IB_QPT_UD: 2389 return "IB_QPT_UD"; 2390 case IB_QPT_RAW_IPV6: 2391 return "IB_QPT_RAW_IPV6"; 2392 case IB_QPT_RAW_ETHERTYPE: 2393 return "IB_QPT_RAW_ETHERTYPE"; 2394 case IB_QPT_XRC_INI: 2395 return "IB_QPT_XRC_INI"; 2396 case IB_QPT_XRC_TGT: 2397 return "IB_QPT_XRC_TGT"; 2398 case IB_QPT_RAW_PACKET: 2399 return "IB_QPT_RAW_PACKET"; 2400 case MLX5_IB_QPT_REG_UMR: 2401 return "MLX5_IB_QPT_REG_UMR"; 2402 case IB_QPT_DRIVER: 2403 return "IB_QPT_DRIVER"; 2404 case IB_QPT_MAX: 2405 default: 2406 return "Invalid QP type"; 2407 } 2408 } 2409 2410 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2411 struct ib_qp_init_attr *attr, 2412 struct mlx5_ib_create_qp *ucmd) 2413 { 2414 struct mlx5_ib_qp *qp; 2415 int err = 0; 2416 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2417 void *dctc; 2418 2419 if (!attr->srq || !attr->recv_cq) 2420 return ERR_PTR(-EINVAL); 2421 2422 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2423 ucmd, sizeof(*ucmd), &uidx); 2424 if (err) 2425 return ERR_PTR(err); 2426 2427 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2428 if (!qp) 2429 return ERR_PTR(-ENOMEM); 2430 2431 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2432 if (!qp->dct.in) { 2433 err = -ENOMEM; 2434 goto err_free; 2435 } 2436 2437 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2438 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2439 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2440 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2441 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2442 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2443 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2444 MLX5_SET(dctc, dctc, user_index, uidx); 2445 2446 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) 2447 configure_responder_scat_cqe(attr, dctc); 2448 2449 qp->state = IB_QPS_RESET; 2450 2451 return &qp->ibqp; 2452 err_free: 2453 kfree(qp); 2454 return ERR_PTR(err); 2455 } 2456 2457 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2458 struct ib_qp_init_attr *init_attr, 2459 struct mlx5_ib_create_qp *ucmd, 2460 struct ib_udata *udata) 2461 { 2462 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2463 int err; 2464 2465 if (!udata) 2466 return -EINVAL; 2467 2468 if (udata->inlen < sizeof(*ucmd)) { 2469 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2470 return -EINVAL; 2471 } 2472 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2473 if (err) 2474 return err; 2475 2476 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2477 init_attr->qp_type = MLX5_IB_QPT_DCI; 2478 } else { 2479 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2480 init_attr->qp_type = MLX5_IB_QPT_DCT; 2481 } else { 2482 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2483 return -EINVAL; 2484 } 2485 } 2486 2487 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2488 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2489 return -EOPNOTSUPP; 2490 } 2491 2492 return 0; 2493 } 2494 2495 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2496 struct ib_qp_init_attr *verbs_init_attr, 2497 struct ib_udata *udata) 2498 { 2499 struct mlx5_ib_dev *dev; 2500 struct mlx5_ib_qp *qp; 2501 u16 xrcdn = 0; 2502 int err; 2503 struct ib_qp_init_attr mlx_init_attr; 2504 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2505 2506 if (pd) { 2507 dev = to_mdev(pd->device); 2508 2509 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2510 if (!udata) { 2511 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2512 return ERR_PTR(-EINVAL); 2513 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2514 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2515 return ERR_PTR(-EINVAL); 2516 } 2517 } 2518 } else { 2519 /* being cautious here */ 2520 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2521 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2522 pr_warn("%s: no PD for transport %s\n", __func__, 2523 ib_qp_type_str(init_attr->qp_type)); 2524 return ERR_PTR(-EINVAL); 2525 } 2526 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2527 } 2528 2529 if (init_attr->qp_type == IB_QPT_DRIVER) { 2530 struct mlx5_ib_create_qp ucmd; 2531 2532 init_attr = &mlx_init_attr; 2533 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2534 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2535 if (err) 2536 return ERR_PTR(err); 2537 2538 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2539 if (init_attr->cap.max_recv_wr || 2540 init_attr->cap.max_recv_sge) { 2541 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2542 return ERR_PTR(-EINVAL); 2543 } 2544 } else { 2545 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2546 } 2547 } 2548 2549 switch (init_attr->qp_type) { 2550 case IB_QPT_XRC_TGT: 2551 case IB_QPT_XRC_INI: 2552 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2553 mlx5_ib_dbg(dev, "XRC not supported\n"); 2554 return ERR_PTR(-ENOSYS); 2555 } 2556 init_attr->recv_cq = NULL; 2557 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2558 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2559 init_attr->send_cq = NULL; 2560 } 2561 2562 /* fall through */ 2563 case IB_QPT_RAW_PACKET: 2564 case IB_QPT_RC: 2565 case IB_QPT_UC: 2566 case IB_QPT_UD: 2567 case IB_QPT_SMI: 2568 case MLX5_IB_QPT_HW_GSI: 2569 case MLX5_IB_QPT_REG_UMR: 2570 case MLX5_IB_QPT_DCI: 2571 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2572 if (!qp) 2573 return ERR_PTR(-ENOMEM); 2574 2575 err = create_qp_common(dev, pd, init_attr, udata, qp); 2576 if (err) { 2577 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2578 kfree(qp); 2579 return ERR_PTR(err); 2580 } 2581 2582 if (is_qp0(init_attr->qp_type)) 2583 qp->ibqp.qp_num = 0; 2584 else if (is_qp1(init_attr->qp_type)) 2585 qp->ibqp.qp_num = 1; 2586 else 2587 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2588 2589 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2590 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2591 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2592 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2593 2594 qp->trans_qp.xrcdn = xrcdn; 2595 2596 break; 2597 2598 case IB_QPT_GSI: 2599 return mlx5_ib_gsi_create_qp(pd, init_attr); 2600 2601 case IB_QPT_RAW_IPV6: 2602 case IB_QPT_RAW_ETHERTYPE: 2603 case IB_QPT_MAX: 2604 default: 2605 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2606 init_attr->qp_type); 2607 /* Don't support raw QPs */ 2608 return ERR_PTR(-EINVAL); 2609 } 2610 2611 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2612 qp->qp_sub_type = init_attr->qp_type; 2613 2614 return &qp->ibqp; 2615 } 2616 2617 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2618 { 2619 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2620 2621 if (mqp->state == IB_QPS_RTR) { 2622 int err; 2623 2624 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2625 if (err) { 2626 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2627 return err; 2628 } 2629 } 2630 2631 kfree(mqp->dct.in); 2632 kfree(mqp); 2633 return 0; 2634 } 2635 2636 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2637 { 2638 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2639 struct mlx5_ib_qp *mqp = to_mqp(qp); 2640 2641 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2642 return mlx5_ib_gsi_destroy_qp(qp); 2643 2644 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2645 return mlx5_ib_destroy_dct(mqp); 2646 2647 destroy_qp_common(dev, mqp); 2648 2649 kfree(mqp); 2650 2651 return 0; 2652 } 2653 2654 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2655 const struct ib_qp_attr *attr, 2656 int attr_mask, __be32 *hw_access_flags) 2657 { 2658 u8 dest_rd_atomic; 2659 u32 access_flags; 2660 2661 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2662 2663 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2664 dest_rd_atomic = attr->max_dest_rd_atomic; 2665 else 2666 dest_rd_atomic = qp->trans_qp.resp_depth; 2667 2668 if (attr_mask & IB_QP_ACCESS_FLAGS) 2669 access_flags = attr->qp_access_flags; 2670 else 2671 access_flags = qp->trans_qp.atomic_rd_en; 2672 2673 if (!dest_rd_atomic) 2674 access_flags &= IB_ACCESS_REMOTE_WRITE; 2675 2676 if (access_flags & IB_ACCESS_REMOTE_READ) 2677 *hw_access_flags |= MLX5_QP_BIT_RRE; 2678 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2679 int atomic_mode; 2680 2681 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2682 if (atomic_mode < 0) 2683 return -EOPNOTSUPP; 2684 2685 *hw_access_flags |= MLX5_QP_BIT_RAE; 2686 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; 2687 } 2688 2689 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2690 *hw_access_flags |= MLX5_QP_BIT_RWE; 2691 2692 *hw_access_flags = cpu_to_be32(*hw_access_flags); 2693 2694 return 0; 2695 } 2696 2697 enum { 2698 MLX5_PATH_FLAG_FL = 1 << 0, 2699 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2700 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2701 }; 2702 2703 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2704 { 2705 if (rate == IB_RATE_PORT_CURRENT) 2706 return 0; 2707 2708 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 2709 return -EINVAL; 2710 2711 while (rate != IB_RATE_PORT_CURRENT && 2712 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2713 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2714 --rate; 2715 2716 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2717 } 2718 2719 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2720 struct mlx5_ib_sq *sq, u8 sl, 2721 struct ib_pd *pd) 2722 { 2723 void *in; 2724 void *tisc; 2725 int inlen; 2726 int err; 2727 2728 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2729 in = kvzalloc(inlen, GFP_KERNEL); 2730 if (!in) 2731 return -ENOMEM; 2732 2733 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2734 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2735 2736 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2737 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2738 2739 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2740 2741 kvfree(in); 2742 2743 return err; 2744 } 2745 2746 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2747 struct mlx5_ib_sq *sq, u8 tx_affinity, 2748 struct ib_pd *pd) 2749 { 2750 void *in; 2751 void *tisc; 2752 int inlen; 2753 int err; 2754 2755 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2756 in = kvzalloc(inlen, GFP_KERNEL); 2757 if (!in) 2758 return -ENOMEM; 2759 2760 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2761 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2762 2763 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2764 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2765 2766 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2767 2768 kvfree(in); 2769 2770 return err; 2771 } 2772 2773 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2774 const struct rdma_ah_attr *ah, 2775 struct mlx5_qp_path *path, u8 port, int attr_mask, 2776 u32 path_flags, const struct ib_qp_attr *attr, 2777 bool alt) 2778 { 2779 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2780 int err; 2781 enum ib_gid_type gid_type; 2782 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2783 u8 sl = rdma_ah_get_sl(ah); 2784 2785 if (attr_mask & IB_QP_PKEY_INDEX) 2786 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2787 attr->pkey_index); 2788 2789 if (ah_flags & IB_AH_GRH) { 2790 if (grh->sgid_index >= 2791 dev->mdev->port_caps[port - 1].gid_table_len) { 2792 pr_err("sgid_index (%u) too large. max is %d\n", 2793 grh->sgid_index, 2794 dev->mdev->port_caps[port - 1].gid_table_len); 2795 return -EINVAL; 2796 } 2797 } 2798 2799 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2800 if (!(ah_flags & IB_AH_GRH)) 2801 return -EINVAL; 2802 2803 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2804 if (qp->ibqp.qp_type == IB_QPT_RC || 2805 qp->ibqp.qp_type == IB_QPT_UC || 2806 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2807 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2808 path->udp_sport = 2809 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); 2810 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2811 gid_type = ah->grh.sgid_attr->gid_type; 2812 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2813 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2814 } else { 2815 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2816 path->fl_free_ar |= 2817 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2818 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2819 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2820 if (ah_flags & IB_AH_GRH) 2821 path->grh_mlid |= 1 << 7; 2822 path->dci_cfi_prio_sl = sl & 0xf; 2823 } 2824 2825 if (ah_flags & IB_AH_GRH) { 2826 path->mgid_index = grh->sgid_index; 2827 path->hop_limit = grh->hop_limit; 2828 path->tclass_flowlabel = 2829 cpu_to_be32((grh->traffic_class << 20) | 2830 (grh->flow_label)); 2831 memcpy(path->rgid, grh->dgid.raw, 16); 2832 } 2833 2834 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2835 if (err < 0) 2836 return err; 2837 path->static_rate = err; 2838 path->port = port; 2839 2840 if (attr_mask & IB_QP_TIMEOUT) 2841 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2842 2843 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2844 return modify_raw_packet_eth_prio(dev->mdev, 2845 &qp->raw_packet_qp.sq, 2846 sl & 0xf, qp->ibqp.pd); 2847 2848 return 0; 2849 } 2850 2851 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2852 [MLX5_QP_STATE_INIT] = { 2853 [MLX5_QP_STATE_INIT] = { 2854 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2855 MLX5_QP_OPTPAR_RAE | 2856 MLX5_QP_OPTPAR_RWE | 2857 MLX5_QP_OPTPAR_PKEY_INDEX | 2858 MLX5_QP_OPTPAR_PRI_PORT, 2859 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2860 MLX5_QP_OPTPAR_PKEY_INDEX | 2861 MLX5_QP_OPTPAR_PRI_PORT, 2862 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2863 MLX5_QP_OPTPAR_Q_KEY | 2864 MLX5_QP_OPTPAR_PRI_PORT, 2865 }, 2866 [MLX5_QP_STATE_RTR] = { 2867 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2868 MLX5_QP_OPTPAR_RRE | 2869 MLX5_QP_OPTPAR_RAE | 2870 MLX5_QP_OPTPAR_RWE | 2871 MLX5_QP_OPTPAR_PKEY_INDEX, 2872 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2873 MLX5_QP_OPTPAR_RWE | 2874 MLX5_QP_OPTPAR_PKEY_INDEX, 2875 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2876 MLX5_QP_OPTPAR_Q_KEY, 2877 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2878 MLX5_QP_OPTPAR_Q_KEY, 2879 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2880 MLX5_QP_OPTPAR_RRE | 2881 MLX5_QP_OPTPAR_RAE | 2882 MLX5_QP_OPTPAR_RWE | 2883 MLX5_QP_OPTPAR_PKEY_INDEX, 2884 }, 2885 }, 2886 [MLX5_QP_STATE_RTR] = { 2887 [MLX5_QP_STATE_RTS] = { 2888 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2889 MLX5_QP_OPTPAR_RRE | 2890 MLX5_QP_OPTPAR_RAE | 2891 MLX5_QP_OPTPAR_RWE | 2892 MLX5_QP_OPTPAR_PM_STATE | 2893 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2894 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2895 MLX5_QP_OPTPAR_RWE | 2896 MLX5_QP_OPTPAR_PM_STATE, 2897 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2898 }, 2899 }, 2900 [MLX5_QP_STATE_RTS] = { 2901 [MLX5_QP_STATE_RTS] = { 2902 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2903 MLX5_QP_OPTPAR_RAE | 2904 MLX5_QP_OPTPAR_RWE | 2905 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2906 MLX5_QP_OPTPAR_PM_STATE | 2907 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2908 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2909 MLX5_QP_OPTPAR_PM_STATE | 2910 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2911 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2912 MLX5_QP_OPTPAR_SRQN | 2913 MLX5_QP_OPTPAR_CQN_RCV, 2914 }, 2915 }, 2916 [MLX5_QP_STATE_SQER] = { 2917 [MLX5_QP_STATE_RTS] = { 2918 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2919 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2920 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2921 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2922 MLX5_QP_OPTPAR_RWE | 2923 MLX5_QP_OPTPAR_RAE | 2924 MLX5_QP_OPTPAR_RRE, 2925 }, 2926 }, 2927 }; 2928 2929 static int ib_nr_to_mlx5_nr(int ib_mask) 2930 { 2931 switch (ib_mask) { 2932 case IB_QP_STATE: 2933 return 0; 2934 case IB_QP_CUR_STATE: 2935 return 0; 2936 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2937 return 0; 2938 case IB_QP_ACCESS_FLAGS: 2939 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2940 MLX5_QP_OPTPAR_RAE; 2941 case IB_QP_PKEY_INDEX: 2942 return MLX5_QP_OPTPAR_PKEY_INDEX; 2943 case IB_QP_PORT: 2944 return MLX5_QP_OPTPAR_PRI_PORT; 2945 case IB_QP_QKEY: 2946 return MLX5_QP_OPTPAR_Q_KEY; 2947 case IB_QP_AV: 2948 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2949 MLX5_QP_OPTPAR_PRI_PORT; 2950 case IB_QP_PATH_MTU: 2951 return 0; 2952 case IB_QP_TIMEOUT: 2953 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2954 case IB_QP_RETRY_CNT: 2955 return MLX5_QP_OPTPAR_RETRY_COUNT; 2956 case IB_QP_RNR_RETRY: 2957 return MLX5_QP_OPTPAR_RNR_RETRY; 2958 case IB_QP_RQ_PSN: 2959 return 0; 2960 case IB_QP_MAX_QP_RD_ATOMIC: 2961 return MLX5_QP_OPTPAR_SRA_MAX; 2962 case IB_QP_ALT_PATH: 2963 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2964 case IB_QP_MIN_RNR_TIMER: 2965 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2966 case IB_QP_SQ_PSN: 2967 return 0; 2968 case IB_QP_MAX_DEST_RD_ATOMIC: 2969 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2970 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2971 case IB_QP_PATH_MIG_STATE: 2972 return MLX5_QP_OPTPAR_PM_STATE; 2973 case IB_QP_CAP: 2974 return 0; 2975 case IB_QP_DEST_QPN: 2976 return 0; 2977 } 2978 return 0; 2979 } 2980 2981 static int ib_mask_to_mlx5_opt(int ib_mask) 2982 { 2983 int result = 0; 2984 int i; 2985 2986 for (i = 0; i < 8 * sizeof(int); i++) { 2987 if ((1 << i) & ib_mask) 2988 result |= ib_nr_to_mlx5_nr(1 << i); 2989 } 2990 2991 return result; 2992 } 2993 2994 static int modify_raw_packet_qp_rq( 2995 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 2996 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 2997 { 2998 void *in; 2999 void *rqc; 3000 int inlen; 3001 int err; 3002 3003 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3004 in = kvzalloc(inlen, GFP_KERNEL); 3005 if (!in) 3006 return -ENOMEM; 3007 3008 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3009 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3010 3011 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3012 MLX5_SET(rqc, rqc, state, new_state); 3013 3014 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3015 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3016 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3017 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3018 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3019 } else 3020 dev_info_once( 3021 &dev->ib_dev.dev, 3022 "RAW PACKET QP counters are not supported on current FW\n"); 3023 } 3024 3025 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 3026 if (err) 3027 goto out; 3028 3029 rq->state = new_state; 3030 3031 out: 3032 kvfree(in); 3033 return err; 3034 } 3035 3036 static int modify_raw_packet_qp_sq( 3037 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3038 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3039 { 3040 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3041 struct mlx5_rate_limit old_rl = ibqp->rl; 3042 struct mlx5_rate_limit new_rl = old_rl; 3043 bool new_rate_added = false; 3044 u16 rl_index = 0; 3045 void *in; 3046 void *sqc; 3047 int inlen; 3048 int err; 3049 3050 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3051 in = kvzalloc(inlen, GFP_KERNEL); 3052 if (!in) 3053 return -ENOMEM; 3054 3055 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3056 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3057 3058 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3059 MLX5_SET(sqc, sqc, state, new_state); 3060 3061 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3062 if (new_state != MLX5_SQC_STATE_RDY) 3063 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3064 __func__); 3065 else 3066 new_rl = raw_qp_param->rl; 3067 } 3068 3069 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3070 if (new_rl.rate) { 3071 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3072 if (err) { 3073 pr_err("Failed configuring rate limit(err %d): \ 3074 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3075 err, new_rl.rate, new_rl.max_burst_sz, 3076 new_rl.typical_pkt_sz); 3077 3078 goto out; 3079 } 3080 new_rate_added = true; 3081 } 3082 3083 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3084 /* index 0 means no limit */ 3085 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3086 } 3087 3088 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 3089 if (err) { 3090 /* Remove new rate from table if failed */ 3091 if (new_rate_added) 3092 mlx5_rl_remove_rate(dev, &new_rl); 3093 goto out; 3094 } 3095 3096 /* Only remove the old rate after new rate was set */ 3097 if ((old_rl.rate && 3098 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3099 (new_state != MLX5_SQC_STATE_RDY)) 3100 mlx5_rl_remove_rate(dev, &old_rl); 3101 3102 ibqp->rl = new_rl; 3103 sq->state = new_state; 3104 3105 out: 3106 kvfree(in); 3107 return err; 3108 } 3109 3110 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3111 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3112 u8 tx_affinity) 3113 { 3114 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3115 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3116 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3117 int modify_rq = !!qp->rq.wqe_cnt; 3118 int modify_sq = !!qp->sq.wqe_cnt; 3119 int rq_state; 3120 int sq_state; 3121 int err; 3122 3123 switch (raw_qp_param->operation) { 3124 case MLX5_CMD_OP_RST2INIT_QP: 3125 rq_state = MLX5_RQC_STATE_RDY; 3126 sq_state = MLX5_SQC_STATE_RDY; 3127 break; 3128 case MLX5_CMD_OP_2ERR_QP: 3129 rq_state = MLX5_RQC_STATE_ERR; 3130 sq_state = MLX5_SQC_STATE_ERR; 3131 break; 3132 case MLX5_CMD_OP_2RST_QP: 3133 rq_state = MLX5_RQC_STATE_RST; 3134 sq_state = MLX5_SQC_STATE_RST; 3135 break; 3136 case MLX5_CMD_OP_RTR2RTS_QP: 3137 case MLX5_CMD_OP_RTS2RTS_QP: 3138 if (raw_qp_param->set_mask == 3139 MLX5_RAW_QP_RATE_LIMIT) { 3140 modify_rq = 0; 3141 sq_state = sq->state; 3142 } else { 3143 return raw_qp_param->set_mask ? -EINVAL : 0; 3144 } 3145 break; 3146 case MLX5_CMD_OP_INIT2INIT_QP: 3147 case MLX5_CMD_OP_INIT2RTR_QP: 3148 if (raw_qp_param->set_mask) 3149 return -EINVAL; 3150 else 3151 return 0; 3152 default: 3153 WARN_ON(1); 3154 return -EINVAL; 3155 } 3156 3157 if (modify_rq) { 3158 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3159 qp->ibqp.pd); 3160 if (err) 3161 return err; 3162 } 3163 3164 if (modify_sq) { 3165 if (tx_affinity) { 3166 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3167 tx_affinity, 3168 qp->ibqp.pd); 3169 if (err) 3170 return err; 3171 } 3172 3173 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3174 raw_qp_param, qp->ibqp.pd); 3175 } 3176 3177 return 0; 3178 } 3179 3180 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, 3181 struct mlx5_ib_pd *pd, 3182 struct mlx5_ib_qp_base *qp_base, 3183 u8 port_num) 3184 { 3185 struct mlx5_ib_ucontext *ucontext = NULL; 3186 unsigned int tx_port_affinity; 3187 3188 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context) 3189 ucontext = to_mucontext(pd->ibpd.uobject->context); 3190 3191 if (ucontext) { 3192 tx_port_affinity = (unsigned int)atomic_add_return( 3193 1, &ucontext->tx_port_affinity) % 3194 MLX5_MAX_PORTS + 3195 1; 3196 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3197 tx_port_affinity, qp_base->mqp.qpn, ucontext); 3198 } else { 3199 tx_port_affinity = 3200 (unsigned int)atomic_add_return( 3201 1, &dev->roce[port_num].tx_port_affinity) % 3202 MLX5_MAX_PORTS + 3203 1; 3204 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3205 tx_port_affinity, qp_base->mqp.qpn); 3206 } 3207 3208 return tx_port_affinity; 3209 } 3210 3211 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3212 const struct ib_qp_attr *attr, int attr_mask, 3213 enum ib_qp_state cur_state, enum ib_qp_state new_state, 3214 const struct mlx5_ib_modify_qp *ucmd) 3215 { 3216 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3217 [MLX5_QP_STATE_RST] = { 3218 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3219 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3220 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3221 }, 3222 [MLX5_QP_STATE_INIT] = { 3223 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3224 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3225 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3226 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3227 }, 3228 [MLX5_QP_STATE_RTR] = { 3229 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3230 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3231 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3232 }, 3233 [MLX5_QP_STATE_RTS] = { 3234 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3235 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3236 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3237 }, 3238 [MLX5_QP_STATE_SQD] = { 3239 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3240 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3241 }, 3242 [MLX5_QP_STATE_SQER] = { 3243 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3244 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3245 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3246 }, 3247 [MLX5_QP_STATE_ERR] = { 3248 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3249 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3250 } 3251 }; 3252 3253 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3254 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3255 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3256 struct mlx5_ib_cq *send_cq, *recv_cq; 3257 struct mlx5_qp_context *context; 3258 struct mlx5_ib_pd *pd; 3259 struct mlx5_ib_port *mibport = NULL; 3260 enum mlx5_qp_state mlx5_cur, mlx5_new; 3261 enum mlx5_qp_optpar optpar; 3262 int mlx5_st; 3263 int err; 3264 u16 op; 3265 u8 tx_affinity = 0; 3266 3267 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3268 qp->qp_sub_type : ibqp->qp_type); 3269 if (mlx5_st < 0) 3270 return -EINVAL; 3271 3272 context = kzalloc(sizeof(*context), GFP_KERNEL); 3273 if (!context) 3274 return -ENOMEM; 3275 3276 pd = get_pd(qp); 3277 context->flags = cpu_to_be32(mlx5_st << 16); 3278 3279 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3280 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3281 } else { 3282 switch (attr->path_mig_state) { 3283 case IB_MIG_MIGRATED: 3284 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3285 break; 3286 case IB_MIG_REARM: 3287 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3288 break; 3289 case IB_MIG_ARMED: 3290 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3291 break; 3292 } 3293 } 3294 3295 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3296 if ((ibqp->qp_type == IB_QPT_RC) || 3297 (ibqp->qp_type == IB_QPT_UD && 3298 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3299 (ibqp->qp_type == IB_QPT_UC) || 3300 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3301 (ibqp->qp_type == IB_QPT_XRC_INI) || 3302 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3303 if (dev->lag_active) { 3304 u8 p = mlx5_core_native_port_num(dev->mdev); 3305 tx_affinity = get_tx_affinity(dev, pd, base, p); 3306 context->flags |= cpu_to_be32(tx_affinity << 24); 3307 } 3308 } 3309 } 3310 3311 if (is_sqp(ibqp->qp_type)) { 3312 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3313 } else if ((ibqp->qp_type == IB_QPT_UD && 3314 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3315 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3316 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3317 } else if (attr_mask & IB_QP_PATH_MTU) { 3318 if (attr->path_mtu < IB_MTU_256 || 3319 attr->path_mtu > IB_MTU_4096) { 3320 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3321 err = -EINVAL; 3322 goto out; 3323 } 3324 context->mtu_msgmax = (attr->path_mtu << 5) | 3325 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3326 } 3327 3328 if (attr_mask & IB_QP_DEST_QPN) 3329 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3330 3331 if (attr_mask & IB_QP_PKEY_INDEX) 3332 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3333 3334 /* todo implement counter_index functionality */ 3335 3336 if (is_sqp(ibqp->qp_type)) 3337 context->pri_path.port = qp->port; 3338 3339 if (attr_mask & IB_QP_PORT) 3340 context->pri_path.port = attr->port_num; 3341 3342 if (attr_mask & IB_QP_AV) { 3343 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3344 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3345 attr_mask, 0, attr, false); 3346 if (err) 3347 goto out; 3348 } 3349 3350 if (attr_mask & IB_QP_TIMEOUT) 3351 context->pri_path.ackto_lt |= attr->timeout << 3; 3352 3353 if (attr_mask & IB_QP_ALT_PATH) { 3354 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3355 &context->alt_path, 3356 attr->alt_port_num, 3357 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3358 0, attr, true); 3359 if (err) 3360 goto out; 3361 } 3362 3363 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3364 &send_cq, &recv_cq); 3365 3366 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3367 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3368 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3369 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3370 3371 if (attr_mask & IB_QP_RNR_RETRY) 3372 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3373 3374 if (attr_mask & IB_QP_RETRY_CNT) 3375 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3376 3377 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3378 if (attr->max_rd_atomic) 3379 context->params1 |= 3380 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3381 } 3382 3383 if (attr_mask & IB_QP_SQ_PSN) 3384 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3385 3386 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3387 if (attr->max_dest_rd_atomic) 3388 context->params2 |= 3389 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3390 } 3391 3392 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3393 __be32 access_flags = 0; 3394 3395 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 3396 if (err) 3397 goto out; 3398 3399 context->params2 |= access_flags; 3400 } 3401 3402 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3403 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3404 3405 if (attr_mask & IB_QP_RQ_PSN) 3406 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3407 3408 if (attr_mask & IB_QP_QKEY) 3409 context->qkey = cpu_to_be32(attr->qkey); 3410 3411 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3412 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3413 3414 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3415 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3416 qp->port) - 1; 3417 3418 /* Underlay port should be used - index 0 function per port */ 3419 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3420 port_num = 0; 3421 3422 mibport = &dev->port[port_num]; 3423 context->qp_counter_set_usr_page |= 3424 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3425 } 3426 3427 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3428 context->sq_crq_size |= cpu_to_be16(1 << 4); 3429 3430 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3431 context->deth_sqpn = cpu_to_be32(1); 3432 3433 mlx5_cur = to_mlx5_state(cur_state); 3434 mlx5_new = to_mlx5_state(new_state); 3435 3436 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3437 !optab[mlx5_cur][mlx5_new]) { 3438 err = -EINVAL; 3439 goto out; 3440 } 3441 3442 op = optab[mlx5_cur][mlx5_new]; 3443 optpar = ib_mask_to_mlx5_opt(attr_mask); 3444 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3445 3446 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3447 qp->flags & MLX5_IB_QP_UNDERLAY) { 3448 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3449 3450 raw_qp_param.operation = op; 3451 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3452 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3453 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3454 } 3455 3456 if (attr_mask & IB_QP_RATE_LIMIT) { 3457 raw_qp_param.rl.rate = attr->rate_limit; 3458 3459 if (ucmd->burst_info.max_burst_sz) { 3460 if (attr->rate_limit && 3461 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3462 raw_qp_param.rl.max_burst_sz = 3463 ucmd->burst_info.max_burst_sz; 3464 } else { 3465 err = -EINVAL; 3466 goto out; 3467 } 3468 } 3469 3470 if (ucmd->burst_info.typical_pkt_sz) { 3471 if (attr->rate_limit && 3472 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3473 raw_qp_param.rl.typical_pkt_sz = 3474 ucmd->burst_info.typical_pkt_sz; 3475 } else { 3476 err = -EINVAL; 3477 goto out; 3478 } 3479 } 3480 3481 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3482 } 3483 3484 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3485 } else { 3486 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3487 &base->mqp); 3488 } 3489 3490 if (err) 3491 goto out; 3492 3493 qp->state = new_state; 3494 3495 if (attr_mask & IB_QP_ACCESS_FLAGS) 3496 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3497 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3498 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3499 if (attr_mask & IB_QP_PORT) 3500 qp->port = attr->port_num; 3501 if (attr_mask & IB_QP_ALT_PATH) 3502 qp->trans_qp.alt_port = attr->alt_port_num; 3503 3504 /* 3505 * If we moved a kernel QP to RESET, clean up all old CQ 3506 * entries and reinitialize the QP. 3507 */ 3508 if (new_state == IB_QPS_RESET && 3509 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3510 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3511 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3512 if (send_cq != recv_cq) 3513 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3514 3515 qp->rq.head = 0; 3516 qp->rq.tail = 0; 3517 qp->sq.head = 0; 3518 qp->sq.tail = 0; 3519 qp->sq.cur_post = 0; 3520 if (qp->sq.wqe_cnt) 3521 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 3522 qp->db.db[MLX5_RCV_DBR] = 0; 3523 qp->db.db[MLX5_SND_DBR] = 0; 3524 } 3525 3526 out: 3527 kfree(context); 3528 return err; 3529 } 3530 3531 static inline bool is_valid_mask(int mask, int req, int opt) 3532 { 3533 if ((mask & req) != req) 3534 return false; 3535 3536 if (mask & ~(req | opt)) 3537 return false; 3538 3539 return true; 3540 } 3541 3542 /* check valid transition for driver QP types 3543 * for now the only QP type that this function supports is DCI 3544 */ 3545 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3546 enum ib_qp_attr_mask attr_mask) 3547 { 3548 int req = IB_QP_STATE; 3549 int opt = 0; 3550 3551 if (new_state == IB_QPS_RESET) { 3552 return is_valid_mask(attr_mask, req, opt); 3553 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3554 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3555 return is_valid_mask(attr_mask, req, opt); 3556 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3557 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3558 return is_valid_mask(attr_mask, req, opt); 3559 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3560 req |= IB_QP_PATH_MTU; 3561 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 3562 return is_valid_mask(attr_mask, req, opt); 3563 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3564 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3565 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3566 opt = IB_QP_MIN_RNR_TIMER; 3567 return is_valid_mask(attr_mask, req, opt); 3568 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3569 opt = IB_QP_MIN_RNR_TIMER; 3570 return is_valid_mask(attr_mask, req, opt); 3571 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3572 return is_valid_mask(attr_mask, req, opt); 3573 } 3574 return false; 3575 } 3576 3577 /* mlx5_ib_modify_dct: modify a DCT QP 3578 * valid transitions are: 3579 * RESET to INIT: must set access_flags, pkey_index and port 3580 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3581 * mtu, gid_index and hop_limit 3582 * Other transitions and attributes are illegal 3583 */ 3584 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3585 int attr_mask, struct ib_udata *udata) 3586 { 3587 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3588 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3589 enum ib_qp_state cur_state, new_state; 3590 int err = 0; 3591 int required = IB_QP_STATE; 3592 void *dctc; 3593 3594 if (!(attr_mask & IB_QP_STATE)) 3595 return -EINVAL; 3596 3597 cur_state = qp->state; 3598 new_state = attr->qp_state; 3599 3600 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3601 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3602 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3603 if (!is_valid_mask(attr_mask, required, 0)) 3604 return -EINVAL; 3605 3606 if (attr->port_num == 0 || 3607 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3608 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3609 attr->port_num, dev->num_ports); 3610 return -EINVAL; 3611 } 3612 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3613 MLX5_SET(dctc, dctc, rre, 1); 3614 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3615 MLX5_SET(dctc, dctc, rwe, 1); 3616 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3617 int atomic_mode; 3618 3619 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 3620 if (atomic_mode < 0) 3621 return -EOPNOTSUPP; 3622 3623 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 3624 MLX5_SET(dctc, dctc, rae, 1); 3625 } 3626 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3627 MLX5_SET(dctc, dctc, port, attr->port_num); 3628 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3629 3630 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3631 struct mlx5_ib_modify_qp_resp resp = {}; 3632 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3633 sizeof(resp.dctn); 3634 3635 if (udata->outlen < min_resp_len) 3636 return -EINVAL; 3637 resp.response_length = min_resp_len; 3638 3639 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3640 if (!is_valid_mask(attr_mask, required, 0)) 3641 return -EINVAL; 3642 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3643 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3644 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3645 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3646 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3647 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3648 3649 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3650 MLX5_ST_SZ_BYTES(create_dct_in)); 3651 if (err) 3652 return err; 3653 resp.dctn = qp->dct.mdct.mqp.qpn; 3654 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3655 if (err) { 3656 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3657 return err; 3658 } 3659 } else { 3660 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3661 return -EINVAL; 3662 } 3663 if (err) 3664 qp->state = IB_QPS_ERR; 3665 else 3666 qp->state = new_state; 3667 return err; 3668 } 3669 3670 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3671 int attr_mask, struct ib_udata *udata) 3672 { 3673 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3674 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3675 struct mlx5_ib_modify_qp ucmd = {}; 3676 enum ib_qp_type qp_type; 3677 enum ib_qp_state cur_state, new_state; 3678 size_t required_cmd_sz; 3679 int err = -EINVAL; 3680 int port; 3681 3682 if (ibqp->rwq_ind_tbl) 3683 return -ENOSYS; 3684 3685 if (udata && udata->inlen) { 3686 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3687 sizeof(ucmd.reserved); 3688 if (udata->inlen < required_cmd_sz) 3689 return -EINVAL; 3690 3691 if (udata->inlen > sizeof(ucmd) && 3692 !ib_is_udata_cleared(udata, sizeof(ucmd), 3693 udata->inlen - sizeof(ucmd))) 3694 return -EOPNOTSUPP; 3695 3696 if (ib_copy_from_udata(&ucmd, udata, 3697 min(udata->inlen, sizeof(ucmd)))) 3698 return -EFAULT; 3699 3700 if (ucmd.comp_mask || 3701 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3702 memchr_inv(&ucmd.burst_info.reserved, 0, 3703 sizeof(ucmd.burst_info.reserved))) 3704 return -EOPNOTSUPP; 3705 } 3706 3707 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3708 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3709 3710 if (ibqp->qp_type == IB_QPT_DRIVER) 3711 qp_type = qp->qp_sub_type; 3712 else 3713 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3714 IB_QPT_GSI : ibqp->qp_type; 3715 3716 if (qp_type == MLX5_IB_QPT_DCT) 3717 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3718 3719 mutex_lock(&qp->mutex); 3720 3721 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3722 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3723 3724 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3725 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3726 } 3727 3728 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3729 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3730 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3731 attr_mask); 3732 goto out; 3733 } 3734 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3735 qp_type != MLX5_IB_QPT_DCI && 3736 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 3737 attr_mask)) { 3738 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3739 cur_state, new_state, ibqp->qp_type, attr_mask); 3740 goto out; 3741 } else if (qp_type == MLX5_IB_QPT_DCI && 3742 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3743 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3744 cur_state, new_state, qp_type, attr_mask); 3745 goto out; 3746 } 3747 3748 if ((attr_mask & IB_QP_PORT) && 3749 (attr->port_num == 0 || 3750 attr->port_num > dev->num_ports)) { 3751 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3752 attr->port_num, dev->num_ports); 3753 goto out; 3754 } 3755 3756 if (attr_mask & IB_QP_PKEY_INDEX) { 3757 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3758 if (attr->pkey_index >= 3759 dev->mdev->port_caps[port - 1].pkey_table_len) { 3760 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3761 attr->pkey_index); 3762 goto out; 3763 } 3764 } 3765 3766 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3767 attr->max_rd_atomic > 3768 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3769 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3770 attr->max_rd_atomic); 3771 goto out; 3772 } 3773 3774 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3775 attr->max_dest_rd_atomic > 3776 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3777 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3778 attr->max_dest_rd_atomic); 3779 goto out; 3780 } 3781 3782 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3783 err = 0; 3784 goto out; 3785 } 3786 3787 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3788 new_state, &ucmd); 3789 3790 out: 3791 mutex_unlock(&qp->mutex); 3792 return err; 3793 } 3794 3795 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3796 u32 wqe_sz, void **cur_edge) 3797 { 3798 u32 idx; 3799 3800 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); 3801 *cur_edge = get_sq_edge(sq, idx); 3802 3803 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); 3804 } 3805 3806 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the 3807 * next nearby edge and get new address translation for current WQE position. 3808 * @sq - SQ buffer. 3809 * @seg: Current WQE position (16B aligned). 3810 * @wqe_sz: Total current WQE size [16B]. 3811 * @cur_edge: Updated current edge. 3812 */ 3813 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3814 u32 wqe_sz, void **cur_edge) 3815 { 3816 if (likely(*seg != *cur_edge)) 3817 return; 3818 3819 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); 3820 } 3821 3822 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's 3823 * pointers. At the end @seg is aligned to 16B regardless the copied size. 3824 * @sq - SQ buffer. 3825 * @cur_edge: Updated current edge. 3826 * @seg: Current WQE position (16B aligned). 3827 * @wqe_sz: Total current WQE size [16B]. 3828 * @src: Pointer to copy from. 3829 * @n: Number of bytes to copy. 3830 */ 3831 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, 3832 void **seg, u32 *wqe_sz, const void *src, 3833 size_t n) 3834 { 3835 while (likely(n)) { 3836 size_t leftlen = *cur_edge - *seg; 3837 size_t copysz = min_t(size_t, leftlen, n); 3838 size_t stride; 3839 3840 memcpy(*seg, src, copysz); 3841 3842 n -= copysz; 3843 src += copysz; 3844 stride = !n ? ALIGN(copysz, 16) : copysz; 3845 *seg += stride; 3846 *wqe_sz += stride >> 4; 3847 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); 3848 } 3849 } 3850 3851 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3852 { 3853 struct mlx5_ib_cq *cq; 3854 unsigned cur; 3855 3856 cur = wq->head - wq->tail; 3857 if (likely(cur + nreq < wq->max_post)) 3858 return 0; 3859 3860 cq = to_mcq(ib_cq); 3861 spin_lock(&cq->lock); 3862 cur = wq->head - wq->tail; 3863 spin_unlock(&cq->lock); 3864 3865 return cur + nreq >= wq->max_post; 3866 } 3867 3868 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3869 u64 remote_addr, u32 rkey) 3870 { 3871 rseg->raddr = cpu_to_be64(remote_addr); 3872 rseg->rkey = cpu_to_be32(rkey); 3873 rseg->reserved = 0; 3874 } 3875 3876 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 3877 void **seg, int *size, void **cur_edge) 3878 { 3879 struct mlx5_wqe_eth_seg *eseg = *seg; 3880 3881 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3882 3883 if (wr->send_flags & IB_SEND_IP_CSUM) 3884 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3885 MLX5_ETH_WQE_L4_CSUM; 3886 3887 if (wr->opcode == IB_WR_LSO) { 3888 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3889 size_t left, copysz; 3890 void *pdata = ud_wr->header; 3891 size_t stride; 3892 3893 left = ud_wr->hlen; 3894 eseg->mss = cpu_to_be16(ud_wr->mss); 3895 eseg->inline_hdr.sz = cpu_to_be16(left); 3896 3897 /* memcpy_send_wqe should get a 16B align address. Hence, we 3898 * first copy up to the current edge and then, if needed, 3899 * fall-through to memcpy_send_wqe. 3900 */ 3901 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, 3902 left); 3903 memcpy(eseg->inline_hdr.start, pdata, copysz); 3904 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - 3905 sizeof(eseg->inline_hdr.start) + copysz, 16); 3906 *size += stride / 16; 3907 *seg += stride; 3908 3909 if (copysz < left) { 3910 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 3911 left -= copysz; 3912 pdata += copysz; 3913 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, 3914 left); 3915 } 3916 3917 return; 3918 } 3919 3920 *seg += sizeof(struct mlx5_wqe_eth_seg); 3921 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3922 } 3923 3924 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3925 const struct ib_send_wr *wr) 3926 { 3927 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3928 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3929 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3930 } 3931 3932 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3933 { 3934 dseg->byte_count = cpu_to_be32(sg->length); 3935 dseg->lkey = cpu_to_be32(sg->lkey); 3936 dseg->addr = cpu_to_be64(sg->addr); 3937 } 3938 3939 static u64 get_xlt_octo(u64 bytes) 3940 { 3941 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3942 MLX5_IB_UMR_OCTOWORD; 3943 } 3944 3945 static __be64 frwr_mkey_mask(void) 3946 { 3947 u64 result; 3948 3949 result = MLX5_MKEY_MASK_LEN | 3950 MLX5_MKEY_MASK_PAGE_SIZE | 3951 MLX5_MKEY_MASK_START_ADDR | 3952 MLX5_MKEY_MASK_EN_RINVAL | 3953 MLX5_MKEY_MASK_KEY | 3954 MLX5_MKEY_MASK_LR | 3955 MLX5_MKEY_MASK_LW | 3956 MLX5_MKEY_MASK_RR | 3957 MLX5_MKEY_MASK_RW | 3958 MLX5_MKEY_MASK_A | 3959 MLX5_MKEY_MASK_SMALL_FENCE | 3960 MLX5_MKEY_MASK_FREE; 3961 3962 return cpu_to_be64(result); 3963 } 3964 3965 static __be64 sig_mkey_mask(void) 3966 { 3967 u64 result; 3968 3969 result = MLX5_MKEY_MASK_LEN | 3970 MLX5_MKEY_MASK_PAGE_SIZE | 3971 MLX5_MKEY_MASK_START_ADDR | 3972 MLX5_MKEY_MASK_EN_SIGERR | 3973 MLX5_MKEY_MASK_EN_RINVAL | 3974 MLX5_MKEY_MASK_KEY | 3975 MLX5_MKEY_MASK_LR | 3976 MLX5_MKEY_MASK_LW | 3977 MLX5_MKEY_MASK_RR | 3978 MLX5_MKEY_MASK_RW | 3979 MLX5_MKEY_MASK_SMALL_FENCE | 3980 MLX5_MKEY_MASK_FREE | 3981 MLX5_MKEY_MASK_BSF_EN; 3982 3983 return cpu_to_be64(result); 3984 } 3985 3986 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3987 struct mlx5_ib_mr *mr, bool umr_inline) 3988 { 3989 int size = mr->ndescs * mr->desc_size; 3990 3991 memset(umr, 0, sizeof(*umr)); 3992 3993 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3994 if (umr_inline) 3995 umr->flags |= MLX5_UMR_INLINE; 3996 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3997 umr->mkey_mask = frwr_mkey_mask(); 3998 } 3999 4000 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 4001 { 4002 memset(umr, 0, sizeof(*umr)); 4003 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 4004 umr->flags = MLX5_UMR_INLINE; 4005 } 4006 4007 static __be64 get_umr_enable_mr_mask(void) 4008 { 4009 u64 result; 4010 4011 result = MLX5_MKEY_MASK_KEY | 4012 MLX5_MKEY_MASK_FREE; 4013 4014 return cpu_to_be64(result); 4015 } 4016 4017 static __be64 get_umr_disable_mr_mask(void) 4018 { 4019 u64 result; 4020 4021 result = MLX5_MKEY_MASK_FREE; 4022 4023 return cpu_to_be64(result); 4024 } 4025 4026 static __be64 get_umr_update_translation_mask(void) 4027 { 4028 u64 result; 4029 4030 result = MLX5_MKEY_MASK_LEN | 4031 MLX5_MKEY_MASK_PAGE_SIZE | 4032 MLX5_MKEY_MASK_START_ADDR; 4033 4034 return cpu_to_be64(result); 4035 } 4036 4037 static __be64 get_umr_update_access_mask(int atomic) 4038 { 4039 u64 result; 4040 4041 result = MLX5_MKEY_MASK_LR | 4042 MLX5_MKEY_MASK_LW | 4043 MLX5_MKEY_MASK_RR | 4044 MLX5_MKEY_MASK_RW; 4045 4046 if (atomic) 4047 result |= MLX5_MKEY_MASK_A; 4048 4049 return cpu_to_be64(result); 4050 } 4051 4052 static __be64 get_umr_update_pd_mask(void) 4053 { 4054 u64 result; 4055 4056 result = MLX5_MKEY_MASK_PD; 4057 4058 return cpu_to_be64(result); 4059 } 4060 4061 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 4062 { 4063 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 4064 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 4065 (mask & MLX5_MKEY_MASK_A && 4066 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 4067 return -EPERM; 4068 return 0; 4069 } 4070 4071 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 4072 struct mlx5_wqe_umr_ctrl_seg *umr, 4073 const struct ib_send_wr *wr, int atomic) 4074 { 4075 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4076 4077 memset(umr, 0, sizeof(*umr)); 4078 4079 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 4080 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 4081 else 4082 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 4083 4084 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 4085 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 4086 u64 offset = get_xlt_octo(umrwr->offset); 4087 4088 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 4089 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 4090 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 4091 } 4092 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 4093 umr->mkey_mask |= get_umr_update_translation_mask(); 4094 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 4095 umr->mkey_mask |= get_umr_update_access_mask(atomic); 4096 umr->mkey_mask |= get_umr_update_pd_mask(); 4097 } 4098 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 4099 umr->mkey_mask |= get_umr_enable_mr_mask(); 4100 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4101 umr->mkey_mask |= get_umr_disable_mr_mask(); 4102 4103 if (!wr->num_sge) 4104 umr->flags |= MLX5_UMR_INLINE; 4105 4106 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 4107 } 4108 4109 static u8 get_umr_flags(int acc) 4110 { 4111 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 4112 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 4113 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 4114 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 4115 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 4116 } 4117 4118 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 4119 struct mlx5_ib_mr *mr, 4120 u32 key, int access) 4121 { 4122 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 4123 4124 memset(seg, 0, sizeof(*seg)); 4125 4126 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 4127 seg->log2_page_size = ilog2(mr->ibmr.page_size); 4128 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 4129 /* KLMs take twice the size of MTTs */ 4130 ndescs *= 2; 4131 4132 seg->flags = get_umr_flags(access) | mr->access_mode; 4133 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 4134 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 4135 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 4136 seg->len = cpu_to_be64(mr->ibmr.length); 4137 seg->xlt_oct_size = cpu_to_be32(ndescs); 4138 } 4139 4140 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 4141 { 4142 memset(seg, 0, sizeof(*seg)); 4143 seg->status = MLX5_MKEY_STATUS_FREE; 4144 } 4145 4146 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, 4147 const struct ib_send_wr *wr) 4148 { 4149 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4150 4151 memset(seg, 0, sizeof(*seg)); 4152 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4153 seg->status = MLX5_MKEY_STATUS_FREE; 4154 4155 seg->flags = convert_access(umrwr->access_flags); 4156 if (umrwr->pd) 4157 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 4158 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 4159 !umrwr->length) 4160 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 4161 4162 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 4163 seg->len = cpu_to_be64(umrwr->length); 4164 seg->log2_page_size = umrwr->page_shift; 4165 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 4166 mlx5_mkey_variant(umrwr->mkey)); 4167 } 4168 4169 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 4170 struct mlx5_ib_mr *mr, 4171 struct mlx5_ib_pd *pd) 4172 { 4173 int bcount = mr->desc_size * mr->ndescs; 4174 4175 dseg->addr = cpu_to_be64(mr->desc_map); 4176 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 4177 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 4178 } 4179 4180 static __be32 send_ieth(const struct ib_send_wr *wr) 4181 { 4182 switch (wr->opcode) { 4183 case IB_WR_SEND_WITH_IMM: 4184 case IB_WR_RDMA_WRITE_WITH_IMM: 4185 return wr->ex.imm_data; 4186 4187 case IB_WR_SEND_WITH_INV: 4188 return cpu_to_be32(wr->ex.invalidate_rkey); 4189 4190 default: 4191 return 0; 4192 } 4193 } 4194 4195 static u8 calc_sig(void *wqe, int size) 4196 { 4197 u8 *p = wqe; 4198 u8 res = 0; 4199 int i; 4200 4201 for (i = 0; i < size; i++) 4202 res ^= p[i]; 4203 4204 return ~res; 4205 } 4206 4207 static u8 wq_sig(void *wqe) 4208 { 4209 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 4210 } 4211 4212 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 4213 void **wqe, int *wqe_sz, void **cur_edge) 4214 { 4215 struct mlx5_wqe_inline_seg *seg; 4216 size_t offset; 4217 int inl = 0; 4218 int i; 4219 4220 seg = *wqe; 4221 *wqe += sizeof(*seg); 4222 offset = sizeof(*seg); 4223 4224 for (i = 0; i < wr->num_sge; i++) { 4225 size_t len = wr->sg_list[i].length; 4226 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); 4227 4228 inl += len; 4229 4230 if (unlikely(inl > qp->max_inline_data)) 4231 return -ENOMEM; 4232 4233 while (likely(len)) { 4234 size_t leftlen; 4235 size_t copysz; 4236 4237 handle_post_send_edge(&qp->sq, wqe, 4238 *wqe_sz + (offset >> 4), 4239 cur_edge); 4240 4241 leftlen = *cur_edge - *wqe; 4242 copysz = min_t(size_t, leftlen, len); 4243 4244 memcpy(*wqe, addr, copysz); 4245 len -= copysz; 4246 addr += copysz; 4247 *wqe += copysz; 4248 offset += copysz; 4249 } 4250 } 4251 4252 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 4253 4254 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 4255 4256 return 0; 4257 } 4258 4259 static u16 prot_field_size(enum ib_signature_type type) 4260 { 4261 switch (type) { 4262 case IB_SIG_TYPE_T10_DIF: 4263 return MLX5_DIF_SIZE; 4264 default: 4265 return 0; 4266 } 4267 } 4268 4269 static u8 bs_selector(int block_size) 4270 { 4271 switch (block_size) { 4272 case 512: return 0x1; 4273 case 520: return 0x2; 4274 case 4096: return 0x3; 4275 case 4160: return 0x4; 4276 case 1073741824: return 0x5; 4277 default: return 0; 4278 } 4279 } 4280 4281 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 4282 struct mlx5_bsf_inl *inl) 4283 { 4284 /* Valid inline section and allow BSF refresh */ 4285 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 4286 MLX5_BSF_REFRESH_DIF); 4287 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 4288 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 4289 /* repeating block */ 4290 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 4291 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 4292 MLX5_DIF_CRC : MLX5_DIF_IPCS; 4293 4294 if (domain->sig.dif.ref_remap) 4295 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 4296 4297 if (domain->sig.dif.app_escape) { 4298 if (domain->sig.dif.ref_escape) 4299 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 4300 else 4301 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 4302 } 4303 4304 inl->dif_app_bitmask_check = 4305 cpu_to_be16(domain->sig.dif.apptag_check_mask); 4306 } 4307 4308 static int mlx5_set_bsf(struct ib_mr *sig_mr, 4309 struct ib_sig_attrs *sig_attrs, 4310 struct mlx5_bsf *bsf, u32 data_size) 4311 { 4312 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 4313 struct mlx5_bsf_basic *basic = &bsf->basic; 4314 struct ib_sig_domain *mem = &sig_attrs->mem; 4315 struct ib_sig_domain *wire = &sig_attrs->wire; 4316 4317 memset(bsf, 0, sizeof(*bsf)); 4318 4319 /* Basic + Extended + Inline */ 4320 basic->bsf_size_sbs = 1 << 7; 4321 /* Input domain check byte mask */ 4322 basic->check_byte_mask = sig_attrs->check_mask; 4323 basic->raw_data_size = cpu_to_be32(data_size); 4324 4325 /* Memory domain */ 4326 switch (sig_attrs->mem.sig_type) { 4327 case IB_SIG_TYPE_NONE: 4328 break; 4329 case IB_SIG_TYPE_T10_DIF: 4330 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4331 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4332 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4333 break; 4334 default: 4335 return -EINVAL; 4336 } 4337 4338 /* Wire domain */ 4339 switch (sig_attrs->wire.sig_type) { 4340 case IB_SIG_TYPE_NONE: 4341 break; 4342 case IB_SIG_TYPE_T10_DIF: 4343 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4344 mem->sig_type == wire->sig_type) { 4345 /* Same block structure */ 4346 basic->bsf_size_sbs |= 1 << 4; 4347 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4348 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4349 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4350 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4351 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4352 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4353 } else 4354 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4355 4356 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4357 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4358 break; 4359 default: 4360 return -EINVAL; 4361 } 4362 4363 return 0; 4364 } 4365 4366 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 4367 struct mlx5_ib_qp *qp, void **seg, 4368 int *size, void **cur_edge) 4369 { 4370 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4371 struct ib_mr *sig_mr = wr->sig_mr; 4372 struct mlx5_bsf *bsf; 4373 u32 data_len = wr->wr.sg_list->length; 4374 u32 data_key = wr->wr.sg_list->lkey; 4375 u64 data_va = wr->wr.sg_list->addr; 4376 int ret; 4377 int wqe_size; 4378 4379 if (!wr->prot || 4380 (data_key == wr->prot->lkey && 4381 data_va == wr->prot->addr && 4382 data_len == wr->prot->length)) { 4383 /** 4384 * Source domain doesn't contain signature information 4385 * or data and protection are interleaved in memory. 4386 * So need construct: 4387 * ------------------ 4388 * | data_klm | 4389 * ------------------ 4390 * | BSF | 4391 * ------------------ 4392 **/ 4393 struct mlx5_klm *data_klm = *seg; 4394 4395 data_klm->bcount = cpu_to_be32(data_len); 4396 data_klm->key = cpu_to_be32(data_key); 4397 data_klm->va = cpu_to_be64(data_va); 4398 wqe_size = ALIGN(sizeof(*data_klm), 64); 4399 } else { 4400 /** 4401 * Source domain contains signature information 4402 * So need construct a strided block format: 4403 * --------------------------- 4404 * | stride_block_ctrl | 4405 * --------------------------- 4406 * | data_klm | 4407 * --------------------------- 4408 * | prot_klm | 4409 * --------------------------- 4410 * | BSF | 4411 * --------------------------- 4412 **/ 4413 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4414 struct mlx5_stride_block_entry *data_sentry; 4415 struct mlx5_stride_block_entry *prot_sentry; 4416 u32 prot_key = wr->prot->lkey; 4417 u64 prot_va = wr->prot->addr; 4418 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4419 int prot_size; 4420 4421 sblock_ctrl = *seg; 4422 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4423 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4424 4425 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4426 if (!prot_size) { 4427 pr_err("Bad block size given: %u\n", block_size); 4428 return -EINVAL; 4429 } 4430 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4431 prot_size); 4432 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4433 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4434 sblock_ctrl->num_entries = cpu_to_be16(2); 4435 4436 data_sentry->bcount = cpu_to_be16(block_size); 4437 data_sentry->key = cpu_to_be32(data_key); 4438 data_sentry->va = cpu_to_be64(data_va); 4439 data_sentry->stride = cpu_to_be16(block_size); 4440 4441 prot_sentry->bcount = cpu_to_be16(prot_size); 4442 prot_sentry->key = cpu_to_be32(prot_key); 4443 prot_sentry->va = cpu_to_be64(prot_va); 4444 prot_sentry->stride = cpu_to_be16(prot_size); 4445 4446 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4447 sizeof(*prot_sentry), 64); 4448 } 4449 4450 *seg += wqe_size; 4451 *size += wqe_size / 16; 4452 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4453 4454 bsf = *seg; 4455 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4456 if (ret) 4457 return -EINVAL; 4458 4459 *seg += sizeof(*bsf); 4460 *size += sizeof(*bsf) / 16; 4461 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4462 4463 return 0; 4464 } 4465 4466 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4467 const struct ib_sig_handover_wr *wr, u32 size, 4468 u32 length, u32 pdn) 4469 { 4470 struct ib_mr *sig_mr = wr->sig_mr; 4471 u32 sig_key = sig_mr->rkey; 4472 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4473 4474 memset(seg, 0, sizeof(*seg)); 4475 4476 seg->flags = get_umr_flags(wr->access_flags) | 4477 MLX5_MKC_ACCESS_MODE_KLMS; 4478 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4479 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4480 MLX5_MKEY_BSF_EN | pdn); 4481 seg->len = cpu_to_be64(length); 4482 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4483 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4484 } 4485 4486 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4487 u32 size) 4488 { 4489 memset(umr, 0, sizeof(*umr)); 4490 4491 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4492 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4493 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4494 umr->mkey_mask = sig_mkey_mask(); 4495 } 4496 4497 4498 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, 4499 struct mlx5_ib_qp *qp, void **seg, int *size, 4500 void **cur_edge) 4501 { 4502 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4503 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4504 u32 pdn = get_pd(qp)->pdn; 4505 u32 xlt_size; 4506 int region_len, ret; 4507 4508 if (unlikely(wr->wr.num_sge != 1) || 4509 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4510 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4511 unlikely(!sig_mr->sig->sig_status_checked)) 4512 return -EINVAL; 4513 4514 /* length of the protected region, data + protection */ 4515 region_len = wr->wr.sg_list->length; 4516 if (wr->prot && 4517 (wr->prot->lkey != wr->wr.sg_list->lkey || 4518 wr->prot->addr != wr->wr.sg_list->addr || 4519 wr->prot->length != wr->wr.sg_list->length)) 4520 region_len += wr->prot->length; 4521 4522 /** 4523 * KLM octoword size - if protection was provided 4524 * then we use strided block format (3 octowords), 4525 * else we use single KLM (1 octoword) 4526 **/ 4527 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4528 4529 set_sig_umr_segment(*seg, xlt_size); 4530 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4531 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4532 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4533 4534 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4535 *seg += sizeof(struct mlx5_mkey_seg); 4536 *size += sizeof(struct mlx5_mkey_seg) / 16; 4537 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4538 4539 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge); 4540 if (ret) 4541 return ret; 4542 4543 sig_mr->sig->sig_status_checked = false; 4544 return 0; 4545 } 4546 4547 static int set_psv_wr(struct ib_sig_domain *domain, 4548 u32 psv_idx, void **seg, int *size) 4549 { 4550 struct mlx5_seg_set_psv *psv_seg = *seg; 4551 4552 memset(psv_seg, 0, sizeof(*psv_seg)); 4553 psv_seg->psv_num = cpu_to_be32(psv_idx); 4554 switch (domain->sig_type) { 4555 case IB_SIG_TYPE_NONE: 4556 break; 4557 case IB_SIG_TYPE_T10_DIF: 4558 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4559 domain->sig.dif.app_tag); 4560 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4561 break; 4562 default: 4563 pr_err("Bad signature type (%d) is given.\n", 4564 domain->sig_type); 4565 return -EINVAL; 4566 } 4567 4568 *seg += sizeof(*psv_seg); 4569 *size += sizeof(*psv_seg) / 16; 4570 4571 return 0; 4572 } 4573 4574 static int set_reg_wr(struct mlx5_ib_qp *qp, 4575 const struct ib_reg_wr *wr, 4576 void **seg, int *size, void **cur_edge) 4577 { 4578 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4579 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4580 size_t mr_list_size = mr->ndescs * mr->desc_size; 4581 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4582 4583 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4584 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4585 "Invalid IB_SEND_INLINE send flag\n"); 4586 return -EINVAL; 4587 } 4588 4589 set_reg_umr_seg(*seg, mr, umr_inline); 4590 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4591 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4592 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4593 4594 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4595 *seg += sizeof(struct mlx5_mkey_seg); 4596 *size += sizeof(struct mlx5_mkey_seg) / 16; 4597 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4598 4599 if (umr_inline) { 4600 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, 4601 mr_list_size); 4602 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); 4603 } else { 4604 set_reg_data_seg(*seg, mr, pd); 4605 *seg += sizeof(struct mlx5_wqe_data_seg); 4606 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4607 } 4608 return 0; 4609 } 4610 4611 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, 4612 void **cur_edge) 4613 { 4614 set_linv_umr_seg(*seg); 4615 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4616 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4617 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4618 set_linv_mkey_seg(*seg); 4619 *seg += sizeof(struct mlx5_mkey_seg); 4620 *size += sizeof(struct mlx5_mkey_seg) / 16; 4621 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4622 } 4623 4624 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) 4625 { 4626 __be32 *p = NULL; 4627 u32 tidx = idx; 4628 int i, j; 4629 4630 pr_debug("dump WQE index %u:\n", idx); 4631 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4632 if ((i & 0xf) == 0) { 4633 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4634 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx); 4635 pr_debug("WQBB at %p:\n", (void *)p); 4636 j = 0; 4637 } 4638 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4639 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4640 be32_to_cpu(p[j + 3])); 4641 } 4642 } 4643 4644 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4645 struct mlx5_wqe_ctrl_seg **ctrl, 4646 const struct ib_send_wr *wr, unsigned int *idx, 4647 int *size, void **cur_edge, int nreq, 4648 bool send_signaled, bool solicited) 4649 { 4650 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4651 return -ENOMEM; 4652 4653 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4654 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); 4655 *ctrl = *seg; 4656 *(uint32_t *)(*seg + 8) = 0; 4657 (*ctrl)->imm = send_ieth(wr); 4658 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4659 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4660 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 4661 4662 *seg += sizeof(**ctrl); 4663 *size = sizeof(**ctrl) / 16; 4664 *cur_edge = qp->sq.cur_edge; 4665 4666 return 0; 4667 } 4668 4669 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4670 struct mlx5_wqe_ctrl_seg **ctrl, 4671 const struct ib_send_wr *wr, unsigned *idx, 4672 int *size, void **cur_edge, int nreq) 4673 { 4674 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, 4675 wr->send_flags & IB_SEND_SIGNALED, 4676 wr->send_flags & IB_SEND_SOLICITED); 4677 } 4678 4679 static void finish_wqe(struct mlx5_ib_qp *qp, 4680 struct mlx5_wqe_ctrl_seg *ctrl, 4681 void *seg, u8 size, void *cur_edge, 4682 unsigned int idx, u64 wr_id, int nreq, u8 fence, 4683 u32 mlx5_opcode) 4684 { 4685 u8 opmod = 0; 4686 4687 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4688 mlx5_opcode | ((u32)opmod << 24)); 4689 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4690 ctrl->fm_ce_se |= fence; 4691 if (unlikely(qp->wq_sig)) 4692 ctrl->signature = wq_sig(ctrl); 4693 4694 qp->sq.wrid[idx] = wr_id; 4695 qp->sq.w_list[idx].opcode = mlx5_opcode; 4696 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4697 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4698 qp->sq.w_list[idx].next = qp->sq.cur_post; 4699 4700 /* We save the edge which was possibly updated during the WQE 4701 * construction, into SQ's cache. 4702 */ 4703 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); 4704 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? 4705 get_sq_edge(&qp->sq, qp->sq.cur_post & 4706 (qp->sq.wqe_cnt - 1)) : 4707 cur_edge; 4708 } 4709 4710 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 4711 const struct ib_send_wr **bad_wr, bool drain) 4712 { 4713 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4714 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4715 struct mlx5_core_dev *mdev = dev->mdev; 4716 struct mlx5_ib_qp *qp; 4717 struct mlx5_ib_mr *mr; 4718 struct mlx5_wqe_xrc_seg *xrc; 4719 struct mlx5_bf *bf; 4720 void *cur_edge; 4721 int uninitialized_var(size); 4722 unsigned long flags; 4723 unsigned idx; 4724 int err = 0; 4725 int num_sge; 4726 void *seg; 4727 int nreq; 4728 int i; 4729 u8 next_fence = 0; 4730 u8 fence; 4731 4732 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 4733 !drain)) { 4734 *bad_wr = wr; 4735 return -EIO; 4736 } 4737 4738 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4739 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4740 4741 qp = to_mqp(ibqp); 4742 bf = &qp->bf; 4743 4744 spin_lock_irqsave(&qp->sq.lock, flags); 4745 4746 for (nreq = 0; wr; nreq++, wr = wr->next) { 4747 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4748 mlx5_ib_warn(dev, "\n"); 4749 err = -EINVAL; 4750 *bad_wr = wr; 4751 goto out; 4752 } 4753 4754 num_sge = wr->num_sge; 4755 if (unlikely(num_sge > qp->sq.max_gs)) { 4756 mlx5_ib_warn(dev, "\n"); 4757 err = -EINVAL; 4758 *bad_wr = wr; 4759 goto out; 4760 } 4761 4762 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, 4763 nreq); 4764 if (err) { 4765 mlx5_ib_warn(dev, "\n"); 4766 err = -ENOMEM; 4767 *bad_wr = wr; 4768 goto out; 4769 } 4770 4771 if (wr->opcode == IB_WR_REG_MR) { 4772 fence = dev->umr_fence; 4773 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4774 } else { 4775 if (wr->send_flags & IB_SEND_FENCE) { 4776 if (qp->next_fence) 4777 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4778 else 4779 fence = MLX5_FENCE_MODE_FENCE; 4780 } else { 4781 fence = qp->next_fence; 4782 } 4783 } 4784 4785 switch (ibqp->qp_type) { 4786 case IB_QPT_XRC_INI: 4787 xrc = seg; 4788 seg += sizeof(*xrc); 4789 size += sizeof(*xrc) / 16; 4790 /* fall through */ 4791 case IB_QPT_RC: 4792 switch (wr->opcode) { 4793 case IB_WR_RDMA_READ: 4794 case IB_WR_RDMA_WRITE: 4795 case IB_WR_RDMA_WRITE_WITH_IMM: 4796 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4797 rdma_wr(wr)->rkey); 4798 seg += sizeof(struct mlx5_wqe_raddr_seg); 4799 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4800 break; 4801 4802 case IB_WR_ATOMIC_CMP_AND_SWP: 4803 case IB_WR_ATOMIC_FETCH_AND_ADD: 4804 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4805 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4806 err = -ENOSYS; 4807 *bad_wr = wr; 4808 goto out; 4809 4810 case IB_WR_LOCAL_INV: 4811 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4812 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4813 set_linv_wr(qp, &seg, &size, &cur_edge); 4814 num_sge = 0; 4815 break; 4816 4817 case IB_WR_REG_MR: 4818 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4819 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4820 err = set_reg_wr(qp, reg_wr(wr), &seg, &size, 4821 &cur_edge); 4822 if (err) { 4823 *bad_wr = wr; 4824 goto out; 4825 } 4826 num_sge = 0; 4827 break; 4828 4829 case IB_WR_REG_SIG_MR: 4830 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4831 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4832 4833 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4834 err = set_sig_umr_wr(wr, qp, &seg, &size, 4835 &cur_edge); 4836 if (err) { 4837 mlx5_ib_warn(dev, "\n"); 4838 *bad_wr = wr; 4839 goto out; 4840 } 4841 4842 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4843 wr->wr_id, nreq, fence, 4844 MLX5_OPCODE_UMR); 4845 /* 4846 * SET_PSV WQEs are not signaled and solicited 4847 * on error 4848 */ 4849 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4850 &size, &cur_edge, nreq, false, 4851 true); 4852 if (err) { 4853 mlx5_ib_warn(dev, "\n"); 4854 err = -ENOMEM; 4855 *bad_wr = wr; 4856 goto out; 4857 } 4858 4859 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4860 mr->sig->psv_memory.psv_idx, &seg, 4861 &size); 4862 if (err) { 4863 mlx5_ib_warn(dev, "\n"); 4864 *bad_wr = wr; 4865 goto out; 4866 } 4867 4868 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4869 wr->wr_id, nreq, fence, 4870 MLX5_OPCODE_SET_PSV); 4871 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4872 &size, &cur_edge, nreq, false, 4873 true); 4874 if (err) { 4875 mlx5_ib_warn(dev, "\n"); 4876 err = -ENOMEM; 4877 *bad_wr = wr; 4878 goto out; 4879 } 4880 4881 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4882 mr->sig->psv_wire.psv_idx, &seg, 4883 &size); 4884 if (err) { 4885 mlx5_ib_warn(dev, "\n"); 4886 *bad_wr = wr; 4887 goto out; 4888 } 4889 4890 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4891 wr->wr_id, nreq, fence, 4892 MLX5_OPCODE_SET_PSV); 4893 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4894 num_sge = 0; 4895 goto skip_psv; 4896 4897 default: 4898 break; 4899 } 4900 break; 4901 4902 case IB_QPT_UC: 4903 switch (wr->opcode) { 4904 case IB_WR_RDMA_WRITE: 4905 case IB_WR_RDMA_WRITE_WITH_IMM: 4906 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4907 rdma_wr(wr)->rkey); 4908 seg += sizeof(struct mlx5_wqe_raddr_seg); 4909 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4910 break; 4911 4912 default: 4913 break; 4914 } 4915 break; 4916 4917 case IB_QPT_SMI: 4918 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4919 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4920 err = -EPERM; 4921 *bad_wr = wr; 4922 goto out; 4923 } 4924 /* fall through */ 4925 case MLX5_IB_QPT_HW_GSI: 4926 set_datagram_seg(seg, wr); 4927 seg += sizeof(struct mlx5_wqe_datagram_seg); 4928 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4929 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4930 4931 break; 4932 case IB_QPT_UD: 4933 set_datagram_seg(seg, wr); 4934 seg += sizeof(struct mlx5_wqe_datagram_seg); 4935 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4936 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4937 4938 /* handle qp that supports ud offload */ 4939 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4940 struct mlx5_wqe_eth_pad *pad; 4941 4942 pad = seg; 4943 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4944 seg += sizeof(struct mlx5_wqe_eth_pad); 4945 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4946 set_eth_seg(wr, qp, &seg, &size, &cur_edge); 4947 handle_post_send_edge(&qp->sq, &seg, size, 4948 &cur_edge); 4949 } 4950 break; 4951 case MLX5_IB_QPT_REG_UMR: 4952 if (wr->opcode != MLX5_IB_WR_UMR) { 4953 err = -EINVAL; 4954 mlx5_ib_warn(dev, "bad opcode\n"); 4955 goto out; 4956 } 4957 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4958 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4959 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4960 if (unlikely(err)) 4961 goto out; 4962 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4963 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4964 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4965 set_reg_mkey_segment(seg, wr); 4966 seg += sizeof(struct mlx5_mkey_seg); 4967 size += sizeof(struct mlx5_mkey_seg) / 16; 4968 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4969 break; 4970 4971 default: 4972 break; 4973 } 4974 4975 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4976 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); 4977 if (unlikely(err)) { 4978 mlx5_ib_warn(dev, "\n"); 4979 *bad_wr = wr; 4980 goto out; 4981 } 4982 } else { 4983 for (i = 0; i < num_sge; i++) { 4984 handle_post_send_edge(&qp->sq, &seg, size, 4985 &cur_edge); 4986 if (likely(wr->sg_list[i].length)) { 4987 set_data_ptr_seg 4988 ((struct mlx5_wqe_data_seg *)seg, 4989 wr->sg_list + i); 4990 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4991 seg += sizeof(struct mlx5_wqe_data_seg); 4992 } 4993 } 4994 } 4995 4996 qp->next_fence = next_fence; 4997 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, 4998 fence, mlx5_ib_opcode[wr->opcode]); 4999 skip_psv: 5000 if (0) 5001 dump_wqe(qp, idx, size); 5002 } 5003 5004 out: 5005 if (likely(nreq)) { 5006 qp->sq.head += nreq; 5007 5008 /* Make sure that descriptors are written before 5009 * updating doorbell record and ringing the doorbell 5010 */ 5011 wmb(); 5012 5013 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 5014 5015 /* Make sure doorbell record is visible to the HCA before 5016 * we hit doorbell */ 5017 wmb(); 5018 5019 /* currently we support only regular doorbells */ 5020 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 5021 /* Make sure doorbells don't leak out of SQ spinlock 5022 * and reach the HCA out of order. 5023 */ 5024 mmiowb(); 5025 bf->offset ^= bf->buf_size; 5026 } 5027 5028 spin_unlock_irqrestore(&qp->sq.lock, flags); 5029 5030 return err; 5031 } 5032 5033 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5034 const struct ib_send_wr **bad_wr) 5035 { 5036 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); 5037 } 5038 5039 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 5040 { 5041 sig->signature = calc_sig(sig, size); 5042 } 5043 5044 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5045 const struct ib_recv_wr **bad_wr, bool drain) 5046 { 5047 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5048 struct mlx5_wqe_data_seg *scat; 5049 struct mlx5_rwqe_sig *sig; 5050 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5051 struct mlx5_core_dev *mdev = dev->mdev; 5052 unsigned long flags; 5053 int err = 0; 5054 int nreq; 5055 int ind; 5056 int i; 5057 5058 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5059 !drain)) { 5060 *bad_wr = wr; 5061 return -EIO; 5062 } 5063 5064 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5065 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 5066 5067 spin_lock_irqsave(&qp->rq.lock, flags); 5068 5069 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 5070 5071 for (nreq = 0; wr; nreq++, wr = wr->next) { 5072 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 5073 err = -ENOMEM; 5074 *bad_wr = wr; 5075 goto out; 5076 } 5077 5078 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 5079 err = -EINVAL; 5080 *bad_wr = wr; 5081 goto out; 5082 } 5083 5084 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); 5085 if (qp->wq_sig) 5086 scat++; 5087 5088 for (i = 0; i < wr->num_sge; i++) 5089 set_data_ptr_seg(scat + i, wr->sg_list + i); 5090 5091 if (i < qp->rq.max_gs) { 5092 scat[i].byte_count = 0; 5093 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 5094 scat[i].addr = 0; 5095 } 5096 5097 if (qp->wq_sig) { 5098 sig = (struct mlx5_rwqe_sig *)scat; 5099 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 5100 } 5101 5102 qp->rq.wrid[ind] = wr->wr_id; 5103 5104 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 5105 } 5106 5107 out: 5108 if (likely(nreq)) { 5109 qp->rq.head += nreq; 5110 5111 /* Make sure that descriptors are written before 5112 * doorbell record. 5113 */ 5114 wmb(); 5115 5116 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 5117 } 5118 5119 spin_unlock_irqrestore(&qp->rq.lock, flags); 5120 5121 return err; 5122 } 5123 5124 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5125 const struct ib_recv_wr **bad_wr) 5126 { 5127 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); 5128 } 5129 5130 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 5131 { 5132 switch (mlx5_state) { 5133 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 5134 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 5135 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 5136 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 5137 case MLX5_QP_STATE_SQ_DRAINING: 5138 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 5139 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 5140 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 5141 default: return -1; 5142 } 5143 } 5144 5145 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 5146 { 5147 switch (mlx5_mig_state) { 5148 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 5149 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 5150 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 5151 default: return -1; 5152 } 5153 } 5154 5155 static int to_ib_qp_access_flags(int mlx5_flags) 5156 { 5157 int ib_flags = 0; 5158 5159 if (mlx5_flags & MLX5_QP_BIT_RRE) 5160 ib_flags |= IB_ACCESS_REMOTE_READ; 5161 if (mlx5_flags & MLX5_QP_BIT_RWE) 5162 ib_flags |= IB_ACCESS_REMOTE_WRITE; 5163 if (mlx5_flags & MLX5_QP_BIT_RAE) 5164 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 5165 5166 return ib_flags; 5167 } 5168 5169 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 5170 struct rdma_ah_attr *ah_attr, 5171 struct mlx5_qp_path *path) 5172 { 5173 5174 memset(ah_attr, 0, sizeof(*ah_attr)); 5175 5176 if (!path->port || path->port > ibdev->num_ports) 5177 return; 5178 5179 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 5180 5181 rdma_ah_set_port_num(ah_attr, path->port); 5182 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 5183 5184 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 5185 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 5186 rdma_ah_set_static_rate(ah_attr, 5187 path->static_rate ? path->static_rate - 5 : 0); 5188 if (path->grh_mlid & (1 << 7)) { 5189 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 5190 5191 rdma_ah_set_grh(ah_attr, NULL, 5192 tc_fl & 0xfffff, 5193 path->mgid_index, 5194 path->hop_limit, 5195 (tc_fl >> 20) & 0xff); 5196 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 5197 } 5198 } 5199 5200 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 5201 struct mlx5_ib_sq *sq, 5202 u8 *sq_state) 5203 { 5204 int err; 5205 5206 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 5207 if (err) 5208 goto out; 5209 sq->state = *sq_state; 5210 5211 out: 5212 return err; 5213 } 5214 5215 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 5216 struct mlx5_ib_rq *rq, 5217 u8 *rq_state) 5218 { 5219 void *out; 5220 void *rqc; 5221 int inlen; 5222 int err; 5223 5224 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 5225 out = kvzalloc(inlen, GFP_KERNEL); 5226 if (!out) 5227 return -ENOMEM; 5228 5229 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 5230 if (err) 5231 goto out; 5232 5233 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 5234 *rq_state = MLX5_GET(rqc, rqc, state); 5235 rq->state = *rq_state; 5236 5237 out: 5238 kvfree(out); 5239 return err; 5240 } 5241 5242 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 5243 struct mlx5_ib_qp *qp, u8 *qp_state) 5244 { 5245 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 5246 [MLX5_RQC_STATE_RST] = { 5247 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5248 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5249 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 5250 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 5251 }, 5252 [MLX5_RQC_STATE_RDY] = { 5253 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5254 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5255 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 5256 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 5257 }, 5258 [MLX5_RQC_STATE_ERR] = { 5259 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5260 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5261 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 5262 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 5263 }, 5264 [MLX5_RQ_STATE_NA] = { 5265 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5266 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5267 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 5268 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 5269 }, 5270 }; 5271 5272 *qp_state = sqrq_trans[rq_state][sq_state]; 5273 5274 if (*qp_state == MLX5_QP_STATE_BAD) { 5275 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 5276 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 5277 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 5278 return -EINVAL; 5279 } 5280 5281 if (*qp_state == MLX5_QP_STATE) 5282 *qp_state = qp->state; 5283 5284 return 0; 5285 } 5286 5287 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 5288 struct mlx5_ib_qp *qp, 5289 u8 *raw_packet_qp_state) 5290 { 5291 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 5292 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 5293 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 5294 int err; 5295 u8 sq_state = MLX5_SQ_STATE_NA; 5296 u8 rq_state = MLX5_RQ_STATE_NA; 5297 5298 if (qp->sq.wqe_cnt) { 5299 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 5300 if (err) 5301 return err; 5302 } 5303 5304 if (qp->rq.wqe_cnt) { 5305 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 5306 if (err) 5307 return err; 5308 } 5309 5310 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 5311 raw_packet_qp_state); 5312 } 5313 5314 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 5315 struct ib_qp_attr *qp_attr) 5316 { 5317 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 5318 struct mlx5_qp_context *context; 5319 int mlx5_state; 5320 u32 *outb; 5321 int err = 0; 5322 5323 outb = kzalloc(outlen, GFP_KERNEL); 5324 if (!outb) 5325 return -ENOMEM; 5326 5327 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 5328 outlen); 5329 if (err) 5330 goto out; 5331 5332 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 5333 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 5334 5335 mlx5_state = be32_to_cpu(context->flags) >> 28; 5336 5337 qp->state = to_ib_qp_state(mlx5_state); 5338 qp_attr->path_mtu = context->mtu_msgmax >> 5; 5339 qp_attr->path_mig_state = 5340 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 5341 qp_attr->qkey = be32_to_cpu(context->qkey); 5342 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 5343 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 5344 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 5345 qp_attr->qp_access_flags = 5346 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 5347 5348 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 5349 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 5350 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5351 qp_attr->alt_pkey_index = 5352 be16_to_cpu(context->alt_path.pkey_index); 5353 qp_attr->alt_port_num = 5354 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5355 } 5356 5357 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5358 qp_attr->port_num = context->pri_path.port; 5359 5360 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5361 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5362 5363 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5364 5365 qp_attr->max_dest_rd_atomic = 5366 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5367 qp_attr->min_rnr_timer = 5368 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5369 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5370 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5371 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5372 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5373 5374 out: 5375 kfree(outb); 5376 return err; 5377 } 5378 5379 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5380 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5381 struct ib_qp_init_attr *qp_init_attr) 5382 { 5383 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5384 u32 *out; 5385 u32 access_flags = 0; 5386 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5387 void *dctc; 5388 int err; 5389 int supported_mask = IB_QP_STATE | 5390 IB_QP_ACCESS_FLAGS | 5391 IB_QP_PORT | 5392 IB_QP_MIN_RNR_TIMER | 5393 IB_QP_AV | 5394 IB_QP_PATH_MTU | 5395 IB_QP_PKEY_INDEX; 5396 5397 if (qp_attr_mask & ~supported_mask) 5398 return -EINVAL; 5399 if (mqp->state != IB_QPS_RTR) 5400 return -EINVAL; 5401 5402 out = kzalloc(outlen, GFP_KERNEL); 5403 if (!out) 5404 return -ENOMEM; 5405 5406 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5407 if (err) 5408 goto out; 5409 5410 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5411 5412 if (qp_attr_mask & IB_QP_STATE) 5413 qp_attr->qp_state = IB_QPS_RTR; 5414 5415 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5416 if (MLX5_GET(dctc, dctc, rre)) 5417 access_flags |= IB_ACCESS_REMOTE_READ; 5418 if (MLX5_GET(dctc, dctc, rwe)) 5419 access_flags |= IB_ACCESS_REMOTE_WRITE; 5420 if (MLX5_GET(dctc, dctc, rae)) 5421 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5422 qp_attr->qp_access_flags = access_flags; 5423 } 5424 5425 if (qp_attr_mask & IB_QP_PORT) 5426 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5427 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5428 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5429 if (qp_attr_mask & IB_QP_AV) { 5430 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5431 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5432 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5433 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5434 } 5435 if (qp_attr_mask & IB_QP_PATH_MTU) 5436 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5437 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5438 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5439 out: 5440 kfree(out); 5441 return err; 5442 } 5443 5444 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5445 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5446 { 5447 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5448 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5449 int err = 0; 5450 u8 raw_packet_qp_state; 5451 5452 if (ibqp->rwq_ind_tbl) 5453 return -ENOSYS; 5454 5455 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5456 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5457 qp_init_attr); 5458 5459 /* Not all of output fields are applicable, make sure to zero them */ 5460 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5461 memset(qp_attr, 0, sizeof(*qp_attr)); 5462 5463 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5464 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5465 qp_attr_mask, qp_init_attr); 5466 5467 mutex_lock(&qp->mutex); 5468 5469 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5470 qp->flags & MLX5_IB_QP_UNDERLAY) { 5471 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5472 if (err) 5473 goto out; 5474 qp->state = raw_packet_qp_state; 5475 qp_attr->port_num = 1; 5476 } else { 5477 err = query_qp_attr(dev, qp, qp_attr); 5478 if (err) 5479 goto out; 5480 } 5481 5482 qp_attr->qp_state = qp->state; 5483 qp_attr->cur_qp_state = qp_attr->qp_state; 5484 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5485 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5486 5487 if (!ibqp->uobject) { 5488 qp_attr->cap.max_send_wr = qp->sq.max_post; 5489 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5490 qp_init_attr->qp_context = ibqp->qp_context; 5491 } else { 5492 qp_attr->cap.max_send_wr = 0; 5493 qp_attr->cap.max_send_sge = 0; 5494 } 5495 5496 qp_init_attr->qp_type = ibqp->qp_type; 5497 qp_init_attr->recv_cq = ibqp->recv_cq; 5498 qp_init_attr->send_cq = ibqp->send_cq; 5499 qp_init_attr->srq = ibqp->srq; 5500 qp_attr->cap.max_inline_data = qp->max_inline_data; 5501 5502 qp_init_attr->cap = qp_attr->cap; 5503 5504 qp_init_attr->create_flags = 0; 5505 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5506 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5507 5508 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5509 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5510 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5511 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5512 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5513 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5514 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5515 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5516 5517 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5518 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5519 5520 out: 5521 mutex_unlock(&qp->mutex); 5522 return err; 5523 } 5524 5525 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5526 struct ib_ucontext *context, 5527 struct ib_udata *udata) 5528 { 5529 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5530 struct mlx5_ib_xrcd *xrcd; 5531 int err; 5532 5533 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5534 return ERR_PTR(-ENOSYS); 5535 5536 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5537 if (!xrcd) 5538 return ERR_PTR(-ENOMEM); 5539 5540 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5541 if (err) { 5542 kfree(xrcd); 5543 return ERR_PTR(-ENOMEM); 5544 } 5545 5546 return &xrcd->ibxrcd; 5547 } 5548 5549 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5550 { 5551 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5552 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5553 int err; 5554 5555 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5556 if (err) 5557 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5558 5559 kfree(xrcd); 5560 return 0; 5561 } 5562 5563 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5564 { 5565 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5566 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5567 struct ib_event event; 5568 5569 if (rwq->ibwq.event_handler) { 5570 event.device = rwq->ibwq.device; 5571 event.element.wq = &rwq->ibwq; 5572 switch (type) { 5573 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5574 event.event = IB_EVENT_WQ_FATAL; 5575 break; 5576 default: 5577 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5578 return; 5579 } 5580 5581 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5582 } 5583 } 5584 5585 static int set_delay_drop(struct mlx5_ib_dev *dev) 5586 { 5587 int err = 0; 5588 5589 mutex_lock(&dev->delay_drop.lock); 5590 if (dev->delay_drop.activate) 5591 goto out; 5592 5593 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5594 if (err) 5595 goto out; 5596 5597 dev->delay_drop.activate = true; 5598 out: 5599 mutex_unlock(&dev->delay_drop.lock); 5600 5601 if (!err) 5602 atomic_inc(&dev->delay_drop.rqs_cnt); 5603 return err; 5604 } 5605 5606 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5607 struct ib_wq_init_attr *init_attr) 5608 { 5609 struct mlx5_ib_dev *dev; 5610 int has_net_offloads; 5611 __be64 *rq_pas0; 5612 void *in; 5613 void *rqc; 5614 void *wq; 5615 int inlen; 5616 int err; 5617 5618 dev = to_mdev(pd->device); 5619 5620 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5621 in = kvzalloc(inlen, GFP_KERNEL); 5622 if (!in) 5623 return -ENOMEM; 5624 5625 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5626 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5627 MLX5_SET(rqc, rqc, mem_rq_type, 5628 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5629 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5630 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5631 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5632 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5633 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5634 MLX5_SET(wq, wq, wq_type, 5635 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5636 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5637 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5638 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5639 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5640 err = -EOPNOTSUPP; 5641 goto out; 5642 } else { 5643 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5644 } 5645 } 5646 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5647 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5648 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5649 MLX5_SET(wq, wq, log_wqe_stride_size, 5650 rwq->single_stride_log_num_of_bytes - 5651 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5652 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5653 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5654 } 5655 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5656 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5657 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5658 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5659 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5660 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5661 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5662 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5663 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5664 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5665 err = -EOPNOTSUPP; 5666 goto out; 5667 } 5668 } else { 5669 MLX5_SET(rqc, rqc, vsd, 1); 5670 } 5671 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5672 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5673 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5674 err = -EOPNOTSUPP; 5675 goto out; 5676 } 5677 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5678 } 5679 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5680 if (!(dev->ib_dev.attrs.raw_packet_caps & 5681 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5682 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5683 err = -EOPNOTSUPP; 5684 goto out; 5685 } 5686 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5687 } 5688 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5689 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5690 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5691 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5692 err = set_delay_drop(dev); 5693 if (err) { 5694 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5695 err); 5696 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5697 } else { 5698 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5699 } 5700 } 5701 out: 5702 kvfree(in); 5703 return err; 5704 } 5705 5706 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5707 struct ib_wq_init_attr *wq_init_attr, 5708 struct mlx5_ib_create_wq *ucmd, 5709 struct mlx5_ib_rwq *rwq) 5710 { 5711 /* Sanity check RQ size before proceeding */ 5712 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5713 return -EINVAL; 5714 5715 if (!ucmd->rq_wqe_count) 5716 return -EINVAL; 5717 5718 rwq->wqe_count = ucmd->rq_wqe_count; 5719 rwq->wqe_shift = ucmd->rq_wqe_shift; 5720 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5721 return -EINVAL; 5722 5723 rwq->log_rq_stride = rwq->wqe_shift; 5724 rwq->log_rq_size = ilog2(rwq->wqe_count); 5725 return 0; 5726 } 5727 5728 static int prepare_user_rq(struct ib_pd *pd, 5729 struct ib_wq_init_attr *init_attr, 5730 struct ib_udata *udata, 5731 struct mlx5_ib_rwq *rwq) 5732 { 5733 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5734 struct mlx5_ib_create_wq ucmd = {}; 5735 int err; 5736 size_t required_cmd_sz; 5737 5738 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5739 + sizeof(ucmd.single_stride_log_num_of_bytes); 5740 if (udata->inlen < required_cmd_sz) { 5741 mlx5_ib_dbg(dev, "invalid inlen\n"); 5742 return -EINVAL; 5743 } 5744 5745 if (udata->inlen > sizeof(ucmd) && 5746 !ib_is_udata_cleared(udata, sizeof(ucmd), 5747 udata->inlen - sizeof(ucmd))) { 5748 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5749 return -EOPNOTSUPP; 5750 } 5751 5752 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5753 mlx5_ib_dbg(dev, "copy failed\n"); 5754 return -EFAULT; 5755 } 5756 5757 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5758 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5759 return -EOPNOTSUPP; 5760 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5761 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5762 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5763 return -EOPNOTSUPP; 5764 } 5765 if ((ucmd.single_stride_log_num_of_bytes < 5766 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5767 (ucmd.single_stride_log_num_of_bytes > 5768 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5769 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5770 ucmd.single_stride_log_num_of_bytes, 5771 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5772 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5773 return -EINVAL; 5774 } 5775 if ((ucmd.single_wqe_log_num_of_strides > 5776 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5777 (ucmd.single_wqe_log_num_of_strides < 5778 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5779 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5780 ucmd.single_wqe_log_num_of_strides, 5781 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5782 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5783 return -EINVAL; 5784 } 5785 rwq->single_stride_log_num_of_bytes = 5786 ucmd.single_stride_log_num_of_bytes; 5787 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5788 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5789 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5790 } 5791 5792 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5793 if (err) { 5794 mlx5_ib_dbg(dev, "err %d\n", err); 5795 return err; 5796 } 5797 5798 err = create_user_rq(dev, pd, rwq, &ucmd); 5799 if (err) { 5800 mlx5_ib_dbg(dev, "err %d\n", err); 5801 return err; 5802 } 5803 5804 rwq->user_index = ucmd.user_index; 5805 return 0; 5806 } 5807 5808 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5809 struct ib_wq_init_attr *init_attr, 5810 struct ib_udata *udata) 5811 { 5812 struct mlx5_ib_dev *dev; 5813 struct mlx5_ib_rwq *rwq; 5814 struct mlx5_ib_create_wq_resp resp = {}; 5815 size_t min_resp_len; 5816 int err; 5817 5818 if (!udata) 5819 return ERR_PTR(-ENOSYS); 5820 5821 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5822 if (udata->outlen && udata->outlen < min_resp_len) 5823 return ERR_PTR(-EINVAL); 5824 5825 dev = to_mdev(pd->device); 5826 switch (init_attr->wq_type) { 5827 case IB_WQT_RQ: 5828 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5829 if (!rwq) 5830 return ERR_PTR(-ENOMEM); 5831 err = prepare_user_rq(pd, init_attr, udata, rwq); 5832 if (err) 5833 goto err; 5834 err = create_rq(rwq, pd, init_attr); 5835 if (err) 5836 goto err_user_rq; 5837 break; 5838 default: 5839 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5840 init_attr->wq_type); 5841 return ERR_PTR(-EINVAL); 5842 } 5843 5844 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5845 rwq->ibwq.state = IB_WQS_RESET; 5846 if (udata->outlen) { 5847 resp.response_length = offsetof(typeof(resp), response_length) + 5848 sizeof(resp.response_length); 5849 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5850 if (err) 5851 goto err_copy; 5852 } 5853 5854 rwq->core_qp.event = mlx5_ib_wq_event; 5855 rwq->ibwq.event_handler = init_attr->event_handler; 5856 return &rwq->ibwq; 5857 5858 err_copy: 5859 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5860 err_user_rq: 5861 destroy_user_rq(dev, pd, rwq); 5862 err: 5863 kfree(rwq); 5864 return ERR_PTR(err); 5865 } 5866 5867 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5868 { 5869 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5870 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5871 5872 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5873 destroy_user_rq(dev, wq->pd, rwq); 5874 kfree(rwq); 5875 5876 return 0; 5877 } 5878 5879 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5880 struct ib_rwq_ind_table_init_attr *init_attr, 5881 struct ib_udata *udata) 5882 { 5883 struct mlx5_ib_dev *dev = to_mdev(device); 5884 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5885 int sz = 1 << init_attr->log_ind_tbl_size; 5886 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5887 size_t min_resp_len; 5888 int inlen; 5889 int err; 5890 int i; 5891 u32 *in; 5892 void *rqtc; 5893 5894 if (udata->inlen > 0 && 5895 !ib_is_udata_cleared(udata, 0, 5896 udata->inlen)) 5897 return ERR_PTR(-EOPNOTSUPP); 5898 5899 if (init_attr->log_ind_tbl_size > 5900 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5901 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5902 init_attr->log_ind_tbl_size, 5903 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5904 return ERR_PTR(-EINVAL); 5905 } 5906 5907 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5908 if (udata->outlen && udata->outlen < min_resp_len) 5909 return ERR_PTR(-EINVAL); 5910 5911 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5912 if (!rwq_ind_tbl) 5913 return ERR_PTR(-ENOMEM); 5914 5915 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5916 in = kvzalloc(inlen, GFP_KERNEL); 5917 if (!in) { 5918 err = -ENOMEM; 5919 goto err; 5920 } 5921 5922 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5923 5924 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5925 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5926 5927 for (i = 0; i < sz; i++) 5928 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5929 5930 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5931 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5932 5933 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5934 kvfree(in); 5935 5936 if (err) 5937 goto err; 5938 5939 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5940 if (udata->outlen) { 5941 resp.response_length = offsetof(typeof(resp), response_length) + 5942 sizeof(resp.response_length); 5943 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5944 if (err) 5945 goto err_copy; 5946 } 5947 5948 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5949 5950 err_copy: 5951 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5952 err: 5953 kfree(rwq_ind_tbl); 5954 return ERR_PTR(err); 5955 } 5956 5957 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5958 { 5959 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5960 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5961 5962 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5963 5964 kfree(rwq_ind_tbl); 5965 return 0; 5966 } 5967 5968 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5969 u32 wq_attr_mask, struct ib_udata *udata) 5970 { 5971 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5972 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5973 struct mlx5_ib_modify_wq ucmd = {}; 5974 size_t required_cmd_sz; 5975 int curr_wq_state; 5976 int wq_state; 5977 int inlen; 5978 int err; 5979 void *rqc; 5980 void *in; 5981 5982 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5983 if (udata->inlen < required_cmd_sz) 5984 return -EINVAL; 5985 5986 if (udata->inlen > sizeof(ucmd) && 5987 !ib_is_udata_cleared(udata, sizeof(ucmd), 5988 udata->inlen - sizeof(ucmd))) 5989 return -EOPNOTSUPP; 5990 5991 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5992 return -EFAULT; 5993 5994 if (ucmd.comp_mask || ucmd.reserved) 5995 return -EOPNOTSUPP; 5996 5997 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5998 in = kvzalloc(inlen, GFP_KERNEL); 5999 if (!in) 6000 return -ENOMEM; 6001 6002 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 6003 6004 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 6005 wq_attr->curr_wq_state : wq->state; 6006 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 6007 wq_attr->wq_state : curr_wq_state; 6008 if (curr_wq_state == IB_WQS_ERR) 6009 curr_wq_state = MLX5_RQC_STATE_ERR; 6010 if (wq_state == IB_WQS_ERR) 6011 wq_state = MLX5_RQC_STATE_ERR; 6012 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 6013 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 6014 MLX5_SET(rqc, rqc, state, wq_state); 6015 6016 if (wq_attr_mask & IB_WQ_FLAGS) { 6017 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6018 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 6019 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6020 mlx5_ib_dbg(dev, "VLAN offloads are not " 6021 "supported\n"); 6022 err = -EOPNOTSUPP; 6023 goto out; 6024 } 6025 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6026 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 6027 MLX5_SET(rqc, rqc, vsd, 6028 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 6029 } 6030 6031 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6032 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 6033 err = -EOPNOTSUPP; 6034 goto out; 6035 } 6036 } 6037 6038 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 6039 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 6040 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6041 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 6042 MLX5_SET(rqc, rqc, counter_set_id, 6043 dev->port->cnts.set_id); 6044 } else 6045 dev_info_once( 6046 &dev->ib_dev.dev, 6047 "Receive WQ counters are not supported on current FW\n"); 6048 } 6049 6050 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 6051 if (!err) 6052 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 6053 6054 out: 6055 kvfree(in); 6056 return err; 6057 } 6058 6059 struct mlx5_ib_drain_cqe { 6060 struct ib_cqe cqe; 6061 struct completion done; 6062 }; 6063 6064 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 6065 { 6066 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 6067 struct mlx5_ib_drain_cqe, 6068 cqe); 6069 6070 complete(&cqe->done); 6071 } 6072 6073 /* This function returns only once the drained WR was completed */ 6074 static void handle_drain_completion(struct ib_cq *cq, 6075 struct mlx5_ib_drain_cqe *sdrain, 6076 struct mlx5_ib_dev *dev) 6077 { 6078 struct mlx5_core_dev *mdev = dev->mdev; 6079 6080 if (cq->poll_ctx == IB_POLL_DIRECT) { 6081 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 6082 ib_process_cq_direct(cq, -1); 6083 return; 6084 } 6085 6086 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6087 struct mlx5_ib_cq *mcq = to_mcq(cq); 6088 bool triggered = false; 6089 unsigned long flags; 6090 6091 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 6092 /* Make sure that the CQ handler won't run if wasn't run yet */ 6093 if (!mcq->mcq.reset_notify_added) 6094 mcq->mcq.reset_notify_added = 1; 6095 else 6096 triggered = true; 6097 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 6098 6099 if (triggered) { 6100 /* Wait for any scheduled/running task to be ended */ 6101 switch (cq->poll_ctx) { 6102 case IB_POLL_SOFTIRQ: 6103 irq_poll_disable(&cq->iop); 6104 irq_poll_enable(&cq->iop); 6105 break; 6106 case IB_POLL_WORKQUEUE: 6107 cancel_work_sync(&cq->work); 6108 break; 6109 default: 6110 WARN_ON_ONCE(1); 6111 } 6112 } 6113 6114 /* Run the CQ handler - this makes sure that the drain WR will 6115 * be processed if wasn't processed yet. 6116 */ 6117 mcq->mcq.comp(&mcq->mcq); 6118 } 6119 6120 wait_for_completion(&sdrain->done); 6121 } 6122 6123 void mlx5_ib_drain_sq(struct ib_qp *qp) 6124 { 6125 struct ib_cq *cq = qp->send_cq; 6126 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6127 struct mlx5_ib_drain_cqe sdrain; 6128 const struct ib_send_wr *bad_swr; 6129 struct ib_rdma_wr swr = { 6130 .wr = { 6131 .next = NULL, 6132 { .wr_cqe = &sdrain.cqe, }, 6133 .opcode = IB_WR_RDMA_WRITE, 6134 }, 6135 }; 6136 int ret; 6137 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6138 struct mlx5_core_dev *mdev = dev->mdev; 6139 6140 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6141 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6142 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6143 return; 6144 } 6145 6146 sdrain.cqe.done = mlx5_ib_drain_qp_done; 6147 init_completion(&sdrain.done); 6148 6149 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); 6150 if (ret) { 6151 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6152 return; 6153 } 6154 6155 handle_drain_completion(cq, &sdrain, dev); 6156 } 6157 6158 void mlx5_ib_drain_rq(struct ib_qp *qp) 6159 { 6160 struct ib_cq *cq = qp->recv_cq; 6161 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6162 struct mlx5_ib_drain_cqe rdrain; 6163 struct ib_recv_wr rwr = {}; 6164 const struct ib_recv_wr *bad_rwr; 6165 int ret; 6166 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6167 struct mlx5_core_dev *mdev = dev->mdev; 6168 6169 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6170 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6171 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6172 return; 6173 } 6174 6175 rwr.wr_cqe = &rdrain.cqe; 6176 rdrain.cqe.done = mlx5_ib_drain_qp_done; 6177 init_completion(&rdrain.done); 6178 6179 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); 6180 if (ret) { 6181 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6182 return; 6183 } 6184 6185 handle_drain_completion(cq, &rdrain, dev); 6186 } 6187