1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/etherdevice.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "umr.h" 44 #include "qp.h" 45 #include "wr.h" 46 47 enum { 48 MLX5_IB_ACK_REQ_FREQ = 8, 49 }; 50 51 enum { 52 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 53 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 54 MLX5_IB_LINK_TYPE_IB = 0, 55 MLX5_IB_LINK_TYPE_ETH = 1 56 }; 57 58 enum raw_qp_set_mask_map { 59 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 60 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 61 }; 62 63 enum { 64 MLX5_QP_RM_GO_BACK_N = 0x1, 65 }; 66 67 struct mlx5_modify_raw_qp_param { 68 u16 operation; 69 70 u32 set_mask; /* raw_qp_set_mask_map */ 71 72 struct mlx5_rate_limit rl; 73 74 u8 rq_q_ctr_id; 75 u32 port; 76 }; 77 78 struct mlx5_ib_qp_event_work { 79 struct work_struct work; 80 struct mlx5_core_qp *qp; 81 int type; 82 }; 83 84 static struct workqueue_struct *mlx5_ib_qp_event_wq; 85 86 static void get_cqs(enum ib_qp_type qp_type, 87 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 88 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 89 90 static int is_qp0(enum ib_qp_type qp_type) 91 { 92 return qp_type == IB_QPT_SMI; 93 } 94 95 static int is_sqp(enum ib_qp_type qp_type) 96 { 97 return is_qp0(qp_type) || is_qp1(qp_type); 98 } 99 100 /** 101 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 102 * to kernel buffer 103 * 104 * @umem: User space memory where the WQ is 105 * @buffer: buffer to copy to 106 * @buflen: buffer length 107 * @wqe_index: index of WQE to copy from 108 * @wq_offset: offset to start of WQ 109 * @wq_wqe_cnt: number of WQEs in WQ 110 * @wq_wqe_shift: log2 of WQE size 111 * @bcnt: number of bytes to copy 112 * @bytes_copied: number of bytes to copy (return value) 113 * 114 * Copies from start of WQE bcnt or less bytes. 115 * Does not gurantee to copy the entire WQE. 116 * 117 * Return: zero on success, or an error code. 118 */ 119 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 120 size_t buflen, int wqe_index, 121 int wq_offset, int wq_wqe_cnt, 122 int wq_wqe_shift, int bcnt, 123 size_t *bytes_copied) 124 { 125 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 126 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 127 size_t copy_length; 128 int ret; 129 130 /* don't copy more than requested, more than buffer length or 131 * beyond WQ end 132 */ 133 copy_length = min_t(u32, buflen, wq_end - offset); 134 copy_length = min_t(u32, copy_length, bcnt); 135 136 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 137 if (ret) 138 return ret; 139 140 if (!ret && bytes_copied) 141 *bytes_copied = copy_length; 142 143 return 0; 144 } 145 146 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 147 void *buffer, size_t buflen, size_t *bc) 148 { 149 struct mlx5_wqe_ctrl_seg *ctrl; 150 size_t bytes_copied = 0; 151 size_t wqe_length; 152 void *p; 153 int ds; 154 155 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 156 157 /* read the control segment first */ 158 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 159 ctrl = p; 160 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 161 wqe_length = ds * MLX5_WQE_DS_UNITS; 162 163 /* read rest of WQE if it spreads over more than one stride */ 164 while (bytes_copied < wqe_length) { 165 size_t copy_length = 166 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 167 168 if (!copy_length) 169 break; 170 171 memcpy(buffer + bytes_copied, p, copy_length); 172 bytes_copied += copy_length; 173 174 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 175 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 176 } 177 *bc = bytes_copied; 178 return 0; 179 } 180 181 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 182 void *buffer, size_t buflen, size_t *bc) 183 { 184 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 185 struct ib_umem *umem = base->ubuffer.umem; 186 struct mlx5_ib_wq *wq = &qp->sq; 187 struct mlx5_wqe_ctrl_seg *ctrl; 188 size_t bytes_copied; 189 size_t bytes_copied2; 190 size_t wqe_length; 191 int ret; 192 int ds; 193 194 /* at first read as much as possible */ 195 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 196 wq->offset, wq->wqe_cnt, 197 wq->wqe_shift, buflen, 198 &bytes_copied); 199 if (ret) 200 return ret; 201 202 /* we need at least control segment size to proceed */ 203 if (bytes_copied < sizeof(*ctrl)) 204 return -EINVAL; 205 206 ctrl = buffer; 207 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 208 wqe_length = ds * MLX5_WQE_DS_UNITS; 209 210 /* if we copied enough then we are done */ 211 if (bytes_copied >= wqe_length) { 212 *bc = bytes_copied; 213 return 0; 214 } 215 216 /* otherwise this a wrapped around wqe 217 * so read the remaining bytes starting 218 * from wqe_index 0 219 */ 220 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 221 buflen - bytes_copied, 0, wq->offset, 222 wq->wqe_cnt, wq->wqe_shift, 223 wqe_length - bytes_copied, 224 &bytes_copied2); 225 226 if (ret) 227 return ret; 228 *bc = bytes_copied + bytes_copied2; 229 return 0; 230 } 231 232 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 233 size_t buflen, size_t *bc) 234 { 235 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 236 struct ib_umem *umem = base->ubuffer.umem; 237 238 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 239 return -EINVAL; 240 241 if (!umem) 242 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 243 buflen, bc); 244 245 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 246 } 247 248 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 249 void *buffer, size_t buflen, size_t *bc) 250 { 251 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 252 struct ib_umem *umem = base->ubuffer.umem; 253 struct mlx5_ib_wq *wq = &qp->rq; 254 size_t bytes_copied; 255 int ret; 256 257 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 258 wq->offset, wq->wqe_cnt, 259 wq->wqe_shift, buflen, 260 &bytes_copied); 261 262 if (ret) 263 return ret; 264 *bc = bytes_copied; 265 return 0; 266 } 267 268 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 269 size_t buflen, size_t *bc) 270 { 271 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 272 struct ib_umem *umem = base->ubuffer.umem; 273 struct mlx5_ib_wq *wq = &qp->rq; 274 size_t wqe_size = 1 << wq->wqe_shift; 275 276 if (buflen < wqe_size) 277 return -EINVAL; 278 279 if (!umem) 280 return -EOPNOTSUPP; 281 282 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 283 } 284 285 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 286 void *buffer, size_t buflen, size_t *bc) 287 { 288 struct ib_umem *umem = srq->umem; 289 size_t bytes_copied; 290 int ret; 291 292 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 293 srq->msrq.max, srq->msrq.wqe_shift, 294 buflen, &bytes_copied); 295 296 if (ret) 297 return ret; 298 *bc = bytes_copied; 299 return 0; 300 } 301 302 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 303 size_t buflen, size_t *bc) 304 { 305 struct ib_umem *umem = srq->umem; 306 size_t wqe_size = 1 << srq->msrq.wqe_shift; 307 308 if (buflen < wqe_size) 309 return -EINVAL; 310 311 if (!umem) 312 return -EOPNOTSUPP; 313 314 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 315 } 316 317 static void mlx5_ib_qp_err_syndrome(struct ib_qp *ibqp) 318 { 319 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 320 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 321 struct mlx5_ib_qp *qp = to_mqp(ibqp); 322 void *pas_ext_union, *err_syn; 323 u32 *outb; 324 int err; 325 326 if (!MLX5_CAP_GEN(dev->mdev, qpc_extension) || 327 !MLX5_CAP_GEN(dev->mdev, qp_error_syndrome)) 328 return; 329 330 outb = kzalloc(outlen, GFP_KERNEL); 331 if (!outb) 332 return; 333 334 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 335 true); 336 if (err) 337 goto out; 338 339 pas_ext_union = 340 MLX5_ADDR_OF(query_qp_out, outb, qp_pas_or_qpc_ext_and_pas); 341 err_syn = MLX5_ADDR_OF(qpc_extension_and_pas_list_in, pas_ext_union, 342 qpc_data_extension.error_syndrome); 343 344 pr_err("%s/%d: QP %d error: %s (0x%x 0x%x 0x%x)\n", 345 ibqp->device->name, ibqp->port, ibqp->qp_num, 346 ib_wc_status_msg( 347 MLX5_GET(cqe_error_syndrome, err_syn, syndrome)), 348 MLX5_GET(cqe_error_syndrome, err_syn, vendor_error_syndrome), 349 MLX5_GET(cqe_error_syndrome, err_syn, hw_syndrome_type), 350 MLX5_GET(cqe_error_syndrome, err_syn, hw_error_syndrome)); 351 out: 352 kfree(outb); 353 } 354 355 static void mlx5_ib_handle_qp_event(struct work_struct *_work) 356 { 357 struct mlx5_ib_qp_event_work *qpe_work = 358 container_of(_work, struct mlx5_ib_qp_event_work, work); 359 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 360 struct ib_event event = {}; 361 362 event.device = ibqp->device; 363 event.element.qp = ibqp; 364 switch (qpe_work->type) { 365 case MLX5_EVENT_TYPE_PATH_MIG: 366 event.event = IB_EVENT_PATH_MIG; 367 break; 368 case MLX5_EVENT_TYPE_COMM_EST: 369 event.event = IB_EVENT_COMM_EST; 370 break; 371 case MLX5_EVENT_TYPE_SQ_DRAINED: 372 event.event = IB_EVENT_SQ_DRAINED; 373 break; 374 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 375 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 376 break; 377 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 378 event.event = IB_EVENT_QP_FATAL; 379 break; 380 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 381 event.event = IB_EVENT_PATH_MIG_ERR; 382 break; 383 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 384 event.event = IB_EVENT_QP_REQ_ERR; 385 break; 386 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 387 event.event = IB_EVENT_QP_ACCESS_ERR; 388 break; 389 default: 390 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", 391 qpe_work->type, qpe_work->qp->qpn); 392 goto out; 393 } 394 395 if ((event.event == IB_EVENT_QP_FATAL) || 396 (event.event == IB_EVENT_QP_ACCESS_ERR)) 397 mlx5_ib_qp_err_syndrome(ibqp); 398 399 ibqp->event_handler(&event, ibqp->qp_context); 400 401 out: 402 mlx5_core_res_put(&qpe_work->qp->common); 403 kfree(qpe_work); 404 } 405 406 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 407 { 408 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 409 struct mlx5_ib_qp_event_work *qpe_work; 410 411 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 412 /* This event is only valid for trans_qps */ 413 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 414 } 415 416 if (!ibqp->event_handler) 417 goto out_no_handler; 418 419 qpe_work = kzalloc(sizeof(*qpe_work), GFP_ATOMIC); 420 if (!qpe_work) 421 goto out_no_handler; 422 423 qpe_work->qp = qp; 424 qpe_work->type = type; 425 INIT_WORK(&qpe_work->work, mlx5_ib_handle_qp_event); 426 queue_work(mlx5_ib_qp_event_wq, &qpe_work->work); 427 return; 428 429 out_no_handler: 430 mlx5_core_res_put(&qp->common); 431 } 432 433 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 434 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 435 { 436 int wqe_size; 437 int wq_size; 438 439 /* Sanity check RQ size before proceeding */ 440 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 441 return -EINVAL; 442 443 if (!has_rq) { 444 qp->rq.max_gs = 0; 445 qp->rq.wqe_cnt = 0; 446 qp->rq.wqe_shift = 0; 447 cap->max_recv_wr = 0; 448 cap->max_recv_sge = 0; 449 } else { 450 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 451 452 if (ucmd) { 453 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 454 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 455 return -EINVAL; 456 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 457 if ((1 << qp->rq.wqe_shift) / 458 sizeof(struct mlx5_wqe_data_seg) < 459 wq_sig) 460 return -EINVAL; 461 qp->rq.max_gs = 462 (1 << qp->rq.wqe_shift) / 463 sizeof(struct mlx5_wqe_data_seg) - 464 wq_sig; 465 qp->rq.max_post = qp->rq.wqe_cnt; 466 } else { 467 wqe_size = 468 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 469 0; 470 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 471 wqe_size = roundup_pow_of_two(wqe_size); 472 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 473 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 474 qp->rq.wqe_cnt = wq_size / wqe_size; 475 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 476 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 477 wqe_size, 478 MLX5_CAP_GEN(dev->mdev, 479 max_wqe_sz_rq)); 480 return -EINVAL; 481 } 482 qp->rq.wqe_shift = ilog2(wqe_size); 483 qp->rq.max_gs = 484 (1 << qp->rq.wqe_shift) / 485 sizeof(struct mlx5_wqe_data_seg) - 486 wq_sig; 487 qp->rq.max_post = qp->rq.wqe_cnt; 488 } 489 } 490 491 return 0; 492 } 493 494 static int sq_overhead(struct ib_qp_init_attr *attr) 495 { 496 int size = 0; 497 498 switch (attr->qp_type) { 499 case IB_QPT_XRC_INI: 500 size += sizeof(struct mlx5_wqe_xrc_seg); 501 fallthrough; 502 case IB_QPT_RC: 503 size += sizeof(struct mlx5_wqe_ctrl_seg) + 504 max(sizeof(struct mlx5_wqe_atomic_seg) + 505 sizeof(struct mlx5_wqe_raddr_seg), 506 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 507 sizeof(struct mlx5_mkey_seg) + 508 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 509 MLX5_IB_UMR_OCTOWORD); 510 break; 511 512 case IB_QPT_XRC_TGT: 513 return 0; 514 515 case IB_QPT_UC: 516 size += sizeof(struct mlx5_wqe_ctrl_seg) + 517 max(sizeof(struct mlx5_wqe_raddr_seg), 518 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 519 sizeof(struct mlx5_mkey_seg)); 520 break; 521 522 case IB_QPT_UD: 523 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 524 size += sizeof(struct mlx5_wqe_eth_pad) + 525 sizeof(struct mlx5_wqe_eth_seg); 526 fallthrough; 527 case IB_QPT_SMI: 528 case MLX5_IB_QPT_HW_GSI: 529 size += sizeof(struct mlx5_wqe_ctrl_seg) + 530 sizeof(struct mlx5_wqe_datagram_seg); 531 break; 532 533 case MLX5_IB_QPT_REG_UMR: 534 size += sizeof(struct mlx5_wqe_ctrl_seg) + 535 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 536 sizeof(struct mlx5_mkey_seg); 537 break; 538 539 default: 540 return -EINVAL; 541 } 542 543 return size; 544 } 545 546 static int calc_send_wqe(struct ib_qp_init_attr *attr) 547 { 548 int inl_size = 0; 549 int size; 550 551 size = sq_overhead(attr); 552 if (size < 0) 553 return size; 554 555 if (attr->cap.max_inline_data) { 556 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 557 attr->cap.max_inline_data; 558 } 559 560 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 561 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 562 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 563 return MLX5_SIG_WQE_SIZE; 564 else 565 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 566 } 567 568 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 569 { 570 int max_sge; 571 572 if (attr->qp_type == IB_QPT_RC) 573 max_sge = (min_t(int, wqe_size, 512) - 574 sizeof(struct mlx5_wqe_ctrl_seg) - 575 sizeof(struct mlx5_wqe_raddr_seg)) / 576 sizeof(struct mlx5_wqe_data_seg); 577 else if (attr->qp_type == IB_QPT_XRC_INI) 578 max_sge = (min_t(int, wqe_size, 512) - 579 sizeof(struct mlx5_wqe_ctrl_seg) - 580 sizeof(struct mlx5_wqe_xrc_seg) - 581 sizeof(struct mlx5_wqe_raddr_seg)) / 582 sizeof(struct mlx5_wqe_data_seg); 583 else 584 max_sge = (wqe_size - sq_overhead(attr)) / 585 sizeof(struct mlx5_wqe_data_seg); 586 587 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 588 sizeof(struct mlx5_wqe_data_seg)); 589 } 590 591 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 592 struct mlx5_ib_qp *qp) 593 { 594 int wqe_size; 595 int wq_size; 596 597 if (!attr->cap.max_send_wr) 598 return 0; 599 600 wqe_size = calc_send_wqe(attr); 601 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 602 if (wqe_size < 0) 603 return wqe_size; 604 605 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 606 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 607 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 608 return -EINVAL; 609 } 610 611 qp->max_inline_data = wqe_size - sq_overhead(attr) - 612 sizeof(struct mlx5_wqe_inline_seg); 613 attr->cap.max_inline_data = qp->max_inline_data; 614 615 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 616 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 617 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 618 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 619 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 620 qp->sq.wqe_cnt, 621 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 622 return -ENOMEM; 623 } 624 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 625 qp->sq.max_gs = get_send_sge(attr, wqe_size); 626 if (qp->sq.max_gs < attr->cap.max_send_sge) 627 return -ENOMEM; 628 629 attr->cap.max_send_sge = qp->sq.max_gs; 630 qp->sq.max_post = wq_size / wqe_size; 631 attr->cap.max_send_wr = qp->sq.max_post; 632 633 return wq_size; 634 } 635 636 static int set_user_buf_size(struct mlx5_ib_dev *dev, 637 struct mlx5_ib_qp *qp, 638 struct mlx5_ib_create_qp *ucmd, 639 struct mlx5_ib_qp_base *base, 640 struct ib_qp_init_attr *attr) 641 { 642 int desc_sz = 1 << qp->sq.wqe_shift; 643 644 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 645 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 646 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 647 return -EINVAL; 648 } 649 650 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 651 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 652 ucmd->sq_wqe_count); 653 return -EINVAL; 654 } 655 656 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 657 658 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 659 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 660 qp->sq.wqe_cnt, 661 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 662 return -EINVAL; 663 } 664 665 if (attr->qp_type == IB_QPT_RAW_PACKET || 666 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 667 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 668 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 669 } else { 670 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 671 (qp->sq.wqe_cnt << 6); 672 } 673 674 return 0; 675 } 676 677 static int qp_has_rq(struct ib_qp_init_attr *attr) 678 { 679 if (attr->qp_type == IB_QPT_XRC_INI || 680 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 681 attr->qp_type == MLX5_IB_QPT_REG_UMR || 682 !attr->cap.max_recv_wr) 683 return 0; 684 685 return 1; 686 } 687 688 enum { 689 /* this is the first blue flame register in the array of bfregs assigned 690 * to a processes. Since we do not use it for blue flame but rather 691 * regular 64 bit doorbells, we do not need a lock for maintaiing 692 * "odd/even" order 693 */ 694 NUM_NON_BLUE_FLAME_BFREGS = 1, 695 }; 696 697 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 698 { 699 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 700 bfregi->num_static_sys_pages * MLX5_NON_FP_BFREGS_PER_UAR; 701 } 702 703 static int num_med_bfreg(struct mlx5_ib_dev *dev, 704 struct mlx5_bfreg_info *bfregi) 705 { 706 int n; 707 708 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 709 NUM_NON_BLUE_FLAME_BFREGS; 710 711 return n >= 0 ? n : 0; 712 } 713 714 static int first_med_bfreg(struct mlx5_ib_dev *dev, 715 struct mlx5_bfreg_info *bfregi) 716 { 717 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 718 } 719 720 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 721 struct mlx5_bfreg_info *bfregi) 722 { 723 int med; 724 725 med = num_med_bfreg(dev, bfregi); 726 return ++med; 727 } 728 729 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 730 struct mlx5_bfreg_info *bfregi) 731 { 732 int i; 733 734 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 735 if (!bfregi->count[i]) { 736 bfregi->count[i]++; 737 return i; 738 } 739 } 740 741 return -ENOMEM; 742 } 743 744 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 745 struct mlx5_bfreg_info *bfregi) 746 { 747 int minidx = first_med_bfreg(dev, bfregi); 748 int i; 749 750 if (minidx < 0) 751 return minidx; 752 753 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 754 if (bfregi->count[i] < bfregi->count[minidx]) 755 minidx = i; 756 if (!bfregi->count[minidx]) 757 break; 758 } 759 760 bfregi->count[minidx]++; 761 return minidx; 762 } 763 764 static int alloc_bfreg(struct mlx5_ib_dev *dev, 765 struct mlx5_bfreg_info *bfregi) 766 { 767 int bfregn = -ENOMEM; 768 769 if (bfregi->lib_uar_dyn) 770 return -EINVAL; 771 772 mutex_lock(&bfregi->lock); 773 if (bfregi->ver >= 2) { 774 bfregn = alloc_high_class_bfreg(dev, bfregi); 775 if (bfregn < 0) 776 bfregn = alloc_med_class_bfreg(dev, bfregi); 777 } 778 779 if (bfregn < 0) { 780 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 781 bfregn = 0; 782 bfregi->count[bfregn]++; 783 } 784 mutex_unlock(&bfregi->lock); 785 786 return bfregn; 787 } 788 789 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 790 { 791 mutex_lock(&bfregi->lock); 792 bfregi->count[bfregn]--; 793 mutex_unlock(&bfregi->lock); 794 } 795 796 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 797 { 798 switch (state) { 799 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 800 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 801 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 802 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 803 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 804 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 805 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 806 default: return -1; 807 } 808 } 809 810 static int to_mlx5_st(enum ib_qp_type type) 811 { 812 switch (type) { 813 case IB_QPT_RC: return MLX5_QP_ST_RC; 814 case IB_QPT_UC: return MLX5_QP_ST_UC; 815 case IB_QPT_UD: return MLX5_QP_ST_UD; 816 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 817 case IB_QPT_XRC_INI: 818 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 819 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 820 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 821 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 822 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 823 default: return -EINVAL; 824 } 825 } 826 827 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 828 struct mlx5_ib_cq *recv_cq); 829 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 830 struct mlx5_ib_cq *recv_cq); 831 832 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 833 struct mlx5_bfreg_info *bfregi, u32 bfregn, 834 bool dyn_bfreg) 835 { 836 unsigned int bfregs_per_sys_page; 837 u32 index_of_sys_page; 838 u32 offset; 839 840 if (bfregi->lib_uar_dyn) 841 return -EINVAL; 842 843 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 844 MLX5_NON_FP_BFREGS_PER_UAR; 845 index_of_sys_page = bfregn / bfregs_per_sys_page; 846 847 if (dyn_bfreg) { 848 index_of_sys_page += bfregi->num_static_sys_pages; 849 850 if (index_of_sys_page >= bfregi->num_sys_pages) 851 return -EINVAL; 852 853 if (bfregn > bfregi->num_dyn_bfregs || 854 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 855 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 856 return -EINVAL; 857 } 858 } 859 860 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 861 return bfregi->sys_pages[index_of_sys_page] + offset; 862 } 863 864 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 865 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 866 { 867 struct mlx5_ib_ucontext *context = 868 rdma_udata_to_drv_context( 869 udata, 870 struct mlx5_ib_ucontext, 871 ibucontext); 872 873 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 874 atomic_dec(&dev->delay_drop.rqs_cnt); 875 876 mlx5_ib_db_unmap_user(context, &rwq->db); 877 ib_umem_release(rwq->umem); 878 } 879 880 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 881 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 882 struct mlx5_ib_create_wq *ucmd) 883 { 884 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 885 udata, struct mlx5_ib_ucontext, ibucontext); 886 unsigned long page_size = 0; 887 u32 offset = 0; 888 int err; 889 890 if (!ucmd->buf_addr) 891 return -EINVAL; 892 893 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 894 if (IS_ERR(rwq->umem)) { 895 mlx5_ib_dbg(dev, "umem_get failed\n"); 896 err = PTR_ERR(rwq->umem); 897 return err; 898 } 899 900 page_size = mlx5_umem_find_best_quantized_pgoff( 901 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 902 page_offset, 64, &rwq->rq_page_offset); 903 if (!page_size) { 904 mlx5_ib_warn(dev, "bad offset\n"); 905 err = -EINVAL; 906 goto err_umem; 907 } 908 909 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 910 rwq->page_shift = order_base_2(page_size); 911 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 912 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 913 914 mlx5_ib_dbg( 915 dev, 916 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 917 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 918 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 919 offset); 920 921 err = mlx5_ib_db_map_user(ucontext, ucmd->db_addr, &rwq->db); 922 if (err) { 923 mlx5_ib_dbg(dev, "map failed\n"); 924 goto err_umem; 925 } 926 927 return 0; 928 929 err_umem: 930 ib_umem_release(rwq->umem); 931 return err; 932 } 933 934 static int adjust_bfregn(struct mlx5_ib_dev *dev, 935 struct mlx5_bfreg_info *bfregi, int bfregn) 936 { 937 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 938 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 939 } 940 941 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 942 struct mlx5_ib_qp *qp, struct ib_udata *udata, 943 struct ib_qp_init_attr *attr, u32 **in, 944 struct mlx5_ib_create_qp_resp *resp, int *inlen, 945 struct mlx5_ib_qp_base *base, 946 struct mlx5_ib_create_qp *ucmd) 947 { 948 struct mlx5_ib_ucontext *context; 949 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 950 unsigned int page_offset_quantized = 0; 951 unsigned long page_size = 0; 952 int uar_index = 0; 953 int bfregn; 954 int ncont = 0; 955 __be64 *pas; 956 void *qpc; 957 int err; 958 u16 uid; 959 u32 uar_flags; 960 961 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 962 ibucontext); 963 uar_flags = qp->flags_en & 964 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 965 switch (uar_flags) { 966 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 967 uar_index = ucmd->bfreg_index; 968 bfregn = MLX5_IB_INVALID_BFREG; 969 break; 970 case MLX5_QP_FLAG_BFREG_INDEX: 971 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 972 ucmd->bfreg_index, true); 973 if (uar_index < 0) 974 return uar_index; 975 bfregn = MLX5_IB_INVALID_BFREG; 976 break; 977 case 0: 978 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 979 return -EINVAL; 980 bfregn = alloc_bfreg(dev, &context->bfregi); 981 if (bfregn < 0) 982 return bfregn; 983 break; 984 default: 985 return -EINVAL; 986 } 987 988 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 989 if (bfregn != MLX5_IB_INVALID_BFREG) 990 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 991 false); 992 993 qp->rq.offset = 0; 994 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 995 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 996 997 err = set_user_buf_size(dev, qp, ucmd, base, attr); 998 if (err) 999 goto err_bfreg; 1000 1001 if (ucmd->buf_addr && ubuffer->buf_size) { 1002 ubuffer->buf_addr = ucmd->buf_addr; 1003 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1004 ubuffer->buf_size, 0); 1005 if (IS_ERR(ubuffer->umem)) { 1006 err = PTR_ERR(ubuffer->umem); 1007 goto err_bfreg; 1008 } 1009 page_size = mlx5_umem_find_best_quantized_pgoff( 1010 ubuffer->umem, qpc, log_page_size, 1011 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 1012 &page_offset_quantized); 1013 if (!page_size) { 1014 err = -EINVAL; 1015 goto err_umem; 1016 } 1017 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 1018 } else { 1019 ubuffer->umem = NULL; 1020 } 1021 1022 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1023 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 1024 *in = kvzalloc(*inlen, GFP_KERNEL); 1025 if (!*in) { 1026 err = -ENOMEM; 1027 goto err_umem; 1028 } 1029 1030 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 1031 MLX5_SET(create_qp_in, *in, uid, uid); 1032 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1033 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 1034 if (ubuffer->umem) { 1035 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 1036 MLX5_SET(qpc, qpc, log_page_size, 1037 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1038 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 1039 } 1040 MLX5_SET(qpc, qpc, uar_page, uar_index); 1041 if (bfregn != MLX5_IB_INVALID_BFREG) 1042 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 1043 else 1044 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 1045 qp->bfregn = bfregn; 1046 1047 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &qp->db); 1048 if (err) { 1049 mlx5_ib_dbg(dev, "map failed\n"); 1050 goto err_free; 1051 } 1052 1053 return 0; 1054 1055 err_free: 1056 kvfree(*in); 1057 1058 err_umem: 1059 ib_umem_release(ubuffer->umem); 1060 1061 err_bfreg: 1062 if (bfregn != MLX5_IB_INVALID_BFREG) 1063 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1064 return err; 1065 } 1066 1067 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1068 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 1069 { 1070 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1071 udata, struct mlx5_ib_ucontext, ibucontext); 1072 1073 if (udata) { 1074 /* User QP */ 1075 mlx5_ib_db_unmap_user(context, &qp->db); 1076 ib_umem_release(base->ubuffer.umem); 1077 1078 /* 1079 * Free only the BFREGs which are handled by the kernel. 1080 * BFREGs of UARs allocated dynamically are handled by user. 1081 */ 1082 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1083 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1084 return; 1085 } 1086 1087 /* Kernel QP */ 1088 kvfree(qp->sq.wqe_head); 1089 kvfree(qp->sq.w_list); 1090 kvfree(qp->sq.wrid); 1091 kvfree(qp->sq.wr_data); 1092 kvfree(qp->rq.wrid); 1093 if (qp->db.db) 1094 mlx5_db_free(dev->mdev, &qp->db); 1095 if (qp->buf.frags) 1096 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1097 } 1098 1099 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1100 struct ib_qp_init_attr *init_attr, 1101 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1102 struct mlx5_ib_qp_base *base) 1103 { 1104 int uar_index; 1105 void *qpc; 1106 int err; 1107 1108 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1109 qp->bf.bfreg = &dev->fp_bfreg; 1110 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1111 qp->bf.bfreg = &dev->wc_bfreg; 1112 else 1113 qp->bf.bfreg = &dev->bfreg; 1114 1115 /* We need to divide by two since each register is comprised of 1116 * two buffers of identical size, namely odd and even 1117 */ 1118 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1119 uar_index = qp->bf.bfreg->index; 1120 1121 err = calc_sq_size(dev, init_attr, qp); 1122 if (err < 0) { 1123 mlx5_ib_dbg(dev, "err %d\n", err); 1124 return err; 1125 } 1126 1127 qp->rq.offset = 0; 1128 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1129 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1130 1131 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1132 &qp->buf, dev->mdev->priv.numa_node); 1133 if (err) { 1134 mlx5_ib_dbg(dev, "err %d\n", err); 1135 return err; 1136 } 1137 1138 if (qp->rq.wqe_cnt) 1139 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1140 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1141 1142 if (qp->sq.wqe_cnt) { 1143 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1144 MLX5_SEND_WQE_BB; 1145 mlx5_init_fbc_offset(qp->buf.frags + 1146 (qp->sq.offset / PAGE_SIZE), 1147 ilog2(MLX5_SEND_WQE_BB), 1148 ilog2(qp->sq.wqe_cnt), 1149 sq_strides_offset, &qp->sq.fbc); 1150 1151 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1152 } 1153 1154 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1155 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1156 *in = kvzalloc(*inlen, GFP_KERNEL); 1157 if (!*in) { 1158 err = -ENOMEM; 1159 goto err_buf; 1160 } 1161 1162 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1163 MLX5_SET(qpc, qpc, uar_page, uar_index); 1164 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1165 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1166 1167 /* Set "fast registration enabled" for all kernel QPs */ 1168 MLX5_SET(qpc, qpc, fre, 1); 1169 MLX5_SET(qpc, qpc, rlky, 1); 1170 1171 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1172 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1173 1174 mlx5_fill_page_frag_array(&qp->buf, 1175 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1176 *in, pas)); 1177 1178 err = mlx5_db_alloc(dev->mdev, &qp->db); 1179 if (err) { 1180 mlx5_ib_dbg(dev, "err %d\n", err); 1181 goto err_free; 1182 } 1183 1184 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1185 sizeof(*qp->sq.wrid), GFP_KERNEL); 1186 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1187 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1188 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1189 sizeof(*qp->rq.wrid), GFP_KERNEL); 1190 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1191 sizeof(*qp->sq.w_list), GFP_KERNEL); 1192 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1193 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1194 1195 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1196 !qp->sq.w_list || !qp->sq.wqe_head) { 1197 err = -ENOMEM; 1198 goto err_wrid; 1199 } 1200 1201 return 0; 1202 1203 err_wrid: 1204 kvfree(qp->sq.wqe_head); 1205 kvfree(qp->sq.w_list); 1206 kvfree(qp->sq.wrid); 1207 kvfree(qp->sq.wr_data); 1208 kvfree(qp->rq.wrid); 1209 mlx5_db_free(dev->mdev, &qp->db); 1210 1211 err_free: 1212 kvfree(*in); 1213 1214 err_buf: 1215 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1216 return err; 1217 } 1218 1219 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1220 { 1221 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1222 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1223 return MLX5_SRQ_RQ; 1224 else if (!qp->has_rq) 1225 return MLX5_ZERO_LEN_RQ; 1226 1227 return MLX5_NON_ZERO_RQ; 1228 } 1229 1230 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1231 struct mlx5_ib_qp *qp, 1232 struct mlx5_ib_sq *sq, u32 tdn, 1233 struct ib_pd *pd) 1234 { 1235 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1236 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1237 1238 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1239 MLX5_SET(tisc, tisc, transport_domain, tdn); 1240 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1241 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1242 1243 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1244 } 1245 1246 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1247 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1248 { 1249 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1250 } 1251 1252 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1253 { 1254 if (sq->flow_rule) 1255 mlx5_del_flow_rules(sq->flow_rule); 1256 sq->flow_rule = NULL; 1257 } 1258 1259 static bool fr_supported(int ts_cap) 1260 { 1261 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1262 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1263 } 1264 1265 static int get_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1266 bool fr_sup, bool rt_sup) 1267 { 1268 if (cq->private_flags & MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS) { 1269 if (!rt_sup) { 1270 mlx5_ib_dbg(dev, 1271 "Real time TS format is not supported\n"); 1272 return -EOPNOTSUPP; 1273 } 1274 return MLX5_TIMESTAMP_FORMAT_REAL_TIME; 1275 } 1276 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1277 if (!fr_sup) { 1278 mlx5_ib_dbg(dev, 1279 "Free running TS format is not supported\n"); 1280 return -EOPNOTSUPP; 1281 } 1282 return MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1283 } 1284 return fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1285 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1286 } 1287 1288 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *recv_cq) 1289 { 1290 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, rq_ts_format); 1291 1292 return get_ts_format(dev, recv_cq, fr_supported(ts_cap), 1293 rt_supported(ts_cap)); 1294 } 1295 1296 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1297 { 1298 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, sq_ts_format); 1299 1300 return get_ts_format(dev, send_cq, fr_supported(ts_cap), 1301 rt_supported(ts_cap)); 1302 } 1303 1304 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1305 struct mlx5_ib_cq *recv_cq) 1306 { 1307 u8 ts_cap = MLX5_CAP_ROCE(dev->mdev, qp_ts_format); 1308 bool fr_sup = fr_supported(ts_cap); 1309 bool rt_sup = rt_supported(ts_cap); 1310 u8 default_ts = fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1311 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1312 int send_ts_format = 1313 send_cq ? get_ts_format(dev, send_cq, fr_sup, rt_sup) : 1314 default_ts; 1315 int recv_ts_format = 1316 recv_cq ? get_ts_format(dev, recv_cq, fr_sup, rt_sup) : 1317 default_ts; 1318 1319 if (send_ts_format < 0 || recv_ts_format < 0) 1320 return -EOPNOTSUPP; 1321 1322 if (send_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1323 recv_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1324 send_ts_format != recv_ts_format) { 1325 mlx5_ib_dbg( 1326 dev, 1327 "The send ts_format does not match the receive ts_format\n"); 1328 return -EOPNOTSUPP; 1329 } 1330 1331 return send_ts_format == default_ts ? recv_ts_format : send_ts_format; 1332 } 1333 1334 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1335 struct ib_udata *udata, 1336 struct mlx5_ib_sq *sq, void *qpin, 1337 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1338 { 1339 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1340 __be64 *pas; 1341 void *in; 1342 void *sqc; 1343 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1344 void *wq; 1345 int inlen; 1346 int err; 1347 unsigned int page_offset_quantized; 1348 unsigned long page_size; 1349 int ts_format; 1350 1351 ts_format = get_sq_ts_format(dev, cq); 1352 if (ts_format < 0) 1353 return ts_format; 1354 1355 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1356 ubuffer->buf_size, 0); 1357 if (IS_ERR(sq->ubuffer.umem)) 1358 return PTR_ERR(sq->ubuffer.umem); 1359 page_size = mlx5_umem_find_best_quantized_pgoff( 1360 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1361 page_offset, 64, &page_offset_quantized); 1362 if (!page_size) { 1363 err = -EINVAL; 1364 goto err_umem; 1365 } 1366 1367 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1368 sizeof(u64) * 1369 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1370 in = kvzalloc(inlen, GFP_KERNEL); 1371 if (!in) { 1372 err = -ENOMEM; 1373 goto err_umem; 1374 } 1375 1376 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1377 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1378 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1379 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1380 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1381 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1382 MLX5_SET(sqc, sqc, ts_format, ts_format); 1383 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1384 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1385 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1386 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1387 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1388 MLX5_CAP_ETH(dev->mdev, swp)) 1389 MLX5_SET(sqc, sqc, allow_swp, 1); 1390 1391 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1392 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1393 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1394 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1395 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1396 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1397 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1398 MLX5_SET(wq, wq, log_wq_pg_sz, 1399 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1400 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1401 1402 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1403 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1404 1405 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1406 1407 kvfree(in); 1408 1409 if (err) 1410 goto err_umem; 1411 1412 return 0; 1413 1414 err_umem: 1415 ib_umem_release(sq->ubuffer.umem); 1416 sq->ubuffer.umem = NULL; 1417 1418 return err; 1419 } 1420 1421 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1422 struct mlx5_ib_sq *sq) 1423 { 1424 destroy_flow_rule_vport_sq(sq); 1425 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1426 ib_umem_release(sq->ubuffer.umem); 1427 } 1428 1429 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1430 struct mlx5_ib_rq *rq, void *qpin, 1431 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1432 { 1433 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1434 __be64 *pas; 1435 void *in; 1436 void *rqc; 1437 void *wq; 1438 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1439 struct ib_umem *umem = rq->base.ubuffer.umem; 1440 unsigned int page_offset_quantized; 1441 unsigned long page_size = 0; 1442 int ts_format; 1443 size_t inlen; 1444 int err; 1445 1446 ts_format = get_rq_ts_format(dev, cq); 1447 if (ts_format < 0) 1448 return ts_format; 1449 1450 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1451 MLX5_ADAPTER_PAGE_SHIFT, 1452 page_offset, 64, 1453 &page_offset_quantized); 1454 if (!page_size) 1455 return -EINVAL; 1456 1457 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1458 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1459 in = kvzalloc(inlen, GFP_KERNEL); 1460 if (!in) 1461 return -ENOMEM; 1462 1463 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1464 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1465 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1466 MLX5_SET(rqc, rqc, vsd, 1); 1467 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1468 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1469 MLX5_SET(rqc, rqc, ts_format, ts_format); 1470 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1471 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1472 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1473 1474 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1475 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1476 1477 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1478 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1479 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1480 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1481 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1482 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1483 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1484 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1485 MLX5_SET(wq, wq, log_wq_pg_sz, 1486 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1487 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1488 1489 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1490 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1491 1492 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1493 1494 kvfree(in); 1495 1496 return err; 1497 } 1498 1499 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1500 struct mlx5_ib_rq *rq) 1501 { 1502 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1503 } 1504 1505 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1506 struct mlx5_ib_rq *rq, 1507 u32 qp_flags_en, 1508 struct ib_pd *pd) 1509 { 1510 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1511 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1512 mlx5_ib_disable_lb(dev, false, true); 1513 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1514 } 1515 1516 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1517 struct mlx5_ib_rq *rq, u32 tdn, 1518 u32 *qp_flags_en, struct ib_pd *pd, 1519 u32 *out) 1520 { 1521 u8 lb_flag = 0; 1522 u32 *in; 1523 void *tirc; 1524 int inlen; 1525 int err; 1526 1527 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1528 in = kvzalloc(inlen, GFP_KERNEL); 1529 if (!in) 1530 return -ENOMEM; 1531 1532 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1533 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1534 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1535 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1536 MLX5_SET(tirc, tirc, transport_domain, tdn); 1537 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1538 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1539 1540 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1541 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1542 1543 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1544 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1545 1546 if (dev->is_rep) { 1547 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1548 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1549 } 1550 1551 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1552 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1553 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1554 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1555 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1556 err = mlx5_ib_enable_lb(dev, false, true); 1557 1558 if (err) 1559 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1560 } 1561 kvfree(in); 1562 1563 return err; 1564 } 1565 1566 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1567 u32 *in, size_t inlen, struct ib_pd *pd, 1568 struct ib_udata *udata, 1569 struct mlx5_ib_create_qp_resp *resp, 1570 struct ib_qp_init_attr *init_attr) 1571 { 1572 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1573 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1574 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1575 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1576 udata, struct mlx5_ib_ucontext, ibucontext); 1577 int err; 1578 u32 tdn = mucontext->tdn; 1579 u16 uid = to_mpd(pd)->uid; 1580 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1581 1582 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1583 return -EINVAL; 1584 if (qp->sq.wqe_cnt) { 1585 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1586 if (err) 1587 return err; 1588 1589 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1590 to_mcq(init_attr->send_cq)); 1591 if (err) 1592 goto err_destroy_tis; 1593 1594 if (uid) { 1595 resp->tisn = sq->tisn; 1596 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1597 resp->sqn = sq->base.mqp.qpn; 1598 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1599 } 1600 1601 sq->base.container_mibqp = qp; 1602 sq->base.mqp.event = mlx5_ib_qp_event; 1603 } 1604 1605 if (qp->rq.wqe_cnt) { 1606 rq->base.container_mibqp = qp; 1607 1608 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1609 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1610 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1611 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1612 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1613 to_mcq(init_attr->recv_cq)); 1614 if (err) 1615 goto err_destroy_sq; 1616 1617 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1618 out); 1619 if (err) 1620 goto err_destroy_rq; 1621 1622 if (uid) { 1623 resp->rqn = rq->base.mqp.qpn; 1624 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1625 resp->tirn = rq->tirn; 1626 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1627 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1628 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1629 resp->tir_icm_addr = MLX5_GET( 1630 create_tir_out, out, icm_address_31_0); 1631 resp->tir_icm_addr |= 1632 (u64)MLX5_GET(create_tir_out, out, 1633 icm_address_39_32) 1634 << 32; 1635 resp->tir_icm_addr |= 1636 (u64)MLX5_GET(create_tir_out, out, 1637 icm_address_63_40) 1638 << 40; 1639 resp->comp_mask |= 1640 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1641 } 1642 } 1643 } 1644 1645 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1646 rq->base.mqp.qpn; 1647 return 0; 1648 1649 err_destroy_rq: 1650 destroy_raw_packet_qp_rq(dev, rq); 1651 err_destroy_sq: 1652 if (!qp->sq.wqe_cnt) 1653 return err; 1654 destroy_raw_packet_qp_sq(dev, sq); 1655 err_destroy_tis: 1656 destroy_raw_packet_qp_tis(dev, sq, pd); 1657 1658 return err; 1659 } 1660 1661 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1662 struct mlx5_ib_qp *qp) 1663 { 1664 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1665 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1666 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1667 1668 if (qp->rq.wqe_cnt) { 1669 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1670 destroy_raw_packet_qp_rq(dev, rq); 1671 } 1672 1673 if (qp->sq.wqe_cnt) { 1674 destroy_raw_packet_qp_sq(dev, sq); 1675 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1676 } 1677 } 1678 1679 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1680 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1681 { 1682 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1683 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1684 1685 sq->sq = &qp->sq; 1686 rq->rq = &qp->rq; 1687 sq->doorbell = &qp->db; 1688 rq->doorbell = &qp->db; 1689 } 1690 1691 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1692 { 1693 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1694 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1695 mlx5_ib_disable_lb(dev, false, true); 1696 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1697 to_mpd(qp->ibqp.pd)->uid); 1698 } 1699 1700 struct mlx5_create_qp_params { 1701 struct ib_udata *udata; 1702 size_t inlen; 1703 size_t outlen; 1704 size_t ucmd_size; 1705 void *ucmd; 1706 u8 is_rss_raw : 1; 1707 struct ib_qp_init_attr *attr; 1708 u32 uidx; 1709 struct mlx5_ib_create_qp_resp resp; 1710 }; 1711 1712 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1713 struct mlx5_ib_qp *qp, 1714 struct mlx5_create_qp_params *params) 1715 { 1716 struct ib_qp_init_attr *init_attr = params->attr; 1717 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1718 struct ib_udata *udata = params->udata; 1719 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1720 udata, struct mlx5_ib_ucontext, ibucontext); 1721 int inlen; 1722 int outlen; 1723 int err; 1724 u32 *in; 1725 u32 *out; 1726 void *tirc; 1727 void *hfso; 1728 u32 selected_fields = 0; 1729 u32 outer_l4; 1730 u32 tdn = mucontext->tdn; 1731 u8 lb_flag = 0; 1732 1733 if (ucmd->comp_mask) { 1734 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1735 return -EOPNOTSUPP; 1736 } 1737 1738 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1739 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1740 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1741 return -EOPNOTSUPP; 1742 } 1743 1744 if (dev->is_rep) 1745 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1746 1747 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1748 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1749 1750 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1751 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1752 1753 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1754 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1755 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1756 if (!in) 1757 return -ENOMEM; 1758 1759 out = in + MLX5_ST_SZ_DW(create_tir_in); 1760 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1761 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1762 MLX5_SET(tirc, tirc, disp_type, 1763 MLX5_TIRC_DISP_TYPE_INDIRECT); 1764 MLX5_SET(tirc, tirc, indirect_table, 1765 init_attr->rwq_ind_tbl->ind_tbl_num); 1766 MLX5_SET(tirc, tirc, transport_domain, tdn); 1767 1768 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1769 1770 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1771 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1772 1773 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1774 1775 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1776 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1777 else 1778 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1779 1780 switch (ucmd->rx_hash_function) { 1781 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1782 { 1783 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1784 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1785 1786 if (len != ucmd->rx_key_len) { 1787 err = -EINVAL; 1788 goto err; 1789 } 1790 1791 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1792 memcpy(rss_key, ucmd->rx_hash_key, len); 1793 break; 1794 } 1795 default: 1796 err = -EOPNOTSUPP; 1797 goto err; 1798 } 1799 1800 if (!ucmd->rx_hash_fields_mask) { 1801 /* special case when this TIR serves as steering entry without hashing */ 1802 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1803 goto create_tir; 1804 err = -EINVAL; 1805 goto err; 1806 } 1807 1808 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1809 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1810 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1811 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1812 err = -EINVAL; 1813 goto err; 1814 } 1815 1816 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1817 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1818 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1819 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1820 MLX5_L3_PROT_TYPE_IPV4); 1821 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1822 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1823 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1824 MLX5_L3_PROT_TYPE_IPV6); 1825 1826 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1827 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1828 << 0 | 1829 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1830 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1831 << 1 | 1832 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1833 1834 /* Check that only one l4 protocol is set */ 1835 if (outer_l4 & (outer_l4 - 1)) { 1836 err = -EINVAL; 1837 goto err; 1838 } 1839 1840 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1841 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1842 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1843 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1844 MLX5_L4_PROT_TYPE_TCP); 1845 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1846 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1847 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1848 MLX5_L4_PROT_TYPE_UDP); 1849 1850 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1851 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1852 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1853 1854 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1855 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1856 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1857 1858 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1859 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1860 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1861 1862 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1863 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1864 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1865 1866 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1867 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1868 1869 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1870 1871 create_tir: 1872 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1873 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1874 1875 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1876 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1877 err = mlx5_ib_enable_lb(dev, false, true); 1878 1879 if (err) 1880 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1881 to_mpd(pd)->uid); 1882 } 1883 1884 if (err) 1885 goto err; 1886 1887 if (mucontext->devx_uid) { 1888 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1889 params->resp.tirn = qp->rss_qp.tirn; 1890 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1891 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1892 params->resp.tir_icm_addr = 1893 MLX5_GET(create_tir_out, out, icm_address_31_0); 1894 params->resp.tir_icm_addr |= 1895 (u64)MLX5_GET(create_tir_out, out, 1896 icm_address_39_32) 1897 << 32; 1898 params->resp.tir_icm_addr |= 1899 (u64)MLX5_GET(create_tir_out, out, 1900 icm_address_63_40) 1901 << 40; 1902 params->resp.comp_mask |= 1903 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1904 } 1905 } 1906 1907 kvfree(in); 1908 /* qpn is reserved for that QP */ 1909 qp->trans_qp.base.mqp.qpn = 0; 1910 qp->is_rss = true; 1911 return 0; 1912 1913 err: 1914 kvfree(in); 1915 return err; 1916 } 1917 1918 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1919 struct mlx5_ib_qp *qp, 1920 struct ib_qp_init_attr *init_attr, 1921 void *qpc) 1922 { 1923 int scqe_sz; 1924 bool allow_scat_cqe = false; 1925 1926 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1927 1928 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1929 return; 1930 1931 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1932 if (scqe_sz == 128) { 1933 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1934 return; 1935 } 1936 1937 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1938 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1939 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1940 } 1941 1942 static int atomic_size_to_mode(int size_mask) 1943 { 1944 /* driver does not support atomic_size > 256B 1945 * and does not know how to translate bigger sizes 1946 */ 1947 int supported_size_mask = size_mask & 0x1ff; 1948 int log_max_size; 1949 1950 if (!supported_size_mask) 1951 return -EOPNOTSUPP; 1952 1953 log_max_size = __fls(supported_size_mask); 1954 1955 if (log_max_size > 3) 1956 return log_max_size; 1957 1958 return MLX5_ATOMIC_MODE_8B; 1959 } 1960 1961 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1962 enum ib_qp_type qp_type) 1963 { 1964 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1965 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1966 int atomic_mode = -EOPNOTSUPP; 1967 int atomic_size_mask; 1968 1969 if (!atomic) 1970 return -EOPNOTSUPP; 1971 1972 if (qp_type == MLX5_IB_QPT_DCT) 1973 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1974 else 1975 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1976 1977 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1978 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1979 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1980 1981 if (atomic_mode <= 0 && 1982 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1983 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1984 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1985 1986 return atomic_mode; 1987 } 1988 1989 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1990 struct mlx5_create_qp_params *params) 1991 { 1992 struct ib_qp_init_attr *attr = params->attr; 1993 u32 uidx = params->uidx; 1994 struct mlx5_ib_resources *devr = &dev->devr; 1995 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1996 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1997 struct mlx5_core_dev *mdev = dev->mdev; 1998 struct mlx5_ib_qp_base *base; 1999 unsigned long flags; 2000 void *qpc; 2001 u32 *in; 2002 int err; 2003 2004 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2005 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2006 2007 in = kvzalloc(inlen, GFP_KERNEL); 2008 if (!in) 2009 return -ENOMEM; 2010 2011 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2012 2013 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 2014 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2015 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 2016 2017 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2018 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2019 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2020 MLX5_SET(qpc, qpc, cd_master, 1); 2021 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2022 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2023 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2024 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2025 2026 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 2027 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 2028 MLX5_SET(qpc, qpc, no_sq, 1); 2029 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2030 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2031 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2032 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 2033 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2034 2035 /* 0xffffff means we ask to work with cqe version 0 */ 2036 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2037 MLX5_SET(qpc, qpc, user_index, uidx); 2038 2039 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2040 MLX5_SET(qpc, qpc, end_padding_mode, 2041 MLX5_WQ_END_PAD_MODE_ALIGN); 2042 /* Special case to clean flag */ 2043 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2044 } 2045 2046 base = &qp->trans_qp.base; 2047 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2048 kvfree(in); 2049 if (err) 2050 return err; 2051 2052 base->container_mibqp = qp; 2053 base->mqp.event = mlx5_ib_qp_event; 2054 if (MLX5_CAP_GEN(mdev, ece_support)) 2055 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2056 2057 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2058 list_add_tail(&qp->qps_list, &dev->qp_list); 2059 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2060 2061 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 2062 return 0; 2063 } 2064 2065 static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2066 struct mlx5_ib_qp *qp, 2067 struct mlx5_create_qp_params *params) 2068 { 2069 struct ib_qp_init_attr *init_attr = params->attr; 2070 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2071 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2072 struct ib_udata *udata = params->udata; 2073 u32 uidx = params->uidx; 2074 struct mlx5_ib_resources *devr = &dev->devr; 2075 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2076 struct mlx5_core_dev *mdev = dev->mdev; 2077 struct mlx5_ib_cq *send_cq; 2078 struct mlx5_ib_cq *recv_cq; 2079 unsigned long flags; 2080 struct mlx5_ib_qp_base *base; 2081 int ts_format; 2082 int mlx5_st; 2083 void *qpc; 2084 u32 *in; 2085 int err; 2086 2087 spin_lock_init(&qp->sq.lock); 2088 spin_lock_init(&qp->rq.lock); 2089 2090 mlx5_st = to_mlx5_st(qp->type); 2091 if (mlx5_st < 0) 2092 return -EINVAL; 2093 2094 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2095 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2096 2097 base = &qp->trans_qp.base; 2098 2099 qp->has_rq = qp_has_rq(init_attr); 2100 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2101 if (err) { 2102 mlx5_ib_dbg(dev, "err %d\n", err); 2103 return err; 2104 } 2105 2106 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2107 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2108 return -EINVAL; 2109 2110 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2111 return -EINVAL; 2112 2113 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2114 to_mcq(init_attr->recv_cq)); 2115 2116 if (ts_format < 0) 2117 return ts_format; 2118 2119 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2120 &inlen, base, ucmd); 2121 if (err) 2122 return err; 2123 2124 if (MLX5_CAP_GEN(mdev, ece_support)) 2125 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2126 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2127 2128 MLX5_SET(qpc, qpc, st, mlx5_st); 2129 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2130 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2131 2132 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2133 MLX5_SET(qpc, qpc, wq_signature, 1); 2134 2135 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2136 MLX5_SET(qpc, qpc, cd_master, 1); 2137 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2138 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2139 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) 2140 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2141 2142 if (qp->rq.wqe_cnt) { 2143 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2144 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2145 } 2146 2147 if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) { 2148 MLX5_SET(qpc, qpc, log_num_dci_stream_channels, 2149 ucmd->dci_streams.log_num_concurent); 2150 MLX5_SET(qpc, qpc, log_num_dci_errored_streams, 2151 ucmd->dci_streams.log_num_errored); 2152 } 2153 2154 MLX5_SET(qpc, qpc, ts_format, ts_format); 2155 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2156 2157 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2158 2159 /* Set default resources */ 2160 if (init_attr->srq) { 2161 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2162 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2163 to_msrq(init_attr->srq)->msrq.srqn); 2164 } else { 2165 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2166 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2167 to_msrq(devr->s1)->msrq.srqn); 2168 } 2169 2170 if (init_attr->send_cq) 2171 MLX5_SET(qpc, qpc, cqn_snd, 2172 to_mcq(init_attr->send_cq)->mcq.cqn); 2173 2174 if (init_attr->recv_cq) 2175 MLX5_SET(qpc, qpc, cqn_rcv, 2176 to_mcq(init_attr->recv_cq)->mcq.cqn); 2177 2178 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2179 2180 /* 0xffffff means we ask to work with cqe version 0 */ 2181 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2182 MLX5_SET(qpc, qpc, user_index, uidx); 2183 2184 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2185 MLX5_SET(qpc, qpc, end_padding_mode, 2186 MLX5_WQ_END_PAD_MODE_ALIGN); 2187 /* Special case to clean flag */ 2188 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2189 } 2190 2191 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2192 2193 kvfree(in); 2194 if (err) 2195 goto err_create; 2196 2197 base->container_mibqp = qp; 2198 base->mqp.event = mlx5_ib_qp_event; 2199 if (MLX5_CAP_GEN(mdev, ece_support)) 2200 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2201 2202 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2203 &send_cq, &recv_cq); 2204 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2205 mlx5_ib_lock_cqs(send_cq, recv_cq); 2206 /* Maintain device to QPs access, needed for further handling via reset 2207 * flow 2208 */ 2209 list_add_tail(&qp->qps_list, &dev->qp_list); 2210 /* Maintain CQ to QPs access, needed for further handling via reset flow 2211 */ 2212 if (send_cq) 2213 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2214 if (recv_cq) 2215 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2216 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2217 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2218 2219 return 0; 2220 2221 err_create: 2222 destroy_qp(dev, qp, base, udata); 2223 return err; 2224 } 2225 2226 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2227 struct mlx5_ib_qp *qp, 2228 struct mlx5_create_qp_params *params) 2229 { 2230 struct ib_qp_init_attr *init_attr = params->attr; 2231 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2232 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2233 struct ib_udata *udata = params->udata; 2234 u32 uidx = params->uidx; 2235 struct mlx5_ib_resources *devr = &dev->devr; 2236 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2237 struct mlx5_core_dev *mdev = dev->mdev; 2238 struct mlx5_ib_cq *send_cq; 2239 struct mlx5_ib_cq *recv_cq; 2240 unsigned long flags; 2241 struct mlx5_ib_qp_base *base; 2242 int ts_format; 2243 int mlx5_st; 2244 void *qpc; 2245 u32 *in; 2246 int err; 2247 2248 spin_lock_init(&qp->sq.lock); 2249 spin_lock_init(&qp->rq.lock); 2250 2251 mlx5_st = to_mlx5_st(qp->type); 2252 if (mlx5_st < 0) 2253 return -EINVAL; 2254 2255 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2256 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2257 2258 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2259 qp->underlay_qpn = init_attr->source_qpn; 2260 2261 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2262 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2263 &qp->raw_packet_qp.rq.base : 2264 &qp->trans_qp.base; 2265 2266 qp->has_rq = qp_has_rq(init_attr); 2267 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2268 if (err) { 2269 mlx5_ib_dbg(dev, "err %d\n", err); 2270 return err; 2271 } 2272 2273 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2274 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2275 return -EINVAL; 2276 2277 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2278 return -EINVAL; 2279 2280 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2281 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2282 to_mcq(init_attr->recv_cq)); 2283 if (ts_format < 0) 2284 return ts_format; 2285 } 2286 2287 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2288 &inlen, base, ucmd); 2289 if (err) 2290 return err; 2291 2292 if (is_sqp(init_attr->qp_type)) 2293 qp->port = init_attr->port_num; 2294 2295 if (MLX5_CAP_GEN(mdev, ece_support)) 2296 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2297 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2298 2299 MLX5_SET(qpc, qpc, st, mlx5_st); 2300 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2301 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2302 2303 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2304 MLX5_SET(qpc, qpc, wq_signature, 1); 2305 2306 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2307 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2308 2309 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2310 MLX5_SET(qpc, qpc, cd_master, 1); 2311 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2312 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2313 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2314 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2315 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2316 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2317 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2318 (init_attr->qp_type == IB_QPT_RC || 2319 init_attr->qp_type == IB_QPT_UC)) { 2320 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2321 2322 MLX5_SET(qpc, qpc, cs_res, 2323 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2324 MLX5_RES_SCAT_DATA32_CQE); 2325 } 2326 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2327 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2328 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2329 2330 if (qp->rq.wqe_cnt) { 2331 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2332 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2333 } 2334 2335 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2336 MLX5_SET(qpc, qpc, ts_format, ts_format); 2337 2338 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2339 2340 if (qp->sq.wqe_cnt) { 2341 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2342 } else { 2343 MLX5_SET(qpc, qpc, no_sq, 1); 2344 if (init_attr->srq && 2345 init_attr->srq->srq_type == IB_SRQT_TM) 2346 MLX5_SET(qpc, qpc, offload_type, 2347 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2348 } 2349 2350 /* Set default resources */ 2351 switch (init_attr->qp_type) { 2352 case IB_QPT_XRC_INI: 2353 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2354 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2355 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2356 break; 2357 default: 2358 if (init_attr->srq) { 2359 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2360 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2361 } else { 2362 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2363 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2364 } 2365 } 2366 2367 if (init_attr->send_cq) 2368 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2369 2370 if (init_attr->recv_cq) 2371 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2372 2373 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2374 2375 /* 0xffffff means we ask to work with cqe version 0 */ 2376 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2377 MLX5_SET(qpc, qpc, user_index, uidx); 2378 2379 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2380 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2381 MLX5_SET(qpc, qpc, end_padding_mode, 2382 MLX5_WQ_END_PAD_MODE_ALIGN); 2383 /* Special case to clean flag */ 2384 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2385 } 2386 2387 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2388 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2389 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2390 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2391 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2392 ¶ms->resp, init_attr); 2393 } else 2394 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2395 2396 kvfree(in); 2397 if (err) 2398 goto err_create; 2399 2400 base->container_mibqp = qp; 2401 base->mqp.event = mlx5_ib_qp_event; 2402 if (MLX5_CAP_GEN(mdev, ece_support)) 2403 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2404 2405 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2406 &send_cq, &recv_cq); 2407 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2408 mlx5_ib_lock_cqs(send_cq, recv_cq); 2409 /* Maintain device to QPs access, needed for further handling via reset 2410 * flow 2411 */ 2412 list_add_tail(&qp->qps_list, &dev->qp_list); 2413 /* Maintain CQ to QPs access, needed for further handling via reset flow 2414 */ 2415 if (send_cq) 2416 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2417 if (recv_cq) 2418 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2419 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2420 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2421 2422 return 0; 2423 2424 err_create: 2425 destroy_qp(dev, qp, base, udata); 2426 return err; 2427 } 2428 2429 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2430 struct mlx5_ib_qp *qp, 2431 struct mlx5_create_qp_params *params) 2432 { 2433 struct ib_qp_init_attr *attr = params->attr; 2434 u32 uidx = params->uidx; 2435 struct mlx5_ib_resources *devr = &dev->devr; 2436 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2437 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2438 struct mlx5_core_dev *mdev = dev->mdev; 2439 struct mlx5_ib_cq *send_cq; 2440 struct mlx5_ib_cq *recv_cq; 2441 unsigned long flags; 2442 struct mlx5_ib_qp_base *base; 2443 int mlx5_st; 2444 void *qpc; 2445 u32 *in; 2446 int err; 2447 2448 spin_lock_init(&qp->sq.lock); 2449 spin_lock_init(&qp->rq.lock); 2450 2451 mlx5_st = to_mlx5_st(qp->type); 2452 if (mlx5_st < 0) 2453 return -EINVAL; 2454 2455 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2456 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2457 2458 base = &qp->trans_qp.base; 2459 2460 qp->has_rq = qp_has_rq(attr); 2461 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2462 if (err) { 2463 mlx5_ib_dbg(dev, "err %d\n", err); 2464 return err; 2465 } 2466 2467 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2468 if (err) 2469 return err; 2470 2471 if (is_sqp(attr->qp_type)) 2472 qp->port = attr->port_num; 2473 2474 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2475 2476 MLX5_SET(qpc, qpc, st, mlx5_st); 2477 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2478 2479 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2480 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2481 else 2482 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2483 2484 2485 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2486 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2487 2488 if (qp->rq.wqe_cnt) { 2489 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2490 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2491 } 2492 2493 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2494 2495 if (qp->sq.wqe_cnt) 2496 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2497 else 2498 MLX5_SET(qpc, qpc, no_sq, 1); 2499 2500 if (attr->srq) { 2501 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2502 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2503 to_msrq(attr->srq)->msrq.srqn); 2504 } else { 2505 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2506 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2507 to_msrq(devr->s1)->msrq.srqn); 2508 } 2509 2510 if (attr->send_cq) 2511 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2512 2513 if (attr->recv_cq) 2514 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2515 2516 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2517 2518 /* 0xffffff means we ask to work with cqe version 0 */ 2519 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2520 MLX5_SET(qpc, qpc, user_index, uidx); 2521 2522 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2523 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2524 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2525 2526 if (qp->flags & IB_QP_CREATE_INTEGRITY_EN && 2527 MLX5_CAP_GEN(mdev, go_back_n)) 2528 MLX5_SET(qpc, qpc, retry_mode, MLX5_QP_RM_GO_BACK_N); 2529 2530 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2531 kvfree(in); 2532 if (err) 2533 goto err_create; 2534 2535 base->container_mibqp = qp; 2536 base->mqp.event = mlx5_ib_qp_event; 2537 2538 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2539 &send_cq, &recv_cq); 2540 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2541 mlx5_ib_lock_cqs(send_cq, recv_cq); 2542 /* Maintain device to QPs access, needed for further handling via reset 2543 * flow 2544 */ 2545 list_add_tail(&qp->qps_list, &dev->qp_list); 2546 /* Maintain CQ to QPs access, needed for further handling via reset flow 2547 */ 2548 if (send_cq) 2549 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2550 if (recv_cq) 2551 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2552 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2553 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2554 2555 return 0; 2556 2557 err_create: 2558 destroy_qp(dev, qp, base, NULL); 2559 return err; 2560 } 2561 2562 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2563 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2564 { 2565 if (send_cq) { 2566 if (recv_cq) { 2567 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2568 spin_lock(&send_cq->lock); 2569 spin_lock_nested(&recv_cq->lock, 2570 SINGLE_DEPTH_NESTING); 2571 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2572 spin_lock(&send_cq->lock); 2573 __acquire(&recv_cq->lock); 2574 } else { 2575 spin_lock(&recv_cq->lock); 2576 spin_lock_nested(&send_cq->lock, 2577 SINGLE_DEPTH_NESTING); 2578 } 2579 } else { 2580 spin_lock(&send_cq->lock); 2581 __acquire(&recv_cq->lock); 2582 } 2583 } else if (recv_cq) { 2584 spin_lock(&recv_cq->lock); 2585 __acquire(&send_cq->lock); 2586 } else { 2587 __acquire(&send_cq->lock); 2588 __acquire(&recv_cq->lock); 2589 } 2590 } 2591 2592 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2593 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2594 { 2595 if (send_cq) { 2596 if (recv_cq) { 2597 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2598 spin_unlock(&recv_cq->lock); 2599 spin_unlock(&send_cq->lock); 2600 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2601 __release(&recv_cq->lock); 2602 spin_unlock(&send_cq->lock); 2603 } else { 2604 spin_unlock(&send_cq->lock); 2605 spin_unlock(&recv_cq->lock); 2606 } 2607 } else { 2608 __release(&recv_cq->lock); 2609 spin_unlock(&send_cq->lock); 2610 } 2611 } else if (recv_cq) { 2612 __release(&send_cq->lock); 2613 spin_unlock(&recv_cq->lock); 2614 } else { 2615 __release(&recv_cq->lock); 2616 __release(&send_cq->lock); 2617 } 2618 } 2619 2620 static void get_cqs(enum ib_qp_type qp_type, 2621 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2622 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2623 { 2624 switch (qp_type) { 2625 case IB_QPT_XRC_TGT: 2626 *send_cq = NULL; 2627 *recv_cq = NULL; 2628 break; 2629 case MLX5_IB_QPT_REG_UMR: 2630 case IB_QPT_XRC_INI: 2631 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2632 *recv_cq = NULL; 2633 break; 2634 2635 case IB_QPT_SMI: 2636 case MLX5_IB_QPT_HW_GSI: 2637 case IB_QPT_RC: 2638 case IB_QPT_UC: 2639 case IB_QPT_UD: 2640 case IB_QPT_RAW_PACKET: 2641 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2642 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2643 break; 2644 default: 2645 *send_cq = NULL; 2646 *recv_cq = NULL; 2647 break; 2648 } 2649 } 2650 2651 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2652 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2653 u8 lag_tx_affinity); 2654 2655 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2656 struct ib_udata *udata) 2657 { 2658 struct mlx5_ib_cq *send_cq, *recv_cq; 2659 struct mlx5_ib_qp_base *base; 2660 unsigned long flags; 2661 int err; 2662 2663 if (qp->is_rss) { 2664 destroy_rss_raw_qp_tir(dev, qp); 2665 return; 2666 } 2667 2668 base = (qp->type == IB_QPT_RAW_PACKET || 2669 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2670 &qp->raw_packet_qp.rq.base : 2671 &qp->trans_qp.base; 2672 2673 if (qp->state != IB_QPS_RESET) { 2674 if (qp->type != IB_QPT_RAW_PACKET && 2675 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2676 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2677 NULL, &base->mqp, NULL); 2678 } else { 2679 struct mlx5_modify_raw_qp_param raw_qp_param = { 2680 .operation = MLX5_CMD_OP_2RST_QP 2681 }; 2682 2683 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2684 } 2685 if (err) 2686 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2687 base->mqp.qpn); 2688 } 2689 2690 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2691 &recv_cq); 2692 2693 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2694 mlx5_ib_lock_cqs(send_cq, recv_cq); 2695 /* del from lists under both locks above to protect reset flow paths */ 2696 list_del(&qp->qps_list); 2697 if (send_cq) 2698 list_del(&qp->cq_send_list); 2699 2700 if (recv_cq) 2701 list_del(&qp->cq_recv_list); 2702 2703 if (!udata) { 2704 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2705 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2706 if (send_cq != recv_cq) 2707 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2708 NULL); 2709 } 2710 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2711 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2712 2713 if (qp->type == IB_QPT_RAW_PACKET || 2714 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2715 destroy_raw_packet_qp(dev, qp); 2716 } else { 2717 err = mlx5_core_destroy_qp(dev, &base->mqp); 2718 if (err) 2719 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2720 base->mqp.qpn); 2721 } 2722 2723 destroy_qp(dev, qp, base, udata); 2724 } 2725 2726 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2727 struct mlx5_ib_qp *qp, 2728 struct mlx5_create_qp_params *params) 2729 { 2730 struct ib_qp_init_attr *attr = params->attr; 2731 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2732 u32 uidx = params->uidx; 2733 void *dctc; 2734 2735 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2736 return -EOPNOTSUPP; 2737 2738 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2739 if (!qp->dct.in) 2740 return -ENOMEM; 2741 2742 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2743 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2744 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2745 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2746 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2747 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2748 MLX5_SET(dctc, dctc, user_index, uidx); 2749 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2750 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2751 2752 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2753 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2754 2755 if (rcqe_sz == 128) 2756 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2757 } 2758 2759 qp->state = IB_QPS_RESET; 2760 return 0; 2761 } 2762 2763 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2764 enum ib_qp_type *type) 2765 { 2766 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2767 goto out; 2768 2769 switch (attr->qp_type) { 2770 case IB_QPT_XRC_TGT: 2771 case IB_QPT_XRC_INI: 2772 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2773 goto out; 2774 fallthrough; 2775 case IB_QPT_RC: 2776 case IB_QPT_UC: 2777 case IB_QPT_SMI: 2778 case MLX5_IB_QPT_HW_GSI: 2779 case IB_QPT_DRIVER: 2780 case IB_QPT_GSI: 2781 case IB_QPT_RAW_PACKET: 2782 case IB_QPT_UD: 2783 case MLX5_IB_QPT_REG_UMR: 2784 break; 2785 default: 2786 goto out; 2787 } 2788 2789 *type = attr->qp_type; 2790 return 0; 2791 2792 out: 2793 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2794 return -EOPNOTSUPP; 2795 } 2796 2797 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2798 struct ib_qp_init_attr *attr, 2799 struct ib_udata *udata) 2800 { 2801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2802 udata, struct mlx5_ib_ucontext, ibucontext); 2803 2804 if (!udata) { 2805 /* Kernel create_qp callers */ 2806 if (attr->rwq_ind_tbl) 2807 return -EOPNOTSUPP; 2808 2809 switch (attr->qp_type) { 2810 case IB_QPT_RAW_PACKET: 2811 case IB_QPT_DRIVER: 2812 return -EOPNOTSUPP; 2813 default: 2814 return 0; 2815 } 2816 } 2817 2818 /* Userspace create_qp callers */ 2819 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2820 mlx5_ib_dbg(dev, 2821 "Raw Packet QP is only supported for CQE version > 0\n"); 2822 return -EINVAL; 2823 } 2824 2825 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2826 mlx5_ib_dbg(dev, 2827 "Wrong QP type %d for the RWQ indirect table\n", 2828 attr->qp_type); 2829 return -EINVAL; 2830 } 2831 2832 /* 2833 * We don't need to see this warning, it means that kernel code 2834 * missing ib_pd. Placed here to catch developer's mistakes. 2835 */ 2836 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2837 "There is a missing PD pointer assignment\n"); 2838 return 0; 2839 } 2840 2841 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2842 bool cond, struct mlx5_ib_qp *qp) 2843 { 2844 if (!(*flags & flag)) 2845 return; 2846 2847 if (cond) { 2848 qp->flags_en |= flag; 2849 *flags &= ~flag; 2850 return; 2851 } 2852 2853 switch (flag) { 2854 case MLX5_QP_FLAG_SCATTER_CQE: 2855 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2856 /* 2857 * We don't return error if these flags were provided, 2858 * and mlx5 doesn't have right capability. 2859 */ 2860 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2861 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2862 return; 2863 default: 2864 break; 2865 } 2866 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2867 } 2868 2869 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2870 void *ucmd, struct ib_qp_init_attr *attr) 2871 { 2872 struct mlx5_core_dev *mdev = dev->mdev; 2873 bool cond; 2874 int flags; 2875 2876 if (attr->rwq_ind_tbl) 2877 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2878 else 2879 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2880 2881 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2882 case MLX5_QP_FLAG_TYPE_DCI: 2883 qp->type = MLX5_IB_QPT_DCI; 2884 break; 2885 case MLX5_QP_FLAG_TYPE_DCT: 2886 qp->type = MLX5_IB_QPT_DCT; 2887 break; 2888 default: 2889 if (qp->type != IB_QPT_DRIVER) 2890 break; 2891 /* 2892 * It is IB_QPT_DRIVER and or no subtype or 2893 * wrong subtype were provided. 2894 */ 2895 return -EINVAL; 2896 } 2897 2898 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2899 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2900 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM, 2901 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels), 2902 qp); 2903 2904 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2905 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2906 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2907 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2908 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2909 2910 if (qp->type == IB_QPT_RAW_PACKET) { 2911 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2912 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2913 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2914 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2915 cond, qp); 2916 process_vendor_flag(dev, &flags, 2917 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2918 qp); 2919 process_vendor_flag(dev, &flags, 2920 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2921 qp); 2922 } 2923 2924 if (qp->type == IB_QPT_RC) 2925 process_vendor_flag(dev, &flags, 2926 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2927 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2928 2929 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2930 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2931 2932 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2933 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2934 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2935 if (attr->rwq_ind_tbl && cond) { 2936 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2937 cond); 2938 return -EINVAL; 2939 } 2940 2941 if (flags) 2942 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2943 2944 return (flags) ? -EINVAL : 0; 2945 } 2946 2947 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2948 bool cond, struct mlx5_ib_qp *qp) 2949 { 2950 if (!(*flags & flag)) 2951 return; 2952 2953 if (cond) { 2954 qp->flags |= flag; 2955 *flags &= ~flag; 2956 return; 2957 } 2958 2959 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2960 /* 2961 * Special case, if condition didn't meet, it won't be error, 2962 * just different in-kernel flow. 2963 */ 2964 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2965 return; 2966 } 2967 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2968 } 2969 2970 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2971 struct ib_qp_init_attr *attr) 2972 { 2973 enum ib_qp_type qp_type = qp->type; 2974 struct mlx5_core_dev *mdev = dev->mdev; 2975 int create_flags = attr->create_flags; 2976 bool cond; 2977 2978 if (qp_type == MLX5_IB_QPT_DCT) 2979 return (create_flags) ? -EINVAL : 0; 2980 2981 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2982 return (create_flags) ? -EINVAL : 0; 2983 2984 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2985 mlx5_get_flow_namespace(dev->mdev, 2986 MLX5_FLOW_NAMESPACE_BYPASS), 2987 qp); 2988 process_create_flag(dev, &create_flags, 2989 IB_QP_CREATE_INTEGRITY_EN, 2990 MLX5_CAP_GEN(mdev, sho), qp); 2991 process_create_flag(dev, &create_flags, 2992 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2993 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2994 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2995 MLX5_CAP_GEN(mdev, cd), qp); 2996 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2997 MLX5_CAP_GEN(mdev, cd), qp); 2998 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2999 MLX5_CAP_GEN(mdev, cd), qp); 3000 3001 if (qp_type == IB_QPT_UD) { 3002 process_create_flag(dev, &create_flags, 3003 IB_QP_CREATE_IPOIB_UD_LSO, 3004 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 3005 qp); 3006 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 3007 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 3008 cond, qp); 3009 } 3010 3011 if (qp_type == IB_QPT_RAW_PACKET) { 3012 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3013 MLX5_CAP_ETH(mdev, scatter_fcs); 3014 process_create_flag(dev, &create_flags, 3015 IB_QP_CREATE_SCATTER_FCS, cond, qp); 3016 3017 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3018 MLX5_CAP_ETH(mdev, vlan_cap); 3019 process_create_flag(dev, &create_flags, 3020 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 3021 } 3022 3023 process_create_flag(dev, &create_flags, 3024 IB_QP_CREATE_PCI_WRITE_END_PADDING, 3025 MLX5_CAP_GEN(mdev, end_pad), qp); 3026 3027 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 3028 qp_type != MLX5_IB_QPT_REG_UMR, qp); 3029 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 3030 true, qp); 3031 3032 if (create_flags) { 3033 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 3034 create_flags); 3035 return -EOPNOTSUPP; 3036 } 3037 return 0; 3038 } 3039 3040 static int process_udata_size(struct mlx5_ib_dev *dev, 3041 struct mlx5_create_qp_params *params) 3042 { 3043 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 3044 struct ib_udata *udata = params->udata; 3045 size_t outlen = udata->outlen; 3046 size_t inlen = udata->inlen; 3047 3048 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 3049 params->ucmd_size = ucmd; 3050 if (!params->is_rss_raw) { 3051 /* User has old rdma-core, which doesn't support ECE */ 3052 size_t min_inlen = 3053 offsetof(struct mlx5_ib_create_qp, ece_options); 3054 3055 /* 3056 * We will check in check_ucmd_data() that user 3057 * cleared everything after inlen. 3058 */ 3059 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 3060 goto out; 3061 } 3062 3063 /* RSS RAW QP */ 3064 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 3065 return -EINVAL; 3066 3067 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 3068 return -EINVAL; 3069 3070 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 3071 params->ucmd_size = ucmd; 3072 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 3073 return -EINVAL; 3074 3075 params->inlen = min(ucmd, inlen); 3076 out: 3077 if (!params->inlen) 3078 mlx5_ib_dbg(dev, "udata is too small\n"); 3079 3080 return (params->inlen) ? 0 : -EINVAL; 3081 } 3082 3083 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 3084 struct mlx5_ib_qp *qp, 3085 struct mlx5_create_qp_params *params) 3086 { 3087 int err; 3088 3089 if (params->is_rss_raw) { 3090 err = create_rss_raw_qp_tir(dev, pd, qp, params); 3091 goto out; 3092 } 3093 3094 switch (qp->type) { 3095 case MLX5_IB_QPT_DCT: 3096 err = create_dct(dev, pd, qp, params); 3097 rdma_restrack_no_track(&qp->ibqp.res); 3098 break; 3099 case MLX5_IB_QPT_DCI: 3100 err = create_dci(dev, pd, qp, params); 3101 break; 3102 case IB_QPT_XRC_TGT: 3103 err = create_xrc_tgt_qp(dev, qp, params); 3104 break; 3105 case IB_QPT_GSI: 3106 err = mlx5_ib_create_gsi(pd, qp, params->attr); 3107 break; 3108 case MLX5_IB_QPT_HW_GSI: 3109 case MLX5_IB_QPT_REG_UMR: 3110 rdma_restrack_no_track(&qp->ibqp.res); 3111 fallthrough; 3112 default: 3113 if (params->udata) 3114 err = create_user_qp(dev, pd, qp, params); 3115 else 3116 err = create_kernel_qp(dev, pd, qp, params); 3117 } 3118 3119 out: 3120 if (err) { 3121 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 3122 return err; 3123 } 3124 3125 if (is_qp0(qp->type)) 3126 qp->ibqp.qp_num = 0; 3127 else if (is_qp1(qp->type)) 3128 qp->ibqp.qp_num = 1; 3129 else 3130 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 3131 3132 mlx5_ib_dbg(dev, 3133 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 3134 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 3135 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 3136 -1, 3137 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 3138 -1, 3139 params->resp.ece_options); 3140 3141 return 0; 3142 } 3143 3144 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3145 struct ib_qp_init_attr *attr) 3146 { 3147 int ret = 0; 3148 3149 switch (qp->type) { 3150 case MLX5_IB_QPT_DCT: 3151 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 3152 break; 3153 case MLX5_IB_QPT_DCI: 3154 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 3155 -EINVAL : 3156 0; 3157 break; 3158 case IB_QPT_RAW_PACKET: 3159 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 if (ret) 3166 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 3167 3168 return ret; 3169 } 3170 3171 static int get_qp_uidx(struct mlx5_ib_qp *qp, 3172 struct mlx5_create_qp_params *params) 3173 { 3174 struct mlx5_ib_create_qp *ucmd = params->ucmd; 3175 struct ib_udata *udata = params->udata; 3176 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3177 udata, struct mlx5_ib_ucontext, ibucontext); 3178 3179 if (params->is_rss_raw) 3180 return 0; 3181 3182 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 3183 } 3184 3185 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 3186 { 3187 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 3188 3189 if (mqp->state == IB_QPS_RTR) { 3190 int err; 3191 3192 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 3193 if (err) { 3194 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 3195 return err; 3196 } 3197 } 3198 3199 kfree(mqp->dct.in); 3200 return 0; 3201 } 3202 3203 static int check_ucmd_data(struct mlx5_ib_dev *dev, 3204 struct mlx5_create_qp_params *params) 3205 { 3206 struct ib_udata *udata = params->udata; 3207 size_t size, last; 3208 int ret; 3209 3210 if (params->is_rss_raw) 3211 /* 3212 * These QPs don't have "reserved" field in their 3213 * create_qp input struct, so their data is always valid. 3214 */ 3215 last = sizeof(struct mlx5_ib_create_qp_rss); 3216 else 3217 last = offsetof(struct mlx5_ib_create_qp, reserved); 3218 3219 if (udata->inlen <= last) 3220 return 0; 3221 3222 /* 3223 * User provides different create_qp structures based on the 3224 * flow and we need to know if he cleared memory after our 3225 * struct create_qp ends. 3226 */ 3227 size = udata->inlen - last; 3228 ret = ib_is_udata_cleared(params->udata, last, size); 3229 if (!ret) 3230 mlx5_ib_dbg( 3231 dev, 3232 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 3233 udata->inlen, params->ucmd_size, last, size); 3234 return ret ? 0 : -EINVAL; 3235 } 3236 3237 int mlx5_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr, 3238 struct ib_udata *udata) 3239 { 3240 struct mlx5_create_qp_params params = {}; 3241 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3242 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3243 struct ib_pd *pd = ibqp->pd; 3244 enum ib_qp_type type; 3245 int err; 3246 3247 err = check_qp_type(dev, attr, &type); 3248 if (err) 3249 return err; 3250 3251 err = check_valid_flow(dev, pd, attr, udata); 3252 if (err) 3253 return err; 3254 3255 params.udata = udata; 3256 params.uidx = MLX5_IB_DEFAULT_UIDX; 3257 params.attr = attr; 3258 params.is_rss_raw = !!attr->rwq_ind_tbl; 3259 3260 if (udata) { 3261 err = process_udata_size(dev, ¶ms); 3262 if (err) 3263 return err; 3264 3265 err = check_ucmd_data(dev, ¶ms); 3266 if (err) 3267 return err; 3268 3269 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3270 if (!params.ucmd) 3271 return -ENOMEM; 3272 3273 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3274 if (err) 3275 goto free_ucmd; 3276 } 3277 3278 mutex_init(&qp->mutex); 3279 qp->type = type; 3280 if (udata) { 3281 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3282 if (err) 3283 goto free_ucmd; 3284 3285 err = get_qp_uidx(qp, ¶ms); 3286 if (err) 3287 goto free_ucmd; 3288 } 3289 err = process_create_flags(dev, qp, attr); 3290 if (err) 3291 goto free_ucmd; 3292 3293 err = check_qp_attr(dev, qp, attr); 3294 if (err) 3295 goto free_ucmd; 3296 3297 err = create_qp(dev, pd, qp, ¶ms); 3298 if (err) 3299 goto free_ucmd; 3300 3301 kfree(params.ucmd); 3302 params.ucmd = NULL; 3303 3304 if (udata) 3305 /* 3306 * It is safe to copy response for all user create QP flows, 3307 * including MLX5_IB_QPT_DCT, which doesn't need it. 3308 * In that case, resp will be filled with zeros. 3309 */ 3310 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3311 if (err) 3312 goto destroy_qp; 3313 3314 return 0; 3315 3316 destroy_qp: 3317 switch (qp->type) { 3318 case MLX5_IB_QPT_DCT: 3319 mlx5_ib_destroy_dct(qp); 3320 break; 3321 case IB_QPT_GSI: 3322 mlx5_ib_destroy_gsi(qp); 3323 break; 3324 default: 3325 destroy_qp_common(dev, qp, udata); 3326 } 3327 3328 free_ucmd: 3329 kfree(params.ucmd); 3330 return err; 3331 } 3332 3333 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3334 { 3335 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3336 struct mlx5_ib_qp *mqp = to_mqp(qp); 3337 3338 if (mqp->type == IB_QPT_GSI) 3339 return mlx5_ib_destroy_gsi(mqp); 3340 3341 if (mqp->type == MLX5_IB_QPT_DCT) 3342 return mlx5_ib_destroy_dct(mqp); 3343 3344 destroy_qp_common(dev, mqp, udata); 3345 return 0; 3346 } 3347 3348 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3349 const struct ib_qp_attr *attr, int attr_mask, 3350 void *qpc) 3351 { 3352 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3353 u8 dest_rd_atomic; 3354 u32 access_flags; 3355 3356 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3357 dest_rd_atomic = attr->max_dest_rd_atomic; 3358 else 3359 dest_rd_atomic = qp->trans_qp.resp_depth; 3360 3361 if (attr_mask & IB_QP_ACCESS_FLAGS) 3362 access_flags = attr->qp_access_flags; 3363 else 3364 access_flags = qp->trans_qp.atomic_rd_en; 3365 3366 if (!dest_rd_atomic) 3367 access_flags &= IB_ACCESS_REMOTE_WRITE; 3368 3369 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3370 3371 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3372 int atomic_mode; 3373 3374 atomic_mode = get_atomic_mode(dev, qp->type); 3375 if (atomic_mode < 0) 3376 return -EOPNOTSUPP; 3377 3378 MLX5_SET(qpc, qpc, rae, 1); 3379 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3380 } 3381 3382 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3383 return 0; 3384 } 3385 3386 enum { 3387 MLX5_PATH_FLAG_FL = 1 << 0, 3388 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3389 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3390 }; 3391 3392 static int mlx5_to_ib_rate_map(u8 rate) 3393 { 3394 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3395 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3396 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3397 IB_RATE_400_GBPS }; 3398 3399 if (rate < ARRAY_SIZE(rates)) 3400 return rates[rate]; 3401 3402 return rate - MLX5_STAT_RATE_OFFSET; 3403 } 3404 3405 static int ib_to_mlx5_rate_map(u8 rate) 3406 { 3407 switch (rate) { 3408 case IB_RATE_PORT_CURRENT: 3409 return 0; 3410 case IB_RATE_56_GBPS: 3411 return 1; 3412 case IB_RATE_25_GBPS: 3413 return 2; 3414 case IB_RATE_100_GBPS: 3415 return 3; 3416 case IB_RATE_200_GBPS: 3417 return 4; 3418 case IB_RATE_50_GBPS: 3419 return 5; 3420 case IB_RATE_400_GBPS: 3421 return 6; 3422 default: 3423 return rate + MLX5_STAT_RATE_OFFSET; 3424 } 3425 3426 return 0; 3427 } 3428 3429 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3430 { 3431 u32 stat_rate_support; 3432 3433 if (rate == IB_RATE_PORT_CURRENT) 3434 return 0; 3435 3436 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3437 return -EINVAL; 3438 3439 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3440 while (rate != IB_RATE_PORT_CURRENT && 3441 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3442 --rate; 3443 3444 return ib_to_mlx5_rate_map(rate); 3445 } 3446 3447 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3448 struct mlx5_ib_sq *sq, u8 sl, 3449 struct ib_pd *pd) 3450 { 3451 void *in; 3452 void *tisc; 3453 int inlen; 3454 int err; 3455 3456 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3457 in = kvzalloc(inlen, GFP_KERNEL); 3458 if (!in) 3459 return -ENOMEM; 3460 3461 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3462 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3463 3464 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3465 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3466 3467 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3468 3469 kvfree(in); 3470 3471 return err; 3472 } 3473 3474 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3475 struct mlx5_ib_sq *sq, u8 tx_affinity, 3476 struct ib_pd *pd) 3477 { 3478 void *in; 3479 void *tisc; 3480 int inlen; 3481 int err; 3482 3483 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3484 in = kvzalloc(inlen, GFP_KERNEL); 3485 if (!in) 3486 return -ENOMEM; 3487 3488 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3489 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3490 3491 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3492 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3493 3494 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3495 3496 kvfree(in); 3497 3498 return err; 3499 } 3500 3501 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3502 u32 lqpn, u32 rqpn) 3503 3504 { 3505 u32 fl = ah->grh.flow_label; 3506 3507 if (!fl) 3508 fl = rdma_calc_flow_label(lqpn, rqpn); 3509 3510 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3511 } 3512 3513 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3514 const struct rdma_ah_attr *ah, void *path, u8 port, 3515 int attr_mask, u32 path_flags, 3516 const struct ib_qp_attr *attr, bool alt) 3517 { 3518 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3519 int err; 3520 enum ib_gid_type gid_type; 3521 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3522 u8 sl = rdma_ah_get_sl(ah); 3523 3524 if (attr_mask & IB_QP_PKEY_INDEX) 3525 MLX5_SET(ads, path, pkey_index, 3526 alt ? attr->alt_pkey_index : attr->pkey_index); 3527 3528 if (ah_flags & IB_AH_GRH) { 3529 const struct ib_port_immutable *immutable; 3530 3531 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3532 if (grh->sgid_index >= immutable->gid_tbl_len) { 3533 pr_err("sgid_index (%u) too large. max is %d\n", 3534 grh->sgid_index, 3535 immutable->gid_tbl_len); 3536 return -EINVAL; 3537 } 3538 } 3539 3540 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3541 if (!(ah_flags & IB_AH_GRH)) 3542 return -EINVAL; 3543 3544 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3545 ah->roce.dmac); 3546 if ((qp->type == IB_QPT_RC || 3547 qp->type == IB_QPT_UC || 3548 qp->type == IB_QPT_XRC_INI || 3549 qp->type == IB_QPT_XRC_TGT) && 3550 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3551 (attr_mask & IB_QP_DEST_QPN)) 3552 mlx5_set_path_udp_sport(path, ah, 3553 qp->ibqp.qp_num, 3554 attr->dest_qp_num); 3555 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3556 gid_type = ah->grh.sgid_attr->gid_type; 3557 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3558 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3559 } else { 3560 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3561 MLX5_SET(ads, path, free_ar, 3562 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3563 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3564 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3565 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3566 MLX5_SET(ads, path, sl, sl); 3567 } 3568 3569 if (ah_flags & IB_AH_GRH) { 3570 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3571 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3572 MLX5_SET(ads, path, tclass, grh->traffic_class); 3573 MLX5_SET(ads, path, flow_label, grh->flow_label); 3574 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3575 sizeof(grh->dgid.raw)); 3576 } 3577 3578 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3579 if (err < 0) 3580 return err; 3581 MLX5_SET(ads, path, stat_rate, err); 3582 MLX5_SET(ads, path, vhca_port_num, port); 3583 3584 if (attr_mask & IB_QP_TIMEOUT) 3585 MLX5_SET(ads, path, ack_timeout, 3586 alt ? attr->alt_timeout : attr->timeout); 3587 3588 if ((qp->type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3589 return modify_raw_packet_eth_prio(dev->mdev, 3590 &qp->raw_packet_qp.sq, 3591 sl & 0xf, qp->ibqp.pd); 3592 3593 return 0; 3594 } 3595 3596 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3597 [MLX5_QP_STATE_INIT] = { 3598 [MLX5_QP_STATE_INIT] = { 3599 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3600 MLX5_QP_OPTPAR_RAE | 3601 MLX5_QP_OPTPAR_RWE | 3602 MLX5_QP_OPTPAR_PKEY_INDEX | 3603 MLX5_QP_OPTPAR_PRI_PORT | 3604 MLX5_QP_OPTPAR_LAG_TX_AFF, 3605 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3606 MLX5_QP_OPTPAR_PKEY_INDEX | 3607 MLX5_QP_OPTPAR_PRI_PORT | 3608 MLX5_QP_OPTPAR_LAG_TX_AFF, 3609 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3610 MLX5_QP_OPTPAR_Q_KEY | 3611 MLX5_QP_OPTPAR_PRI_PORT, 3612 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3613 MLX5_QP_OPTPAR_RAE | 3614 MLX5_QP_OPTPAR_RWE | 3615 MLX5_QP_OPTPAR_PKEY_INDEX | 3616 MLX5_QP_OPTPAR_PRI_PORT | 3617 MLX5_QP_OPTPAR_LAG_TX_AFF, 3618 }, 3619 [MLX5_QP_STATE_RTR] = { 3620 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3621 MLX5_QP_OPTPAR_RRE | 3622 MLX5_QP_OPTPAR_RAE | 3623 MLX5_QP_OPTPAR_RWE | 3624 MLX5_QP_OPTPAR_PKEY_INDEX | 3625 MLX5_QP_OPTPAR_LAG_TX_AFF, 3626 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3627 MLX5_QP_OPTPAR_RWE | 3628 MLX5_QP_OPTPAR_PKEY_INDEX | 3629 MLX5_QP_OPTPAR_LAG_TX_AFF, 3630 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3631 MLX5_QP_OPTPAR_Q_KEY, 3632 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3633 MLX5_QP_OPTPAR_Q_KEY, 3634 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3635 MLX5_QP_OPTPAR_RRE | 3636 MLX5_QP_OPTPAR_RAE | 3637 MLX5_QP_OPTPAR_RWE | 3638 MLX5_QP_OPTPAR_PKEY_INDEX | 3639 MLX5_QP_OPTPAR_LAG_TX_AFF, 3640 }, 3641 }, 3642 [MLX5_QP_STATE_RTR] = { 3643 [MLX5_QP_STATE_RTS] = { 3644 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3645 MLX5_QP_OPTPAR_RRE | 3646 MLX5_QP_OPTPAR_RAE | 3647 MLX5_QP_OPTPAR_RWE | 3648 MLX5_QP_OPTPAR_PM_STATE | 3649 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3650 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3651 MLX5_QP_OPTPAR_RWE | 3652 MLX5_QP_OPTPAR_PM_STATE, 3653 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3654 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3655 MLX5_QP_OPTPAR_RRE | 3656 MLX5_QP_OPTPAR_RAE | 3657 MLX5_QP_OPTPAR_RWE | 3658 MLX5_QP_OPTPAR_PM_STATE | 3659 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3660 }, 3661 }, 3662 [MLX5_QP_STATE_RTS] = { 3663 [MLX5_QP_STATE_RTS] = { 3664 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3665 MLX5_QP_OPTPAR_RAE | 3666 MLX5_QP_OPTPAR_RWE | 3667 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3668 MLX5_QP_OPTPAR_PM_STATE | 3669 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3670 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3671 MLX5_QP_OPTPAR_PM_STATE | 3672 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3673 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3674 MLX5_QP_OPTPAR_SRQN | 3675 MLX5_QP_OPTPAR_CQN_RCV, 3676 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3677 MLX5_QP_OPTPAR_RAE | 3678 MLX5_QP_OPTPAR_RWE | 3679 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3680 MLX5_QP_OPTPAR_PM_STATE | 3681 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3682 }, 3683 }, 3684 [MLX5_QP_STATE_SQER] = { 3685 [MLX5_QP_STATE_RTS] = { 3686 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3687 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3688 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3689 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3690 MLX5_QP_OPTPAR_RWE | 3691 MLX5_QP_OPTPAR_RAE | 3692 MLX5_QP_OPTPAR_RRE, 3693 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3694 MLX5_QP_OPTPAR_RWE | 3695 MLX5_QP_OPTPAR_RAE | 3696 MLX5_QP_OPTPAR_RRE, 3697 }, 3698 }, 3699 [MLX5_QP_STATE_SQD] = { 3700 [MLX5_QP_STATE_RTS] = { 3701 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3702 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3703 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3704 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3705 MLX5_QP_OPTPAR_RWE | 3706 MLX5_QP_OPTPAR_RAE | 3707 MLX5_QP_OPTPAR_RRE, 3708 }, 3709 }, 3710 }; 3711 3712 static int ib_nr_to_mlx5_nr(int ib_mask) 3713 { 3714 switch (ib_mask) { 3715 case IB_QP_STATE: 3716 return 0; 3717 case IB_QP_CUR_STATE: 3718 return 0; 3719 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3720 return 0; 3721 case IB_QP_ACCESS_FLAGS: 3722 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3723 MLX5_QP_OPTPAR_RAE; 3724 case IB_QP_PKEY_INDEX: 3725 return MLX5_QP_OPTPAR_PKEY_INDEX; 3726 case IB_QP_PORT: 3727 return MLX5_QP_OPTPAR_PRI_PORT; 3728 case IB_QP_QKEY: 3729 return MLX5_QP_OPTPAR_Q_KEY; 3730 case IB_QP_AV: 3731 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3732 MLX5_QP_OPTPAR_PRI_PORT; 3733 case IB_QP_PATH_MTU: 3734 return 0; 3735 case IB_QP_TIMEOUT: 3736 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3737 case IB_QP_RETRY_CNT: 3738 return MLX5_QP_OPTPAR_RETRY_COUNT; 3739 case IB_QP_RNR_RETRY: 3740 return MLX5_QP_OPTPAR_RNR_RETRY; 3741 case IB_QP_RQ_PSN: 3742 return 0; 3743 case IB_QP_MAX_QP_RD_ATOMIC: 3744 return MLX5_QP_OPTPAR_SRA_MAX; 3745 case IB_QP_ALT_PATH: 3746 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3747 case IB_QP_MIN_RNR_TIMER: 3748 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3749 case IB_QP_SQ_PSN: 3750 return 0; 3751 case IB_QP_MAX_DEST_RD_ATOMIC: 3752 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3753 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3754 case IB_QP_PATH_MIG_STATE: 3755 return MLX5_QP_OPTPAR_PM_STATE; 3756 case IB_QP_CAP: 3757 return 0; 3758 case IB_QP_DEST_QPN: 3759 return 0; 3760 } 3761 return 0; 3762 } 3763 3764 static int ib_mask_to_mlx5_opt(int ib_mask) 3765 { 3766 int result = 0; 3767 int i; 3768 3769 for (i = 0; i < 8 * sizeof(int); i++) { 3770 if ((1 << i) & ib_mask) 3771 result |= ib_nr_to_mlx5_nr(1 << i); 3772 } 3773 3774 return result; 3775 } 3776 3777 static int modify_raw_packet_qp_rq( 3778 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3779 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3780 { 3781 void *in; 3782 void *rqc; 3783 int inlen; 3784 int err; 3785 3786 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3787 in = kvzalloc(inlen, GFP_KERNEL); 3788 if (!in) 3789 return -ENOMEM; 3790 3791 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3792 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3793 3794 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3795 MLX5_SET(rqc, rqc, state, new_state); 3796 3797 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3798 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3799 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3800 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3801 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3802 } else 3803 dev_info_once( 3804 &dev->ib_dev.dev, 3805 "RAW PACKET QP counters are not supported on current FW\n"); 3806 } 3807 3808 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3809 if (err) 3810 goto out; 3811 3812 rq->state = new_state; 3813 3814 out: 3815 kvfree(in); 3816 return err; 3817 } 3818 3819 static int modify_raw_packet_qp_sq( 3820 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3821 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3822 { 3823 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3824 struct mlx5_rate_limit old_rl = ibqp->rl; 3825 struct mlx5_rate_limit new_rl = old_rl; 3826 bool new_rate_added = false; 3827 u16 rl_index = 0; 3828 void *in; 3829 void *sqc; 3830 int inlen; 3831 int err; 3832 3833 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3834 in = kvzalloc(inlen, GFP_KERNEL); 3835 if (!in) 3836 return -ENOMEM; 3837 3838 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3839 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3840 3841 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3842 MLX5_SET(sqc, sqc, state, new_state); 3843 3844 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3845 if (new_state != MLX5_SQC_STATE_RDY) 3846 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3847 __func__); 3848 else 3849 new_rl = raw_qp_param->rl; 3850 } 3851 3852 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3853 if (new_rl.rate) { 3854 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3855 if (err) { 3856 pr_err("Failed configuring rate limit(err %d): \ 3857 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3858 err, new_rl.rate, new_rl.max_burst_sz, 3859 new_rl.typical_pkt_sz); 3860 3861 goto out; 3862 } 3863 new_rate_added = true; 3864 } 3865 3866 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3867 /* index 0 means no limit */ 3868 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3869 } 3870 3871 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3872 if (err) { 3873 /* Remove new rate from table if failed */ 3874 if (new_rate_added) 3875 mlx5_rl_remove_rate(dev, &new_rl); 3876 goto out; 3877 } 3878 3879 /* Only remove the old rate after new rate was set */ 3880 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3881 (new_state != MLX5_SQC_STATE_RDY)) { 3882 mlx5_rl_remove_rate(dev, &old_rl); 3883 if (new_state != MLX5_SQC_STATE_RDY) 3884 memset(&new_rl, 0, sizeof(new_rl)); 3885 } 3886 3887 ibqp->rl = new_rl; 3888 sq->state = new_state; 3889 3890 out: 3891 kvfree(in); 3892 return err; 3893 } 3894 3895 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3896 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3897 u8 tx_affinity) 3898 { 3899 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3900 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3901 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3902 int modify_rq = !!qp->rq.wqe_cnt; 3903 int modify_sq = !!qp->sq.wqe_cnt; 3904 int rq_state; 3905 int sq_state; 3906 int err; 3907 3908 switch (raw_qp_param->operation) { 3909 case MLX5_CMD_OP_RST2INIT_QP: 3910 rq_state = MLX5_RQC_STATE_RDY; 3911 sq_state = MLX5_SQC_STATE_RST; 3912 break; 3913 case MLX5_CMD_OP_2ERR_QP: 3914 rq_state = MLX5_RQC_STATE_ERR; 3915 sq_state = MLX5_SQC_STATE_ERR; 3916 break; 3917 case MLX5_CMD_OP_2RST_QP: 3918 rq_state = MLX5_RQC_STATE_RST; 3919 sq_state = MLX5_SQC_STATE_RST; 3920 break; 3921 case MLX5_CMD_OP_RTR2RTS_QP: 3922 case MLX5_CMD_OP_RTS2RTS_QP: 3923 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3924 return -EINVAL; 3925 3926 modify_rq = 0; 3927 sq_state = MLX5_SQC_STATE_RDY; 3928 break; 3929 case MLX5_CMD_OP_INIT2INIT_QP: 3930 case MLX5_CMD_OP_INIT2RTR_QP: 3931 if (raw_qp_param->set_mask) 3932 return -EINVAL; 3933 else 3934 return 0; 3935 default: 3936 WARN_ON(1); 3937 return -EINVAL; 3938 } 3939 3940 if (modify_rq) { 3941 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3942 qp->ibqp.pd); 3943 if (err) 3944 return err; 3945 } 3946 3947 if (modify_sq) { 3948 struct mlx5_flow_handle *flow_rule; 3949 3950 if (tx_affinity) { 3951 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3952 tx_affinity, 3953 qp->ibqp.pd); 3954 if (err) 3955 return err; 3956 } 3957 3958 flow_rule = create_flow_rule_vport_sq(dev, sq, 3959 raw_qp_param->port); 3960 if (IS_ERR(flow_rule)) 3961 return PTR_ERR(flow_rule); 3962 3963 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3964 raw_qp_param, qp->ibqp.pd); 3965 if (err) { 3966 if (flow_rule) 3967 mlx5_del_flow_rules(flow_rule); 3968 return err; 3969 } 3970 3971 if (flow_rule) { 3972 destroy_flow_rule_vport_sq(sq); 3973 sq->flow_rule = flow_rule; 3974 } 3975 3976 return err; 3977 } 3978 3979 return 0; 3980 } 3981 3982 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3983 struct ib_udata *udata) 3984 { 3985 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3986 udata, struct mlx5_ib_ucontext, ibucontext); 3987 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3988 atomic_t *tx_port_affinity; 3989 3990 if (ucontext) 3991 tx_port_affinity = &ucontext->tx_port_affinity; 3992 else 3993 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3994 3995 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3996 (dev->lag_active ? dev->lag_ports : MLX5_CAP_GEN(dev->mdev, num_lag_ports)) + 1; 3997 } 3998 3999 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 4000 { 4001 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 4002 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 4003 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 4004 (qp->type == MLX5_IB_QPT_DCI)) 4005 return true; 4006 return false; 4007 } 4008 4009 static unsigned int get_tx_affinity(struct ib_qp *qp, 4010 const struct ib_qp_attr *attr, 4011 int attr_mask, u8 init, 4012 struct ib_udata *udata) 4013 { 4014 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 4015 udata, struct mlx5_ib_ucontext, ibucontext); 4016 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4017 struct mlx5_ib_qp *mqp = to_mqp(qp); 4018 struct mlx5_ib_qp_base *qp_base; 4019 unsigned int tx_affinity; 4020 4021 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 4022 qp_supports_affinity(mqp))) 4023 return 0; 4024 4025 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4026 tx_affinity = mqp->gsi_lag_port; 4027 else if (init) 4028 tx_affinity = get_tx_affinity_rr(dev, udata); 4029 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 4030 tx_affinity = 4031 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 4032 else 4033 return 0; 4034 4035 qp_base = &mqp->trans_qp.base; 4036 if (ucontext) 4037 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 4038 tx_affinity, qp_base->mqp.qpn, ucontext); 4039 else 4040 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 4041 tx_affinity, qp_base->mqp.qpn); 4042 return tx_affinity; 4043 } 4044 4045 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 4046 struct rdma_counter *counter) 4047 { 4048 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4049 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 4050 struct mlx5_ib_qp *mqp = to_mqp(qp); 4051 struct mlx5_ib_qp_base *base; 4052 u32 set_id; 4053 u32 *qpc; 4054 4055 if (counter) 4056 set_id = counter->id; 4057 else 4058 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 4059 4060 base = &mqp->trans_qp.base; 4061 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 4062 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 4063 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 4064 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 4065 MLX5_QP_OPTPAR_COUNTER_SET_ID); 4066 4067 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 4068 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4069 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 4070 } 4071 4072 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 4073 const struct ib_qp_attr *attr, int attr_mask, 4074 enum ib_qp_state cur_state, 4075 enum ib_qp_state new_state, 4076 const struct mlx5_ib_modify_qp *ucmd, 4077 struct mlx5_ib_modify_qp_resp *resp, 4078 struct ib_udata *udata) 4079 { 4080 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 4081 [MLX5_QP_STATE_RST] = { 4082 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4083 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4084 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 4085 }, 4086 [MLX5_QP_STATE_INIT] = { 4087 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4088 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4089 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 4090 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 4091 }, 4092 [MLX5_QP_STATE_RTR] = { 4093 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4094 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4095 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 4096 }, 4097 [MLX5_QP_STATE_RTS] = { 4098 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4099 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4100 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 4101 }, 4102 [MLX5_QP_STATE_SQD] = { 4103 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4104 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4105 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD_RTS_QP, 4106 }, 4107 [MLX5_QP_STATE_SQER] = { 4108 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4109 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4110 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 4111 }, 4112 [MLX5_QP_STATE_ERR] = { 4113 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4114 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4115 } 4116 }; 4117 4118 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4119 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4120 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 4121 struct mlx5_ib_cq *send_cq, *recv_cq; 4122 struct mlx5_ib_pd *pd; 4123 enum mlx5_qp_state mlx5_cur, mlx5_new; 4124 void *qpc, *pri_path, *alt_path; 4125 enum mlx5_qp_optpar optpar = 0; 4126 u32 set_id = 0; 4127 int mlx5_st; 4128 int err; 4129 u16 op; 4130 u8 tx_affinity = 0; 4131 4132 mlx5_st = to_mlx5_st(qp->type); 4133 if (mlx5_st < 0) 4134 return -EINVAL; 4135 4136 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 4137 if (!qpc) 4138 return -ENOMEM; 4139 4140 pd = to_mpd(qp->ibqp.pd); 4141 MLX5_SET(qpc, qpc, st, mlx5_st); 4142 4143 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 4144 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4145 } else { 4146 switch (attr->path_mig_state) { 4147 case IB_MIG_MIGRATED: 4148 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4149 break; 4150 case IB_MIG_REARM: 4151 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 4152 break; 4153 case IB_MIG_ARMED: 4154 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 4155 break; 4156 } 4157 } 4158 4159 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 4160 cur_state == IB_QPS_RESET && 4161 new_state == IB_QPS_INIT, udata); 4162 4163 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 4164 if (tx_affinity && new_state == IB_QPS_RTR && 4165 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 4166 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 4167 4168 if (is_sqp(qp->type)) { 4169 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 4170 MLX5_SET(qpc, qpc, log_msg_max, 8); 4171 } else if ((qp->type == IB_QPT_UD && 4172 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 4173 qp->type == MLX5_IB_QPT_REG_UMR) { 4174 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 4175 MLX5_SET(qpc, qpc, log_msg_max, 12); 4176 } else if (attr_mask & IB_QP_PATH_MTU) { 4177 if (attr->path_mtu < IB_MTU_256 || 4178 attr->path_mtu > IB_MTU_4096) { 4179 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 4180 err = -EINVAL; 4181 goto out; 4182 } 4183 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 4184 MLX5_SET(qpc, qpc, log_msg_max, 4185 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 4186 } 4187 4188 if (attr_mask & IB_QP_DEST_QPN) 4189 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 4190 4191 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4192 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4193 4194 if (attr_mask & IB_QP_PKEY_INDEX) 4195 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 4196 4197 /* todo implement counter_index functionality */ 4198 4199 if (is_sqp(qp->type)) 4200 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 4201 4202 if (attr_mask & IB_QP_PORT) 4203 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 4204 4205 if (attr_mask & IB_QP_AV) { 4206 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 4207 attr_mask & IB_QP_PORT ? attr->port_num : 4208 qp->port, 4209 attr_mask, 0, attr, false); 4210 if (err) 4211 goto out; 4212 } 4213 4214 if (attr_mask & IB_QP_TIMEOUT) 4215 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 4216 4217 if (attr_mask & IB_QP_ALT_PATH) { 4218 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 4219 attr->alt_port_num, 4220 attr_mask | IB_QP_PKEY_INDEX | 4221 IB_QP_TIMEOUT, 4222 0, attr, true); 4223 if (err) 4224 goto out; 4225 } 4226 4227 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 4228 &send_cq, &recv_cq); 4229 4230 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 4231 if (send_cq) 4232 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 4233 if (recv_cq) 4234 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 4235 4236 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 4237 4238 if (attr_mask & IB_QP_RNR_RETRY) 4239 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 4240 4241 if (attr_mask & IB_QP_RETRY_CNT) 4242 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 4243 4244 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 4245 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 4246 4247 if (attr_mask & IB_QP_SQ_PSN) 4248 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 4249 4250 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 4251 MLX5_SET(qpc, qpc, log_rra_max, 4252 ilog2(attr->max_dest_rd_atomic)); 4253 4254 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4255 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4256 if (err) 4257 goto out; 4258 } 4259 4260 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4261 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4262 4263 if (attr_mask & IB_QP_RQ_PSN) 4264 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4265 4266 if (attr_mask & IB_QP_QKEY) 4267 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4268 4269 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4270 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4271 4272 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4273 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4274 qp->port) - 1; 4275 4276 /* Underlay port should be used - index 0 function per port */ 4277 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4278 port_num = 0; 4279 4280 if (ibqp->counter) 4281 set_id = ibqp->counter->id; 4282 else 4283 set_id = mlx5_ib_get_counters_id(dev, port_num); 4284 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4285 } 4286 4287 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4288 MLX5_SET(qpc, qpc, rlky, 1); 4289 4290 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4291 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4292 4293 mlx5_cur = to_mlx5_state(cur_state); 4294 mlx5_new = to_mlx5_state(new_state); 4295 4296 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4297 !optab[mlx5_cur][mlx5_new]) { 4298 err = -EINVAL; 4299 goto out; 4300 } 4301 4302 op = optab[mlx5_cur][mlx5_new]; 4303 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4304 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4305 4306 if (qp->type == IB_QPT_RAW_PACKET || 4307 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4308 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4309 4310 raw_qp_param.operation = op; 4311 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4312 raw_qp_param.rq_q_ctr_id = set_id; 4313 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4314 } 4315 4316 if (attr_mask & IB_QP_PORT) 4317 raw_qp_param.port = attr->port_num; 4318 4319 if (attr_mask & IB_QP_RATE_LIMIT) { 4320 raw_qp_param.rl.rate = attr->rate_limit; 4321 4322 if (ucmd->burst_info.max_burst_sz) { 4323 if (attr->rate_limit && 4324 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4325 raw_qp_param.rl.max_burst_sz = 4326 ucmd->burst_info.max_burst_sz; 4327 } else { 4328 err = -EINVAL; 4329 goto out; 4330 } 4331 } 4332 4333 if (ucmd->burst_info.typical_pkt_sz) { 4334 if (attr->rate_limit && 4335 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4336 raw_qp_param.rl.typical_pkt_sz = 4337 ucmd->burst_info.typical_pkt_sz; 4338 } else { 4339 err = -EINVAL; 4340 goto out; 4341 } 4342 } 4343 4344 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4345 } 4346 4347 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4348 } else { 4349 if (udata) { 4350 /* For the kernel flows, the resp will stay zero */ 4351 resp->ece_options = 4352 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4353 ucmd->ece_options : 0; 4354 resp->response_length = sizeof(*resp); 4355 } 4356 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4357 &resp->ece_options); 4358 } 4359 4360 if (err) 4361 goto out; 4362 4363 qp->state = new_state; 4364 4365 if (attr_mask & IB_QP_ACCESS_FLAGS) 4366 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4367 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4368 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4369 if (attr_mask & IB_QP_PORT) 4370 qp->port = attr->port_num; 4371 if (attr_mask & IB_QP_ALT_PATH) 4372 qp->trans_qp.alt_port = attr->alt_port_num; 4373 4374 /* 4375 * If we moved a kernel QP to RESET, clean up all old CQ 4376 * entries and reinitialize the QP. 4377 */ 4378 if (new_state == IB_QPS_RESET && 4379 !ibqp->uobject && qp->type != IB_QPT_XRC_TGT) { 4380 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4381 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4382 if (send_cq != recv_cq) 4383 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4384 4385 qp->rq.head = 0; 4386 qp->rq.tail = 0; 4387 qp->sq.head = 0; 4388 qp->sq.tail = 0; 4389 qp->sq.cur_post = 0; 4390 if (qp->sq.wqe_cnt) 4391 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4392 qp->sq.last_poll = 0; 4393 qp->db.db[MLX5_RCV_DBR] = 0; 4394 qp->db.db[MLX5_SND_DBR] = 0; 4395 } 4396 4397 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4398 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4399 if (!err) 4400 qp->counter_pending = 0; 4401 } 4402 4403 out: 4404 kfree(qpc); 4405 return err; 4406 } 4407 4408 static inline bool is_valid_mask(int mask, int req, int opt) 4409 { 4410 if ((mask & req) != req) 4411 return false; 4412 4413 if (mask & ~(req | opt)) 4414 return false; 4415 4416 return true; 4417 } 4418 4419 /* check valid transition for driver QP types 4420 * for now the only QP type that this function supports is DCI 4421 */ 4422 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4423 enum ib_qp_attr_mask attr_mask) 4424 { 4425 int req = IB_QP_STATE; 4426 int opt = 0; 4427 4428 if (new_state == IB_QPS_RESET) { 4429 return is_valid_mask(attr_mask, req, opt); 4430 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4431 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4432 return is_valid_mask(attr_mask, req, opt); 4433 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4434 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4435 return is_valid_mask(attr_mask, req, opt); 4436 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4437 req |= IB_QP_PATH_MTU; 4438 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4439 return is_valid_mask(attr_mask, req, opt); 4440 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4441 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4442 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4443 opt = IB_QP_MIN_RNR_TIMER; 4444 return is_valid_mask(attr_mask, req, opt); 4445 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4446 opt = IB_QP_MIN_RNR_TIMER; 4447 return is_valid_mask(attr_mask, req, opt); 4448 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4449 return is_valid_mask(attr_mask, req, opt); 4450 } 4451 return false; 4452 } 4453 4454 /* mlx5_ib_modify_dct: modify a DCT QP 4455 * valid transitions are: 4456 * RESET to INIT: must set access_flags, pkey_index and port 4457 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4458 * mtu, gid_index and hop_limit 4459 * Other transitions and attributes are illegal 4460 */ 4461 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4462 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4463 struct ib_udata *udata) 4464 { 4465 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4466 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4467 enum ib_qp_state cur_state, new_state; 4468 int required = IB_QP_STATE; 4469 void *dctc; 4470 int err; 4471 4472 if (!(attr_mask & IB_QP_STATE)) 4473 return -EINVAL; 4474 4475 cur_state = qp->state; 4476 new_state = attr->qp_state; 4477 4478 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4479 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4480 /* 4481 * DCT doesn't initialize QP till modify command is executed, 4482 * so we need to overwrite previously set ECE field if user 4483 * provided any value except zero, which means not set/not 4484 * valid. 4485 */ 4486 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4487 4488 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4489 u16 set_id; 4490 4491 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4492 if (!is_valid_mask(attr_mask, required, 0)) 4493 return -EINVAL; 4494 4495 if (attr->port_num == 0 || 4496 attr->port_num > dev->num_ports) { 4497 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4498 attr->port_num, dev->num_ports); 4499 return -EINVAL; 4500 } 4501 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4502 MLX5_SET(dctc, dctc, rre, 1); 4503 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4504 MLX5_SET(dctc, dctc, rwe, 1); 4505 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4506 int atomic_mode; 4507 4508 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4509 if (atomic_mode < 0) 4510 return -EOPNOTSUPP; 4511 4512 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4513 MLX5_SET(dctc, dctc, rae, 1); 4514 } 4515 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4516 if (mlx5_lag_is_active(dev->mdev)) 4517 MLX5_SET(dctc, dctc, port, 4518 get_tx_affinity_rr(dev, udata)); 4519 else 4520 MLX5_SET(dctc, dctc, port, attr->port_num); 4521 4522 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4523 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4524 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4525 struct mlx5_ib_modify_qp_resp resp = {}; 4526 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4527 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4528 4529 if (udata->outlen < min_resp_len) 4530 return -EINVAL; 4531 /* 4532 * If we don't have enough space for the ECE options, 4533 * simply indicate it with resp.response_length. 4534 */ 4535 resp.response_length = (udata->outlen < sizeof(resp)) ? 4536 min_resp_len : 4537 sizeof(resp); 4538 4539 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4540 if (!is_valid_mask(attr_mask, required, 0)) 4541 return -EINVAL; 4542 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4543 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4544 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4545 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4546 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4547 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4548 if (attr->ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE) 4549 MLX5_SET(dctc, dctc, eth_prio, attr->ah_attr.sl & 0x7); 4550 4551 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4552 MLX5_ST_SZ_BYTES(create_dct_in), out, 4553 sizeof(out)); 4554 err = mlx5_cmd_check(dev->mdev, err, qp->dct.in, out); 4555 if (err) 4556 return err; 4557 resp.dctn = qp->dct.mdct.mqp.qpn; 4558 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4559 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4560 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4561 if (err) { 4562 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4563 return err; 4564 } 4565 } else { 4566 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4567 return -EINVAL; 4568 } 4569 4570 qp->state = new_state; 4571 return 0; 4572 } 4573 4574 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4575 struct mlx5_ib_qp *qp) 4576 { 4577 if (dev->profile != &raw_eth_profile) 4578 return true; 4579 4580 if (qp->type == IB_QPT_RAW_PACKET || qp->type == MLX5_IB_QPT_REG_UMR) 4581 return true; 4582 4583 /* Internal QP used for wc testing, with NOPs in wq */ 4584 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 4585 return true; 4586 4587 return false; 4588 } 4589 4590 static int validate_rd_atomic(struct mlx5_ib_dev *dev, struct ib_qp_attr *attr, 4591 int attr_mask, enum ib_qp_type qp_type) 4592 { 4593 int log_max_ra_res; 4594 int log_max_ra_req; 4595 4596 if (qp_type == MLX5_IB_QPT_DCI) { 4597 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4598 log_max_ra_res_dc); 4599 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4600 log_max_ra_req_dc); 4601 } else { 4602 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4603 log_max_ra_res_qp); 4604 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4605 log_max_ra_req_qp); 4606 } 4607 4608 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4609 attr->max_rd_atomic > log_max_ra_res) { 4610 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4611 attr->max_rd_atomic); 4612 return false; 4613 } 4614 4615 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4616 attr->max_dest_rd_atomic > log_max_ra_req) { 4617 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4618 attr->max_dest_rd_atomic); 4619 return false; 4620 } 4621 return true; 4622 } 4623 4624 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4625 int attr_mask, struct ib_udata *udata) 4626 { 4627 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4628 struct mlx5_ib_modify_qp_resp resp = {}; 4629 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4630 struct mlx5_ib_modify_qp ucmd = {}; 4631 enum ib_qp_type qp_type; 4632 enum ib_qp_state cur_state, new_state; 4633 int err = -EINVAL; 4634 4635 if (!mlx5_ib_modify_qp_allowed(dev, qp)) 4636 return -EOPNOTSUPP; 4637 4638 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4639 return -EOPNOTSUPP; 4640 4641 if (ibqp->rwq_ind_tbl) 4642 return -ENOSYS; 4643 4644 if (udata && udata->inlen) { 4645 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4646 return -EINVAL; 4647 4648 if (udata->inlen > sizeof(ucmd) && 4649 !ib_is_udata_cleared(udata, sizeof(ucmd), 4650 udata->inlen - sizeof(ucmd))) 4651 return -EOPNOTSUPP; 4652 4653 if (ib_copy_from_udata(&ucmd, udata, 4654 min(udata->inlen, sizeof(ucmd)))) 4655 return -EFAULT; 4656 4657 if (ucmd.comp_mask || 4658 memchr_inv(&ucmd.burst_info.reserved, 0, 4659 sizeof(ucmd.burst_info.reserved))) 4660 return -EOPNOTSUPP; 4661 4662 } 4663 4664 if (qp->type == IB_QPT_GSI) 4665 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4666 4667 qp_type = (qp->type == MLX5_IB_QPT_HW_GSI) ? IB_QPT_GSI : qp->type; 4668 4669 if (qp_type == MLX5_IB_QPT_DCT) 4670 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4671 4672 mutex_lock(&qp->mutex); 4673 4674 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4675 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4676 4677 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4678 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4679 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4680 attr_mask); 4681 goto out; 4682 } 4683 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4684 qp_type != MLX5_IB_QPT_DCI && 4685 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4686 attr_mask)) { 4687 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4688 cur_state, new_state, qp->type, attr_mask); 4689 goto out; 4690 } else if (qp_type == MLX5_IB_QPT_DCI && 4691 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4692 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4693 cur_state, new_state, qp_type, attr_mask); 4694 goto out; 4695 } 4696 4697 if ((attr_mask & IB_QP_PORT) && 4698 (attr->port_num == 0 || 4699 attr->port_num > dev->num_ports)) { 4700 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4701 attr->port_num, dev->num_ports); 4702 goto out; 4703 } 4704 4705 if ((attr_mask & IB_QP_PKEY_INDEX) && 4706 attr->pkey_index >= dev->pkey_table_len) { 4707 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4708 goto out; 4709 } 4710 4711 if (!validate_rd_atomic(dev, attr, attr_mask, qp_type)) 4712 goto out; 4713 4714 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4715 err = 0; 4716 goto out; 4717 } 4718 4719 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4720 new_state, &ucmd, &resp, udata); 4721 4722 /* resp.response_length is set in ECE supported flows only */ 4723 if (!err && resp.response_length && 4724 udata->outlen >= resp.response_length) 4725 /* Return -EFAULT to the user and expect him to destroy QP. */ 4726 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4727 4728 out: 4729 mutex_unlock(&qp->mutex); 4730 return err; 4731 } 4732 4733 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4734 { 4735 switch (mlx5_state) { 4736 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4737 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4738 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4739 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4740 case MLX5_QP_STATE_SQ_DRAINING: 4741 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4742 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4743 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4744 default: return -1; 4745 } 4746 } 4747 4748 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4749 { 4750 switch (mlx5_mig_state) { 4751 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4752 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4753 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4754 default: return -1; 4755 } 4756 } 4757 4758 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4759 struct rdma_ah_attr *ah_attr, void *path) 4760 { 4761 int port = MLX5_GET(ads, path, vhca_port_num); 4762 int static_rate; 4763 4764 memset(ah_attr, 0, sizeof(*ah_attr)); 4765 4766 if (!port || port > ibdev->num_ports) 4767 return; 4768 4769 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4770 4771 rdma_ah_set_port_num(ah_attr, port); 4772 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4773 4774 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4775 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4776 4777 static_rate = MLX5_GET(ads, path, stat_rate); 4778 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4779 if (MLX5_GET(ads, path, grh) || 4780 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4781 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4782 MLX5_GET(ads, path, src_addr_index), 4783 MLX5_GET(ads, path, hop_limit), 4784 MLX5_GET(ads, path, tclass)); 4785 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4786 } 4787 } 4788 4789 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4790 struct mlx5_ib_sq *sq, 4791 u8 *sq_state) 4792 { 4793 int err; 4794 4795 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4796 if (err) 4797 goto out; 4798 sq->state = *sq_state; 4799 4800 out: 4801 return err; 4802 } 4803 4804 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4805 struct mlx5_ib_rq *rq, 4806 u8 *rq_state) 4807 { 4808 void *out; 4809 void *rqc; 4810 int inlen; 4811 int err; 4812 4813 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4814 out = kvzalloc(inlen, GFP_KERNEL); 4815 if (!out) 4816 return -ENOMEM; 4817 4818 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4819 if (err) 4820 goto out; 4821 4822 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4823 *rq_state = MLX5_GET(rqc, rqc, state); 4824 rq->state = *rq_state; 4825 4826 out: 4827 kvfree(out); 4828 return err; 4829 } 4830 4831 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4832 struct mlx5_ib_qp *qp, u8 *qp_state) 4833 { 4834 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4835 [MLX5_RQC_STATE_RST] = { 4836 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4837 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4838 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4839 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4840 }, 4841 [MLX5_RQC_STATE_RDY] = { 4842 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4843 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4844 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4845 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4846 }, 4847 [MLX5_RQC_STATE_ERR] = { 4848 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4849 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4850 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4851 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4852 }, 4853 [MLX5_RQ_STATE_NA] = { 4854 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4855 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4856 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4857 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4858 }, 4859 }; 4860 4861 *qp_state = sqrq_trans[rq_state][sq_state]; 4862 4863 if (*qp_state == MLX5_QP_STATE_BAD) { 4864 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4865 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4866 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4867 return -EINVAL; 4868 } 4869 4870 if (*qp_state == MLX5_QP_STATE) 4871 *qp_state = qp->state; 4872 4873 return 0; 4874 } 4875 4876 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4877 struct mlx5_ib_qp *qp, 4878 u8 *raw_packet_qp_state) 4879 { 4880 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4881 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4882 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4883 int err; 4884 u8 sq_state = MLX5_SQ_STATE_NA; 4885 u8 rq_state = MLX5_RQ_STATE_NA; 4886 4887 if (qp->sq.wqe_cnt) { 4888 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4889 if (err) 4890 return err; 4891 } 4892 4893 if (qp->rq.wqe_cnt) { 4894 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4895 if (err) 4896 return err; 4897 } 4898 4899 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4900 raw_packet_qp_state); 4901 } 4902 4903 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4904 struct ib_qp_attr *qp_attr) 4905 { 4906 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4907 void *qpc, *pri_path, *alt_path; 4908 u32 *outb; 4909 int err; 4910 4911 outb = kzalloc(outlen, GFP_KERNEL); 4912 if (!outb) 4913 return -ENOMEM; 4914 4915 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 4916 false); 4917 if (err) 4918 goto out; 4919 4920 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4921 4922 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4923 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4924 qp_attr->sq_draining = 1; 4925 4926 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4927 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4928 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4929 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4930 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4931 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4932 4933 if (MLX5_GET(qpc, qpc, rre)) 4934 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4935 if (MLX5_GET(qpc, qpc, rwe)) 4936 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4937 if (MLX5_GET(qpc, qpc, rae)) 4938 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4939 4940 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4941 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4942 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4943 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4944 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4945 4946 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4947 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4948 4949 if (qp->type == IB_QPT_RC || qp->type == IB_QPT_UC || 4950 qp->type == IB_QPT_XRC_INI || qp->type == IB_QPT_XRC_TGT) { 4951 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4952 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4953 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4954 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4955 } 4956 4957 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4958 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4959 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4960 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4961 4962 out: 4963 kfree(outb); 4964 return err; 4965 } 4966 4967 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4968 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4969 struct ib_qp_init_attr *qp_init_attr) 4970 { 4971 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4972 u32 *out; 4973 u32 access_flags = 0; 4974 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4975 void *dctc; 4976 int err; 4977 int supported_mask = IB_QP_STATE | 4978 IB_QP_ACCESS_FLAGS | 4979 IB_QP_PORT | 4980 IB_QP_MIN_RNR_TIMER | 4981 IB_QP_AV | 4982 IB_QP_PATH_MTU | 4983 IB_QP_PKEY_INDEX; 4984 4985 if (qp_attr_mask & ~supported_mask) 4986 return -EINVAL; 4987 if (mqp->state != IB_QPS_RTR) 4988 return -EINVAL; 4989 4990 out = kzalloc(outlen, GFP_KERNEL); 4991 if (!out) 4992 return -ENOMEM; 4993 4994 err = mlx5_core_dct_query(dev, dct, out, outlen); 4995 if (err) 4996 goto out; 4997 4998 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4999 5000 if (qp_attr_mask & IB_QP_STATE) 5001 qp_attr->qp_state = IB_QPS_RTR; 5002 5003 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5004 if (MLX5_GET(dctc, dctc, rre)) 5005 access_flags |= IB_ACCESS_REMOTE_READ; 5006 if (MLX5_GET(dctc, dctc, rwe)) 5007 access_flags |= IB_ACCESS_REMOTE_WRITE; 5008 if (MLX5_GET(dctc, dctc, rae)) 5009 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5010 qp_attr->qp_access_flags = access_flags; 5011 } 5012 5013 if (qp_attr_mask & IB_QP_PORT) 5014 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5015 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5016 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5017 if (qp_attr_mask & IB_QP_AV) { 5018 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5019 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5020 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5021 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5022 } 5023 if (qp_attr_mask & IB_QP_PATH_MTU) 5024 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5025 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5026 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5027 out: 5028 kfree(out); 5029 return err; 5030 } 5031 5032 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5033 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5034 { 5035 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5036 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5037 int err = 0; 5038 u8 raw_packet_qp_state; 5039 5040 if (ibqp->rwq_ind_tbl) 5041 return -ENOSYS; 5042 5043 if (qp->type == IB_QPT_GSI) 5044 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5045 qp_init_attr); 5046 5047 /* Not all of output fields are applicable, make sure to zero them */ 5048 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5049 memset(qp_attr, 0, sizeof(*qp_attr)); 5050 5051 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 5052 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5053 qp_attr_mask, qp_init_attr); 5054 5055 mutex_lock(&qp->mutex); 5056 5057 if (qp->type == IB_QPT_RAW_PACKET || 5058 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 5059 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5060 if (err) 5061 goto out; 5062 qp->state = raw_packet_qp_state; 5063 qp_attr->port_num = 1; 5064 } else { 5065 err = query_qp_attr(dev, qp, qp_attr); 5066 if (err) 5067 goto out; 5068 } 5069 5070 qp_attr->qp_state = qp->state; 5071 qp_attr->cur_qp_state = qp_attr->qp_state; 5072 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5073 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5074 5075 if (!ibqp->uobject) { 5076 qp_attr->cap.max_send_wr = qp->sq.max_post; 5077 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5078 qp_init_attr->qp_context = ibqp->qp_context; 5079 } else { 5080 qp_attr->cap.max_send_wr = 0; 5081 qp_attr->cap.max_send_sge = 0; 5082 } 5083 5084 qp_init_attr->qp_type = qp->type; 5085 qp_init_attr->recv_cq = ibqp->recv_cq; 5086 qp_init_attr->send_cq = ibqp->send_cq; 5087 qp_init_attr->srq = ibqp->srq; 5088 qp_attr->cap.max_inline_data = qp->max_inline_data; 5089 5090 qp_init_attr->cap = qp_attr->cap; 5091 5092 qp_init_attr->create_flags = qp->flags; 5093 5094 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5095 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5096 5097 out: 5098 mutex_unlock(&qp->mutex); 5099 return err; 5100 } 5101 5102 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 5103 { 5104 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 5105 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 5106 5107 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5108 return -EOPNOTSUPP; 5109 5110 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5111 } 5112 5113 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5114 { 5115 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5116 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5117 5118 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5119 } 5120 5121 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5122 { 5123 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5124 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5125 struct ib_event event; 5126 5127 if (rwq->ibwq.event_handler) { 5128 event.device = rwq->ibwq.device; 5129 event.element.wq = &rwq->ibwq; 5130 switch (type) { 5131 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5132 event.event = IB_EVENT_WQ_FATAL; 5133 break; 5134 default: 5135 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5136 return; 5137 } 5138 5139 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5140 } 5141 } 5142 5143 static int set_delay_drop(struct mlx5_ib_dev *dev) 5144 { 5145 int err = 0; 5146 5147 mutex_lock(&dev->delay_drop.lock); 5148 if (dev->delay_drop.activate) 5149 goto out; 5150 5151 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 5152 if (err) 5153 goto out; 5154 5155 dev->delay_drop.activate = true; 5156 out: 5157 mutex_unlock(&dev->delay_drop.lock); 5158 5159 if (!err) 5160 atomic_inc(&dev->delay_drop.rqs_cnt); 5161 return err; 5162 } 5163 5164 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5165 struct ib_wq_init_attr *init_attr) 5166 { 5167 struct mlx5_ib_dev *dev; 5168 int has_net_offloads; 5169 __be64 *rq_pas0; 5170 int ts_format; 5171 void *in; 5172 void *rqc; 5173 void *wq; 5174 int inlen; 5175 int err; 5176 5177 dev = to_mdev(pd->device); 5178 5179 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 5180 if (ts_format < 0) 5181 return ts_format; 5182 5183 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5184 in = kvzalloc(inlen, GFP_KERNEL); 5185 if (!in) 5186 return -ENOMEM; 5187 5188 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5189 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5190 MLX5_SET(rqc, rqc, mem_rq_type, 5191 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5192 MLX5_SET(rqc, rqc, ts_format, ts_format); 5193 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5194 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5195 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5196 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5197 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5198 MLX5_SET(wq, wq, wq_type, 5199 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5200 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5201 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5202 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5203 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5204 err = -EOPNOTSUPP; 5205 goto out; 5206 } else { 5207 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5208 } 5209 } 5210 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5211 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5212 /* 5213 * In Firmware number of strides in each WQE is: 5214 * "512 * 2^single_wqe_log_num_of_strides" 5215 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 5216 * accepted as 0 to 9 5217 */ 5218 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 5219 2, 3, 4, 5, 6, 7, 8, 9 }; 5220 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5221 MLX5_SET(wq, wq, log_wqe_stride_size, 5222 rwq->single_stride_log_num_of_bytes - 5223 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5224 MLX5_SET(wq, wq, log_wqe_num_of_strides, 5225 fw_map[rwq->log_num_strides - 5226 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 5227 } 5228 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5229 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5230 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5231 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5232 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5233 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5234 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5235 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5236 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5237 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5238 err = -EOPNOTSUPP; 5239 goto out; 5240 } 5241 } else { 5242 MLX5_SET(rqc, rqc, vsd, 1); 5243 } 5244 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5245 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5246 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5247 err = -EOPNOTSUPP; 5248 goto out; 5249 } 5250 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5251 } 5252 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5253 if (!(dev->ib_dev.attrs.raw_packet_caps & 5254 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5255 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5256 err = -EOPNOTSUPP; 5257 goto out; 5258 } 5259 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5260 } 5261 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5262 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 5263 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 5264 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5265 err = set_delay_drop(dev); 5266 if (err) { 5267 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5268 err); 5269 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5270 } else { 5271 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5272 } 5273 } 5274 out: 5275 kvfree(in); 5276 return err; 5277 } 5278 5279 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5280 struct ib_wq_init_attr *wq_init_attr, 5281 struct mlx5_ib_create_wq *ucmd, 5282 struct mlx5_ib_rwq *rwq) 5283 { 5284 /* Sanity check RQ size before proceeding */ 5285 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5286 return -EINVAL; 5287 5288 if (!ucmd->rq_wqe_count) 5289 return -EINVAL; 5290 5291 rwq->wqe_count = ucmd->rq_wqe_count; 5292 rwq->wqe_shift = ucmd->rq_wqe_shift; 5293 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5294 return -EINVAL; 5295 5296 rwq->log_rq_stride = rwq->wqe_shift; 5297 rwq->log_rq_size = ilog2(rwq->wqe_count); 5298 return 0; 5299 } 5300 5301 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5302 { 5303 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5304 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5305 return false; 5306 5307 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5308 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5309 return false; 5310 5311 return true; 5312 } 5313 5314 static int prepare_user_rq(struct ib_pd *pd, 5315 struct ib_wq_init_attr *init_attr, 5316 struct ib_udata *udata, 5317 struct mlx5_ib_rwq *rwq) 5318 { 5319 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5320 struct mlx5_ib_create_wq ucmd = {}; 5321 int err; 5322 size_t required_cmd_sz; 5323 5324 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 5325 single_stride_log_num_of_bytes); 5326 if (udata->inlen < required_cmd_sz) { 5327 mlx5_ib_dbg(dev, "invalid inlen\n"); 5328 return -EINVAL; 5329 } 5330 5331 if (udata->inlen > sizeof(ucmd) && 5332 !ib_is_udata_cleared(udata, sizeof(ucmd), 5333 udata->inlen - sizeof(ucmd))) { 5334 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5335 return -EOPNOTSUPP; 5336 } 5337 5338 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5339 mlx5_ib_dbg(dev, "copy failed\n"); 5340 return -EFAULT; 5341 } 5342 5343 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5344 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5345 return -EOPNOTSUPP; 5346 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5347 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5348 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5349 return -EOPNOTSUPP; 5350 } 5351 if ((ucmd.single_stride_log_num_of_bytes < 5352 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5353 (ucmd.single_stride_log_num_of_bytes > 5354 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5355 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5356 ucmd.single_stride_log_num_of_bytes, 5357 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5358 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5359 return -EINVAL; 5360 } 5361 if (!log_of_strides_valid(dev, 5362 ucmd.single_wqe_log_num_of_strides)) { 5363 mlx5_ib_dbg( 5364 dev, 5365 "Invalid log num strides (%u. Range is %u - %u)\n", 5366 ucmd.single_wqe_log_num_of_strides, 5367 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5368 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5369 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5370 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5371 return -EINVAL; 5372 } 5373 rwq->single_stride_log_num_of_bytes = 5374 ucmd.single_stride_log_num_of_bytes; 5375 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5376 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5377 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5378 } 5379 5380 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5381 if (err) { 5382 mlx5_ib_dbg(dev, "err %d\n", err); 5383 return err; 5384 } 5385 5386 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5387 if (err) { 5388 mlx5_ib_dbg(dev, "err %d\n", err); 5389 return err; 5390 } 5391 5392 rwq->user_index = ucmd.user_index; 5393 return 0; 5394 } 5395 5396 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5397 struct ib_wq_init_attr *init_attr, 5398 struct ib_udata *udata) 5399 { 5400 struct mlx5_ib_dev *dev; 5401 struct mlx5_ib_rwq *rwq; 5402 struct mlx5_ib_create_wq_resp resp = {}; 5403 size_t min_resp_len; 5404 int err; 5405 5406 if (!udata) 5407 return ERR_PTR(-ENOSYS); 5408 5409 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5410 if (udata->outlen && udata->outlen < min_resp_len) 5411 return ERR_PTR(-EINVAL); 5412 5413 if (!capable(CAP_SYS_RAWIO) && 5414 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5415 return ERR_PTR(-EPERM); 5416 5417 dev = to_mdev(pd->device); 5418 switch (init_attr->wq_type) { 5419 case IB_WQT_RQ: 5420 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5421 if (!rwq) 5422 return ERR_PTR(-ENOMEM); 5423 err = prepare_user_rq(pd, init_attr, udata, rwq); 5424 if (err) 5425 goto err; 5426 err = create_rq(rwq, pd, init_attr); 5427 if (err) 5428 goto err_user_rq; 5429 break; 5430 default: 5431 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5432 init_attr->wq_type); 5433 return ERR_PTR(-EINVAL); 5434 } 5435 5436 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5437 rwq->ibwq.state = IB_WQS_RESET; 5438 if (udata->outlen) { 5439 resp.response_length = offsetofend( 5440 struct mlx5_ib_create_wq_resp, response_length); 5441 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5442 if (err) 5443 goto err_copy; 5444 } 5445 5446 rwq->core_qp.event = mlx5_ib_wq_event; 5447 rwq->ibwq.event_handler = init_attr->event_handler; 5448 return &rwq->ibwq; 5449 5450 err_copy: 5451 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5452 err_user_rq: 5453 destroy_user_rq(dev, pd, rwq, udata); 5454 err: 5455 kfree(rwq); 5456 return ERR_PTR(err); 5457 } 5458 5459 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5460 { 5461 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5462 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5463 int ret; 5464 5465 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5466 if (ret) 5467 return ret; 5468 destroy_user_rq(dev, wq->pd, rwq, udata); 5469 kfree(rwq); 5470 return 0; 5471 } 5472 5473 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5474 struct ib_rwq_ind_table_init_attr *init_attr, 5475 struct ib_udata *udata) 5476 { 5477 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5478 to_mrwq_ind_table(ib_rwq_ind_table); 5479 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5480 int sz = 1 << init_attr->log_ind_tbl_size; 5481 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5482 size_t min_resp_len; 5483 int inlen; 5484 int err; 5485 int i; 5486 u32 *in; 5487 void *rqtc; 5488 5489 if (udata->inlen > 0 && 5490 !ib_is_udata_cleared(udata, 0, 5491 udata->inlen)) 5492 return -EOPNOTSUPP; 5493 5494 if (init_attr->log_ind_tbl_size > 5495 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5496 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5497 init_attr->log_ind_tbl_size, 5498 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5499 return -EINVAL; 5500 } 5501 5502 min_resp_len = 5503 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5504 if (udata->outlen && udata->outlen < min_resp_len) 5505 return -EINVAL; 5506 5507 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5508 in = kvzalloc(inlen, GFP_KERNEL); 5509 if (!in) 5510 return -ENOMEM; 5511 5512 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5513 5514 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5515 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5516 5517 for (i = 0; i < sz; i++) 5518 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5519 5520 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5521 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5522 5523 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5524 kvfree(in); 5525 if (err) 5526 return err; 5527 5528 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5529 if (udata->outlen) { 5530 resp.response_length = 5531 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5532 response_length); 5533 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5534 if (err) 5535 goto err_copy; 5536 } 5537 5538 return 0; 5539 5540 err_copy: 5541 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5542 return err; 5543 } 5544 5545 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5546 { 5547 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5548 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5549 5550 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5551 } 5552 5553 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5554 u32 wq_attr_mask, struct ib_udata *udata) 5555 { 5556 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5557 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5558 struct mlx5_ib_modify_wq ucmd = {}; 5559 size_t required_cmd_sz; 5560 int curr_wq_state; 5561 int wq_state; 5562 int inlen; 5563 int err; 5564 void *rqc; 5565 void *in; 5566 5567 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5568 if (udata->inlen < required_cmd_sz) 5569 return -EINVAL; 5570 5571 if (udata->inlen > sizeof(ucmd) && 5572 !ib_is_udata_cleared(udata, sizeof(ucmd), 5573 udata->inlen - sizeof(ucmd))) 5574 return -EOPNOTSUPP; 5575 5576 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5577 return -EFAULT; 5578 5579 if (ucmd.comp_mask || ucmd.reserved) 5580 return -EOPNOTSUPP; 5581 5582 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5583 in = kvzalloc(inlen, GFP_KERNEL); 5584 if (!in) 5585 return -ENOMEM; 5586 5587 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5588 5589 curr_wq_state = wq_attr->curr_wq_state; 5590 wq_state = wq_attr->wq_state; 5591 if (curr_wq_state == IB_WQS_ERR) 5592 curr_wq_state = MLX5_RQC_STATE_ERR; 5593 if (wq_state == IB_WQS_ERR) 5594 wq_state = MLX5_RQC_STATE_ERR; 5595 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5596 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5597 MLX5_SET(rqc, rqc, state, wq_state); 5598 5599 if (wq_attr_mask & IB_WQ_FLAGS) { 5600 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5601 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5602 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5603 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5604 err = -EOPNOTSUPP; 5605 goto out; 5606 } 5607 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5608 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5609 MLX5_SET(rqc, rqc, vsd, 5610 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5611 } 5612 5613 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5614 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5615 err = -EOPNOTSUPP; 5616 goto out; 5617 } 5618 } 5619 5620 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5621 u16 set_id; 5622 5623 set_id = mlx5_ib_get_counters_id(dev, 0); 5624 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5625 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5626 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5627 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5628 } else 5629 dev_info_once( 5630 &dev->ib_dev.dev, 5631 "Receive WQ counters are not supported on current FW\n"); 5632 } 5633 5634 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5635 if (!err) 5636 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5637 5638 out: 5639 kvfree(in); 5640 return err; 5641 } 5642 5643 struct mlx5_ib_drain_cqe { 5644 struct ib_cqe cqe; 5645 struct completion done; 5646 }; 5647 5648 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5649 { 5650 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5651 struct mlx5_ib_drain_cqe, 5652 cqe); 5653 5654 complete(&cqe->done); 5655 } 5656 5657 /* This function returns only once the drained WR was completed */ 5658 static void handle_drain_completion(struct ib_cq *cq, 5659 struct mlx5_ib_drain_cqe *sdrain, 5660 struct mlx5_ib_dev *dev) 5661 { 5662 struct mlx5_core_dev *mdev = dev->mdev; 5663 5664 if (cq->poll_ctx == IB_POLL_DIRECT) { 5665 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5666 ib_process_cq_direct(cq, -1); 5667 return; 5668 } 5669 5670 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5671 struct mlx5_ib_cq *mcq = to_mcq(cq); 5672 bool triggered = false; 5673 unsigned long flags; 5674 5675 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5676 /* Make sure that the CQ handler won't run if wasn't run yet */ 5677 if (!mcq->mcq.reset_notify_added) 5678 mcq->mcq.reset_notify_added = 1; 5679 else 5680 triggered = true; 5681 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5682 5683 if (triggered) { 5684 /* Wait for any scheduled/running task to be ended */ 5685 switch (cq->poll_ctx) { 5686 case IB_POLL_SOFTIRQ: 5687 irq_poll_disable(&cq->iop); 5688 irq_poll_enable(&cq->iop); 5689 break; 5690 case IB_POLL_WORKQUEUE: 5691 cancel_work_sync(&cq->work); 5692 break; 5693 default: 5694 WARN_ON_ONCE(1); 5695 } 5696 } 5697 5698 /* Run the CQ handler - this makes sure that the drain WR will 5699 * be processed if wasn't processed yet. 5700 */ 5701 mcq->mcq.comp(&mcq->mcq, NULL); 5702 } 5703 5704 wait_for_completion(&sdrain->done); 5705 } 5706 5707 void mlx5_ib_drain_sq(struct ib_qp *qp) 5708 { 5709 struct ib_cq *cq = qp->send_cq; 5710 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5711 struct mlx5_ib_drain_cqe sdrain; 5712 const struct ib_send_wr *bad_swr; 5713 struct ib_rdma_wr swr = { 5714 .wr = { 5715 .next = NULL, 5716 { .wr_cqe = &sdrain.cqe, }, 5717 .opcode = IB_WR_RDMA_WRITE, 5718 }, 5719 }; 5720 int ret; 5721 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5722 struct mlx5_core_dev *mdev = dev->mdev; 5723 5724 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5725 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5726 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5727 return; 5728 } 5729 5730 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5731 init_completion(&sdrain.done); 5732 5733 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5734 if (ret) { 5735 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5736 return; 5737 } 5738 5739 handle_drain_completion(cq, &sdrain, dev); 5740 } 5741 5742 void mlx5_ib_drain_rq(struct ib_qp *qp) 5743 { 5744 struct ib_cq *cq = qp->recv_cq; 5745 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5746 struct mlx5_ib_drain_cqe rdrain; 5747 struct ib_recv_wr rwr = {}; 5748 const struct ib_recv_wr *bad_rwr; 5749 int ret; 5750 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5751 struct mlx5_core_dev *mdev = dev->mdev; 5752 5753 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5754 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5755 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5756 return; 5757 } 5758 5759 rwr.wr_cqe = &rdrain.cqe; 5760 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5761 init_completion(&rdrain.done); 5762 5763 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5764 if (ret) { 5765 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5766 return; 5767 } 5768 5769 handle_drain_completion(cq, &rdrain, dev); 5770 } 5771 5772 /* 5773 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5774 * the default counter 5775 */ 5776 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5777 { 5778 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5779 struct mlx5_ib_qp *mqp = to_mqp(qp); 5780 int err = 0; 5781 5782 mutex_lock(&mqp->mutex); 5783 if (mqp->state == IB_QPS_RESET) { 5784 qp->counter = counter; 5785 goto out; 5786 } 5787 5788 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5789 err = -EOPNOTSUPP; 5790 goto out; 5791 } 5792 5793 if (mqp->state == IB_QPS_RTS) { 5794 err = __mlx5_ib_qp_set_counter(qp, counter); 5795 if (!err) 5796 qp->counter = counter; 5797 5798 goto out; 5799 } 5800 5801 mqp->counter_pending = 1; 5802 qp->counter = counter; 5803 5804 out: 5805 mutex_unlock(&mqp->mutex); 5806 return err; 5807 } 5808 5809 int mlx5_ib_qp_event_init(void) 5810 { 5811 mlx5_ib_qp_event_wq = alloc_ordered_workqueue("mlx5_ib_qp_event_wq", 0); 5812 if (!mlx5_ib_qp_event_wq) 5813 return -ENOMEM; 5814 5815 return 0; 5816 } 5817 5818 void mlx5_ib_qp_event_cleanup(void) 5819 { 5820 destroy_workqueue(mlx5_ib_qp_event_wq); 5821 } 5822