1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 41 /* not supported currently */ 42 static int wq_signature; 43 44 enum { 45 MLX5_IB_ACK_REQ_FREQ = 8, 46 }; 47 48 enum { 49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 51 MLX5_IB_LINK_TYPE_IB = 0, 52 MLX5_IB_LINK_TYPE_ETH = 1 53 }; 54 55 enum { 56 MLX5_IB_SQ_STRIDE = 6, 57 }; 58 59 static const u32 mlx5_ib_opcode[] = { 60 [IB_WR_SEND] = MLX5_OPCODE_SEND, 61 [IB_WR_LSO] = MLX5_OPCODE_LSO, 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 74 }; 75 76 struct mlx5_wqe_eth_pad { 77 u8 rsvd0[16]; 78 }; 79 80 enum raw_qp_set_mask_map { 81 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 82 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 83 }; 84 85 struct mlx5_modify_raw_qp_param { 86 u16 operation; 87 88 u32 set_mask; /* raw_qp_set_mask_map */ 89 90 struct mlx5_rate_limit rl; 91 92 u8 rq_q_ctr_id; 93 }; 94 95 static void get_cqs(enum ib_qp_type qp_type, 96 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 97 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 98 99 static int is_qp0(enum ib_qp_type qp_type) 100 { 101 return qp_type == IB_QPT_SMI; 102 } 103 104 static int is_sqp(enum ib_qp_type qp_type) 105 { 106 return is_qp0(qp_type) || is_qp1(qp_type); 107 } 108 109 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 110 { 111 return mlx5_buf_offset(&qp->buf, offset); 112 } 113 114 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 115 { 116 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 117 } 118 119 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 120 { 121 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 122 } 123 124 /** 125 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 126 * 127 * @qp: QP to copy from. 128 * @send: copy from the send queue when non-zero, use the receive queue 129 * otherwise. 130 * @wqe_index: index to start copying from. For send work queues, the 131 * wqe_index is in units of MLX5_SEND_WQE_BB. 132 * For receive work queue, it is the number of work queue 133 * element in the queue. 134 * @buffer: destination buffer. 135 * @length: maximum number of bytes to copy. 136 * 137 * Copies at least a single WQE, but may copy more data. 138 * 139 * Return: the number of bytes copied, or an error code. 140 */ 141 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 142 void *buffer, u32 length, 143 struct mlx5_ib_qp_base *base) 144 { 145 struct ib_device *ibdev = qp->ibqp.device; 146 struct mlx5_ib_dev *dev = to_mdev(ibdev); 147 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 148 size_t offset; 149 size_t wq_end; 150 struct ib_umem *umem = base->ubuffer.umem; 151 u32 first_copy_length; 152 int wqe_length; 153 int ret; 154 155 if (wq->wqe_cnt == 0) { 156 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 157 qp->ibqp.qp_type); 158 return -EINVAL; 159 } 160 161 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 162 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 163 164 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 165 return -EINVAL; 166 167 if (offset > umem->length || 168 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 169 return -EINVAL; 170 171 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 172 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 173 if (ret) 174 return ret; 175 176 if (send) { 177 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 178 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 179 180 wqe_length = ds * MLX5_WQE_DS_UNITS; 181 } else { 182 wqe_length = 1 << wq->wqe_shift; 183 } 184 185 if (wqe_length <= first_copy_length) 186 return first_copy_length; 187 188 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 189 wqe_length - first_copy_length); 190 if (ret) 191 return ret; 192 193 return wqe_length; 194 } 195 196 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 197 { 198 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 199 struct ib_event event; 200 201 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 202 /* This event is only valid for trans_qps */ 203 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 204 } 205 206 if (ibqp->event_handler) { 207 event.device = ibqp->device; 208 event.element.qp = ibqp; 209 switch (type) { 210 case MLX5_EVENT_TYPE_PATH_MIG: 211 event.event = IB_EVENT_PATH_MIG; 212 break; 213 case MLX5_EVENT_TYPE_COMM_EST: 214 event.event = IB_EVENT_COMM_EST; 215 break; 216 case MLX5_EVENT_TYPE_SQ_DRAINED: 217 event.event = IB_EVENT_SQ_DRAINED; 218 break; 219 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 220 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 221 break; 222 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 223 event.event = IB_EVENT_QP_FATAL; 224 break; 225 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 226 event.event = IB_EVENT_PATH_MIG_ERR; 227 break; 228 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 229 event.event = IB_EVENT_QP_REQ_ERR; 230 break; 231 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 232 event.event = IB_EVENT_QP_ACCESS_ERR; 233 break; 234 default: 235 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 236 return; 237 } 238 239 ibqp->event_handler(&event, ibqp->qp_context); 240 } 241 } 242 243 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 244 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 245 { 246 int wqe_size; 247 int wq_size; 248 249 /* Sanity check RQ size before proceeding */ 250 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 251 return -EINVAL; 252 253 if (!has_rq) { 254 qp->rq.max_gs = 0; 255 qp->rq.wqe_cnt = 0; 256 qp->rq.wqe_shift = 0; 257 cap->max_recv_wr = 0; 258 cap->max_recv_sge = 0; 259 } else { 260 if (ucmd) { 261 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 262 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 263 return -EINVAL; 264 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 265 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 266 return -EINVAL; 267 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 268 qp->rq.max_post = qp->rq.wqe_cnt; 269 } else { 270 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 271 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 272 wqe_size = roundup_pow_of_two(wqe_size); 273 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 274 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 275 qp->rq.wqe_cnt = wq_size / wqe_size; 276 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 277 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 278 wqe_size, 279 MLX5_CAP_GEN(dev->mdev, 280 max_wqe_sz_rq)); 281 return -EINVAL; 282 } 283 qp->rq.wqe_shift = ilog2(wqe_size); 284 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 285 qp->rq.max_post = qp->rq.wqe_cnt; 286 } 287 } 288 289 return 0; 290 } 291 292 static int sq_overhead(struct ib_qp_init_attr *attr) 293 { 294 int size = 0; 295 296 switch (attr->qp_type) { 297 case IB_QPT_XRC_INI: 298 size += sizeof(struct mlx5_wqe_xrc_seg); 299 /* fall through */ 300 case IB_QPT_RC: 301 size += sizeof(struct mlx5_wqe_ctrl_seg) + 302 max(sizeof(struct mlx5_wqe_atomic_seg) + 303 sizeof(struct mlx5_wqe_raddr_seg), 304 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 305 sizeof(struct mlx5_mkey_seg)); 306 break; 307 308 case IB_QPT_XRC_TGT: 309 return 0; 310 311 case IB_QPT_UC: 312 size += sizeof(struct mlx5_wqe_ctrl_seg) + 313 max(sizeof(struct mlx5_wqe_raddr_seg), 314 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 315 sizeof(struct mlx5_mkey_seg)); 316 break; 317 318 case IB_QPT_UD: 319 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 320 size += sizeof(struct mlx5_wqe_eth_pad) + 321 sizeof(struct mlx5_wqe_eth_seg); 322 /* fall through */ 323 case IB_QPT_SMI: 324 case MLX5_IB_QPT_HW_GSI: 325 size += sizeof(struct mlx5_wqe_ctrl_seg) + 326 sizeof(struct mlx5_wqe_datagram_seg); 327 break; 328 329 case MLX5_IB_QPT_REG_UMR: 330 size += sizeof(struct mlx5_wqe_ctrl_seg) + 331 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 332 sizeof(struct mlx5_mkey_seg); 333 break; 334 335 default: 336 return -EINVAL; 337 } 338 339 return size; 340 } 341 342 static int calc_send_wqe(struct ib_qp_init_attr *attr) 343 { 344 int inl_size = 0; 345 int size; 346 347 size = sq_overhead(attr); 348 if (size < 0) 349 return size; 350 351 if (attr->cap.max_inline_data) { 352 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 353 attr->cap.max_inline_data; 354 } 355 356 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 357 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 358 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 359 return MLX5_SIG_WQE_SIZE; 360 else 361 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 362 } 363 364 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 365 { 366 int max_sge; 367 368 if (attr->qp_type == IB_QPT_RC) 369 max_sge = (min_t(int, wqe_size, 512) - 370 sizeof(struct mlx5_wqe_ctrl_seg) - 371 sizeof(struct mlx5_wqe_raddr_seg)) / 372 sizeof(struct mlx5_wqe_data_seg); 373 else if (attr->qp_type == IB_QPT_XRC_INI) 374 max_sge = (min_t(int, wqe_size, 512) - 375 sizeof(struct mlx5_wqe_ctrl_seg) - 376 sizeof(struct mlx5_wqe_xrc_seg) - 377 sizeof(struct mlx5_wqe_raddr_seg)) / 378 sizeof(struct mlx5_wqe_data_seg); 379 else 380 max_sge = (wqe_size - sq_overhead(attr)) / 381 sizeof(struct mlx5_wqe_data_seg); 382 383 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 384 sizeof(struct mlx5_wqe_data_seg)); 385 } 386 387 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 388 struct mlx5_ib_qp *qp) 389 { 390 int wqe_size; 391 int wq_size; 392 393 if (!attr->cap.max_send_wr) 394 return 0; 395 396 wqe_size = calc_send_wqe(attr); 397 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 398 if (wqe_size < 0) 399 return wqe_size; 400 401 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 402 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 403 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 404 return -EINVAL; 405 } 406 407 qp->max_inline_data = wqe_size - sq_overhead(attr) - 408 sizeof(struct mlx5_wqe_inline_seg); 409 attr->cap.max_inline_data = qp->max_inline_data; 410 411 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 412 qp->signature_en = true; 413 414 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 415 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 416 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 417 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 418 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 419 qp->sq.wqe_cnt, 420 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 421 return -ENOMEM; 422 } 423 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 424 qp->sq.max_gs = get_send_sge(attr, wqe_size); 425 if (qp->sq.max_gs < attr->cap.max_send_sge) 426 return -ENOMEM; 427 428 attr->cap.max_send_sge = qp->sq.max_gs; 429 qp->sq.max_post = wq_size / wqe_size; 430 attr->cap.max_send_wr = qp->sq.max_post; 431 432 return wq_size; 433 } 434 435 static int set_user_buf_size(struct mlx5_ib_dev *dev, 436 struct mlx5_ib_qp *qp, 437 struct mlx5_ib_create_qp *ucmd, 438 struct mlx5_ib_qp_base *base, 439 struct ib_qp_init_attr *attr) 440 { 441 int desc_sz = 1 << qp->sq.wqe_shift; 442 443 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 444 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 445 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 446 return -EINVAL; 447 } 448 449 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 450 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 451 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 452 return -EINVAL; 453 } 454 455 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 456 457 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 458 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 459 qp->sq.wqe_cnt, 460 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 461 return -EINVAL; 462 } 463 464 if (attr->qp_type == IB_QPT_RAW_PACKET || 465 qp->flags & MLX5_IB_QP_UNDERLAY) { 466 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 467 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 468 } else { 469 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 470 (qp->sq.wqe_cnt << 6); 471 } 472 473 return 0; 474 } 475 476 static int qp_has_rq(struct ib_qp_init_attr *attr) 477 { 478 if (attr->qp_type == IB_QPT_XRC_INI || 479 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 480 attr->qp_type == MLX5_IB_QPT_REG_UMR || 481 !attr->cap.max_recv_wr) 482 return 0; 483 484 return 1; 485 } 486 487 enum { 488 /* this is the first blue flame register in the array of bfregs assigned 489 * to a processes. Since we do not use it for blue flame but rather 490 * regular 64 bit doorbells, we do not need a lock for maintaiing 491 * "odd/even" order 492 */ 493 NUM_NON_BLUE_FLAME_BFREGS = 1, 494 }; 495 496 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 497 { 498 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 499 } 500 501 static int num_med_bfreg(struct mlx5_ib_dev *dev, 502 struct mlx5_bfreg_info *bfregi) 503 { 504 int n; 505 506 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 507 NUM_NON_BLUE_FLAME_BFREGS; 508 509 return n >= 0 ? n : 0; 510 } 511 512 static int first_med_bfreg(struct mlx5_ib_dev *dev, 513 struct mlx5_bfreg_info *bfregi) 514 { 515 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 516 } 517 518 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 519 struct mlx5_bfreg_info *bfregi) 520 { 521 int med; 522 523 med = num_med_bfreg(dev, bfregi); 524 return ++med; 525 } 526 527 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 528 struct mlx5_bfreg_info *bfregi) 529 { 530 int i; 531 532 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 533 if (!bfregi->count[i]) { 534 bfregi->count[i]++; 535 return i; 536 } 537 } 538 539 return -ENOMEM; 540 } 541 542 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 543 struct mlx5_bfreg_info *bfregi) 544 { 545 int minidx = first_med_bfreg(dev, bfregi); 546 int i; 547 548 if (minidx < 0) 549 return minidx; 550 551 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 552 if (bfregi->count[i] < bfregi->count[minidx]) 553 minidx = i; 554 if (!bfregi->count[minidx]) 555 break; 556 } 557 558 bfregi->count[minidx]++; 559 return minidx; 560 } 561 562 static int alloc_bfreg(struct mlx5_ib_dev *dev, 563 struct mlx5_bfreg_info *bfregi, 564 enum mlx5_ib_latency_class lat) 565 { 566 int bfregn = -EINVAL; 567 568 mutex_lock(&bfregi->lock); 569 switch (lat) { 570 case MLX5_IB_LATENCY_CLASS_LOW: 571 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 572 bfregn = 0; 573 bfregi->count[bfregn]++; 574 break; 575 576 case MLX5_IB_LATENCY_CLASS_MEDIUM: 577 if (bfregi->ver < 2) 578 bfregn = -ENOMEM; 579 else 580 bfregn = alloc_med_class_bfreg(dev, bfregi); 581 break; 582 583 case MLX5_IB_LATENCY_CLASS_HIGH: 584 if (bfregi->ver < 2) 585 bfregn = -ENOMEM; 586 else 587 bfregn = alloc_high_class_bfreg(dev, bfregi); 588 break; 589 } 590 mutex_unlock(&bfregi->lock); 591 592 return bfregn; 593 } 594 595 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 596 { 597 mutex_lock(&bfregi->lock); 598 bfregi->count[bfregn]--; 599 mutex_unlock(&bfregi->lock); 600 } 601 602 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 603 { 604 switch (state) { 605 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 606 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 607 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 608 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 609 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 610 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 611 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 612 default: return -1; 613 } 614 } 615 616 static int to_mlx5_st(enum ib_qp_type type) 617 { 618 switch (type) { 619 case IB_QPT_RC: return MLX5_QP_ST_RC; 620 case IB_QPT_UC: return MLX5_QP_ST_UC; 621 case IB_QPT_UD: return MLX5_QP_ST_UD; 622 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 623 case IB_QPT_XRC_INI: 624 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 625 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 626 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 627 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 628 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 629 case IB_QPT_RAW_PACKET: 630 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 631 case IB_QPT_MAX: 632 default: return -EINVAL; 633 } 634 } 635 636 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 637 struct mlx5_ib_cq *recv_cq); 638 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 639 struct mlx5_ib_cq *recv_cq); 640 641 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 642 struct mlx5_bfreg_info *bfregi, int bfregn, 643 bool dyn_bfreg) 644 { 645 int bfregs_per_sys_page; 646 int index_of_sys_page; 647 int offset; 648 649 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 650 MLX5_NON_FP_BFREGS_PER_UAR; 651 index_of_sys_page = bfregn / bfregs_per_sys_page; 652 653 if (dyn_bfreg) { 654 index_of_sys_page += bfregi->num_static_sys_pages; 655 if (bfregn > bfregi->num_dyn_bfregs || 656 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 657 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 658 return -EINVAL; 659 } 660 } 661 662 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 663 return bfregi->sys_pages[index_of_sys_page] + offset; 664 } 665 666 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 667 struct ib_pd *pd, 668 unsigned long addr, size_t size, 669 struct ib_umem **umem, 670 int *npages, int *page_shift, int *ncont, 671 u32 *offset) 672 { 673 int err; 674 675 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 676 if (IS_ERR(*umem)) { 677 mlx5_ib_dbg(dev, "umem_get failed\n"); 678 return PTR_ERR(*umem); 679 } 680 681 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 682 683 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 684 if (err) { 685 mlx5_ib_warn(dev, "bad offset\n"); 686 goto err_umem; 687 } 688 689 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 690 addr, size, *npages, *page_shift, *ncont, *offset); 691 692 return 0; 693 694 err_umem: 695 ib_umem_release(*umem); 696 *umem = NULL; 697 698 return err; 699 } 700 701 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 702 struct mlx5_ib_rwq *rwq) 703 { 704 struct mlx5_ib_ucontext *context; 705 706 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 707 atomic_dec(&dev->delay_drop.rqs_cnt); 708 709 context = to_mucontext(pd->uobject->context); 710 mlx5_ib_db_unmap_user(context, &rwq->db); 711 if (rwq->umem) 712 ib_umem_release(rwq->umem); 713 } 714 715 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 716 struct mlx5_ib_rwq *rwq, 717 struct mlx5_ib_create_wq *ucmd) 718 { 719 struct mlx5_ib_ucontext *context; 720 int page_shift = 0; 721 int npages; 722 u32 offset = 0; 723 int ncont = 0; 724 int err; 725 726 if (!ucmd->buf_addr) 727 return -EINVAL; 728 729 context = to_mucontext(pd->uobject->context); 730 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 731 rwq->buf_size, 0, 0); 732 if (IS_ERR(rwq->umem)) { 733 mlx5_ib_dbg(dev, "umem_get failed\n"); 734 err = PTR_ERR(rwq->umem); 735 return err; 736 } 737 738 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 739 &ncont, NULL); 740 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 741 &rwq->rq_page_offset); 742 if (err) { 743 mlx5_ib_warn(dev, "bad offset\n"); 744 goto err_umem; 745 } 746 747 rwq->rq_num_pas = ncont; 748 rwq->page_shift = page_shift; 749 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 750 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 751 752 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 753 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 754 npages, page_shift, ncont, offset); 755 756 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 757 if (err) { 758 mlx5_ib_dbg(dev, "map failed\n"); 759 goto err_umem; 760 } 761 762 rwq->create_type = MLX5_WQ_USER; 763 return 0; 764 765 err_umem: 766 ib_umem_release(rwq->umem); 767 return err; 768 } 769 770 static int adjust_bfregn(struct mlx5_ib_dev *dev, 771 struct mlx5_bfreg_info *bfregi, int bfregn) 772 { 773 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 774 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 775 } 776 777 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 778 struct mlx5_ib_qp *qp, struct ib_udata *udata, 779 struct ib_qp_init_attr *attr, 780 u32 **in, 781 struct mlx5_ib_create_qp_resp *resp, int *inlen, 782 struct mlx5_ib_qp_base *base) 783 { 784 struct mlx5_ib_ucontext *context; 785 struct mlx5_ib_create_qp ucmd; 786 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 787 int page_shift = 0; 788 int uar_index = 0; 789 int npages; 790 u32 offset = 0; 791 int bfregn; 792 int ncont = 0; 793 __be64 *pas; 794 void *qpc; 795 int err; 796 797 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 798 if (err) { 799 mlx5_ib_dbg(dev, "copy failed\n"); 800 return err; 801 } 802 803 context = to_mucontext(pd->uobject->context); 804 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 805 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 806 ucmd.bfreg_index, true); 807 if (uar_index < 0) 808 return uar_index; 809 810 bfregn = MLX5_IB_INVALID_BFREG; 811 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 812 /* 813 * TBD: should come from the verbs when we have the API 814 */ 815 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 816 bfregn = MLX5_CROSS_CHANNEL_BFREG; 817 } 818 else { 819 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 820 if (bfregn < 0) { 821 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 822 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 823 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 824 if (bfregn < 0) { 825 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 826 mlx5_ib_dbg(dev, "reverting to high latency\n"); 827 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 828 if (bfregn < 0) { 829 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 830 return bfregn; 831 } 832 } 833 } 834 } 835 836 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 837 if (bfregn != MLX5_IB_INVALID_BFREG) 838 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 839 false); 840 841 qp->rq.offset = 0; 842 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 843 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 844 845 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 846 if (err) 847 goto err_bfreg; 848 849 if (ucmd.buf_addr && ubuffer->buf_size) { 850 ubuffer->buf_addr = ucmd.buf_addr; 851 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 852 ubuffer->buf_size, 853 &ubuffer->umem, &npages, &page_shift, 854 &ncont, &offset); 855 if (err) 856 goto err_bfreg; 857 } else { 858 ubuffer->umem = NULL; 859 } 860 861 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 862 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 863 *in = kvzalloc(*inlen, GFP_KERNEL); 864 if (!*in) { 865 err = -ENOMEM; 866 goto err_umem; 867 } 868 869 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 870 if (ubuffer->umem) 871 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 872 873 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 874 875 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 876 MLX5_SET(qpc, qpc, page_offset, offset); 877 878 MLX5_SET(qpc, qpc, uar_page, uar_index); 879 if (bfregn != MLX5_IB_INVALID_BFREG) 880 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 881 else 882 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 883 qp->bfregn = bfregn; 884 885 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 886 if (err) { 887 mlx5_ib_dbg(dev, "map failed\n"); 888 goto err_free; 889 } 890 891 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 892 if (err) { 893 mlx5_ib_dbg(dev, "copy failed\n"); 894 goto err_unmap; 895 } 896 qp->create_type = MLX5_QP_USER; 897 898 return 0; 899 900 err_unmap: 901 mlx5_ib_db_unmap_user(context, &qp->db); 902 903 err_free: 904 kvfree(*in); 905 906 err_umem: 907 if (ubuffer->umem) 908 ib_umem_release(ubuffer->umem); 909 910 err_bfreg: 911 if (bfregn != MLX5_IB_INVALID_BFREG) 912 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 913 return err; 914 } 915 916 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 917 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 918 { 919 struct mlx5_ib_ucontext *context; 920 921 context = to_mucontext(pd->uobject->context); 922 mlx5_ib_db_unmap_user(context, &qp->db); 923 if (base->ubuffer.umem) 924 ib_umem_release(base->ubuffer.umem); 925 926 /* 927 * Free only the BFREGs which are handled by the kernel. 928 * BFREGs of UARs allocated dynamically are handled by user. 929 */ 930 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 931 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 932 } 933 934 static int create_kernel_qp(struct mlx5_ib_dev *dev, 935 struct ib_qp_init_attr *init_attr, 936 struct mlx5_ib_qp *qp, 937 u32 **in, int *inlen, 938 struct mlx5_ib_qp_base *base) 939 { 940 int uar_index; 941 void *qpc; 942 int err; 943 944 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 945 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 946 IB_QP_CREATE_IPOIB_UD_LSO | 947 IB_QP_CREATE_NETIF_QP | 948 mlx5_ib_create_qp_sqpn_qp1())) 949 return -EINVAL; 950 951 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 952 qp->bf.bfreg = &dev->fp_bfreg; 953 else 954 qp->bf.bfreg = &dev->bfreg; 955 956 /* We need to divide by two since each register is comprised of 957 * two buffers of identical size, namely odd and even 958 */ 959 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 960 uar_index = qp->bf.bfreg->index; 961 962 err = calc_sq_size(dev, init_attr, qp); 963 if (err < 0) { 964 mlx5_ib_dbg(dev, "err %d\n", err); 965 return err; 966 } 967 968 qp->rq.offset = 0; 969 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 970 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 971 972 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 973 if (err) { 974 mlx5_ib_dbg(dev, "err %d\n", err); 975 return err; 976 } 977 978 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 979 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 980 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 981 *in = kvzalloc(*inlen, GFP_KERNEL); 982 if (!*in) { 983 err = -ENOMEM; 984 goto err_buf; 985 } 986 987 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 988 MLX5_SET(qpc, qpc, uar_page, uar_index); 989 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 990 991 /* Set "fast registration enabled" for all kernel QPs */ 992 MLX5_SET(qpc, qpc, fre, 1); 993 MLX5_SET(qpc, qpc, rlky, 1); 994 995 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 996 MLX5_SET(qpc, qpc, deth_sqpn, 1); 997 qp->flags |= MLX5_IB_QP_SQPN_QP1; 998 } 999 1000 mlx5_fill_page_array(&qp->buf, 1001 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 1002 1003 err = mlx5_db_alloc(dev->mdev, &qp->db); 1004 if (err) { 1005 mlx5_ib_dbg(dev, "err %d\n", err); 1006 goto err_free; 1007 } 1008 1009 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1010 sizeof(*qp->sq.wrid), GFP_KERNEL); 1011 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1012 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1013 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1014 sizeof(*qp->rq.wrid), GFP_KERNEL); 1015 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1016 sizeof(*qp->sq.w_list), GFP_KERNEL); 1017 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1018 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1019 1020 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1021 !qp->sq.w_list || !qp->sq.wqe_head) { 1022 err = -ENOMEM; 1023 goto err_wrid; 1024 } 1025 qp->create_type = MLX5_QP_KERNEL; 1026 1027 return 0; 1028 1029 err_wrid: 1030 kvfree(qp->sq.wqe_head); 1031 kvfree(qp->sq.w_list); 1032 kvfree(qp->sq.wrid); 1033 kvfree(qp->sq.wr_data); 1034 kvfree(qp->rq.wrid); 1035 mlx5_db_free(dev->mdev, &qp->db); 1036 1037 err_free: 1038 kvfree(*in); 1039 1040 err_buf: 1041 mlx5_buf_free(dev->mdev, &qp->buf); 1042 return err; 1043 } 1044 1045 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1046 { 1047 kvfree(qp->sq.wqe_head); 1048 kvfree(qp->sq.w_list); 1049 kvfree(qp->sq.wrid); 1050 kvfree(qp->sq.wr_data); 1051 kvfree(qp->rq.wrid); 1052 mlx5_db_free(dev->mdev, &qp->db); 1053 mlx5_buf_free(dev->mdev, &qp->buf); 1054 } 1055 1056 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1057 { 1058 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1059 (attr->qp_type == MLX5_IB_QPT_DCI) || 1060 (attr->qp_type == IB_QPT_XRC_INI)) 1061 return MLX5_SRQ_RQ; 1062 else if (!qp->has_rq) 1063 return MLX5_ZERO_LEN_RQ; 1064 else 1065 return MLX5_NON_ZERO_RQ; 1066 } 1067 1068 static int is_connected(enum ib_qp_type qp_type) 1069 { 1070 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1071 return 1; 1072 1073 return 0; 1074 } 1075 1076 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1077 struct mlx5_ib_qp *qp, 1078 struct mlx5_ib_sq *sq, u32 tdn) 1079 { 1080 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1081 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1082 1083 MLX5_SET(tisc, tisc, transport_domain, tdn); 1084 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1085 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1086 1087 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1088 } 1089 1090 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1091 struct mlx5_ib_sq *sq) 1092 { 1093 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1094 } 1095 1096 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1097 struct mlx5_ib_sq *sq) 1098 { 1099 if (sq->flow_rule) 1100 mlx5_del_flow_rules(sq->flow_rule); 1101 } 1102 1103 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1104 struct mlx5_ib_sq *sq, void *qpin, 1105 struct ib_pd *pd) 1106 { 1107 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1108 __be64 *pas; 1109 void *in; 1110 void *sqc; 1111 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1112 void *wq; 1113 int inlen; 1114 int err; 1115 int page_shift = 0; 1116 int npages; 1117 int ncont = 0; 1118 u32 offset = 0; 1119 1120 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1121 &sq->ubuffer.umem, &npages, &page_shift, 1122 &ncont, &offset); 1123 if (err) 1124 return err; 1125 1126 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1127 in = kvzalloc(inlen, GFP_KERNEL); 1128 if (!in) { 1129 err = -ENOMEM; 1130 goto err_umem; 1131 } 1132 1133 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1134 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1135 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1136 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1137 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1138 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1139 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1140 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1141 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1142 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1143 MLX5_CAP_ETH(dev->mdev, swp)) 1144 MLX5_SET(sqc, sqc, allow_swp, 1); 1145 1146 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1147 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1148 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1149 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1150 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1151 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1152 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1153 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1154 MLX5_SET(wq, wq, page_offset, offset); 1155 1156 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1157 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1158 1159 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1160 1161 kvfree(in); 1162 1163 if (err) 1164 goto err_umem; 1165 1166 err = create_flow_rule_vport_sq(dev, sq); 1167 if (err) 1168 goto err_flow; 1169 1170 return 0; 1171 1172 err_flow: 1173 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1174 1175 err_umem: 1176 ib_umem_release(sq->ubuffer.umem); 1177 sq->ubuffer.umem = NULL; 1178 1179 return err; 1180 } 1181 1182 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1183 struct mlx5_ib_sq *sq) 1184 { 1185 destroy_flow_rule_vport_sq(dev, sq); 1186 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1187 ib_umem_release(sq->ubuffer.umem); 1188 } 1189 1190 static size_t get_rq_pas_size(void *qpc) 1191 { 1192 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1193 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1194 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1195 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1196 u32 po_quanta = 1 << (log_page_size - 6); 1197 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1198 u32 page_size = 1 << log_page_size; 1199 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1200 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1201 1202 return rq_num_pas * sizeof(u64); 1203 } 1204 1205 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1206 struct mlx5_ib_rq *rq, void *qpin, 1207 size_t qpinlen) 1208 { 1209 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1210 __be64 *pas; 1211 __be64 *qp_pas; 1212 void *in; 1213 void *rqc; 1214 void *wq; 1215 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1216 size_t rq_pas_size = get_rq_pas_size(qpc); 1217 size_t inlen; 1218 int err; 1219 1220 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1221 return -EINVAL; 1222 1223 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1224 in = kvzalloc(inlen, GFP_KERNEL); 1225 if (!in) 1226 return -ENOMEM; 1227 1228 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1229 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1230 MLX5_SET(rqc, rqc, vsd, 1); 1231 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1232 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1233 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1234 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1235 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1236 1237 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1238 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1239 1240 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1241 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1242 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1243 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1244 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1245 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1246 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1247 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1248 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1249 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1250 1251 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1252 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1253 memcpy(pas, qp_pas, rq_pas_size); 1254 1255 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1256 1257 kvfree(in); 1258 1259 return err; 1260 } 1261 1262 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1263 struct mlx5_ib_rq *rq) 1264 { 1265 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1266 } 1267 1268 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1269 { 1270 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1271 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1272 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1273 } 1274 1275 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1276 struct mlx5_ib_rq *rq, u32 tdn, 1277 bool tunnel_offload_en) 1278 { 1279 u32 *in; 1280 void *tirc; 1281 int inlen; 1282 int err; 1283 1284 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1285 in = kvzalloc(inlen, GFP_KERNEL); 1286 if (!in) 1287 return -ENOMEM; 1288 1289 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1290 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1291 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1292 MLX5_SET(tirc, tirc, transport_domain, tdn); 1293 if (tunnel_offload_en) 1294 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1295 1296 if (dev->rep) 1297 MLX5_SET(tirc, tirc, self_lb_block, 1298 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1299 1300 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1301 1302 kvfree(in); 1303 1304 return err; 1305 } 1306 1307 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1308 struct mlx5_ib_rq *rq) 1309 { 1310 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1311 } 1312 1313 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1314 u32 *in, size_t inlen, 1315 struct ib_pd *pd) 1316 { 1317 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1318 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1319 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1320 struct ib_uobject *uobj = pd->uobject; 1321 struct ib_ucontext *ucontext = uobj->context; 1322 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1323 int err; 1324 u32 tdn = mucontext->tdn; 1325 1326 if (qp->sq.wqe_cnt) { 1327 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1328 if (err) 1329 return err; 1330 1331 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1332 if (err) 1333 goto err_destroy_tis; 1334 1335 sq->base.container_mibqp = qp; 1336 sq->base.mqp.event = mlx5_ib_qp_event; 1337 } 1338 1339 if (qp->rq.wqe_cnt) { 1340 rq->base.container_mibqp = qp; 1341 1342 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1343 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1344 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1345 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1346 err = create_raw_packet_qp_rq(dev, rq, in, inlen); 1347 if (err) 1348 goto err_destroy_sq; 1349 1350 1351 err = create_raw_packet_qp_tir(dev, rq, tdn, 1352 qp->tunnel_offload_en); 1353 if (err) 1354 goto err_destroy_rq; 1355 } 1356 1357 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1358 rq->base.mqp.qpn; 1359 1360 return 0; 1361 1362 err_destroy_rq: 1363 destroy_raw_packet_qp_rq(dev, rq); 1364 err_destroy_sq: 1365 if (!qp->sq.wqe_cnt) 1366 return err; 1367 destroy_raw_packet_qp_sq(dev, sq); 1368 err_destroy_tis: 1369 destroy_raw_packet_qp_tis(dev, sq); 1370 1371 return err; 1372 } 1373 1374 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1375 struct mlx5_ib_qp *qp) 1376 { 1377 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1378 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1379 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1380 1381 if (qp->rq.wqe_cnt) { 1382 destroy_raw_packet_qp_tir(dev, rq); 1383 destroy_raw_packet_qp_rq(dev, rq); 1384 } 1385 1386 if (qp->sq.wqe_cnt) { 1387 destroy_raw_packet_qp_sq(dev, sq); 1388 destroy_raw_packet_qp_tis(dev, sq); 1389 } 1390 } 1391 1392 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1393 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1394 { 1395 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1396 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1397 1398 sq->sq = &qp->sq; 1399 rq->rq = &qp->rq; 1400 sq->doorbell = &qp->db; 1401 rq->doorbell = &qp->db; 1402 } 1403 1404 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1405 { 1406 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1407 } 1408 1409 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1410 struct ib_pd *pd, 1411 struct ib_qp_init_attr *init_attr, 1412 struct ib_udata *udata) 1413 { 1414 struct ib_uobject *uobj = pd->uobject; 1415 struct ib_ucontext *ucontext = uobj->context; 1416 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1417 struct mlx5_ib_create_qp_resp resp = {}; 1418 int inlen; 1419 int err; 1420 u32 *in; 1421 void *tirc; 1422 void *hfso; 1423 u32 selected_fields = 0; 1424 u32 outer_l4; 1425 size_t min_resp_len; 1426 u32 tdn = mucontext->tdn; 1427 struct mlx5_ib_create_qp_rss ucmd = {}; 1428 size_t required_cmd_sz; 1429 1430 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1431 return -EOPNOTSUPP; 1432 1433 if (init_attr->create_flags || init_attr->send_cq) 1434 return -EINVAL; 1435 1436 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1437 if (udata->outlen < min_resp_len) 1438 return -EINVAL; 1439 1440 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1441 if (udata->inlen < required_cmd_sz) { 1442 mlx5_ib_dbg(dev, "invalid inlen\n"); 1443 return -EINVAL; 1444 } 1445 1446 if (udata->inlen > sizeof(ucmd) && 1447 !ib_is_udata_cleared(udata, sizeof(ucmd), 1448 udata->inlen - sizeof(ucmd))) { 1449 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1450 return -EOPNOTSUPP; 1451 } 1452 1453 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1454 mlx5_ib_dbg(dev, "copy failed\n"); 1455 return -EFAULT; 1456 } 1457 1458 if (ucmd.comp_mask) { 1459 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1460 return -EOPNOTSUPP; 1461 } 1462 1463 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1464 mlx5_ib_dbg(dev, "invalid flags\n"); 1465 return -EOPNOTSUPP; 1466 } 1467 1468 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1469 !tunnel_offload_supported(dev->mdev)) { 1470 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1471 return -EOPNOTSUPP; 1472 } 1473 1474 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1475 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1476 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1477 return -EOPNOTSUPP; 1478 } 1479 1480 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1481 if (err) { 1482 mlx5_ib_dbg(dev, "copy failed\n"); 1483 return -EINVAL; 1484 } 1485 1486 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1487 in = kvzalloc(inlen, GFP_KERNEL); 1488 if (!in) 1489 return -ENOMEM; 1490 1491 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1492 MLX5_SET(tirc, tirc, disp_type, 1493 MLX5_TIRC_DISP_TYPE_INDIRECT); 1494 MLX5_SET(tirc, tirc, indirect_table, 1495 init_attr->rwq_ind_tbl->ind_tbl_num); 1496 MLX5_SET(tirc, tirc, transport_domain, tdn); 1497 1498 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1499 1500 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1501 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1502 1503 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1504 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1505 else 1506 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1507 1508 switch (ucmd.rx_hash_function) { 1509 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1510 { 1511 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1512 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1513 1514 if (len != ucmd.rx_key_len) { 1515 err = -EINVAL; 1516 goto err; 1517 } 1518 1519 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1520 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1521 memcpy(rss_key, ucmd.rx_hash_key, len); 1522 break; 1523 } 1524 default: 1525 err = -EOPNOTSUPP; 1526 goto err; 1527 } 1528 1529 if (!ucmd.rx_hash_fields_mask) { 1530 /* special case when this TIR serves as steering entry without hashing */ 1531 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1532 goto create_tir; 1533 err = -EINVAL; 1534 goto err; 1535 } 1536 1537 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1538 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1539 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1540 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1541 err = -EINVAL; 1542 goto err; 1543 } 1544 1545 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1546 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1547 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1548 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1549 MLX5_L3_PROT_TYPE_IPV4); 1550 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1551 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1552 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1553 MLX5_L3_PROT_TYPE_IPV6); 1554 1555 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1556 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1557 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1558 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1559 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1560 1561 /* Check that only one l4 protocol is set */ 1562 if (outer_l4 & (outer_l4 - 1)) { 1563 err = -EINVAL; 1564 goto err; 1565 } 1566 1567 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1568 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1569 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1570 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1571 MLX5_L4_PROT_TYPE_TCP); 1572 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1573 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1574 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1575 MLX5_L4_PROT_TYPE_UDP); 1576 1577 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1578 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1579 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1580 1581 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1582 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1583 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1584 1585 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1586 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1587 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1588 1589 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1590 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1591 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1592 1593 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1594 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1595 1596 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1597 1598 create_tir: 1599 if (dev->rep) 1600 MLX5_SET(tirc, tirc, self_lb_block, 1601 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1602 1603 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1604 1605 if (err) 1606 goto err; 1607 1608 kvfree(in); 1609 /* qpn is reserved for that QP */ 1610 qp->trans_qp.base.mqp.qpn = 0; 1611 qp->flags |= MLX5_IB_QP_RSS; 1612 return 0; 1613 1614 err: 1615 kvfree(in); 1616 return err; 1617 } 1618 1619 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1620 struct ib_qp_init_attr *init_attr, 1621 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1622 { 1623 struct mlx5_ib_resources *devr = &dev->devr; 1624 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1625 struct mlx5_core_dev *mdev = dev->mdev; 1626 struct mlx5_ib_create_qp_resp resp; 1627 struct mlx5_ib_cq *send_cq; 1628 struct mlx5_ib_cq *recv_cq; 1629 unsigned long flags; 1630 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1631 struct mlx5_ib_create_qp ucmd; 1632 struct mlx5_ib_qp_base *base; 1633 int mlx5_st; 1634 void *qpc; 1635 u32 *in; 1636 int err; 1637 1638 mutex_init(&qp->mutex); 1639 spin_lock_init(&qp->sq.lock); 1640 spin_lock_init(&qp->rq.lock); 1641 1642 mlx5_st = to_mlx5_st(init_attr->qp_type); 1643 if (mlx5_st < 0) 1644 return -EINVAL; 1645 1646 if (init_attr->rwq_ind_tbl) { 1647 if (!udata) 1648 return -ENOSYS; 1649 1650 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1651 return err; 1652 } 1653 1654 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1655 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1656 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1657 return -EINVAL; 1658 } else { 1659 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1660 } 1661 } 1662 1663 if (init_attr->create_flags & 1664 (IB_QP_CREATE_CROSS_CHANNEL | 1665 IB_QP_CREATE_MANAGED_SEND | 1666 IB_QP_CREATE_MANAGED_RECV)) { 1667 if (!MLX5_CAP_GEN(mdev, cd)) { 1668 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1669 return -EINVAL; 1670 } 1671 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1672 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1673 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1674 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1675 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1676 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1677 } 1678 1679 if (init_attr->qp_type == IB_QPT_UD && 1680 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1681 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1682 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1683 return -EOPNOTSUPP; 1684 } 1685 1686 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1687 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1688 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1689 return -EOPNOTSUPP; 1690 } 1691 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1692 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1693 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1694 return -EOPNOTSUPP; 1695 } 1696 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1697 } 1698 1699 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1700 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1701 1702 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1703 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1704 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1705 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1706 return -EOPNOTSUPP; 1707 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1708 } 1709 1710 if (pd && pd->uobject) { 1711 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1712 mlx5_ib_dbg(dev, "copy failed\n"); 1713 return -EFAULT; 1714 } 1715 1716 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1717 &ucmd, udata->inlen, &uidx); 1718 if (err) 1719 return err; 1720 1721 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1722 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1723 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1724 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1725 !tunnel_offload_supported(mdev)) { 1726 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1727 return -EOPNOTSUPP; 1728 } 1729 qp->tunnel_offload_en = true; 1730 } 1731 1732 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1733 if (init_attr->qp_type != IB_QPT_UD || 1734 (MLX5_CAP_GEN(dev->mdev, port_type) != 1735 MLX5_CAP_PORT_TYPE_IB) || 1736 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1737 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1738 return -EOPNOTSUPP; 1739 } 1740 1741 qp->flags |= MLX5_IB_QP_UNDERLAY; 1742 qp->underlay_qpn = init_attr->source_qpn; 1743 } 1744 } else { 1745 qp->wq_sig = !!wq_signature; 1746 } 1747 1748 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1749 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1750 &qp->raw_packet_qp.rq.base : 1751 &qp->trans_qp.base; 1752 1753 qp->has_rq = qp_has_rq(init_attr); 1754 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1755 qp, (pd && pd->uobject) ? &ucmd : NULL); 1756 if (err) { 1757 mlx5_ib_dbg(dev, "err %d\n", err); 1758 return err; 1759 } 1760 1761 if (pd) { 1762 if (pd->uobject) { 1763 __u32 max_wqes = 1764 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1765 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1766 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1767 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1768 mlx5_ib_dbg(dev, "invalid rq params\n"); 1769 return -EINVAL; 1770 } 1771 if (ucmd.sq_wqe_count > max_wqes) { 1772 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1773 ucmd.sq_wqe_count, max_wqes); 1774 return -EINVAL; 1775 } 1776 if (init_attr->create_flags & 1777 mlx5_ib_create_qp_sqpn_qp1()) { 1778 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1779 return -EINVAL; 1780 } 1781 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1782 &resp, &inlen, base); 1783 if (err) 1784 mlx5_ib_dbg(dev, "err %d\n", err); 1785 } else { 1786 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1787 base); 1788 if (err) 1789 mlx5_ib_dbg(dev, "err %d\n", err); 1790 } 1791 1792 if (err) 1793 return err; 1794 } else { 1795 in = kvzalloc(inlen, GFP_KERNEL); 1796 if (!in) 1797 return -ENOMEM; 1798 1799 qp->create_type = MLX5_QP_EMPTY; 1800 } 1801 1802 if (is_sqp(init_attr->qp_type)) 1803 qp->port = init_attr->port_num; 1804 1805 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1806 1807 MLX5_SET(qpc, qpc, st, mlx5_st); 1808 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1809 1810 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1811 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1812 else 1813 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1814 1815 1816 if (qp->wq_sig) 1817 MLX5_SET(qpc, qpc, wq_signature, 1); 1818 1819 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1820 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1821 1822 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1823 MLX5_SET(qpc, qpc, cd_master, 1); 1824 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1825 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1826 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1827 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1828 1829 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1830 int rcqe_sz; 1831 int scqe_sz; 1832 1833 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1834 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1835 1836 if (rcqe_sz == 128) 1837 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1838 else 1839 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1840 1841 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1842 if (scqe_sz == 128) 1843 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1844 else 1845 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1846 } 1847 } 1848 1849 if (qp->rq.wqe_cnt) { 1850 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1851 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1852 } 1853 1854 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1855 1856 if (qp->sq.wqe_cnt) { 1857 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1858 } else { 1859 MLX5_SET(qpc, qpc, no_sq, 1); 1860 if (init_attr->srq && 1861 init_attr->srq->srq_type == IB_SRQT_TM) 1862 MLX5_SET(qpc, qpc, offload_type, 1863 MLX5_QPC_OFFLOAD_TYPE_RNDV); 1864 } 1865 1866 /* Set default resources */ 1867 switch (init_attr->qp_type) { 1868 case IB_QPT_XRC_TGT: 1869 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1870 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1871 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1872 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1873 break; 1874 case IB_QPT_XRC_INI: 1875 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1876 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1877 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1878 break; 1879 default: 1880 if (init_attr->srq) { 1881 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1882 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1883 } else { 1884 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1885 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1886 } 1887 } 1888 1889 if (init_attr->send_cq) 1890 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1891 1892 if (init_attr->recv_cq) 1893 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1894 1895 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1896 1897 /* 0xffffff means we ask to work with cqe version 0 */ 1898 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1899 MLX5_SET(qpc, qpc, user_index, uidx); 1900 1901 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1902 if (init_attr->qp_type == IB_QPT_UD && 1903 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1904 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1905 qp->flags |= MLX5_IB_QP_LSO; 1906 } 1907 1908 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1909 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 1910 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 1911 err = -EOPNOTSUPP; 1912 goto err; 1913 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1914 MLX5_SET(qpc, qpc, end_padding_mode, 1915 MLX5_WQ_END_PAD_MODE_ALIGN); 1916 } else { 1917 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 1918 } 1919 } 1920 1921 if (inlen < 0) { 1922 err = -EINVAL; 1923 goto err; 1924 } 1925 1926 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1927 qp->flags & MLX5_IB_QP_UNDERLAY) { 1928 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1929 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1930 err = create_raw_packet_qp(dev, qp, in, inlen, pd); 1931 } else { 1932 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1933 } 1934 1935 if (err) { 1936 mlx5_ib_dbg(dev, "create qp failed\n"); 1937 goto err_create; 1938 } 1939 1940 kvfree(in); 1941 1942 base->container_mibqp = qp; 1943 base->mqp.event = mlx5_ib_qp_event; 1944 1945 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1946 &send_cq, &recv_cq); 1947 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1948 mlx5_ib_lock_cqs(send_cq, recv_cq); 1949 /* Maintain device to QPs access, needed for further handling via reset 1950 * flow 1951 */ 1952 list_add_tail(&qp->qps_list, &dev->qp_list); 1953 /* Maintain CQ to QPs access, needed for further handling via reset flow 1954 */ 1955 if (send_cq) 1956 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1957 if (recv_cq) 1958 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1959 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1960 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1961 1962 return 0; 1963 1964 err_create: 1965 if (qp->create_type == MLX5_QP_USER) 1966 destroy_qp_user(dev, pd, qp, base); 1967 else if (qp->create_type == MLX5_QP_KERNEL) 1968 destroy_qp_kernel(dev, qp); 1969 1970 err: 1971 kvfree(in); 1972 return err; 1973 } 1974 1975 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1976 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1977 { 1978 if (send_cq) { 1979 if (recv_cq) { 1980 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1981 spin_lock(&send_cq->lock); 1982 spin_lock_nested(&recv_cq->lock, 1983 SINGLE_DEPTH_NESTING); 1984 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1985 spin_lock(&send_cq->lock); 1986 __acquire(&recv_cq->lock); 1987 } else { 1988 spin_lock(&recv_cq->lock); 1989 spin_lock_nested(&send_cq->lock, 1990 SINGLE_DEPTH_NESTING); 1991 } 1992 } else { 1993 spin_lock(&send_cq->lock); 1994 __acquire(&recv_cq->lock); 1995 } 1996 } else if (recv_cq) { 1997 spin_lock(&recv_cq->lock); 1998 __acquire(&send_cq->lock); 1999 } else { 2000 __acquire(&send_cq->lock); 2001 __acquire(&recv_cq->lock); 2002 } 2003 } 2004 2005 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2006 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2007 { 2008 if (send_cq) { 2009 if (recv_cq) { 2010 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2011 spin_unlock(&recv_cq->lock); 2012 spin_unlock(&send_cq->lock); 2013 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2014 __release(&recv_cq->lock); 2015 spin_unlock(&send_cq->lock); 2016 } else { 2017 spin_unlock(&send_cq->lock); 2018 spin_unlock(&recv_cq->lock); 2019 } 2020 } else { 2021 __release(&recv_cq->lock); 2022 spin_unlock(&send_cq->lock); 2023 } 2024 } else if (recv_cq) { 2025 __release(&send_cq->lock); 2026 spin_unlock(&recv_cq->lock); 2027 } else { 2028 __release(&recv_cq->lock); 2029 __release(&send_cq->lock); 2030 } 2031 } 2032 2033 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2034 { 2035 return to_mpd(qp->ibqp.pd); 2036 } 2037 2038 static void get_cqs(enum ib_qp_type qp_type, 2039 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2040 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2041 { 2042 switch (qp_type) { 2043 case IB_QPT_XRC_TGT: 2044 *send_cq = NULL; 2045 *recv_cq = NULL; 2046 break; 2047 case MLX5_IB_QPT_REG_UMR: 2048 case IB_QPT_XRC_INI: 2049 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2050 *recv_cq = NULL; 2051 break; 2052 2053 case IB_QPT_SMI: 2054 case MLX5_IB_QPT_HW_GSI: 2055 case IB_QPT_RC: 2056 case IB_QPT_UC: 2057 case IB_QPT_UD: 2058 case IB_QPT_RAW_IPV6: 2059 case IB_QPT_RAW_ETHERTYPE: 2060 case IB_QPT_RAW_PACKET: 2061 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2062 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2063 break; 2064 2065 case IB_QPT_MAX: 2066 default: 2067 *send_cq = NULL; 2068 *recv_cq = NULL; 2069 break; 2070 } 2071 } 2072 2073 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2074 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2075 u8 lag_tx_affinity); 2076 2077 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2078 { 2079 struct mlx5_ib_cq *send_cq, *recv_cq; 2080 struct mlx5_ib_qp_base *base; 2081 unsigned long flags; 2082 int err; 2083 2084 if (qp->ibqp.rwq_ind_tbl) { 2085 destroy_rss_raw_qp_tir(dev, qp); 2086 return; 2087 } 2088 2089 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2090 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2091 &qp->raw_packet_qp.rq.base : 2092 &qp->trans_qp.base; 2093 2094 if (qp->state != IB_QPS_RESET) { 2095 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2096 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2097 err = mlx5_core_qp_modify(dev->mdev, 2098 MLX5_CMD_OP_2RST_QP, 0, 2099 NULL, &base->mqp); 2100 } else { 2101 struct mlx5_modify_raw_qp_param raw_qp_param = { 2102 .operation = MLX5_CMD_OP_2RST_QP 2103 }; 2104 2105 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2106 } 2107 if (err) 2108 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2109 base->mqp.qpn); 2110 } 2111 2112 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2113 &send_cq, &recv_cq); 2114 2115 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2116 mlx5_ib_lock_cqs(send_cq, recv_cq); 2117 /* del from lists under both locks above to protect reset flow paths */ 2118 list_del(&qp->qps_list); 2119 if (send_cq) 2120 list_del(&qp->cq_send_list); 2121 2122 if (recv_cq) 2123 list_del(&qp->cq_recv_list); 2124 2125 if (qp->create_type == MLX5_QP_KERNEL) { 2126 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2127 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2128 if (send_cq != recv_cq) 2129 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2130 NULL); 2131 } 2132 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2133 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2134 2135 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2136 qp->flags & MLX5_IB_QP_UNDERLAY) { 2137 destroy_raw_packet_qp(dev, qp); 2138 } else { 2139 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2140 if (err) 2141 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2142 base->mqp.qpn); 2143 } 2144 2145 if (qp->create_type == MLX5_QP_KERNEL) 2146 destroy_qp_kernel(dev, qp); 2147 else if (qp->create_type == MLX5_QP_USER) 2148 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2149 } 2150 2151 static const char *ib_qp_type_str(enum ib_qp_type type) 2152 { 2153 switch (type) { 2154 case IB_QPT_SMI: 2155 return "IB_QPT_SMI"; 2156 case IB_QPT_GSI: 2157 return "IB_QPT_GSI"; 2158 case IB_QPT_RC: 2159 return "IB_QPT_RC"; 2160 case IB_QPT_UC: 2161 return "IB_QPT_UC"; 2162 case IB_QPT_UD: 2163 return "IB_QPT_UD"; 2164 case IB_QPT_RAW_IPV6: 2165 return "IB_QPT_RAW_IPV6"; 2166 case IB_QPT_RAW_ETHERTYPE: 2167 return "IB_QPT_RAW_ETHERTYPE"; 2168 case IB_QPT_XRC_INI: 2169 return "IB_QPT_XRC_INI"; 2170 case IB_QPT_XRC_TGT: 2171 return "IB_QPT_XRC_TGT"; 2172 case IB_QPT_RAW_PACKET: 2173 return "IB_QPT_RAW_PACKET"; 2174 case MLX5_IB_QPT_REG_UMR: 2175 return "MLX5_IB_QPT_REG_UMR"; 2176 case IB_QPT_DRIVER: 2177 return "IB_QPT_DRIVER"; 2178 case IB_QPT_MAX: 2179 default: 2180 return "Invalid QP type"; 2181 } 2182 } 2183 2184 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2185 struct ib_qp_init_attr *attr, 2186 struct mlx5_ib_create_qp *ucmd) 2187 { 2188 struct mlx5_ib_qp *qp; 2189 int err = 0; 2190 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2191 void *dctc; 2192 2193 if (!attr->srq || !attr->recv_cq) 2194 return ERR_PTR(-EINVAL); 2195 2196 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2197 ucmd, sizeof(*ucmd), &uidx); 2198 if (err) 2199 return ERR_PTR(err); 2200 2201 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2202 if (!qp) 2203 return ERR_PTR(-ENOMEM); 2204 2205 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2206 if (!qp->dct.in) { 2207 err = -ENOMEM; 2208 goto err_free; 2209 } 2210 2211 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2212 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2213 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2214 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2215 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2216 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2217 MLX5_SET(dctc, dctc, user_index, uidx); 2218 2219 qp->state = IB_QPS_RESET; 2220 2221 return &qp->ibqp; 2222 err_free: 2223 kfree(qp); 2224 return ERR_PTR(err); 2225 } 2226 2227 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2228 struct ib_qp_init_attr *init_attr, 2229 struct mlx5_ib_create_qp *ucmd, 2230 struct ib_udata *udata) 2231 { 2232 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2233 int err; 2234 2235 if (!udata) 2236 return -EINVAL; 2237 2238 if (udata->inlen < sizeof(*ucmd)) { 2239 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2240 return -EINVAL; 2241 } 2242 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2243 if (err) 2244 return err; 2245 2246 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2247 init_attr->qp_type = MLX5_IB_QPT_DCI; 2248 } else { 2249 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2250 init_attr->qp_type = MLX5_IB_QPT_DCT; 2251 } else { 2252 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2253 return -EINVAL; 2254 } 2255 } 2256 2257 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2258 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2259 return -EOPNOTSUPP; 2260 } 2261 2262 return 0; 2263 } 2264 2265 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2266 struct ib_qp_init_attr *verbs_init_attr, 2267 struct ib_udata *udata) 2268 { 2269 struct mlx5_ib_dev *dev; 2270 struct mlx5_ib_qp *qp; 2271 u16 xrcdn = 0; 2272 int err; 2273 struct ib_qp_init_attr mlx_init_attr; 2274 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2275 2276 if (pd) { 2277 dev = to_mdev(pd->device); 2278 2279 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2280 if (!pd->uobject) { 2281 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2282 return ERR_PTR(-EINVAL); 2283 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2284 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2285 return ERR_PTR(-EINVAL); 2286 } 2287 } 2288 } else { 2289 /* being cautious here */ 2290 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2291 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2292 pr_warn("%s: no PD for transport %s\n", __func__, 2293 ib_qp_type_str(init_attr->qp_type)); 2294 return ERR_PTR(-EINVAL); 2295 } 2296 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2297 } 2298 2299 if (init_attr->qp_type == IB_QPT_DRIVER) { 2300 struct mlx5_ib_create_qp ucmd; 2301 2302 init_attr = &mlx_init_attr; 2303 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2304 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2305 if (err) 2306 return ERR_PTR(err); 2307 2308 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2309 if (init_attr->cap.max_recv_wr || 2310 init_attr->cap.max_recv_sge) { 2311 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2312 return ERR_PTR(-EINVAL); 2313 } 2314 } else { 2315 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2316 } 2317 } 2318 2319 switch (init_attr->qp_type) { 2320 case IB_QPT_XRC_TGT: 2321 case IB_QPT_XRC_INI: 2322 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2323 mlx5_ib_dbg(dev, "XRC not supported\n"); 2324 return ERR_PTR(-ENOSYS); 2325 } 2326 init_attr->recv_cq = NULL; 2327 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2328 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2329 init_attr->send_cq = NULL; 2330 } 2331 2332 /* fall through */ 2333 case IB_QPT_RAW_PACKET: 2334 case IB_QPT_RC: 2335 case IB_QPT_UC: 2336 case IB_QPT_UD: 2337 case IB_QPT_SMI: 2338 case MLX5_IB_QPT_HW_GSI: 2339 case MLX5_IB_QPT_REG_UMR: 2340 case MLX5_IB_QPT_DCI: 2341 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2342 if (!qp) 2343 return ERR_PTR(-ENOMEM); 2344 2345 err = create_qp_common(dev, pd, init_attr, udata, qp); 2346 if (err) { 2347 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2348 kfree(qp); 2349 return ERR_PTR(err); 2350 } 2351 2352 if (is_qp0(init_attr->qp_type)) 2353 qp->ibqp.qp_num = 0; 2354 else if (is_qp1(init_attr->qp_type)) 2355 qp->ibqp.qp_num = 1; 2356 else 2357 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2358 2359 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2360 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2361 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2362 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2363 2364 qp->trans_qp.xrcdn = xrcdn; 2365 2366 break; 2367 2368 case IB_QPT_GSI: 2369 return mlx5_ib_gsi_create_qp(pd, init_attr); 2370 2371 case IB_QPT_RAW_IPV6: 2372 case IB_QPT_RAW_ETHERTYPE: 2373 case IB_QPT_MAX: 2374 default: 2375 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2376 init_attr->qp_type); 2377 /* Don't support raw QPs */ 2378 return ERR_PTR(-EINVAL); 2379 } 2380 2381 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2382 qp->qp_sub_type = init_attr->qp_type; 2383 2384 return &qp->ibqp; 2385 } 2386 2387 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2388 { 2389 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2390 2391 if (mqp->state == IB_QPS_RTR) { 2392 int err; 2393 2394 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2395 if (err) { 2396 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2397 return err; 2398 } 2399 } 2400 2401 kfree(mqp->dct.in); 2402 kfree(mqp); 2403 return 0; 2404 } 2405 2406 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2407 { 2408 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2409 struct mlx5_ib_qp *mqp = to_mqp(qp); 2410 2411 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2412 return mlx5_ib_gsi_destroy_qp(qp); 2413 2414 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2415 return mlx5_ib_destroy_dct(mqp); 2416 2417 destroy_qp_common(dev, mqp); 2418 2419 kfree(mqp); 2420 2421 return 0; 2422 } 2423 2424 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2425 int attr_mask) 2426 { 2427 u32 hw_access_flags = 0; 2428 u8 dest_rd_atomic; 2429 u32 access_flags; 2430 2431 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2432 dest_rd_atomic = attr->max_dest_rd_atomic; 2433 else 2434 dest_rd_atomic = qp->trans_qp.resp_depth; 2435 2436 if (attr_mask & IB_QP_ACCESS_FLAGS) 2437 access_flags = attr->qp_access_flags; 2438 else 2439 access_flags = qp->trans_qp.atomic_rd_en; 2440 2441 if (!dest_rd_atomic) 2442 access_flags &= IB_ACCESS_REMOTE_WRITE; 2443 2444 if (access_flags & IB_ACCESS_REMOTE_READ) 2445 hw_access_flags |= MLX5_QP_BIT_RRE; 2446 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2447 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2448 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2449 hw_access_flags |= MLX5_QP_BIT_RWE; 2450 2451 return cpu_to_be32(hw_access_flags); 2452 } 2453 2454 enum { 2455 MLX5_PATH_FLAG_FL = 1 << 0, 2456 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2457 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2458 }; 2459 2460 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2461 { 2462 if (rate == IB_RATE_PORT_CURRENT) 2463 return 0; 2464 2465 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) 2466 return -EINVAL; 2467 2468 while (rate != IB_RATE_PORT_CURRENT && 2469 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2470 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2471 --rate; 2472 2473 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2474 } 2475 2476 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2477 struct mlx5_ib_sq *sq, u8 sl) 2478 { 2479 void *in; 2480 void *tisc; 2481 int inlen; 2482 int err; 2483 2484 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2485 in = kvzalloc(inlen, GFP_KERNEL); 2486 if (!in) 2487 return -ENOMEM; 2488 2489 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2490 2491 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2492 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2493 2494 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2495 2496 kvfree(in); 2497 2498 return err; 2499 } 2500 2501 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2502 struct mlx5_ib_sq *sq, u8 tx_affinity) 2503 { 2504 void *in; 2505 void *tisc; 2506 int inlen; 2507 int err; 2508 2509 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2510 in = kvzalloc(inlen, GFP_KERNEL); 2511 if (!in) 2512 return -ENOMEM; 2513 2514 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2515 2516 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2517 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2518 2519 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2520 2521 kvfree(in); 2522 2523 return err; 2524 } 2525 2526 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2527 const struct rdma_ah_attr *ah, 2528 struct mlx5_qp_path *path, u8 port, int attr_mask, 2529 u32 path_flags, const struct ib_qp_attr *attr, 2530 bool alt) 2531 { 2532 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2533 int err; 2534 enum ib_gid_type gid_type; 2535 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2536 u8 sl = rdma_ah_get_sl(ah); 2537 2538 if (attr_mask & IB_QP_PKEY_INDEX) 2539 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2540 attr->pkey_index); 2541 2542 if (ah_flags & IB_AH_GRH) { 2543 if (grh->sgid_index >= 2544 dev->mdev->port_caps[port - 1].gid_table_len) { 2545 pr_err("sgid_index (%u) too large. max is %d\n", 2546 grh->sgid_index, 2547 dev->mdev->port_caps[port - 1].gid_table_len); 2548 return -EINVAL; 2549 } 2550 } 2551 2552 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2553 if (!(ah_flags & IB_AH_GRH)) 2554 return -EINVAL; 2555 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2556 &gid_type); 2557 if (err) 2558 return err; 2559 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2560 if (qp->ibqp.qp_type == IB_QPT_RC || 2561 qp->ibqp.qp_type == IB_QPT_UC || 2562 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2563 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2564 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2565 grh->sgid_index); 2566 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2567 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2568 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2569 } else { 2570 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2571 path->fl_free_ar |= 2572 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2573 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2574 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2575 if (ah_flags & IB_AH_GRH) 2576 path->grh_mlid |= 1 << 7; 2577 path->dci_cfi_prio_sl = sl & 0xf; 2578 } 2579 2580 if (ah_flags & IB_AH_GRH) { 2581 path->mgid_index = grh->sgid_index; 2582 path->hop_limit = grh->hop_limit; 2583 path->tclass_flowlabel = 2584 cpu_to_be32((grh->traffic_class << 20) | 2585 (grh->flow_label)); 2586 memcpy(path->rgid, grh->dgid.raw, 16); 2587 } 2588 2589 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2590 if (err < 0) 2591 return err; 2592 path->static_rate = err; 2593 path->port = port; 2594 2595 if (attr_mask & IB_QP_TIMEOUT) 2596 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2597 2598 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2599 return modify_raw_packet_eth_prio(dev->mdev, 2600 &qp->raw_packet_qp.sq, 2601 sl & 0xf); 2602 2603 return 0; 2604 } 2605 2606 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2607 [MLX5_QP_STATE_INIT] = { 2608 [MLX5_QP_STATE_INIT] = { 2609 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2610 MLX5_QP_OPTPAR_RAE | 2611 MLX5_QP_OPTPAR_RWE | 2612 MLX5_QP_OPTPAR_PKEY_INDEX | 2613 MLX5_QP_OPTPAR_PRI_PORT, 2614 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2615 MLX5_QP_OPTPAR_PKEY_INDEX | 2616 MLX5_QP_OPTPAR_PRI_PORT, 2617 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2618 MLX5_QP_OPTPAR_Q_KEY | 2619 MLX5_QP_OPTPAR_PRI_PORT, 2620 }, 2621 [MLX5_QP_STATE_RTR] = { 2622 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2623 MLX5_QP_OPTPAR_RRE | 2624 MLX5_QP_OPTPAR_RAE | 2625 MLX5_QP_OPTPAR_RWE | 2626 MLX5_QP_OPTPAR_PKEY_INDEX, 2627 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2628 MLX5_QP_OPTPAR_RWE | 2629 MLX5_QP_OPTPAR_PKEY_INDEX, 2630 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2631 MLX5_QP_OPTPAR_Q_KEY, 2632 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2633 MLX5_QP_OPTPAR_Q_KEY, 2634 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2635 MLX5_QP_OPTPAR_RRE | 2636 MLX5_QP_OPTPAR_RAE | 2637 MLX5_QP_OPTPAR_RWE | 2638 MLX5_QP_OPTPAR_PKEY_INDEX, 2639 }, 2640 }, 2641 [MLX5_QP_STATE_RTR] = { 2642 [MLX5_QP_STATE_RTS] = { 2643 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2644 MLX5_QP_OPTPAR_RRE | 2645 MLX5_QP_OPTPAR_RAE | 2646 MLX5_QP_OPTPAR_RWE | 2647 MLX5_QP_OPTPAR_PM_STATE | 2648 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2649 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2650 MLX5_QP_OPTPAR_RWE | 2651 MLX5_QP_OPTPAR_PM_STATE, 2652 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2653 }, 2654 }, 2655 [MLX5_QP_STATE_RTS] = { 2656 [MLX5_QP_STATE_RTS] = { 2657 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2658 MLX5_QP_OPTPAR_RAE | 2659 MLX5_QP_OPTPAR_RWE | 2660 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2661 MLX5_QP_OPTPAR_PM_STATE | 2662 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2663 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2664 MLX5_QP_OPTPAR_PM_STATE | 2665 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2666 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2667 MLX5_QP_OPTPAR_SRQN | 2668 MLX5_QP_OPTPAR_CQN_RCV, 2669 }, 2670 }, 2671 [MLX5_QP_STATE_SQER] = { 2672 [MLX5_QP_STATE_RTS] = { 2673 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2674 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2675 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2676 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2677 MLX5_QP_OPTPAR_RWE | 2678 MLX5_QP_OPTPAR_RAE | 2679 MLX5_QP_OPTPAR_RRE, 2680 }, 2681 }, 2682 }; 2683 2684 static int ib_nr_to_mlx5_nr(int ib_mask) 2685 { 2686 switch (ib_mask) { 2687 case IB_QP_STATE: 2688 return 0; 2689 case IB_QP_CUR_STATE: 2690 return 0; 2691 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2692 return 0; 2693 case IB_QP_ACCESS_FLAGS: 2694 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2695 MLX5_QP_OPTPAR_RAE; 2696 case IB_QP_PKEY_INDEX: 2697 return MLX5_QP_OPTPAR_PKEY_INDEX; 2698 case IB_QP_PORT: 2699 return MLX5_QP_OPTPAR_PRI_PORT; 2700 case IB_QP_QKEY: 2701 return MLX5_QP_OPTPAR_Q_KEY; 2702 case IB_QP_AV: 2703 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2704 MLX5_QP_OPTPAR_PRI_PORT; 2705 case IB_QP_PATH_MTU: 2706 return 0; 2707 case IB_QP_TIMEOUT: 2708 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2709 case IB_QP_RETRY_CNT: 2710 return MLX5_QP_OPTPAR_RETRY_COUNT; 2711 case IB_QP_RNR_RETRY: 2712 return MLX5_QP_OPTPAR_RNR_RETRY; 2713 case IB_QP_RQ_PSN: 2714 return 0; 2715 case IB_QP_MAX_QP_RD_ATOMIC: 2716 return MLX5_QP_OPTPAR_SRA_MAX; 2717 case IB_QP_ALT_PATH: 2718 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2719 case IB_QP_MIN_RNR_TIMER: 2720 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2721 case IB_QP_SQ_PSN: 2722 return 0; 2723 case IB_QP_MAX_DEST_RD_ATOMIC: 2724 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2725 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2726 case IB_QP_PATH_MIG_STATE: 2727 return MLX5_QP_OPTPAR_PM_STATE; 2728 case IB_QP_CAP: 2729 return 0; 2730 case IB_QP_DEST_QPN: 2731 return 0; 2732 } 2733 return 0; 2734 } 2735 2736 static int ib_mask_to_mlx5_opt(int ib_mask) 2737 { 2738 int result = 0; 2739 int i; 2740 2741 for (i = 0; i < 8 * sizeof(int); i++) { 2742 if ((1 << i) & ib_mask) 2743 result |= ib_nr_to_mlx5_nr(1 << i); 2744 } 2745 2746 return result; 2747 } 2748 2749 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2750 struct mlx5_ib_rq *rq, int new_state, 2751 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2752 { 2753 void *in; 2754 void *rqc; 2755 int inlen; 2756 int err; 2757 2758 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2759 in = kvzalloc(inlen, GFP_KERNEL); 2760 if (!in) 2761 return -ENOMEM; 2762 2763 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2764 2765 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2766 MLX5_SET(rqc, rqc, state, new_state); 2767 2768 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2769 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2770 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2771 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2772 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2773 } else 2774 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2775 dev->ib_dev.name); 2776 } 2777 2778 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2779 if (err) 2780 goto out; 2781 2782 rq->state = new_state; 2783 2784 out: 2785 kvfree(in); 2786 return err; 2787 } 2788 2789 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2790 struct mlx5_ib_sq *sq, 2791 int new_state, 2792 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2793 { 2794 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2795 struct mlx5_rate_limit old_rl = ibqp->rl; 2796 struct mlx5_rate_limit new_rl = old_rl; 2797 bool new_rate_added = false; 2798 u16 rl_index = 0; 2799 void *in; 2800 void *sqc; 2801 int inlen; 2802 int err; 2803 2804 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2805 in = kvzalloc(inlen, GFP_KERNEL); 2806 if (!in) 2807 return -ENOMEM; 2808 2809 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2810 2811 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2812 MLX5_SET(sqc, sqc, state, new_state); 2813 2814 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2815 if (new_state != MLX5_SQC_STATE_RDY) 2816 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2817 __func__); 2818 else 2819 new_rl = raw_qp_param->rl; 2820 } 2821 2822 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 2823 if (new_rl.rate) { 2824 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 2825 if (err) { 2826 pr_err("Failed configuring rate limit(err %d): \ 2827 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 2828 err, new_rl.rate, new_rl.max_burst_sz, 2829 new_rl.typical_pkt_sz); 2830 2831 goto out; 2832 } 2833 new_rate_added = true; 2834 } 2835 2836 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2837 /* index 0 means no limit */ 2838 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2839 } 2840 2841 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2842 if (err) { 2843 /* Remove new rate from table if failed */ 2844 if (new_rate_added) 2845 mlx5_rl_remove_rate(dev, &new_rl); 2846 goto out; 2847 } 2848 2849 /* Only remove the old rate after new rate was set */ 2850 if ((old_rl.rate && 2851 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 2852 (new_state != MLX5_SQC_STATE_RDY)) 2853 mlx5_rl_remove_rate(dev, &old_rl); 2854 2855 ibqp->rl = new_rl; 2856 sq->state = new_state; 2857 2858 out: 2859 kvfree(in); 2860 return err; 2861 } 2862 2863 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2864 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2865 u8 tx_affinity) 2866 { 2867 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2868 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2869 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2870 int modify_rq = !!qp->rq.wqe_cnt; 2871 int modify_sq = !!qp->sq.wqe_cnt; 2872 int rq_state; 2873 int sq_state; 2874 int err; 2875 2876 switch (raw_qp_param->operation) { 2877 case MLX5_CMD_OP_RST2INIT_QP: 2878 rq_state = MLX5_RQC_STATE_RDY; 2879 sq_state = MLX5_SQC_STATE_RDY; 2880 break; 2881 case MLX5_CMD_OP_2ERR_QP: 2882 rq_state = MLX5_RQC_STATE_ERR; 2883 sq_state = MLX5_SQC_STATE_ERR; 2884 break; 2885 case MLX5_CMD_OP_2RST_QP: 2886 rq_state = MLX5_RQC_STATE_RST; 2887 sq_state = MLX5_SQC_STATE_RST; 2888 break; 2889 case MLX5_CMD_OP_RTR2RTS_QP: 2890 case MLX5_CMD_OP_RTS2RTS_QP: 2891 if (raw_qp_param->set_mask == 2892 MLX5_RAW_QP_RATE_LIMIT) { 2893 modify_rq = 0; 2894 sq_state = sq->state; 2895 } else { 2896 return raw_qp_param->set_mask ? -EINVAL : 0; 2897 } 2898 break; 2899 case MLX5_CMD_OP_INIT2INIT_QP: 2900 case MLX5_CMD_OP_INIT2RTR_QP: 2901 if (raw_qp_param->set_mask) 2902 return -EINVAL; 2903 else 2904 return 0; 2905 default: 2906 WARN_ON(1); 2907 return -EINVAL; 2908 } 2909 2910 if (modify_rq) { 2911 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2912 if (err) 2913 return err; 2914 } 2915 2916 if (modify_sq) { 2917 if (tx_affinity) { 2918 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2919 tx_affinity); 2920 if (err) 2921 return err; 2922 } 2923 2924 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2925 } 2926 2927 return 0; 2928 } 2929 2930 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2931 const struct ib_qp_attr *attr, int attr_mask, 2932 enum ib_qp_state cur_state, enum ib_qp_state new_state, 2933 const struct mlx5_ib_modify_qp *ucmd) 2934 { 2935 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2936 [MLX5_QP_STATE_RST] = { 2937 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2938 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2939 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2940 }, 2941 [MLX5_QP_STATE_INIT] = { 2942 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2943 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2944 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2945 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2946 }, 2947 [MLX5_QP_STATE_RTR] = { 2948 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2949 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2950 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2951 }, 2952 [MLX5_QP_STATE_RTS] = { 2953 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2954 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2955 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2956 }, 2957 [MLX5_QP_STATE_SQD] = { 2958 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2959 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2960 }, 2961 [MLX5_QP_STATE_SQER] = { 2962 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2963 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2964 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2965 }, 2966 [MLX5_QP_STATE_ERR] = { 2967 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2968 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2969 } 2970 }; 2971 2972 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2973 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2974 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2975 struct mlx5_ib_cq *send_cq, *recv_cq; 2976 struct mlx5_qp_context *context; 2977 struct mlx5_ib_pd *pd; 2978 struct mlx5_ib_port *mibport = NULL; 2979 enum mlx5_qp_state mlx5_cur, mlx5_new; 2980 enum mlx5_qp_optpar optpar; 2981 int mlx5_st; 2982 int err; 2983 u16 op; 2984 u8 tx_affinity = 0; 2985 2986 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 2987 qp->qp_sub_type : ibqp->qp_type); 2988 if (mlx5_st < 0) 2989 return -EINVAL; 2990 2991 context = kzalloc(sizeof(*context), GFP_KERNEL); 2992 if (!context) 2993 return -ENOMEM; 2994 2995 context->flags = cpu_to_be32(mlx5_st << 16); 2996 2997 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2998 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2999 } else { 3000 switch (attr->path_mig_state) { 3001 case IB_MIG_MIGRATED: 3002 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3003 break; 3004 case IB_MIG_REARM: 3005 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3006 break; 3007 case IB_MIG_ARMED: 3008 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3009 break; 3010 } 3011 } 3012 3013 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3014 if ((ibqp->qp_type == IB_QPT_RC) || 3015 (ibqp->qp_type == IB_QPT_UD && 3016 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3017 (ibqp->qp_type == IB_QPT_UC) || 3018 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3019 (ibqp->qp_type == IB_QPT_XRC_INI) || 3020 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3021 if (mlx5_lag_is_active(dev->mdev)) { 3022 u8 p = mlx5_core_native_port_num(dev->mdev); 3023 tx_affinity = (unsigned int)atomic_add_return(1, 3024 &dev->roce[p].next_port) % 3025 MLX5_MAX_PORTS + 1; 3026 context->flags |= cpu_to_be32(tx_affinity << 24); 3027 } 3028 } 3029 } 3030 3031 if (is_sqp(ibqp->qp_type)) { 3032 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3033 } else if ((ibqp->qp_type == IB_QPT_UD && 3034 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3035 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3036 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3037 } else if (attr_mask & IB_QP_PATH_MTU) { 3038 if (attr->path_mtu < IB_MTU_256 || 3039 attr->path_mtu > IB_MTU_4096) { 3040 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3041 err = -EINVAL; 3042 goto out; 3043 } 3044 context->mtu_msgmax = (attr->path_mtu << 5) | 3045 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3046 } 3047 3048 if (attr_mask & IB_QP_DEST_QPN) 3049 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3050 3051 if (attr_mask & IB_QP_PKEY_INDEX) 3052 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3053 3054 /* todo implement counter_index functionality */ 3055 3056 if (is_sqp(ibqp->qp_type)) 3057 context->pri_path.port = qp->port; 3058 3059 if (attr_mask & IB_QP_PORT) 3060 context->pri_path.port = attr->port_num; 3061 3062 if (attr_mask & IB_QP_AV) { 3063 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3064 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3065 attr_mask, 0, attr, false); 3066 if (err) 3067 goto out; 3068 } 3069 3070 if (attr_mask & IB_QP_TIMEOUT) 3071 context->pri_path.ackto_lt |= attr->timeout << 3; 3072 3073 if (attr_mask & IB_QP_ALT_PATH) { 3074 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3075 &context->alt_path, 3076 attr->alt_port_num, 3077 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3078 0, attr, true); 3079 if (err) 3080 goto out; 3081 } 3082 3083 pd = get_pd(qp); 3084 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3085 &send_cq, &recv_cq); 3086 3087 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3088 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3089 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3090 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3091 3092 if (attr_mask & IB_QP_RNR_RETRY) 3093 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3094 3095 if (attr_mask & IB_QP_RETRY_CNT) 3096 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3097 3098 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3099 if (attr->max_rd_atomic) 3100 context->params1 |= 3101 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3102 } 3103 3104 if (attr_mask & IB_QP_SQ_PSN) 3105 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3106 3107 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3108 if (attr->max_dest_rd_atomic) 3109 context->params2 |= 3110 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3111 } 3112 3113 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3114 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 3115 3116 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3117 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3118 3119 if (attr_mask & IB_QP_RQ_PSN) 3120 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3121 3122 if (attr_mask & IB_QP_QKEY) 3123 context->qkey = cpu_to_be32(attr->qkey); 3124 3125 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3126 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3127 3128 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3129 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3130 qp->port) - 1; 3131 3132 /* Underlay port should be used - index 0 function per port */ 3133 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3134 port_num = 0; 3135 3136 mibport = &dev->port[port_num]; 3137 context->qp_counter_set_usr_page |= 3138 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3139 } 3140 3141 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3142 context->sq_crq_size |= cpu_to_be16(1 << 4); 3143 3144 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3145 context->deth_sqpn = cpu_to_be32(1); 3146 3147 mlx5_cur = to_mlx5_state(cur_state); 3148 mlx5_new = to_mlx5_state(new_state); 3149 3150 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3151 !optab[mlx5_cur][mlx5_new]) { 3152 err = -EINVAL; 3153 goto out; 3154 } 3155 3156 op = optab[mlx5_cur][mlx5_new]; 3157 optpar = ib_mask_to_mlx5_opt(attr_mask); 3158 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3159 3160 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3161 qp->flags & MLX5_IB_QP_UNDERLAY) { 3162 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3163 3164 raw_qp_param.operation = op; 3165 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3166 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3167 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3168 } 3169 3170 if (attr_mask & IB_QP_RATE_LIMIT) { 3171 raw_qp_param.rl.rate = attr->rate_limit; 3172 3173 if (ucmd->burst_info.max_burst_sz) { 3174 if (attr->rate_limit && 3175 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3176 raw_qp_param.rl.max_burst_sz = 3177 ucmd->burst_info.max_burst_sz; 3178 } else { 3179 err = -EINVAL; 3180 goto out; 3181 } 3182 } 3183 3184 if (ucmd->burst_info.typical_pkt_sz) { 3185 if (attr->rate_limit && 3186 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3187 raw_qp_param.rl.typical_pkt_sz = 3188 ucmd->burst_info.typical_pkt_sz; 3189 } else { 3190 err = -EINVAL; 3191 goto out; 3192 } 3193 } 3194 3195 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3196 } 3197 3198 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3199 } else { 3200 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3201 &base->mqp); 3202 } 3203 3204 if (err) 3205 goto out; 3206 3207 qp->state = new_state; 3208 3209 if (attr_mask & IB_QP_ACCESS_FLAGS) 3210 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3211 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3212 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3213 if (attr_mask & IB_QP_PORT) 3214 qp->port = attr->port_num; 3215 if (attr_mask & IB_QP_ALT_PATH) 3216 qp->trans_qp.alt_port = attr->alt_port_num; 3217 3218 /* 3219 * If we moved a kernel QP to RESET, clean up all old CQ 3220 * entries and reinitialize the QP. 3221 */ 3222 if (new_state == IB_QPS_RESET && 3223 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3224 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3225 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3226 if (send_cq != recv_cq) 3227 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3228 3229 qp->rq.head = 0; 3230 qp->rq.tail = 0; 3231 qp->sq.head = 0; 3232 qp->sq.tail = 0; 3233 qp->sq.cur_post = 0; 3234 qp->sq.last_poll = 0; 3235 qp->db.db[MLX5_RCV_DBR] = 0; 3236 qp->db.db[MLX5_SND_DBR] = 0; 3237 } 3238 3239 out: 3240 kfree(context); 3241 return err; 3242 } 3243 3244 static inline bool is_valid_mask(int mask, int req, int opt) 3245 { 3246 if ((mask & req) != req) 3247 return false; 3248 3249 if (mask & ~(req | opt)) 3250 return false; 3251 3252 return true; 3253 } 3254 3255 /* check valid transition for driver QP types 3256 * for now the only QP type that this function supports is DCI 3257 */ 3258 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3259 enum ib_qp_attr_mask attr_mask) 3260 { 3261 int req = IB_QP_STATE; 3262 int opt = 0; 3263 3264 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3265 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3266 return is_valid_mask(attr_mask, req, opt); 3267 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3268 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3269 return is_valid_mask(attr_mask, req, opt); 3270 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3271 req |= IB_QP_PATH_MTU; 3272 opt = IB_QP_PKEY_INDEX; 3273 return is_valid_mask(attr_mask, req, opt); 3274 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3275 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3276 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3277 opt = IB_QP_MIN_RNR_TIMER; 3278 return is_valid_mask(attr_mask, req, opt); 3279 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3280 opt = IB_QP_MIN_RNR_TIMER; 3281 return is_valid_mask(attr_mask, req, opt); 3282 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3283 return is_valid_mask(attr_mask, req, opt); 3284 } 3285 return false; 3286 } 3287 3288 /* mlx5_ib_modify_dct: modify a DCT QP 3289 * valid transitions are: 3290 * RESET to INIT: must set access_flags, pkey_index and port 3291 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3292 * mtu, gid_index and hop_limit 3293 * Other transitions and attributes are illegal 3294 */ 3295 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3296 int attr_mask, struct ib_udata *udata) 3297 { 3298 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3299 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3300 enum ib_qp_state cur_state, new_state; 3301 int err = 0; 3302 int required = IB_QP_STATE; 3303 void *dctc; 3304 3305 if (!(attr_mask & IB_QP_STATE)) 3306 return -EINVAL; 3307 3308 cur_state = qp->state; 3309 new_state = attr->qp_state; 3310 3311 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3312 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3313 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3314 if (!is_valid_mask(attr_mask, required, 0)) 3315 return -EINVAL; 3316 3317 if (attr->port_num == 0 || 3318 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3319 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3320 attr->port_num, dev->num_ports); 3321 return -EINVAL; 3322 } 3323 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3324 MLX5_SET(dctc, dctc, rre, 1); 3325 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3326 MLX5_SET(dctc, dctc, rwe, 1); 3327 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3328 if (!mlx5_ib_dc_atomic_is_supported(dev)) 3329 return -EOPNOTSUPP; 3330 MLX5_SET(dctc, dctc, rae, 1); 3331 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX); 3332 } 3333 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3334 MLX5_SET(dctc, dctc, port, attr->port_num); 3335 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3336 3337 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3338 struct mlx5_ib_modify_qp_resp resp = {}; 3339 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3340 sizeof(resp.dctn); 3341 3342 if (udata->outlen < min_resp_len) 3343 return -EINVAL; 3344 resp.response_length = min_resp_len; 3345 3346 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3347 if (!is_valid_mask(attr_mask, required, 0)) 3348 return -EINVAL; 3349 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3350 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3351 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3352 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3353 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3354 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3355 3356 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3357 MLX5_ST_SZ_BYTES(create_dct_in)); 3358 if (err) 3359 return err; 3360 resp.dctn = qp->dct.mdct.mqp.qpn; 3361 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3362 if (err) { 3363 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3364 return err; 3365 } 3366 } else { 3367 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3368 return -EINVAL; 3369 } 3370 if (err) 3371 qp->state = IB_QPS_ERR; 3372 else 3373 qp->state = new_state; 3374 return err; 3375 } 3376 3377 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3378 int attr_mask, struct ib_udata *udata) 3379 { 3380 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3381 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3382 struct mlx5_ib_modify_qp ucmd = {}; 3383 enum ib_qp_type qp_type; 3384 enum ib_qp_state cur_state, new_state; 3385 size_t required_cmd_sz; 3386 int err = -EINVAL; 3387 int port; 3388 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 3389 3390 if (ibqp->rwq_ind_tbl) 3391 return -ENOSYS; 3392 3393 if (udata && udata->inlen) { 3394 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3395 sizeof(ucmd.reserved); 3396 if (udata->inlen < required_cmd_sz) 3397 return -EINVAL; 3398 3399 if (udata->inlen > sizeof(ucmd) && 3400 !ib_is_udata_cleared(udata, sizeof(ucmd), 3401 udata->inlen - sizeof(ucmd))) 3402 return -EOPNOTSUPP; 3403 3404 if (ib_copy_from_udata(&ucmd, udata, 3405 min(udata->inlen, sizeof(ucmd)))) 3406 return -EFAULT; 3407 3408 if (ucmd.comp_mask || 3409 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3410 memchr_inv(&ucmd.burst_info.reserved, 0, 3411 sizeof(ucmd.burst_info.reserved))) 3412 return -EOPNOTSUPP; 3413 } 3414 3415 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3416 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3417 3418 if (ibqp->qp_type == IB_QPT_DRIVER) 3419 qp_type = qp->qp_sub_type; 3420 else 3421 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3422 IB_QPT_GSI : ibqp->qp_type; 3423 3424 if (qp_type == MLX5_IB_QPT_DCT) 3425 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3426 3427 mutex_lock(&qp->mutex); 3428 3429 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3430 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3431 3432 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3433 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3434 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 3435 } 3436 3437 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3438 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3439 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3440 attr_mask); 3441 goto out; 3442 } 3443 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3444 qp_type != MLX5_IB_QPT_DCI && 3445 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 3446 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3447 cur_state, new_state, ibqp->qp_type, attr_mask); 3448 goto out; 3449 } else if (qp_type == MLX5_IB_QPT_DCI && 3450 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3451 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3452 cur_state, new_state, qp_type, attr_mask); 3453 goto out; 3454 } 3455 3456 if ((attr_mask & IB_QP_PORT) && 3457 (attr->port_num == 0 || 3458 attr->port_num > dev->num_ports)) { 3459 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3460 attr->port_num, dev->num_ports); 3461 goto out; 3462 } 3463 3464 if (attr_mask & IB_QP_PKEY_INDEX) { 3465 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3466 if (attr->pkey_index >= 3467 dev->mdev->port_caps[port - 1].pkey_table_len) { 3468 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3469 attr->pkey_index); 3470 goto out; 3471 } 3472 } 3473 3474 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3475 attr->max_rd_atomic > 3476 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3477 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3478 attr->max_rd_atomic); 3479 goto out; 3480 } 3481 3482 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3483 attr->max_dest_rd_atomic > 3484 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3485 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3486 attr->max_dest_rd_atomic); 3487 goto out; 3488 } 3489 3490 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3491 err = 0; 3492 goto out; 3493 } 3494 3495 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3496 new_state, &ucmd); 3497 3498 out: 3499 mutex_unlock(&qp->mutex); 3500 return err; 3501 } 3502 3503 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3504 { 3505 struct mlx5_ib_cq *cq; 3506 unsigned cur; 3507 3508 cur = wq->head - wq->tail; 3509 if (likely(cur + nreq < wq->max_post)) 3510 return 0; 3511 3512 cq = to_mcq(ib_cq); 3513 spin_lock(&cq->lock); 3514 cur = wq->head - wq->tail; 3515 spin_unlock(&cq->lock); 3516 3517 return cur + nreq >= wq->max_post; 3518 } 3519 3520 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3521 u64 remote_addr, u32 rkey) 3522 { 3523 rseg->raddr = cpu_to_be64(remote_addr); 3524 rseg->rkey = cpu_to_be32(rkey); 3525 rseg->reserved = 0; 3526 } 3527 3528 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3529 struct ib_send_wr *wr, void *qend, 3530 struct mlx5_ib_qp *qp, int *size) 3531 { 3532 void *seg = eseg; 3533 3534 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3535 3536 if (wr->send_flags & IB_SEND_IP_CSUM) 3537 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3538 MLX5_ETH_WQE_L4_CSUM; 3539 3540 seg += sizeof(struct mlx5_wqe_eth_seg); 3541 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3542 3543 if (wr->opcode == IB_WR_LSO) { 3544 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3545 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3546 u64 left, leftlen, copysz; 3547 void *pdata = ud_wr->header; 3548 3549 left = ud_wr->hlen; 3550 eseg->mss = cpu_to_be16(ud_wr->mss); 3551 eseg->inline_hdr.sz = cpu_to_be16(left); 3552 3553 /* 3554 * check if there is space till the end of queue, if yes, 3555 * copy all in one shot, otherwise copy till the end of queue, 3556 * rollback and than the copy the left 3557 */ 3558 leftlen = qend - (void *)eseg->inline_hdr.start; 3559 copysz = min_t(u64, leftlen, left); 3560 3561 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3562 3563 if (likely(copysz > size_of_inl_hdr_start)) { 3564 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3565 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3566 } 3567 3568 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3569 seg = mlx5_get_send_wqe(qp, 0); 3570 left -= copysz; 3571 pdata += copysz; 3572 memcpy(seg, pdata, left); 3573 seg += ALIGN(left, 16); 3574 *size += ALIGN(left, 16) / 16; 3575 } 3576 } 3577 3578 return seg; 3579 } 3580 3581 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3582 struct ib_send_wr *wr) 3583 { 3584 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3585 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3586 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3587 } 3588 3589 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3590 { 3591 dseg->byte_count = cpu_to_be32(sg->length); 3592 dseg->lkey = cpu_to_be32(sg->lkey); 3593 dseg->addr = cpu_to_be64(sg->addr); 3594 } 3595 3596 static u64 get_xlt_octo(u64 bytes) 3597 { 3598 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3599 MLX5_IB_UMR_OCTOWORD; 3600 } 3601 3602 static __be64 frwr_mkey_mask(void) 3603 { 3604 u64 result; 3605 3606 result = MLX5_MKEY_MASK_LEN | 3607 MLX5_MKEY_MASK_PAGE_SIZE | 3608 MLX5_MKEY_MASK_START_ADDR | 3609 MLX5_MKEY_MASK_EN_RINVAL | 3610 MLX5_MKEY_MASK_KEY | 3611 MLX5_MKEY_MASK_LR | 3612 MLX5_MKEY_MASK_LW | 3613 MLX5_MKEY_MASK_RR | 3614 MLX5_MKEY_MASK_RW | 3615 MLX5_MKEY_MASK_A | 3616 MLX5_MKEY_MASK_SMALL_FENCE | 3617 MLX5_MKEY_MASK_FREE; 3618 3619 return cpu_to_be64(result); 3620 } 3621 3622 static __be64 sig_mkey_mask(void) 3623 { 3624 u64 result; 3625 3626 result = MLX5_MKEY_MASK_LEN | 3627 MLX5_MKEY_MASK_PAGE_SIZE | 3628 MLX5_MKEY_MASK_START_ADDR | 3629 MLX5_MKEY_MASK_EN_SIGERR | 3630 MLX5_MKEY_MASK_EN_RINVAL | 3631 MLX5_MKEY_MASK_KEY | 3632 MLX5_MKEY_MASK_LR | 3633 MLX5_MKEY_MASK_LW | 3634 MLX5_MKEY_MASK_RR | 3635 MLX5_MKEY_MASK_RW | 3636 MLX5_MKEY_MASK_SMALL_FENCE | 3637 MLX5_MKEY_MASK_FREE | 3638 MLX5_MKEY_MASK_BSF_EN; 3639 3640 return cpu_to_be64(result); 3641 } 3642 3643 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3644 struct mlx5_ib_mr *mr) 3645 { 3646 int size = mr->ndescs * mr->desc_size; 3647 3648 memset(umr, 0, sizeof(*umr)); 3649 3650 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3651 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3652 umr->mkey_mask = frwr_mkey_mask(); 3653 } 3654 3655 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3656 { 3657 memset(umr, 0, sizeof(*umr)); 3658 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3659 umr->flags = MLX5_UMR_INLINE; 3660 } 3661 3662 static __be64 get_umr_enable_mr_mask(void) 3663 { 3664 u64 result; 3665 3666 result = MLX5_MKEY_MASK_KEY | 3667 MLX5_MKEY_MASK_FREE; 3668 3669 return cpu_to_be64(result); 3670 } 3671 3672 static __be64 get_umr_disable_mr_mask(void) 3673 { 3674 u64 result; 3675 3676 result = MLX5_MKEY_MASK_FREE; 3677 3678 return cpu_to_be64(result); 3679 } 3680 3681 static __be64 get_umr_update_translation_mask(void) 3682 { 3683 u64 result; 3684 3685 result = MLX5_MKEY_MASK_LEN | 3686 MLX5_MKEY_MASK_PAGE_SIZE | 3687 MLX5_MKEY_MASK_START_ADDR; 3688 3689 return cpu_to_be64(result); 3690 } 3691 3692 static __be64 get_umr_update_access_mask(int atomic) 3693 { 3694 u64 result; 3695 3696 result = MLX5_MKEY_MASK_LR | 3697 MLX5_MKEY_MASK_LW | 3698 MLX5_MKEY_MASK_RR | 3699 MLX5_MKEY_MASK_RW; 3700 3701 if (atomic) 3702 result |= MLX5_MKEY_MASK_A; 3703 3704 return cpu_to_be64(result); 3705 } 3706 3707 static __be64 get_umr_update_pd_mask(void) 3708 { 3709 u64 result; 3710 3711 result = MLX5_MKEY_MASK_PD; 3712 3713 return cpu_to_be64(result); 3714 } 3715 3716 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 3717 { 3718 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 3719 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 3720 (mask & MLX5_MKEY_MASK_A && 3721 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 3722 return -EPERM; 3723 return 0; 3724 } 3725 3726 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 3727 struct mlx5_wqe_umr_ctrl_seg *umr, 3728 struct ib_send_wr *wr, int atomic) 3729 { 3730 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3731 3732 memset(umr, 0, sizeof(*umr)); 3733 3734 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3735 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3736 else 3737 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3738 3739 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3740 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3741 u64 offset = get_xlt_octo(umrwr->offset); 3742 3743 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3744 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3745 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3746 } 3747 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3748 umr->mkey_mask |= get_umr_update_translation_mask(); 3749 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3750 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3751 umr->mkey_mask |= get_umr_update_pd_mask(); 3752 } 3753 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3754 umr->mkey_mask |= get_umr_enable_mr_mask(); 3755 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3756 umr->mkey_mask |= get_umr_disable_mr_mask(); 3757 3758 if (!wr->num_sge) 3759 umr->flags |= MLX5_UMR_INLINE; 3760 3761 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 3762 } 3763 3764 static u8 get_umr_flags(int acc) 3765 { 3766 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3767 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3768 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3769 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3770 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3771 } 3772 3773 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3774 struct mlx5_ib_mr *mr, 3775 u32 key, int access) 3776 { 3777 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3778 3779 memset(seg, 0, sizeof(*seg)); 3780 3781 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3782 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3783 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3784 /* KLMs take twice the size of MTTs */ 3785 ndescs *= 2; 3786 3787 seg->flags = get_umr_flags(access) | mr->access_mode; 3788 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3789 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3790 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3791 seg->len = cpu_to_be64(mr->ibmr.length); 3792 seg->xlt_oct_size = cpu_to_be32(ndescs); 3793 } 3794 3795 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3796 { 3797 memset(seg, 0, sizeof(*seg)); 3798 seg->status = MLX5_MKEY_STATUS_FREE; 3799 } 3800 3801 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3802 { 3803 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3804 3805 memset(seg, 0, sizeof(*seg)); 3806 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3807 seg->status = MLX5_MKEY_STATUS_FREE; 3808 3809 seg->flags = convert_access(umrwr->access_flags); 3810 if (umrwr->pd) 3811 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3812 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3813 !umrwr->length) 3814 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3815 3816 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3817 seg->len = cpu_to_be64(umrwr->length); 3818 seg->log2_page_size = umrwr->page_shift; 3819 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3820 mlx5_mkey_variant(umrwr->mkey)); 3821 } 3822 3823 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3824 struct mlx5_ib_mr *mr, 3825 struct mlx5_ib_pd *pd) 3826 { 3827 int bcount = mr->desc_size * mr->ndescs; 3828 3829 dseg->addr = cpu_to_be64(mr->desc_map); 3830 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3831 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3832 } 3833 3834 static __be32 send_ieth(struct ib_send_wr *wr) 3835 { 3836 switch (wr->opcode) { 3837 case IB_WR_SEND_WITH_IMM: 3838 case IB_WR_RDMA_WRITE_WITH_IMM: 3839 return wr->ex.imm_data; 3840 3841 case IB_WR_SEND_WITH_INV: 3842 return cpu_to_be32(wr->ex.invalidate_rkey); 3843 3844 default: 3845 return 0; 3846 } 3847 } 3848 3849 static u8 calc_sig(void *wqe, int size) 3850 { 3851 u8 *p = wqe; 3852 u8 res = 0; 3853 int i; 3854 3855 for (i = 0; i < size; i++) 3856 res ^= p[i]; 3857 3858 return ~res; 3859 } 3860 3861 static u8 wq_sig(void *wqe) 3862 { 3863 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3864 } 3865 3866 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3867 void *wqe, int *sz) 3868 { 3869 struct mlx5_wqe_inline_seg *seg; 3870 void *qend = qp->sq.qend; 3871 void *addr; 3872 int inl = 0; 3873 int copy; 3874 int len; 3875 int i; 3876 3877 seg = wqe; 3878 wqe += sizeof(*seg); 3879 for (i = 0; i < wr->num_sge; i++) { 3880 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3881 len = wr->sg_list[i].length; 3882 inl += len; 3883 3884 if (unlikely(inl > qp->max_inline_data)) 3885 return -ENOMEM; 3886 3887 if (unlikely(wqe + len > qend)) { 3888 copy = qend - wqe; 3889 memcpy(wqe, addr, copy); 3890 addr += copy; 3891 len -= copy; 3892 wqe = mlx5_get_send_wqe(qp, 0); 3893 } 3894 memcpy(wqe, addr, len); 3895 wqe += len; 3896 } 3897 3898 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3899 3900 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3901 3902 return 0; 3903 } 3904 3905 static u16 prot_field_size(enum ib_signature_type type) 3906 { 3907 switch (type) { 3908 case IB_SIG_TYPE_T10_DIF: 3909 return MLX5_DIF_SIZE; 3910 default: 3911 return 0; 3912 } 3913 } 3914 3915 static u8 bs_selector(int block_size) 3916 { 3917 switch (block_size) { 3918 case 512: return 0x1; 3919 case 520: return 0x2; 3920 case 4096: return 0x3; 3921 case 4160: return 0x4; 3922 case 1073741824: return 0x5; 3923 default: return 0; 3924 } 3925 } 3926 3927 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3928 struct mlx5_bsf_inl *inl) 3929 { 3930 /* Valid inline section and allow BSF refresh */ 3931 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3932 MLX5_BSF_REFRESH_DIF); 3933 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3934 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3935 /* repeating block */ 3936 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3937 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3938 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3939 3940 if (domain->sig.dif.ref_remap) 3941 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3942 3943 if (domain->sig.dif.app_escape) { 3944 if (domain->sig.dif.ref_escape) 3945 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3946 else 3947 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3948 } 3949 3950 inl->dif_app_bitmask_check = 3951 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3952 } 3953 3954 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3955 struct ib_sig_attrs *sig_attrs, 3956 struct mlx5_bsf *bsf, u32 data_size) 3957 { 3958 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3959 struct mlx5_bsf_basic *basic = &bsf->basic; 3960 struct ib_sig_domain *mem = &sig_attrs->mem; 3961 struct ib_sig_domain *wire = &sig_attrs->wire; 3962 3963 memset(bsf, 0, sizeof(*bsf)); 3964 3965 /* Basic + Extended + Inline */ 3966 basic->bsf_size_sbs = 1 << 7; 3967 /* Input domain check byte mask */ 3968 basic->check_byte_mask = sig_attrs->check_mask; 3969 basic->raw_data_size = cpu_to_be32(data_size); 3970 3971 /* Memory domain */ 3972 switch (sig_attrs->mem.sig_type) { 3973 case IB_SIG_TYPE_NONE: 3974 break; 3975 case IB_SIG_TYPE_T10_DIF: 3976 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3977 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3978 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3979 break; 3980 default: 3981 return -EINVAL; 3982 } 3983 3984 /* Wire domain */ 3985 switch (sig_attrs->wire.sig_type) { 3986 case IB_SIG_TYPE_NONE: 3987 break; 3988 case IB_SIG_TYPE_T10_DIF: 3989 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3990 mem->sig_type == wire->sig_type) { 3991 /* Same block structure */ 3992 basic->bsf_size_sbs |= 1 << 4; 3993 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3994 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3995 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3996 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3997 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3998 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3999 } else 4000 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4001 4002 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4003 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4004 break; 4005 default: 4006 return -EINVAL; 4007 } 4008 4009 return 0; 4010 } 4011 4012 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 4013 struct mlx5_ib_qp *qp, void **seg, int *size) 4014 { 4015 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4016 struct ib_mr *sig_mr = wr->sig_mr; 4017 struct mlx5_bsf *bsf; 4018 u32 data_len = wr->wr.sg_list->length; 4019 u32 data_key = wr->wr.sg_list->lkey; 4020 u64 data_va = wr->wr.sg_list->addr; 4021 int ret; 4022 int wqe_size; 4023 4024 if (!wr->prot || 4025 (data_key == wr->prot->lkey && 4026 data_va == wr->prot->addr && 4027 data_len == wr->prot->length)) { 4028 /** 4029 * Source domain doesn't contain signature information 4030 * or data and protection are interleaved in memory. 4031 * So need construct: 4032 * ------------------ 4033 * | data_klm | 4034 * ------------------ 4035 * | BSF | 4036 * ------------------ 4037 **/ 4038 struct mlx5_klm *data_klm = *seg; 4039 4040 data_klm->bcount = cpu_to_be32(data_len); 4041 data_klm->key = cpu_to_be32(data_key); 4042 data_klm->va = cpu_to_be64(data_va); 4043 wqe_size = ALIGN(sizeof(*data_klm), 64); 4044 } else { 4045 /** 4046 * Source domain contains signature information 4047 * So need construct a strided block format: 4048 * --------------------------- 4049 * | stride_block_ctrl | 4050 * --------------------------- 4051 * | data_klm | 4052 * --------------------------- 4053 * | prot_klm | 4054 * --------------------------- 4055 * | BSF | 4056 * --------------------------- 4057 **/ 4058 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4059 struct mlx5_stride_block_entry *data_sentry; 4060 struct mlx5_stride_block_entry *prot_sentry; 4061 u32 prot_key = wr->prot->lkey; 4062 u64 prot_va = wr->prot->addr; 4063 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4064 int prot_size; 4065 4066 sblock_ctrl = *seg; 4067 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4068 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4069 4070 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4071 if (!prot_size) { 4072 pr_err("Bad block size given: %u\n", block_size); 4073 return -EINVAL; 4074 } 4075 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4076 prot_size); 4077 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4078 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4079 sblock_ctrl->num_entries = cpu_to_be16(2); 4080 4081 data_sentry->bcount = cpu_to_be16(block_size); 4082 data_sentry->key = cpu_to_be32(data_key); 4083 data_sentry->va = cpu_to_be64(data_va); 4084 data_sentry->stride = cpu_to_be16(block_size); 4085 4086 prot_sentry->bcount = cpu_to_be16(prot_size); 4087 prot_sentry->key = cpu_to_be32(prot_key); 4088 prot_sentry->va = cpu_to_be64(prot_va); 4089 prot_sentry->stride = cpu_to_be16(prot_size); 4090 4091 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4092 sizeof(*prot_sentry), 64); 4093 } 4094 4095 *seg += wqe_size; 4096 *size += wqe_size / 16; 4097 if (unlikely((*seg == qp->sq.qend))) 4098 *seg = mlx5_get_send_wqe(qp, 0); 4099 4100 bsf = *seg; 4101 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4102 if (ret) 4103 return -EINVAL; 4104 4105 *seg += sizeof(*bsf); 4106 *size += sizeof(*bsf) / 16; 4107 if (unlikely((*seg == qp->sq.qend))) 4108 *seg = mlx5_get_send_wqe(qp, 0); 4109 4110 return 0; 4111 } 4112 4113 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4114 struct ib_sig_handover_wr *wr, u32 size, 4115 u32 length, u32 pdn) 4116 { 4117 struct ib_mr *sig_mr = wr->sig_mr; 4118 u32 sig_key = sig_mr->rkey; 4119 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4120 4121 memset(seg, 0, sizeof(*seg)); 4122 4123 seg->flags = get_umr_flags(wr->access_flags) | 4124 MLX5_MKC_ACCESS_MODE_KLMS; 4125 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4126 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4127 MLX5_MKEY_BSF_EN | pdn); 4128 seg->len = cpu_to_be64(length); 4129 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4130 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4131 } 4132 4133 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4134 u32 size) 4135 { 4136 memset(umr, 0, sizeof(*umr)); 4137 4138 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4139 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4140 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4141 umr->mkey_mask = sig_mkey_mask(); 4142 } 4143 4144 4145 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 4146 void **seg, int *size) 4147 { 4148 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4149 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4150 u32 pdn = get_pd(qp)->pdn; 4151 u32 xlt_size; 4152 int region_len, ret; 4153 4154 if (unlikely(wr->wr.num_sge != 1) || 4155 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4156 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4157 unlikely(!sig_mr->sig->sig_status_checked)) 4158 return -EINVAL; 4159 4160 /* length of the protected region, data + protection */ 4161 region_len = wr->wr.sg_list->length; 4162 if (wr->prot && 4163 (wr->prot->lkey != wr->wr.sg_list->lkey || 4164 wr->prot->addr != wr->wr.sg_list->addr || 4165 wr->prot->length != wr->wr.sg_list->length)) 4166 region_len += wr->prot->length; 4167 4168 /** 4169 * KLM octoword size - if protection was provided 4170 * then we use strided block format (3 octowords), 4171 * else we use single KLM (1 octoword) 4172 **/ 4173 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4174 4175 set_sig_umr_segment(*seg, xlt_size); 4176 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4177 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4178 if (unlikely((*seg == qp->sq.qend))) 4179 *seg = mlx5_get_send_wqe(qp, 0); 4180 4181 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4182 *seg += sizeof(struct mlx5_mkey_seg); 4183 *size += sizeof(struct mlx5_mkey_seg) / 16; 4184 if (unlikely((*seg == qp->sq.qend))) 4185 *seg = mlx5_get_send_wqe(qp, 0); 4186 4187 ret = set_sig_data_segment(wr, qp, seg, size); 4188 if (ret) 4189 return ret; 4190 4191 sig_mr->sig->sig_status_checked = false; 4192 return 0; 4193 } 4194 4195 static int set_psv_wr(struct ib_sig_domain *domain, 4196 u32 psv_idx, void **seg, int *size) 4197 { 4198 struct mlx5_seg_set_psv *psv_seg = *seg; 4199 4200 memset(psv_seg, 0, sizeof(*psv_seg)); 4201 psv_seg->psv_num = cpu_to_be32(psv_idx); 4202 switch (domain->sig_type) { 4203 case IB_SIG_TYPE_NONE: 4204 break; 4205 case IB_SIG_TYPE_T10_DIF: 4206 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4207 domain->sig.dif.app_tag); 4208 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4209 break; 4210 default: 4211 pr_err("Bad signature type (%d) is given.\n", 4212 domain->sig_type); 4213 return -EINVAL; 4214 } 4215 4216 *seg += sizeof(*psv_seg); 4217 *size += sizeof(*psv_seg) / 16; 4218 4219 return 0; 4220 } 4221 4222 static int set_reg_wr(struct mlx5_ib_qp *qp, 4223 struct ib_reg_wr *wr, 4224 void **seg, int *size) 4225 { 4226 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4227 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4228 4229 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4230 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4231 "Invalid IB_SEND_INLINE send flag\n"); 4232 return -EINVAL; 4233 } 4234 4235 set_reg_umr_seg(*seg, mr); 4236 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4237 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4238 if (unlikely((*seg == qp->sq.qend))) 4239 *seg = mlx5_get_send_wqe(qp, 0); 4240 4241 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4242 *seg += sizeof(struct mlx5_mkey_seg); 4243 *size += sizeof(struct mlx5_mkey_seg) / 16; 4244 if (unlikely((*seg == qp->sq.qend))) 4245 *seg = mlx5_get_send_wqe(qp, 0); 4246 4247 set_reg_data_seg(*seg, mr, pd); 4248 *seg += sizeof(struct mlx5_wqe_data_seg); 4249 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4250 4251 return 0; 4252 } 4253 4254 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 4255 { 4256 set_linv_umr_seg(*seg); 4257 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4258 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4259 if (unlikely((*seg == qp->sq.qend))) 4260 *seg = mlx5_get_send_wqe(qp, 0); 4261 set_linv_mkey_seg(*seg); 4262 *seg += sizeof(struct mlx5_mkey_seg); 4263 *size += sizeof(struct mlx5_mkey_seg) / 16; 4264 if (unlikely((*seg == qp->sq.qend))) 4265 *seg = mlx5_get_send_wqe(qp, 0); 4266 } 4267 4268 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 4269 { 4270 __be32 *p = NULL; 4271 int tidx = idx; 4272 int i, j; 4273 4274 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 4275 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4276 if ((i & 0xf) == 0) { 4277 void *buf = mlx5_get_send_wqe(qp, tidx); 4278 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4279 p = buf; 4280 j = 0; 4281 } 4282 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4283 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4284 be32_to_cpu(p[j + 3])); 4285 } 4286 } 4287 4288 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4289 struct mlx5_wqe_ctrl_seg **ctrl, 4290 struct ib_send_wr *wr, unsigned *idx, 4291 int *size, int nreq) 4292 { 4293 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4294 return -ENOMEM; 4295 4296 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4297 *seg = mlx5_get_send_wqe(qp, *idx); 4298 *ctrl = *seg; 4299 *(uint32_t *)(*seg + 8) = 0; 4300 (*ctrl)->imm = send_ieth(wr); 4301 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4302 (wr->send_flags & IB_SEND_SIGNALED ? 4303 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4304 (wr->send_flags & IB_SEND_SOLICITED ? 4305 MLX5_WQE_CTRL_SOLICITED : 0); 4306 4307 *seg += sizeof(**ctrl); 4308 *size = sizeof(**ctrl) / 16; 4309 4310 return 0; 4311 } 4312 4313 static void finish_wqe(struct mlx5_ib_qp *qp, 4314 struct mlx5_wqe_ctrl_seg *ctrl, 4315 u8 size, unsigned idx, u64 wr_id, 4316 int nreq, u8 fence, u32 mlx5_opcode) 4317 { 4318 u8 opmod = 0; 4319 4320 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4321 mlx5_opcode | ((u32)opmod << 24)); 4322 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4323 ctrl->fm_ce_se |= fence; 4324 if (unlikely(qp->wq_sig)) 4325 ctrl->signature = wq_sig(ctrl); 4326 4327 qp->sq.wrid[idx] = wr_id; 4328 qp->sq.w_list[idx].opcode = mlx5_opcode; 4329 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4330 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4331 qp->sq.w_list[idx].next = qp->sq.cur_post; 4332 } 4333 4334 4335 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 4336 struct ib_send_wr **bad_wr) 4337 { 4338 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4339 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4340 struct mlx5_core_dev *mdev = dev->mdev; 4341 struct mlx5_ib_qp *qp; 4342 struct mlx5_ib_mr *mr; 4343 struct mlx5_wqe_data_seg *dpseg; 4344 struct mlx5_wqe_xrc_seg *xrc; 4345 struct mlx5_bf *bf; 4346 int uninitialized_var(size); 4347 void *qend; 4348 unsigned long flags; 4349 unsigned idx; 4350 int err = 0; 4351 int num_sge; 4352 void *seg; 4353 int nreq; 4354 int i; 4355 u8 next_fence = 0; 4356 u8 fence; 4357 4358 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4359 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4360 4361 qp = to_mqp(ibqp); 4362 bf = &qp->bf; 4363 qend = qp->sq.qend; 4364 4365 spin_lock_irqsave(&qp->sq.lock, flags); 4366 4367 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4368 err = -EIO; 4369 *bad_wr = wr; 4370 nreq = 0; 4371 goto out; 4372 } 4373 4374 for (nreq = 0; wr; nreq++, wr = wr->next) { 4375 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4376 mlx5_ib_warn(dev, "\n"); 4377 err = -EINVAL; 4378 *bad_wr = wr; 4379 goto out; 4380 } 4381 4382 num_sge = wr->num_sge; 4383 if (unlikely(num_sge > qp->sq.max_gs)) { 4384 mlx5_ib_warn(dev, "\n"); 4385 err = -EINVAL; 4386 *bad_wr = wr; 4387 goto out; 4388 } 4389 4390 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 4391 if (err) { 4392 mlx5_ib_warn(dev, "\n"); 4393 err = -ENOMEM; 4394 *bad_wr = wr; 4395 goto out; 4396 } 4397 4398 if (wr->opcode == IB_WR_LOCAL_INV || 4399 wr->opcode == IB_WR_REG_MR) { 4400 fence = dev->umr_fence; 4401 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4402 } else if (wr->send_flags & IB_SEND_FENCE) { 4403 if (qp->next_fence) 4404 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4405 else 4406 fence = MLX5_FENCE_MODE_FENCE; 4407 } else { 4408 fence = qp->next_fence; 4409 } 4410 4411 switch (ibqp->qp_type) { 4412 case IB_QPT_XRC_INI: 4413 xrc = seg; 4414 seg += sizeof(*xrc); 4415 size += sizeof(*xrc) / 16; 4416 /* fall through */ 4417 case IB_QPT_RC: 4418 switch (wr->opcode) { 4419 case IB_WR_RDMA_READ: 4420 case IB_WR_RDMA_WRITE: 4421 case IB_WR_RDMA_WRITE_WITH_IMM: 4422 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4423 rdma_wr(wr)->rkey); 4424 seg += sizeof(struct mlx5_wqe_raddr_seg); 4425 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4426 break; 4427 4428 case IB_WR_ATOMIC_CMP_AND_SWP: 4429 case IB_WR_ATOMIC_FETCH_AND_ADD: 4430 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4431 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4432 err = -ENOSYS; 4433 *bad_wr = wr; 4434 goto out; 4435 4436 case IB_WR_LOCAL_INV: 4437 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4438 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4439 set_linv_wr(qp, &seg, &size); 4440 num_sge = 0; 4441 break; 4442 4443 case IB_WR_REG_MR: 4444 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4445 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4446 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4447 if (err) { 4448 *bad_wr = wr; 4449 goto out; 4450 } 4451 num_sge = 0; 4452 break; 4453 4454 case IB_WR_REG_SIG_MR: 4455 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4456 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4457 4458 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4459 err = set_sig_umr_wr(wr, qp, &seg, &size); 4460 if (err) { 4461 mlx5_ib_warn(dev, "\n"); 4462 *bad_wr = wr; 4463 goto out; 4464 } 4465 4466 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4467 fence, MLX5_OPCODE_UMR); 4468 /* 4469 * SET_PSV WQEs are not signaled and solicited 4470 * on error 4471 */ 4472 wr->send_flags &= ~IB_SEND_SIGNALED; 4473 wr->send_flags |= IB_SEND_SOLICITED; 4474 err = begin_wqe(qp, &seg, &ctrl, wr, 4475 &idx, &size, nreq); 4476 if (err) { 4477 mlx5_ib_warn(dev, "\n"); 4478 err = -ENOMEM; 4479 *bad_wr = wr; 4480 goto out; 4481 } 4482 4483 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4484 mr->sig->psv_memory.psv_idx, &seg, 4485 &size); 4486 if (err) { 4487 mlx5_ib_warn(dev, "\n"); 4488 *bad_wr = wr; 4489 goto out; 4490 } 4491 4492 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4493 fence, MLX5_OPCODE_SET_PSV); 4494 err = begin_wqe(qp, &seg, &ctrl, wr, 4495 &idx, &size, nreq); 4496 if (err) { 4497 mlx5_ib_warn(dev, "\n"); 4498 err = -ENOMEM; 4499 *bad_wr = wr; 4500 goto out; 4501 } 4502 4503 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4504 mr->sig->psv_wire.psv_idx, &seg, 4505 &size); 4506 if (err) { 4507 mlx5_ib_warn(dev, "\n"); 4508 *bad_wr = wr; 4509 goto out; 4510 } 4511 4512 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4513 fence, MLX5_OPCODE_SET_PSV); 4514 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4515 num_sge = 0; 4516 goto skip_psv; 4517 4518 default: 4519 break; 4520 } 4521 break; 4522 4523 case IB_QPT_UC: 4524 switch (wr->opcode) { 4525 case IB_WR_RDMA_WRITE: 4526 case IB_WR_RDMA_WRITE_WITH_IMM: 4527 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4528 rdma_wr(wr)->rkey); 4529 seg += sizeof(struct mlx5_wqe_raddr_seg); 4530 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4531 break; 4532 4533 default: 4534 break; 4535 } 4536 break; 4537 4538 case IB_QPT_SMI: 4539 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4540 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4541 err = -EPERM; 4542 *bad_wr = wr; 4543 goto out; 4544 } 4545 /* fall through */ 4546 case MLX5_IB_QPT_HW_GSI: 4547 set_datagram_seg(seg, wr); 4548 seg += sizeof(struct mlx5_wqe_datagram_seg); 4549 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4550 if (unlikely((seg == qend))) 4551 seg = mlx5_get_send_wqe(qp, 0); 4552 break; 4553 case IB_QPT_UD: 4554 set_datagram_seg(seg, wr); 4555 seg += sizeof(struct mlx5_wqe_datagram_seg); 4556 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4557 4558 if (unlikely((seg == qend))) 4559 seg = mlx5_get_send_wqe(qp, 0); 4560 4561 /* handle qp that supports ud offload */ 4562 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4563 struct mlx5_wqe_eth_pad *pad; 4564 4565 pad = seg; 4566 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4567 seg += sizeof(struct mlx5_wqe_eth_pad); 4568 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4569 4570 seg = set_eth_seg(seg, wr, qend, qp, &size); 4571 4572 if (unlikely((seg == qend))) 4573 seg = mlx5_get_send_wqe(qp, 0); 4574 } 4575 break; 4576 case MLX5_IB_QPT_REG_UMR: 4577 if (wr->opcode != MLX5_IB_WR_UMR) { 4578 err = -EINVAL; 4579 mlx5_ib_warn(dev, "bad opcode\n"); 4580 goto out; 4581 } 4582 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4583 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4584 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4585 if (unlikely(err)) 4586 goto out; 4587 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4588 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4589 if (unlikely((seg == qend))) 4590 seg = mlx5_get_send_wqe(qp, 0); 4591 set_reg_mkey_segment(seg, wr); 4592 seg += sizeof(struct mlx5_mkey_seg); 4593 size += sizeof(struct mlx5_mkey_seg) / 16; 4594 if (unlikely((seg == qend))) 4595 seg = mlx5_get_send_wqe(qp, 0); 4596 break; 4597 4598 default: 4599 break; 4600 } 4601 4602 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4603 int uninitialized_var(sz); 4604 4605 err = set_data_inl_seg(qp, wr, seg, &sz); 4606 if (unlikely(err)) { 4607 mlx5_ib_warn(dev, "\n"); 4608 *bad_wr = wr; 4609 goto out; 4610 } 4611 size += sz; 4612 } else { 4613 dpseg = seg; 4614 for (i = 0; i < num_sge; i++) { 4615 if (unlikely(dpseg == qend)) { 4616 seg = mlx5_get_send_wqe(qp, 0); 4617 dpseg = seg; 4618 } 4619 if (likely(wr->sg_list[i].length)) { 4620 set_data_ptr_seg(dpseg, wr->sg_list + i); 4621 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4622 dpseg++; 4623 } 4624 } 4625 } 4626 4627 qp->next_fence = next_fence; 4628 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4629 mlx5_ib_opcode[wr->opcode]); 4630 skip_psv: 4631 if (0) 4632 dump_wqe(qp, idx, size); 4633 } 4634 4635 out: 4636 if (likely(nreq)) { 4637 qp->sq.head += nreq; 4638 4639 /* Make sure that descriptors are written before 4640 * updating doorbell record and ringing the doorbell 4641 */ 4642 wmb(); 4643 4644 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4645 4646 /* Make sure doorbell record is visible to the HCA before 4647 * we hit doorbell */ 4648 wmb(); 4649 4650 /* currently we support only regular doorbells */ 4651 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4652 /* Make sure doorbells don't leak out of SQ spinlock 4653 * and reach the HCA out of order. 4654 */ 4655 mmiowb(); 4656 bf->offset ^= bf->buf_size; 4657 } 4658 4659 spin_unlock_irqrestore(&qp->sq.lock, flags); 4660 4661 return err; 4662 } 4663 4664 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4665 { 4666 sig->signature = calc_sig(sig, size); 4667 } 4668 4669 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4670 struct ib_recv_wr **bad_wr) 4671 { 4672 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4673 struct mlx5_wqe_data_seg *scat; 4674 struct mlx5_rwqe_sig *sig; 4675 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4676 struct mlx5_core_dev *mdev = dev->mdev; 4677 unsigned long flags; 4678 int err = 0; 4679 int nreq; 4680 int ind; 4681 int i; 4682 4683 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4684 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4685 4686 spin_lock_irqsave(&qp->rq.lock, flags); 4687 4688 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4689 err = -EIO; 4690 *bad_wr = wr; 4691 nreq = 0; 4692 goto out; 4693 } 4694 4695 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4696 4697 for (nreq = 0; wr; nreq++, wr = wr->next) { 4698 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4699 err = -ENOMEM; 4700 *bad_wr = wr; 4701 goto out; 4702 } 4703 4704 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4705 err = -EINVAL; 4706 *bad_wr = wr; 4707 goto out; 4708 } 4709 4710 scat = get_recv_wqe(qp, ind); 4711 if (qp->wq_sig) 4712 scat++; 4713 4714 for (i = 0; i < wr->num_sge; i++) 4715 set_data_ptr_seg(scat + i, wr->sg_list + i); 4716 4717 if (i < qp->rq.max_gs) { 4718 scat[i].byte_count = 0; 4719 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4720 scat[i].addr = 0; 4721 } 4722 4723 if (qp->wq_sig) { 4724 sig = (struct mlx5_rwqe_sig *)scat; 4725 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4726 } 4727 4728 qp->rq.wrid[ind] = wr->wr_id; 4729 4730 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4731 } 4732 4733 out: 4734 if (likely(nreq)) { 4735 qp->rq.head += nreq; 4736 4737 /* Make sure that descriptors are written before 4738 * doorbell record. 4739 */ 4740 wmb(); 4741 4742 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4743 } 4744 4745 spin_unlock_irqrestore(&qp->rq.lock, flags); 4746 4747 return err; 4748 } 4749 4750 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4751 { 4752 switch (mlx5_state) { 4753 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4754 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4755 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4756 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4757 case MLX5_QP_STATE_SQ_DRAINING: 4758 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4759 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4760 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4761 default: return -1; 4762 } 4763 } 4764 4765 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4766 { 4767 switch (mlx5_mig_state) { 4768 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4769 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4770 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4771 default: return -1; 4772 } 4773 } 4774 4775 static int to_ib_qp_access_flags(int mlx5_flags) 4776 { 4777 int ib_flags = 0; 4778 4779 if (mlx5_flags & MLX5_QP_BIT_RRE) 4780 ib_flags |= IB_ACCESS_REMOTE_READ; 4781 if (mlx5_flags & MLX5_QP_BIT_RWE) 4782 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4783 if (mlx5_flags & MLX5_QP_BIT_RAE) 4784 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4785 4786 return ib_flags; 4787 } 4788 4789 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4790 struct rdma_ah_attr *ah_attr, 4791 struct mlx5_qp_path *path) 4792 { 4793 4794 memset(ah_attr, 0, sizeof(*ah_attr)); 4795 4796 if (!path->port || path->port > ibdev->num_ports) 4797 return; 4798 4799 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4800 4801 rdma_ah_set_port_num(ah_attr, path->port); 4802 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4803 4804 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4805 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4806 rdma_ah_set_static_rate(ah_attr, 4807 path->static_rate ? path->static_rate - 5 : 0); 4808 if (path->grh_mlid & (1 << 7)) { 4809 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4810 4811 rdma_ah_set_grh(ah_attr, NULL, 4812 tc_fl & 0xfffff, 4813 path->mgid_index, 4814 path->hop_limit, 4815 (tc_fl >> 20) & 0xff); 4816 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4817 } 4818 } 4819 4820 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4821 struct mlx5_ib_sq *sq, 4822 u8 *sq_state) 4823 { 4824 int err; 4825 4826 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4827 if (err) 4828 goto out; 4829 sq->state = *sq_state; 4830 4831 out: 4832 return err; 4833 } 4834 4835 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4836 struct mlx5_ib_rq *rq, 4837 u8 *rq_state) 4838 { 4839 void *out; 4840 void *rqc; 4841 int inlen; 4842 int err; 4843 4844 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4845 out = kvzalloc(inlen, GFP_KERNEL); 4846 if (!out) 4847 return -ENOMEM; 4848 4849 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4850 if (err) 4851 goto out; 4852 4853 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4854 *rq_state = MLX5_GET(rqc, rqc, state); 4855 rq->state = *rq_state; 4856 4857 out: 4858 kvfree(out); 4859 return err; 4860 } 4861 4862 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4863 struct mlx5_ib_qp *qp, u8 *qp_state) 4864 { 4865 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4866 [MLX5_RQC_STATE_RST] = { 4867 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4868 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4869 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4870 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4871 }, 4872 [MLX5_RQC_STATE_RDY] = { 4873 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4874 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4875 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4876 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4877 }, 4878 [MLX5_RQC_STATE_ERR] = { 4879 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4880 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4881 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4882 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4883 }, 4884 [MLX5_RQ_STATE_NA] = { 4885 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4886 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4887 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4888 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4889 }, 4890 }; 4891 4892 *qp_state = sqrq_trans[rq_state][sq_state]; 4893 4894 if (*qp_state == MLX5_QP_STATE_BAD) { 4895 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4896 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4897 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4898 return -EINVAL; 4899 } 4900 4901 if (*qp_state == MLX5_QP_STATE) 4902 *qp_state = qp->state; 4903 4904 return 0; 4905 } 4906 4907 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4908 struct mlx5_ib_qp *qp, 4909 u8 *raw_packet_qp_state) 4910 { 4911 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4912 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4913 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4914 int err; 4915 u8 sq_state = MLX5_SQ_STATE_NA; 4916 u8 rq_state = MLX5_RQ_STATE_NA; 4917 4918 if (qp->sq.wqe_cnt) { 4919 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4920 if (err) 4921 return err; 4922 } 4923 4924 if (qp->rq.wqe_cnt) { 4925 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4926 if (err) 4927 return err; 4928 } 4929 4930 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4931 raw_packet_qp_state); 4932 } 4933 4934 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4935 struct ib_qp_attr *qp_attr) 4936 { 4937 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4938 struct mlx5_qp_context *context; 4939 int mlx5_state; 4940 u32 *outb; 4941 int err = 0; 4942 4943 outb = kzalloc(outlen, GFP_KERNEL); 4944 if (!outb) 4945 return -ENOMEM; 4946 4947 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4948 outlen); 4949 if (err) 4950 goto out; 4951 4952 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4953 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4954 4955 mlx5_state = be32_to_cpu(context->flags) >> 28; 4956 4957 qp->state = to_ib_qp_state(mlx5_state); 4958 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4959 qp_attr->path_mig_state = 4960 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4961 qp_attr->qkey = be32_to_cpu(context->qkey); 4962 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4963 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4964 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4965 qp_attr->qp_access_flags = 4966 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4967 4968 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4969 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4970 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4971 qp_attr->alt_pkey_index = 4972 be16_to_cpu(context->alt_path.pkey_index); 4973 qp_attr->alt_port_num = 4974 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4975 } 4976 4977 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4978 qp_attr->port_num = context->pri_path.port; 4979 4980 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4981 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4982 4983 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4984 4985 qp_attr->max_dest_rd_atomic = 4986 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4987 qp_attr->min_rnr_timer = 4988 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4989 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4990 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4991 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4992 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4993 4994 out: 4995 kfree(outb); 4996 return err; 4997 } 4998 4999 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5000 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5001 struct ib_qp_init_attr *qp_init_attr) 5002 { 5003 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5004 u32 *out; 5005 u32 access_flags = 0; 5006 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5007 void *dctc; 5008 int err; 5009 int supported_mask = IB_QP_STATE | 5010 IB_QP_ACCESS_FLAGS | 5011 IB_QP_PORT | 5012 IB_QP_MIN_RNR_TIMER | 5013 IB_QP_AV | 5014 IB_QP_PATH_MTU | 5015 IB_QP_PKEY_INDEX; 5016 5017 if (qp_attr_mask & ~supported_mask) 5018 return -EINVAL; 5019 if (mqp->state != IB_QPS_RTR) 5020 return -EINVAL; 5021 5022 out = kzalloc(outlen, GFP_KERNEL); 5023 if (!out) 5024 return -ENOMEM; 5025 5026 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5027 if (err) 5028 goto out; 5029 5030 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5031 5032 if (qp_attr_mask & IB_QP_STATE) 5033 qp_attr->qp_state = IB_QPS_RTR; 5034 5035 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5036 if (MLX5_GET(dctc, dctc, rre)) 5037 access_flags |= IB_ACCESS_REMOTE_READ; 5038 if (MLX5_GET(dctc, dctc, rwe)) 5039 access_flags |= IB_ACCESS_REMOTE_WRITE; 5040 if (MLX5_GET(dctc, dctc, rae)) 5041 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5042 qp_attr->qp_access_flags = access_flags; 5043 } 5044 5045 if (qp_attr_mask & IB_QP_PORT) 5046 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5047 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5048 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5049 if (qp_attr_mask & IB_QP_AV) { 5050 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5051 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5052 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5053 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5054 } 5055 if (qp_attr_mask & IB_QP_PATH_MTU) 5056 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5057 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5058 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5059 out: 5060 kfree(out); 5061 return err; 5062 } 5063 5064 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5065 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5066 { 5067 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5068 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5069 int err = 0; 5070 u8 raw_packet_qp_state; 5071 5072 if (ibqp->rwq_ind_tbl) 5073 return -ENOSYS; 5074 5075 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5076 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5077 qp_init_attr); 5078 5079 /* Not all of output fields are applicable, make sure to zero them */ 5080 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5081 memset(qp_attr, 0, sizeof(*qp_attr)); 5082 5083 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5084 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5085 qp_attr_mask, qp_init_attr); 5086 5087 mutex_lock(&qp->mutex); 5088 5089 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5090 qp->flags & MLX5_IB_QP_UNDERLAY) { 5091 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5092 if (err) 5093 goto out; 5094 qp->state = raw_packet_qp_state; 5095 qp_attr->port_num = 1; 5096 } else { 5097 err = query_qp_attr(dev, qp, qp_attr); 5098 if (err) 5099 goto out; 5100 } 5101 5102 qp_attr->qp_state = qp->state; 5103 qp_attr->cur_qp_state = qp_attr->qp_state; 5104 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5105 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5106 5107 if (!ibqp->uobject) { 5108 qp_attr->cap.max_send_wr = qp->sq.max_post; 5109 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5110 qp_init_attr->qp_context = ibqp->qp_context; 5111 } else { 5112 qp_attr->cap.max_send_wr = 0; 5113 qp_attr->cap.max_send_sge = 0; 5114 } 5115 5116 qp_init_attr->qp_type = ibqp->qp_type; 5117 qp_init_attr->recv_cq = ibqp->recv_cq; 5118 qp_init_attr->send_cq = ibqp->send_cq; 5119 qp_init_attr->srq = ibqp->srq; 5120 qp_attr->cap.max_inline_data = qp->max_inline_data; 5121 5122 qp_init_attr->cap = qp_attr->cap; 5123 5124 qp_init_attr->create_flags = 0; 5125 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5126 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5127 5128 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5129 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5130 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5131 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5132 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5133 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5134 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5135 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5136 5137 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5138 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5139 5140 out: 5141 mutex_unlock(&qp->mutex); 5142 return err; 5143 } 5144 5145 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5146 struct ib_ucontext *context, 5147 struct ib_udata *udata) 5148 { 5149 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5150 struct mlx5_ib_xrcd *xrcd; 5151 int err; 5152 5153 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5154 return ERR_PTR(-ENOSYS); 5155 5156 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5157 if (!xrcd) 5158 return ERR_PTR(-ENOMEM); 5159 5160 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 5161 if (err) { 5162 kfree(xrcd); 5163 return ERR_PTR(-ENOMEM); 5164 } 5165 5166 return &xrcd->ibxrcd; 5167 } 5168 5169 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5170 { 5171 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5172 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5173 int err; 5174 5175 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 5176 if (err) 5177 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5178 5179 kfree(xrcd); 5180 return 0; 5181 } 5182 5183 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5184 { 5185 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5186 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5187 struct ib_event event; 5188 5189 if (rwq->ibwq.event_handler) { 5190 event.device = rwq->ibwq.device; 5191 event.element.wq = &rwq->ibwq; 5192 switch (type) { 5193 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5194 event.event = IB_EVENT_WQ_FATAL; 5195 break; 5196 default: 5197 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5198 return; 5199 } 5200 5201 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5202 } 5203 } 5204 5205 static int set_delay_drop(struct mlx5_ib_dev *dev) 5206 { 5207 int err = 0; 5208 5209 mutex_lock(&dev->delay_drop.lock); 5210 if (dev->delay_drop.activate) 5211 goto out; 5212 5213 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5214 if (err) 5215 goto out; 5216 5217 dev->delay_drop.activate = true; 5218 out: 5219 mutex_unlock(&dev->delay_drop.lock); 5220 5221 if (!err) 5222 atomic_inc(&dev->delay_drop.rqs_cnt); 5223 return err; 5224 } 5225 5226 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5227 struct ib_wq_init_attr *init_attr) 5228 { 5229 struct mlx5_ib_dev *dev; 5230 int has_net_offloads; 5231 __be64 *rq_pas0; 5232 void *in; 5233 void *rqc; 5234 void *wq; 5235 int inlen; 5236 int err; 5237 5238 dev = to_mdev(pd->device); 5239 5240 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5241 in = kvzalloc(inlen, GFP_KERNEL); 5242 if (!in) 5243 return -ENOMEM; 5244 5245 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5246 MLX5_SET(rqc, rqc, mem_rq_type, 5247 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5248 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5249 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5250 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5251 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5252 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5253 MLX5_SET(wq, wq, wq_type, 5254 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5255 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5256 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5257 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5258 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5259 err = -EOPNOTSUPP; 5260 goto out; 5261 } else { 5262 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5263 } 5264 } 5265 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5266 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5267 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5268 MLX5_SET(wq, wq, log_wqe_stride_size, 5269 rwq->single_stride_log_num_of_bytes - 5270 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5271 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5272 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5273 } 5274 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5275 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5276 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5277 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5278 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5279 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5280 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5281 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5282 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5283 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5284 err = -EOPNOTSUPP; 5285 goto out; 5286 } 5287 } else { 5288 MLX5_SET(rqc, rqc, vsd, 1); 5289 } 5290 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5291 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5292 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5293 err = -EOPNOTSUPP; 5294 goto out; 5295 } 5296 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5297 } 5298 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5299 if (!(dev->ib_dev.attrs.raw_packet_caps & 5300 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5301 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5302 err = -EOPNOTSUPP; 5303 goto out; 5304 } 5305 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5306 } 5307 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5308 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5309 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5310 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5311 err = set_delay_drop(dev); 5312 if (err) { 5313 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5314 err); 5315 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5316 } else { 5317 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5318 } 5319 } 5320 out: 5321 kvfree(in); 5322 return err; 5323 } 5324 5325 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5326 struct ib_wq_init_attr *wq_init_attr, 5327 struct mlx5_ib_create_wq *ucmd, 5328 struct mlx5_ib_rwq *rwq) 5329 { 5330 /* Sanity check RQ size before proceeding */ 5331 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5332 return -EINVAL; 5333 5334 if (!ucmd->rq_wqe_count) 5335 return -EINVAL; 5336 5337 rwq->wqe_count = ucmd->rq_wqe_count; 5338 rwq->wqe_shift = ucmd->rq_wqe_shift; 5339 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 5340 rwq->log_rq_stride = rwq->wqe_shift; 5341 rwq->log_rq_size = ilog2(rwq->wqe_count); 5342 return 0; 5343 } 5344 5345 static int prepare_user_rq(struct ib_pd *pd, 5346 struct ib_wq_init_attr *init_attr, 5347 struct ib_udata *udata, 5348 struct mlx5_ib_rwq *rwq) 5349 { 5350 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5351 struct mlx5_ib_create_wq ucmd = {}; 5352 int err; 5353 size_t required_cmd_sz; 5354 5355 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5356 + sizeof(ucmd.single_stride_log_num_of_bytes); 5357 if (udata->inlen < required_cmd_sz) { 5358 mlx5_ib_dbg(dev, "invalid inlen\n"); 5359 return -EINVAL; 5360 } 5361 5362 if (udata->inlen > sizeof(ucmd) && 5363 !ib_is_udata_cleared(udata, sizeof(ucmd), 5364 udata->inlen - sizeof(ucmd))) { 5365 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5366 return -EOPNOTSUPP; 5367 } 5368 5369 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5370 mlx5_ib_dbg(dev, "copy failed\n"); 5371 return -EFAULT; 5372 } 5373 5374 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5375 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5376 return -EOPNOTSUPP; 5377 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5378 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5379 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5380 return -EOPNOTSUPP; 5381 } 5382 if ((ucmd.single_stride_log_num_of_bytes < 5383 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5384 (ucmd.single_stride_log_num_of_bytes > 5385 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5386 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5387 ucmd.single_stride_log_num_of_bytes, 5388 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5389 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5390 return -EINVAL; 5391 } 5392 if ((ucmd.single_wqe_log_num_of_strides > 5393 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5394 (ucmd.single_wqe_log_num_of_strides < 5395 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5396 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5397 ucmd.single_wqe_log_num_of_strides, 5398 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5399 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5400 return -EINVAL; 5401 } 5402 rwq->single_stride_log_num_of_bytes = 5403 ucmd.single_stride_log_num_of_bytes; 5404 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5405 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5406 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5407 } 5408 5409 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5410 if (err) { 5411 mlx5_ib_dbg(dev, "err %d\n", err); 5412 return err; 5413 } 5414 5415 err = create_user_rq(dev, pd, rwq, &ucmd); 5416 if (err) { 5417 mlx5_ib_dbg(dev, "err %d\n", err); 5418 if (err) 5419 return err; 5420 } 5421 5422 rwq->user_index = ucmd.user_index; 5423 return 0; 5424 } 5425 5426 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5427 struct ib_wq_init_attr *init_attr, 5428 struct ib_udata *udata) 5429 { 5430 struct mlx5_ib_dev *dev; 5431 struct mlx5_ib_rwq *rwq; 5432 struct mlx5_ib_create_wq_resp resp = {}; 5433 size_t min_resp_len; 5434 int err; 5435 5436 if (!udata) 5437 return ERR_PTR(-ENOSYS); 5438 5439 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5440 if (udata->outlen && udata->outlen < min_resp_len) 5441 return ERR_PTR(-EINVAL); 5442 5443 dev = to_mdev(pd->device); 5444 switch (init_attr->wq_type) { 5445 case IB_WQT_RQ: 5446 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5447 if (!rwq) 5448 return ERR_PTR(-ENOMEM); 5449 err = prepare_user_rq(pd, init_attr, udata, rwq); 5450 if (err) 5451 goto err; 5452 err = create_rq(rwq, pd, init_attr); 5453 if (err) 5454 goto err_user_rq; 5455 break; 5456 default: 5457 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5458 init_attr->wq_type); 5459 return ERR_PTR(-EINVAL); 5460 } 5461 5462 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5463 rwq->ibwq.state = IB_WQS_RESET; 5464 if (udata->outlen) { 5465 resp.response_length = offsetof(typeof(resp), response_length) + 5466 sizeof(resp.response_length); 5467 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5468 if (err) 5469 goto err_copy; 5470 } 5471 5472 rwq->core_qp.event = mlx5_ib_wq_event; 5473 rwq->ibwq.event_handler = init_attr->event_handler; 5474 return &rwq->ibwq; 5475 5476 err_copy: 5477 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5478 err_user_rq: 5479 destroy_user_rq(dev, pd, rwq); 5480 err: 5481 kfree(rwq); 5482 return ERR_PTR(err); 5483 } 5484 5485 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5486 { 5487 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5488 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5489 5490 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5491 destroy_user_rq(dev, wq->pd, rwq); 5492 kfree(rwq); 5493 5494 return 0; 5495 } 5496 5497 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5498 struct ib_rwq_ind_table_init_attr *init_attr, 5499 struct ib_udata *udata) 5500 { 5501 struct mlx5_ib_dev *dev = to_mdev(device); 5502 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5503 int sz = 1 << init_attr->log_ind_tbl_size; 5504 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5505 size_t min_resp_len; 5506 int inlen; 5507 int err; 5508 int i; 5509 u32 *in; 5510 void *rqtc; 5511 5512 if (udata->inlen > 0 && 5513 !ib_is_udata_cleared(udata, 0, 5514 udata->inlen)) 5515 return ERR_PTR(-EOPNOTSUPP); 5516 5517 if (init_attr->log_ind_tbl_size > 5518 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5519 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5520 init_attr->log_ind_tbl_size, 5521 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5522 return ERR_PTR(-EINVAL); 5523 } 5524 5525 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5526 if (udata->outlen && udata->outlen < min_resp_len) 5527 return ERR_PTR(-EINVAL); 5528 5529 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5530 if (!rwq_ind_tbl) 5531 return ERR_PTR(-ENOMEM); 5532 5533 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5534 in = kvzalloc(inlen, GFP_KERNEL); 5535 if (!in) { 5536 err = -ENOMEM; 5537 goto err; 5538 } 5539 5540 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5541 5542 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5543 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5544 5545 for (i = 0; i < sz; i++) 5546 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5547 5548 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5549 kvfree(in); 5550 5551 if (err) 5552 goto err; 5553 5554 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5555 if (udata->outlen) { 5556 resp.response_length = offsetof(typeof(resp), response_length) + 5557 sizeof(resp.response_length); 5558 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5559 if (err) 5560 goto err_copy; 5561 } 5562 5563 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5564 5565 err_copy: 5566 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5567 err: 5568 kfree(rwq_ind_tbl); 5569 return ERR_PTR(err); 5570 } 5571 5572 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5573 { 5574 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5575 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5576 5577 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5578 5579 kfree(rwq_ind_tbl); 5580 return 0; 5581 } 5582 5583 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5584 u32 wq_attr_mask, struct ib_udata *udata) 5585 { 5586 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5587 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5588 struct mlx5_ib_modify_wq ucmd = {}; 5589 size_t required_cmd_sz; 5590 int curr_wq_state; 5591 int wq_state; 5592 int inlen; 5593 int err; 5594 void *rqc; 5595 void *in; 5596 5597 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5598 if (udata->inlen < required_cmd_sz) 5599 return -EINVAL; 5600 5601 if (udata->inlen > sizeof(ucmd) && 5602 !ib_is_udata_cleared(udata, sizeof(ucmd), 5603 udata->inlen - sizeof(ucmd))) 5604 return -EOPNOTSUPP; 5605 5606 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5607 return -EFAULT; 5608 5609 if (ucmd.comp_mask || ucmd.reserved) 5610 return -EOPNOTSUPP; 5611 5612 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5613 in = kvzalloc(inlen, GFP_KERNEL); 5614 if (!in) 5615 return -ENOMEM; 5616 5617 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5618 5619 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5620 wq_attr->curr_wq_state : wq->state; 5621 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5622 wq_attr->wq_state : curr_wq_state; 5623 if (curr_wq_state == IB_WQS_ERR) 5624 curr_wq_state = MLX5_RQC_STATE_ERR; 5625 if (wq_state == IB_WQS_ERR) 5626 wq_state = MLX5_RQC_STATE_ERR; 5627 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5628 MLX5_SET(rqc, rqc, state, wq_state); 5629 5630 if (wq_attr_mask & IB_WQ_FLAGS) { 5631 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5632 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5633 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5634 mlx5_ib_dbg(dev, "VLAN offloads are not " 5635 "supported\n"); 5636 err = -EOPNOTSUPP; 5637 goto out; 5638 } 5639 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5640 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5641 MLX5_SET(rqc, rqc, vsd, 5642 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5643 } 5644 5645 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5646 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5647 err = -EOPNOTSUPP; 5648 goto out; 5649 } 5650 } 5651 5652 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5653 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5654 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5655 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5656 MLX5_SET(rqc, rqc, counter_set_id, 5657 dev->port->cnts.set_id); 5658 } else 5659 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5660 dev->ib_dev.name); 5661 } 5662 5663 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5664 if (!err) 5665 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5666 5667 out: 5668 kvfree(in); 5669 return err; 5670 } 5671