1 /* 2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include "mlx5_ib.h" 36 #include "user.h" 37 38 /* not supported currently */ 39 static int wq_signature; 40 41 enum { 42 MLX5_IB_ACK_REQ_FREQ = 8, 43 }; 44 45 enum { 46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 48 MLX5_IB_LINK_TYPE_IB = 0, 49 MLX5_IB_LINK_TYPE_ETH = 1 50 }; 51 52 enum { 53 MLX5_IB_SQ_STRIDE = 6, 54 MLX5_IB_CACHE_LINE_SIZE = 64, 55 }; 56 57 static const u32 mlx5_ib_opcode[] = { 58 [IB_WR_SEND] = MLX5_OPCODE_SEND, 59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR, 68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 71 }; 72 73 struct umr_wr { 74 u64 virt_addr; 75 struct ib_pd *pd; 76 unsigned int page_shift; 77 unsigned int npages; 78 u32 length; 79 int access_flags; 80 u32 mkey; 81 }; 82 83 static int is_qp0(enum ib_qp_type qp_type) 84 { 85 return qp_type == IB_QPT_SMI; 86 } 87 88 static int is_qp1(enum ib_qp_type qp_type) 89 { 90 return qp_type == IB_QPT_GSI; 91 } 92 93 static int is_sqp(enum ib_qp_type qp_type) 94 { 95 return is_qp0(qp_type) || is_qp1(qp_type); 96 } 97 98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 99 { 100 return mlx5_buf_offset(&qp->buf, offset); 101 } 102 103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 104 { 105 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 106 } 107 108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 109 { 110 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 111 } 112 113 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 114 { 115 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 116 struct ib_event event; 117 118 if (type == MLX5_EVENT_TYPE_PATH_MIG) 119 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 120 121 if (ibqp->event_handler) { 122 event.device = ibqp->device; 123 event.element.qp = ibqp; 124 switch (type) { 125 case MLX5_EVENT_TYPE_PATH_MIG: 126 event.event = IB_EVENT_PATH_MIG; 127 break; 128 case MLX5_EVENT_TYPE_COMM_EST: 129 event.event = IB_EVENT_COMM_EST; 130 break; 131 case MLX5_EVENT_TYPE_SQ_DRAINED: 132 event.event = IB_EVENT_SQ_DRAINED; 133 break; 134 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 135 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 136 break; 137 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 138 event.event = IB_EVENT_QP_FATAL; 139 break; 140 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 141 event.event = IB_EVENT_PATH_MIG_ERR; 142 break; 143 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 144 event.event = IB_EVENT_QP_REQ_ERR; 145 break; 146 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 147 event.event = IB_EVENT_QP_ACCESS_ERR; 148 break; 149 default: 150 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 151 return; 152 } 153 154 ibqp->event_handler(&event, ibqp->qp_context); 155 } 156 } 157 158 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 159 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 160 { 161 int wqe_size; 162 int wq_size; 163 164 /* Sanity check RQ size before proceeding */ 165 if (cap->max_recv_wr > dev->mdev.caps.max_wqes) 166 return -EINVAL; 167 168 if (!has_rq) { 169 qp->rq.max_gs = 0; 170 qp->rq.wqe_cnt = 0; 171 qp->rq.wqe_shift = 0; 172 } else { 173 if (ucmd) { 174 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 175 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 176 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 177 qp->rq.max_post = qp->rq.wqe_cnt; 178 } else { 179 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 180 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 181 wqe_size = roundup_pow_of_two(wqe_size); 182 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 183 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 184 qp->rq.wqe_cnt = wq_size / wqe_size; 185 if (wqe_size > dev->mdev.caps.max_rq_desc_sz) { 186 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 187 wqe_size, 188 dev->mdev.caps.max_rq_desc_sz); 189 return -EINVAL; 190 } 191 qp->rq.wqe_shift = ilog2(wqe_size); 192 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 193 qp->rq.max_post = qp->rq.wqe_cnt; 194 } 195 } 196 197 return 0; 198 } 199 200 static int sq_overhead(enum ib_qp_type qp_type) 201 { 202 int size = 0; 203 204 switch (qp_type) { 205 case IB_QPT_XRC_INI: 206 size += sizeof(struct mlx5_wqe_xrc_seg); 207 /* fall through */ 208 case IB_QPT_RC: 209 size += sizeof(struct mlx5_wqe_ctrl_seg) + 210 sizeof(struct mlx5_wqe_atomic_seg) + 211 sizeof(struct mlx5_wqe_raddr_seg); 212 break; 213 214 case IB_QPT_XRC_TGT: 215 return 0; 216 217 case IB_QPT_UC: 218 size += sizeof(struct mlx5_wqe_ctrl_seg) + 219 sizeof(struct mlx5_wqe_raddr_seg) + 220 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 221 sizeof(struct mlx5_mkey_seg); 222 break; 223 224 case IB_QPT_UD: 225 case IB_QPT_SMI: 226 case IB_QPT_GSI: 227 size += sizeof(struct mlx5_wqe_ctrl_seg) + 228 sizeof(struct mlx5_wqe_datagram_seg); 229 break; 230 231 case MLX5_IB_QPT_REG_UMR: 232 size += sizeof(struct mlx5_wqe_ctrl_seg) + 233 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 234 sizeof(struct mlx5_mkey_seg); 235 break; 236 237 default: 238 return -EINVAL; 239 } 240 241 return size; 242 } 243 244 static int calc_send_wqe(struct ib_qp_init_attr *attr) 245 { 246 int inl_size = 0; 247 int size; 248 249 size = sq_overhead(attr->qp_type); 250 if (size < 0) 251 return size; 252 253 if (attr->cap.max_inline_data) { 254 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 255 attr->cap.max_inline_data; 256 } 257 258 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 259 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 260 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 261 return MLX5_SIG_WQE_SIZE; 262 else 263 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 264 } 265 266 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 267 struct mlx5_ib_qp *qp) 268 { 269 int wqe_size; 270 int wq_size; 271 272 if (!attr->cap.max_send_wr) 273 return 0; 274 275 wqe_size = calc_send_wqe(attr); 276 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 277 if (wqe_size < 0) 278 return wqe_size; 279 280 if (wqe_size > dev->mdev.caps.max_sq_desc_sz) { 281 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 282 wqe_size, dev->mdev.caps.max_sq_desc_sz); 283 return -EINVAL; 284 } 285 286 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) - 287 sizeof(struct mlx5_wqe_inline_seg); 288 attr->cap.max_inline_data = qp->max_inline_data; 289 290 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 291 qp->signature_en = true; 292 293 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 294 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 295 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) { 296 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 297 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes); 298 return -ENOMEM; 299 } 300 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 301 qp->sq.max_gs = attr->cap.max_send_sge; 302 qp->sq.max_post = wq_size / wqe_size; 303 attr->cap.max_send_wr = qp->sq.max_post; 304 305 return wq_size; 306 } 307 308 static int set_user_buf_size(struct mlx5_ib_dev *dev, 309 struct mlx5_ib_qp *qp, 310 struct mlx5_ib_create_qp *ucmd) 311 { 312 int desc_sz = 1 << qp->sq.wqe_shift; 313 314 if (desc_sz > dev->mdev.caps.max_sq_desc_sz) { 315 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 316 desc_sz, dev->mdev.caps.max_sq_desc_sz); 317 return -EINVAL; 318 } 319 320 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 321 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 322 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 323 return -EINVAL; 324 } 325 326 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 327 328 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) { 329 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 330 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes); 331 return -EINVAL; 332 } 333 334 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 335 (qp->sq.wqe_cnt << 6); 336 337 return 0; 338 } 339 340 static int qp_has_rq(struct ib_qp_init_attr *attr) 341 { 342 if (attr->qp_type == IB_QPT_XRC_INI || 343 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 344 attr->qp_type == MLX5_IB_QPT_REG_UMR || 345 !attr->cap.max_recv_wr) 346 return 0; 347 348 return 1; 349 } 350 351 static int first_med_uuar(void) 352 { 353 return 1; 354 } 355 356 static int next_uuar(int n) 357 { 358 n++; 359 360 while (((n % 4) & 2)) 361 n++; 362 363 return n; 364 } 365 366 static int num_med_uuar(struct mlx5_uuar_info *uuari) 367 { 368 int n; 369 370 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 371 uuari->num_low_latency_uuars - 1; 372 373 return n >= 0 ? n : 0; 374 } 375 376 static int max_uuari(struct mlx5_uuar_info *uuari) 377 { 378 return uuari->num_uars * 4; 379 } 380 381 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 382 { 383 int med; 384 int i; 385 int t; 386 387 med = num_med_uuar(uuari); 388 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 389 t++; 390 if (t == med) 391 return next_uuar(i); 392 } 393 394 return 0; 395 } 396 397 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 398 { 399 int i; 400 401 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 402 if (!test_bit(i, uuari->bitmap)) { 403 set_bit(i, uuari->bitmap); 404 uuari->count[i]++; 405 return i; 406 } 407 } 408 409 return -ENOMEM; 410 } 411 412 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 413 { 414 int minidx = first_med_uuar(); 415 int i; 416 417 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 418 if (uuari->count[i] < uuari->count[minidx]) 419 minidx = i; 420 } 421 422 uuari->count[minidx]++; 423 return minidx; 424 } 425 426 static int alloc_uuar(struct mlx5_uuar_info *uuari, 427 enum mlx5_ib_latency_class lat) 428 { 429 int uuarn = -EINVAL; 430 431 mutex_lock(&uuari->lock); 432 switch (lat) { 433 case MLX5_IB_LATENCY_CLASS_LOW: 434 uuarn = 0; 435 uuari->count[uuarn]++; 436 break; 437 438 case MLX5_IB_LATENCY_CLASS_MEDIUM: 439 if (uuari->ver < 2) 440 uuarn = -ENOMEM; 441 else 442 uuarn = alloc_med_class_uuar(uuari); 443 break; 444 445 case MLX5_IB_LATENCY_CLASS_HIGH: 446 if (uuari->ver < 2) 447 uuarn = -ENOMEM; 448 else 449 uuarn = alloc_high_class_uuar(uuari); 450 break; 451 452 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 453 uuarn = 2; 454 break; 455 } 456 mutex_unlock(&uuari->lock); 457 458 return uuarn; 459 } 460 461 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 462 { 463 clear_bit(uuarn, uuari->bitmap); 464 --uuari->count[uuarn]; 465 } 466 467 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 468 { 469 clear_bit(uuarn, uuari->bitmap); 470 --uuari->count[uuarn]; 471 } 472 473 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 474 { 475 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 476 int high_uuar = nuuars - uuari->num_low_latency_uuars; 477 478 mutex_lock(&uuari->lock); 479 if (uuarn == 0) { 480 --uuari->count[uuarn]; 481 goto out; 482 } 483 484 if (uuarn < high_uuar) { 485 free_med_class_uuar(uuari, uuarn); 486 goto out; 487 } 488 489 free_high_class_uuar(uuari, uuarn); 490 491 out: 492 mutex_unlock(&uuari->lock); 493 } 494 495 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 496 { 497 switch (state) { 498 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 499 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 500 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 501 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 502 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 503 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 504 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 505 default: return -1; 506 } 507 } 508 509 static int to_mlx5_st(enum ib_qp_type type) 510 { 511 switch (type) { 512 case IB_QPT_RC: return MLX5_QP_ST_RC; 513 case IB_QPT_UC: return MLX5_QP_ST_UC; 514 case IB_QPT_UD: return MLX5_QP_ST_UD; 515 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 516 case IB_QPT_XRC_INI: 517 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 518 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 519 case IB_QPT_GSI: return MLX5_QP_ST_QP1; 520 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 521 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 522 case IB_QPT_RAW_PACKET: 523 case IB_QPT_MAX: 524 default: return -EINVAL; 525 } 526 } 527 528 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 529 { 530 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 531 } 532 533 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 534 struct mlx5_ib_qp *qp, struct ib_udata *udata, 535 struct mlx5_create_qp_mbox_in **in, 536 struct mlx5_ib_create_qp_resp *resp, int *inlen) 537 { 538 struct mlx5_ib_ucontext *context; 539 struct mlx5_ib_create_qp ucmd; 540 int page_shift = 0; 541 int uar_index; 542 int npages; 543 u32 offset = 0; 544 int uuarn; 545 int ncont = 0; 546 int err; 547 548 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 549 if (err) { 550 mlx5_ib_dbg(dev, "copy failed\n"); 551 return err; 552 } 553 554 context = to_mucontext(pd->uobject->context); 555 /* 556 * TBD: should come from the verbs when we have the API 557 */ 558 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 559 if (uuarn < 0) { 560 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 561 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 562 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 563 if (uuarn < 0) { 564 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 565 mlx5_ib_dbg(dev, "reverting to high latency\n"); 566 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 567 if (uuarn < 0) { 568 mlx5_ib_warn(dev, "uuar allocation failed\n"); 569 return uuarn; 570 } 571 } 572 } 573 574 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 575 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 576 577 err = set_user_buf_size(dev, qp, &ucmd); 578 if (err) 579 goto err_uuar; 580 581 if (ucmd.buf_addr && qp->buf_size) { 582 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 583 qp->buf_size, 0, 0); 584 if (IS_ERR(qp->umem)) { 585 mlx5_ib_dbg(dev, "umem_get failed\n"); 586 err = PTR_ERR(qp->umem); 587 goto err_uuar; 588 } 589 } else { 590 qp->umem = NULL; 591 } 592 593 if (qp->umem) { 594 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift, 595 &ncont, NULL); 596 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset); 597 if (err) { 598 mlx5_ib_warn(dev, "bad offset\n"); 599 goto err_umem; 600 } 601 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n", 602 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset); 603 } 604 605 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont; 606 *in = mlx5_vzalloc(*inlen); 607 if (!*in) { 608 err = -ENOMEM; 609 goto err_umem; 610 } 611 if (qp->umem) 612 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0); 613 (*in)->ctx.log_pg_sz_remote_qpn = 614 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 615 (*in)->ctx.params2 = cpu_to_be32(offset << 6); 616 617 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 618 resp->uuar_index = uuarn; 619 qp->uuarn = uuarn; 620 621 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 622 if (err) { 623 mlx5_ib_dbg(dev, "map failed\n"); 624 goto err_free; 625 } 626 627 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 628 if (err) { 629 mlx5_ib_dbg(dev, "copy failed\n"); 630 goto err_unmap; 631 } 632 qp->create_type = MLX5_QP_USER; 633 634 return 0; 635 636 err_unmap: 637 mlx5_ib_db_unmap_user(context, &qp->db); 638 639 err_free: 640 mlx5_vfree(*in); 641 642 err_umem: 643 if (qp->umem) 644 ib_umem_release(qp->umem); 645 646 err_uuar: 647 free_uuar(&context->uuari, uuarn); 648 return err; 649 } 650 651 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp) 652 { 653 struct mlx5_ib_ucontext *context; 654 655 context = to_mucontext(pd->uobject->context); 656 mlx5_ib_db_unmap_user(context, &qp->db); 657 if (qp->umem) 658 ib_umem_release(qp->umem); 659 free_uuar(&context->uuari, qp->uuarn); 660 } 661 662 static int create_kernel_qp(struct mlx5_ib_dev *dev, 663 struct ib_qp_init_attr *init_attr, 664 struct mlx5_ib_qp *qp, 665 struct mlx5_create_qp_mbox_in **in, int *inlen) 666 { 667 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 668 struct mlx5_uuar_info *uuari; 669 int uar_index; 670 int uuarn; 671 int err; 672 673 uuari = &dev->mdev.priv.uuari; 674 if (init_attr->create_flags & ~IB_QP_CREATE_SIGNATURE_EN) 675 return -EINVAL; 676 677 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 678 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 679 680 uuarn = alloc_uuar(uuari, lc); 681 if (uuarn < 0) { 682 mlx5_ib_dbg(dev, "\n"); 683 return -ENOMEM; 684 } 685 686 qp->bf = &uuari->bfs[uuarn]; 687 uar_index = qp->bf->uar->index; 688 689 err = calc_sq_size(dev, init_attr, qp); 690 if (err < 0) { 691 mlx5_ib_dbg(dev, "err %d\n", err); 692 goto err_uuar; 693 } 694 695 qp->rq.offset = 0; 696 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 697 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 698 699 err = mlx5_buf_alloc(&dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf); 700 if (err) { 701 mlx5_ib_dbg(dev, "err %d\n", err); 702 goto err_uuar; 703 } 704 705 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 706 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages; 707 *in = mlx5_vzalloc(*inlen); 708 if (!*in) { 709 err = -ENOMEM; 710 goto err_buf; 711 } 712 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 713 (*in)->ctx.log_pg_sz_remote_qpn = 714 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 715 /* Set "fast registration enabled" for all kernel QPs */ 716 (*in)->ctx.params1 |= cpu_to_be32(1 << 11); 717 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4); 718 719 mlx5_fill_page_array(&qp->buf, (*in)->pas); 720 721 err = mlx5_db_alloc(&dev->mdev, &qp->db); 722 if (err) { 723 mlx5_ib_dbg(dev, "err %d\n", err); 724 goto err_free; 725 } 726 727 qp->db.db[0] = 0; 728 qp->db.db[1] = 0; 729 730 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 731 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 732 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 733 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 734 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 735 736 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 737 !qp->sq.w_list || !qp->sq.wqe_head) { 738 err = -ENOMEM; 739 goto err_wrid; 740 } 741 qp->create_type = MLX5_QP_KERNEL; 742 743 return 0; 744 745 err_wrid: 746 mlx5_db_free(&dev->mdev, &qp->db); 747 kfree(qp->sq.wqe_head); 748 kfree(qp->sq.w_list); 749 kfree(qp->sq.wrid); 750 kfree(qp->sq.wr_data); 751 kfree(qp->rq.wrid); 752 753 err_free: 754 mlx5_vfree(*in); 755 756 err_buf: 757 mlx5_buf_free(&dev->mdev, &qp->buf); 758 759 err_uuar: 760 free_uuar(&dev->mdev.priv.uuari, uuarn); 761 return err; 762 } 763 764 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 765 { 766 mlx5_db_free(&dev->mdev, &qp->db); 767 kfree(qp->sq.wqe_head); 768 kfree(qp->sq.w_list); 769 kfree(qp->sq.wrid); 770 kfree(qp->sq.wr_data); 771 kfree(qp->rq.wrid); 772 mlx5_buf_free(&dev->mdev, &qp->buf); 773 free_uuar(&dev->mdev.priv.uuari, qp->bf->uuarn); 774 } 775 776 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 777 { 778 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 779 (attr->qp_type == IB_QPT_XRC_INI)) 780 return cpu_to_be32(MLX5_SRQ_RQ); 781 else if (!qp->has_rq) 782 return cpu_to_be32(MLX5_ZERO_LEN_RQ); 783 else 784 return cpu_to_be32(MLX5_NON_ZERO_RQ); 785 } 786 787 static int is_connected(enum ib_qp_type qp_type) 788 { 789 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 790 return 1; 791 792 return 0; 793 } 794 795 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 796 struct ib_qp_init_attr *init_attr, 797 struct ib_udata *udata, struct mlx5_ib_qp *qp) 798 { 799 struct mlx5_ib_resources *devr = &dev->devr; 800 struct mlx5_ib_create_qp_resp resp; 801 struct mlx5_create_qp_mbox_in *in; 802 struct mlx5_ib_create_qp ucmd; 803 int inlen = sizeof(*in); 804 int err; 805 806 mutex_init(&qp->mutex); 807 spin_lock_init(&qp->sq.lock); 808 spin_lock_init(&qp->rq.lock); 809 810 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 811 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 812 813 if (pd && pd->uobject) { 814 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 815 mlx5_ib_dbg(dev, "copy failed\n"); 816 return -EFAULT; 817 } 818 819 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 820 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 821 } else { 822 qp->wq_sig = !!wq_signature; 823 } 824 825 qp->has_rq = qp_has_rq(init_attr); 826 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 827 qp, (pd && pd->uobject) ? &ucmd : NULL); 828 if (err) { 829 mlx5_ib_dbg(dev, "err %d\n", err); 830 return err; 831 } 832 833 if (pd) { 834 if (pd->uobject) { 835 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 836 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 837 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 838 mlx5_ib_dbg(dev, "invalid rq params\n"); 839 return -EINVAL; 840 } 841 if (ucmd.sq_wqe_count > dev->mdev.caps.max_wqes) { 842 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 843 ucmd.sq_wqe_count, dev->mdev.caps.max_wqes); 844 return -EINVAL; 845 } 846 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen); 847 if (err) 848 mlx5_ib_dbg(dev, "err %d\n", err); 849 } else { 850 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen); 851 if (err) 852 mlx5_ib_dbg(dev, "err %d\n", err); 853 else 854 qp->pa_lkey = to_mpd(pd)->pa_lkey; 855 } 856 857 if (err) 858 return err; 859 } else { 860 in = mlx5_vzalloc(sizeof(*in)); 861 if (!in) 862 return -ENOMEM; 863 864 qp->create_type = MLX5_QP_EMPTY; 865 } 866 867 if (is_sqp(init_attr->qp_type)) 868 qp->port = init_attr->port_num; 869 870 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 | 871 MLX5_QP_PM_MIGRATED << 11); 872 873 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 874 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn); 875 else 876 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE); 877 878 if (qp->wq_sig) 879 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG); 880 881 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 882 int rcqe_sz; 883 int scqe_sz; 884 885 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 886 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 887 888 if (rcqe_sz == 128) 889 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE; 890 else 891 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE; 892 893 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 894 if (scqe_sz == 128) 895 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE; 896 else 897 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE; 898 } 899 } 900 901 if (qp->rq.wqe_cnt) { 902 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4); 903 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3; 904 } 905 906 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr); 907 908 if (qp->sq.wqe_cnt) 909 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11); 910 else 911 in->ctx.sq_crq_size |= cpu_to_be16(0x8000); 912 913 /* Set default resources */ 914 switch (init_attr->qp_type) { 915 case IB_QPT_XRC_TGT: 916 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 917 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 918 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 919 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn); 920 break; 921 case IB_QPT_XRC_INI: 922 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 923 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 924 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 925 break; 926 default: 927 if (init_attr->srq) { 928 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn); 929 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn); 930 } else { 931 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 932 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 933 } 934 } 935 936 if (init_attr->send_cq) 937 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn); 938 939 if (init_attr->recv_cq) 940 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn); 941 942 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma); 943 944 err = mlx5_core_create_qp(&dev->mdev, &qp->mqp, in, inlen); 945 if (err) { 946 mlx5_ib_dbg(dev, "create qp failed\n"); 947 goto err_create; 948 } 949 950 mlx5_vfree(in); 951 /* Hardware wants QPN written in big-endian order (after 952 * shifting) for send doorbell. Precompute this value to save 953 * a little bit when posting sends. 954 */ 955 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 956 957 qp->mqp.event = mlx5_ib_qp_event; 958 959 return 0; 960 961 err_create: 962 if (qp->create_type == MLX5_QP_USER) 963 destroy_qp_user(pd, qp); 964 else if (qp->create_type == MLX5_QP_KERNEL) 965 destroy_qp_kernel(dev, qp); 966 967 mlx5_vfree(in); 968 return err; 969 } 970 971 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 972 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 973 { 974 if (send_cq) { 975 if (recv_cq) { 976 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 977 spin_lock_irq(&send_cq->lock); 978 spin_lock_nested(&recv_cq->lock, 979 SINGLE_DEPTH_NESTING); 980 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 981 spin_lock_irq(&send_cq->lock); 982 __acquire(&recv_cq->lock); 983 } else { 984 spin_lock_irq(&recv_cq->lock); 985 spin_lock_nested(&send_cq->lock, 986 SINGLE_DEPTH_NESTING); 987 } 988 } else { 989 spin_lock_irq(&send_cq->lock); 990 } 991 } else if (recv_cq) { 992 spin_lock_irq(&recv_cq->lock); 993 } 994 } 995 996 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 997 __releases(&send_cq->lock) __releases(&recv_cq->lock) 998 { 999 if (send_cq) { 1000 if (recv_cq) { 1001 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1002 spin_unlock(&recv_cq->lock); 1003 spin_unlock_irq(&send_cq->lock); 1004 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1005 __release(&recv_cq->lock); 1006 spin_unlock_irq(&send_cq->lock); 1007 } else { 1008 spin_unlock(&send_cq->lock); 1009 spin_unlock_irq(&recv_cq->lock); 1010 } 1011 } else { 1012 spin_unlock_irq(&send_cq->lock); 1013 } 1014 } else if (recv_cq) { 1015 spin_unlock_irq(&recv_cq->lock); 1016 } 1017 } 1018 1019 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1020 { 1021 return to_mpd(qp->ibqp.pd); 1022 } 1023 1024 static void get_cqs(struct mlx5_ib_qp *qp, 1025 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1026 { 1027 switch (qp->ibqp.qp_type) { 1028 case IB_QPT_XRC_TGT: 1029 *send_cq = NULL; 1030 *recv_cq = NULL; 1031 break; 1032 case MLX5_IB_QPT_REG_UMR: 1033 case IB_QPT_XRC_INI: 1034 *send_cq = to_mcq(qp->ibqp.send_cq); 1035 *recv_cq = NULL; 1036 break; 1037 1038 case IB_QPT_SMI: 1039 case IB_QPT_GSI: 1040 case IB_QPT_RC: 1041 case IB_QPT_UC: 1042 case IB_QPT_UD: 1043 case IB_QPT_RAW_IPV6: 1044 case IB_QPT_RAW_ETHERTYPE: 1045 *send_cq = to_mcq(qp->ibqp.send_cq); 1046 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1047 break; 1048 1049 case IB_QPT_RAW_PACKET: 1050 case IB_QPT_MAX: 1051 default: 1052 *send_cq = NULL; 1053 *recv_cq = NULL; 1054 break; 1055 } 1056 } 1057 1058 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1059 { 1060 struct mlx5_ib_cq *send_cq, *recv_cq; 1061 struct mlx5_modify_qp_mbox_in *in; 1062 int err; 1063 1064 in = kzalloc(sizeof(*in), GFP_KERNEL); 1065 if (!in) 1066 return; 1067 if (qp->state != IB_QPS_RESET) 1068 if (mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(qp->state), 1069 MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp)) 1070 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n", 1071 qp->mqp.qpn); 1072 1073 get_cqs(qp, &send_cq, &recv_cq); 1074 1075 if (qp->create_type == MLX5_QP_KERNEL) { 1076 mlx5_ib_lock_cqs(send_cq, recv_cq); 1077 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn, 1078 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1079 if (send_cq != recv_cq) 1080 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1081 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1082 } 1083 1084 err = mlx5_core_destroy_qp(&dev->mdev, &qp->mqp); 1085 if (err) 1086 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn); 1087 kfree(in); 1088 1089 1090 if (qp->create_type == MLX5_QP_KERNEL) 1091 destroy_qp_kernel(dev, qp); 1092 else if (qp->create_type == MLX5_QP_USER) 1093 destroy_qp_user(&get_pd(qp)->ibpd, qp); 1094 } 1095 1096 static const char *ib_qp_type_str(enum ib_qp_type type) 1097 { 1098 switch (type) { 1099 case IB_QPT_SMI: 1100 return "IB_QPT_SMI"; 1101 case IB_QPT_GSI: 1102 return "IB_QPT_GSI"; 1103 case IB_QPT_RC: 1104 return "IB_QPT_RC"; 1105 case IB_QPT_UC: 1106 return "IB_QPT_UC"; 1107 case IB_QPT_UD: 1108 return "IB_QPT_UD"; 1109 case IB_QPT_RAW_IPV6: 1110 return "IB_QPT_RAW_IPV6"; 1111 case IB_QPT_RAW_ETHERTYPE: 1112 return "IB_QPT_RAW_ETHERTYPE"; 1113 case IB_QPT_XRC_INI: 1114 return "IB_QPT_XRC_INI"; 1115 case IB_QPT_XRC_TGT: 1116 return "IB_QPT_XRC_TGT"; 1117 case IB_QPT_RAW_PACKET: 1118 return "IB_QPT_RAW_PACKET"; 1119 case MLX5_IB_QPT_REG_UMR: 1120 return "MLX5_IB_QPT_REG_UMR"; 1121 case IB_QPT_MAX: 1122 default: 1123 return "Invalid QP type"; 1124 } 1125 } 1126 1127 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1128 struct ib_qp_init_attr *init_attr, 1129 struct ib_udata *udata) 1130 { 1131 struct mlx5_ib_dev *dev; 1132 struct mlx5_ib_qp *qp; 1133 u16 xrcdn = 0; 1134 int err; 1135 1136 if (pd) { 1137 dev = to_mdev(pd->device); 1138 } else { 1139 /* being cautious here */ 1140 if (init_attr->qp_type != IB_QPT_XRC_TGT && 1141 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 1142 pr_warn("%s: no PD for transport %s\n", __func__, 1143 ib_qp_type_str(init_attr->qp_type)); 1144 return ERR_PTR(-EINVAL); 1145 } 1146 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 1147 } 1148 1149 switch (init_attr->qp_type) { 1150 case IB_QPT_XRC_TGT: 1151 case IB_QPT_XRC_INI: 1152 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC)) { 1153 mlx5_ib_dbg(dev, "XRC not supported\n"); 1154 return ERR_PTR(-ENOSYS); 1155 } 1156 init_attr->recv_cq = NULL; 1157 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 1158 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1159 init_attr->send_cq = NULL; 1160 } 1161 1162 /* fall through */ 1163 case IB_QPT_RC: 1164 case IB_QPT_UC: 1165 case IB_QPT_UD: 1166 case IB_QPT_SMI: 1167 case IB_QPT_GSI: 1168 case MLX5_IB_QPT_REG_UMR: 1169 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1170 if (!qp) 1171 return ERR_PTR(-ENOMEM); 1172 1173 err = create_qp_common(dev, pd, init_attr, udata, qp); 1174 if (err) { 1175 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 1176 kfree(qp); 1177 return ERR_PTR(err); 1178 } 1179 1180 if (is_qp0(init_attr->qp_type)) 1181 qp->ibqp.qp_num = 0; 1182 else if (is_qp1(init_attr->qp_type)) 1183 qp->ibqp.qp_num = 1; 1184 else 1185 qp->ibqp.qp_num = qp->mqp.qpn; 1186 1187 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 1188 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn, 1189 to_mcq(init_attr->send_cq)->mcq.cqn); 1190 1191 qp->xrcdn = xrcdn; 1192 1193 break; 1194 1195 case IB_QPT_RAW_IPV6: 1196 case IB_QPT_RAW_ETHERTYPE: 1197 case IB_QPT_RAW_PACKET: 1198 case IB_QPT_MAX: 1199 default: 1200 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 1201 init_attr->qp_type); 1202 /* Don't support raw QPs */ 1203 return ERR_PTR(-EINVAL); 1204 } 1205 1206 return &qp->ibqp; 1207 } 1208 1209 int mlx5_ib_destroy_qp(struct ib_qp *qp) 1210 { 1211 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1212 struct mlx5_ib_qp *mqp = to_mqp(qp); 1213 1214 destroy_qp_common(dev, mqp); 1215 1216 kfree(mqp); 1217 1218 return 0; 1219 } 1220 1221 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 1222 int attr_mask) 1223 { 1224 u32 hw_access_flags = 0; 1225 u8 dest_rd_atomic; 1226 u32 access_flags; 1227 1228 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1229 dest_rd_atomic = attr->max_dest_rd_atomic; 1230 else 1231 dest_rd_atomic = qp->resp_depth; 1232 1233 if (attr_mask & IB_QP_ACCESS_FLAGS) 1234 access_flags = attr->qp_access_flags; 1235 else 1236 access_flags = qp->atomic_rd_en; 1237 1238 if (!dest_rd_atomic) 1239 access_flags &= IB_ACCESS_REMOTE_WRITE; 1240 1241 if (access_flags & IB_ACCESS_REMOTE_READ) 1242 hw_access_flags |= MLX5_QP_BIT_RRE; 1243 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1244 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 1245 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1246 hw_access_flags |= MLX5_QP_BIT_RWE; 1247 1248 return cpu_to_be32(hw_access_flags); 1249 } 1250 1251 enum { 1252 MLX5_PATH_FLAG_FL = 1 << 0, 1253 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 1254 MLX5_PATH_FLAG_COUNTER = 1 << 2, 1255 }; 1256 1257 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 1258 { 1259 if (rate == IB_RATE_PORT_CURRENT) { 1260 return 0; 1261 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 1262 return -EINVAL; 1263 } else { 1264 while (rate != IB_RATE_2_5_GBPS && 1265 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 1266 dev->mdev.caps.stat_rate_support)) 1267 --rate; 1268 } 1269 1270 return rate + MLX5_STAT_RATE_OFFSET; 1271 } 1272 1273 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah, 1274 struct mlx5_qp_path *path, u8 port, int attr_mask, 1275 u32 path_flags, const struct ib_qp_attr *attr) 1276 { 1277 int err; 1278 1279 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 1280 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0; 1281 1282 if (attr_mask & IB_QP_PKEY_INDEX) 1283 path->pkey_index = attr->pkey_index; 1284 1285 path->grh_mlid = ah->src_path_bits & 0x7f; 1286 path->rlid = cpu_to_be16(ah->dlid); 1287 1288 if (ah->ah_flags & IB_AH_GRH) { 1289 path->grh_mlid |= 1 << 7; 1290 path->mgid_index = ah->grh.sgid_index; 1291 path->hop_limit = ah->grh.hop_limit; 1292 path->tclass_flowlabel = 1293 cpu_to_be32((ah->grh.traffic_class << 20) | 1294 (ah->grh.flow_label)); 1295 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1296 } 1297 1298 err = ib_rate_to_mlx5(dev, ah->static_rate); 1299 if (err < 0) 1300 return err; 1301 path->static_rate = err; 1302 path->port = port; 1303 1304 if (ah->ah_flags & IB_AH_GRH) { 1305 if (ah->grh.sgid_index >= dev->mdev.caps.port[port - 1].gid_table_len) { 1306 pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n", 1307 ah->grh.sgid_index, dev->mdev.caps.port[port - 1].gid_table_len); 1308 return -EINVAL; 1309 } 1310 1311 path->grh_mlid |= 1 << 7; 1312 path->mgid_index = ah->grh.sgid_index; 1313 path->hop_limit = ah->grh.hop_limit; 1314 path->tclass_flowlabel = 1315 cpu_to_be32((ah->grh.traffic_class << 20) | 1316 (ah->grh.flow_label)); 1317 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1318 } 1319 1320 if (attr_mask & IB_QP_TIMEOUT) 1321 path->ackto_lt = attr->timeout << 3; 1322 1323 path->sl = ah->sl & 0xf; 1324 1325 return 0; 1326 } 1327 1328 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 1329 [MLX5_QP_STATE_INIT] = { 1330 [MLX5_QP_STATE_INIT] = { 1331 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1332 MLX5_QP_OPTPAR_RAE | 1333 MLX5_QP_OPTPAR_RWE | 1334 MLX5_QP_OPTPAR_PKEY_INDEX | 1335 MLX5_QP_OPTPAR_PRI_PORT, 1336 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1337 MLX5_QP_OPTPAR_PKEY_INDEX | 1338 MLX5_QP_OPTPAR_PRI_PORT, 1339 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1340 MLX5_QP_OPTPAR_Q_KEY | 1341 MLX5_QP_OPTPAR_PRI_PORT, 1342 }, 1343 [MLX5_QP_STATE_RTR] = { 1344 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1345 MLX5_QP_OPTPAR_RRE | 1346 MLX5_QP_OPTPAR_RAE | 1347 MLX5_QP_OPTPAR_RWE | 1348 MLX5_QP_OPTPAR_PKEY_INDEX, 1349 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1350 MLX5_QP_OPTPAR_RWE | 1351 MLX5_QP_OPTPAR_PKEY_INDEX, 1352 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1353 MLX5_QP_OPTPAR_Q_KEY, 1354 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 1355 MLX5_QP_OPTPAR_Q_KEY, 1356 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1357 MLX5_QP_OPTPAR_RRE | 1358 MLX5_QP_OPTPAR_RAE | 1359 MLX5_QP_OPTPAR_RWE | 1360 MLX5_QP_OPTPAR_PKEY_INDEX, 1361 }, 1362 }, 1363 [MLX5_QP_STATE_RTR] = { 1364 [MLX5_QP_STATE_RTS] = { 1365 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1366 MLX5_QP_OPTPAR_RRE | 1367 MLX5_QP_OPTPAR_RAE | 1368 MLX5_QP_OPTPAR_RWE | 1369 MLX5_QP_OPTPAR_PM_STATE | 1370 MLX5_QP_OPTPAR_RNR_TIMEOUT, 1371 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1372 MLX5_QP_OPTPAR_RWE | 1373 MLX5_QP_OPTPAR_PM_STATE, 1374 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1375 }, 1376 }, 1377 [MLX5_QP_STATE_RTS] = { 1378 [MLX5_QP_STATE_RTS] = { 1379 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1380 MLX5_QP_OPTPAR_RAE | 1381 MLX5_QP_OPTPAR_RWE | 1382 MLX5_QP_OPTPAR_RNR_TIMEOUT | 1383 MLX5_QP_OPTPAR_PM_STATE | 1384 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1385 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1386 MLX5_QP_OPTPAR_PM_STATE | 1387 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1388 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 1389 MLX5_QP_OPTPAR_SRQN | 1390 MLX5_QP_OPTPAR_CQN_RCV, 1391 }, 1392 }, 1393 [MLX5_QP_STATE_SQER] = { 1394 [MLX5_QP_STATE_RTS] = { 1395 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1396 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 1397 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 1398 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 1399 MLX5_QP_OPTPAR_RWE | 1400 MLX5_QP_OPTPAR_RAE | 1401 MLX5_QP_OPTPAR_RRE, 1402 }, 1403 }, 1404 }; 1405 1406 static int ib_nr_to_mlx5_nr(int ib_mask) 1407 { 1408 switch (ib_mask) { 1409 case IB_QP_STATE: 1410 return 0; 1411 case IB_QP_CUR_STATE: 1412 return 0; 1413 case IB_QP_EN_SQD_ASYNC_NOTIFY: 1414 return 0; 1415 case IB_QP_ACCESS_FLAGS: 1416 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 1417 MLX5_QP_OPTPAR_RAE; 1418 case IB_QP_PKEY_INDEX: 1419 return MLX5_QP_OPTPAR_PKEY_INDEX; 1420 case IB_QP_PORT: 1421 return MLX5_QP_OPTPAR_PRI_PORT; 1422 case IB_QP_QKEY: 1423 return MLX5_QP_OPTPAR_Q_KEY; 1424 case IB_QP_AV: 1425 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 1426 MLX5_QP_OPTPAR_PRI_PORT; 1427 case IB_QP_PATH_MTU: 1428 return 0; 1429 case IB_QP_TIMEOUT: 1430 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 1431 case IB_QP_RETRY_CNT: 1432 return MLX5_QP_OPTPAR_RETRY_COUNT; 1433 case IB_QP_RNR_RETRY: 1434 return MLX5_QP_OPTPAR_RNR_RETRY; 1435 case IB_QP_RQ_PSN: 1436 return 0; 1437 case IB_QP_MAX_QP_RD_ATOMIC: 1438 return MLX5_QP_OPTPAR_SRA_MAX; 1439 case IB_QP_ALT_PATH: 1440 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 1441 case IB_QP_MIN_RNR_TIMER: 1442 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 1443 case IB_QP_SQ_PSN: 1444 return 0; 1445 case IB_QP_MAX_DEST_RD_ATOMIC: 1446 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 1447 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 1448 case IB_QP_PATH_MIG_STATE: 1449 return MLX5_QP_OPTPAR_PM_STATE; 1450 case IB_QP_CAP: 1451 return 0; 1452 case IB_QP_DEST_QPN: 1453 return 0; 1454 } 1455 return 0; 1456 } 1457 1458 static int ib_mask_to_mlx5_opt(int ib_mask) 1459 { 1460 int result = 0; 1461 int i; 1462 1463 for (i = 0; i < 8 * sizeof(int); i++) { 1464 if ((1 << i) & ib_mask) 1465 result |= ib_nr_to_mlx5_nr(1 << i); 1466 } 1467 1468 return result; 1469 } 1470 1471 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 1472 const struct ib_qp_attr *attr, int attr_mask, 1473 enum ib_qp_state cur_state, enum ib_qp_state new_state) 1474 { 1475 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1476 struct mlx5_ib_qp *qp = to_mqp(ibqp); 1477 struct mlx5_ib_cq *send_cq, *recv_cq; 1478 struct mlx5_qp_context *context; 1479 struct mlx5_modify_qp_mbox_in *in; 1480 struct mlx5_ib_pd *pd; 1481 enum mlx5_qp_state mlx5_cur, mlx5_new; 1482 enum mlx5_qp_optpar optpar; 1483 int sqd_event; 1484 int mlx5_st; 1485 int err; 1486 1487 in = kzalloc(sizeof(*in), GFP_KERNEL); 1488 if (!in) 1489 return -ENOMEM; 1490 1491 context = &in->ctx; 1492 err = to_mlx5_st(ibqp->qp_type); 1493 if (err < 0) 1494 goto out; 1495 1496 context->flags = cpu_to_be32(err << 16); 1497 1498 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 1499 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 1500 } else { 1501 switch (attr->path_mig_state) { 1502 case IB_MIG_MIGRATED: 1503 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 1504 break; 1505 case IB_MIG_REARM: 1506 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 1507 break; 1508 case IB_MIG_ARMED: 1509 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 1510 break; 1511 } 1512 } 1513 1514 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) { 1515 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 1516 } else if (ibqp->qp_type == IB_QPT_UD || 1517 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 1518 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1519 } else if (attr_mask & IB_QP_PATH_MTU) { 1520 if (attr->path_mtu < IB_MTU_256 || 1521 attr->path_mtu > IB_MTU_4096) { 1522 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 1523 err = -EINVAL; 1524 goto out; 1525 } 1526 context->mtu_msgmax = (attr->path_mtu << 5) | dev->mdev.caps.log_max_msg; 1527 } 1528 1529 if (attr_mask & IB_QP_DEST_QPN) 1530 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 1531 1532 if (attr_mask & IB_QP_PKEY_INDEX) 1533 context->pri_path.pkey_index = attr->pkey_index; 1534 1535 /* todo implement counter_index functionality */ 1536 1537 if (is_sqp(ibqp->qp_type)) 1538 context->pri_path.port = qp->port; 1539 1540 if (attr_mask & IB_QP_PORT) 1541 context->pri_path.port = attr->port_num; 1542 1543 if (attr_mask & IB_QP_AV) { 1544 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path, 1545 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 1546 attr_mask, 0, attr); 1547 if (err) 1548 goto out; 1549 } 1550 1551 if (attr_mask & IB_QP_TIMEOUT) 1552 context->pri_path.ackto_lt |= attr->timeout << 3; 1553 1554 if (attr_mask & IB_QP_ALT_PATH) { 1555 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path, 1556 attr->alt_port_num, attr_mask, 0, attr); 1557 if (err) 1558 goto out; 1559 } 1560 1561 pd = get_pd(qp); 1562 get_cqs(qp, &send_cq, &recv_cq); 1563 1564 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 1565 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 1566 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 1567 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 1568 1569 if (attr_mask & IB_QP_RNR_RETRY) 1570 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1571 1572 if (attr_mask & IB_QP_RETRY_CNT) 1573 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1574 1575 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1576 if (attr->max_rd_atomic) 1577 context->params1 |= 1578 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1579 } 1580 1581 if (attr_mask & IB_QP_SQ_PSN) 1582 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1583 1584 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1585 if (attr->max_dest_rd_atomic) 1586 context->params2 |= 1587 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1588 } 1589 1590 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 1591 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 1592 1593 if (attr_mask & IB_QP_MIN_RNR_TIMER) 1594 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1595 1596 if (attr_mask & IB_QP_RQ_PSN) 1597 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1598 1599 if (attr_mask & IB_QP_QKEY) 1600 context->qkey = cpu_to_be32(attr->qkey); 1601 1602 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1603 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1604 1605 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 1606 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 1607 sqd_event = 1; 1608 else 1609 sqd_event = 0; 1610 1611 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1612 context->sq_crq_size |= cpu_to_be16(1 << 4); 1613 1614 1615 mlx5_cur = to_mlx5_state(cur_state); 1616 mlx5_new = to_mlx5_state(new_state); 1617 mlx5_st = to_mlx5_st(ibqp->qp_type); 1618 if (mlx5_st < 0) 1619 goto out; 1620 1621 optpar = ib_mask_to_mlx5_opt(attr_mask); 1622 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 1623 in->optparam = cpu_to_be32(optpar); 1624 err = mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(cur_state), 1625 to_mlx5_state(new_state), in, sqd_event, 1626 &qp->mqp); 1627 if (err) 1628 goto out; 1629 1630 qp->state = new_state; 1631 1632 if (attr_mask & IB_QP_ACCESS_FLAGS) 1633 qp->atomic_rd_en = attr->qp_access_flags; 1634 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1635 qp->resp_depth = attr->max_dest_rd_atomic; 1636 if (attr_mask & IB_QP_PORT) 1637 qp->port = attr->port_num; 1638 if (attr_mask & IB_QP_ALT_PATH) 1639 qp->alt_port = attr->alt_port_num; 1640 1641 /* 1642 * If we moved a kernel QP to RESET, clean up all old CQ 1643 * entries and reinitialize the QP. 1644 */ 1645 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 1646 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn, 1647 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 1648 if (send_cq != recv_cq) 1649 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1650 1651 qp->rq.head = 0; 1652 qp->rq.tail = 0; 1653 qp->sq.head = 0; 1654 qp->sq.tail = 0; 1655 qp->sq.cur_post = 0; 1656 qp->sq.last_poll = 0; 1657 qp->db.db[MLX5_RCV_DBR] = 0; 1658 qp->db.db[MLX5_SND_DBR] = 0; 1659 } 1660 1661 out: 1662 kfree(in); 1663 return err; 1664 } 1665 1666 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1667 int attr_mask, struct ib_udata *udata) 1668 { 1669 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1670 struct mlx5_ib_qp *qp = to_mqp(ibqp); 1671 enum ib_qp_state cur_state, new_state; 1672 int err = -EINVAL; 1673 int port; 1674 1675 mutex_lock(&qp->mutex); 1676 1677 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 1678 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1679 1680 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR && 1681 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask, 1682 IB_LINK_LAYER_UNSPECIFIED)) 1683 goto out; 1684 1685 if ((attr_mask & IB_QP_PORT) && 1686 (attr->port_num == 0 || attr->port_num > dev->mdev.caps.num_ports)) 1687 goto out; 1688 1689 if (attr_mask & IB_QP_PKEY_INDEX) { 1690 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1691 if (attr->pkey_index >= dev->mdev.caps.port[port - 1].pkey_table_len) 1692 goto out; 1693 } 1694 1695 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1696 attr->max_rd_atomic > dev->mdev.caps.max_ra_res_qp) 1697 goto out; 1698 1699 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1700 attr->max_dest_rd_atomic > dev->mdev.caps.max_ra_req_qp) 1701 goto out; 1702 1703 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 1704 err = 0; 1705 goto out; 1706 } 1707 1708 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 1709 1710 out: 1711 mutex_unlock(&qp->mutex); 1712 return err; 1713 } 1714 1715 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 1716 { 1717 struct mlx5_ib_cq *cq; 1718 unsigned cur; 1719 1720 cur = wq->head - wq->tail; 1721 if (likely(cur + nreq < wq->max_post)) 1722 return 0; 1723 1724 cq = to_mcq(ib_cq); 1725 spin_lock(&cq->lock); 1726 cur = wq->head - wq->tail; 1727 spin_unlock(&cq->lock); 1728 1729 return cur + nreq >= wq->max_post; 1730 } 1731 1732 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 1733 u64 remote_addr, u32 rkey) 1734 { 1735 rseg->raddr = cpu_to_be64(remote_addr); 1736 rseg->rkey = cpu_to_be32(rkey); 1737 rseg->reserved = 0; 1738 } 1739 1740 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 1741 struct ib_send_wr *wr) 1742 { 1743 memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av)); 1744 dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV); 1745 dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1746 } 1747 1748 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 1749 { 1750 dseg->byte_count = cpu_to_be32(sg->length); 1751 dseg->lkey = cpu_to_be32(sg->lkey); 1752 dseg->addr = cpu_to_be64(sg->addr); 1753 } 1754 1755 static __be16 get_klm_octo(int npages) 1756 { 1757 return cpu_to_be16(ALIGN(npages, 8) / 2); 1758 } 1759 1760 static __be64 frwr_mkey_mask(void) 1761 { 1762 u64 result; 1763 1764 result = MLX5_MKEY_MASK_LEN | 1765 MLX5_MKEY_MASK_PAGE_SIZE | 1766 MLX5_MKEY_MASK_START_ADDR | 1767 MLX5_MKEY_MASK_EN_RINVAL | 1768 MLX5_MKEY_MASK_KEY | 1769 MLX5_MKEY_MASK_LR | 1770 MLX5_MKEY_MASK_LW | 1771 MLX5_MKEY_MASK_RR | 1772 MLX5_MKEY_MASK_RW | 1773 MLX5_MKEY_MASK_A | 1774 MLX5_MKEY_MASK_SMALL_FENCE | 1775 MLX5_MKEY_MASK_FREE; 1776 1777 return cpu_to_be64(result); 1778 } 1779 1780 static __be64 sig_mkey_mask(void) 1781 { 1782 u64 result; 1783 1784 result = MLX5_MKEY_MASK_LEN | 1785 MLX5_MKEY_MASK_PAGE_SIZE | 1786 MLX5_MKEY_MASK_START_ADDR | 1787 MLX5_MKEY_MASK_EN_SIGERR | 1788 MLX5_MKEY_MASK_EN_RINVAL | 1789 MLX5_MKEY_MASK_KEY | 1790 MLX5_MKEY_MASK_LR | 1791 MLX5_MKEY_MASK_LW | 1792 MLX5_MKEY_MASK_RR | 1793 MLX5_MKEY_MASK_RW | 1794 MLX5_MKEY_MASK_SMALL_FENCE | 1795 MLX5_MKEY_MASK_FREE | 1796 MLX5_MKEY_MASK_BSF_EN; 1797 1798 return cpu_to_be64(result); 1799 } 1800 1801 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 1802 struct ib_send_wr *wr, int li) 1803 { 1804 memset(umr, 0, sizeof(*umr)); 1805 1806 if (li) { 1807 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 1808 umr->flags = 1 << 7; 1809 return; 1810 } 1811 1812 umr->flags = (1 << 5); /* fail if not free */ 1813 umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len); 1814 umr->mkey_mask = frwr_mkey_mask(); 1815 } 1816 1817 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 1818 struct ib_send_wr *wr) 1819 { 1820 struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg; 1821 u64 mask; 1822 1823 memset(umr, 0, sizeof(*umr)); 1824 1825 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 1826 umr->flags = 1 << 5; /* fail if not free */ 1827 umr->klm_octowords = get_klm_octo(umrwr->npages); 1828 mask = MLX5_MKEY_MASK_LEN | 1829 MLX5_MKEY_MASK_PAGE_SIZE | 1830 MLX5_MKEY_MASK_START_ADDR | 1831 MLX5_MKEY_MASK_PD | 1832 MLX5_MKEY_MASK_LR | 1833 MLX5_MKEY_MASK_LW | 1834 MLX5_MKEY_MASK_KEY | 1835 MLX5_MKEY_MASK_RR | 1836 MLX5_MKEY_MASK_RW | 1837 MLX5_MKEY_MASK_A | 1838 MLX5_MKEY_MASK_FREE; 1839 umr->mkey_mask = cpu_to_be64(mask); 1840 } else { 1841 umr->flags = 2 << 5; /* fail if free */ 1842 mask = MLX5_MKEY_MASK_FREE; 1843 umr->mkey_mask = cpu_to_be64(mask); 1844 } 1845 1846 if (!wr->num_sge) 1847 umr->flags |= (1 << 7); /* inline */ 1848 } 1849 1850 static u8 get_umr_flags(int acc) 1851 { 1852 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1853 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1854 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1855 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1856 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 1857 } 1858 1859 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr, 1860 int li, int *writ) 1861 { 1862 memset(seg, 0, sizeof(*seg)); 1863 if (li) { 1864 seg->status = 1 << 6; 1865 return; 1866 } 1867 1868 seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags) | 1869 MLX5_ACCESS_MODE_MTT; 1870 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE); 1871 seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00); 1872 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 1873 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start); 1874 seg->len = cpu_to_be64(wr->wr.fast_reg.length); 1875 seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2); 1876 seg->log2_page_size = wr->wr.fast_reg.page_shift; 1877 } 1878 1879 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 1880 { 1881 memset(seg, 0, sizeof(*seg)); 1882 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 1883 seg->status = 1 << 6; 1884 return; 1885 } 1886 1887 seg->flags = convert_access(wr->wr.fast_reg.access_flags); 1888 seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn); 1889 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start); 1890 seg->len = cpu_to_be64(wr->wr.fast_reg.length); 1891 seg->log2_page_size = wr->wr.fast_reg.page_shift; 1892 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 1893 mlx5_mkey_variant(wr->wr.fast_reg.rkey)); 1894 } 1895 1896 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg, 1897 struct ib_send_wr *wr, 1898 struct mlx5_core_dev *mdev, 1899 struct mlx5_ib_pd *pd, 1900 int writ) 1901 { 1902 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list); 1903 u64 *page_list = wr->wr.fast_reg.page_list->page_list; 1904 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0); 1905 int i; 1906 1907 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) 1908 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm); 1909 dseg->addr = cpu_to_be64(mfrpl->map); 1910 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64)); 1911 dseg->lkey = cpu_to_be32(pd->pa_lkey); 1912 } 1913 1914 static __be32 send_ieth(struct ib_send_wr *wr) 1915 { 1916 switch (wr->opcode) { 1917 case IB_WR_SEND_WITH_IMM: 1918 case IB_WR_RDMA_WRITE_WITH_IMM: 1919 return wr->ex.imm_data; 1920 1921 case IB_WR_SEND_WITH_INV: 1922 return cpu_to_be32(wr->ex.invalidate_rkey); 1923 1924 default: 1925 return 0; 1926 } 1927 } 1928 1929 static u8 calc_sig(void *wqe, int size) 1930 { 1931 u8 *p = wqe; 1932 u8 res = 0; 1933 int i; 1934 1935 for (i = 0; i < size; i++) 1936 res ^= p[i]; 1937 1938 return ~res; 1939 } 1940 1941 static u8 wq_sig(void *wqe) 1942 { 1943 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 1944 } 1945 1946 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 1947 void *wqe, int *sz) 1948 { 1949 struct mlx5_wqe_inline_seg *seg; 1950 void *qend = qp->sq.qend; 1951 void *addr; 1952 int inl = 0; 1953 int copy; 1954 int len; 1955 int i; 1956 1957 seg = wqe; 1958 wqe += sizeof(*seg); 1959 for (i = 0; i < wr->num_sge; i++) { 1960 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 1961 len = wr->sg_list[i].length; 1962 inl += len; 1963 1964 if (unlikely(inl > qp->max_inline_data)) 1965 return -ENOMEM; 1966 1967 if (unlikely(wqe + len > qend)) { 1968 copy = qend - wqe; 1969 memcpy(wqe, addr, copy); 1970 addr += copy; 1971 len -= copy; 1972 wqe = mlx5_get_send_wqe(qp, 0); 1973 } 1974 memcpy(wqe, addr, len); 1975 wqe += len; 1976 } 1977 1978 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 1979 1980 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 1981 1982 return 0; 1983 } 1984 1985 static u16 prot_field_size(enum ib_signature_type type) 1986 { 1987 switch (type) { 1988 case IB_SIG_TYPE_T10_DIF: 1989 return MLX5_DIF_SIZE; 1990 default: 1991 return 0; 1992 } 1993 } 1994 1995 static u8 bs_selector(int block_size) 1996 { 1997 switch (block_size) { 1998 case 512: return 0x1; 1999 case 520: return 0x2; 2000 case 4096: return 0x3; 2001 case 4160: return 0x4; 2002 case 1073741824: return 0x5; 2003 default: return 0; 2004 } 2005 } 2006 2007 static int format_selector(struct ib_sig_attrs *attr, 2008 struct ib_sig_domain *domain, 2009 int *selector) 2010 { 2011 2012 #define FORMAT_DIF_NONE 0 2013 #define FORMAT_DIF_CRC_INC 8 2014 #define FORMAT_DIF_CRC_NO_INC 12 2015 #define FORMAT_DIF_CSUM_INC 13 2016 #define FORMAT_DIF_CSUM_NO_INC 14 2017 2018 switch (domain->sig.dif.type) { 2019 case IB_T10DIF_NONE: 2020 /* No DIF */ 2021 *selector = FORMAT_DIF_NONE; 2022 break; 2023 case IB_T10DIF_TYPE1: /* Fall through */ 2024 case IB_T10DIF_TYPE2: 2025 switch (domain->sig.dif.bg_type) { 2026 case IB_T10DIF_CRC: 2027 *selector = FORMAT_DIF_CRC_INC; 2028 break; 2029 case IB_T10DIF_CSUM: 2030 *selector = FORMAT_DIF_CSUM_INC; 2031 break; 2032 default: 2033 return 1; 2034 } 2035 break; 2036 case IB_T10DIF_TYPE3: 2037 switch (domain->sig.dif.bg_type) { 2038 case IB_T10DIF_CRC: 2039 *selector = domain->sig.dif.type3_inc_reftag ? 2040 FORMAT_DIF_CRC_INC : 2041 FORMAT_DIF_CRC_NO_INC; 2042 break; 2043 case IB_T10DIF_CSUM: 2044 *selector = domain->sig.dif.type3_inc_reftag ? 2045 FORMAT_DIF_CSUM_INC : 2046 FORMAT_DIF_CSUM_NO_INC; 2047 break; 2048 default: 2049 return 1; 2050 } 2051 break; 2052 default: 2053 return 1; 2054 } 2055 2056 return 0; 2057 } 2058 2059 static int mlx5_set_bsf(struct ib_mr *sig_mr, 2060 struct ib_sig_attrs *sig_attrs, 2061 struct mlx5_bsf *bsf, u32 data_size) 2062 { 2063 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 2064 struct mlx5_bsf_basic *basic = &bsf->basic; 2065 struct ib_sig_domain *mem = &sig_attrs->mem; 2066 struct ib_sig_domain *wire = &sig_attrs->wire; 2067 int ret, selector; 2068 2069 switch (sig_attrs->mem.sig_type) { 2070 case IB_SIG_TYPE_T10_DIF: 2071 if (sig_attrs->wire.sig_type != IB_SIG_TYPE_T10_DIF) 2072 return -EINVAL; 2073 2074 /* Input domain check byte mask */ 2075 basic->check_byte_mask = sig_attrs->check_mask; 2076 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 2077 mem->sig.dif.type == wire->sig.dif.type) { 2078 /* Same block structure */ 2079 basic->bsf_size_sbs = 1 << 4; 2080 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 2081 basic->wire.copy_byte_mask = 0xff; 2082 else 2083 basic->wire.copy_byte_mask = 0x3f; 2084 } else 2085 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 2086 2087 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 2088 basic->raw_data_size = cpu_to_be32(data_size); 2089 2090 ret = format_selector(sig_attrs, mem, &selector); 2091 if (ret) 2092 return -EINVAL; 2093 basic->m_bfs_psv = cpu_to_be32(selector << 24 | 2094 msig->psv_memory.psv_idx); 2095 2096 ret = format_selector(sig_attrs, wire, &selector); 2097 if (ret) 2098 return -EINVAL; 2099 basic->w_bfs_psv = cpu_to_be32(selector << 24 | 2100 msig->psv_wire.psv_idx); 2101 break; 2102 2103 default: 2104 return -EINVAL; 2105 } 2106 2107 return 0; 2108 } 2109 2110 static int set_sig_data_segment(struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 2111 void **seg, int *size) 2112 { 2113 struct ib_sig_attrs *sig_attrs = wr->wr.sig_handover.sig_attrs; 2114 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr; 2115 struct mlx5_bsf *bsf; 2116 u32 data_len = wr->sg_list->length; 2117 u32 data_key = wr->sg_list->lkey; 2118 u64 data_va = wr->sg_list->addr; 2119 int ret; 2120 int wqe_size; 2121 2122 if (!wr->wr.sig_handover.prot) { 2123 /** 2124 * Source domain doesn't contain signature information 2125 * So need construct: 2126 * ------------------ 2127 * | data_klm | 2128 * ------------------ 2129 * | BSF | 2130 * ------------------ 2131 **/ 2132 struct mlx5_klm *data_klm = *seg; 2133 2134 data_klm->bcount = cpu_to_be32(data_len); 2135 data_klm->key = cpu_to_be32(data_key); 2136 data_klm->va = cpu_to_be64(data_va); 2137 wqe_size = ALIGN(sizeof(*data_klm), 64); 2138 } else { 2139 /** 2140 * Source domain contains signature information 2141 * So need construct a strided block format: 2142 * --------------------------- 2143 * | stride_block_ctrl | 2144 * --------------------------- 2145 * | data_klm | 2146 * --------------------------- 2147 * | prot_klm | 2148 * --------------------------- 2149 * | BSF | 2150 * --------------------------- 2151 **/ 2152 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 2153 struct mlx5_stride_block_entry *data_sentry; 2154 struct mlx5_stride_block_entry *prot_sentry; 2155 u32 prot_key = wr->wr.sig_handover.prot->lkey; 2156 u64 prot_va = wr->wr.sig_handover.prot->addr; 2157 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 2158 int prot_size; 2159 2160 sblock_ctrl = *seg; 2161 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 2162 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 2163 2164 prot_size = prot_field_size(sig_attrs->mem.sig_type); 2165 if (!prot_size) { 2166 pr_err("Bad block size given: %u\n", block_size); 2167 return -EINVAL; 2168 } 2169 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 2170 prot_size); 2171 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 2172 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 2173 sblock_ctrl->num_entries = cpu_to_be16(2); 2174 2175 data_sentry->bcount = cpu_to_be16(block_size); 2176 data_sentry->key = cpu_to_be32(data_key); 2177 data_sentry->va = cpu_to_be64(data_va); 2178 prot_sentry->bcount = cpu_to_be16(prot_size); 2179 prot_sentry->key = cpu_to_be32(prot_key); 2180 2181 if (prot_key == data_key && prot_va == data_va) { 2182 /** 2183 * The data and protection are interleaved 2184 * in a single memory region 2185 **/ 2186 prot_sentry->va = cpu_to_be64(data_va + block_size); 2187 prot_sentry->stride = cpu_to_be16(block_size + prot_size); 2188 data_sentry->stride = prot_sentry->stride; 2189 } else { 2190 /* The data and protection are two different buffers */ 2191 prot_sentry->va = cpu_to_be64(prot_va); 2192 data_sentry->stride = cpu_to_be16(block_size); 2193 prot_sentry->stride = cpu_to_be16(prot_size); 2194 } 2195 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 2196 sizeof(*prot_sentry), 64); 2197 } 2198 2199 *seg += wqe_size; 2200 *size += wqe_size / 16; 2201 if (unlikely((*seg == qp->sq.qend))) 2202 *seg = mlx5_get_send_wqe(qp, 0); 2203 2204 bsf = *seg; 2205 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 2206 if (ret) 2207 return -EINVAL; 2208 2209 *seg += sizeof(*bsf); 2210 *size += sizeof(*bsf) / 16; 2211 if (unlikely((*seg == qp->sq.qend))) 2212 *seg = mlx5_get_send_wqe(qp, 0); 2213 2214 return 0; 2215 } 2216 2217 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 2218 struct ib_send_wr *wr, u32 nelements, 2219 u32 length, u32 pdn) 2220 { 2221 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr; 2222 u32 sig_key = sig_mr->rkey; 2223 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 2224 2225 memset(seg, 0, sizeof(*seg)); 2226 2227 seg->flags = get_umr_flags(wr->wr.sig_handover.access_flags) | 2228 MLX5_ACCESS_MODE_KLM; 2229 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 2230 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 2231 MLX5_MKEY_BSF_EN | pdn); 2232 seg->len = cpu_to_be64(length); 2233 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 2234 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 2235 } 2236 2237 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 2238 struct ib_send_wr *wr, u32 nelements) 2239 { 2240 memset(umr, 0, sizeof(*umr)); 2241 2242 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 2243 umr->klm_octowords = get_klm_octo(nelements); 2244 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 2245 umr->mkey_mask = sig_mkey_mask(); 2246 } 2247 2248 2249 static int set_sig_umr_wr(struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 2250 void **seg, int *size) 2251 { 2252 struct mlx5_ib_mr *sig_mr = to_mmr(wr->wr.sig_handover.sig_mr); 2253 u32 pdn = get_pd(qp)->pdn; 2254 u32 klm_oct_size; 2255 int region_len, ret; 2256 2257 if (unlikely(wr->num_sge != 1) || 2258 unlikely(wr->wr.sig_handover.access_flags & 2259 IB_ACCESS_REMOTE_ATOMIC) || 2260 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 2261 unlikely(!sig_mr->sig->sig_status_checked)) 2262 return -EINVAL; 2263 2264 /* length of the protected region, data + protection */ 2265 region_len = wr->sg_list->length; 2266 if (wr->wr.sig_handover.prot) 2267 region_len += wr->wr.sig_handover.prot->length; 2268 2269 /** 2270 * KLM octoword size - if protection was provided 2271 * then we use strided block format (3 octowords), 2272 * else we use single KLM (1 octoword) 2273 **/ 2274 klm_oct_size = wr->wr.sig_handover.prot ? 3 : 1; 2275 2276 set_sig_umr_segment(*seg, wr, klm_oct_size); 2277 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2278 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2279 if (unlikely((*seg == qp->sq.qend))) 2280 *seg = mlx5_get_send_wqe(qp, 0); 2281 2282 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 2283 *seg += sizeof(struct mlx5_mkey_seg); 2284 *size += sizeof(struct mlx5_mkey_seg) / 16; 2285 if (unlikely((*seg == qp->sq.qend))) 2286 *seg = mlx5_get_send_wqe(qp, 0); 2287 2288 ret = set_sig_data_segment(wr, qp, seg, size); 2289 if (ret) 2290 return ret; 2291 2292 sig_mr->sig->sig_status_checked = false; 2293 return 0; 2294 } 2295 2296 static int set_psv_wr(struct ib_sig_domain *domain, 2297 u32 psv_idx, void **seg, int *size) 2298 { 2299 struct mlx5_seg_set_psv *psv_seg = *seg; 2300 2301 memset(psv_seg, 0, sizeof(*psv_seg)); 2302 psv_seg->psv_num = cpu_to_be32(psv_idx); 2303 switch (domain->sig_type) { 2304 case IB_SIG_TYPE_T10_DIF: 2305 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 2306 domain->sig.dif.app_tag); 2307 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 2308 2309 *seg += sizeof(*psv_seg); 2310 *size += sizeof(*psv_seg) / 16; 2311 break; 2312 2313 default: 2314 pr_err("Bad signature type given.\n"); 2315 return 1; 2316 } 2317 2318 return 0; 2319 } 2320 2321 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size, 2322 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp) 2323 { 2324 int writ = 0; 2325 int li; 2326 2327 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0; 2328 if (unlikely(wr->send_flags & IB_SEND_INLINE)) 2329 return -EINVAL; 2330 2331 set_frwr_umr_segment(*seg, wr, li); 2332 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2333 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2334 if (unlikely((*seg == qp->sq.qend))) 2335 *seg = mlx5_get_send_wqe(qp, 0); 2336 set_mkey_segment(*seg, wr, li, &writ); 2337 *seg += sizeof(struct mlx5_mkey_seg); 2338 *size += sizeof(struct mlx5_mkey_seg) / 16; 2339 if (unlikely((*seg == qp->sq.qend))) 2340 *seg = mlx5_get_send_wqe(qp, 0); 2341 if (!li) { 2342 if (unlikely(wr->wr.fast_reg.page_list_len > 2343 wr->wr.fast_reg.page_list->max_page_list_len)) 2344 return -ENOMEM; 2345 2346 set_frwr_pages(*seg, wr, mdev, pd, writ); 2347 *seg += sizeof(struct mlx5_wqe_data_seg); 2348 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 2349 } 2350 return 0; 2351 } 2352 2353 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 2354 { 2355 __be32 *p = NULL; 2356 int tidx = idx; 2357 int i, j; 2358 2359 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 2360 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 2361 if ((i & 0xf) == 0) { 2362 void *buf = mlx5_get_send_wqe(qp, tidx); 2363 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 2364 p = buf; 2365 j = 0; 2366 } 2367 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 2368 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 2369 be32_to_cpu(p[j + 3])); 2370 } 2371 } 2372 2373 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 2374 unsigned bytecnt, struct mlx5_ib_qp *qp) 2375 { 2376 while (bytecnt > 0) { 2377 __iowrite64_copy(dst++, src++, 8); 2378 __iowrite64_copy(dst++, src++, 8); 2379 __iowrite64_copy(dst++, src++, 8); 2380 __iowrite64_copy(dst++, src++, 8); 2381 __iowrite64_copy(dst++, src++, 8); 2382 __iowrite64_copy(dst++, src++, 8); 2383 __iowrite64_copy(dst++, src++, 8); 2384 __iowrite64_copy(dst++, src++, 8); 2385 bytecnt -= 64; 2386 if (unlikely(src == qp->sq.qend)) 2387 src = mlx5_get_send_wqe(qp, 0); 2388 } 2389 } 2390 2391 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 2392 { 2393 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 2394 wr->send_flags & IB_SEND_FENCE)) 2395 return MLX5_FENCE_MODE_STRONG_ORDERING; 2396 2397 if (unlikely(fence)) { 2398 if (wr->send_flags & IB_SEND_FENCE) 2399 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 2400 else 2401 return fence; 2402 2403 } else { 2404 return 0; 2405 } 2406 } 2407 2408 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 2409 struct mlx5_wqe_ctrl_seg **ctrl, 2410 struct ib_send_wr *wr, int *idx, 2411 int *size, int nreq) 2412 { 2413 int err = 0; 2414 2415 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) { 2416 err = -ENOMEM; 2417 return err; 2418 } 2419 2420 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 2421 *seg = mlx5_get_send_wqe(qp, *idx); 2422 *ctrl = *seg; 2423 *(uint32_t *)(*seg + 8) = 0; 2424 (*ctrl)->imm = send_ieth(wr); 2425 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 2426 (wr->send_flags & IB_SEND_SIGNALED ? 2427 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 2428 (wr->send_flags & IB_SEND_SOLICITED ? 2429 MLX5_WQE_CTRL_SOLICITED : 0); 2430 2431 *seg += sizeof(**ctrl); 2432 *size = sizeof(**ctrl) / 16; 2433 2434 return err; 2435 } 2436 2437 static void finish_wqe(struct mlx5_ib_qp *qp, 2438 struct mlx5_wqe_ctrl_seg *ctrl, 2439 u8 size, unsigned idx, u64 wr_id, 2440 int nreq, u8 fence, u8 next_fence, 2441 u32 mlx5_opcode) 2442 { 2443 u8 opmod = 0; 2444 2445 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 2446 mlx5_opcode | ((u32)opmod << 24)); 2447 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8)); 2448 ctrl->fm_ce_se |= fence; 2449 qp->fm_cache = next_fence; 2450 if (unlikely(qp->wq_sig)) 2451 ctrl->signature = wq_sig(ctrl); 2452 2453 qp->sq.wrid[idx] = wr_id; 2454 qp->sq.w_list[idx].opcode = mlx5_opcode; 2455 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 2456 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 2457 qp->sq.w_list[idx].next = qp->sq.cur_post; 2458 } 2459 2460 2461 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 2462 struct ib_send_wr **bad_wr) 2463 { 2464 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 2465 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2466 struct mlx5_core_dev *mdev = &dev->mdev; 2467 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2468 struct mlx5_ib_mr *mr; 2469 struct mlx5_wqe_data_seg *dpseg; 2470 struct mlx5_wqe_xrc_seg *xrc; 2471 struct mlx5_bf *bf = qp->bf; 2472 int uninitialized_var(size); 2473 void *qend = qp->sq.qend; 2474 unsigned long flags; 2475 unsigned idx; 2476 int err = 0; 2477 int inl = 0; 2478 int num_sge; 2479 void *seg; 2480 int nreq; 2481 int i; 2482 u8 next_fence = 0; 2483 u8 fence; 2484 2485 spin_lock_irqsave(&qp->sq.lock, flags); 2486 2487 for (nreq = 0; wr; nreq++, wr = wr->next) { 2488 if (unlikely(wr->opcode >= sizeof(mlx5_ib_opcode) / sizeof(mlx5_ib_opcode[0]))) { 2489 mlx5_ib_warn(dev, "\n"); 2490 err = -EINVAL; 2491 *bad_wr = wr; 2492 goto out; 2493 } 2494 2495 fence = qp->fm_cache; 2496 num_sge = wr->num_sge; 2497 if (unlikely(num_sge > qp->sq.max_gs)) { 2498 mlx5_ib_warn(dev, "\n"); 2499 err = -ENOMEM; 2500 *bad_wr = wr; 2501 goto out; 2502 } 2503 2504 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 2505 if (err) { 2506 mlx5_ib_warn(dev, "\n"); 2507 err = -ENOMEM; 2508 *bad_wr = wr; 2509 goto out; 2510 } 2511 2512 switch (ibqp->qp_type) { 2513 case IB_QPT_XRC_INI: 2514 xrc = seg; 2515 xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num); 2516 seg += sizeof(*xrc); 2517 size += sizeof(*xrc) / 16; 2518 /* fall through */ 2519 case IB_QPT_RC: 2520 switch (wr->opcode) { 2521 case IB_WR_RDMA_READ: 2522 case IB_WR_RDMA_WRITE: 2523 case IB_WR_RDMA_WRITE_WITH_IMM: 2524 set_raddr_seg(seg, wr->wr.rdma.remote_addr, 2525 wr->wr.rdma.rkey); 2526 seg += sizeof(struct mlx5_wqe_raddr_seg); 2527 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 2528 break; 2529 2530 case IB_WR_ATOMIC_CMP_AND_SWP: 2531 case IB_WR_ATOMIC_FETCH_AND_ADD: 2532 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 2533 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 2534 err = -ENOSYS; 2535 *bad_wr = wr; 2536 goto out; 2537 2538 case IB_WR_LOCAL_INV: 2539 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2540 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 2541 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 2542 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp); 2543 if (err) { 2544 mlx5_ib_warn(dev, "\n"); 2545 *bad_wr = wr; 2546 goto out; 2547 } 2548 num_sge = 0; 2549 break; 2550 2551 case IB_WR_FAST_REG_MR: 2552 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2553 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR; 2554 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey); 2555 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp); 2556 if (err) { 2557 mlx5_ib_warn(dev, "\n"); 2558 *bad_wr = wr; 2559 goto out; 2560 } 2561 num_sge = 0; 2562 break; 2563 2564 case IB_WR_REG_SIG_MR: 2565 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 2566 mr = to_mmr(wr->wr.sig_handover.sig_mr); 2567 2568 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 2569 err = set_sig_umr_wr(wr, qp, &seg, &size); 2570 if (err) { 2571 mlx5_ib_warn(dev, "\n"); 2572 *bad_wr = wr; 2573 goto out; 2574 } 2575 2576 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2577 nreq, get_fence(fence, wr), 2578 next_fence, MLX5_OPCODE_UMR); 2579 /* 2580 * SET_PSV WQEs are not signaled and solicited 2581 * on error 2582 */ 2583 wr->send_flags &= ~IB_SEND_SIGNALED; 2584 wr->send_flags |= IB_SEND_SOLICITED; 2585 err = begin_wqe(qp, &seg, &ctrl, wr, 2586 &idx, &size, nreq); 2587 if (err) { 2588 mlx5_ib_warn(dev, "\n"); 2589 err = -ENOMEM; 2590 *bad_wr = wr; 2591 goto out; 2592 } 2593 2594 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->mem, 2595 mr->sig->psv_memory.psv_idx, &seg, 2596 &size); 2597 if (err) { 2598 mlx5_ib_warn(dev, "\n"); 2599 *bad_wr = wr; 2600 goto out; 2601 } 2602 2603 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2604 nreq, get_fence(fence, wr), 2605 next_fence, MLX5_OPCODE_SET_PSV); 2606 err = begin_wqe(qp, &seg, &ctrl, wr, 2607 &idx, &size, nreq); 2608 if (err) { 2609 mlx5_ib_warn(dev, "\n"); 2610 err = -ENOMEM; 2611 *bad_wr = wr; 2612 goto out; 2613 } 2614 2615 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2616 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->wire, 2617 mr->sig->psv_wire.psv_idx, &seg, 2618 &size); 2619 if (err) { 2620 mlx5_ib_warn(dev, "\n"); 2621 *bad_wr = wr; 2622 goto out; 2623 } 2624 2625 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2626 nreq, get_fence(fence, wr), 2627 next_fence, MLX5_OPCODE_SET_PSV); 2628 num_sge = 0; 2629 goto skip_psv; 2630 2631 default: 2632 break; 2633 } 2634 break; 2635 2636 case IB_QPT_UC: 2637 switch (wr->opcode) { 2638 case IB_WR_RDMA_WRITE: 2639 case IB_WR_RDMA_WRITE_WITH_IMM: 2640 set_raddr_seg(seg, wr->wr.rdma.remote_addr, 2641 wr->wr.rdma.rkey); 2642 seg += sizeof(struct mlx5_wqe_raddr_seg); 2643 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 2644 break; 2645 2646 default: 2647 break; 2648 } 2649 break; 2650 2651 case IB_QPT_UD: 2652 case IB_QPT_SMI: 2653 case IB_QPT_GSI: 2654 set_datagram_seg(seg, wr); 2655 seg += sizeof(struct mlx5_wqe_datagram_seg); 2656 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 2657 if (unlikely((seg == qend))) 2658 seg = mlx5_get_send_wqe(qp, 0); 2659 break; 2660 2661 case MLX5_IB_QPT_REG_UMR: 2662 if (wr->opcode != MLX5_IB_WR_UMR) { 2663 err = -EINVAL; 2664 mlx5_ib_warn(dev, "bad opcode\n"); 2665 goto out; 2666 } 2667 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 2668 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey); 2669 set_reg_umr_segment(seg, wr); 2670 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2671 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2672 if (unlikely((seg == qend))) 2673 seg = mlx5_get_send_wqe(qp, 0); 2674 set_reg_mkey_segment(seg, wr); 2675 seg += sizeof(struct mlx5_mkey_seg); 2676 size += sizeof(struct mlx5_mkey_seg) / 16; 2677 if (unlikely((seg == qend))) 2678 seg = mlx5_get_send_wqe(qp, 0); 2679 break; 2680 2681 default: 2682 break; 2683 } 2684 2685 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 2686 int uninitialized_var(sz); 2687 2688 err = set_data_inl_seg(qp, wr, seg, &sz); 2689 if (unlikely(err)) { 2690 mlx5_ib_warn(dev, "\n"); 2691 *bad_wr = wr; 2692 goto out; 2693 } 2694 inl = 1; 2695 size += sz; 2696 } else { 2697 dpseg = seg; 2698 for (i = 0; i < num_sge; i++) { 2699 if (unlikely(dpseg == qend)) { 2700 seg = mlx5_get_send_wqe(qp, 0); 2701 dpseg = seg; 2702 } 2703 if (likely(wr->sg_list[i].length)) { 2704 set_data_ptr_seg(dpseg, wr->sg_list + i); 2705 size += sizeof(struct mlx5_wqe_data_seg) / 16; 2706 dpseg++; 2707 } 2708 } 2709 } 2710 2711 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 2712 get_fence(fence, wr), next_fence, 2713 mlx5_ib_opcode[wr->opcode]); 2714 skip_psv: 2715 if (0) 2716 dump_wqe(qp, idx, size); 2717 } 2718 2719 out: 2720 if (likely(nreq)) { 2721 qp->sq.head += nreq; 2722 2723 /* Make sure that descriptors are written before 2724 * updating doorbell record and ringing the doorbell 2725 */ 2726 wmb(); 2727 2728 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 2729 2730 /* Make sure doorbell record is visible to the HCA before 2731 * we hit doorbell */ 2732 wmb(); 2733 2734 if (bf->need_lock) 2735 spin_lock(&bf->lock); 2736 2737 /* TBD enable WC */ 2738 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 2739 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 2740 /* wc_wmb(); */ 2741 } else { 2742 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 2743 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 2744 /* Make sure doorbells don't leak out of SQ spinlock 2745 * and reach the HCA out of order. 2746 */ 2747 mmiowb(); 2748 } 2749 bf->offset ^= bf->buf_size; 2750 if (bf->need_lock) 2751 spin_unlock(&bf->lock); 2752 } 2753 2754 spin_unlock_irqrestore(&qp->sq.lock, flags); 2755 2756 return err; 2757 } 2758 2759 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 2760 { 2761 sig->signature = calc_sig(sig, size); 2762 } 2763 2764 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 2765 struct ib_recv_wr **bad_wr) 2766 { 2767 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2768 struct mlx5_wqe_data_seg *scat; 2769 struct mlx5_rwqe_sig *sig; 2770 unsigned long flags; 2771 int err = 0; 2772 int nreq; 2773 int ind; 2774 int i; 2775 2776 spin_lock_irqsave(&qp->rq.lock, flags); 2777 2778 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 2779 2780 for (nreq = 0; wr; nreq++, wr = wr->next) { 2781 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 2782 err = -ENOMEM; 2783 *bad_wr = wr; 2784 goto out; 2785 } 2786 2787 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 2788 err = -EINVAL; 2789 *bad_wr = wr; 2790 goto out; 2791 } 2792 2793 scat = get_recv_wqe(qp, ind); 2794 if (qp->wq_sig) 2795 scat++; 2796 2797 for (i = 0; i < wr->num_sge; i++) 2798 set_data_ptr_seg(scat + i, wr->sg_list + i); 2799 2800 if (i < qp->rq.max_gs) { 2801 scat[i].byte_count = 0; 2802 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 2803 scat[i].addr = 0; 2804 } 2805 2806 if (qp->wq_sig) { 2807 sig = (struct mlx5_rwqe_sig *)scat; 2808 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 2809 } 2810 2811 qp->rq.wrid[ind] = wr->wr_id; 2812 2813 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 2814 } 2815 2816 out: 2817 if (likely(nreq)) { 2818 qp->rq.head += nreq; 2819 2820 /* Make sure that descriptors are written before 2821 * doorbell record. 2822 */ 2823 wmb(); 2824 2825 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 2826 } 2827 2828 spin_unlock_irqrestore(&qp->rq.lock, flags); 2829 2830 return err; 2831 } 2832 2833 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 2834 { 2835 switch (mlx5_state) { 2836 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 2837 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 2838 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 2839 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 2840 case MLX5_QP_STATE_SQ_DRAINING: 2841 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 2842 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 2843 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 2844 default: return -1; 2845 } 2846 } 2847 2848 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 2849 { 2850 switch (mlx5_mig_state) { 2851 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 2852 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 2853 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 2854 default: return -1; 2855 } 2856 } 2857 2858 static int to_ib_qp_access_flags(int mlx5_flags) 2859 { 2860 int ib_flags = 0; 2861 2862 if (mlx5_flags & MLX5_QP_BIT_RRE) 2863 ib_flags |= IB_ACCESS_REMOTE_READ; 2864 if (mlx5_flags & MLX5_QP_BIT_RWE) 2865 ib_flags |= IB_ACCESS_REMOTE_WRITE; 2866 if (mlx5_flags & MLX5_QP_BIT_RAE) 2867 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 2868 2869 return ib_flags; 2870 } 2871 2872 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 2873 struct mlx5_qp_path *path) 2874 { 2875 struct mlx5_core_dev *dev = &ibdev->mdev; 2876 2877 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 2878 ib_ah_attr->port_num = path->port; 2879 2880 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports) 2881 return; 2882 2883 ib_ah_attr->sl = path->sl & 0xf; 2884 2885 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 2886 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 2887 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 2888 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 2889 if (ib_ah_attr->ah_flags) { 2890 ib_ah_attr->grh.sgid_index = path->mgid_index; 2891 ib_ah_attr->grh.hop_limit = path->hop_limit; 2892 ib_ah_attr->grh.traffic_class = 2893 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 2894 ib_ah_attr->grh.flow_label = 2895 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 2896 memcpy(ib_ah_attr->grh.dgid.raw, 2897 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 2898 } 2899 } 2900 2901 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 2902 struct ib_qp_init_attr *qp_init_attr) 2903 { 2904 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2905 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2906 struct mlx5_query_qp_mbox_out *outb; 2907 struct mlx5_qp_context *context; 2908 int mlx5_state; 2909 int err = 0; 2910 2911 mutex_lock(&qp->mutex); 2912 outb = kzalloc(sizeof(*outb), GFP_KERNEL); 2913 if (!outb) { 2914 err = -ENOMEM; 2915 goto out; 2916 } 2917 context = &outb->ctx; 2918 err = mlx5_core_qp_query(&dev->mdev, &qp->mqp, outb, sizeof(*outb)); 2919 if (err) 2920 goto out_free; 2921 2922 mlx5_state = be32_to_cpu(context->flags) >> 28; 2923 2924 qp->state = to_ib_qp_state(mlx5_state); 2925 qp_attr->qp_state = qp->state; 2926 qp_attr->path_mtu = context->mtu_msgmax >> 5; 2927 qp_attr->path_mig_state = 2928 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 2929 qp_attr->qkey = be32_to_cpu(context->qkey); 2930 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 2931 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 2932 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 2933 qp_attr->qp_access_flags = 2934 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 2935 2936 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 2937 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 2938 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 2939 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f; 2940 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 2941 } 2942 2943 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f; 2944 qp_attr->port_num = context->pri_path.port; 2945 2946 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 2947 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 2948 2949 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 2950 2951 qp_attr->max_dest_rd_atomic = 2952 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 2953 qp_attr->min_rnr_timer = 2954 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 2955 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 2956 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 2957 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 2958 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 2959 qp_attr->cur_qp_state = qp_attr->qp_state; 2960 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 2961 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 2962 2963 if (!ibqp->uobject) { 2964 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 2965 qp_attr->cap.max_send_sge = qp->sq.max_gs; 2966 } else { 2967 qp_attr->cap.max_send_wr = 0; 2968 qp_attr->cap.max_send_sge = 0; 2969 } 2970 2971 /* We don't support inline sends for kernel QPs (yet), and we 2972 * don't know what userspace's value should be. 2973 */ 2974 qp_attr->cap.max_inline_data = 0; 2975 2976 qp_init_attr->cap = qp_attr->cap; 2977 2978 qp_init_attr->create_flags = 0; 2979 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2980 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 2981 2982 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 2983 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 2984 2985 out_free: 2986 kfree(outb); 2987 2988 out: 2989 mutex_unlock(&qp->mutex); 2990 return err; 2991 } 2992 2993 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 2994 struct ib_ucontext *context, 2995 struct ib_udata *udata) 2996 { 2997 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2998 struct mlx5_ib_xrcd *xrcd; 2999 int err; 3000 3001 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC)) 3002 return ERR_PTR(-ENOSYS); 3003 3004 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 3005 if (!xrcd) 3006 return ERR_PTR(-ENOMEM); 3007 3008 err = mlx5_core_xrcd_alloc(&dev->mdev, &xrcd->xrcdn); 3009 if (err) { 3010 kfree(xrcd); 3011 return ERR_PTR(-ENOMEM); 3012 } 3013 3014 return &xrcd->ibxrcd; 3015 } 3016 3017 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 3018 { 3019 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 3020 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 3021 int err; 3022 3023 err = mlx5_core_xrcd_dealloc(&dev->mdev, xrcdn); 3024 if (err) { 3025 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 3026 return err; 3027 } 3028 3029 kfree(xrcd); 3030 3031 return 0; 3032 } 3033