1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "cmd.h" 42 #include "qp.h" 43 #include "wr.h" 44 45 enum { 46 MLX5_IB_ACK_REQ_FREQ = 8, 47 }; 48 49 enum { 50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 52 MLX5_IB_LINK_TYPE_IB = 0, 53 MLX5_IB_LINK_TYPE_ETH = 1 54 }; 55 56 enum raw_qp_set_mask_map { 57 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 58 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 59 }; 60 61 struct mlx5_modify_raw_qp_param { 62 u16 operation; 63 64 u32 set_mask; /* raw_qp_set_mask_map */ 65 66 struct mlx5_rate_limit rl; 67 68 u8 rq_q_ctr_id; 69 u16 port; 70 }; 71 72 static void get_cqs(enum ib_qp_type qp_type, 73 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 74 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 75 76 static int is_qp0(enum ib_qp_type qp_type) 77 { 78 return qp_type == IB_QPT_SMI; 79 } 80 81 static int is_sqp(enum ib_qp_type qp_type) 82 { 83 return is_qp0(qp_type) || is_qp1(qp_type); 84 } 85 86 /** 87 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 88 * to kernel buffer 89 * 90 * @umem: User space memory where the WQ is 91 * @buffer: buffer to copy to 92 * @buflen: buffer length 93 * @wqe_index: index of WQE to copy from 94 * @wq_offset: offset to start of WQ 95 * @wq_wqe_cnt: number of WQEs in WQ 96 * @wq_wqe_shift: log2 of WQE size 97 * @bcnt: number of bytes to copy 98 * @bytes_copied: number of bytes to copy (return value) 99 * 100 * Copies from start of WQE bcnt or less bytes. 101 * Does not gurantee to copy the entire WQE. 102 * 103 * Return: zero on success, or an error code. 104 */ 105 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 106 size_t buflen, int wqe_index, 107 int wq_offset, int wq_wqe_cnt, 108 int wq_wqe_shift, int bcnt, 109 size_t *bytes_copied) 110 { 111 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 112 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 113 size_t copy_length; 114 int ret; 115 116 /* don't copy more than requested, more than buffer length or 117 * beyond WQ end 118 */ 119 copy_length = min_t(u32, buflen, wq_end - offset); 120 copy_length = min_t(u32, copy_length, bcnt); 121 122 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 123 if (ret) 124 return ret; 125 126 if (!ret && bytes_copied) 127 *bytes_copied = copy_length; 128 129 return 0; 130 } 131 132 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 133 void *buffer, size_t buflen, size_t *bc) 134 { 135 struct mlx5_wqe_ctrl_seg *ctrl; 136 size_t bytes_copied = 0; 137 size_t wqe_length; 138 void *p; 139 int ds; 140 141 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 142 143 /* read the control segment first */ 144 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 145 ctrl = p; 146 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 147 wqe_length = ds * MLX5_WQE_DS_UNITS; 148 149 /* read rest of WQE if it spreads over more than one stride */ 150 while (bytes_copied < wqe_length) { 151 size_t copy_length = 152 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 153 154 if (!copy_length) 155 break; 156 157 memcpy(buffer + bytes_copied, p, copy_length); 158 bytes_copied += copy_length; 159 160 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 161 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 162 } 163 *bc = bytes_copied; 164 return 0; 165 } 166 167 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 168 void *buffer, size_t buflen, size_t *bc) 169 { 170 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 171 struct ib_umem *umem = base->ubuffer.umem; 172 struct mlx5_ib_wq *wq = &qp->sq; 173 struct mlx5_wqe_ctrl_seg *ctrl; 174 size_t bytes_copied; 175 size_t bytes_copied2; 176 size_t wqe_length; 177 int ret; 178 int ds; 179 180 /* at first read as much as possible */ 181 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 182 wq->offset, wq->wqe_cnt, 183 wq->wqe_shift, buflen, 184 &bytes_copied); 185 if (ret) 186 return ret; 187 188 /* we need at least control segment size to proceed */ 189 if (bytes_copied < sizeof(*ctrl)) 190 return -EINVAL; 191 192 ctrl = buffer; 193 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 194 wqe_length = ds * MLX5_WQE_DS_UNITS; 195 196 /* if we copied enough then we are done */ 197 if (bytes_copied >= wqe_length) { 198 *bc = bytes_copied; 199 return 0; 200 } 201 202 /* otherwise this a wrapped around wqe 203 * so read the remaining bytes starting 204 * from wqe_index 0 205 */ 206 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 207 buflen - bytes_copied, 0, wq->offset, 208 wq->wqe_cnt, wq->wqe_shift, 209 wqe_length - bytes_copied, 210 &bytes_copied2); 211 212 if (ret) 213 return ret; 214 *bc = bytes_copied + bytes_copied2; 215 return 0; 216 } 217 218 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 219 size_t buflen, size_t *bc) 220 { 221 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 222 struct ib_umem *umem = base->ubuffer.umem; 223 224 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 225 return -EINVAL; 226 227 if (!umem) 228 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 229 buflen, bc); 230 231 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 232 } 233 234 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 235 void *buffer, size_t buflen, size_t *bc) 236 { 237 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 238 struct ib_umem *umem = base->ubuffer.umem; 239 struct mlx5_ib_wq *wq = &qp->rq; 240 size_t bytes_copied; 241 int ret; 242 243 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 244 wq->offset, wq->wqe_cnt, 245 wq->wqe_shift, buflen, 246 &bytes_copied); 247 248 if (ret) 249 return ret; 250 *bc = bytes_copied; 251 return 0; 252 } 253 254 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 255 size_t buflen, size_t *bc) 256 { 257 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 258 struct ib_umem *umem = base->ubuffer.umem; 259 struct mlx5_ib_wq *wq = &qp->rq; 260 size_t wqe_size = 1 << wq->wqe_shift; 261 262 if (buflen < wqe_size) 263 return -EINVAL; 264 265 if (!umem) 266 return -EOPNOTSUPP; 267 268 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 269 } 270 271 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 272 void *buffer, size_t buflen, size_t *bc) 273 { 274 struct ib_umem *umem = srq->umem; 275 size_t bytes_copied; 276 int ret; 277 278 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 279 srq->msrq.max, srq->msrq.wqe_shift, 280 buflen, &bytes_copied); 281 282 if (ret) 283 return ret; 284 *bc = bytes_copied; 285 return 0; 286 } 287 288 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 289 size_t buflen, size_t *bc) 290 { 291 struct ib_umem *umem = srq->umem; 292 size_t wqe_size = 1 << srq->msrq.wqe_shift; 293 294 if (buflen < wqe_size) 295 return -EINVAL; 296 297 if (!umem) 298 return -EOPNOTSUPP; 299 300 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 301 } 302 303 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 304 { 305 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 306 struct ib_event event; 307 308 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 309 /* This event is only valid for trans_qps */ 310 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 311 } 312 313 if (ibqp->event_handler) { 314 event.device = ibqp->device; 315 event.element.qp = ibqp; 316 switch (type) { 317 case MLX5_EVENT_TYPE_PATH_MIG: 318 event.event = IB_EVENT_PATH_MIG; 319 break; 320 case MLX5_EVENT_TYPE_COMM_EST: 321 event.event = IB_EVENT_COMM_EST; 322 break; 323 case MLX5_EVENT_TYPE_SQ_DRAINED: 324 event.event = IB_EVENT_SQ_DRAINED; 325 break; 326 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 327 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 328 break; 329 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 330 event.event = IB_EVENT_QP_FATAL; 331 break; 332 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 333 event.event = IB_EVENT_PATH_MIG_ERR; 334 break; 335 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 336 event.event = IB_EVENT_QP_REQ_ERR; 337 break; 338 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 339 event.event = IB_EVENT_QP_ACCESS_ERR; 340 break; 341 default: 342 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 343 return; 344 } 345 346 ibqp->event_handler(&event, ibqp->qp_context); 347 } 348 } 349 350 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 351 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 352 { 353 int wqe_size; 354 int wq_size; 355 356 /* Sanity check RQ size before proceeding */ 357 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 358 return -EINVAL; 359 360 if (!has_rq) { 361 qp->rq.max_gs = 0; 362 qp->rq.wqe_cnt = 0; 363 qp->rq.wqe_shift = 0; 364 cap->max_recv_wr = 0; 365 cap->max_recv_sge = 0; 366 } else { 367 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 368 369 if (ucmd) { 370 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 371 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 372 return -EINVAL; 373 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 374 if ((1 << qp->rq.wqe_shift) / 375 sizeof(struct mlx5_wqe_data_seg) < 376 wq_sig) 377 return -EINVAL; 378 qp->rq.max_gs = 379 (1 << qp->rq.wqe_shift) / 380 sizeof(struct mlx5_wqe_data_seg) - 381 wq_sig; 382 qp->rq.max_post = qp->rq.wqe_cnt; 383 } else { 384 wqe_size = 385 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 386 0; 387 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 388 wqe_size = roundup_pow_of_two(wqe_size); 389 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 390 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 391 qp->rq.wqe_cnt = wq_size / wqe_size; 392 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 393 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 394 wqe_size, 395 MLX5_CAP_GEN(dev->mdev, 396 max_wqe_sz_rq)); 397 return -EINVAL; 398 } 399 qp->rq.wqe_shift = ilog2(wqe_size); 400 qp->rq.max_gs = 401 (1 << qp->rq.wqe_shift) / 402 sizeof(struct mlx5_wqe_data_seg) - 403 wq_sig; 404 qp->rq.max_post = qp->rq.wqe_cnt; 405 } 406 } 407 408 return 0; 409 } 410 411 static int sq_overhead(struct ib_qp_init_attr *attr) 412 { 413 int size = 0; 414 415 switch (attr->qp_type) { 416 case IB_QPT_XRC_INI: 417 size += sizeof(struct mlx5_wqe_xrc_seg); 418 /* fall through */ 419 case IB_QPT_RC: 420 size += sizeof(struct mlx5_wqe_ctrl_seg) + 421 max(sizeof(struct mlx5_wqe_atomic_seg) + 422 sizeof(struct mlx5_wqe_raddr_seg), 423 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 424 sizeof(struct mlx5_mkey_seg) + 425 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 426 MLX5_IB_UMR_OCTOWORD); 427 break; 428 429 case IB_QPT_XRC_TGT: 430 return 0; 431 432 case IB_QPT_UC: 433 size += sizeof(struct mlx5_wqe_ctrl_seg) + 434 max(sizeof(struct mlx5_wqe_raddr_seg), 435 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 436 sizeof(struct mlx5_mkey_seg)); 437 break; 438 439 case IB_QPT_UD: 440 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 441 size += sizeof(struct mlx5_wqe_eth_pad) + 442 sizeof(struct mlx5_wqe_eth_seg); 443 /* fall through */ 444 case IB_QPT_SMI: 445 case MLX5_IB_QPT_HW_GSI: 446 size += sizeof(struct mlx5_wqe_ctrl_seg) + 447 sizeof(struct mlx5_wqe_datagram_seg); 448 break; 449 450 case MLX5_IB_QPT_REG_UMR: 451 size += sizeof(struct mlx5_wqe_ctrl_seg) + 452 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 453 sizeof(struct mlx5_mkey_seg); 454 break; 455 456 default: 457 return -EINVAL; 458 } 459 460 return size; 461 } 462 463 static int calc_send_wqe(struct ib_qp_init_attr *attr) 464 { 465 int inl_size = 0; 466 int size; 467 468 size = sq_overhead(attr); 469 if (size < 0) 470 return size; 471 472 if (attr->cap.max_inline_data) { 473 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 474 attr->cap.max_inline_data; 475 } 476 477 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 478 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 479 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 480 return MLX5_SIG_WQE_SIZE; 481 else 482 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 483 } 484 485 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 486 { 487 int max_sge; 488 489 if (attr->qp_type == IB_QPT_RC) 490 max_sge = (min_t(int, wqe_size, 512) - 491 sizeof(struct mlx5_wqe_ctrl_seg) - 492 sizeof(struct mlx5_wqe_raddr_seg)) / 493 sizeof(struct mlx5_wqe_data_seg); 494 else if (attr->qp_type == IB_QPT_XRC_INI) 495 max_sge = (min_t(int, wqe_size, 512) - 496 sizeof(struct mlx5_wqe_ctrl_seg) - 497 sizeof(struct mlx5_wqe_xrc_seg) - 498 sizeof(struct mlx5_wqe_raddr_seg)) / 499 sizeof(struct mlx5_wqe_data_seg); 500 else 501 max_sge = (wqe_size - sq_overhead(attr)) / 502 sizeof(struct mlx5_wqe_data_seg); 503 504 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 505 sizeof(struct mlx5_wqe_data_seg)); 506 } 507 508 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 509 struct mlx5_ib_qp *qp) 510 { 511 int wqe_size; 512 int wq_size; 513 514 if (!attr->cap.max_send_wr) 515 return 0; 516 517 wqe_size = calc_send_wqe(attr); 518 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 519 if (wqe_size < 0) 520 return wqe_size; 521 522 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 523 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 524 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 525 return -EINVAL; 526 } 527 528 qp->max_inline_data = wqe_size - sq_overhead(attr) - 529 sizeof(struct mlx5_wqe_inline_seg); 530 attr->cap.max_inline_data = qp->max_inline_data; 531 532 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 533 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 534 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 535 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 536 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 537 qp->sq.wqe_cnt, 538 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 539 return -ENOMEM; 540 } 541 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 542 qp->sq.max_gs = get_send_sge(attr, wqe_size); 543 if (qp->sq.max_gs < attr->cap.max_send_sge) 544 return -ENOMEM; 545 546 attr->cap.max_send_sge = qp->sq.max_gs; 547 qp->sq.max_post = wq_size / wqe_size; 548 attr->cap.max_send_wr = qp->sq.max_post; 549 550 return wq_size; 551 } 552 553 static int set_user_buf_size(struct mlx5_ib_dev *dev, 554 struct mlx5_ib_qp *qp, 555 struct mlx5_ib_create_qp *ucmd, 556 struct mlx5_ib_qp_base *base, 557 struct ib_qp_init_attr *attr) 558 { 559 int desc_sz = 1 << qp->sq.wqe_shift; 560 561 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 562 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 563 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 564 return -EINVAL; 565 } 566 567 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 568 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 569 ucmd->sq_wqe_count); 570 return -EINVAL; 571 } 572 573 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 574 575 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 576 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 577 qp->sq.wqe_cnt, 578 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 579 return -EINVAL; 580 } 581 582 if (attr->qp_type == IB_QPT_RAW_PACKET || 583 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 584 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 585 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 586 } else { 587 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 588 (qp->sq.wqe_cnt << 6); 589 } 590 591 return 0; 592 } 593 594 static int qp_has_rq(struct ib_qp_init_attr *attr) 595 { 596 if (attr->qp_type == IB_QPT_XRC_INI || 597 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 598 attr->qp_type == MLX5_IB_QPT_REG_UMR || 599 !attr->cap.max_recv_wr) 600 return 0; 601 602 return 1; 603 } 604 605 enum { 606 /* this is the first blue flame register in the array of bfregs assigned 607 * to a processes. Since we do not use it for blue flame but rather 608 * regular 64 bit doorbells, we do not need a lock for maintaiing 609 * "odd/even" order 610 */ 611 NUM_NON_BLUE_FLAME_BFREGS = 1, 612 }; 613 614 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 615 { 616 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 617 } 618 619 static int num_med_bfreg(struct mlx5_ib_dev *dev, 620 struct mlx5_bfreg_info *bfregi) 621 { 622 int n; 623 624 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 625 NUM_NON_BLUE_FLAME_BFREGS; 626 627 return n >= 0 ? n : 0; 628 } 629 630 static int first_med_bfreg(struct mlx5_ib_dev *dev, 631 struct mlx5_bfreg_info *bfregi) 632 { 633 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 634 } 635 636 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 637 struct mlx5_bfreg_info *bfregi) 638 { 639 int med; 640 641 med = num_med_bfreg(dev, bfregi); 642 return ++med; 643 } 644 645 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 646 struct mlx5_bfreg_info *bfregi) 647 { 648 int i; 649 650 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 651 if (!bfregi->count[i]) { 652 bfregi->count[i]++; 653 return i; 654 } 655 } 656 657 return -ENOMEM; 658 } 659 660 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 661 struct mlx5_bfreg_info *bfregi) 662 { 663 int minidx = first_med_bfreg(dev, bfregi); 664 int i; 665 666 if (minidx < 0) 667 return minidx; 668 669 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 670 if (bfregi->count[i] < bfregi->count[minidx]) 671 minidx = i; 672 if (!bfregi->count[minidx]) 673 break; 674 } 675 676 bfregi->count[minidx]++; 677 return minidx; 678 } 679 680 static int alloc_bfreg(struct mlx5_ib_dev *dev, 681 struct mlx5_bfreg_info *bfregi) 682 { 683 int bfregn = -ENOMEM; 684 685 if (bfregi->lib_uar_dyn) 686 return -EINVAL; 687 688 mutex_lock(&bfregi->lock); 689 if (bfregi->ver >= 2) { 690 bfregn = alloc_high_class_bfreg(dev, bfregi); 691 if (bfregn < 0) 692 bfregn = alloc_med_class_bfreg(dev, bfregi); 693 } 694 695 if (bfregn < 0) { 696 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 697 bfregn = 0; 698 bfregi->count[bfregn]++; 699 } 700 mutex_unlock(&bfregi->lock); 701 702 return bfregn; 703 } 704 705 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 706 { 707 mutex_lock(&bfregi->lock); 708 bfregi->count[bfregn]--; 709 mutex_unlock(&bfregi->lock); 710 } 711 712 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 713 { 714 switch (state) { 715 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 716 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 717 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 718 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 719 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 720 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 721 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 722 default: return -1; 723 } 724 } 725 726 static int to_mlx5_st(enum ib_qp_type type) 727 { 728 switch (type) { 729 case IB_QPT_RC: return MLX5_QP_ST_RC; 730 case IB_QPT_UC: return MLX5_QP_ST_UC; 731 case IB_QPT_UD: return MLX5_QP_ST_UD; 732 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 733 case IB_QPT_XRC_INI: 734 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 735 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 736 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 737 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 738 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 739 default: return -EINVAL; 740 } 741 } 742 743 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 744 struct mlx5_ib_cq *recv_cq); 745 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 746 struct mlx5_ib_cq *recv_cq); 747 748 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 749 struct mlx5_bfreg_info *bfregi, u32 bfregn, 750 bool dyn_bfreg) 751 { 752 unsigned int bfregs_per_sys_page; 753 u32 index_of_sys_page; 754 u32 offset; 755 756 if (bfregi->lib_uar_dyn) 757 return -EINVAL; 758 759 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 760 MLX5_NON_FP_BFREGS_PER_UAR; 761 index_of_sys_page = bfregn / bfregs_per_sys_page; 762 763 if (dyn_bfreg) { 764 index_of_sys_page += bfregi->num_static_sys_pages; 765 766 if (index_of_sys_page >= bfregi->num_sys_pages) 767 return -EINVAL; 768 769 if (bfregn > bfregi->num_dyn_bfregs || 770 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 771 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 772 return -EINVAL; 773 } 774 } 775 776 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 777 return bfregi->sys_pages[index_of_sys_page] + offset; 778 } 779 780 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, 781 unsigned long addr, size_t size, 782 struct ib_umem **umem, int *npages, int *page_shift, 783 int *ncont, u32 *offset) 784 { 785 int err; 786 787 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0); 788 if (IS_ERR(*umem)) { 789 mlx5_ib_dbg(dev, "umem_get failed\n"); 790 return PTR_ERR(*umem); 791 } 792 793 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 794 795 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 796 if (err) { 797 mlx5_ib_warn(dev, "bad offset\n"); 798 goto err_umem; 799 } 800 801 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 802 addr, size, *npages, *page_shift, *ncont, *offset); 803 804 return 0; 805 806 err_umem: 807 ib_umem_release(*umem); 808 *umem = NULL; 809 810 return err; 811 } 812 813 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 814 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 815 { 816 struct mlx5_ib_ucontext *context = 817 rdma_udata_to_drv_context( 818 udata, 819 struct mlx5_ib_ucontext, 820 ibucontext); 821 822 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 823 atomic_dec(&dev->delay_drop.rqs_cnt); 824 825 mlx5_ib_db_unmap_user(context, &rwq->db); 826 ib_umem_release(rwq->umem); 827 } 828 829 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 830 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 831 struct mlx5_ib_create_wq *ucmd) 832 { 833 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 834 udata, struct mlx5_ib_ucontext, ibucontext); 835 int page_shift = 0; 836 int npages; 837 u32 offset = 0; 838 int ncont = 0; 839 int err; 840 841 if (!ucmd->buf_addr) 842 return -EINVAL; 843 844 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 845 if (IS_ERR(rwq->umem)) { 846 mlx5_ib_dbg(dev, "umem_get failed\n"); 847 err = PTR_ERR(rwq->umem); 848 return err; 849 } 850 851 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 852 &ncont, NULL); 853 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 854 &rwq->rq_page_offset); 855 if (err) { 856 mlx5_ib_warn(dev, "bad offset\n"); 857 goto err_umem; 858 } 859 860 rwq->rq_num_pas = ncont; 861 rwq->page_shift = page_shift; 862 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 863 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 864 865 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 866 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 867 npages, page_shift, ncont, offset); 868 869 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 870 if (err) { 871 mlx5_ib_dbg(dev, "map failed\n"); 872 goto err_umem; 873 } 874 875 return 0; 876 877 err_umem: 878 ib_umem_release(rwq->umem); 879 return err; 880 } 881 882 static int adjust_bfregn(struct mlx5_ib_dev *dev, 883 struct mlx5_bfreg_info *bfregi, int bfregn) 884 { 885 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 886 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 887 } 888 889 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 890 struct mlx5_ib_qp *qp, struct ib_udata *udata, 891 struct ib_qp_init_attr *attr, u32 **in, 892 struct mlx5_ib_create_qp_resp *resp, int *inlen, 893 struct mlx5_ib_qp_base *base, 894 struct mlx5_ib_create_qp *ucmd) 895 { 896 struct mlx5_ib_ucontext *context; 897 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 898 int page_shift = 0; 899 int uar_index = 0; 900 int npages; 901 u32 offset = 0; 902 int bfregn; 903 int ncont = 0; 904 __be64 *pas; 905 void *qpc; 906 int err; 907 u16 uid; 908 u32 uar_flags; 909 910 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 911 ibucontext); 912 uar_flags = qp->flags_en & 913 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 914 switch (uar_flags) { 915 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 916 uar_index = ucmd->bfreg_index; 917 bfregn = MLX5_IB_INVALID_BFREG; 918 break; 919 case MLX5_QP_FLAG_BFREG_INDEX: 920 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 921 ucmd->bfreg_index, true); 922 if (uar_index < 0) 923 return uar_index; 924 bfregn = MLX5_IB_INVALID_BFREG; 925 break; 926 case 0: 927 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 928 return -EINVAL; 929 bfregn = alloc_bfreg(dev, &context->bfregi); 930 if (bfregn < 0) 931 return bfregn; 932 break; 933 default: 934 return -EINVAL; 935 } 936 937 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 938 if (bfregn != MLX5_IB_INVALID_BFREG) 939 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 940 false); 941 942 qp->rq.offset = 0; 943 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 944 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 945 946 err = set_user_buf_size(dev, qp, ucmd, base, attr); 947 if (err) 948 goto err_bfreg; 949 950 if (ucmd->buf_addr && ubuffer->buf_size) { 951 ubuffer->buf_addr = ucmd->buf_addr; 952 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, 953 ubuffer->buf_size, &ubuffer->umem, 954 &npages, &page_shift, &ncont, &offset); 955 if (err) 956 goto err_bfreg; 957 } else { 958 ubuffer->umem = NULL; 959 } 960 961 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 962 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 963 *in = kvzalloc(*inlen, GFP_KERNEL); 964 if (!*in) { 965 err = -ENOMEM; 966 goto err_umem; 967 } 968 969 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 970 MLX5_SET(create_qp_in, *in, uid, uid); 971 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 972 if (ubuffer->umem) 973 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 974 975 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 976 977 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 978 MLX5_SET(qpc, qpc, page_offset, offset); 979 980 MLX5_SET(qpc, qpc, uar_page, uar_index); 981 if (bfregn != MLX5_IB_INVALID_BFREG) 982 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 983 else 984 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 985 qp->bfregn = bfregn; 986 987 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db); 988 if (err) { 989 mlx5_ib_dbg(dev, "map failed\n"); 990 goto err_free; 991 } 992 993 return 0; 994 995 err_free: 996 kvfree(*in); 997 998 err_umem: 999 ib_umem_release(ubuffer->umem); 1000 1001 err_bfreg: 1002 if (bfregn != MLX5_IB_INVALID_BFREG) 1003 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1004 return err; 1005 } 1006 1007 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1008 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 1009 { 1010 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1011 udata, struct mlx5_ib_ucontext, ibucontext); 1012 1013 if (udata) { 1014 /* User QP */ 1015 mlx5_ib_db_unmap_user(context, &qp->db); 1016 ib_umem_release(base->ubuffer.umem); 1017 1018 /* 1019 * Free only the BFREGs which are handled by the kernel. 1020 * BFREGs of UARs allocated dynamically are handled by user. 1021 */ 1022 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1023 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1024 return; 1025 } 1026 1027 /* Kernel QP */ 1028 kvfree(qp->sq.wqe_head); 1029 kvfree(qp->sq.w_list); 1030 kvfree(qp->sq.wrid); 1031 kvfree(qp->sq.wr_data); 1032 kvfree(qp->rq.wrid); 1033 if (qp->db.db) 1034 mlx5_db_free(dev->mdev, &qp->db); 1035 if (qp->buf.frags) 1036 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1037 } 1038 1039 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1040 struct ib_qp_init_attr *init_attr, 1041 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1042 struct mlx5_ib_qp_base *base) 1043 { 1044 int uar_index; 1045 void *qpc; 1046 int err; 1047 1048 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1049 qp->bf.bfreg = &dev->fp_bfreg; 1050 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1051 qp->bf.bfreg = &dev->wc_bfreg; 1052 else 1053 qp->bf.bfreg = &dev->bfreg; 1054 1055 /* We need to divide by two since each register is comprised of 1056 * two buffers of identical size, namely odd and even 1057 */ 1058 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1059 uar_index = qp->bf.bfreg->index; 1060 1061 err = calc_sq_size(dev, init_attr, qp); 1062 if (err < 0) { 1063 mlx5_ib_dbg(dev, "err %d\n", err); 1064 return err; 1065 } 1066 1067 qp->rq.offset = 0; 1068 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1069 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1070 1071 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1072 &qp->buf, dev->mdev->priv.numa_node); 1073 if (err) { 1074 mlx5_ib_dbg(dev, "err %d\n", err); 1075 return err; 1076 } 1077 1078 if (qp->rq.wqe_cnt) 1079 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1080 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1081 1082 if (qp->sq.wqe_cnt) { 1083 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1084 MLX5_SEND_WQE_BB; 1085 mlx5_init_fbc_offset(qp->buf.frags + 1086 (qp->sq.offset / PAGE_SIZE), 1087 ilog2(MLX5_SEND_WQE_BB), 1088 ilog2(qp->sq.wqe_cnt), 1089 sq_strides_offset, &qp->sq.fbc); 1090 1091 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1092 } 1093 1094 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1095 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1096 *in = kvzalloc(*inlen, GFP_KERNEL); 1097 if (!*in) { 1098 err = -ENOMEM; 1099 goto err_buf; 1100 } 1101 1102 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1103 MLX5_SET(qpc, qpc, uar_page, uar_index); 1104 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1105 1106 /* Set "fast registration enabled" for all kernel QPs */ 1107 MLX5_SET(qpc, qpc, fre, 1); 1108 MLX5_SET(qpc, qpc, rlky, 1); 1109 1110 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1111 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1112 1113 mlx5_fill_page_frag_array(&qp->buf, 1114 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1115 *in, pas)); 1116 1117 err = mlx5_db_alloc(dev->mdev, &qp->db); 1118 if (err) { 1119 mlx5_ib_dbg(dev, "err %d\n", err); 1120 goto err_free; 1121 } 1122 1123 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1124 sizeof(*qp->sq.wrid), GFP_KERNEL); 1125 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1126 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1127 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1128 sizeof(*qp->rq.wrid), GFP_KERNEL); 1129 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1130 sizeof(*qp->sq.w_list), GFP_KERNEL); 1131 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1132 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1133 1134 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1135 !qp->sq.w_list || !qp->sq.wqe_head) { 1136 err = -ENOMEM; 1137 goto err_wrid; 1138 } 1139 1140 return 0; 1141 1142 err_wrid: 1143 kvfree(qp->sq.wqe_head); 1144 kvfree(qp->sq.w_list); 1145 kvfree(qp->sq.wrid); 1146 kvfree(qp->sq.wr_data); 1147 kvfree(qp->rq.wrid); 1148 mlx5_db_free(dev->mdev, &qp->db); 1149 1150 err_free: 1151 kvfree(*in); 1152 1153 err_buf: 1154 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1155 return err; 1156 } 1157 1158 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1159 { 1160 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1161 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1162 return MLX5_SRQ_RQ; 1163 else if (!qp->has_rq) 1164 return MLX5_ZERO_LEN_RQ; 1165 1166 return MLX5_NON_ZERO_RQ; 1167 } 1168 1169 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1170 struct mlx5_ib_qp *qp, 1171 struct mlx5_ib_sq *sq, u32 tdn, 1172 struct ib_pd *pd) 1173 { 1174 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1175 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1176 1177 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1178 MLX5_SET(tisc, tisc, transport_domain, tdn); 1179 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1180 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1181 1182 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1183 } 1184 1185 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1186 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1187 { 1188 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1189 } 1190 1191 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1192 { 1193 if (sq->flow_rule) 1194 mlx5_del_flow_rules(sq->flow_rule); 1195 sq->flow_rule = NULL; 1196 } 1197 1198 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1199 struct ib_udata *udata, 1200 struct mlx5_ib_sq *sq, void *qpin, 1201 struct ib_pd *pd) 1202 { 1203 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1204 __be64 *pas; 1205 void *in; 1206 void *sqc; 1207 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1208 void *wq; 1209 int inlen; 1210 int err; 1211 int page_shift = 0; 1212 int npages; 1213 int ncont = 0; 1214 u32 offset = 0; 1215 1216 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, 1217 &sq->ubuffer.umem, &npages, &page_shift, &ncont, 1218 &offset); 1219 if (err) 1220 return err; 1221 1222 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1223 in = kvzalloc(inlen, GFP_KERNEL); 1224 if (!in) { 1225 err = -ENOMEM; 1226 goto err_umem; 1227 } 1228 1229 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1230 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1231 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1232 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1233 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1234 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1235 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1236 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1237 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1238 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1239 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1240 MLX5_CAP_ETH(dev->mdev, swp)) 1241 MLX5_SET(sqc, sqc, allow_swp, 1); 1242 1243 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1244 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1245 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1246 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1247 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1248 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1249 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1250 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1251 MLX5_SET(wq, wq, page_offset, offset); 1252 1253 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1254 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1255 1256 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1257 1258 kvfree(in); 1259 1260 if (err) 1261 goto err_umem; 1262 1263 return 0; 1264 1265 err_umem: 1266 ib_umem_release(sq->ubuffer.umem); 1267 sq->ubuffer.umem = NULL; 1268 1269 return err; 1270 } 1271 1272 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1273 struct mlx5_ib_sq *sq) 1274 { 1275 destroy_flow_rule_vport_sq(sq); 1276 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1277 ib_umem_release(sq->ubuffer.umem); 1278 } 1279 1280 static size_t get_rq_pas_size(void *qpc) 1281 { 1282 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1283 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1284 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1285 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1286 u32 po_quanta = 1 << (log_page_size - 6); 1287 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1288 u32 page_size = 1 << log_page_size; 1289 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1290 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1291 1292 return rq_num_pas * sizeof(u64); 1293 } 1294 1295 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1296 struct mlx5_ib_rq *rq, void *qpin, 1297 size_t qpinlen, struct ib_pd *pd) 1298 { 1299 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1300 __be64 *pas; 1301 __be64 *qp_pas; 1302 void *in; 1303 void *rqc; 1304 void *wq; 1305 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1306 size_t rq_pas_size = get_rq_pas_size(qpc); 1307 size_t inlen; 1308 int err; 1309 1310 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1311 return -EINVAL; 1312 1313 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1314 in = kvzalloc(inlen, GFP_KERNEL); 1315 if (!in) 1316 return -ENOMEM; 1317 1318 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1319 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1320 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1321 MLX5_SET(rqc, rqc, vsd, 1); 1322 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1323 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1324 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1325 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1326 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1327 1328 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1329 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1330 1331 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1332 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1333 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1334 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1335 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1336 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1337 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1338 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1339 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1340 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1341 1342 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1343 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1344 memcpy(pas, qp_pas, rq_pas_size); 1345 1346 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1347 1348 kvfree(in); 1349 1350 return err; 1351 } 1352 1353 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1354 struct mlx5_ib_rq *rq) 1355 { 1356 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1357 } 1358 1359 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1360 struct mlx5_ib_rq *rq, 1361 u32 qp_flags_en, 1362 struct ib_pd *pd) 1363 { 1364 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1365 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1366 mlx5_ib_disable_lb(dev, false, true); 1367 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1368 } 1369 1370 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1371 struct mlx5_ib_rq *rq, u32 tdn, 1372 u32 *qp_flags_en, struct ib_pd *pd, 1373 u32 *out) 1374 { 1375 u8 lb_flag = 0; 1376 u32 *in; 1377 void *tirc; 1378 int inlen; 1379 int err; 1380 1381 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1382 in = kvzalloc(inlen, GFP_KERNEL); 1383 if (!in) 1384 return -ENOMEM; 1385 1386 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1387 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1388 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1389 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1390 MLX5_SET(tirc, tirc, transport_domain, tdn); 1391 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1392 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1393 1394 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1395 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1396 1397 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1398 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1399 1400 if (dev->is_rep) { 1401 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1402 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1403 } 1404 1405 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1406 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1407 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1408 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1409 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1410 err = mlx5_ib_enable_lb(dev, false, true); 1411 1412 if (err) 1413 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1414 } 1415 kvfree(in); 1416 1417 return err; 1418 } 1419 1420 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1421 u32 *in, size_t inlen, 1422 struct ib_pd *pd, 1423 struct ib_udata *udata, 1424 struct mlx5_ib_create_qp_resp *resp) 1425 { 1426 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1427 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1428 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1429 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1430 udata, struct mlx5_ib_ucontext, ibucontext); 1431 int err; 1432 u32 tdn = mucontext->tdn; 1433 u16 uid = to_mpd(pd)->uid; 1434 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1435 1436 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1437 return -EINVAL; 1438 if (qp->sq.wqe_cnt) { 1439 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1440 if (err) 1441 return err; 1442 1443 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); 1444 if (err) 1445 goto err_destroy_tis; 1446 1447 if (uid) { 1448 resp->tisn = sq->tisn; 1449 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1450 resp->sqn = sq->base.mqp.qpn; 1451 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1452 } 1453 1454 sq->base.container_mibqp = qp; 1455 sq->base.mqp.event = mlx5_ib_qp_event; 1456 } 1457 1458 if (qp->rq.wqe_cnt) { 1459 rq->base.container_mibqp = qp; 1460 1461 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1462 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1463 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1464 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1465 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1466 if (err) 1467 goto err_destroy_sq; 1468 1469 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1470 out); 1471 if (err) 1472 goto err_destroy_rq; 1473 1474 if (uid) { 1475 resp->rqn = rq->base.mqp.qpn; 1476 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1477 resp->tirn = rq->tirn; 1478 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1479 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1480 resp->tir_icm_addr = MLX5_GET( 1481 create_tir_out, out, icm_address_31_0); 1482 resp->tir_icm_addr |= 1483 (u64)MLX5_GET(create_tir_out, out, 1484 icm_address_39_32) 1485 << 32; 1486 resp->tir_icm_addr |= 1487 (u64)MLX5_GET(create_tir_out, out, 1488 icm_address_63_40) 1489 << 40; 1490 resp->comp_mask |= 1491 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1492 } 1493 } 1494 } 1495 1496 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1497 rq->base.mqp.qpn; 1498 return 0; 1499 1500 err_destroy_rq: 1501 destroy_raw_packet_qp_rq(dev, rq); 1502 err_destroy_sq: 1503 if (!qp->sq.wqe_cnt) 1504 return err; 1505 destroy_raw_packet_qp_sq(dev, sq); 1506 err_destroy_tis: 1507 destroy_raw_packet_qp_tis(dev, sq, pd); 1508 1509 return err; 1510 } 1511 1512 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1513 struct mlx5_ib_qp *qp) 1514 { 1515 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1516 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1517 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1518 1519 if (qp->rq.wqe_cnt) { 1520 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1521 destroy_raw_packet_qp_rq(dev, rq); 1522 } 1523 1524 if (qp->sq.wqe_cnt) { 1525 destroy_raw_packet_qp_sq(dev, sq); 1526 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1527 } 1528 } 1529 1530 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1531 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1532 { 1533 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1534 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1535 1536 sq->sq = &qp->sq; 1537 rq->rq = &qp->rq; 1538 sq->doorbell = &qp->db; 1539 rq->doorbell = &qp->db; 1540 } 1541 1542 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1543 { 1544 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1545 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1546 mlx5_ib_disable_lb(dev, false, true); 1547 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1548 to_mpd(qp->ibqp.pd)->uid); 1549 } 1550 1551 struct mlx5_create_qp_params { 1552 struct ib_udata *udata; 1553 size_t inlen; 1554 size_t outlen; 1555 size_t ucmd_size; 1556 void *ucmd; 1557 u8 is_rss_raw : 1; 1558 struct ib_qp_init_attr *attr; 1559 u32 uidx; 1560 struct mlx5_ib_create_qp_resp resp; 1561 }; 1562 1563 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1564 struct mlx5_ib_qp *qp, 1565 struct mlx5_create_qp_params *params) 1566 { 1567 struct ib_qp_init_attr *init_attr = params->attr; 1568 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1569 struct ib_udata *udata = params->udata; 1570 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1571 udata, struct mlx5_ib_ucontext, ibucontext); 1572 int inlen; 1573 int outlen; 1574 int err; 1575 u32 *in; 1576 u32 *out; 1577 void *tirc; 1578 void *hfso; 1579 u32 selected_fields = 0; 1580 u32 outer_l4; 1581 u32 tdn = mucontext->tdn; 1582 u8 lb_flag = 0; 1583 1584 if (ucmd->comp_mask) { 1585 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1586 return -EOPNOTSUPP; 1587 } 1588 1589 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1590 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1591 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1592 return -EOPNOTSUPP; 1593 } 1594 1595 if (dev->is_rep) 1596 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1597 1598 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1599 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1600 1601 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1602 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1603 1604 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1605 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1606 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1607 if (!in) 1608 return -ENOMEM; 1609 1610 out = in + MLX5_ST_SZ_DW(create_tir_in); 1611 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1612 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1613 MLX5_SET(tirc, tirc, disp_type, 1614 MLX5_TIRC_DISP_TYPE_INDIRECT); 1615 MLX5_SET(tirc, tirc, indirect_table, 1616 init_attr->rwq_ind_tbl->ind_tbl_num); 1617 MLX5_SET(tirc, tirc, transport_domain, tdn); 1618 1619 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1620 1621 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1622 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1623 1624 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1625 1626 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1627 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1628 else 1629 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1630 1631 switch (ucmd->rx_hash_function) { 1632 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1633 { 1634 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1635 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1636 1637 if (len != ucmd->rx_key_len) { 1638 err = -EINVAL; 1639 goto err; 1640 } 1641 1642 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1643 memcpy(rss_key, ucmd->rx_hash_key, len); 1644 break; 1645 } 1646 default: 1647 err = -EOPNOTSUPP; 1648 goto err; 1649 } 1650 1651 if (!ucmd->rx_hash_fields_mask) { 1652 /* special case when this TIR serves as steering entry without hashing */ 1653 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1654 goto create_tir; 1655 err = -EINVAL; 1656 goto err; 1657 } 1658 1659 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1660 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1661 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1662 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1663 err = -EINVAL; 1664 goto err; 1665 } 1666 1667 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1668 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1669 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1670 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1671 MLX5_L3_PROT_TYPE_IPV4); 1672 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1673 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1674 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1675 MLX5_L3_PROT_TYPE_IPV6); 1676 1677 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1678 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1679 << 0 | 1680 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1681 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1682 << 1 | 1683 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1684 1685 /* Check that only one l4 protocol is set */ 1686 if (outer_l4 & (outer_l4 - 1)) { 1687 err = -EINVAL; 1688 goto err; 1689 } 1690 1691 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1692 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1693 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1694 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1695 MLX5_L4_PROT_TYPE_TCP); 1696 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1697 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1698 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1699 MLX5_L4_PROT_TYPE_UDP); 1700 1701 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1702 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1703 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1704 1705 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1706 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1707 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1708 1709 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1710 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1711 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1712 1713 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1714 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1715 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1716 1717 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1718 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1719 1720 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1721 1722 create_tir: 1723 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1724 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1725 1726 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1727 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1728 err = mlx5_ib_enable_lb(dev, false, true); 1729 1730 if (err) 1731 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1732 to_mpd(pd)->uid); 1733 } 1734 1735 if (err) 1736 goto err; 1737 1738 if (mucontext->devx_uid) { 1739 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1740 params->resp.tirn = qp->rss_qp.tirn; 1741 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { 1742 params->resp.tir_icm_addr = 1743 MLX5_GET(create_tir_out, out, icm_address_31_0); 1744 params->resp.tir_icm_addr |= 1745 (u64)MLX5_GET(create_tir_out, out, 1746 icm_address_39_32) 1747 << 32; 1748 params->resp.tir_icm_addr |= 1749 (u64)MLX5_GET(create_tir_out, out, 1750 icm_address_63_40) 1751 << 40; 1752 params->resp.comp_mask |= 1753 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1754 } 1755 } 1756 1757 kvfree(in); 1758 /* qpn is reserved for that QP */ 1759 qp->trans_qp.base.mqp.qpn = 0; 1760 qp->is_rss = true; 1761 return 0; 1762 1763 err: 1764 kvfree(in); 1765 return err; 1766 } 1767 1768 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1769 struct mlx5_ib_qp *qp, 1770 struct ib_qp_init_attr *init_attr, 1771 void *qpc) 1772 { 1773 int scqe_sz; 1774 bool allow_scat_cqe = false; 1775 1776 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1777 1778 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1779 return; 1780 1781 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1782 if (scqe_sz == 128) { 1783 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1784 return; 1785 } 1786 1787 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1788 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1789 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1790 } 1791 1792 static int atomic_size_to_mode(int size_mask) 1793 { 1794 /* driver does not support atomic_size > 256B 1795 * and does not know how to translate bigger sizes 1796 */ 1797 int supported_size_mask = size_mask & 0x1ff; 1798 int log_max_size; 1799 1800 if (!supported_size_mask) 1801 return -EOPNOTSUPP; 1802 1803 log_max_size = __fls(supported_size_mask); 1804 1805 if (log_max_size > 3) 1806 return log_max_size; 1807 1808 return MLX5_ATOMIC_MODE_8B; 1809 } 1810 1811 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1812 enum ib_qp_type qp_type) 1813 { 1814 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1815 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1816 int atomic_mode = -EOPNOTSUPP; 1817 int atomic_size_mask; 1818 1819 if (!atomic) 1820 return -EOPNOTSUPP; 1821 1822 if (qp_type == MLX5_IB_QPT_DCT) 1823 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1824 else 1825 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1826 1827 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1828 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1829 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1830 1831 if (atomic_mode <= 0 && 1832 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1833 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1834 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1835 1836 return atomic_mode; 1837 } 1838 1839 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1840 struct mlx5_create_qp_params *params) 1841 { 1842 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1843 struct ib_qp_init_attr *attr = params->attr; 1844 u32 uidx = params->uidx; 1845 struct mlx5_ib_resources *devr = &dev->devr; 1846 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1847 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1848 struct mlx5_core_dev *mdev = dev->mdev; 1849 struct mlx5_ib_qp_base *base; 1850 unsigned long flags; 1851 void *qpc; 1852 u32 *in; 1853 int err; 1854 1855 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1856 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1857 1858 in = kvzalloc(inlen, GFP_KERNEL); 1859 if (!in) 1860 return -ENOMEM; 1861 1862 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd) 1863 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1864 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1865 1866 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 1867 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1868 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 1869 1870 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1871 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1872 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1873 MLX5_SET(qpc, qpc, cd_master, 1); 1874 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1875 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1876 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1877 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1878 1879 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 1880 MLX5_SET(qpc, qpc, no_sq, 1); 1881 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1882 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1883 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1884 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 1885 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1886 1887 /* 0xffffff means we ask to work with cqe version 0 */ 1888 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1889 MLX5_SET(qpc, qpc, user_index, uidx); 1890 1891 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1892 MLX5_SET(qpc, qpc, end_padding_mode, 1893 MLX5_WQ_END_PAD_MODE_ALIGN); 1894 /* Special case to clean flag */ 1895 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 1896 } 1897 1898 base = &qp->trans_qp.base; 1899 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 1900 kvfree(in); 1901 if (err) 1902 return err; 1903 1904 base->container_mibqp = qp; 1905 base->mqp.event = mlx5_ib_qp_event; 1906 if (MLX5_CAP_GEN(mdev, ece_support)) 1907 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 1908 1909 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1910 list_add_tail(&qp->qps_list, &dev->qp_list); 1911 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1912 1913 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 1914 return 0; 1915 } 1916 1917 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1918 struct mlx5_ib_qp *qp, 1919 struct mlx5_create_qp_params *params) 1920 { 1921 struct ib_qp_init_attr *init_attr = params->attr; 1922 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1923 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1924 struct ib_udata *udata = params->udata; 1925 u32 uidx = params->uidx; 1926 struct mlx5_ib_resources *devr = &dev->devr; 1927 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1928 struct mlx5_core_dev *mdev = dev->mdev; 1929 struct mlx5_ib_cq *send_cq; 1930 struct mlx5_ib_cq *recv_cq; 1931 unsigned long flags; 1932 struct mlx5_ib_qp_base *base; 1933 int mlx5_st; 1934 void *qpc; 1935 u32 *in; 1936 int err; 1937 1938 spin_lock_init(&qp->sq.lock); 1939 spin_lock_init(&qp->rq.lock); 1940 1941 mlx5_st = to_mlx5_st(qp->type); 1942 if (mlx5_st < 0) 1943 return -EINVAL; 1944 1945 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1946 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1947 1948 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1949 qp->underlay_qpn = init_attr->source_qpn; 1950 1951 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1952 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 1953 &qp->raw_packet_qp.rq.base : 1954 &qp->trans_qp.base; 1955 1956 qp->has_rq = qp_has_rq(init_attr); 1957 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 1958 if (err) { 1959 mlx5_ib_dbg(dev, "err %d\n", err); 1960 return err; 1961 } 1962 1963 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 1964 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 1965 return -EINVAL; 1966 1967 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 1968 return -EINVAL; 1969 1970 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 1971 &inlen, base, ucmd); 1972 if (err) 1973 return err; 1974 1975 if (is_sqp(init_attr->qp_type)) 1976 qp->port = init_attr->port_num; 1977 1978 if (MLX5_CAP_GEN(mdev, ece_support)) 1979 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1980 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1981 1982 MLX5_SET(qpc, qpc, st, mlx5_st); 1983 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1984 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 1985 1986 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 1987 MLX5_SET(qpc, qpc, wq_signature, 1); 1988 1989 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1990 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1991 1992 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1993 MLX5_SET(qpc, qpc, cd_master, 1); 1994 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1995 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1996 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1997 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1998 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 1999 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2000 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2001 (init_attr->qp_type == IB_QPT_RC || 2002 init_attr->qp_type == IB_QPT_UC)) { 2003 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2004 2005 MLX5_SET(qpc, qpc, cs_res, 2006 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2007 MLX5_RES_SCAT_DATA32_CQE); 2008 } 2009 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2010 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2011 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2012 2013 if (qp->rq.wqe_cnt) { 2014 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2015 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2016 } 2017 2018 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2019 2020 if (qp->sq.wqe_cnt) { 2021 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2022 } else { 2023 MLX5_SET(qpc, qpc, no_sq, 1); 2024 if (init_attr->srq && 2025 init_attr->srq->srq_type == IB_SRQT_TM) 2026 MLX5_SET(qpc, qpc, offload_type, 2027 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2028 } 2029 2030 /* Set default resources */ 2031 switch (init_attr->qp_type) { 2032 case IB_QPT_XRC_INI: 2033 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2034 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2035 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2036 break; 2037 default: 2038 if (init_attr->srq) { 2039 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2040 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2041 } else { 2042 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2043 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2044 } 2045 } 2046 2047 if (init_attr->send_cq) 2048 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2049 2050 if (init_attr->recv_cq) 2051 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2052 2053 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2054 2055 /* 0xffffff means we ask to work with cqe version 0 */ 2056 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2057 MLX5_SET(qpc, qpc, user_index, uidx); 2058 2059 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2060 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2061 MLX5_SET(qpc, qpc, end_padding_mode, 2062 MLX5_WQ_END_PAD_MODE_ALIGN); 2063 /* Special case to clean flag */ 2064 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2065 } 2066 2067 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2068 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2069 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2070 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2071 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2072 ¶ms->resp); 2073 } else 2074 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2075 2076 kvfree(in); 2077 if (err) 2078 goto err_create; 2079 2080 base->container_mibqp = qp; 2081 base->mqp.event = mlx5_ib_qp_event; 2082 if (MLX5_CAP_GEN(mdev, ece_support)) 2083 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2084 2085 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2086 &send_cq, &recv_cq); 2087 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2088 mlx5_ib_lock_cqs(send_cq, recv_cq); 2089 /* Maintain device to QPs access, needed for further handling via reset 2090 * flow 2091 */ 2092 list_add_tail(&qp->qps_list, &dev->qp_list); 2093 /* Maintain CQ to QPs access, needed for further handling via reset flow 2094 */ 2095 if (send_cq) 2096 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2097 if (recv_cq) 2098 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2099 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2100 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2101 2102 return 0; 2103 2104 err_create: 2105 destroy_qp(dev, qp, base, udata); 2106 return err; 2107 } 2108 2109 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2110 struct mlx5_ib_qp *qp, 2111 struct mlx5_create_qp_params *params) 2112 { 2113 struct ib_qp_init_attr *attr = params->attr; 2114 u32 uidx = params->uidx; 2115 struct mlx5_ib_resources *devr = &dev->devr; 2116 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2117 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2118 struct mlx5_core_dev *mdev = dev->mdev; 2119 struct mlx5_ib_cq *send_cq; 2120 struct mlx5_ib_cq *recv_cq; 2121 unsigned long flags; 2122 struct mlx5_ib_qp_base *base; 2123 int mlx5_st; 2124 void *qpc; 2125 u32 *in; 2126 int err; 2127 2128 spin_lock_init(&qp->sq.lock); 2129 spin_lock_init(&qp->rq.lock); 2130 2131 mlx5_st = to_mlx5_st(qp->type); 2132 if (mlx5_st < 0) 2133 return -EINVAL; 2134 2135 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2136 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2137 2138 base = &qp->trans_qp.base; 2139 2140 qp->has_rq = qp_has_rq(attr); 2141 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2142 if (err) { 2143 mlx5_ib_dbg(dev, "err %d\n", err); 2144 return err; 2145 } 2146 2147 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2148 if (err) 2149 return err; 2150 2151 if (is_sqp(attr->qp_type)) 2152 qp->port = attr->port_num; 2153 2154 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2155 2156 MLX5_SET(qpc, qpc, st, mlx5_st); 2157 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2158 2159 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2160 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2161 else 2162 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2163 2164 2165 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2166 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2167 2168 if (qp->rq.wqe_cnt) { 2169 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2170 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2171 } 2172 2173 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2174 2175 if (qp->sq.wqe_cnt) 2176 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2177 else 2178 MLX5_SET(qpc, qpc, no_sq, 1); 2179 2180 if (attr->srq) { 2181 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2182 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2183 to_msrq(attr->srq)->msrq.srqn); 2184 } else { 2185 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2186 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2187 to_msrq(devr->s1)->msrq.srqn); 2188 } 2189 2190 if (attr->send_cq) 2191 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2192 2193 if (attr->recv_cq) 2194 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2195 2196 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2197 2198 /* 0xffffff means we ask to work with cqe version 0 */ 2199 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2200 MLX5_SET(qpc, qpc, user_index, uidx); 2201 2202 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2203 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2204 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2205 2206 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2207 kvfree(in); 2208 if (err) 2209 goto err_create; 2210 2211 base->container_mibqp = qp; 2212 base->mqp.event = mlx5_ib_qp_event; 2213 2214 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2215 &send_cq, &recv_cq); 2216 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2217 mlx5_ib_lock_cqs(send_cq, recv_cq); 2218 /* Maintain device to QPs access, needed for further handling via reset 2219 * flow 2220 */ 2221 list_add_tail(&qp->qps_list, &dev->qp_list); 2222 /* Maintain CQ to QPs access, needed for further handling via reset flow 2223 */ 2224 if (send_cq) 2225 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2226 if (recv_cq) 2227 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2228 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2229 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2230 2231 return 0; 2232 2233 err_create: 2234 destroy_qp(dev, qp, base, NULL); 2235 return err; 2236 } 2237 2238 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2239 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2240 { 2241 if (send_cq) { 2242 if (recv_cq) { 2243 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2244 spin_lock(&send_cq->lock); 2245 spin_lock_nested(&recv_cq->lock, 2246 SINGLE_DEPTH_NESTING); 2247 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2248 spin_lock(&send_cq->lock); 2249 __acquire(&recv_cq->lock); 2250 } else { 2251 spin_lock(&recv_cq->lock); 2252 spin_lock_nested(&send_cq->lock, 2253 SINGLE_DEPTH_NESTING); 2254 } 2255 } else { 2256 spin_lock(&send_cq->lock); 2257 __acquire(&recv_cq->lock); 2258 } 2259 } else if (recv_cq) { 2260 spin_lock(&recv_cq->lock); 2261 __acquire(&send_cq->lock); 2262 } else { 2263 __acquire(&send_cq->lock); 2264 __acquire(&recv_cq->lock); 2265 } 2266 } 2267 2268 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2269 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2270 { 2271 if (send_cq) { 2272 if (recv_cq) { 2273 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2274 spin_unlock(&recv_cq->lock); 2275 spin_unlock(&send_cq->lock); 2276 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2277 __release(&recv_cq->lock); 2278 spin_unlock(&send_cq->lock); 2279 } else { 2280 spin_unlock(&send_cq->lock); 2281 spin_unlock(&recv_cq->lock); 2282 } 2283 } else { 2284 __release(&recv_cq->lock); 2285 spin_unlock(&send_cq->lock); 2286 } 2287 } else if (recv_cq) { 2288 __release(&send_cq->lock); 2289 spin_unlock(&recv_cq->lock); 2290 } else { 2291 __release(&recv_cq->lock); 2292 __release(&send_cq->lock); 2293 } 2294 } 2295 2296 static void get_cqs(enum ib_qp_type qp_type, 2297 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2298 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2299 { 2300 switch (qp_type) { 2301 case IB_QPT_XRC_TGT: 2302 *send_cq = NULL; 2303 *recv_cq = NULL; 2304 break; 2305 case MLX5_IB_QPT_REG_UMR: 2306 case IB_QPT_XRC_INI: 2307 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2308 *recv_cq = NULL; 2309 break; 2310 2311 case IB_QPT_SMI: 2312 case MLX5_IB_QPT_HW_GSI: 2313 case IB_QPT_RC: 2314 case IB_QPT_UC: 2315 case IB_QPT_UD: 2316 case IB_QPT_RAW_PACKET: 2317 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2318 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2319 break; 2320 default: 2321 *send_cq = NULL; 2322 *recv_cq = NULL; 2323 break; 2324 } 2325 } 2326 2327 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2328 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2329 u8 lag_tx_affinity); 2330 2331 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2332 struct ib_udata *udata) 2333 { 2334 struct mlx5_ib_cq *send_cq, *recv_cq; 2335 struct mlx5_ib_qp_base *base; 2336 unsigned long flags; 2337 int err; 2338 2339 if (qp->is_rss) { 2340 destroy_rss_raw_qp_tir(dev, qp); 2341 return; 2342 } 2343 2344 base = (qp->type == IB_QPT_RAW_PACKET || 2345 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2346 &qp->raw_packet_qp.rq.base : 2347 &qp->trans_qp.base; 2348 2349 if (qp->state != IB_QPS_RESET) { 2350 if (qp->type != IB_QPT_RAW_PACKET && 2351 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2352 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2353 NULL, &base->mqp, NULL); 2354 } else { 2355 struct mlx5_modify_raw_qp_param raw_qp_param = { 2356 .operation = MLX5_CMD_OP_2RST_QP 2357 }; 2358 2359 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2360 } 2361 if (err) 2362 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2363 base->mqp.qpn); 2364 } 2365 2366 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2367 &recv_cq); 2368 2369 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2370 mlx5_ib_lock_cqs(send_cq, recv_cq); 2371 /* del from lists under both locks above to protect reset flow paths */ 2372 list_del(&qp->qps_list); 2373 if (send_cq) 2374 list_del(&qp->cq_send_list); 2375 2376 if (recv_cq) 2377 list_del(&qp->cq_recv_list); 2378 2379 if (!udata) { 2380 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2381 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2382 if (send_cq != recv_cq) 2383 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2384 NULL); 2385 } 2386 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2387 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2388 2389 if (qp->type == IB_QPT_RAW_PACKET || 2390 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2391 destroy_raw_packet_qp(dev, qp); 2392 } else { 2393 err = mlx5_core_destroy_qp(dev, &base->mqp); 2394 if (err) 2395 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2396 base->mqp.qpn); 2397 } 2398 2399 destroy_qp(dev, qp, base, udata); 2400 } 2401 2402 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2403 struct mlx5_ib_qp *qp, 2404 struct mlx5_create_qp_params *params) 2405 { 2406 struct ib_qp_init_attr *attr = params->attr; 2407 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2408 u32 uidx = params->uidx; 2409 void *dctc; 2410 2411 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2412 if (!qp->dct.in) 2413 return -ENOMEM; 2414 2415 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2416 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2417 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2418 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2419 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2420 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2421 MLX5_SET(dctc, dctc, user_index, uidx); 2422 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2423 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2424 2425 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2426 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2427 2428 if (rcqe_sz == 128) 2429 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2430 } 2431 2432 qp->state = IB_QPS_RESET; 2433 2434 return 0; 2435 } 2436 2437 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2438 enum ib_qp_type *type) 2439 { 2440 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2441 goto out; 2442 2443 switch (attr->qp_type) { 2444 case IB_QPT_XRC_TGT: 2445 case IB_QPT_XRC_INI: 2446 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2447 goto out; 2448 fallthrough; 2449 case IB_QPT_RC: 2450 case IB_QPT_UC: 2451 case IB_QPT_SMI: 2452 case MLX5_IB_QPT_HW_GSI: 2453 case IB_QPT_DRIVER: 2454 case IB_QPT_GSI: 2455 if (dev->profile == &raw_eth_profile) 2456 goto out; 2457 case IB_QPT_RAW_PACKET: 2458 case IB_QPT_UD: 2459 case MLX5_IB_QPT_REG_UMR: 2460 break; 2461 default: 2462 goto out; 2463 } 2464 2465 *type = attr->qp_type; 2466 return 0; 2467 2468 out: 2469 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2470 return -EOPNOTSUPP; 2471 } 2472 2473 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2474 struct ib_qp_init_attr *attr, 2475 struct ib_udata *udata) 2476 { 2477 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2478 udata, struct mlx5_ib_ucontext, ibucontext); 2479 2480 if (!udata) { 2481 /* Kernel create_qp callers */ 2482 if (attr->rwq_ind_tbl) 2483 return -EOPNOTSUPP; 2484 2485 switch (attr->qp_type) { 2486 case IB_QPT_RAW_PACKET: 2487 case IB_QPT_DRIVER: 2488 return -EOPNOTSUPP; 2489 default: 2490 return 0; 2491 } 2492 } 2493 2494 /* Userspace create_qp callers */ 2495 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2496 mlx5_ib_dbg(dev, 2497 "Raw Packet QP is only supported for CQE version > 0\n"); 2498 return -EINVAL; 2499 } 2500 2501 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2502 mlx5_ib_dbg(dev, 2503 "Wrong QP type %d for the RWQ indirect table\n", 2504 attr->qp_type); 2505 return -EINVAL; 2506 } 2507 2508 switch (attr->qp_type) { 2509 case IB_QPT_SMI: 2510 case MLX5_IB_QPT_HW_GSI: 2511 case MLX5_IB_QPT_REG_UMR: 2512 case IB_QPT_GSI: 2513 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n", 2514 attr->qp_type); 2515 return -EINVAL; 2516 default: 2517 break; 2518 } 2519 2520 /* 2521 * We don't need to see this warning, it means that kernel code 2522 * missing ib_pd. Placed here to catch developer's mistakes. 2523 */ 2524 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2525 "There is a missing PD pointer assignment\n"); 2526 return 0; 2527 } 2528 2529 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2530 bool cond, struct mlx5_ib_qp *qp) 2531 { 2532 if (!(*flags & flag)) 2533 return; 2534 2535 if (cond) { 2536 qp->flags_en |= flag; 2537 *flags &= ~flag; 2538 return; 2539 } 2540 2541 switch (flag) { 2542 case MLX5_QP_FLAG_SCATTER_CQE: 2543 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2544 /* 2545 * We don't return error if these flags were provided, 2546 * and mlx5 doesn't have right capability. 2547 */ 2548 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2549 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2550 return; 2551 default: 2552 break; 2553 } 2554 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2555 } 2556 2557 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2558 void *ucmd, struct ib_qp_init_attr *attr) 2559 { 2560 struct mlx5_core_dev *mdev = dev->mdev; 2561 bool cond; 2562 int flags; 2563 2564 if (attr->rwq_ind_tbl) 2565 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2566 else 2567 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2568 2569 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2570 case MLX5_QP_FLAG_TYPE_DCI: 2571 qp->type = MLX5_IB_QPT_DCI; 2572 break; 2573 case MLX5_QP_FLAG_TYPE_DCT: 2574 qp->type = MLX5_IB_QPT_DCT; 2575 break; 2576 default: 2577 if (qp->type != IB_QPT_DRIVER) 2578 break; 2579 /* 2580 * It is IB_QPT_DRIVER and or no subtype or 2581 * wrong subtype were provided. 2582 */ 2583 return -EINVAL; 2584 } 2585 2586 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2587 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2588 2589 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2590 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2591 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2592 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2593 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2594 2595 if (qp->type == IB_QPT_RAW_PACKET) { 2596 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2597 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2598 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2599 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2600 cond, qp); 2601 process_vendor_flag(dev, &flags, 2602 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2603 qp); 2604 process_vendor_flag(dev, &flags, 2605 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2606 qp); 2607 } 2608 2609 if (qp->type == IB_QPT_RC) 2610 process_vendor_flag(dev, &flags, 2611 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2612 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2613 2614 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2615 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2616 2617 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2618 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2619 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2620 if (attr->rwq_ind_tbl && cond) { 2621 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2622 cond); 2623 return -EINVAL; 2624 } 2625 2626 if (flags) 2627 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2628 2629 return (flags) ? -EINVAL : 0; 2630 } 2631 2632 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2633 bool cond, struct mlx5_ib_qp *qp) 2634 { 2635 if (!(*flags & flag)) 2636 return; 2637 2638 if (cond) { 2639 qp->flags |= flag; 2640 *flags &= ~flag; 2641 return; 2642 } 2643 2644 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2645 /* 2646 * Special case, if condition didn't meet, it won't be error, 2647 * just different in-kernel flow. 2648 */ 2649 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2650 return; 2651 } 2652 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2653 } 2654 2655 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2656 struct ib_qp_init_attr *attr) 2657 { 2658 enum ib_qp_type qp_type = qp->type; 2659 struct mlx5_core_dev *mdev = dev->mdev; 2660 int create_flags = attr->create_flags; 2661 bool cond; 2662 2663 if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile) 2664 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST) 2665 return -EINVAL; 2666 2667 if (qp_type == MLX5_IB_QPT_DCT) 2668 return (create_flags) ? -EINVAL : 0; 2669 2670 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2671 return (create_flags) ? -EINVAL : 0; 2672 2673 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2674 mlx5_get_flow_namespace(dev->mdev, 2675 MLX5_FLOW_NAMESPACE_BYPASS), 2676 qp); 2677 process_create_flag(dev, &create_flags, 2678 IB_QP_CREATE_INTEGRITY_EN, 2679 MLX5_CAP_GEN(mdev, sho), qp); 2680 process_create_flag(dev, &create_flags, 2681 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2682 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2683 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2684 MLX5_CAP_GEN(mdev, cd), qp); 2685 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2686 MLX5_CAP_GEN(mdev, cd), qp); 2687 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2688 MLX5_CAP_GEN(mdev, cd), qp); 2689 2690 if (qp_type == IB_QPT_UD) { 2691 process_create_flag(dev, &create_flags, 2692 IB_QP_CREATE_IPOIB_UD_LSO, 2693 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2694 qp); 2695 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2696 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 2697 cond, qp); 2698 } 2699 2700 if (qp_type == IB_QPT_RAW_PACKET) { 2701 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2702 MLX5_CAP_ETH(mdev, scatter_fcs); 2703 process_create_flag(dev, &create_flags, 2704 IB_QP_CREATE_SCATTER_FCS, cond, qp); 2705 2706 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2707 MLX5_CAP_ETH(mdev, vlan_cap); 2708 process_create_flag(dev, &create_flags, 2709 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 2710 } 2711 2712 process_create_flag(dev, &create_flags, 2713 IB_QP_CREATE_PCI_WRITE_END_PADDING, 2714 MLX5_CAP_GEN(mdev, end_pad), qp); 2715 2716 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 2717 qp_type != MLX5_IB_QPT_REG_UMR, qp); 2718 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 2719 true, qp); 2720 2721 if (create_flags) 2722 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 2723 create_flags); 2724 2725 return (create_flags) ? -EINVAL : 0; 2726 } 2727 2728 static int process_udata_size(struct mlx5_ib_dev *dev, 2729 struct mlx5_create_qp_params *params) 2730 { 2731 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 2732 struct ib_udata *udata = params->udata; 2733 size_t outlen = udata->outlen; 2734 size_t inlen = udata->inlen; 2735 2736 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 2737 params->ucmd_size = ucmd; 2738 if (!params->is_rss_raw) { 2739 /* User has old rdma-core, which doesn't support ECE */ 2740 size_t min_inlen = 2741 offsetof(struct mlx5_ib_create_qp, ece_options); 2742 2743 /* 2744 * We will check in check_ucmd_data() that user 2745 * cleared everything after inlen. 2746 */ 2747 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 2748 goto out; 2749 } 2750 2751 /* RSS RAW QP */ 2752 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 2753 return -EINVAL; 2754 2755 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 2756 return -EINVAL; 2757 2758 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 2759 params->ucmd_size = ucmd; 2760 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 2761 return -EINVAL; 2762 2763 params->inlen = min(ucmd, inlen); 2764 out: 2765 if (!params->inlen) 2766 mlx5_ib_dbg(dev, "udata is too small\n"); 2767 2768 return (params->inlen) ? 0 : -EINVAL; 2769 } 2770 2771 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2772 struct mlx5_ib_qp *qp, 2773 struct mlx5_create_qp_params *params) 2774 { 2775 int err; 2776 2777 if (params->is_rss_raw) { 2778 err = create_rss_raw_qp_tir(dev, pd, qp, params); 2779 goto out; 2780 } 2781 2782 if (qp->type == MLX5_IB_QPT_DCT) { 2783 err = create_dct(dev, pd, qp, params); 2784 goto out; 2785 } 2786 2787 if (qp->type == IB_QPT_XRC_TGT) { 2788 err = create_xrc_tgt_qp(dev, qp, params); 2789 goto out; 2790 } 2791 2792 if (params->udata) 2793 err = create_user_qp(dev, pd, qp, params); 2794 else 2795 err = create_kernel_qp(dev, pd, qp, params); 2796 2797 out: 2798 if (err) { 2799 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 2800 return err; 2801 } 2802 2803 if (is_qp0(qp->type)) 2804 qp->ibqp.qp_num = 0; 2805 else if (is_qp1(qp->type)) 2806 qp->ibqp.qp_num = 1; 2807 else 2808 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2809 2810 mlx5_ib_dbg(dev, 2811 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 2812 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2813 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 2814 -1, 2815 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 2816 -1, 2817 params->resp.ece_options); 2818 2819 return 0; 2820 } 2821 2822 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2823 struct ib_qp_init_attr *attr) 2824 { 2825 int ret = 0; 2826 2827 switch (qp->type) { 2828 case MLX5_IB_QPT_DCT: 2829 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 2830 break; 2831 case MLX5_IB_QPT_DCI: 2832 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 2833 -EINVAL : 2834 0; 2835 break; 2836 case IB_QPT_RAW_PACKET: 2837 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 2838 break; 2839 default: 2840 break; 2841 } 2842 2843 if (ret) 2844 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 2845 2846 return ret; 2847 } 2848 2849 static int get_qp_uidx(struct mlx5_ib_qp *qp, 2850 struct mlx5_create_qp_params *params) 2851 { 2852 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2853 struct ib_udata *udata = params->udata; 2854 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2855 udata, struct mlx5_ib_ucontext, ibucontext); 2856 2857 if (params->is_rss_raw) 2858 return 0; 2859 2860 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 2861 } 2862 2863 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2864 { 2865 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2866 2867 if (mqp->state == IB_QPS_RTR) { 2868 int err; 2869 2870 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 2871 if (err) { 2872 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2873 return err; 2874 } 2875 } 2876 2877 kfree(mqp->dct.in); 2878 kfree(mqp); 2879 return 0; 2880 } 2881 2882 static int check_ucmd_data(struct mlx5_ib_dev *dev, 2883 struct mlx5_create_qp_params *params) 2884 { 2885 struct ib_udata *udata = params->udata; 2886 size_t size, last; 2887 int ret; 2888 2889 if (params->is_rss_raw) 2890 /* 2891 * These QPs don't have "reserved" field in their 2892 * create_qp input struct, so their data is always valid. 2893 */ 2894 last = sizeof(struct mlx5_ib_create_qp_rss); 2895 else 2896 last = offsetof(struct mlx5_ib_create_qp, reserved); 2897 2898 if (udata->inlen <= last) 2899 return 0; 2900 2901 /* 2902 * User provides different create_qp structures based on the 2903 * flow and we need to know if he cleared memory after our 2904 * struct create_qp ends. 2905 */ 2906 size = udata->inlen - last; 2907 ret = ib_is_udata_cleared(params->udata, last, size); 2908 if (!ret) 2909 mlx5_ib_dbg( 2910 dev, 2911 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 2912 udata->inlen, params->ucmd_size, last, size); 2913 return ret ? 0 : -EINVAL; 2914 } 2915 2916 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr, 2917 struct ib_udata *udata) 2918 { 2919 struct mlx5_create_qp_params params = {}; 2920 struct mlx5_ib_dev *dev; 2921 struct mlx5_ib_qp *qp; 2922 enum ib_qp_type type; 2923 int err; 2924 2925 dev = pd ? to_mdev(pd->device) : 2926 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device); 2927 2928 err = check_qp_type(dev, attr, &type); 2929 if (err) 2930 return ERR_PTR(err); 2931 2932 err = check_valid_flow(dev, pd, attr, udata); 2933 if (err) 2934 return ERR_PTR(err); 2935 2936 if (attr->qp_type == IB_QPT_GSI) 2937 return mlx5_ib_gsi_create_qp(pd, attr); 2938 2939 params.udata = udata; 2940 params.uidx = MLX5_IB_DEFAULT_UIDX; 2941 params.attr = attr; 2942 params.is_rss_raw = !!attr->rwq_ind_tbl; 2943 2944 if (udata) { 2945 err = process_udata_size(dev, ¶ms); 2946 if (err) 2947 return ERR_PTR(err); 2948 2949 err = check_ucmd_data(dev, ¶ms); 2950 if (err) 2951 return ERR_PTR(err); 2952 2953 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 2954 if (!params.ucmd) 2955 return ERR_PTR(-ENOMEM); 2956 2957 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 2958 if (err) 2959 goto free_ucmd; 2960 } 2961 2962 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2963 if (!qp) { 2964 err = -ENOMEM; 2965 goto free_ucmd; 2966 } 2967 2968 mutex_init(&qp->mutex); 2969 qp->type = type; 2970 if (udata) { 2971 err = process_vendor_flags(dev, qp, params.ucmd, attr); 2972 if (err) 2973 goto free_qp; 2974 2975 err = get_qp_uidx(qp, ¶ms); 2976 if (err) 2977 goto free_qp; 2978 } 2979 err = process_create_flags(dev, qp, attr); 2980 if (err) 2981 goto free_qp; 2982 2983 err = check_qp_attr(dev, qp, attr); 2984 if (err) 2985 goto free_qp; 2986 2987 err = create_qp(dev, pd, qp, ¶ms); 2988 if (err) 2989 goto free_qp; 2990 2991 kfree(params.ucmd); 2992 params.ucmd = NULL; 2993 2994 if (udata) 2995 /* 2996 * It is safe to copy response for all user create QP flows, 2997 * including MLX5_IB_QPT_DCT, which doesn't need it. 2998 * In that case, resp will be filled with zeros. 2999 */ 3000 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3001 if (err) 3002 goto destroy_qp; 3003 3004 return &qp->ibqp; 3005 3006 destroy_qp: 3007 if (qp->type == MLX5_IB_QPT_DCT) { 3008 mlx5_ib_destroy_dct(qp); 3009 } else { 3010 /* 3011 * These lines below are temp solution till QP allocation 3012 * will be moved to be under IB/core responsiblity. 3013 */ 3014 qp->ibqp.send_cq = attr->send_cq; 3015 qp->ibqp.recv_cq = attr->recv_cq; 3016 qp->ibqp.pd = pd; 3017 destroy_qp_common(dev, qp, udata); 3018 } 3019 3020 qp = NULL; 3021 free_qp: 3022 kfree(qp); 3023 free_ucmd: 3024 kfree(params.ucmd); 3025 return ERR_PTR(err); 3026 } 3027 3028 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3029 { 3030 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3031 struct mlx5_ib_qp *mqp = to_mqp(qp); 3032 3033 if (unlikely(qp->qp_type == IB_QPT_GSI)) 3034 return mlx5_ib_gsi_destroy_qp(qp); 3035 3036 if (mqp->type == MLX5_IB_QPT_DCT) 3037 return mlx5_ib_destroy_dct(mqp); 3038 3039 destroy_qp_common(dev, mqp, udata); 3040 3041 kfree(mqp); 3042 3043 return 0; 3044 } 3045 3046 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3047 const struct ib_qp_attr *attr, int attr_mask, 3048 void *qpc) 3049 { 3050 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3051 u8 dest_rd_atomic; 3052 u32 access_flags; 3053 3054 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3055 dest_rd_atomic = attr->max_dest_rd_atomic; 3056 else 3057 dest_rd_atomic = qp->trans_qp.resp_depth; 3058 3059 if (attr_mask & IB_QP_ACCESS_FLAGS) 3060 access_flags = attr->qp_access_flags; 3061 else 3062 access_flags = qp->trans_qp.atomic_rd_en; 3063 3064 if (!dest_rd_atomic) 3065 access_flags &= IB_ACCESS_REMOTE_WRITE; 3066 3067 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3068 3069 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3070 int atomic_mode; 3071 3072 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 3073 if (atomic_mode < 0) 3074 return -EOPNOTSUPP; 3075 3076 MLX5_SET(qpc, qpc, rae, 1); 3077 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3078 } 3079 3080 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3081 return 0; 3082 } 3083 3084 enum { 3085 MLX5_PATH_FLAG_FL = 1 << 0, 3086 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3087 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3088 }; 3089 3090 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3091 { 3092 if (rate == IB_RATE_PORT_CURRENT) 3093 return 0; 3094 3095 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3096 return -EINVAL; 3097 3098 while (rate != IB_RATE_PORT_CURRENT && 3099 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 3100 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 3101 --rate; 3102 3103 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 3104 } 3105 3106 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3107 struct mlx5_ib_sq *sq, u8 sl, 3108 struct ib_pd *pd) 3109 { 3110 void *in; 3111 void *tisc; 3112 int inlen; 3113 int err; 3114 3115 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3116 in = kvzalloc(inlen, GFP_KERNEL); 3117 if (!in) 3118 return -ENOMEM; 3119 3120 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3121 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3122 3123 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3124 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3125 3126 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3127 3128 kvfree(in); 3129 3130 return err; 3131 } 3132 3133 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3134 struct mlx5_ib_sq *sq, u8 tx_affinity, 3135 struct ib_pd *pd) 3136 { 3137 void *in; 3138 void *tisc; 3139 int inlen; 3140 int err; 3141 3142 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3143 in = kvzalloc(inlen, GFP_KERNEL); 3144 if (!in) 3145 return -ENOMEM; 3146 3147 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3148 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3149 3150 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3151 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3152 3153 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3154 3155 kvfree(in); 3156 3157 return err; 3158 } 3159 3160 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3161 u32 lqpn, u32 rqpn) 3162 3163 { 3164 u32 fl = ah->grh.flow_label; 3165 3166 if (!fl) 3167 fl = rdma_calc_flow_label(lqpn, rqpn); 3168 3169 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3170 } 3171 3172 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3173 const struct rdma_ah_attr *ah, void *path, u8 port, 3174 int attr_mask, u32 path_flags, 3175 const struct ib_qp_attr *attr, bool alt) 3176 { 3177 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3178 int err; 3179 enum ib_gid_type gid_type; 3180 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3181 u8 sl = rdma_ah_get_sl(ah); 3182 3183 if (attr_mask & IB_QP_PKEY_INDEX) 3184 MLX5_SET(ads, path, pkey_index, 3185 alt ? attr->alt_pkey_index : attr->pkey_index); 3186 3187 if (ah_flags & IB_AH_GRH) { 3188 if (grh->sgid_index >= 3189 dev->mdev->port_caps[port - 1].gid_table_len) { 3190 pr_err("sgid_index (%u) too large. max is %d\n", 3191 grh->sgid_index, 3192 dev->mdev->port_caps[port - 1].gid_table_len); 3193 return -EINVAL; 3194 } 3195 } 3196 3197 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3198 if (!(ah_flags & IB_AH_GRH)) 3199 return -EINVAL; 3200 3201 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3202 ah->roce.dmac); 3203 if ((qp->ibqp.qp_type == IB_QPT_RC || 3204 qp->ibqp.qp_type == IB_QPT_UC || 3205 qp->ibqp.qp_type == IB_QPT_XRC_INI || 3206 qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 3207 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3208 (attr_mask & IB_QP_DEST_QPN)) 3209 mlx5_set_path_udp_sport(path, ah, 3210 qp->ibqp.qp_num, 3211 attr->dest_qp_num); 3212 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3213 gid_type = ah->grh.sgid_attr->gid_type; 3214 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3215 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3216 } else { 3217 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3218 MLX5_SET(ads, path, free_ar, 3219 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3220 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3221 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3222 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3223 MLX5_SET(ads, path, sl, sl); 3224 } 3225 3226 if (ah_flags & IB_AH_GRH) { 3227 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3228 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3229 MLX5_SET(ads, path, tclass, grh->traffic_class); 3230 MLX5_SET(ads, path, flow_label, grh->flow_label); 3231 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3232 sizeof(grh->dgid.raw)); 3233 } 3234 3235 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3236 if (err < 0) 3237 return err; 3238 MLX5_SET(ads, path, stat_rate, err); 3239 MLX5_SET(ads, path, vhca_port_num, port); 3240 3241 if (attr_mask & IB_QP_TIMEOUT) 3242 MLX5_SET(ads, path, ack_timeout, 3243 alt ? attr->alt_timeout : attr->timeout); 3244 3245 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3246 return modify_raw_packet_eth_prio(dev->mdev, 3247 &qp->raw_packet_qp.sq, 3248 sl & 0xf, qp->ibqp.pd); 3249 3250 return 0; 3251 } 3252 3253 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3254 [MLX5_QP_STATE_INIT] = { 3255 [MLX5_QP_STATE_INIT] = { 3256 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3257 MLX5_QP_OPTPAR_RAE | 3258 MLX5_QP_OPTPAR_RWE | 3259 MLX5_QP_OPTPAR_PKEY_INDEX | 3260 MLX5_QP_OPTPAR_PRI_PORT | 3261 MLX5_QP_OPTPAR_LAG_TX_AFF, 3262 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3263 MLX5_QP_OPTPAR_PKEY_INDEX | 3264 MLX5_QP_OPTPAR_PRI_PORT | 3265 MLX5_QP_OPTPAR_LAG_TX_AFF, 3266 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3267 MLX5_QP_OPTPAR_Q_KEY | 3268 MLX5_QP_OPTPAR_PRI_PORT, 3269 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3270 MLX5_QP_OPTPAR_RAE | 3271 MLX5_QP_OPTPAR_RWE | 3272 MLX5_QP_OPTPAR_PKEY_INDEX | 3273 MLX5_QP_OPTPAR_PRI_PORT | 3274 MLX5_QP_OPTPAR_LAG_TX_AFF, 3275 }, 3276 [MLX5_QP_STATE_RTR] = { 3277 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3278 MLX5_QP_OPTPAR_RRE | 3279 MLX5_QP_OPTPAR_RAE | 3280 MLX5_QP_OPTPAR_RWE | 3281 MLX5_QP_OPTPAR_PKEY_INDEX | 3282 MLX5_QP_OPTPAR_LAG_TX_AFF, 3283 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3284 MLX5_QP_OPTPAR_RWE | 3285 MLX5_QP_OPTPAR_PKEY_INDEX | 3286 MLX5_QP_OPTPAR_LAG_TX_AFF, 3287 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3288 MLX5_QP_OPTPAR_Q_KEY, 3289 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3290 MLX5_QP_OPTPAR_Q_KEY, 3291 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3292 MLX5_QP_OPTPAR_RRE | 3293 MLX5_QP_OPTPAR_RAE | 3294 MLX5_QP_OPTPAR_RWE | 3295 MLX5_QP_OPTPAR_PKEY_INDEX | 3296 MLX5_QP_OPTPAR_LAG_TX_AFF, 3297 }, 3298 }, 3299 [MLX5_QP_STATE_RTR] = { 3300 [MLX5_QP_STATE_RTS] = { 3301 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3302 MLX5_QP_OPTPAR_RRE | 3303 MLX5_QP_OPTPAR_RAE | 3304 MLX5_QP_OPTPAR_RWE | 3305 MLX5_QP_OPTPAR_PM_STATE | 3306 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3307 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3308 MLX5_QP_OPTPAR_RWE | 3309 MLX5_QP_OPTPAR_PM_STATE, 3310 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3311 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3312 MLX5_QP_OPTPAR_RRE | 3313 MLX5_QP_OPTPAR_RAE | 3314 MLX5_QP_OPTPAR_RWE | 3315 MLX5_QP_OPTPAR_PM_STATE | 3316 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3317 }, 3318 }, 3319 [MLX5_QP_STATE_RTS] = { 3320 [MLX5_QP_STATE_RTS] = { 3321 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3322 MLX5_QP_OPTPAR_RAE | 3323 MLX5_QP_OPTPAR_RWE | 3324 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3325 MLX5_QP_OPTPAR_PM_STATE | 3326 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3327 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3328 MLX5_QP_OPTPAR_PM_STATE | 3329 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3330 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3331 MLX5_QP_OPTPAR_SRQN | 3332 MLX5_QP_OPTPAR_CQN_RCV, 3333 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3334 MLX5_QP_OPTPAR_RAE | 3335 MLX5_QP_OPTPAR_RWE | 3336 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3337 MLX5_QP_OPTPAR_PM_STATE | 3338 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3339 }, 3340 }, 3341 [MLX5_QP_STATE_SQER] = { 3342 [MLX5_QP_STATE_RTS] = { 3343 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3344 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3345 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3346 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3347 MLX5_QP_OPTPAR_RWE | 3348 MLX5_QP_OPTPAR_RAE | 3349 MLX5_QP_OPTPAR_RRE, 3350 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3351 MLX5_QP_OPTPAR_RWE | 3352 MLX5_QP_OPTPAR_RAE | 3353 MLX5_QP_OPTPAR_RRE, 3354 }, 3355 }, 3356 }; 3357 3358 static int ib_nr_to_mlx5_nr(int ib_mask) 3359 { 3360 switch (ib_mask) { 3361 case IB_QP_STATE: 3362 return 0; 3363 case IB_QP_CUR_STATE: 3364 return 0; 3365 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3366 return 0; 3367 case IB_QP_ACCESS_FLAGS: 3368 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3369 MLX5_QP_OPTPAR_RAE; 3370 case IB_QP_PKEY_INDEX: 3371 return MLX5_QP_OPTPAR_PKEY_INDEX; 3372 case IB_QP_PORT: 3373 return MLX5_QP_OPTPAR_PRI_PORT; 3374 case IB_QP_QKEY: 3375 return MLX5_QP_OPTPAR_Q_KEY; 3376 case IB_QP_AV: 3377 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3378 MLX5_QP_OPTPAR_PRI_PORT; 3379 case IB_QP_PATH_MTU: 3380 return 0; 3381 case IB_QP_TIMEOUT: 3382 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3383 case IB_QP_RETRY_CNT: 3384 return MLX5_QP_OPTPAR_RETRY_COUNT; 3385 case IB_QP_RNR_RETRY: 3386 return MLX5_QP_OPTPAR_RNR_RETRY; 3387 case IB_QP_RQ_PSN: 3388 return 0; 3389 case IB_QP_MAX_QP_RD_ATOMIC: 3390 return MLX5_QP_OPTPAR_SRA_MAX; 3391 case IB_QP_ALT_PATH: 3392 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3393 case IB_QP_MIN_RNR_TIMER: 3394 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3395 case IB_QP_SQ_PSN: 3396 return 0; 3397 case IB_QP_MAX_DEST_RD_ATOMIC: 3398 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3399 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3400 case IB_QP_PATH_MIG_STATE: 3401 return MLX5_QP_OPTPAR_PM_STATE; 3402 case IB_QP_CAP: 3403 return 0; 3404 case IB_QP_DEST_QPN: 3405 return 0; 3406 } 3407 return 0; 3408 } 3409 3410 static int ib_mask_to_mlx5_opt(int ib_mask) 3411 { 3412 int result = 0; 3413 int i; 3414 3415 for (i = 0; i < 8 * sizeof(int); i++) { 3416 if ((1 << i) & ib_mask) 3417 result |= ib_nr_to_mlx5_nr(1 << i); 3418 } 3419 3420 return result; 3421 } 3422 3423 static int modify_raw_packet_qp_rq( 3424 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3425 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3426 { 3427 void *in; 3428 void *rqc; 3429 int inlen; 3430 int err; 3431 3432 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3433 in = kvzalloc(inlen, GFP_KERNEL); 3434 if (!in) 3435 return -ENOMEM; 3436 3437 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3438 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3439 3440 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3441 MLX5_SET(rqc, rqc, state, new_state); 3442 3443 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3444 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3445 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3446 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3447 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3448 } else 3449 dev_info_once( 3450 &dev->ib_dev.dev, 3451 "RAW PACKET QP counters are not supported on current FW\n"); 3452 } 3453 3454 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3455 if (err) 3456 goto out; 3457 3458 rq->state = new_state; 3459 3460 out: 3461 kvfree(in); 3462 return err; 3463 } 3464 3465 static int modify_raw_packet_qp_sq( 3466 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3467 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3468 { 3469 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3470 struct mlx5_rate_limit old_rl = ibqp->rl; 3471 struct mlx5_rate_limit new_rl = old_rl; 3472 bool new_rate_added = false; 3473 u16 rl_index = 0; 3474 void *in; 3475 void *sqc; 3476 int inlen; 3477 int err; 3478 3479 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3480 in = kvzalloc(inlen, GFP_KERNEL); 3481 if (!in) 3482 return -ENOMEM; 3483 3484 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3485 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3486 3487 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3488 MLX5_SET(sqc, sqc, state, new_state); 3489 3490 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3491 if (new_state != MLX5_SQC_STATE_RDY) 3492 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3493 __func__); 3494 else 3495 new_rl = raw_qp_param->rl; 3496 } 3497 3498 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3499 if (new_rl.rate) { 3500 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3501 if (err) { 3502 pr_err("Failed configuring rate limit(err %d): \ 3503 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3504 err, new_rl.rate, new_rl.max_burst_sz, 3505 new_rl.typical_pkt_sz); 3506 3507 goto out; 3508 } 3509 new_rate_added = true; 3510 } 3511 3512 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3513 /* index 0 means no limit */ 3514 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3515 } 3516 3517 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3518 if (err) { 3519 /* Remove new rate from table if failed */ 3520 if (new_rate_added) 3521 mlx5_rl_remove_rate(dev, &new_rl); 3522 goto out; 3523 } 3524 3525 /* Only remove the old rate after new rate was set */ 3526 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3527 (new_state != MLX5_SQC_STATE_RDY)) { 3528 mlx5_rl_remove_rate(dev, &old_rl); 3529 if (new_state != MLX5_SQC_STATE_RDY) 3530 memset(&new_rl, 0, sizeof(new_rl)); 3531 } 3532 3533 ibqp->rl = new_rl; 3534 sq->state = new_state; 3535 3536 out: 3537 kvfree(in); 3538 return err; 3539 } 3540 3541 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3542 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3543 u8 tx_affinity) 3544 { 3545 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3546 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3547 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3548 int modify_rq = !!qp->rq.wqe_cnt; 3549 int modify_sq = !!qp->sq.wqe_cnt; 3550 int rq_state; 3551 int sq_state; 3552 int err; 3553 3554 switch (raw_qp_param->operation) { 3555 case MLX5_CMD_OP_RST2INIT_QP: 3556 rq_state = MLX5_RQC_STATE_RDY; 3557 sq_state = MLX5_SQC_STATE_RDY; 3558 break; 3559 case MLX5_CMD_OP_2ERR_QP: 3560 rq_state = MLX5_RQC_STATE_ERR; 3561 sq_state = MLX5_SQC_STATE_ERR; 3562 break; 3563 case MLX5_CMD_OP_2RST_QP: 3564 rq_state = MLX5_RQC_STATE_RST; 3565 sq_state = MLX5_SQC_STATE_RST; 3566 break; 3567 case MLX5_CMD_OP_RTR2RTS_QP: 3568 case MLX5_CMD_OP_RTS2RTS_QP: 3569 if (raw_qp_param->set_mask == 3570 MLX5_RAW_QP_RATE_LIMIT) { 3571 modify_rq = 0; 3572 sq_state = sq->state; 3573 } else { 3574 return raw_qp_param->set_mask ? -EINVAL : 0; 3575 } 3576 break; 3577 case MLX5_CMD_OP_INIT2INIT_QP: 3578 case MLX5_CMD_OP_INIT2RTR_QP: 3579 if (raw_qp_param->set_mask) 3580 return -EINVAL; 3581 else 3582 return 0; 3583 default: 3584 WARN_ON(1); 3585 return -EINVAL; 3586 } 3587 3588 if (modify_rq) { 3589 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3590 qp->ibqp.pd); 3591 if (err) 3592 return err; 3593 } 3594 3595 if (modify_sq) { 3596 struct mlx5_flow_handle *flow_rule; 3597 3598 if (tx_affinity) { 3599 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3600 tx_affinity, 3601 qp->ibqp.pd); 3602 if (err) 3603 return err; 3604 } 3605 3606 flow_rule = create_flow_rule_vport_sq(dev, sq, 3607 raw_qp_param->port); 3608 if (IS_ERR(flow_rule)) 3609 return PTR_ERR(flow_rule); 3610 3611 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3612 raw_qp_param, qp->ibqp.pd); 3613 if (err) { 3614 if (flow_rule) 3615 mlx5_del_flow_rules(flow_rule); 3616 return err; 3617 } 3618 3619 if (flow_rule) { 3620 destroy_flow_rule_vport_sq(sq); 3621 sq->flow_rule = flow_rule; 3622 } 3623 3624 return err; 3625 } 3626 3627 return 0; 3628 } 3629 3630 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3631 struct ib_udata *udata) 3632 { 3633 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3634 udata, struct mlx5_ib_ucontext, ibucontext); 3635 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3636 atomic_t *tx_port_affinity; 3637 3638 if (ucontext) 3639 tx_port_affinity = &ucontext->tx_port_affinity; 3640 else 3641 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3642 3643 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3644 MLX5_MAX_PORTS + 1; 3645 } 3646 3647 static bool qp_supports_affinity(struct ib_qp *qp) 3648 { 3649 if ((qp->qp_type == IB_QPT_RC) || 3650 (qp->qp_type == IB_QPT_UD) || 3651 (qp->qp_type == IB_QPT_UC) || 3652 (qp->qp_type == IB_QPT_RAW_PACKET) || 3653 (qp->qp_type == IB_QPT_XRC_INI) || 3654 (qp->qp_type == IB_QPT_XRC_TGT)) 3655 return true; 3656 return false; 3657 } 3658 3659 static unsigned int get_tx_affinity(struct ib_qp *qp, 3660 const struct ib_qp_attr *attr, 3661 int attr_mask, u8 init, 3662 struct ib_udata *udata) 3663 { 3664 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3665 udata, struct mlx5_ib_ucontext, ibucontext); 3666 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3667 struct mlx5_ib_qp *mqp = to_mqp(qp); 3668 struct mlx5_ib_qp_base *qp_base; 3669 unsigned int tx_affinity; 3670 3671 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 3672 qp_supports_affinity(qp))) 3673 return 0; 3674 3675 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3676 tx_affinity = mqp->gsi_lag_port; 3677 else if (init) 3678 tx_affinity = get_tx_affinity_rr(dev, udata); 3679 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 3680 tx_affinity = 3681 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 3682 else 3683 return 0; 3684 3685 qp_base = &mqp->trans_qp.base; 3686 if (ucontext) 3687 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3688 tx_affinity, qp_base->mqp.qpn, ucontext); 3689 else 3690 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3691 tx_affinity, qp_base->mqp.qpn); 3692 return tx_affinity; 3693 } 3694 3695 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3696 struct rdma_counter *counter) 3697 { 3698 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3699 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 3700 struct mlx5_ib_qp *mqp = to_mqp(qp); 3701 struct mlx5_ib_qp_base *base; 3702 u32 set_id; 3703 u32 *qpc; 3704 3705 if (counter) 3706 set_id = counter->id; 3707 else 3708 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3709 3710 base = &mqp->trans_qp.base; 3711 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 3712 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 3713 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 3714 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 3715 MLX5_QP_OPTPAR_COUNTER_SET_ID); 3716 3717 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 3718 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3719 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 3720 } 3721 3722 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3723 const struct ib_qp_attr *attr, int attr_mask, 3724 enum ib_qp_state cur_state, 3725 enum ib_qp_state new_state, 3726 const struct mlx5_ib_modify_qp *ucmd, 3727 struct mlx5_ib_modify_qp_resp *resp, 3728 struct ib_udata *udata) 3729 { 3730 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3731 [MLX5_QP_STATE_RST] = { 3732 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3733 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3734 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3735 }, 3736 [MLX5_QP_STATE_INIT] = { 3737 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3738 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3739 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3740 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3741 }, 3742 [MLX5_QP_STATE_RTR] = { 3743 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3744 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3745 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3746 }, 3747 [MLX5_QP_STATE_RTS] = { 3748 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3749 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3750 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3751 }, 3752 [MLX5_QP_STATE_SQD] = { 3753 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3754 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3755 }, 3756 [MLX5_QP_STATE_SQER] = { 3757 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3758 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3759 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3760 }, 3761 [MLX5_QP_STATE_ERR] = { 3762 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3763 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3764 } 3765 }; 3766 3767 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3768 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3769 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3770 struct mlx5_ib_cq *send_cq, *recv_cq; 3771 struct mlx5_ib_pd *pd; 3772 enum mlx5_qp_state mlx5_cur, mlx5_new; 3773 void *qpc, *pri_path, *alt_path; 3774 enum mlx5_qp_optpar optpar = 0; 3775 u32 set_id = 0; 3776 int mlx5_st; 3777 int err; 3778 u16 op; 3779 u8 tx_affinity = 0; 3780 3781 mlx5_st = to_mlx5_st(qp->type); 3782 if (mlx5_st < 0) 3783 return -EINVAL; 3784 3785 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 3786 if (!qpc) 3787 return -ENOMEM; 3788 3789 pd = to_mpd(qp->ibqp.pd); 3790 MLX5_SET(qpc, qpc, st, mlx5_st); 3791 3792 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3793 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3794 } else { 3795 switch (attr->path_mig_state) { 3796 case IB_MIG_MIGRATED: 3797 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3798 break; 3799 case IB_MIG_REARM: 3800 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 3801 break; 3802 case IB_MIG_ARMED: 3803 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 3804 break; 3805 } 3806 } 3807 3808 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 3809 cur_state == IB_QPS_RESET && 3810 new_state == IB_QPS_INIT, udata); 3811 3812 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 3813 if (tx_affinity && new_state == IB_QPS_RTR && 3814 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 3815 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 3816 3817 if (is_sqp(ibqp->qp_type)) { 3818 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 3819 MLX5_SET(qpc, qpc, log_msg_max, 8); 3820 } else if ((ibqp->qp_type == IB_QPT_UD && 3821 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 3822 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3823 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 3824 MLX5_SET(qpc, qpc, log_msg_max, 12); 3825 } else if (attr_mask & IB_QP_PATH_MTU) { 3826 if (attr->path_mtu < IB_MTU_256 || 3827 attr->path_mtu > IB_MTU_4096) { 3828 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3829 err = -EINVAL; 3830 goto out; 3831 } 3832 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 3833 MLX5_SET(qpc, qpc, log_msg_max, 3834 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 3835 } 3836 3837 if (attr_mask & IB_QP_DEST_QPN) 3838 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 3839 3840 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 3841 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 3842 3843 if (attr_mask & IB_QP_PKEY_INDEX) 3844 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 3845 3846 /* todo implement counter_index functionality */ 3847 3848 if (is_sqp(ibqp->qp_type)) 3849 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 3850 3851 if (attr_mask & IB_QP_PORT) 3852 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 3853 3854 if (attr_mask & IB_QP_AV) { 3855 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 3856 attr_mask & IB_QP_PORT ? attr->port_num : 3857 qp->port, 3858 attr_mask, 0, attr, false); 3859 if (err) 3860 goto out; 3861 } 3862 3863 if (attr_mask & IB_QP_TIMEOUT) 3864 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 3865 3866 if (attr_mask & IB_QP_ALT_PATH) { 3867 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 3868 attr->alt_port_num, 3869 attr_mask | IB_QP_PKEY_INDEX | 3870 IB_QP_TIMEOUT, 3871 0, attr, true); 3872 if (err) 3873 goto out; 3874 } 3875 3876 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3877 &send_cq, &recv_cq); 3878 3879 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3880 if (send_cq) 3881 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 3882 if (recv_cq) 3883 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 3884 3885 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 3886 3887 if (attr_mask & IB_QP_RNR_RETRY) 3888 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 3889 3890 if (attr_mask & IB_QP_RETRY_CNT) 3891 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 3892 3893 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 3894 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 3895 3896 if (attr_mask & IB_QP_SQ_PSN) 3897 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 3898 3899 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 3900 MLX5_SET(qpc, qpc, log_rra_max, 3901 ilog2(attr->max_dest_rd_atomic)); 3902 3903 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3904 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 3905 if (err) 3906 goto out; 3907 } 3908 3909 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3910 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 3911 3912 if (attr_mask & IB_QP_RQ_PSN) 3913 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 3914 3915 if (attr_mask & IB_QP_QKEY) 3916 MLX5_SET(qpc, qpc, q_key, attr->qkey); 3917 3918 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3919 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 3920 3921 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3922 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3923 qp->port) - 1; 3924 3925 /* Underlay port should be used - index 0 function per port */ 3926 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 3927 port_num = 0; 3928 3929 if (ibqp->counter) 3930 set_id = ibqp->counter->id; 3931 else 3932 set_id = mlx5_ib_get_counters_id(dev, port_num); 3933 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3934 } 3935 3936 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3937 MLX5_SET(qpc, qpc, rlky, 1); 3938 3939 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3940 MLX5_SET(qpc, qpc, deth_sqpn, 1); 3941 3942 mlx5_cur = to_mlx5_state(cur_state); 3943 mlx5_new = to_mlx5_state(new_state); 3944 3945 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3946 !optab[mlx5_cur][mlx5_new]) { 3947 err = -EINVAL; 3948 goto out; 3949 } 3950 3951 op = optab[mlx5_cur][mlx5_new]; 3952 optpar |= ib_mask_to_mlx5_opt(attr_mask); 3953 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3954 3955 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3956 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 3957 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3958 3959 raw_qp_param.operation = op; 3960 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3961 raw_qp_param.rq_q_ctr_id = set_id; 3962 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3963 } 3964 3965 if (attr_mask & IB_QP_PORT) 3966 raw_qp_param.port = attr->port_num; 3967 3968 if (attr_mask & IB_QP_RATE_LIMIT) { 3969 raw_qp_param.rl.rate = attr->rate_limit; 3970 3971 if (ucmd->burst_info.max_burst_sz) { 3972 if (attr->rate_limit && 3973 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3974 raw_qp_param.rl.max_burst_sz = 3975 ucmd->burst_info.max_burst_sz; 3976 } else { 3977 err = -EINVAL; 3978 goto out; 3979 } 3980 } 3981 3982 if (ucmd->burst_info.typical_pkt_sz) { 3983 if (attr->rate_limit && 3984 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3985 raw_qp_param.rl.typical_pkt_sz = 3986 ucmd->burst_info.typical_pkt_sz; 3987 } else { 3988 err = -EINVAL; 3989 goto out; 3990 } 3991 } 3992 3993 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3994 } 3995 3996 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3997 } else { 3998 if (udata) { 3999 /* For the kernel flows, the resp will stay zero */ 4000 resp->ece_options = 4001 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4002 ucmd->ece_options : 0; 4003 resp->response_length = sizeof(*resp); 4004 } 4005 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4006 &resp->ece_options); 4007 } 4008 4009 if (err) 4010 goto out; 4011 4012 qp->state = new_state; 4013 4014 if (attr_mask & IB_QP_ACCESS_FLAGS) 4015 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4016 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4017 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4018 if (attr_mask & IB_QP_PORT) 4019 qp->port = attr->port_num; 4020 if (attr_mask & IB_QP_ALT_PATH) 4021 qp->trans_qp.alt_port = attr->alt_port_num; 4022 4023 /* 4024 * If we moved a kernel QP to RESET, clean up all old CQ 4025 * entries and reinitialize the QP. 4026 */ 4027 if (new_state == IB_QPS_RESET && 4028 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 4029 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4030 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4031 if (send_cq != recv_cq) 4032 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4033 4034 qp->rq.head = 0; 4035 qp->rq.tail = 0; 4036 qp->sq.head = 0; 4037 qp->sq.tail = 0; 4038 qp->sq.cur_post = 0; 4039 if (qp->sq.wqe_cnt) 4040 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4041 qp->sq.last_poll = 0; 4042 qp->db.db[MLX5_RCV_DBR] = 0; 4043 qp->db.db[MLX5_SND_DBR] = 0; 4044 } 4045 4046 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4047 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4048 if (!err) 4049 qp->counter_pending = 0; 4050 } 4051 4052 out: 4053 kfree(qpc); 4054 return err; 4055 } 4056 4057 static inline bool is_valid_mask(int mask, int req, int opt) 4058 { 4059 if ((mask & req) != req) 4060 return false; 4061 4062 if (mask & ~(req | opt)) 4063 return false; 4064 4065 return true; 4066 } 4067 4068 /* check valid transition for driver QP types 4069 * for now the only QP type that this function supports is DCI 4070 */ 4071 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4072 enum ib_qp_attr_mask attr_mask) 4073 { 4074 int req = IB_QP_STATE; 4075 int opt = 0; 4076 4077 if (new_state == IB_QPS_RESET) { 4078 return is_valid_mask(attr_mask, req, opt); 4079 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4080 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4081 return is_valid_mask(attr_mask, req, opt); 4082 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4083 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4084 return is_valid_mask(attr_mask, req, opt); 4085 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4086 req |= IB_QP_PATH_MTU; 4087 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4088 return is_valid_mask(attr_mask, req, opt); 4089 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4090 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4091 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4092 opt = IB_QP_MIN_RNR_TIMER; 4093 return is_valid_mask(attr_mask, req, opt); 4094 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4095 opt = IB_QP_MIN_RNR_TIMER; 4096 return is_valid_mask(attr_mask, req, opt); 4097 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4098 return is_valid_mask(attr_mask, req, opt); 4099 } 4100 return false; 4101 } 4102 4103 /* mlx5_ib_modify_dct: modify a DCT QP 4104 * valid transitions are: 4105 * RESET to INIT: must set access_flags, pkey_index and port 4106 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4107 * mtu, gid_index and hop_limit 4108 * Other transitions and attributes are illegal 4109 */ 4110 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4111 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4112 struct ib_udata *udata) 4113 { 4114 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4115 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4116 enum ib_qp_state cur_state, new_state; 4117 int err = 0; 4118 int required = IB_QP_STATE; 4119 void *dctc; 4120 4121 if (!(attr_mask & IB_QP_STATE)) 4122 return -EINVAL; 4123 4124 cur_state = qp->state; 4125 new_state = attr->qp_state; 4126 4127 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4128 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4129 /* 4130 * DCT doesn't initialize QP till modify command is executed, 4131 * so we need to overwrite previously set ECE field if user 4132 * provided any value except zero, which means not set/not 4133 * valid. 4134 */ 4135 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4136 4137 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4138 u16 set_id; 4139 4140 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4141 if (!is_valid_mask(attr_mask, required, 0)) 4142 return -EINVAL; 4143 4144 if (attr->port_num == 0 || 4145 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4146 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4147 attr->port_num, dev->num_ports); 4148 return -EINVAL; 4149 } 4150 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4151 MLX5_SET(dctc, dctc, rre, 1); 4152 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4153 MLX5_SET(dctc, dctc, rwe, 1); 4154 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4155 int atomic_mode; 4156 4157 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4158 if (atomic_mode < 0) 4159 return -EOPNOTSUPP; 4160 4161 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4162 MLX5_SET(dctc, dctc, rae, 1); 4163 } 4164 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4165 MLX5_SET(dctc, dctc, port, attr->port_num); 4166 4167 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4168 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4169 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4170 struct mlx5_ib_modify_qp_resp resp = {}; 4171 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4172 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4173 4174 if (udata->outlen < min_resp_len) 4175 return -EINVAL; 4176 /* 4177 * If we don't have enough space for the ECE options, 4178 * simply indicate it with resp.response_length. 4179 */ 4180 resp.response_length = (udata->outlen < sizeof(resp)) ? 4181 min_resp_len : 4182 sizeof(resp); 4183 4184 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4185 if (!is_valid_mask(attr_mask, required, 0)) 4186 return -EINVAL; 4187 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4188 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4189 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4190 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4191 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4192 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4193 4194 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4195 MLX5_ST_SZ_BYTES(create_dct_in), out, 4196 sizeof(out)); 4197 if (err) 4198 return err; 4199 resp.dctn = qp->dct.mdct.mqp.qpn; 4200 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4201 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4202 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4203 if (err) { 4204 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4205 return err; 4206 } 4207 } else { 4208 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4209 return -EINVAL; 4210 } 4211 if (err) 4212 qp->state = IB_QPS_ERR; 4213 else 4214 qp->state = new_state; 4215 return err; 4216 } 4217 4218 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4219 int attr_mask, struct ib_udata *udata) 4220 { 4221 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4222 struct mlx5_ib_modify_qp_resp resp = {}; 4223 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4224 struct mlx5_ib_modify_qp ucmd = {}; 4225 enum ib_qp_type qp_type; 4226 enum ib_qp_state cur_state, new_state; 4227 int err = -EINVAL; 4228 int port; 4229 4230 if (ibqp->rwq_ind_tbl) 4231 return -ENOSYS; 4232 4233 if (udata && udata->inlen) { 4234 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4235 return -EINVAL; 4236 4237 if (udata->inlen > sizeof(ucmd) && 4238 !ib_is_udata_cleared(udata, sizeof(ucmd), 4239 udata->inlen - sizeof(ucmd))) 4240 return -EOPNOTSUPP; 4241 4242 if (ib_copy_from_udata(&ucmd, udata, 4243 min(udata->inlen, sizeof(ucmd)))) 4244 return -EFAULT; 4245 4246 if (ucmd.comp_mask || 4247 memchr_inv(&ucmd.burst_info.reserved, 0, 4248 sizeof(ucmd.burst_info.reserved))) 4249 return -EOPNOTSUPP; 4250 4251 } 4252 4253 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4254 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4255 4256 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI : 4257 qp->type; 4258 4259 if (qp_type == MLX5_IB_QPT_DCT) 4260 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4261 4262 mutex_lock(&qp->mutex); 4263 4264 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4265 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4266 4267 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 4268 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 4269 } 4270 4271 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4272 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4273 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4274 attr_mask); 4275 goto out; 4276 } 4277 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4278 qp_type != MLX5_IB_QPT_DCI && 4279 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4280 attr_mask)) { 4281 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4282 cur_state, new_state, ibqp->qp_type, attr_mask); 4283 goto out; 4284 } else if (qp_type == MLX5_IB_QPT_DCI && 4285 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4286 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4287 cur_state, new_state, qp_type, attr_mask); 4288 goto out; 4289 } 4290 4291 if ((attr_mask & IB_QP_PORT) && 4292 (attr->port_num == 0 || 4293 attr->port_num > dev->num_ports)) { 4294 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4295 attr->port_num, dev->num_ports); 4296 goto out; 4297 } 4298 4299 if (attr_mask & IB_QP_PKEY_INDEX) { 4300 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 4301 if (attr->pkey_index >= 4302 dev->mdev->port_caps[port - 1].pkey_table_len) { 4303 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 4304 attr->pkey_index); 4305 goto out; 4306 } 4307 } 4308 4309 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4310 attr->max_rd_atomic > 4311 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4312 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4313 attr->max_rd_atomic); 4314 goto out; 4315 } 4316 4317 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4318 attr->max_dest_rd_atomic > 4319 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4320 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4321 attr->max_dest_rd_atomic); 4322 goto out; 4323 } 4324 4325 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4326 err = 0; 4327 goto out; 4328 } 4329 4330 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4331 new_state, &ucmd, &resp, udata); 4332 4333 /* resp.response_length is set in ECE supported flows only */ 4334 if (!err && resp.response_length && 4335 udata->outlen >= resp.response_length) 4336 /* Return -EFAULT to the user and expect him to destroy QP. */ 4337 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4338 4339 out: 4340 mutex_unlock(&qp->mutex); 4341 return err; 4342 } 4343 4344 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4345 { 4346 switch (mlx5_state) { 4347 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4348 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4349 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4350 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4351 case MLX5_QP_STATE_SQ_DRAINING: 4352 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4353 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4354 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4355 default: return -1; 4356 } 4357 } 4358 4359 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4360 { 4361 switch (mlx5_mig_state) { 4362 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4363 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4364 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4365 default: return -1; 4366 } 4367 } 4368 4369 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4370 struct rdma_ah_attr *ah_attr, void *path) 4371 { 4372 int port = MLX5_GET(ads, path, vhca_port_num); 4373 int static_rate; 4374 4375 memset(ah_attr, 0, sizeof(*ah_attr)); 4376 4377 if (!port || port > ibdev->num_ports) 4378 return; 4379 4380 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4381 4382 rdma_ah_set_port_num(ah_attr, port); 4383 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4384 4385 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4386 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4387 4388 static_rate = MLX5_GET(ads, path, stat_rate); 4389 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0); 4390 if (MLX5_GET(ads, path, grh) || 4391 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4392 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4393 MLX5_GET(ads, path, src_addr_index), 4394 MLX5_GET(ads, path, hop_limit), 4395 MLX5_GET(ads, path, tclass)); 4396 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4397 } 4398 } 4399 4400 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4401 struct mlx5_ib_sq *sq, 4402 u8 *sq_state) 4403 { 4404 int err; 4405 4406 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4407 if (err) 4408 goto out; 4409 sq->state = *sq_state; 4410 4411 out: 4412 return err; 4413 } 4414 4415 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4416 struct mlx5_ib_rq *rq, 4417 u8 *rq_state) 4418 { 4419 void *out; 4420 void *rqc; 4421 int inlen; 4422 int err; 4423 4424 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4425 out = kvzalloc(inlen, GFP_KERNEL); 4426 if (!out) 4427 return -ENOMEM; 4428 4429 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4430 if (err) 4431 goto out; 4432 4433 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4434 *rq_state = MLX5_GET(rqc, rqc, state); 4435 rq->state = *rq_state; 4436 4437 out: 4438 kvfree(out); 4439 return err; 4440 } 4441 4442 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4443 struct mlx5_ib_qp *qp, u8 *qp_state) 4444 { 4445 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4446 [MLX5_RQC_STATE_RST] = { 4447 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4448 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4449 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4450 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4451 }, 4452 [MLX5_RQC_STATE_RDY] = { 4453 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4454 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4455 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4456 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4457 }, 4458 [MLX5_RQC_STATE_ERR] = { 4459 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4460 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4461 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4462 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4463 }, 4464 [MLX5_RQ_STATE_NA] = { 4465 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4466 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4467 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4468 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4469 }, 4470 }; 4471 4472 *qp_state = sqrq_trans[rq_state][sq_state]; 4473 4474 if (*qp_state == MLX5_QP_STATE_BAD) { 4475 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4476 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4477 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4478 return -EINVAL; 4479 } 4480 4481 if (*qp_state == MLX5_QP_STATE) 4482 *qp_state = qp->state; 4483 4484 return 0; 4485 } 4486 4487 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4488 struct mlx5_ib_qp *qp, 4489 u8 *raw_packet_qp_state) 4490 { 4491 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4492 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4493 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4494 int err; 4495 u8 sq_state = MLX5_SQ_STATE_NA; 4496 u8 rq_state = MLX5_RQ_STATE_NA; 4497 4498 if (qp->sq.wqe_cnt) { 4499 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4500 if (err) 4501 return err; 4502 } 4503 4504 if (qp->rq.wqe_cnt) { 4505 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4506 if (err) 4507 return err; 4508 } 4509 4510 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4511 raw_packet_qp_state); 4512 } 4513 4514 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4515 struct ib_qp_attr *qp_attr) 4516 { 4517 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4518 void *qpc, *pri_path, *alt_path; 4519 u32 *outb; 4520 int err; 4521 4522 outb = kzalloc(outlen, GFP_KERNEL); 4523 if (!outb) 4524 return -ENOMEM; 4525 4526 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 4527 if (err) 4528 goto out; 4529 4530 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4531 4532 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4533 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4534 qp_attr->sq_draining = 1; 4535 4536 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4537 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4538 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4539 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4540 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4541 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4542 4543 if (MLX5_GET(qpc, qpc, rre)) 4544 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4545 if (MLX5_GET(qpc, qpc, rwe)) 4546 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4547 if (MLX5_GET(qpc, qpc, rae)) 4548 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4549 4550 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4551 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4552 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4553 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4554 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4555 4556 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4557 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4558 4559 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4560 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4561 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4562 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4563 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4564 } 4565 4566 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4567 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4568 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4569 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4570 4571 out: 4572 kfree(outb); 4573 return err; 4574 } 4575 4576 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4577 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4578 struct ib_qp_init_attr *qp_init_attr) 4579 { 4580 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4581 u32 *out; 4582 u32 access_flags = 0; 4583 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4584 void *dctc; 4585 int err; 4586 int supported_mask = IB_QP_STATE | 4587 IB_QP_ACCESS_FLAGS | 4588 IB_QP_PORT | 4589 IB_QP_MIN_RNR_TIMER | 4590 IB_QP_AV | 4591 IB_QP_PATH_MTU | 4592 IB_QP_PKEY_INDEX; 4593 4594 if (qp_attr_mask & ~supported_mask) 4595 return -EINVAL; 4596 if (mqp->state != IB_QPS_RTR) 4597 return -EINVAL; 4598 4599 out = kzalloc(outlen, GFP_KERNEL); 4600 if (!out) 4601 return -ENOMEM; 4602 4603 err = mlx5_core_dct_query(dev, dct, out, outlen); 4604 if (err) 4605 goto out; 4606 4607 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4608 4609 if (qp_attr_mask & IB_QP_STATE) 4610 qp_attr->qp_state = IB_QPS_RTR; 4611 4612 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4613 if (MLX5_GET(dctc, dctc, rre)) 4614 access_flags |= IB_ACCESS_REMOTE_READ; 4615 if (MLX5_GET(dctc, dctc, rwe)) 4616 access_flags |= IB_ACCESS_REMOTE_WRITE; 4617 if (MLX5_GET(dctc, dctc, rae)) 4618 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4619 qp_attr->qp_access_flags = access_flags; 4620 } 4621 4622 if (qp_attr_mask & IB_QP_PORT) 4623 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4624 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4625 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4626 if (qp_attr_mask & IB_QP_AV) { 4627 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4628 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4629 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4630 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4631 } 4632 if (qp_attr_mask & IB_QP_PATH_MTU) 4633 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4634 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4635 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4636 out: 4637 kfree(out); 4638 return err; 4639 } 4640 4641 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4642 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4643 { 4644 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4645 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4646 int err = 0; 4647 u8 raw_packet_qp_state; 4648 4649 if (ibqp->rwq_ind_tbl) 4650 return -ENOSYS; 4651 4652 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4653 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4654 qp_init_attr); 4655 4656 /* Not all of output fields are applicable, make sure to zero them */ 4657 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4658 memset(qp_attr, 0, sizeof(*qp_attr)); 4659 4660 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 4661 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4662 qp_attr_mask, qp_init_attr); 4663 4664 mutex_lock(&qp->mutex); 4665 4666 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4667 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4668 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4669 if (err) 4670 goto out; 4671 qp->state = raw_packet_qp_state; 4672 qp_attr->port_num = 1; 4673 } else { 4674 err = query_qp_attr(dev, qp, qp_attr); 4675 if (err) 4676 goto out; 4677 } 4678 4679 qp_attr->qp_state = qp->state; 4680 qp_attr->cur_qp_state = qp_attr->qp_state; 4681 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4682 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4683 4684 if (!ibqp->uobject) { 4685 qp_attr->cap.max_send_wr = qp->sq.max_post; 4686 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4687 qp_init_attr->qp_context = ibqp->qp_context; 4688 } else { 4689 qp_attr->cap.max_send_wr = 0; 4690 qp_attr->cap.max_send_sge = 0; 4691 } 4692 4693 qp_init_attr->qp_type = ibqp->qp_type; 4694 qp_init_attr->recv_cq = ibqp->recv_cq; 4695 qp_init_attr->send_cq = ibqp->send_cq; 4696 qp_init_attr->srq = ibqp->srq; 4697 qp_attr->cap.max_inline_data = qp->max_inline_data; 4698 4699 qp_init_attr->cap = qp_attr->cap; 4700 4701 qp_init_attr->create_flags = qp->flags; 4702 4703 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4704 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4705 4706 out: 4707 mutex_unlock(&qp->mutex); 4708 return err; 4709 } 4710 4711 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4712 struct ib_udata *udata) 4713 { 4714 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4715 struct mlx5_ib_xrcd *xrcd; 4716 int err; 4717 4718 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4719 return ERR_PTR(-ENOSYS); 4720 4721 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4722 if (!xrcd) 4723 return ERR_PTR(-ENOMEM); 4724 4725 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 4726 if (err) { 4727 kfree(xrcd); 4728 return ERR_PTR(-ENOMEM); 4729 } 4730 4731 return &xrcd->ibxrcd; 4732 } 4733 4734 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4735 { 4736 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4737 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4738 int err; 4739 4740 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 4741 if (err) 4742 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4743 4744 kfree(xrcd); 4745 return 0; 4746 } 4747 4748 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4749 { 4750 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4751 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4752 struct ib_event event; 4753 4754 if (rwq->ibwq.event_handler) { 4755 event.device = rwq->ibwq.device; 4756 event.element.wq = &rwq->ibwq; 4757 switch (type) { 4758 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4759 event.event = IB_EVENT_WQ_FATAL; 4760 break; 4761 default: 4762 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4763 return; 4764 } 4765 4766 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4767 } 4768 } 4769 4770 static int set_delay_drop(struct mlx5_ib_dev *dev) 4771 { 4772 int err = 0; 4773 4774 mutex_lock(&dev->delay_drop.lock); 4775 if (dev->delay_drop.activate) 4776 goto out; 4777 4778 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 4779 if (err) 4780 goto out; 4781 4782 dev->delay_drop.activate = true; 4783 out: 4784 mutex_unlock(&dev->delay_drop.lock); 4785 4786 if (!err) 4787 atomic_inc(&dev->delay_drop.rqs_cnt); 4788 return err; 4789 } 4790 4791 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4792 struct ib_wq_init_attr *init_attr) 4793 { 4794 struct mlx5_ib_dev *dev; 4795 int has_net_offloads; 4796 __be64 *rq_pas0; 4797 void *in; 4798 void *rqc; 4799 void *wq; 4800 int inlen; 4801 int err; 4802 4803 dev = to_mdev(pd->device); 4804 4805 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4806 in = kvzalloc(inlen, GFP_KERNEL); 4807 if (!in) 4808 return -ENOMEM; 4809 4810 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4811 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4812 MLX5_SET(rqc, rqc, mem_rq_type, 4813 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4814 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4815 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4816 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4817 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4818 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4819 MLX5_SET(wq, wq, wq_type, 4820 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 4821 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 4822 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 4823 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 4824 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 4825 err = -EOPNOTSUPP; 4826 goto out; 4827 } else { 4828 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4829 } 4830 } 4831 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4832 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 4833 /* 4834 * In Firmware number of strides in each WQE is: 4835 * "512 * 2^single_wqe_log_num_of_strides" 4836 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 4837 * accepted as 0 to 9 4838 */ 4839 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 4840 2, 3, 4, 5, 6, 7, 8, 9 }; 4841 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 4842 MLX5_SET(wq, wq, log_wqe_stride_size, 4843 rwq->single_stride_log_num_of_bytes - 4844 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 4845 MLX5_SET(wq, wq, log_wqe_num_of_strides, 4846 fw_map[rwq->log_num_strides - 4847 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 4848 } 4849 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4850 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4851 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4852 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4853 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4854 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4855 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4856 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4857 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4858 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4859 err = -EOPNOTSUPP; 4860 goto out; 4861 } 4862 } else { 4863 MLX5_SET(rqc, rqc, vsd, 1); 4864 } 4865 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4866 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4867 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4868 err = -EOPNOTSUPP; 4869 goto out; 4870 } 4871 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4872 } 4873 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4874 if (!(dev->ib_dev.attrs.raw_packet_caps & 4875 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4876 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4877 err = -EOPNOTSUPP; 4878 goto out; 4879 } 4880 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4881 } 4882 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4883 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4884 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 4885 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4886 err = set_delay_drop(dev); 4887 if (err) { 4888 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4889 err); 4890 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 4891 } else { 4892 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4893 } 4894 } 4895 out: 4896 kvfree(in); 4897 return err; 4898 } 4899 4900 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4901 struct ib_wq_init_attr *wq_init_attr, 4902 struct mlx5_ib_create_wq *ucmd, 4903 struct mlx5_ib_rwq *rwq) 4904 { 4905 /* Sanity check RQ size before proceeding */ 4906 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4907 return -EINVAL; 4908 4909 if (!ucmd->rq_wqe_count) 4910 return -EINVAL; 4911 4912 rwq->wqe_count = ucmd->rq_wqe_count; 4913 rwq->wqe_shift = ucmd->rq_wqe_shift; 4914 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 4915 return -EINVAL; 4916 4917 rwq->log_rq_stride = rwq->wqe_shift; 4918 rwq->log_rq_size = ilog2(rwq->wqe_count); 4919 return 0; 4920 } 4921 4922 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 4923 { 4924 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 4925 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 4926 return false; 4927 4928 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 4929 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 4930 return false; 4931 4932 return true; 4933 } 4934 4935 static int prepare_user_rq(struct ib_pd *pd, 4936 struct ib_wq_init_attr *init_attr, 4937 struct ib_udata *udata, 4938 struct mlx5_ib_rwq *rwq) 4939 { 4940 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4941 struct mlx5_ib_create_wq ucmd = {}; 4942 int err; 4943 size_t required_cmd_sz; 4944 4945 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 4946 + sizeof(ucmd.single_stride_log_num_of_bytes); 4947 if (udata->inlen < required_cmd_sz) { 4948 mlx5_ib_dbg(dev, "invalid inlen\n"); 4949 return -EINVAL; 4950 } 4951 4952 if (udata->inlen > sizeof(ucmd) && 4953 !ib_is_udata_cleared(udata, sizeof(ucmd), 4954 udata->inlen - sizeof(ucmd))) { 4955 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4956 return -EOPNOTSUPP; 4957 } 4958 4959 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4960 mlx5_ib_dbg(dev, "copy failed\n"); 4961 return -EFAULT; 4962 } 4963 4964 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 4965 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4966 return -EOPNOTSUPP; 4967 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 4968 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 4969 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 4970 return -EOPNOTSUPP; 4971 } 4972 if ((ucmd.single_stride_log_num_of_bytes < 4973 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 4974 (ucmd.single_stride_log_num_of_bytes > 4975 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 4976 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 4977 ucmd.single_stride_log_num_of_bytes, 4978 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 4979 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 4980 return -EINVAL; 4981 } 4982 if (!log_of_strides_valid(dev, 4983 ucmd.single_wqe_log_num_of_strides)) { 4984 mlx5_ib_dbg( 4985 dev, 4986 "Invalid log num strides (%u. Range is %u - %u)\n", 4987 ucmd.single_wqe_log_num_of_strides, 4988 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 4989 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 4990 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 4991 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 4992 return -EINVAL; 4993 } 4994 rwq->single_stride_log_num_of_bytes = 4995 ucmd.single_stride_log_num_of_bytes; 4996 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 4997 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 4998 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 4999 } 5000 5001 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5002 if (err) { 5003 mlx5_ib_dbg(dev, "err %d\n", err); 5004 return err; 5005 } 5006 5007 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5008 if (err) { 5009 mlx5_ib_dbg(dev, "err %d\n", err); 5010 return err; 5011 } 5012 5013 rwq->user_index = ucmd.user_index; 5014 return 0; 5015 } 5016 5017 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5018 struct ib_wq_init_attr *init_attr, 5019 struct ib_udata *udata) 5020 { 5021 struct mlx5_ib_dev *dev; 5022 struct mlx5_ib_rwq *rwq; 5023 struct mlx5_ib_create_wq_resp resp = {}; 5024 size_t min_resp_len; 5025 int err; 5026 5027 if (!udata) 5028 return ERR_PTR(-ENOSYS); 5029 5030 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5031 if (udata->outlen && udata->outlen < min_resp_len) 5032 return ERR_PTR(-EINVAL); 5033 5034 if (!capable(CAP_SYS_RAWIO) && 5035 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5036 return ERR_PTR(-EPERM); 5037 5038 dev = to_mdev(pd->device); 5039 switch (init_attr->wq_type) { 5040 case IB_WQT_RQ: 5041 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5042 if (!rwq) 5043 return ERR_PTR(-ENOMEM); 5044 err = prepare_user_rq(pd, init_attr, udata, rwq); 5045 if (err) 5046 goto err; 5047 err = create_rq(rwq, pd, init_attr); 5048 if (err) 5049 goto err_user_rq; 5050 break; 5051 default: 5052 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5053 init_attr->wq_type); 5054 return ERR_PTR(-EINVAL); 5055 } 5056 5057 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5058 rwq->ibwq.state = IB_WQS_RESET; 5059 if (udata->outlen) { 5060 resp.response_length = offsetof(typeof(resp), response_length) + 5061 sizeof(resp.response_length); 5062 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5063 if (err) 5064 goto err_copy; 5065 } 5066 5067 rwq->core_qp.event = mlx5_ib_wq_event; 5068 rwq->ibwq.event_handler = init_attr->event_handler; 5069 return &rwq->ibwq; 5070 5071 err_copy: 5072 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5073 err_user_rq: 5074 destroy_user_rq(dev, pd, rwq, udata); 5075 err: 5076 kfree(rwq); 5077 return ERR_PTR(err); 5078 } 5079 5080 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5081 { 5082 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5083 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5084 5085 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5086 destroy_user_rq(dev, wq->pd, rwq, udata); 5087 kfree(rwq); 5088 } 5089 5090 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5091 struct ib_rwq_ind_table_init_attr *init_attr, 5092 struct ib_udata *udata) 5093 { 5094 struct mlx5_ib_dev *dev = to_mdev(device); 5095 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5096 int sz = 1 << init_attr->log_ind_tbl_size; 5097 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5098 size_t min_resp_len; 5099 int inlen; 5100 int err; 5101 int i; 5102 u32 *in; 5103 void *rqtc; 5104 5105 if (udata->inlen > 0 && 5106 !ib_is_udata_cleared(udata, 0, 5107 udata->inlen)) 5108 return ERR_PTR(-EOPNOTSUPP); 5109 5110 if (init_attr->log_ind_tbl_size > 5111 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5112 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5113 init_attr->log_ind_tbl_size, 5114 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5115 return ERR_PTR(-EINVAL); 5116 } 5117 5118 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5119 if (udata->outlen && udata->outlen < min_resp_len) 5120 return ERR_PTR(-EINVAL); 5121 5122 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5123 if (!rwq_ind_tbl) 5124 return ERR_PTR(-ENOMEM); 5125 5126 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5127 in = kvzalloc(inlen, GFP_KERNEL); 5128 if (!in) { 5129 err = -ENOMEM; 5130 goto err; 5131 } 5132 5133 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5134 5135 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5136 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5137 5138 for (i = 0; i < sz; i++) 5139 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5140 5141 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5142 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5143 5144 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5145 kvfree(in); 5146 5147 if (err) 5148 goto err; 5149 5150 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5151 if (udata->outlen) { 5152 resp.response_length = offsetof(typeof(resp), response_length) + 5153 sizeof(resp.response_length); 5154 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5155 if (err) 5156 goto err_copy; 5157 } 5158 5159 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5160 5161 err_copy: 5162 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5163 err: 5164 kfree(rwq_ind_tbl); 5165 return ERR_PTR(err); 5166 } 5167 5168 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5169 { 5170 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5171 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5172 5173 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5174 5175 kfree(rwq_ind_tbl); 5176 return 0; 5177 } 5178 5179 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5180 u32 wq_attr_mask, struct ib_udata *udata) 5181 { 5182 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5183 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5184 struct mlx5_ib_modify_wq ucmd = {}; 5185 size_t required_cmd_sz; 5186 int curr_wq_state; 5187 int wq_state; 5188 int inlen; 5189 int err; 5190 void *rqc; 5191 void *in; 5192 5193 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5194 if (udata->inlen < required_cmd_sz) 5195 return -EINVAL; 5196 5197 if (udata->inlen > sizeof(ucmd) && 5198 !ib_is_udata_cleared(udata, sizeof(ucmd), 5199 udata->inlen - sizeof(ucmd))) 5200 return -EOPNOTSUPP; 5201 5202 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5203 return -EFAULT; 5204 5205 if (ucmd.comp_mask || ucmd.reserved) 5206 return -EOPNOTSUPP; 5207 5208 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5209 in = kvzalloc(inlen, GFP_KERNEL); 5210 if (!in) 5211 return -ENOMEM; 5212 5213 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5214 5215 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5216 wq_attr->curr_wq_state : wq->state; 5217 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5218 wq_attr->wq_state : curr_wq_state; 5219 if (curr_wq_state == IB_WQS_ERR) 5220 curr_wq_state = MLX5_RQC_STATE_ERR; 5221 if (wq_state == IB_WQS_ERR) 5222 wq_state = MLX5_RQC_STATE_ERR; 5223 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5224 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5225 MLX5_SET(rqc, rqc, state, wq_state); 5226 5227 if (wq_attr_mask & IB_WQ_FLAGS) { 5228 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5229 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5230 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5231 mlx5_ib_dbg(dev, "VLAN offloads are not " 5232 "supported\n"); 5233 err = -EOPNOTSUPP; 5234 goto out; 5235 } 5236 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5237 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5238 MLX5_SET(rqc, rqc, vsd, 5239 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5240 } 5241 5242 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5243 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5244 err = -EOPNOTSUPP; 5245 goto out; 5246 } 5247 } 5248 5249 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5250 u16 set_id; 5251 5252 set_id = mlx5_ib_get_counters_id(dev, 0); 5253 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5254 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5255 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5256 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5257 } else 5258 dev_info_once( 5259 &dev->ib_dev.dev, 5260 "Receive WQ counters are not supported on current FW\n"); 5261 } 5262 5263 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5264 if (!err) 5265 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5266 5267 out: 5268 kvfree(in); 5269 return err; 5270 } 5271 5272 struct mlx5_ib_drain_cqe { 5273 struct ib_cqe cqe; 5274 struct completion done; 5275 }; 5276 5277 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5278 { 5279 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5280 struct mlx5_ib_drain_cqe, 5281 cqe); 5282 5283 complete(&cqe->done); 5284 } 5285 5286 /* This function returns only once the drained WR was completed */ 5287 static void handle_drain_completion(struct ib_cq *cq, 5288 struct mlx5_ib_drain_cqe *sdrain, 5289 struct mlx5_ib_dev *dev) 5290 { 5291 struct mlx5_core_dev *mdev = dev->mdev; 5292 5293 if (cq->poll_ctx == IB_POLL_DIRECT) { 5294 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5295 ib_process_cq_direct(cq, -1); 5296 return; 5297 } 5298 5299 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5300 struct mlx5_ib_cq *mcq = to_mcq(cq); 5301 bool triggered = false; 5302 unsigned long flags; 5303 5304 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5305 /* Make sure that the CQ handler won't run if wasn't run yet */ 5306 if (!mcq->mcq.reset_notify_added) 5307 mcq->mcq.reset_notify_added = 1; 5308 else 5309 triggered = true; 5310 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5311 5312 if (triggered) { 5313 /* Wait for any scheduled/running task to be ended */ 5314 switch (cq->poll_ctx) { 5315 case IB_POLL_SOFTIRQ: 5316 irq_poll_disable(&cq->iop); 5317 irq_poll_enable(&cq->iop); 5318 break; 5319 case IB_POLL_WORKQUEUE: 5320 cancel_work_sync(&cq->work); 5321 break; 5322 default: 5323 WARN_ON_ONCE(1); 5324 } 5325 } 5326 5327 /* Run the CQ handler - this makes sure that the drain WR will 5328 * be processed if wasn't processed yet. 5329 */ 5330 mcq->mcq.comp(&mcq->mcq, NULL); 5331 } 5332 5333 wait_for_completion(&sdrain->done); 5334 } 5335 5336 void mlx5_ib_drain_sq(struct ib_qp *qp) 5337 { 5338 struct ib_cq *cq = qp->send_cq; 5339 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5340 struct mlx5_ib_drain_cqe sdrain; 5341 const struct ib_send_wr *bad_swr; 5342 struct ib_rdma_wr swr = { 5343 .wr = { 5344 .next = NULL, 5345 { .wr_cqe = &sdrain.cqe, }, 5346 .opcode = IB_WR_RDMA_WRITE, 5347 }, 5348 }; 5349 int ret; 5350 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5351 struct mlx5_core_dev *mdev = dev->mdev; 5352 5353 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5354 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5355 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5356 return; 5357 } 5358 5359 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5360 init_completion(&sdrain.done); 5361 5362 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5363 if (ret) { 5364 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5365 return; 5366 } 5367 5368 handle_drain_completion(cq, &sdrain, dev); 5369 } 5370 5371 void mlx5_ib_drain_rq(struct ib_qp *qp) 5372 { 5373 struct ib_cq *cq = qp->recv_cq; 5374 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5375 struct mlx5_ib_drain_cqe rdrain; 5376 struct ib_recv_wr rwr = {}; 5377 const struct ib_recv_wr *bad_rwr; 5378 int ret; 5379 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5380 struct mlx5_core_dev *mdev = dev->mdev; 5381 5382 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5383 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5384 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5385 return; 5386 } 5387 5388 rwr.wr_cqe = &rdrain.cqe; 5389 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5390 init_completion(&rdrain.done); 5391 5392 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5393 if (ret) { 5394 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5395 return; 5396 } 5397 5398 handle_drain_completion(cq, &rdrain, dev); 5399 } 5400 5401 /** 5402 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5403 * the default counter 5404 */ 5405 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5406 { 5407 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5408 struct mlx5_ib_qp *mqp = to_mqp(qp); 5409 int err = 0; 5410 5411 mutex_lock(&mqp->mutex); 5412 if (mqp->state == IB_QPS_RESET) { 5413 qp->counter = counter; 5414 goto out; 5415 } 5416 5417 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5418 err = -EOPNOTSUPP; 5419 goto out; 5420 } 5421 5422 if (mqp->state == IB_QPS_RTS) { 5423 err = __mlx5_ib_qp_set_counter(qp, counter); 5424 if (!err) 5425 qp->counter = counter; 5426 5427 goto out; 5428 } 5429 5430 mqp->counter_pending = 1; 5431 qp->counter = counter; 5432 5433 out: 5434 mutex_unlock(&mqp->mutex); 5435 return err; 5436 } 5437