1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "qp.h" 44 #include "wr.h" 45 46 enum { 47 MLX5_IB_ACK_REQ_FREQ = 8, 48 }; 49 50 enum { 51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 53 MLX5_IB_LINK_TYPE_IB = 0, 54 MLX5_IB_LINK_TYPE_ETH = 1 55 }; 56 57 enum raw_qp_set_mask_map { 58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 60 }; 61 62 struct mlx5_modify_raw_qp_param { 63 u16 operation; 64 65 u32 set_mask; /* raw_qp_set_mask_map */ 66 67 struct mlx5_rate_limit rl; 68 69 u8 rq_q_ctr_id; 70 u32 port; 71 }; 72 73 static void get_cqs(enum ib_qp_type qp_type, 74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 76 77 static int is_qp0(enum ib_qp_type qp_type) 78 { 79 return qp_type == IB_QPT_SMI; 80 } 81 82 static int is_sqp(enum ib_qp_type qp_type) 83 { 84 return is_qp0(qp_type) || is_qp1(qp_type); 85 } 86 87 /** 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 89 * to kernel buffer 90 * 91 * @umem: User space memory where the WQ is 92 * @buffer: buffer to copy to 93 * @buflen: buffer length 94 * @wqe_index: index of WQE to copy from 95 * @wq_offset: offset to start of WQ 96 * @wq_wqe_cnt: number of WQEs in WQ 97 * @wq_wqe_shift: log2 of WQE size 98 * @bcnt: number of bytes to copy 99 * @bytes_copied: number of bytes to copy (return value) 100 * 101 * Copies from start of WQE bcnt or less bytes. 102 * Does not gurantee to copy the entire WQE. 103 * 104 * Return: zero on success, or an error code. 105 */ 106 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 107 size_t buflen, int wqe_index, 108 int wq_offset, int wq_wqe_cnt, 109 int wq_wqe_shift, int bcnt, 110 size_t *bytes_copied) 111 { 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 114 size_t copy_length; 115 int ret; 116 117 /* don't copy more than requested, more than buffer length or 118 * beyond WQ end 119 */ 120 copy_length = min_t(u32, buflen, wq_end - offset); 121 copy_length = min_t(u32, copy_length, bcnt); 122 123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 124 if (ret) 125 return ret; 126 127 if (!ret && bytes_copied) 128 *bytes_copied = copy_length; 129 130 return 0; 131 } 132 133 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 134 void *buffer, size_t buflen, size_t *bc) 135 { 136 struct mlx5_wqe_ctrl_seg *ctrl; 137 size_t bytes_copied = 0; 138 size_t wqe_length; 139 void *p; 140 int ds; 141 142 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 143 144 /* read the control segment first */ 145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 146 ctrl = p; 147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 148 wqe_length = ds * MLX5_WQE_DS_UNITS; 149 150 /* read rest of WQE if it spreads over more than one stride */ 151 while (bytes_copied < wqe_length) { 152 size_t copy_length = 153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 154 155 if (!copy_length) 156 break; 157 158 memcpy(buffer + bytes_copied, p, copy_length); 159 bytes_copied += copy_length; 160 161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 163 } 164 *bc = bytes_copied; 165 return 0; 166 } 167 168 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 169 void *buffer, size_t buflen, size_t *bc) 170 { 171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 172 struct ib_umem *umem = base->ubuffer.umem; 173 struct mlx5_ib_wq *wq = &qp->sq; 174 struct mlx5_wqe_ctrl_seg *ctrl; 175 size_t bytes_copied; 176 size_t bytes_copied2; 177 size_t wqe_length; 178 int ret; 179 int ds; 180 181 /* at first read as much as possible */ 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 183 wq->offset, wq->wqe_cnt, 184 wq->wqe_shift, buflen, 185 &bytes_copied); 186 if (ret) 187 return ret; 188 189 /* we need at least control segment size to proceed */ 190 if (bytes_copied < sizeof(*ctrl)) 191 return -EINVAL; 192 193 ctrl = buffer; 194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 195 wqe_length = ds * MLX5_WQE_DS_UNITS; 196 197 /* if we copied enough then we are done */ 198 if (bytes_copied >= wqe_length) { 199 *bc = bytes_copied; 200 return 0; 201 } 202 203 /* otherwise this a wrapped around wqe 204 * so read the remaining bytes starting 205 * from wqe_index 0 206 */ 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 208 buflen - bytes_copied, 0, wq->offset, 209 wq->wqe_cnt, wq->wqe_shift, 210 wqe_length - bytes_copied, 211 &bytes_copied2); 212 213 if (ret) 214 return ret; 215 *bc = bytes_copied + bytes_copied2; 216 return 0; 217 } 218 219 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 220 size_t buflen, size_t *bc) 221 { 222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 223 struct ib_umem *umem = base->ubuffer.umem; 224 225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 226 return -EINVAL; 227 228 if (!umem) 229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 230 buflen, bc); 231 232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 233 } 234 235 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 236 void *buffer, size_t buflen, size_t *bc) 237 { 238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 239 struct ib_umem *umem = base->ubuffer.umem; 240 struct mlx5_ib_wq *wq = &qp->rq; 241 size_t bytes_copied; 242 int ret; 243 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 245 wq->offset, wq->wqe_cnt, 246 wq->wqe_shift, buflen, 247 &bytes_copied); 248 249 if (ret) 250 return ret; 251 *bc = bytes_copied; 252 return 0; 253 } 254 255 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 256 size_t buflen, size_t *bc) 257 { 258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 259 struct ib_umem *umem = base->ubuffer.umem; 260 struct mlx5_ib_wq *wq = &qp->rq; 261 size_t wqe_size = 1 << wq->wqe_shift; 262 263 if (buflen < wqe_size) 264 return -EINVAL; 265 266 if (!umem) 267 return -EOPNOTSUPP; 268 269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 270 } 271 272 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 273 void *buffer, size_t buflen, size_t *bc) 274 { 275 struct ib_umem *umem = srq->umem; 276 size_t bytes_copied; 277 int ret; 278 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 280 srq->msrq.max, srq->msrq.wqe_shift, 281 buflen, &bytes_copied); 282 283 if (ret) 284 return ret; 285 *bc = bytes_copied; 286 return 0; 287 } 288 289 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 290 size_t buflen, size_t *bc) 291 { 292 struct ib_umem *umem = srq->umem; 293 size_t wqe_size = 1 << srq->msrq.wqe_shift; 294 295 if (buflen < wqe_size) 296 return -EINVAL; 297 298 if (!umem) 299 return -EOPNOTSUPP; 300 301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 302 } 303 304 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 305 { 306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 307 struct ib_event event; 308 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 310 /* This event is only valid for trans_qps */ 311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 312 } 313 314 if (ibqp->event_handler) { 315 event.device = ibqp->device; 316 event.element.qp = ibqp; 317 switch (type) { 318 case MLX5_EVENT_TYPE_PATH_MIG: 319 event.event = IB_EVENT_PATH_MIG; 320 break; 321 case MLX5_EVENT_TYPE_COMM_EST: 322 event.event = IB_EVENT_COMM_EST; 323 break; 324 case MLX5_EVENT_TYPE_SQ_DRAINED: 325 event.event = IB_EVENT_SQ_DRAINED; 326 break; 327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 328 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 329 break; 330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 331 event.event = IB_EVENT_QP_FATAL; 332 break; 333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 334 event.event = IB_EVENT_PATH_MIG_ERR; 335 break; 336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 337 event.event = IB_EVENT_QP_REQ_ERR; 338 break; 339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 340 event.event = IB_EVENT_QP_ACCESS_ERR; 341 break; 342 default: 343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 344 return; 345 } 346 347 ibqp->event_handler(&event, ibqp->qp_context); 348 } 349 } 350 351 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 353 { 354 int wqe_size; 355 int wq_size; 356 357 /* Sanity check RQ size before proceeding */ 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 359 return -EINVAL; 360 361 if (!has_rq) { 362 qp->rq.max_gs = 0; 363 qp->rq.wqe_cnt = 0; 364 qp->rq.wqe_shift = 0; 365 cap->max_recv_wr = 0; 366 cap->max_recv_sge = 0; 367 } else { 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 369 370 if (ucmd) { 371 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 373 return -EINVAL; 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 375 if ((1 << qp->rq.wqe_shift) / 376 sizeof(struct mlx5_wqe_data_seg) < 377 wq_sig) 378 return -EINVAL; 379 qp->rq.max_gs = 380 (1 << qp->rq.wqe_shift) / 381 sizeof(struct mlx5_wqe_data_seg) - 382 wq_sig; 383 qp->rq.max_post = qp->rq.wqe_cnt; 384 } else { 385 wqe_size = 386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 387 0; 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 389 wqe_size = roundup_pow_of_two(wqe_size); 390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 392 qp->rq.wqe_cnt = wq_size / wqe_size; 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 395 wqe_size, 396 MLX5_CAP_GEN(dev->mdev, 397 max_wqe_sz_rq)); 398 return -EINVAL; 399 } 400 qp->rq.wqe_shift = ilog2(wqe_size); 401 qp->rq.max_gs = 402 (1 << qp->rq.wqe_shift) / 403 sizeof(struct mlx5_wqe_data_seg) - 404 wq_sig; 405 qp->rq.max_post = qp->rq.wqe_cnt; 406 } 407 } 408 409 return 0; 410 } 411 412 static int sq_overhead(struct ib_qp_init_attr *attr) 413 { 414 int size = 0; 415 416 switch (attr->qp_type) { 417 case IB_QPT_XRC_INI: 418 size += sizeof(struct mlx5_wqe_xrc_seg); 419 fallthrough; 420 case IB_QPT_RC: 421 size += sizeof(struct mlx5_wqe_ctrl_seg) + 422 max(sizeof(struct mlx5_wqe_atomic_seg) + 423 sizeof(struct mlx5_wqe_raddr_seg), 424 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 425 sizeof(struct mlx5_mkey_seg) + 426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 427 MLX5_IB_UMR_OCTOWORD); 428 break; 429 430 case IB_QPT_XRC_TGT: 431 return 0; 432 433 case IB_QPT_UC: 434 size += sizeof(struct mlx5_wqe_ctrl_seg) + 435 max(sizeof(struct mlx5_wqe_raddr_seg), 436 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 437 sizeof(struct mlx5_mkey_seg)); 438 break; 439 440 case IB_QPT_UD: 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 442 size += sizeof(struct mlx5_wqe_eth_pad) + 443 sizeof(struct mlx5_wqe_eth_seg); 444 fallthrough; 445 case IB_QPT_SMI: 446 case MLX5_IB_QPT_HW_GSI: 447 size += sizeof(struct mlx5_wqe_ctrl_seg) + 448 sizeof(struct mlx5_wqe_datagram_seg); 449 break; 450 451 case MLX5_IB_QPT_REG_UMR: 452 size += sizeof(struct mlx5_wqe_ctrl_seg) + 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 454 sizeof(struct mlx5_mkey_seg); 455 break; 456 457 default: 458 return -EINVAL; 459 } 460 461 return size; 462 } 463 464 static int calc_send_wqe(struct ib_qp_init_attr *attr) 465 { 466 int inl_size = 0; 467 int size; 468 469 size = sq_overhead(attr); 470 if (size < 0) 471 return size; 472 473 if (attr->cap.max_inline_data) { 474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 475 attr->cap.max_inline_data; 476 } 477 478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 481 return MLX5_SIG_WQE_SIZE; 482 else 483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 484 } 485 486 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 487 { 488 int max_sge; 489 490 if (attr->qp_type == IB_QPT_RC) 491 max_sge = (min_t(int, wqe_size, 512) - 492 sizeof(struct mlx5_wqe_ctrl_seg) - 493 sizeof(struct mlx5_wqe_raddr_seg)) / 494 sizeof(struct mlx5_wqe_data_seg); 495 else if (attr->qp_type == IB_QPT_XRC_INI) 496 max_sge = (min_t(int, wqe_size, 512) - 497 sizeof(struct mlx5_wqe_ctrl_seg) - 498 sizeof(struct mlx5_wqe_xrc_seg) - 499 sizeof(struct mlx5_wqe_raddr_seg)) / 500 sizeof(struct mlx5_wqe_data_seg); 501 else 502 max_sge = (wqe_size - sq_overhead(attr)) / 503 sizeof(struct mlx5_wqe_data_seg); 504 505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 506 sizeof(struct mlx5_wqe_data_seg)); 507 } 508 509 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 510 struct mlx5_ib_qp *qp) 511 { 512 int wqe_size; 513 int wq_size; 514 515 if (!attr->cap.max_send_wr) 516 return 0; 517 518 wqe_size = calc_send_wqe(attr); 519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 520 if (wqe_size < 0) 521 return wqe_size; 522 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 526 return -EINVAL; 527 } 528 529 qp->max_inline_data = wqe_size - sq_overhead(attr) - 530 sizeof(struct mlx5_wqe_inline_seg); 531 attr->cap.max_inline_data = qp->max_inline_data; 532 533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 538 qp->sq.wqe_cnt, 539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 540 return -ENOMEM; 541 } 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 543 qp->sq.max_gs = get_send_sge(attr, wqe_size); 544 if (qp->sq.max_gs < attr->cap.max_send_sge) 545 return -ENOMEM; 546 547 attr->cap.max_send_sge = qp->sq.max_gs; 548 qp->sq.max_post = wq_size / wqe_size; 549 attr->cap.max_send_wr = qp->sq.max_post; 550 551 return wq_size; 552 } 553 554 static int set_user_buf_size(struct mlx5_ib_dev *dev, 555 struct mlx5_ib_qp *qp, 556 struct mlx5_ib_create_qp *ucmd, 557 struct mlx5_ib_qp_base *base, 558 struct ib_qp_init_attr *attr) 559 { 560 int desc_sz = 1 << qp->sq.wqe_shift; 561 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 565 return -EINVAL; 566 } 567 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 570 ucmd->sq_wqe_count); 571 return -EINVAL; 572 } 573 574 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 575 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 578 qp->sq.wqe_cnt, 579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 580 return -EINVAL; 581 } 582 583 if (attr->qp_type == IB_QPT_RAW_PACKET || 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 587 } else { 588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 589 (qp->sq.wqe_cnt << 6); 590 } 591 592 return 0; 593 } 594 595 static int qp_has_rq(struct ib_qp_init_attr *attr) 596 { 597 if (attr->qp_type == IB_QPT_XRC_INI || 598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 599 attr->qp_type == MLX5_IB_QPT_REG_UMR || 600 !attr->cap.max_recv_wr) 601 return 0; 602 603 return 1; 604 } 605 606 enum { 607 /* this is the first blue flame register in the array of bfregs assigned 608 * to a processes. Since we do not use it for blue flame but rather 609 * regular 64 bit doorbells, we do not need a lock for maintaiing 610 * "odd/even" order 611 */ 612 NUM_NON_BLUE_FLAME_BFREGS = 1, 613 }; 614 615 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 616 { 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 618 } 619 620 static int num_med_bfreg(struct mlx5_ib_dev *dev, 621 struct mlx5_bfreg_info *bfregi) 622 { 623 int n; 624 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 626 NUM_NON_BLUE_FLAME_BFREGS; 627 628 return n >= 0 ? n : 0; 629 } 630 631 static int first_med_bfreg(struct mlx5_ib_dev *dev, 632 struct mlx5_bfreg_info *bfregi) 633 { 634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 635 } 636 637 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 638 struct mlx5_bfreg_info *bfregi) 639 { 640 int med; 641 642 med = num_med_bfreg(dev, bfregi); 643 return ++med; 644 } 645 646 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 647 struct mlx5_bfreg_info *bfregi) 648 { 649 int i; 650 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 652 if (!bfregi->count[i]) { 653 bfregi->count[i]++; 654 return i; 655 } 656 } 657 658 return -ENOMEM; 659 } 660 661 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 662 struct mlx5_bfreg_info *bfregi) 663 { 664 int minidx = first_med_bfreg(dev, bfregi); 665 int i; 666 667 if (minidx < 0) 668 return minidx; 669 670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 671 if (bfregi->count[i] < bfregi->count[minidx]) 672 minidx = i; 673 if (!bfregi->count[minidx]) 674 break; 675 } 676 677 bfregi->count[minidx]++; 678 return minidx; 679 } 680 681 static int alloc_bfreg(struct mlx5_ib_dev *dev, 682 struct mlx5_bfreg_info *bfregi) 683 { 684 int bfregn = -ENOMEM; 685 686 if (bfregi->lib_uar_dyn) 687 return -EINVAL; 688 689 mutex_lock(&bfregi->lock); 690 if (bfregi->ver >= 2) { 691 bfregn = alloc_high_class_bfreg(dev, bfregi); 692 if (bfregn < 0) 693 bfregn = alloc_med_class_bfreg(dev, bfregi); 694 } 695 696 if (bfregn < 0) { 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 698 bfregn = 0; 699 bfregi->count[bfregn]++; 700 } 701 mutex_unlock(&bfregi->lock); 702 703 return bfregn; 704 } 705 706 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 707 { 708 mutex_lock(&bfregi->lock); 709 bfregi->count[bfregn]--; 710 mutex_unlock(&bfregi->lock); 711 } 712 713 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 714 { 715 switch (state) { 716 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 723 default: return -1; 724 } 725 } 726 727 static int to_mlx5_st(enum ib_qp_type type) 728 { 729 switch (type) { 730 case IB_QPT_RC: return MLX5_QP_ST_RC; 731 case IB_QPT_UC: return MLX5_QP_ST_UC; 732 case IB_QPT_UD: return MLX5_QP_ST_UD; 733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 734 case IB_QPT_XRC_INI: 735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 736 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 740 default: return -EINVAL; 741 } 742 } 743 744 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 745 struct mlx5_ib_cq *recv_cq); 746 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 747 struct mlx5_ib_cq *recv_cq); 748 749 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, u32 bfregn, 751 bool dyn_bfreg) 752 { 753 unsigned int bfregs_per_sys_page; 754 u32 index_of_sys_page; 755 u32 offset; 756 757 if (bfregi->lib_uar_dyn) 758 return -EINVAL; 759 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 761 MLX5_NON_FP_BFREGS_PER_UAR; 762 index_of_sys_page = bfregn / bfregs_per_sys_page; 763 764 if (dyn_bfreg) { 765 index_of_sys_page += bfregi->num_static_sys_pages; 766 767 if (index_of_sys_page >= bfregi->num_sys_pages) 768 return -EINVAL; 769 770 if (bfregn > bfregi->num_dyn_bfregs || 771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 773 return -EINVAL; 774 } 775 } 776 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 778 return bfregi->sys_pages[index_of_sys_page] + offset; 779 } 780 781 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 782 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 783 { 784 struct mlx5_ib_ucontext *context = 785 rdma_udata_to_drv_context( 786 udata, 787 struct mlx5_ib_ucontext, 788 ibucontext); 789 790 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 791 atomic_dec(&dev->delay_drop.rqs_cnt); 792 793 mlx5_ib_db_unmap_user(context, &rwq->db); 794 ib_umem_release(rwq->umem); 795 } 796 797 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 798 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 799 struct mlx5_ib_create_wq *ucmd) 800 { 801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 802 udata, struct mlx5_ib_ucontext, ibucontext); 803 unsigned long page_size = 0; 804 u32 offset = 0; 805 int err; 806 807 if (!ucmd->buf_addr) 808 return -EINVAL; 809 810 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 811 if (IS_ERR(rwq->umem)) { 812 mlx5_ib_dbg(dev, "umem_get failed\n"); 813 err = PTR_ERR(rwq->umem); 814 return err; 815 } 816 817 page_size = mlx5_umem_find_best_quantized_pgoff( 818 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 819 page_offset, 64, &rwq->rq_page_offset); 820 if (!page_size) { 821 mlx5_ib_warn(dev, "bad offset\n"); 822 err = -EINVAL; 823 goto err_umem; 824 } 825 826 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 827 rwq->page_shift = order_base_2(page_size); 828 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 829 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 830 831 mlx5_ib_dbg( 832 dev, 833 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 834 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 835 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 836 offset); 837 838 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 839 if (err) { 840 mlx5_ib_dbg(dev, "map failed\n"); 841 goto err_umem; 842 } 843 844 return 0; 845 846 err_umem: 847 ib_umem_release(rwq->umem); 848 return err; 849 } 850 851 static int adjust_bfregn(struct mlx5_ib_dev *dev, 852 struct mlx5_bfreg_info *bfregi, int bfregn) 853 { 854 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 855 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 856 } 857 858 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 859 struct mlx5_ib_qp *qp, struct ib_udata *udata, 860 struct ib_qp_init_attr *attr, u32 **in, 861 struct mlx5_ib_create_qp_resp *resp, int *inlen, 862 struct mlx5_ib_qp_base *base, 863 struct mlx5_ib_create_qp *ucmd) 864 { 865 struct mlx5_ib_ucontext *context; 866 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 867 unsigned int page_offset_quantized = 0; 868 unsigned long page_size = 0; 869 int uar_index = 0; 870 int bfregn; 871 int ncont = 0; 872 __be64 *pas; 873 void *qpc; 874 int err; 875 u16 uid; 876 u32 uar_flags; 877 878 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 879 ibucontext); 880 uar_flags = qp->flags_en & 881 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 882 switch (uar_flags) { 883 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 884 uar_index = ucmd->bfreg_index; 885 bfregn = MLX5_IB_INVALID_BFREG; 886 break; 887 case MLX5_QP_FLAG_BFREG_INDEX: 888 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 889 ucmd->bfreg_index, true); 890 if (uar_index < 0) 891 return uar_index; 892 bfregn = MLX5_IB_INVALID_BFREG; 893 break; 894 case 0: 895 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 896 return -EINVAL; 897 bfregn = alloc_bfreg(dev, &context->bfregi); 898 if (bfregn < 0) 899 return bfregn; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 906 if (bfregn != MLX5_IB_INVALID_BFREG) 907 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 908 false); 909 910 qp->rq.offset = 0; 911 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 912 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 913 914 err = set_user_buf_size(dev, qp, ucmd, base, attr); 915 if (err) 916 goto err_bfreg; 917 918 if (ucmd->buf_addr && ubuffer->buf_size) { 919 ubuffer->buf_addr = ucmd->buf_addr; 920 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 921 ubuffer->buf_size, 0); 922 if (IS_ERR(ubuffer->umem)) { 923 err = PTR_ERR(ubuffer->umem); 924 goto err_bfreg; 925 } 926 page_size = mlx5_umem_find_best_quantized_pgoff( 927 ubuffer->umem, qpc, log_page_size, 928 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 929 &page_offset_quantized); 930 if (!page_size) { 931 err = -EINVAL; 932 goto err_umem; 933 } 934 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 935 } else { 936 ubuffer->umem = NULL; 937 } 938 939 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 940 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 941 *in = kvzalloc(*inlen, GFP_KERNEL); 942 if (!*in) { 943 err = -ENOMEM; 944 goto err_umem; 945 } 946 947 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 948 MLX5_SET(create_qp_in, *in, uid, uid); 949 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 950 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 951 if (ubuffer->umem) { 952 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 953 MLX5_SET(qpc, qpc, log_page_size, 954 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 955 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 956 } 957 MLX5_SET(qpc, qpc, uar_page, uar_index); 958 if (bfregn != MLX5_IB_INVALID_BFREG) 959 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 960 else 961 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 962 qp->bfregn = bfregn; 963 964 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db); 965 if (err) { 966 mlx5_ib_dbg(dev, "map failed\n"); 967 goto err_free; 968 } 969 970 return 0; 971 972 err_free: 973 kvfree(*in); 974 975 err_umem: 976 ib_umem_release(ubuffer->umem); 977 978 err_bfreg: 979 if (bfregn != MLX5_IB_INVALID_BFREG) 980 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 981 return err; 982 } 983 984 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 985 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 986 { 987 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 988 udata, struct mlx5_ib_ucontext, ibucontext); 989 990 if (udata) { 991 /* User QP */ 992 mlx5_ib_db_unmap_user(context, &qp->db); 993 ib_umem_release(base->ubuffer.umem); 994 995 /* 996 * Free only the BFREGs which are handled by the kernel. 997 * BFREGs of UARs allocated dynamically are handled by user. 998 */ 999 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1000 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1001 return; 1002 } 1003 1004 /* Kernel QP */ 1005 kvfree(qp->sq.wqe_head); 1006 kvfree(qp->sq.w_list); 1007 kvfree(qp->sq.wrid); 1008 kvfree(qp->sq.wr_data); 1009 kvfree(qp->rq.wrid); 1010 if (qp->db.db) 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 if (qp->buf.frags) 1013 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1014 } 1015 1016 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1017 struct ib_qp_init_attr *init_attr, 1018 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1019 struct mlx5_ib_qp_base *base) 1020 { 1021 int uar_index; 1022 void *qpc; 1023 int err; 1024 1025 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1026 qp->bf.bfreg = &dev->fp_bfreg; 1027 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1028 qp->bf.bfreg = &dev->wc_bfreg; 1029 else 1030 qp->bf.bfreg = &dev->bfreg; 1031 1032 /* We need to divide by two since each register is comprised of 1033 * two buffers of identical size, namely odd and even 1034 */ 1035 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1036 uar_index = qp->bf.bfreg->index; 1037 1038 err = calc_sq_size(dev, init_attr, qp); 1039 if (err < 0) { 1040 mlx5_ib_dbg(dev, "err %d\n", err); 1041 return err; 1042 } 1043 1044 qp->rq.offset = 0; 1045 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1046 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1047 1048 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1049 &qp->buf, dev->mdev->priv.numa_node); 1050 if (err) { 1051 mlx5_ib_dbg(dev, "err %d\n", err); 1052 return err; 1053 } 1054 1055 if (qp->rq.wqe_cnt) 1056 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1057 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1058 1059 if (qp->sq.wqe_cnt) { 1060 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1061 MLX5_SEND_WQE_BB; 1062 mlx5_init_fbc_offset(qp->buf.frags + 1063 (qp->sq.offset / PAGE_SIZE), 1064 ilog2(MLX5_SEND_WQE_BB), 1065 ilog2(qp->sq.wqe_cnt), 1066 sq_strides_offset, &qp->sq.fbc); 1067 1068 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1069 } 1070 1071 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1072 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1073 *in = kvzalloc(*inlen, GFP_KERNEL); 1074 if (!*in) { 1075 err = -ENOMEM; 1076 goto err_buf; 1077 } 1078 1079 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1080 MLX5_SET(qpc, qpc, uar_page, uar_index); 1081 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1082 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1083 1084 /* Set "fast registration enabled" for all kernel QPs */ 1085 MLX5_SET(qpc, qpc, fre, 1); 1086 MLX5_SET(qpc, qpc, rlky, 1); 1087 1088 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1089 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1090 1091 mlx5_fill_page_frag_array(&qp->buf, 1092 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1093 *in, pas)); 1094 1095 err = mlx5_db_alloc(dev->mdev, &qp->db); 1096 if (err) { 1097 mlx5_ib_dbg(dev, "err %d\n", err); 1098 goto err_free; 1099 } 1100 1101 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1102 sizeof(*qp->sq.wrid), GFP_KERNEL); 1103 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1104 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1105 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1106 sizeof(*qp->rq.wrid), GFP_KERNEL); 1107 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1108 sizeof(*qp->sq.w_list), GFP_KERNEL); 1109 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1110 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1111 1112 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1113 !qp->sq.w_list || !qp->sq.wqe_head) { 1114 err = -ENOMEM; 1115 goto err_wrid; 1116 } 1117 1118 return 0; 1119 1120 err_wrid: 1121 kvfree(qp->sq.wqe_head); 1122 kvfree(qp->sq.w_list); 1123 kvfree(qp->sq.wrid); 1124 kvfree(qp->sq.wr_data); 1125 kvfree(qp->rq.wrid); 1126 mlx5_db_free(dev->mdev, &qp->db); 1127 1128 err_free: 1129 kvfree(*in); 1130 1131 err_buf: 1132 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1133 return err; 1134 } 1135 1136 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1137 { 1138 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1139 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1140 return MLX5_SRQ_RQ; 1141 else if (!qp->has_rq) 1142 return MLX5_ZERO_LEN_RQ; 1143 1144 return MLX5_NON_ZERO_RQ; 1145 } 1146 1147 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1148 struct mlx5_ib_qp *qp, 1149 struct mlx5_ib_sq *sq, u32 tdn, 1150 struct ib_pd *pd) 1151 { 1152 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1153 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1154 1155 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1156 MLX5_SET(tisc, tisc, transport_domain, tdn); 1157 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1158 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1159 1160 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1161 } 1162 1163 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1164 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1165 { 1166 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1167 } 1168 1169 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1170 { 1171 if (sq->flow_rule) 1172 mlx5_del_flow_rules(sq->flow_rule); 1173 sq->flow_rule = NULL; 1174 } 1175 1176 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1177 { 1178 bool fr_supported = 1179 MLX5_CAP_GEN(dev->mdev, rq_ts_format) == 1180 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1181 MLX5_CAP_GEN(dev->mdev, rq_ts_format) == 1182 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1183 1184 if (send_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1185 if (!fr_supported) { 1186 mlx5_ib_dbg(dev, "Free running TS format is not supported\n"); 1187 return -EOPNOTSUPP; 1188 } 1189 return MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING; 1190 } 1191 return fr_supported ? MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING : 1192 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT; 1193 } 1194 1195 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1196 { 1197 bool fr_supported = 1198 MLX5_CAP_GEN(dev->mdev, sq_ts_format) == 1199 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1200 MLX5_CAP_GEN(dev->mdev, sq_ts_format) == 1201 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1202 1203 if (send_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1204 if (!fr_supported) { 1205 mlx5_ib_dbg(dev, "Free running TS format is not supported\n"); 1206 return -EOPNOTSUPP; 1207 } 1208 return MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING; 1209 } 1210 return fr_supported ? MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING : 1211 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT; 1212 } 1213 1214 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1215 struct mlx5_ib_cq *recv_cq) 1216 { 1217 bool fr_supported = 1218 MLX5_CAP_ROCE(dev->mdev, qp_ts_format) == 1219 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1220 MLX5_CAP_ROCE(dev->mdev, qp_ts_format) == 1221 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1222 int ts_format = fr_supported ? MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 1223 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 1224 1225 if (recv_cq && 1226 recv_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) 1227 ts_format = MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING; 1228 1229 if (send_cq && 1230 send_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) 1231 ts_format = MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING; 1232 1233 if (ts_format == MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING && 1234 !fr_supported) { 1235 mlx5_ib_dbg(dev, "Free running TS format is not supported\n"); 1236 return -EOPNOTSUPP; 1237 } 1238 return ts_format; 1239 } 1240 1241 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1242 struct ib_udata *udata, 1243 struct mlx5_ib_sq *sq, void *qpin, 1244 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1245 { 1246 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1247 __be64 *pas; 1248 void *in; 1249 void *sqc; 1250 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1251 void *wq; 1252 int inlen; 1253 int err; 1254 unsigned int page_offset_quantized; 1255 unsigned long page_size; 1256 int ts_format; 1257 1258 ts_format = get_sq_ts_format(dev, cq); 1259 if (ts_format < 0) 1260 return ts_format; 1261 1262 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1263 ubuffer->buf_size, 0); 1264 if (IS_ERR(sq->ubuffer.umem)) 1265 return PTR_ERR(sq->ubuffer.umem); 1266 page_size = mlx5_umem_find_best_quantized_pgoff( 1267 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1268 page_offset, 64, &page_offset_quantized); 1269 if (!page_size) { 1270 err = -EINVAL; 1271 goto err_umem; 1272 } 1273 1274 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1275 sizeof(u64) * 1276 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1277 in = kvzalloc(inlen, GFP_KERNEL); 1278 if (!in) { 1279 err = -ENOMEM; 1280 goto err_umem; 1281 } 1282 1283 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1284 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1285 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1286 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1287 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1288 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1289 MLX5_SET(sqc, sqc, ts_format, ts_format); 1290 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1291 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1292 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1293 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1294 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1295 MLX5_CAP_ETH(dev->mdev, swp)) 1296 MLX5_SET(sqc, sqc, allow_swp, 1); 1297 1298 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1299 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1300 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1301 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1302 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1303 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1304 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1305 MLX5_SET(wq, wq, log_wq_pg_sz, 1306 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1307 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1308 1309 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1310 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1311 1312 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1313 1314 kvfree(in); 1315 1316 if (err) 1317 goto err_umem; 1318 1319 return 0; 1320 1321 err_umem: 1322 ib_umem_release(sq->ubuffer.umem); 1323 sq->ubuffer.umem = NULL; 1324 1325 return err; 1326 } 1327 1328 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1329 struct mlx5_ib_sq *sq) 1330 { 1331 destroy_flow_rule_vport_sq(sq); 1332 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1333 ib_umem_release(sq->ubuffer.umem); 1334 } 1335 1336 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1337 struct mlx5_ib_rq *rq, void *qpin, 1338 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1339 { 1340 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1341 __be64 *pas; 1342 void *in; 1343 void *rqc; 1344 void *wq; 1345 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1346 struct ib_umem *umem = rq->base.ubuffer.umem; 1347 unsigned int page_offset_quantized; 1348 unsigned long page_size = 0; 1349 int ts_format; 1350 size_t inlen; 1351 int err; 1352 1353 ts_format = get_rq_ts_format(dev, cq); 1354 if (ts_format < 0) 1355 return ts_format; 1356 1357 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1358 MLX5_ADAPTER_PAGE_SHIFT, 1359 page_offset, 64, 1360 &page_offset_quantized); 1361 if (!page_size) 1362 return -EINVAL; 1363 1364 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1365 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1366 in = kvzalloc(inlen, GFP_KERNEL); 1367 if (!in) 1368 return -ENOMEM; 1369 1370 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1371 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1372 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1373 MLX5_SET(rqc, rqc, vsd, 1); 1374 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1375 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1376 MLX5_SET(rqc, rqc, ts_format, ts_format); 1377 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1378 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1379 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1380 1381 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1382 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1383 1384 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1385 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1386 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1387 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1388 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1389 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1390 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1391 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1392 MLX5_SET(wq, wq, log_wq_pg_sz, 1393 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1394 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1395 1396 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1397 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1398 1399 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1400 1401 kvfree(in); 1402 1403 return err; 1404 } 1405 1406 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1407 struct mlx5_ib_rq *rq) 1408 { 1409 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1410 } 1411 1412 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1413 struct mlx5_ib_rq *rq, 1414 u32 qp_flags_en, 1415 struct ib_pd *pd) 1416 { 1417 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1418 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1419 mlx5_ib_disable_lb(dev, false, true); 1420 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1421 } 1422 1423 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1424 struct mlx5_ib_rq *rq, u32 tdn, 1425 u32 *qp_flags_en, struct ib_pd *pd, 1426 u32 *out) 1427 { 1428 u8 lb_flag = 0; 1429 u32 *in; 1430 void *tirc; 1431 int inlen; 1432 int err; 1433 1434 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1435 in = kvzalloc(inlen, GFP_KERNEL); 1436 if (!in) 1437 return -ENOMEM; 1438 1439 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1440 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1441 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1442 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1443 MLX5_SET(tirc, tirc, transport_domain, tdn); 1444 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1445 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1446 1447 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1448 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1449 1450 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1451 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1452 1453 if (dev->is_rep) { 1454 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1455 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1456 } 1457 1458 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1459 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1460 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1461 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1462 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1463 err = mlx5_ib_enable_lb(dev, false, true); 1464 1465 if (err) 1466 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1467 } 1468 kvfree(in); 1469 1470 return err; 1471 } 1472 1473 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1474 u32 *in, size_t inlen, struct ib_pd *pd, 1475 struct ib_udata *udata, 1476 struct mlx5_ib_create_qp_resp *resp, 1477 struct ib_qp_init_attr *init_attr) 1478 { 1479 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1480 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1481 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1482 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1483 udata, struct mlx5_ib_ucontext, ibucontext); 1484 int err; 1485 u32 tdn = mucontext->tdn; 1486 u16 uid = to_mpd(pd)->uid; 1487 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1488 1489 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1490 return -EINVAL; 1491 if (qp->sq.wqe_cnt) { 1492 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1493 if (err) 1494 return err; 1495 1496 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1497 to_mcq(init_attr->send_cq)); 1498 if (err) 1499 goto err_destroy_tis; 1500 1501 if (uid) { 1502 resp->tisn = sq->tisn; 1503 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1504 resp->sqn = sq->base.mqp.qpn; 1505 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1506 } 1507 1508 sq->base.container_mibqp = qp; 1509 sq->base.mqp.event = mlx5_ib_qp_event; 1510 } 1511 1512 if (qp->rq.wqe_cnt) { 1513 rq->base.container_mibqp = qp; 1514 1515 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1516 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1517 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1518 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1519 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1520 to_mcq(init_attr->recv_cq)); 1521 if (err) 1522 goto err_destroy_sq; 1523 1524 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1525 out); 1526 if (err) 1527 goto err_destroy_rq; 1528 1529 if (uid) { 1530 resp->rqn = rq->base.mqp.qpn; 1531 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1532 resp->tirn = rq->tirn; 1533 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1534 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1535 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1536 resp->tir_icm_addr = MLX5_GET( 1537 create_tir_out, out, icm_address_31_0); 1538 resp->tir_icm_addr |= 1539 (u64)MLX5_GET(create_tir_out, out, 1540 icm_address_39_32) 1541 << 32; 1542 resp->tir_icm_addr |= 1543 (u64)MLX5_GET(create_tir_out, out, 1544 icm_address_63_40) 1545 << 40; 1546 resp->comp_mask |= 1547 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1548 } 1549 } 1550 } 1551 1552 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1553 rq->base.mqp.qpn; 1554 return 0; 1555 1556 err_destroy_rq: 1557 destroy_raw_packet_qp_rq(dev, rq); 1558 err_destroy_sq: 1559 if (!qp->sq.wqe_cnt) 1560 return err; 1561 destroy_raw_packet_qp_sq(dev, sq); 1562 err_destroy_tis: 1563 destroy_raw_packet_qp_tis(dev, sq, pd); 1564 1565 return err; 1566 } 1567 1568 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1569 struct mlx5_ib_qp *qp) 1570 { 1571 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1572 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1573 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1574 1575 if (qp->rq.wqe_cnt) { 1576 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1577 destroy_raw_packet_qp_rq(dev, rq); 1578 } 1579 1580 if (qp->sq.wqe_cnt) { 1581 destroy_raw_packet_qp_sq(dev, sq); 1582 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1583 } 1584 } 1585 1586 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1587 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1588 { 1589 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1590 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1591 1592 sq->sq = &qp->sq; 1593 rq->rq = &qp->rq; 1594 sq->doorbell = &qp->db; 1595 rq->doorbell = &qp->db; 1596 } 1597 1598 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1599 { 1600 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1601 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1602 mlx5_ib_disable_lb(dev, false, true); 1603 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1604 to_mpd(qp->ibqp.pd)->uid); 1605 } 1606 1607 struct mlx5_create_qp_params { 1608 struct ib_udata *udata; 1609 size_t inlen; 1610 size_t outlen; 1611 size_t ucmd_size; 1612 void *ucmd; 1613 u8 is_rss_raw : 1; 1614 struct ib_qp_init_attr *attr; 1615 u32 uidx; 1616 struct mlx5_ib_create_qp_resp resp; 1617 }; 1618 1619 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1620 struct mlx5_ib_qp *qp, 1621 struct mlx5_create_qp_params *params) 1622 { 1623 struct ib_qp_init_attr *init_attr = params->attr; 1624 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1625 struct ib_udata *udata = params->udata; 1626 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1627 udata, struct mlx5_ib_ucontext, ibucontext); 1628 int inlen; 1629 int outlen; 1630 int err; 1631 u32 *in; 1632 u32 *out; 1633 void *tirc; 1634 void *hfso; 1635 u32 selected_fields = 0; 1636 u32 outer_l4; 1637 u32 tdn = mucontext->tdn; 1638 u8 lb_flag = 0; 1639 1640 if (ucmd->comp_mask) { 1641 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1642 return -EOPNOTSUPP; 1643 } 1644 1645 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1646 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1647 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1648 return -EOPNOTSUPP; 1649 } 1650 1651 if (dev->is_rep) 1652 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1653 1654 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1655 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1656 1657 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1658 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1659 1660 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1661 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1662 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1663 if (!in) 1664 return -ENOMEM; 1665 1666 out = in + MLX5_ST_SZ_DW(create_tir_in); 1667 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1668 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1669 MLX5_SET(tirc, tirc, disp_type, 1670 MLX5_TIRC_DISP_TYPE_INDIRECT); 1671 MLX5_SET(tirc, tirc, indirect_table, 1672 init_attr->rwq_ind_tbl->ind_tbl_num); 1673 MLX5_SET(tirc, tirc, transport_domain, tdn); 1674 1675 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1676 1677 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1678 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1679 1680 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1681 1682 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1683 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1684 else 1685 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1686 1687 switch (ucmd->rx_hash_function) { 1688 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1689 { 1690 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1691 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1692 1693 if (len != ucmd->rx_key_len) { 1694 err = -EINVAL; 1695 goto err; 1696 } 1697 1698 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1699 memcpy(rss_key, ucmd->rx_hash_key, len); 1700 break; 1701 } 1702 default: 1703 err = -EOPNOTSUPP; 1704 goto err; 1705 } 1706 1707 if (!ucmd->rx_hash_fields_mask) { 1708 /* special case when this TIR serves as steering entry without hashing */ 1709 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1710 goto create_tir; 1711 err = -EINVAL; 1712 goto err; 1713 } 1714 1715 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1716 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1717 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1718 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1719 err = -EINVAL; 1720 goto err; 1721 } 1722 1723 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1724 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1725 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1726 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1727 MLX5_L3_PROT_TYPE_IPV4); 1728 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1729 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1730 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1731 MLX5_L3_PROT_TYPE_IPV6); 1732 1733 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1734 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1735 << 0 | 1736 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1737 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1738 << 1 | 1739 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1740 1741 /* Check that only one l4 protocol is set */ 1742 if (outer_l4 & (outer_l4 - 1)) { 1743 err = -EINVAL; 1744 goto err; 1745 } 1746 1747 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1748 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1749 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1750 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1751 MLX5_L4_PROT_TYPE_TCP); 1752 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1753 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1754 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1755 MLX5_L4_PROT_TYPE_UDP); 1756 1757 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1758 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1759 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1760 1761 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1762 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1763 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1764 1765 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1766 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1767 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1768 1769 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1770 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1771 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1772 1773 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1774 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1775 1776 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1777 1778 create_tir: 1779 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1780 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1781 1782 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1783 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1784 err = mlx5_ib_enable_lb(dev, false, true); 1785 1786 if (err) 1787 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1788 to_mpd(pd)->uid); 1789 } 1790 1791 if (err) 1792 goto err; 1793 1794 if (mucontext->devx_uid) { 1795 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1796 params->resp.tirn = qp->rss_qp.tirn; 1797 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1798 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1799 params->resp.tir_icm_addr = 1800 MLX5_GET(create_tir_out, out, icm_address_31_0); 1801 params->resp.tir_icm_addr |= 1802 (u64)MLX5_GET(create_tir_out, out, 1803 icm_address_39_32) 1804 << 32; 1805 params->resp.tir_icm_addr |= 1806 (u64)MLX5_GET(create_tir_out, out, 1807 icm_address_63_40) 1808 << 40; 1809 params->resp.comp_mask |= 1810 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1811 } 1812 } 1813 1814 kvfree(in); 1815 /* qpn is reserved for that QP */ 1816 qp->trans_qp.base.mqp.qpn = 0; 1817 qp->is_rss = true; 1818 return 0; 1819 1820 err: 1821 kvfree(in); 1822 return err; 1823 } 1824 1825 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1826 struct mlx5_ib_qp *qp, 1827 struct ib_qp_init_attr *init_attr, 1828 void *qpc) 1829 { 1830 int scqe_sz; 1831 bool allow_scat_cqe = false; 1832 1833 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1834 1835 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1836 return; 1837 1838 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1839 if (scqe_sz == 128) { 1840 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1841 return; 1842 } 1843 1844 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1845 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1846 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1847 } 1848 1849 static int atomic_size_to_mode(int size_mask) 1850 { 1851 /* driver does not support atomic_size > 256B 1852 * and does not know how to translate bigger sizes 1853 */ 1854 int supported_size_mask = size_mask & 0x1ff; 1855 int log_max_size; 1856 1857 if (!supported_size_mask) 1858 return -EOPNOTSUPP; 1859 1860 log_max_size = __fls(supported_size_mask); 1861 1862 if (log_max_size > 3) 1863 return log_max_size; 1864 1865 return MLX5_ATOMIC_MODE_8B; 1866 } 1867 1868 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1869 enum ib_qp_type qp_type) 1870 { 1871 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1872 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1873 int atomic_mode = -EOPNOTSUPP; 1874 int atomic_size_mask; 1875 1876 if (!atomic) 1877 return -EOPNOTSUPP; 1878 1879 if (qp_type == MLX5_IB_QPT_DCT) 1880 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1881 else 1882 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1883 1884 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1885 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1886 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1887 1888 if (atomic_mode <= 0 && 1889 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1890 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1891 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1892 1893 return atomic_mode; 1894 } 1895 1896 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1897 struct mlx5_create_qp_params *params) 1898 { 1899 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1900 struct ib_qp_init_attr *attr = params->attr; 1901 u32 uidx = params->uidx; 1902 struct mlx5_ib_resources *devr = &dev->devr; 1903 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1904 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1905 struct mlx5_core_dev *mdev = dev->mdev; 1906 struct mlx5_ib_qp_base *base; 1907 unsigned long flags; 1908 void *qpc; 1909 u32 *in; 1910 int err; 1911 1912 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1913 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1914 1915 in = kvzalloc(inlen, GFP_KERNEL); 1916 if (!in) 1917 return -ENOMEM; 1918 1919 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd) 1920 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1921 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1922 1923 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 1924 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1925 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 1926 1927 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1928 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1929 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1930 MLX5_SET(qpc, qpc, cd_master, 1); 1931 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1932 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1933 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1934 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1935 1936 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1937 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 1938 MLX5_SET(qpc, qpc, no_sq, 1); 1939 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1940 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1941 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1942 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 1943 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1944 1945 /* 0xffffff means we ask to work with cqe version 0 */ 1946 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1947 MLX5_SET(qpc, qpc, user_index, uidx); 1948 1949 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1950 MLX5_SET(qpc, qpc, end_padding_mode, 1951 MLX5_WQ_END_PAD_MODE_ALIGN); 1952 /* Special case to clean flag */ 1953 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 1954 } 1955 1956 base = &qp->trans_qp.base; 1957 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 1958 kvfree(in); 1959 if (err) 1960 return err; 1961 1962 base->container_mibqp = qp; 1963 base->mqp.event = mlx5_ib_qp_event; 1964 if (MLX5_CAP_GEN(mdev, ece_support)) 1965 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 1966 1967 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1968 list_add_tail(&qp->qps_list, &dev->qp_list); 1969 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1970 1971 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 1972 return 0; 1973 } 1974 1975 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1976 struct mlx5_ib_qp *qp, 1977 struct mlx5_create_qp_params *params) 1978 { 1979 struct ib_qp_init_attr *init_attr = params->attr; 1980 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1981 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1982 struct ib_udata *udata = params->udata; 1983 u32 uidx = params->uidx; 1984 struct mlx5_ib_resources *devr = &dev->devr; 1985 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1986 struct mlx5_core_dev *mdev = dev->mdev; 1987 struct mlx5_ib_cq *send_cq; 1988 struct mlx5_ib_cq *recv_cq; 1989 unsigned long flags; 1990 struct mlx5_ib_qp_base *base; 1991 int ts_format; 1992 int mlx5_st; 1993 void *qpc; 1994 u32 *in; 1995 int err; 1996 1997 spin_lock_init(&qp->sq.lock); 1998 spin_lock_init(&qp->rq.lock); 1999 2000 mlx5_st = to_mlx5_st(qp->type); 2001 if (mlx5_st < 0) 2002 return -EINVAL; 2003 2004 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2005 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2006 2007 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2008 qp->underlay_qpn = init_attr->source_qpn; 2009 2010 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2011 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2012 &qp->raw_packet_qp.rq.base : 2013 &qp->trans_qp.base; 2014 2015 qp->has_rq = qp_has_rq(init_attr); 2016 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2017 if (err) { 2018 mlx5_ib_dbg(dev, "err %d\n", err); 2019 return err; 2020 } 2021 2022 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2023 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2024 return -EINVAL; 2025 2026 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2027 return -EINVAL; 2028 2029 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2030 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2031 to_mcq(init_attr->recv_cq)); 2032 if (ts_format < 0) 2033 return ts_format; 2034 } 2035 2036 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2037 &inlen, base, ucmd); 2038 if (err) 2039 return err; 2040 2041 if (is_sqp(init_attr->qp_type)) 2042 qp->port = init_attr->port_num; 2043 2044 if (MLX5_CAP_GEN(mdev, ece_support)) 2045 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2046 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2047 2048 MLX5_SET(qpc, qpc, st, mlx5_st); 2049 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2050 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2051 2052 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2053 MLX5_SET(qpc, qpc, wq_signature, 1); 2054 2055 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2056 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2057 2058 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2059 MLX5_SET(qpc, qpc, cd_master, 1); 2060 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2061 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2062 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2063 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2064 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2065 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2066 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2067 (init_attr->qp_type == IB_QPT_RC || 2068 init_attr->qp_type == IB_QPT_UC)) { 2069 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2070 2071 MLX5_SET(qpc, qpc, cs_res, 2072 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2073 MLX5_RES_SCAT_DATA32_CQE); 2074 } 2075 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2076 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2077 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2078 2079 if (qp->rq.wqe_cnt) { 2080 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2081 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2082 } 2083 2084 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2085 MLX5_SET(qpc, qpc, ts_format, ts_format); 2086 2087 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2088 2089 if (qp->sq.wqe_cnt) { 2090 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2091 } else { 2092 MLX5_SET(qpc, qpc, no_sq, 1); 2093 if (init_attr->srq && 2094 init_attr->srq->srq_type == IB_SRQT_TM) 2095 MLX5_SET(qpc, qpc, offload_type, 2096 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2097 } 2098 2099 /* Set default resources */ 2100 switch (init_attr->qp_type) { 2101 case IB_QPT_XRC_INI: 2102 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2103 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2104 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2105 break; 2106 default: 2107 if (init_attr->srq) { 2108 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2109 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2110 } else { 2111 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2112 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2113 } 2114 } 2115 2116 if (init_attr->send_cq) 2117 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2118 2119 if (init_attr->recv_cq) 2120 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2121 2122 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2123 2124 /* 0xffffff means we ask to work with cqe version 0 */ 2125 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2126 MLX5_SET(qpc, qpc, user_index, uidx); 2127 2128 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2129 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2130 MLX5_SET(qpc, qpc, end_padding_mode, 2131 MLX5_WQ_END_PAD_MODE_ALIGN); 2132 /* Special case to clean flag */ 2133 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2134 } 2135 2136 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2137 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2138 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2139 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2140 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2141 ¶ms->resp, init_attr); 2142 } else 2143 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2144 2145 kvfree(in); 2146 if (err) 2147 goto err_create; 2148 2149 base->container_mibqp = qp; 2150 base->mqp.event = mlx5_ib_qp_event; 2151 if (MLX5_CAP_GEN(mdev, ece_support)) 2152 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2153 2154 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2155 &send_cq, &recv_cq); 2156 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2157 mlx5_ib_lock_cqs(send_cq, recv_cq); 2158 /* Maintain device to QPs access, needed for further handling via reset 2159 * flow 2160 */ 2161 list_add_tail(&qp->qps_list, &dev->qp_list); 2162 /* Maintain CQ to QPs access, needed for further handling via reset flow 2163 */ 2164 if (send_cq) 2165 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2166 if (recv_cq) 2167 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2168 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2169 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2170 2171 return 0; 2172 2173 err_create: 2174 destroy_qp(dev, qp, base, udata); 2175 return err; 2176 } 2177 2178 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2179 struct mlx5_ib_qp *qp, 2180 struct mlx5_create_qp_params *params) 2181 { 2182 struct ib_qp_init_attr *attr = params->attr; 2183 u32 uidx = params->uidx; 2184 struct mlx5_ib_resources *devr = &dev->devr; 2185 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2186 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2187 struct mlx5_core_dev *mdev = dev->mdev; 2188 struct mlx5_ib_cq *send_cq; 2189 struct mlx5_ib_cq *recv_cq; 2190 unsigned long flags; 2191 struct mlx5_ib_qp_base *base; 2192 int mlx5_st; 2193 void *qpc; 2194 u32 *in; 2195 int err; 2196 2197 spin_lock_init(&qp->sq.lock); 2198 spin_lock_init(&qp->rq.lock); 2199 2200 mlx5_st = to_mlx5_st(qp->type); 2201 if (mlx5_st < 0) 2202 return -EINVAL; 2203 2204 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2205 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2206 2207 base = &qp->trans_qp.base; 2208 2209 qp->has_rq = qp_has_rq(attr); 2210 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2211 if (err) { 2212 mlx5_ib_dbg(dev, "err %d\n", err); 2213 return err; 2214 } 2215 2216 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2217 if (err) 2218 return err; 2219 2220 if (is_sqp(attr->qp_type)) 2221 qp->port = attr->port_num; 2222 2223 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2224 2225 MLX5_SET(qpc, qpc, st, mlx5_st); 2226 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2227 2228 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2229 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2230 else 2231 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2232 2233 2234 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2235 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2236 2237 if (qp->rq.wqe_cnt) { 2238 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2239 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2240 } 2241 2242 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2243 2244 if (qp->sq.wqe_cnt) 2245 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2246 else 2247 MLX5_SET(qpc, qpc, no_sq, 1); 2248 2249 if (attr->srq) { 2250 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2251 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2252 to_msrq(attr->srq)->msrq.srqn); 2253 } else { 2254 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2255 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2256 to_msrq(devr->s1)->msrq.srqn); 2257 } 2258 2259 if (attr->send_cq) 2260 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2261 2262 if (attr->recv_cq) 2263 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2264 2265 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2266 2267 /* 0xffffff means we ask to work with cqe version 0 */ 2268 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2269 MLX5_SET(qpc, qpc, user_index, uidx); 2270 2271 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2272 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2273 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2274 2275 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2276 kvfree(in); 2277 if (err) 2278 goto err_create; 2279 2280 base->container_mibqp = qp; 2281 base->mqp.event = mlx5_ib_qp_event; 2282 2283 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2284 &send_cq, &recv_cq); 2285 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2286 mlx5_ib_lock_cqs(send_cq, recv_cq); 2287 /* Maintain device to QPs access, needed for further handling via reset 2288 * flow 2289 */ 2290 list_add_tail(&qp->qps_list, &dev->qp_list); 2291 /* Maintain CQ to QPs access, needed for further handling via reset flow 2292 */ 2293 if (send_cq) 2294 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2295 if (recv_cq) 2296 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2297 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2298 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2299 2300 return 0; 2301 2302 err_create: 2303 destroy_qp(dev, qp, base, NULL); 2304 return err; 2305 } 2306 2307 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2308 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2309 { 2310 if (send_cq) { 2311 if (recv_cq) { 2312 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2313 spin_lock(&send_cq->lock); 2314 spin_lock_nested(&recv_cq->lock, 2315 SINGLE_DEPTH_NESTING); 2316 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2317 spin_lock(&send_cq->lock); 2318 __acquire(&recv_cq->lock); 2319 } else { 2320 spin_lock(&recv_cq->lock); 2321 spin_lock_nested(&send_cq->lock, 2322 SINGLE_DEPTH_NESTING); 2323 } 2324 } else { 2325 spin_lock(&send_cq->lock); 2326 __acquire(&recv_cq->lock); 2327 } 2328 } else if (recv_cq) { 2329 spin_lock(&recv_cq->lock); 2330 __acquire(&send_cq->lock); 2331 } else { 2332 __acquire(&send_cq->lock); 2333 __acquire(&recv_cq->lock); 2334 } 2335 } 2336 2337 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2338 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2339 { 2340 if (send_cq) { 2341 if (recv_cq) { 2342 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2343 spin_unlock(&recv_cq->lock); 2344 spin_unlock(&send_cq->lock); 2345 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2346 __release(&recv_cq->lock); 2347 spin_unlock(&send_cq->lock); 2348 } else { 2349 spin_unlock(&send_cq->lock); 2350 spin_unlock(&recv_cq->lock); 2351 } 2352 } else { 2353 __release(&recv_cq->lock); 2354 spin_unlock(&send_cq->lock); 2355 } 2356 } else if (recv_cq) { 2357 __release(&send_cq->lock); 2358 spin_unlock(&recv_cq->lock); 2359 } else { 2360 __release(&recv_cq->lock); 2361 __release(&send_cq->lock); 2362 } 2363 } 2364 2365 static void get_cqs(enum ib_qp_type qp_type, 2366 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2367 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2368 { 2369 switch (qp_type) { 2370 case IB_QPT_XRC_TGT: 2371 *send_cq = NULL; 2372 *recv_cq = NULL; 2373 break; 2374 case MLX5_IB_QPT_REG_UMR: 2375 case IB_QPT_XRC_INI: 2376 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2377 *recv_cq = NULL; 2378 break; 2379 2380 case IB_QPT_SMI: 2381 case MLX5_IB_QPT_HW_GSI: 2382 case IB_QPT_RC: 2383 case IB_QPT_UC: 2384 case IB_QPT_UD: 2385 case IB_QPT_RAW_PACKET: 2386 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2387 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2388 break; 2389 default: 2390 *send_cq = NULL; 2391 *recv_cq = NULL; 2392 break; 2393 } 2394 } 2395 2396 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2397 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2398 u8 lag_tx_affinity); 2399 2400 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2401 struct ib_udata *udata) 2402 { 2403 struct mlx5_ib_cq *send_cq, *recv_cq; 2404 struct mlx5_ib_qp_base *base; 2405 unsigned long flags; 2406 int err; 2407 2408 if (qp->is_rss) { 2409 destroy_rss_raw_qp_tir(dev, qp); 2410 return; 2411 } 2412 2413 base = (qp->type == IB_QPT_RAW_PACKET || 2414 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2415 &qp->raw_packet_qp.rq.base : 2416 &qp->trans_qp.base; 2417 2418 if (qp->state != IB_QPS_RESET) { 2419 if (qp->type != IB_QPT_RAW_PACKET && 2420 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2421 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2422 NULL, &base->mqp, NULL); 2423 } else { 2424 struct mlx5_modify_raw_qp_param raw_qp_param = { 2425 .operation = MLX5_CMD_OP_2RST_QP 2426 }; 2427 2428 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2429 } 2430 if (err) 2431 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2432 base->mqp.qpn); 2433 } 2434 2435 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2436 &recv_cq); 2437 2438 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2439 mlx5_ib_lock_cqs(send_cq, recv_cq); 2440 /* del from lists under both locks above to protect reset flow paths */ 2441 list_del(&qp->qps_list); 2442 if (send_cq) 2443 list_del(&qp->cq_send_list); 2444 2445 if (recv_cq) 2446 list_del(&qp->cq_recv_list); 2447 2448 if (!udata) { 2449 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2450 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2451 if (send_cq != recv_cq) 2452 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2453 NULL); 2454 } 2455 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2456 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2457 2458 if (qp->type == IB_QPT_RAW_PACKET || 2459 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2460 destroy_raw_packet_qp(dev, qp); 2461 } else { 2462 err = mlx5_core_destroy_qp(dev, &base->mqp); 2463 if (err) 2464 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2465 base->mqp.qpn); 2466 } 2467 2468 destroy_qp(dev, qp, base, udata); 2469 } 2470 2471 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2472 struct mlx5_ib_qp *qp, 2473 struct mlx5_create_qp_params *params) 2474 { 2475 struct ib_qp_init_attr *attr = params->attr; 2476 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2477 u32 uidx = params->uidx; 2478 void *dctc; 2479 2480 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2481 return -EOPNOTSUPP; 2482 2483 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2484 if (!qp->dct.in) 2485 return -ENOMEM; 2486 2487 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2488 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2489 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2490 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2491 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2492 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2493 MLX5_SET(dctc, dctc, user_index, uidx); 2494 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2495 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2496 2497 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2498 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2499 2500 if (rcqe_sz == 128) 2501 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2502 } 2503 2504 qp->state = IB_QPS_RESET; 2505 rdma_restrack_no_track(&qp->ibqp.res); 2506 return 0; 2507 } 2508 2509 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2510 enum ib_qp_type *type) 2511 { 2512 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2513 goto out; 2514 2515 switch (attr->qp_type) { 2516 case IB_QPT_XRC_TGT: 2517 case IB_QPT_XRC_INI: 2518 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2519 goto out; 2520 fallthrough; 2521 case IB_QPT_RC: 2522 case IB_QPT_UC: 2523 case IB_QPT_SMI: 2524 case MLX5_IB_QPT_HW_GSI: 2525 case IB_QPT_DRIVER: 2526 case IB_QPT_GSI: 2527 case IB_QPT_RAW_PACKET: 2528 case IB_QPT_UD: 2529 case MLX5_IB_QPT_REG_UMR: 2530 break; 2531 default: 2532 goto out; 2533 } 2534 2535 *type = attr->qp_type; 2536 return 0; 2537 2538 out: 2539 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2540 return -EOPNOTSUPP; 2541 } 2542 2543 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2544 struct ib_qp_init_attr *attr, 2545 struct ib_udata *udata) 2546 { 2547 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2548 udata, struct mlx5_ib_ucontext, ibucontext); 2549 2550 if (!udata) { 2551 /* Kernel create_qp callers */ 2552 if (attr->rwq_ind_tbl) 2553 return -EOPNOTSUPP; 2554 2555 switch (attr->qp_type) { 2556 case IB_QPT_RAW_PACKET: 2557 case IB_QPT_DRIVER: 2558 return -EOPNOTSUPP; 2559 default: 2560 return 0; 2561 } 2562 } 2563 2564 /* Userspace create_qp callers */ 2565 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2566 mlx5_ib_dbg(dev, 2567 "Raw Packet QP is only supported for CQE version > 0\n"); 2568 return -EINVAL; 2569 } 2570 2571 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2572 mlx5_ib_dbg(dev, 2573 "Wrong QP type %d for the RWQ indirect table\n", 2574 attr->qp_type); 2575 return -EINVAL; 2576 } 2577 2578 /* 2579 * We don't need to see this warning, it means that kernel code 2580 * missing ib_pd. Placed here to catch developer's mistakes. 2581 */ 2582 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2583 "There is a missing PD pointer assignment\n"); 2584 return 0; 2585 } 2586 2587 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2588 bool cond, struct mlx5_ib_qp *qp) 2589 { 2590 if (!(*flags & flag)) 2591 return; 2592 2593 if (cond) { 2594 qp->flags_en |= flag; 2595 *flags &= ~flag; 2596 return; 2597 } 2598 2599 switch (flag) { 2600 case MLX5_QP_FLAG_SCATTER_CQE: 2601 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2602 /* 2603 * We don't return error if these flags were provided, 2604 * and mlx5 doesn't have right capability. 2605 */ 2606 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2607 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2608 return; 2609 default: 2610 break; 2611 } 2612 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2613 } 2614 2615 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2616 void *ucmd, struct ib_qp_init_attr *attr) 2617 { 2618 struct mlx5_core_dev *mdev = dev->mdev; 2619 bool cond; 2620 int flags; 2621 2622 if (attr->rwq_ind_tbl) 2623 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2624 else 2625 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2626 2627 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2628 case MLX5_QP_FLAG_TYPE_DCI: 2629 qp->type = MLX5_IB_QPT_DCI; 2630 break; 2631 case MLX5_QP_FLAG_TYPE_DCT: 2632 qp->type = MLX5_IB_QPT_DCT; 2633 break; 2634 default: 2635 if (qp->type != IB_QPT_DRIVER) 2636 break; 2637 /* 2638 * It is IB_QPT_DRIVER and or no subtype or 2639 * wrong subtype were provided. 2640 */ 2641 return -EINVAL; 2642 } 2643 2644 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2645 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2646 2647 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2648 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2649 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2650 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2651 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2652 2653 if (qp->type == IB_QPT_RAW_PACKET) { 2654 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2655 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2656 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2657 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2658 cond, qp); 2659 process_vendor_flag(dev, &flags, 2660 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2661 qp); 2662 process_vendor_flag(dev, &flags, 2663 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2664 qp); 2665 } 2666 2667 if (qp->type == IB_QPT_RC) 2668 process_vendor_flag(dev, &flags, 2669 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2670 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2671 2672 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2673 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2674 2675 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2676 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2677 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2678 if (attr->rwq_ind_tbl && cond) { 2679 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2680 cond); 2681 return -EINVAL; 2682 } 2683 2684 if (flags) 2685 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2686 2687 return (flags) ? -EINVAL : 0; 2688 } 2689 2690 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2691 bool cond, struct mlx5_ib_qp *qp) 2692 { 2693 if (!(*flags & flag)) 2694 return; 2695 2696 if (cond) { 2697 qp->flags |= flag; 2698 *flags &= ~flag; 2699 return; 2700 } 2701 2702 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2703 /* 2704 * Special case, if condition didn't meet, it won't be error, 2705 * just different in-kernel flow. 2706 */ 2707 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2708 return; 2709 } 2710 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2711 } 2712 2713 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2714 struct ib_qp_init_attr *attr) 2715 { 2716 enum ib_qp_type qp_type = qp->type; 2717 struct mlx5_core_dev *mdev = dev->mdev; 2718 int create_flags = attr->create_flags; 2719 bool cond; 2720 2721 if (qp_type == MLX5_IB_QPT_DCT) 2722 return (create_flags) ? -EINVAL : 0; 2723 2724 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2725 return (create_flags) ? -EINVAL : 0; 2726 2727 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2728 mlx5_get_flow_namespace(dev->mdev, 2729 MLX5_FLOW_NAMESPACE_BYPASS), 2730 qp); 2731 process_create_flag(dev, &create_flags, 2732 IB_QP_CREATE_INTEGRITY_EN, 2733 MLX5_CAP_GEN(mdev, sho), qp); 2734 process_create_flag(dev, &create_flags, 2735 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2736 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2737 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2738 MLX5_CAP_GEN(mdev, cd), qp); 2739 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2740 MLX5_CAP_GEN(mdev, cd), qp); 2741 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2742 MLX5_CAP_GEN(mdev, cd), qp); 2743 2744 if (qp_type == IB_QPT_UD) { 2745 process_create_flag(dev, &create_flags, 2746 IB_QP_CREATE_IPOIB_UD_LSO, 2747 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2748 qp); 2749 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2750 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 2751 cond, qp); 2752 } 2753 2754 if (qp_type == IB_QPT_RAW_PACKET) { 2755 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2756 MLX5_CAP_ETH(mdev, scatter_fcs); 2757 process_create_flag(dev, &create_flags, 2758 IB_QP_CREATE_SCATTER_FCS, cond, qp); 2759 2760 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2761 MLX5_CAP_ETH(mdev, vlan_cap); 2762 process_create_flag(dev, &create_flags, 2763 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 2764 } 2765 2766 process_create_flag(dev, &create_flags, 2767 IB_QP_CREATE_PCI_WRITE_END_PADDING, 2768 MLX5_CAP_GEN(mdev, end_pad), qp); 2769 2770 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 2771 qp_type != MLX5_IB_QPT_REG_UMR, qp); 2772 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 2773 true, qp); 2774 2775 if (create_flags) { 2776 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 2777 create_flags); 2778 return -EOPNOTSUPP; 2779 } 2780 return 0; 2781 } 2782 2783 static int process_udata_size(struct mlx5_ib_dev *dev, 2784 struct mlx5_create_qp_params *params) 2785 { 2786 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 2787 struct ib_udata *udata = params->udata; 2788 size_t outlen = udata->outlen; 2789 size_t inlen = udata->inlen; 2790 2791 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 2792 params->ucmd_size = ucmd; 2793 if (!params->is_rss_raw) { 2794 /* User has old rdma-core, which doesn't support ECE */ 2795 size_t min_inlen = 2796 offsetof(struct mlx5_ib_create_qp, ece_options); 2797 2798 /* 2799 * We will check in check_ucmd_data() that user 2800 * cleared everything after inlen. 2801 */ 2802 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 2803 goto out; 2804 } 2805 2806 /* RSS RAW QP */ 2807 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 2808 return -EINVAL; 2809 2810 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 2811 return -EINVAL; 2812 2813 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 2814 params->ucmd_size = ucmd; 2815 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 2816 return -EINVAL; 2817 2818 params->inlen = min(ucmd, inlen); 2819 out: 2820 if (!params->inlen) 2821 mlx5_ib_dbg(dev, "udata is too small\n"); 2822 2823 return (params->inlen) ? 0 : -EINVAL; 2824 } 2825 2826 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2827 struct mlx5_ib_qp *qp, 2828 struct mlx5_create_qp_params *params) 2829 { 2830 int err; 2831 2832 if (params->is_rss_raw) { 2833 err = create_rss_raw_qp_tir(dev, pd, qp, params); 2834 goto out; 2835 } 2836 2837 switch (qp->type) { 2838 case MLX5_IB_QPT_DCT: 2839 err = create_dct(dev, pd, qp, params); 2840 break; 2841 case IB_QPT_XRC_TGT: 2842 err = create_xrc_tgt_qp(dev, qp, params); 2843 break; 2844 case IB_QPT_GSI: 2845 err = mlx5_ib_create_gsi(pd, qp, params->attr); 2846 break; 2847 default: 2848 if (params->udata) 2849 err = create_user_qp(dev, pd, qp, params); 2850 else 2851 err = create_kernel_qp(dev, pd, qp, params); 2852 } 2853 2854 out: 2855 if (err) { 2856 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 2857 return err; 2858 } 2859 2860 if (is_qp0(qp->type)) 2861 qp->ibqp.qp_num = 0; 2862 else if (is_qp1(qp->type)) 2863 qp->ibqp.qp_num = 1; 2864 else 2865 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2866 2867 mlx5_ib_dbg(dev, 2868 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 2869 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2870 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 2871 -1, 2872 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 2873 -1, 2874 params->resp.ece_options); 2875 2876 return 0; 2877 } 2878 2879 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2880 struct ib_qp_init_attr *attr) 2881 { 2882 int ret = 0; 2883 2884 switch (qp->type) { 2885 case MLX5_IB_QPT_DCT: 2886 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 2887 break; 2888 case MLX5_IB_QPT_DCI: 2889 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 2890 -EINVAL : 2891 0; 2892 break; 2893 case IB_QPT_RAW_PACKET: 2894 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 2895 break; 2896 default: 2897 break; 2898 } 2899 2900 if (ret) 2901 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 2902 2903 return ret; 2904 } 2905 2906 static int get_qp_uidx(struct mlx5_ib_qp *qp, 2907 struct mlx5_create_qp_params *params) 2908 { 2909 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2910 struct ib_udata *udata = params->udata; 2911 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2912 udata, struct mlx5_ib_ucontext, ibucontext); 2913 2914 if (params->is_rss_raw) 2915 return 0; 2916 2917 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 2918 } 2919 2920 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2921 { 2922 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2923 2924 if (mqp->state == IB_QPS_RTR) { 2925 int err; 2926 2927 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 2928 if (err) { 2929 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2930 return err; 2931 } 2932 } 2933 2934 kfree(mqp->dct.in); 2935 kfree(mqp); 2936 return 0; 2937 } 2938 2939 static int check_ucmd_data(struct mlx5_ib_dev *dev, 2940 struct mlx5_create_qp_params *params) 2941 { 2942 struct ib_udata *udata = params->udata; 2943 size_t size, last; 2944 int ret; 2945 2946 if (params->is_rss_raw) 2947 /* 2948 * These QPs don't have "reserved" field in their 2949 * create_qp input struct, so their data is always valid. 2950 */ 2951 last = sizeof(struct mlx5_ib_create_qp_rss); 2952 else 2953 last = offsetof(struct mlx5_ib_create_qp, reserved); 2954 2955 if (udata->inlen <= last) 2956 return 0; 2957 2958 /* 2959 * User provides different create_qp structures based on the 2960 * flow and we need to know if he cleared memory after our 2961 * struct create_qp ends. 2962 */ 2963 size = udata->inlen - last; 2964 ret = ib_is_udata_cleared(params->udata, last, size); 2965 if (!ret) 2966 mlx5_ib_dbg( 2967 dev, 2968 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 2969 udata->inlen, params->ucmd_size, last, size); 2970 return ret ? 0 : -EINVAL; 2971 } 2972 2973 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr, 2974 struct ib_udata *udata) 2975 { 2976 struct mlx5_create_qp_params params = {}; 2977 struct mlx5_ib_dev *dev; 2978 struct mlx5_ib_qp *qp; 2979 enum ib_qp_type type; 2980 int err; 2981 2982 dev = pd ? to_mdev(pd->device) : 2983 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device); 2984 2985 err = check_qp_type(dev, attr, &type); 2986 if (err) 2987 return ERR_PTR(err); 2988 2989 err = check_valid_flow(dev, pd, attr, udata); 2990 if (err) 2991 return ERR_PTR(err); 2992 2993 params.udata = udata; 2994 params.uidx = MLX5_IB_DEFAULT_UIDX; 2995 params.attr = attr; 2996 params.is_rss_raw = !!attr->rwq_ind_tbl; 2997 2998 if (udata) { 2999 err = process_udata_size(dev, ¶ms); 3000 if (err) 3001 return ERR_PTR(err); 3002 3003 err = check_ucmd_data(dev, ¶ms); 3004 if (err) 3005 return ERR_PTR(err); 3006 3007 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3008 if (!params.ucmd) 3009 return ERR_PTR(-ENOMEM); 3010 3011 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3012 if (err) 3013 goto free_ucmd; 3014 } 3015 3016 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 3017 if (!qp) { 3018 err = -ENOMEM; 3019 goto free_ucmd; 3020 } 3021 3022 mutex_init(&qp->mutex); 3023 qp->type = type; 3024 if (udata) { 3025 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3026 if (err) 3027 goto free_qp; 3028 3029 err = get_qp_uidx(qp, ¶ms); 3030 if (err) 3031 goto free_qp; 3032 } 3033 err = process_create_flags(dev, qp, attr); 3034 if (err) 3035 goto free_qp; 3036 3037 err = check_qp_attr(dev, qp, attr); 3038 if (err) 3039 goto free_qp; 3040 3041 err = create_qp(dev, pd, qp, ¶ms); 3042 if (err) 3043 goto free_qp; 3044 3045 kfree(params.ucmd); 3046 params.ucmd = NULL; 3047 3048 if (udata) 3049 /* 3050 * It is safe to copy response for all user create QP flows, 3051 * including MLX5_IB_QPT_DCT, which doesn't need it. 3052 * In that case, resp will be filled with zeros. 3053 */ 3054 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3055 if (err) 3056 goto destroy_qp; 3057 3058 return &qp->ibqp; 3059 3060 destroy_qp: 3061 switch (qp->type) { 3062 case MLX5_IB_QPT_DCT: 3063 mlx5_ib_destroy_dct(qp); 3064 break; 3065 case IB_QPT_GSI: 3066 mlx5_ib_destroy_gsi(qp); 3067 break; 3068 default: 3069 /* 3070 * These lines below are temp solution till QP allocation 3071 * will be moved to be under IB/core responsiblity. 3072 */ 3073 qp->ibqp.send_cq = attr->send_cq; 3074 qp->ibqp.recv_cq = attr->recv_cq; 3075 qp->ibqp.pd = pd; 3076 destroy_qp_common(dev, qp, udata); 3077 } 3078 3079 qp = NULL; 3080 free_qp: 3081 kfree(qp); 3082 free_ucmd: 3083 kfree(params.ucmd); 3084 return ERR_PTR(err); 3085 } 3086 3087 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3088 { 3089 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3090 struct mlx5_ib_qp *mqp = to_mqp(qp); 3091 3092 if (unlikely(qp->qp_type == IB_QPT_GSI)) 3093 return mlx5_ib_destroy_gsi(mqp); 3094 3095 if (mqp->type == MLX5_IB_QPT_DCT) 3096 return mlx5_ib_destroy_dct(mqp); 3097 3098 destroy_qp_common(dev, mqp, udata); 3099 3100 kfree(mqp); 3101 3102 return 0; 3103 } 3104 3105 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3106 const struct ib_qp_attr *attr, int attr_mask, 3107 void *qpc) 3108 { 3109 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3110 u8 dest_rd_atomic; 3111 u32 access_flags; 3112 3113 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3114 dest_rd_atomic = attr->max_dest_rd_atomic; 3115 else 3116 dest_rd_atomic = qp->trans_qp.resp_depth; 3117 3118 if (attr_mask & IB_QP_ACCESS_FLAGS) 3119 access_flags = attr->qp_access_flags; 3120 else 3121 access_flags = qp->trans_qp.atomic_rd_en; 3122 3123 if (!dest_rd_atomic) 3124 access_flags &= IB_ACCESS_REMOTE_WRITE; 3125 3126 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3127 3128 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3129 int atomic_mode; 3130 3131 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 3132 if (atomic_mode < 0) 3133 return -EOPNOTSUPP; 3134 3135 MLX5_SET(qpc, qpc, rae, 1); 3136 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3137 } 3138 3139 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3140 return 0; 3141 } 3142 3143 enum { 3144 MLX5_PATH_FLAG_FL = 1 << 0, 3145 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3146 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3147 }; 3148 3149 static int mlx5_to_ib_rate_map(u8 rate) 3150 { 3151 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3152 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3153 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3154 IB_RATE_400_GBPS }; 3155 3156 if (rate < ARRAY_SIZE(rates)) 3157 return rates[rate]; 3158 3159 return rate - MLX5_STAT_RATE_OFFSET; 3160 } 3161 3162 static int ib_to_mlx5_rate_map(u8 rate) 3163 { 3164 switch (rate) { 3165 case IB_RATE_PORT_CURRENT: 3166 return 0; 3167 case IB_RATE_56_GBPS: 3168 return 1; 3169 case IB_RATE_25_GBPS: 3170 return 2; 3171 case IB_RATE_100_GBPS: 3172 return 3; 3173 case IB_RATE_200_GBPS: 3174 return 4; 3175 case IB_RATE_50_GBPS: 3176 return 5; 3177 case IB_RATE_400_GBPS: 3178 return 6; 3179 default: 3180 return rate + MLX5_STAT_RATE_OFFSET; 3181 } 3182 3183 return 0; 3184 } 3185 3186 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3187 { 3188 u32 stat_rate_support; 3189 3190 if (rate == IB_RATE_PORT_CURRENT) 3191 return 0; 3192 3193 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3194 return -EINVAL; 3195 3196 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3197 while (rate != IB_RATE_PORT_CURRENT && 3198 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3199 --rate; 3200 3201 return ib_to_mlx5_rate_map(rate); 3202 } 3203 3204 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3205 struct mlx5_ib_sq *sq, u8 sl, 3206 struct ib_pd *pd) 3207 { 3208 void *in; 3209 void *tisc; 3210 int inlen; 3211 int err; 3212 3213 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3214 in = kvzalloc(inlen, GFP_KERNEL); 3215 if (!in) 3216 return -ENOMEM; 3217 3218 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3219 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3220 3221 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3222 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3223 3224 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3225 3226 kvfree(in); 3227 3228 return err; 3229 } 3230 3231 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3232 struct mlx5_ib_sq *sq, u8 tx_affinity, 3233 struct ib_pd *pd) 3234 { 3235 void *in; 3236 void *tisc; 3237 int inlen; 3238 int err; 3239 3240 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3241 in = kvzalloc(inlen, GFP_KERNEL); 3242 if (!in) 3243 return -ENOMEM; 3244 3245 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3246 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3247 3248 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3249 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3250 3251 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3252 3253 kvfree(in); 3254 3255 return err; 3256 } 3257 3258 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3259 u32 lqpn, u32 rqpn) 3260 3261 { 3262 u32 fl = ah->grh.flow_label; 3263 3264 if (!fl) 3265 fl = rdma_calc_flow_label(lqpn, rqpn); 3266 3267 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3268 } 3269 3270 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3271 const struct rdma_ah_attr *ah, void *path, u8 port, 3272 int attr_mask, u32 path_flags, 3273 const struct ib_qp_attr *attr, bool alt) 3274 { 3275 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3276 int err; 3277 enum ib_gid_type gid_type; 3278 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3279 u8 sl = rdma_ah_get_sl(ah); 3280 3281 if (attr_mask & IB_QP_PKEY_INDEX) 3282 MLX5_SET(ads, path, pkey_index, 3283 alt ? attr->alt_pkey_index : attr->pkey_index); 3284 3285 if (ah_flags & IB_AH_GRH) { 3286 const struct ib_port_immutable *immutable; 3287 3288 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3289 if (grh->sgid_index >= immutable->gid_tbl_len) { 3290 pr_err("sgid_index (%u) too large. max is %d\n", 3291 grh->sgid_index, 3292 immutable->gid_tbl_len); 3293 return -EINVAL; 3294 } 3295 } 3296 3297 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3298 if (!(ah_flags & IB_AH_GRH)) 3299 return -EINVAL; 3300 3301 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3302 ah->roce.dmac); 3303 if ((qp->ibqp.qp_type == IB_QPT_RC || 3304 qp->ibqp.qp_type == IB_QPT_UC || 3305 qp->ibqp.qp_type == IB_QPT_XRC_INI || 3306 qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 3307 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3308 (attr_mask & IB_QP_DEST_QPN)) 3309 mlx5_set_path_udp_sport(path, ah, 3310 qp->ibqp.qp_num, 3311 attr->dest_qp_num); 3312 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3313 gid_type = ah->grh.sgid_attr->gid_type; 3314 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3315 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3316 } else { 3317 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3318 MLX5_SET(ads, path, free_ar, 3319 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3320 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3321 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3322 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3323 MLX5_SET(ads, path, sl, sl); 3324 } 3325 3326 if (ah_flags & IB_AH_GRH) { 3327 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3328 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3329 MLX5_SET(ads, path, tclass, grh->traffic_class); 3330 MLX5_SET(ads, path, flow_label, grh->flow_label); 3331 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3332 sizeof(grh->dgid.raw)); 3333 } 3334 3335 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3336 if (err < 0) 3337 return err; 3338 MLX5_SET(ads, path, stat_rate, err); 3339 MLX5_SET(ads, path, vhca_port_num, port); 3340 3341 if (attr_mask & IB_QP_TIMEOUT) 3342 MLX5_SET(ads, path, ack_timeout, 3343 alt ? attr->alt_timeout : attr->timeout); 3344 3345 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3346 return modify_raw_packet_eth_prio(dev->mdev, 3347 &qp->raw_packet_qp.sq, 3348 sl & 0xf, qp->ibqp.pd); 3349 3350 return 0; 3351 } 3352 3353 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3354 [MLX5_QP_STATE_INIT] = { 3355 [MLX5_QP_STATE_INIT] = { 3356 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3357 MLX5_QP_OPTPAR_RAE | 3358 MLX5_QP_OPTPAR_RWE | 3359 MLX5_QP_OPTPAR_PKEY_INDEX | 3360 MLX5_QP_OPTPAR_PRI_PORT | 3361 MLX5_QP_OPTPAR_LAG_TX_AFF, 3362 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3363 MLX5_QP_OPTPAR_PKEY_INDEX | 3364 MLX5_QP_OPTPAR_PRI_PORT | 3365 MLX5_QP_OPTPAR_LAG_TX_AFF, 3366 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3367 MLX5_QP_OPTPAR_Q_KEY | 3368 MLX5_QP_OPTPAR_PRI_PORT, 3369 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3370 MLX5_QP_OPTPAR_RAE | 3371 MLX5_QP_OPTPAR_RWE | 3372 MLX5_QP_OPTPAR_PKEY_INDEX | 3373 MLX5_QP_OPTPAR_PRI_PORT | 3374 MLX5_QP_OPTPAR_LAG_TX_AFF, 3375 }, 3376 [MLX5_QP_STATE_RTR] = { 3377 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3378 MLX5_QP_OPTPAR_RRE | 3379 MLX5_QP_OPTPAR_RAE | 3380 MLX5_QP_OPTPAR_RWE | 3381 MLX5_QP_OPTPAR_PKEY_INDEX | 3382 MLX5_QP_OPTPAR_LAG_TX_AFF, 3383 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3384 MLX5_QP_OPTPAR_RWE | 3385 MLX5_QP_OPTPAR_PKEY_INDEX | 3386 MLX5_QP_OPTPAR_LAG_TX_AFF, 3387 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3388 MLX5_QP_OPTPAR_Q_KEY, 3389 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3390 MLX5_QP_OPTPAR_Q_KEY, 3391 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3392 MLX5_QP_OPTPAR_RRE | 3393 MLX5_QP_OPTPAR_RAE | 3394 MLX5_QP_OPTPAR_RWE | 3395 MLX5_QP_OPTPAR_PKEY_INDEX | 3396 MLX5_QP_OPTPAR_LAG_TX_AFF, 3397 }, 3398 }, 3399 [MLX5_QP_STATE_RTR] = { 3400 [MLX5_QP_STATE_RTS] = { 3401 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3402 MLX5_QP_OPTPAR_RRE | 3403 MLX5_QP_OPTPAR_RAE | 3404 MLX5_QP_OPTPAR_RWE | 3405 MLX5_QP_OPTPAR_PM_STATE | 3406 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3407 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3408 MLX5_QP_OPTPAR_RWE | 3409 MLX5_QP_OPTPAR_PM_STATE, 3410 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3411 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3412 MLX5_QP_OPTPAR_RRE | 3413 MLX5_QP_OPTPAR_RAE | 3414 MLX5_QP_OPTPAR_RWE | 3415 MLX5_QP_OPTPAR_PM_STATE | 3416 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3417 }, 3418 }, 3419 [MLX5_QP_STATE_RTS] = { 3420 [MLX5_QP_STATE_RTS] = { 3421 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3422 MLX5_QP_OPTPAR_RAE | 3423 MLX5_QP_OPTPAR_RWE | 3424 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3425 MLX5_QP_OPTPAR_PM_STATE | 3426 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3427 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3428 MLX5_QP_OPTPAR_PM_STATE | 3429 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3430 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3431 MLX5_QP_OPTPAR_SRQN | 3432 MLX5_QP_OPTPAR_CQN_RCV, 3433 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3434 MLX5_QP_OPTPAR_RAE | 3435 MLX5_QP_OPTPAR_RWE | 3436 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3437 MLX5_QP_OPTPAR_PM_STATE | 3438 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3439 }, 3440 }, 3441 [MLX5_QP_STATE_SQER] = { 3442 [MLX5_QP_STATE_RTS] = { 3443 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3444 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3445 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3446 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3447 MLX5_QP_OPTPAR_RWE | 3448 MLX5_QP_OPTPAR_RAE | 3449 MLX5_QP_OPTPAR_RRE, 3450 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3451 MLX5_QP_OPTPAR_RWE | 3452 MLX5_QP_OPTPAR_RAE | 3453 MLX5_QP_OPTPAR_RRE, 3454 }, 3455 }, 3456 }; 3457 3458 static int ib_nr_to_mlx5_nr(int ib_mask) 3459 { 3460 switch (ib_mask) { 3461 case IB_QP_STATE: 3462 return 0; 3463 case IB_QP_CUR_STATE: 3464 return 0; 3465 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3466 return 0; 3467 case IB_QP_ACCESS_FLAGS: 3468 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3469 MLX5_QP_OPTPAR_RAE; 3470 case IB_QP_PKEY_INDEX: 3471 return MLX5_QP_OPTPAR_PKEY_INDEX; 3472 case IB_QP_PORT: 3473 return MLX5_QP_OPTPAR_PRI_PORT; 3474 case IB_QP_QKEY: 3475 return MLX5_QP_OPTPAR_Q_KEY; 3476 case IB_QP_AV: 3477 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3478 MLX5_QP_OPTPAR_PRI_PORT; 3479 case IB_QP_PATH_MTU: 3480 return 0; 3481 case IB_QP_TIMEOUT: 3482 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3483 case IB_QP_RETRY_CNT: 3484 return MLX5_QP_OPTPAR_RETRY_COUNT; 3485 case IB_QP_RNR_RETRY: 3486 return MLX5_QP_OPTPAR_RNR_RETRY; 3487 case IB_QP_RQ_PSN: 3488 return 0; 3489 case IB_QP_MAX_QP_RD_ATOMIC: 3490 return MLX5_QP_OPTPAR_SRA_MAX; 3491 case IB_QP_ALT_PATH: 3492 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3493 case IB_QP_MIN_RNR_TIMER: 3494 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3495 case IB_QP_SQ_PSN: 3496 return 0; 3497 case IB_QP_MAX_DEST_RD_ATOMIC: 3498 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3499 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3500 case IB_QP_PATH_MIG_STATE: 3501 return MLX5_QP_OPTPAR_PM_STATE; 3502 case IB_QP_CAP: 3503 return 0; 3504 case IB_QP_DEST_QPN: 3505 return 0; 3506 } 3507 return 0; 3508 } 3509 3510 static int ib_mask_to_mlx5_opt(int ib_mask) 3511 { 3512 int result = 0; 3513 int i; 3514 3515 for (i = 0; i < 8 * sizeof(int); i++) { 3516 if ((1 << i) & ib_mask) 3517 result |= ib_nr_to_mlx5_nr(1 << i); 3518 } 3519 3520 return result; 3521 } 3522 3523 static int modify_raw_packet_qp_rq( 3524 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3525 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3526 { 3527 void *in; 3528 void *rqc; 3529 int inlen; 3530 int err; 3531 3532 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3533 in = kvzalloc(inlen, GFP_KERNEL); 3534 if (!in) 3535 return -ENOMEM; 3536 3537 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3538 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3539 3540 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3541 MLX5_SET(rqc, rqc, state, new_state); 3542 3543 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3544 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3545 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3546 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3547 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3548 } else 3549 dev_info_once( 3550 &dev->ib_dev.dev, 3551 "RAW PACKET QP counters are not supported on current FW\n"); 3552 } 3553 3554 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3555 if (err) 3556 goto out; 3557 3558 rq->state = new_state; 3559 3560 out: 3561 kvfree(in); 3562 return err; 3563 } 3564 3565 static int modify_raw_packet_qp_sq( 3566 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3567 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3568 { 3569 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3570 struct mlx5_rate_limit old_rl = ibqp->rl; 3571 struct mlx5_rate_limit new_rl = old_rl; 3572 bool new_rate_added = false; 3573 u16 rl_index = 0; 3574 void *in; 3575 void *sqc; 3576 int inlen; 3577 int err; 3578 3579 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3580 in = kvzalloc(inlen, GFP_KERNEL); 3581 if (!in) 3582 return -ENOMEM; 3583 3584 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3585 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3586 3587 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3588 MLX5_SET(sqc, sqc, state, new_state); 3589 3590 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3591 if (new_state != MLX5_SQC_STATE_RDY) 3592 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3593 __func__); 3594 else 3595 new_rl = raw_qp_param->rl; 3596 } 3597 3598 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3599 if (new_rl.rate) { 3600 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3601 if (err) { 3602 pr_err("Failed configuring rate limit(err %d): \ 3603 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3604 err, new_rl.rate, new_rl.max_burst_sz, 3605 new_rl.typical_pkt_sz); 3606 3607 goto out; 3608 } 3609 new_rate_added = true; 3610 } 3611 3612 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3613 /* index 0 means no limit */ 3614 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3615 } 3616 3617 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3618 if (err) { 3619 /* Remove new rate from table if failed */ 3620 if (new_rate_added) 3621 mlx5_rl_remove_rate(dev, &new_rl); 3622 goto out; 3623 } 3624 3625 /* Only remove the old rate after new rate was set */ 3626 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3627 (new_state != MLX5_SQC_STATE_RDY)) { 3628 mlx5_rl_remove_rate(dev, &old_rl); 3629 if (new_state != MLX5_SQC_STATE_RDY) 3630 memset(&new_rl, 0, sizeof(new_rl)); 3631 } 3632 3633 ibqp->rl = new_rl; 3634 sq->state = new_state; 3635 3636 out: 3637 kvfree(in); 3638 return err; 3639 } 3640 3641 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3642 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3643 u8 tx_affinity) 3644 { 3645 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3646 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3647 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3648 int modify_rq = !!qp->rq.wqe_cnt; 3649 int modify_sq = !!qp->sq.wqe_cnt; 3650 int rq_state; 3651 int sq_state; 3652 int err; 3653 3654 switch (raw_qp_param->operation) { 3655 case MLX5_CMD_OP_RST2INIT_QP: 3656 rq_state = MLX5_RQC_STATE_RDY; 3657 sq_state = MLX5_SQC_STATE_RST; 3658 break; 3659 case MLX5_CMD_OP_2ERR_QP: 3660 rq_state = MLX5_RQC_STATE_ERR; 3661 sq_state = MLX5_SQC_STATE_ERR; 3662 break; 3663 case MLX5_CMD_OP_2RST_QP: 3664 rq_state = MLX5_RQC_STATE_RST; 3665 sq_state = MLX5_SQC_STATE_RST; 3666 break; 3667 case MLX5_CMD_OP_RTR2RTS_QP: 3668 case MLX5_CMD_OP_RTS2RTS_QP: 3669 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3670 return -EINVAL; 3671 3672 modify_rq = 0; 3673 sq_state = MLX5_SQC_STATE_RDY; 3674 break; 3675 case MLX5_CMD_OP_INIT2INIT_QP: 3676 case MLX5_CMD_OP_INIT2RTR_QP: 3677 if (raw_qp_param->set_mask) 3678 return -EINVAL; 3679 else 3680 return 0; 3681 default: 3682 WARN_ON(1); 3683 return -EINVAL; 3684 } 3685 3686 if (modify_rq) { 3687 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3688 qp->ibqp.pd); 3689 if (err) 3690 return err; 3691 } 3692 3693 if (modify_sq) { 3694 struct mlx5_flow_handle *flow_rule; 3695 3696 if (tx_affinity) { 3697 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3698 tx_affinity, 3699 qp->ibqp.pd); 3700 if (err) 3701 return err; 3702 } 3703 3704 flow_rule = create_flow_rule_vport_sq(dev, sq, 3705 raw_qp_param->port); 3706 if (IS_ERR(flow_rule)) 3707 return PTR_ERR(flow_rule); 3708 3709 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3710 raw_qp_param, qp->ibqp.pd); 3711 if (err) { 3712 if (flow_rule) 3713 mlx5_del_flow_rules(flow_rule); 3714 return err; 3715 } 3716 3717 if (flow_rule) { 3718 destroy_flow_rule_vport_sq(sq); 3719 sq->flow_rule = flow_rule; 3720 } 3721 3722 return err; 3723 } 3724 3725 return 0; 3726 } 3727 3728 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3729 struct ib_udata *udata) 3730 { 3731 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3732 udata, struct mlx5_ib_ucontext, ibucontext); 3733 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3734 atomic_t *tx_port_affinity; 3735 3736 if (ucontext) 3737 tx_port_affinity = &ucontext->tx_port_affinity; 3738 else 3739 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3740 3741 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3742 MLX5_MAX_PORTS + 1; 3743 } 3744 3745 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3746 { 3747 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3748 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3749 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3750 (qp->type == MLX5_IB_QPT_DCI)) 3751 return true; 3752 return false; 3753 } 3754 3755 static unsigned int get_tx_affinity(struct ib_qp *qp, 3756 const struct ib_qp_attr *attr, 3757 int attr_mask, u8 init, 3758 struct ib_udata *udata) 3759 { 3760 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3761 udata, struct mlx5_ib_ucontext, ibucontext); 3762 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3763 struct mlx5_ib_qp *mqp = to_mqp(qp); 3764 struct mlx5_ib_qp_base *qp_base; 3765 unsigned int tx_affinity; 3766 3767 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 3768 qp_supports_affinity(mqp))) 3769 return 0; 3770 3771 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3772 tx_affinity = mqp->gsi_lag_port; 3773 else if (init) 3774 tx_affinity = get_tx_affinity_rr(dev, udata); 3775 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 3776 tx_affinity = 3777 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 3778 else 3779 return 0; 3780 3781 qp_base = &mqp->trans_qp.base; 3782 if (ucontext) 3783 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3784 tx_affinity, qp_base->mqp.qpn, ucontext); 3785 else 3786 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3787 tx_affinity, qp_base->mqp.qpn); 3788 return tx_affinity; 3789 } 3790 3791 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3792 struct rdma_counter *counter) 3793 { 3794 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3795 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 3796 struct mlx5_ib_qp *mqp = to_mqp(qp); 3797 struct mlx5_ib_qp_base *base; 3798 u32 set_id; 3799 u32 *qpc; 3800 3801 if (counter) 3802 set_id = counter->id; 3803 else 3804 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3805 3806 base = &mqp->trans_qp.base; 3807 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 3808 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 3809 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 3810 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 3811 MLX5_QP_OPTPAR_COUNTER_SET_ID); 3812 3813 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 3814 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3815 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 3816 } 3817 3818 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3819 const struct ib_qp_attr *attr, int attr_mask, 3820 enum ib_qp_state cur_state, 3821 enum ib_qp_state new_state, 3822 const struct mlx5_ib_modify_qp *ucmd, 3823 struct mlx5_ib_modify_qp_resp *resp, 3824 struct ib_udata *udata) 3825 { 3826 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3827 [MLX5_QP_STATE_RST] = { 3828 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3829 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3830 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3831 }, 3832 [MLX5_QP_STATE_INIT] = { 3833 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3834 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3835 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3836 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3837 }, 3838 [MLX5_QP_STATE_RTR] = { 3839 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3840 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3841 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3842 }, 3843 [MLX5_QP_STATE_RTS] = { 3844 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3845 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3846 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3847 }, 3848 [MLX5_QP_STATE_SQD] = { 3849 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3850 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3851 }, 3852 [MLX5_QP_STATE_SQER] = { 3853 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3854 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3855 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3856 }, 3857 [MLX5_QP_STATE_ERR] = { 3858 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3859 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3860 } 3861 }; 3862 3863 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3864 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3865 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3866 struct mlx5_ib_cq *send_cq, *recv_cq; 3867 struct mlx5_ib_pd *pd; 3868 enum mlx5_qp_state mlx5_cur, mlx5_new; 3869 void *qpc, *pri_path, *alt_path; 3870 enum mlx5_qp_optpar optpar = 0; 3871 u32 set_id = 0; 3872 int mlx5_st; 3873 int err; 3874 u16 op; 3875 u8 tx_affinity = 0; 3876 3877 mlx5_st = to_mlx5_st(qp->type); 3878 if (mlx5_st < 0) 3879 return -EINVAL; 3880 3881 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 3882 if (!qpc) 3883 return -ENOMEM; 3884 3885 pd = to_mpd(qp->ibqp.pd); 3886 MLX5_SET(qpc, qpc, st, mlx5_st); 3887 3888 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3889 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3890 } else { 3891 switch (attr->path_mig_state) { 3892 case IB_MIG_MIGRATED: 3893 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3894 break; 3895 case IB_MIG_REARM: 3896 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 3897 break; 3898 case IB_MIG_ARMED: 3899 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 3900 break; 3901 } 3902 } 3903 3904 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 3905 cur_state == IB_QPS_RESET && 3906 new_state == IB_QPS_INIT, udata); 3907 3908 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 3909 if (tx_affinity && new_state == IB_QPS_RTR && 3910 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 3911 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 3912 3913 if (is_sqp(ibqp->qp_type)) { 3914 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 3915 MLX5_SET(qpc, qpc, log_msg_max, 8); 3916 } else if ((ibqp->qp_type == IB_QPT_UD && 3917 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 3918 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3919 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 3920 MLX5_SET(qpc, qpc, log_msg_max, 12); 3921 } else if (attr_mask & IB_QP_PATH_MTU) { 3922 if (attr->path_mtu < IB_MTU_256 || 3923 attr->path_mtu > IB_MTU_4096) { 3924 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3925 err = -EINVAL; 3926 goto out; 3927 } 3928 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 3929 MLX5_SET(qpc, qpc, log_msg_max, 3930 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 3931 } 3932 3933 if (attr_mask & IB_QP_DEST_QPN) 3934 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 3935 3936 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 3937 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 3938 3939 if (attr_mask & IB_QP_PKEY_INDEX) 3940 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 3941 3942 /* todo implement counter_index functionality */ 3943 3944 if (is_sqp(ibqp->qp_type)) 3945 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 3946 3947 if (attr_mask & IB_QP_PORT) 3948 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 3949 3950 if (attr_mask & IB_QP_AV) { 3951 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 3952 attr_mask & IB_QP_PORT ? attr->port_num : 3953 qp->port, 3954 attr_mask, 0, attr, false); 3955 if (err) 3956 goto out; 3957 } 3958 3959 if (attr_mask & IB_QP_TIMEOUT) 3960 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 3961 3962 if (attr_mask & IB_QP_ALT_PATH) { 3963 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 3964 attr->alt_port_num, 3965 attr_mask | IB_QP_PKEY_INDEX | 3966 IB_QP_TIMEOUT, 3967 0, attr, true); 3968 if (err) 3969 goto out; 3970 } 3971 3972 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3973 &send_cq, &recv_cq); 3974 3975 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3976 if (send_cq) 3977 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 3978 if (recv_cq) 3979 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 3980 3981 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 3982 3983 if (attr_mask & IB_QP_RNR_RETRY) 3984 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 3985 3986 if (attr_mask & IB_QP_RETRY_CNT) 3987 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 3988 3989 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 3990 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 3991 3992 if (attr_mask & IB_QP_SQ_PSN) 3993 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 3994 3995 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 3996 MLX5_SET(qpc, qpc, log_rra_max, 3997 ilog2(attr->max_dest_rd_atomic)); 3998 3999 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4000 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4001 if (err) 4002 goto out; 4003 } 4004 4005 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4006 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4007 4008 if (attr_mask & IB_QP_RQ_PSN) 4009 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4010 4011 if (attr_mask & IB_QP_QKEY) 4012 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4013 4014 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4015 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4016 4017 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4018 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4019 qp->port) - 1; 4020 4021 /* Underlay port should be used - index 0 function per port */ 4022 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4023 port_num = 0; 4024 4025 if (ibqp->counter) 4026 set_id = ibqp->counter->id; 4027 else 4028 set_id = mlx5_ib_get_counters_id(dev, port_num); 4029 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4030 } 4031 4032 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4033 MLX5_SET(qpc, qpc, rlky, 1); 4034 4035 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4036 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4037 4038 mlx5_cur = to_mlx5_state(cur_state); 4039 mlx5_new = to_mlx5_state(new_state); 4040 4041 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4042 !optab[mlx5_cur][mlx5_new]) { 4043 err = -EINVAL; 4044 goto out; 4045 } 4046 4047 op = optab[mlx5_cur][mlx5_new]; 4048 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4049 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4050 4051 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4052 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4053 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4054 4055 raw_qp_param.operation = op; 4056 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4057 raw_qp_param.rq_q_ctr_id = set_id; 4058 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4059 } 4060 4061 if (attr_mask & IB_QP_PORT) 4062 raw_qp_param.port = attr->port_num; 4063 4064 if (attr_mask & IB_QP_RATE_LIMIT) { 4065 raw_qp_param.rl.rate = attr->rate_limit; 4066 4067 if (ucmd->burst_info.max_burst_sz) { 4068 if (attr->rate_limit && 4069 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4070 raw_qp_param.rl.max_burst_sz = 4071 ucmd->burst_info.max_burst_sz; 4072 } else { 4073 err = -EINVAL; 4074 goto out; 4075 } 4076 } 4077 4078 if (ucmd->burst_info.typical_pkt_sz) { 4079 if (attr->rate_limit && 4080 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4081 raw_qp_param.rl.typical_pkt_sz = 4082 ucmd->burst_info.typical_pkt_sz; 4083 } else { 4084 err = -EINVAL; 4085 goto out; 4086 } 4087 } 4088 4089 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4090 } 4091 4092 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4093 } else { 4094 if (udata) { 4095 /* For the kernel flows, the resp will stay zero */ 4096 resp->ece_options = 4097 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4098 ucmd->ece_options : 0; 4099 resp->response_length = sizeof(*resp); 4100 } 4101 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4102 &resp->ece_options); 4103 } 4104 4105 if (err) 4106 goto out; 4107 4108 qp->state = new_state; 4109 4110 if (attr_mask & IB_QP_ACCESS_FLAGS) 4111 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4112 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4113 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4114 if (attr_mask & IB_QP_PORT) 4115 qp->port = attr->port_num; 4116 if (attr_mask & IB_QP_ALT_PATH) 4117 qp->trans_qp.alt_port = attr->alt_port_num; 4118 4119 /* 4120 * If we moved a kernel QP to RESET, clean up all old CQ 4121 * entries and reinitialize the QP. 4122 */ 4123 if (new_state == IB_QPS_RESET && 4124 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 4125 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4126 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4127 if (send_cq != recv_cq) 4128 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4129 4130 qp->rq.head = 0; 4131 qp->rq.tail = 0; 4132 qp->sq.head = 0; 4133 qp->sq.tail = 0; 4134 qp->sq.cur_post = 0; 4135 if (qp->sq.wqe_cnt) 4136 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4137 qp->sq.last_poll = 0; 4138 qp->db.db[MLX5_RCV_DBR] = 0; 4139 qp->db.db[MLX5_SND_DBR] = 0; 4140 } 4141 4142 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4143 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4144 if (!err) 4145 qp->counter_pending = 0; 4146 } 4147 4148 out: 4149 kfree(qpc); 4150 return err; 4151 } 4152 4153 static inline bool is_valid_mask(int mask, int req, int opt) 4154 { 4155 if ((mask & req) != req) 4156 return false; 4157 4158 if (mask & ~(req | opt)) 4159 return false; 4160 4161 return true; 4162 } 4163 4164 /* check valid transition for driver QP types 4165 * for now the only QP type that this function supports is DCI 4166 */ 4167 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4168 enum ib_qp_attr_mask attr_mask) 4169 { 4170 int req = IB_QP_STATE; 4171 int opt = 0; 4172 4173 if (new_state == IB_QPS_RESET) { 4174 return is_valid_mask(attr_mask, req, opt); 4175 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4176 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4177 return is_valid_mask(attr_mask, req, opt); 4178 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4179 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4180 return is_valid_mask(attr_mask, req, opt); 4181 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4182 req |= IB_QP_PATH_MTU; 4183 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4184 return is_valid_mask(attr_mask, req, opt); 4185 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4186 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4187 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4188 opt = IB_QP_MIN_RNR_TIMER; 4189 return is_valid_mask(attr_mask, req, opt); 4190 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4191 opt = IB_QP_MIN_RNR_TIMER; 4192 return is_valid_mask(attr_mask, req, opt); 4193 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4194 return is_valid_mask(attr_mask, req, opt); 4195 } 4196 return false; 4197 } 4198 4199 /* mlx5_ib_modify_dct: modify a DCT QP 4200 * valid transitions are: 4201 * RESET to INIT: must set access_flags, pkey_index and port 4202 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4203 * mtu, gid_index and hop_limit 4204 * Other transitions and attributes are illegal 4205 */ 4206 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4207 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4208 struct ib_udata *udata) 4209 { 4210 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4211 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4212 enum ib_qp_state cur_state, new_state; 4213 int required = IB_QP_STATE; 4214 void *dctc; 4215 int err; 4216 4217 if (!(attr_mask & IB_QP_STATE)) 4218 return -EINVAL; 4219 4220 cur_state = qp->state; 4221 new_state = attr->qp_state; 4222 4223 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4224 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4225 /* 4226 * DCT doesn't initialize QP till modify command is executed, 4227 * so we need to overwrite previously set ECE field if user 4228 * provided any value except zero, which means not set/not 4229 * valid. 4230 */ 4231 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4232 4233 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4234 u16 set_id; 4235 4236 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4237 if (!is_valid_mask(attr_mask, required, 0)) 4238 return -EINVAL; 4239 4240 if (attr->port_num == 0 || 4241 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4242 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4243 attr->port_num, dev->num_ports); 4244 return -EINVAL; 4245 } 4246 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4247 MLX5_SET(dctc, dctc, rre, 1); 4248 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4249 MLX5_SET(dctc, dctc, rwe, 1); 4250 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4251 int atomic_mode; 4252 4253 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4254 if (atomic_mode < 0) 4255 return -EOPNOTSUPP; 4256 4257 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4258 MLX5_SET(dctc, dctc, rae, 1); 4259 } 4260 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4261 if (mlx5_lag_is_active(dev->mdev)) 4262 MLX5_SET(dctc, dctc, port, 4263 get_tx_affinity_rr(dev, udata)); 4264 else 4265 MLX5_SET(dctc, dctc, port, attr->port_num); 4266 4267 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4268 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4269 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4270 struct mlx5_ib_modify_qp_resp resp = {}; 4271 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4272 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4273 4274 if (udata->outlen < min_resp_len) 4275 return -EINVAL; 4276 /* 4277 * If we don't have enough space for the ECE options, 4278 * simply indicate it with resp.response_length. 4279 */ 4280 resp.response_length = (udata->outlen < sizeof(resp)) ? 4281 min_resp_len : 4282 sizeof(resp); 4283 4284 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4285 if (!is_valid_mask(attr_mask, required, 0)) 4286 return -EINVAL; 4287 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4288 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4289 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4290 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4291 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4292 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4293 4294 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4295 MLX5_ST_SZ_BYTES(create_dct_in), out, 4296 sizeof(out)); 4297 if (err) 4298 return err; 4299 resp.dctn = qp->dct.mdct.mqp.qpn; 4300 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4301 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4302 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4303 if (err) { 4304 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4305 return err; 4306 } 4307 } else { 4308 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4309 return -EINVAL; 4310 } 4311 4312 qp->state = new_state; 4313 return 0; 4314 } 4315 4316 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4317 struct mlx5_ib_qp *qp, 4318 enum ib_qp_type qp_type) 4319 { 4320 if (dev->profile != &raw_eth_profile) 4321 return true; 4322 4323 if (qp_type == IB_QPT_RAW_PACKET || qp_type == MLX5_IB_QPT_REG_UMR) 4324 return true; 4325 4326 /* Internal QP used for wc testing, with NOPs in wq */ 4327 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 4328 return true; 4329 4330 return false; 4331 } 4332 4333 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4334 int attr_mask, struct ib_udata *udata) 4335 { 4336 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4337 struct mlx5_ib_modify_qp_resp resp = {}; 4338 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4339 struct mlx5_ib_modify_qp ucmd = {}; 4340 enum ib_qp_type qp_type; 4341 enum ib_qp_state cur_state, new_state; 4342 int err = -EINVAL; 4343 4344 if (!mlx5_ib_modify_qp_allowed(dev, qp, ibqp->qp_type)) 4345 return -EOPNOTSUPP; 4346 4347 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4348 return -EOPNOTSUPP; 4349 4350 if (ibqp->rwq_ind_tbl) 4351 return -ENOSYS; 4352 4353 if (udata && udata->inlen) { 4354 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4355 return -EINVAL; 4356 4357 if (udata->inlen > sizeof(ucmd) && 4358 !ib_is_udata_cleared(udata, sizeof(ucmd), 4359 udata->inlen - sizeof(ucmd))) 4360 return -EOPNOTSUPP; 4361 4362 if (ib_copy_from_udata(&ucmd, udata, 4363 min(udata->inlen, sizeof(ucmd)))) 4364 return -EFAULT; 4365 4366 if (ucmd.comp_mask || 4367 memchr_inv(&ucmd.burst_info.reserved, 0, 4368 sizeof(ucmd.burst_info.reserved))) 4369 return -EOPNOTSUPP; 4370 4371 } 4372 4373 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4374 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4375 4376 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI : 4377 qp->type; 4378 4379 if (qp_type == MLX5_IB_QPT_DCT) 4380 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4381 4382 mutex_lock(&qp->mutex); 4383 4384 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4385 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4386 4387 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4388 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4389 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4390 attr_mask); 4391 goto out; 4392 } 4393 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4394 qp_type != MLX5_IB_QPT_DCI && 4395 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4396 attr_mask)) { 4397 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4398 cur_state, new_state, ibqp->qp_type, attr_mask); 4399 goto out; 4400 } else if (qp_type == MLX5_IB_QPT_DCI && 4401 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4402 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4403 cur_state, new_state, qp_type, attr_mask); 4404 goto out; 4405 } 4406 4407 if ((attr_mask & IB_QP_PORT) && 4408 (attr->port_num == 0 || 4409 attr->port_num > dev->num_ports)) { 4410 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4411 attr->port_num, dev->num_ports); 4412 goto out; 4413 } 4414 4415 if ((attr_mask & IB_QP_PKEY_INDEX) && 4416 attr->pkey_index >= dev->pkey_table_len) { 4417 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4418 goto out; 4419 } 4420 4421 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4422 attr->max_rd_atomic > 4423 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4424 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4425 attr->max_rd_atomic); 4426 goto out; 4427 } 4428 4429 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4430 attr->max_dest_rd_atomic > 4431 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4432 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4433 attr->max_dest_rd_atomic); 4434 goto out; 4435 } 4436 4437 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4438 err = 0; 4439 goto out; 4440 } 4441 4442 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4443 new_state, &ucmd, &resp, udata); 4444 4445 /* resp.response_length is set in ECE supported flows only */ 4446 if (!err && resp.response_length && 4447 udata->outlen >= resp.response_length) 4448 /* Return -EFAULT to the user and expect him to destroy QP. */ 4449 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4450 4451 out: 4452 mutex_unlock(&qp->mutex); 4453 return err; 4454 } 4455 4456 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4457 { 4458 switch (mlx5_state) { 4459 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4460 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4461 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4462 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4463 case MLX5_QP_STATE_SQ_DRAINING: 4464 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4465 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4466 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4467 default: return -1; 4468 } 4469 } 4470 4471 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4472 { 4473 switch (mlx5_mig_state) { 4474 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4475 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4476 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4477 default: return -1; 4478 } 4479 } 4480 4481 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4482 struct rdma_ah_attr *ah_attr, void *path) 4483 { 4484 int port = MLX5_GET(ads, path, vhca_port_num); 4485 int static_rate; 4486 4487 memset(ah_attr, 0, sizeof(*ah_attr)); 4488 4489 if (!port || port > ibdev->num_ports) 4490 return; 4491 4492 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4493 4494 rdma_ah_set_port_num(ah_attr, port); 4495 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4496 4497 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4498 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4499 4500 static_rate = MLX5_GET(ads, path, stat_rate); 4501 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4502 if (MLX5_GET(ads, path, grh) || 4503 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4504 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4505 MLX5_GET(ads, path, src_addr_index), 4506 MLX5_GET(ads, path, hop_limit), 4507 MLX5_GET(ads, path, tclass)); 4508 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4509 } 4510 } 4511 4512 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4513 struct mlx5_ib_sq *sq, 4514 u8 *sq_state) 4515 { 4516 int err; 4517 4518 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4519 if (err) 4520 goto out; 4521 sq->state = *sq_state; 4522 4523 out: 4524 return err; 4525 } 4526 4527 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4528 struct mlx5_ib_rq *rq, 4529 u8 *rq_state) 4530 { 4531 void *out; 4532 void *rqc; 4533 int inlen; 4534 int err; 4535 4536 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4537 out = kvzalloc(inlen, GFP_KERNEL); 4538 if (!out) 4539 return -ENOMEM; 4540 4541 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4542 if (err) 4543 goto out; 4544 4545 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4546 *rq_state = MLX5_GET(rqc, rqc, state); 4547 rq->state = *rq_state; 4548 4549 out: 4550 kvfree(out); 4551 return err; 4552 } 4553 4554 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4555 struct mlx5_ib_qp *qp, u8 *qp_state) 4556 { 4557 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4558 [MLX5_RQC_STATE_RST] = { 4559 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4560 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4561 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4562 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4563 }, 4564 [MLX5_RQC_STATE_RDY] = { 4565 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4566 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4567 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4568 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4569 }, 4570 [MLX5_RQC_STATE_ERR] = { 4571 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4572 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4573 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4574 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4575 }, 4576 [MLX5_RQ_STATE_NA] = { 4577 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4578 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4579 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4580 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4581 }, 4582 }; 4583 4584 *qp_state = sqrq_trans[rq_state][sq_state]; 4585 4586 if (*qp_state == MLX5_QP_STATE_BAD) { 4587 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4588 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4589 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4590 return -EINVAL; 4591 } 4592 4593 if (*qp_state == MLX5_QP_STATE) 4594 *qp_state = qp->state; 4595 4596 return 0; 4597 } 4598 4599 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4600 struct mlx5_ib_qp *qp, 4601 u8 *raw_packet_qp_state) 4602 { 4603 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4604 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4605 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4606 int err; 4607 u8 sq_state = MLX5_SQ_STATE_NA; 4608 u8 rq_state = MLX5_RQ_STATE_NA; 4609 4610 if (qp->sq.wqe_cnt) { 4611 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4612 if (err) 4613 return err; 4614 } 4615 4616 if (qp->rq.wqe_cnt) { 4617 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4618 if (err) 4619 return err; 4620 } 4621 4622 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4623 raw_packet_qp_state); 4624 } 4625 4626 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4627 struct ib_qp_attr *qp_attr) 4628 { 4629 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4630 void *qpc, *pri_path, *alt_path; 4631 u32 *outb; 4632 int err; 4633 4634 outb = kzalloc(outlen, GFP_KERNEL); 4635 if (!outb) 4636 return -ENOMEM; 4637 4638 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 4639 if (err) 4640 goto out; 4641 4642 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4643 4644 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4645 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4646 qp_attr->sq_draining = 1; 4647 4648 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4649 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4650 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4651 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4652 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4653 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4654 4655 if (MLX5_GET(qpc, qpc, rre)) 4656 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4657 if (MLX5_GET(qpc, qpc, rwe)) 4658 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4659 if (MLX5_GET(qpc, qpc, rae)) 4660 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4661 4662 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4663 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4664 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4665 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4666 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4667 4668 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4669 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4670 4671 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC || 4672 qp->ibqp.qp_type == IB_QPT_XRC_INI || 4673 qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 4674 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4675 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4676 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4677 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4678 } 4679 4680 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4681 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4682 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4683 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4684 4685 out: 4686 kfree(outb); 4687 return err; 4688 } 4689 4690 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4691 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4692 struct ib_qp_init_attr *qp_init_attr) 4693 { 4694 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4695 u32 *out; 4696 u32 access_flags = 0; 4697 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4698 void *dctc; 4699 int err; 4700 int supported_mask = IB_QP_STATE | 4701 IB_QP_ACCESS_FLAGS | 4702 IB_QP_PORT | 4703 IB_QP_MIN_RNR_TIMER | 4704 IB_QP_AV | 4705 IB_QP_PATH_MTU | 4706 IB_QP_PKEY_INDEX; 4707 4708 if (qp_attr_mask & ~supported_mask) 4709 return -EINVAL; 4710 if (mqp->state != IB_QPS_RTR) 4711 return -EINVAL; 4712 4713 out = kzalloc(outlen, GFP_KERNEL); 4714 if (!out) 4715 return -ENOMEM; 4716 4717 err = mlx5_core_dct_query(dev, dct, out, outlen); 4718 if (err) 4719 goto out; 4720 4721 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4722 4723 if (qp_attr_mask & IB_QP_STATE) 4724 qp_attr->qp_state = IB_QPS_RTR; 4725 4726 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4727 if (MLX5_GET(dctc, dctc, rre)) 4728 access_flags |= IB_ACCESS_REMOTE_READ; 4729 if (MLX5_GET(dctc, dctc, rwe)) 4730 access_flags |= IB_ACCESS_REMOTE_WRITE; 4731 if (MLX5_GET(dctc, dctc, rae)) 4732 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4733 qp_attr->qp_access_flags = access_flags; 4734 } 4735 4736 if (qp_attr_mask & IB_QP_PORT) 4737 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4738 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4739 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4740 if (qp_attr_mask & IB_QP_AV) { 4741 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4742 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4743 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4744 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4745 } 4746 if (qp_attr_mask & IB_QP_PATH_MTU) 4747 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4748 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4749 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4750 out: 4751 kfree(out); 4752 return err; 4753 } 4754 4755 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4756 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4757 { 4758 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4759 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4760 int err = 0; 4761 u8 raw_packet_qp_state; 4762 4763 if (ibqp->rwq_ind_tbl) 4764 return -ENOSYS; 4765 4766 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4767 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4768 qp_init_attr); 4769 4770 /* Not all of output fields are applicable, make sure to zero them */ 4771 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4772 memset(qp_attr, 0, sizeof(*qp_attr)); 4773 4774 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 4775 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4776 qp_attr_mask, qp_init_attr); 4777 4778 mutex_lock(&qp->mutex); 4779 4780 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4781 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4782 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4783 if (err) 4784 goto out; 4785 qp->state = raw_packet_qp_state; 4786 qp_attr->port_num = 1; 4787 } else { 4788 err = query_qp_attr(dev, qp, qp_attr); 4789 if (err) 4790 goto out; 4791 } 4792 4793 qp_attr->qp_state = qp->state; 4794 qp_attr->cur_qp_state = qp_attr->qp_state; 4795 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4796 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4797 4798 if (!ibqp->uobject) { 4799 qp_attr->cap.max_send_wr = qp->sq.max_post; 4800 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4801 qp_init_attr->qp_context = ibqp->qp_context; 4802 } else { 4803 qp_attr->cap.max_send_wr = 0; 4804 qp_attr->cap.max_send_sge = 0; 4805 } 4806 4807 qp_init_attr->qp_type = ibqp->qp_type; 4808 qp_init_attr->recv_cq = ibqp->recv_cq; 4809 qp_init_attr->send_cq = ibqp->send_cq; 4810 qp_init_attr->srq = ibqp->srq; 4811 qp_attr->cap.max_inline_data = qp->max_inline_data; 4812 4813 qp_init_attr->cap = qp_attr->cap; 4814 4815 qp_init_attr->create_flags = qp->flags; 4816 4817 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4818 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4819 4820 out: 4821 mutex_unlock(&qp->mutex); 4822 return err; 4823 } 4824 4825 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 4826 { 4827 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 4828 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 4829 4830 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4831 return -EOPNOTSUPP; 4832 4833 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 4834 } 4835 4836 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4837 { 4838 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4839 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4840 4841 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 4842 } 4843 4844 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4845 { 4846 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4847 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4848 struct ib_event event; 4849 4850 if (rwq->ibwq.event_handler) { 4851 event.device = rwq->ibwq.device; 4852 event.element.wq = &rwq->ibwq; 4853 switch (type) { 4854 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4855 event.event = IB_EVENT_WQ_FATAL; 4856 break; 4857 default: 4858 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4859 return; 4860 } 4861 4862 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4863 } 4864 } 4865 4866 static int set_delay_drop(struct mlx5_ib_dev *dev) 4867 { 4868 int err = 0; 4869 4870 mutex_lock(&dev->delay_drop.lock); 4871 if (dev->delay_drop.activate) 4872 goto out; 4873 4874 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 4875 if (err) 4876 goto out; 4877 4878 dev->delay_drop.activate = true; 4879 out: 4880 mutex_unlock(&dev->delay_drop.lock); 4881 4882 if (!err) 4883 atomic_inc(&dev->delay_drop.rqs_cnt); 4884 return err; 4885 } 4886 4887 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4888 struct ib_wq_init_attr *init_attr) 4889 { 4890 struct mlx5_ib_dev *dev; 4891 int has_net_offloads; 4892 __be64 *rq_pas0; 4893 int ts_format; 4894 void *in; 4895 void *rqc; 4896 void *wq; 4897 int inlen; 4898 int err; 4899 4900 dev = to_mdev(pd->device); 4901 4902 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 4903 if (ts_format < 0) 4904 return ts_format; 4905 4906 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4907 in = kvzalloc(inlen, GFP_KERNEL); 4908 if (!in) 4909 return -ENOMEM; 4910 4911 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4912 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4913 MLX5_SET(rqc, rqc, mem_rq_type, 4914 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4915 MLX5_SET(rqc, rqc, ts_format, ts_format); 4916 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4917 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4918 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4919 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4920 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4921 MLX5_SET(wq, wq, wq_type, 4922 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 4923 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 4924 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 4925 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 4926 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 4927 err = -EOPNOTSUPP; 4928 goto out; 4929 } else { 4930 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4931 } 4932 } 4933 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4934 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 4935 /* 4936 * In Firmware number of strides in each WQE is: 4937 * "512 * 2^single_wqe_log_num_of_strides" 4938 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 4939 * accepted as 0 to 9 4940 */ 4941 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 4942 2, 3, 4, 5, 6, 7, 8, 9 }; 4943 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 4944 MLX5_SET(wq, wq, log_wqe_stride_size, 4945 rwq->single_stride_log_num_of_bytes - 4946 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 4947 MLX5_SET(wq, wq, log_wqe_num_of_strides, 4948 fw_map[rwq->log_num_strides - 4949 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 4950 } 4951 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4952 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4953 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4954 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4955 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4956 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4957 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4958 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4959 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4960 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4961 err = -EOPNOTSUPP; 4962 goto out; 4963 } 4964 } else { 4965 MLX5_SET(rqc, rqc, vsd, 1); 4966 } 4967 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4968 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4969 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4970 err = -EOPNOTSUPP; 4971 goto out; 4972 } 4973 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4974 } 4975 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4976 if (!(dev->ib_dev.attrs.raw_packet_caps & 4977 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4978 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4979 err = -EOPNOTSUPP; 4980 goto out; 4981 } 4982 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4983 } 4984 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4985 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 4986 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 4987 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4988 err = set_delay_drop(dev); 4989 if (err) { 4990 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4991 err); 4992 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 4993 } else { 4994 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4995 } 4996 } 4997 out: 4998 kvfree(in); 4999 return err; 5000 } 5001 5002 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5003 struct ib_wq_init_attr *wq_init_attr, 5004 struct mlx5_ib_create_wq *ucmd, 5005 struct mlx5_ib_rwq *rwq) 5006 { 5007 /* Sanity check RQ size before proceeding */ 5008 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5009 return -EINVAL; 5010 5011 if (!ucmd->rq_wqe_count) 5012 return -EINVAL; 5013 5014 rwq->wqe_count = ucmd->rq_wqe_count; 5015 rwq->wqe_shift = ucmd->rq_wqe_shift; 5016 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5017 return -EINVAL; 5018 5019 rwq->log_rq_stride = rwq->wqe_shift; 5020 rwq->log_rq_size = ilog2(rwq->wqe_count); 5021 return 0; 5022 } 5023 5024 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5025 { 5026 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5027 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5028 return false; 5029 5030 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5031 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5032 return false; 5033 5034 return true; 5035 } 5036 5037 static int prepare_user_rq(struct ib_pd *pd, 5038 struct ib_wq_init_attr *init_attr, 5039 struct ib_udata *udata, 5040 struct mlx5_ib_rwq *rwq) 5041 { 5042 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5043 struct mlx5_ib_create_wq ucmd = {}; 5044 int err; 5045 size_t required_cmd_sz; 5046 5047 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 5048 single_stride_log_num_of_bytes); 5049 if (udata->inlen < required_cmd_sz) { 5050 mlx5_ib_dbg(dev, "invalid inlen\n"); 5051 return -EINVAL; 5052 } 5053 5054 if (udata->inlen > sizeof(ucmd) && 5055 !ib_is_udata_cleared(udata, sizeof(ucmd), 5056 udata->inlen - sizeof(ucmd))) { 5057 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5058 return -EOPNOTSUPP; 5059 } 5060 5061 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5062 mlx5_ib_dbg(dev, "copy failed\n"); 5063 return -EFAULT; 5064 } 5065 5066 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5067 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5068 return -EOPNOTSUPP; 5069 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5070 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5071 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5072 return -EOPNOTSUPP; 5073 } 5074 if ((ucmd.single_stride_log_num_of_bytes < 5075 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5076 (ucmd.single_stride_log_num_of_bytes > 5077 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5078 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5079 ucmd.single_stride_log_num_of_bytes, 5080 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5081 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5082 return -EINVAL; 5083 } 5084 if (!log_of_strides_valid(dev, 5085 ucmd.single_wqe_log_num_of_strides)) { 5086 mlx5_ib_dbg( 5087 dev, 5088 "Invalid log num strides (%u. Range is %u - %u)\n", 5089 ucmd.single_wqe_log_num_of_strides, 5090 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5091 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5092 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5093 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5094 return -EINVAL; 5095 } 5096 rwq->single_stride_log_num_of_bytes = 5097 ucmd.single_stride_log_num_of_bytes; 5098 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5099 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5100 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5101 } 5102 5103 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5104 if (err) { 5105 mlx5_ib_dbg(dev, "err %d\n", err); 5106 return err; 5107 } 5108 5109 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5110 if (err) { 5111 mlx5_ib_dbg(dev, "err %d\n", err); 5112 return err; 5113 } 5114 5115 rwq->user_index = ucmd.user_index; 5116 return 0; 5117 } 5118 5119 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5120 struct ib_wq_init_attr *init_attr, 5121 struct ib_udata *udata) 5122 { 5123 struct mlx5_ib_dev *dev; 5124 struct mlx5_ib_rwq *rwq; 5125 struct mlx5_ib_create_wq_resp resp = {}; 5126 size_t min_resp_len; 5127 int err; 5128 5129 if (!udata) 5130 return ERR_PTR(-ENOSYS); 5131 5132 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5133 if (udata->outlen && udata->outlen < min_resp_len) 5134 return ERR_PTR(-EINVAL); 5135 5136 if (!capable(CAP_SYS_RAWIO) && 5137 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5138 return ERR_PTR(-EPERM); 5139 5140 dev = to_mdev(pd->device); 5141 switch (init_attr->wq_type) { 5142 case IB_WQT_RQ: 5143 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5144 if (!rwq) 5145 return ERR_PTR(-ENOMEM); 5146 err = prepare_user_rq(pd, init_attr, udata, rwq); 5147 if (err) 5148 goto err; 5149 err = create_rq(rwq, pd, init_attr); 5150 if (err) 5151 goto err_user_rq; 5152 break; 5153 default: 5154 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5155 init_attr->wq_type); 5156 return ERR_PTR(-EINVAL); 5157 } 5158 5159 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5160 rwq->ibwq.state = IB_WQS_RESET; 5161 if (udata->outlen) { 5162 resp.response_length = offsetofend( 5163 struct mlx5_ib_create_wq_resp, response_length); 5164 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5165 if (err) 5166 goto err_copy; 5167 } 5168 5169 rwq->core_qp.event = mlx5_ib_wq_event; 5170 rwq->ibwq.event_handler = init_attr->event_handler; 5171 return &rwq->ibwq; 5172 5173 err_copy: 5174 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5175 err_user_rq: 5176 destroy_user_rq(dev, pd, rwq, udata); 5177 err: 5178 kfree(rwq); 5179 return ERR_PTR(err); 5180 } 5181 5182 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5183 { 5184 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5185 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5186 int ret; 5187 5188 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5189 if (ret) 5190 return ret; 5191 destroy_user_rq(dev, wq->pd, rwq, udata); 5192 kfree(rwq); 5193 return 0; 5194 } 5195 5196 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5197 struct ib_rwq_ind_table_init_attr *init_attr, 5198 struct ib_udata *udata) 5199 { 5200 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5201 to_mrwq_ind_table(ib_rwq_ind_table); 5202 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5203 int sz = 1 << init_attr->log_ind_tbl_size; 5204 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5205 size_t min_resp_len; 5206 int inlen; 5207 int err; 5208 int i; 5209 u32 *in; 5210 void *rqtc; 5211 5212 if (udata->inlen > 0 && 5213 !ib_is_udata_cleared(udata, 0, 5214 udata->inlen)) 5215 return -EOPNOTSUPP; 5216 5217 if (init_attr->log_ind_tbl_size > 5218 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5219 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5220 init_attr->log_ind_tbl_size, 5221 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5222 return -EINVAL; 5223 } 5224 5225 min_resp_len = 5226 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5227 if (udata->outlen && udata->outlen < min_resp_len) 5228 return -EINVAL; 5229 5230 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5231 in = kvzalloc(inlen, GFP_KERNEL); 5232 if (!in) 5233 return -ENOMEM; 5234 5235 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5236 5237 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5238 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5239 5240 for (i = 0; i < sz; i++) 5241 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5242 5243 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5244 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5245 5246 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5247 kvfree(in); 5248 if (err) 5249 return err; 5250 5251 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5252 if (udata->outlen) { 5253 resp.response_length = 5254 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5255 response_length); 5256 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5257 if (err) 5258 goto err_copy; 5259 } 5260 5261 return 0; 5262 5263 err_copy: 5264 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5265 return err; 5266 } 5267 5268 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5269 { 5270 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5271 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5272 5273 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5274 } 5275 5276 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5277 u32 wq_attr_mask, struct ib_udata *udata) 5278 { 5279 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5280 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5281 struct mlx5_ib_modify_wq ucmd = {}; 5282 size_t required_cmd_sz; 5283 int curr_wq_state; 5284 int wq_state; 5285 int inlen; 5286 int err; 5287 void *rqc; 5288 void *in; 5289 5290 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5291 if (udata->inlen < required_cmd_sz) 5292 return -EINVAL; 5293 5294 if (udata->inlen > sizeof(ucmd) && 5295 !ib_is_udata_cleared(udata, sizeof(ucmd), 5296 udata->inlen - sizeof(ucmd))) 5297 return -EOPNOTSUPP; 5298 5299 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5300 return -EFAULT; 5301 5302 if (ucmd.comp_mask || ucmd.reserved) 5303 return -EOPNOTSUPP; 5304 5305 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5306 in = kvzalloc(inlen, GFP_KERNEL); 5307 if (!in) 5308 return -ENOMEM; 5309 5310 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5311 5312 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5313 wq_attr->curr_wq_state : wq->state; 5314 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5315 wq_attr->wq_state : curr_wq_state; 5316 if (curr_wq_state == IB_WQS_ERR) 5317 curr_wq_state = MLX5_RQC_STATE_ERR; 5318 if (wq_state == IB_WQS_ERR) 5319 wq_state = MLX5_RQC_STATE_ERR; 5320 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5321 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5322 MLX5_SET(rqc, rqc, state, wq_state); 5323 5324 if (wq_attr_mask & IB_WQ_FLAGS) { 5325 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5326 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5327 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5328 mlx5_ib_dbg(dev, "VLAN offloads are not " 5329 "supported\n"); 5330 err = -EOPNOTSUPP; 5331 goto out; 5332 } 5333 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5334 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5335 MLX5_SET(rqc, rqc, vsd, 5336 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5337 } 5338 5339 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5340 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5341 err = -EOPNOTSUPP; 5342 goto out; 5343 } 5344 } 5345 5346 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5347 u16 set_id; 5348 5349 set_id = mlx5_ib_get_counters_id(dev, 0); 5350 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5351 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5352 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5353 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5354 } else 5355 dev_info_once( 5356 &dev->ib_dev.dev, 5357 "Receive WQ counters are not supported on current FW\n"); 5358 } 5359 5360 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5361 if (!err) 5362 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5363 5364 out: 5365 kvfree(in); 5366 return err; 5367 } 5368 5369 struct mlx5_ib_drain_cqe { 5370 struct ib_cqe cqe; 5371 struct completion done; 5372 }; 5373 5374 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5375 { 5376 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5377 struct mlx5_ib_drain_cqe, 5378 cqe); 5379 5380 complete(&cqe->done); 5381 } 5382 5383 /* This function returns only once the drained WR was completed */ 5384 static void handle_drain_completion(struct ib_cq *cq, 5385 struct mlx5_ib_drain_cqe *sdrain, 5386 struct mlx5_ib_dev *dev) 5387 { 5388 struct mlx5_core_dev *mdev = dev->mdev; 5389 5390 if (cq->poll_ctx == IB_POLL_DIRECT) { 5391 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5392 ib_process_cq_direct(cq, -1); 5393 return; 5394 } 5395 5396 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5397 struct mlx5_ib_cq *mcq = to_mcq(cq); 5398 bool triggered = false; 5399 unsigned long flags; 5400 5401 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5402 /* Make sure that the CQ handler won't run if wasn't run yet */ 5403 if (!mcq->mcq.reset_notify_added) 5404 mcq->mcq.reset_notify_added = 1; 5405 else 5406 triggered = true; 5407 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5408 5409 if (triggered) { 5410 /* Wait for any scheduled/running task to be ended */ 5411 switch (cq->poll_ctx) { 5412 case IB_POLL_SOFTIRQ: 5413 irq_poll_disable(&cq->iop); 5414 irq_poll_enable(&cq->iop); 5415 break; 5416 case IB_POLL_WORKQUEUE: 5417 cancel_work_sync(&cq->work); 5418 break; 5419 default: 5420 WARN_ON_ONCE(1); 5421 } 5422 } 5423 5424 /* Run the CQ handler - this makes sure that the drain WR will 5425 * be processed if wasn't processed yet. 5426 */ 5427 mcq->mcq.comp(&mcq->mcq, NULL); 5428 } 5429 5430 wait_for_completion(&sdrain->done); 5431 } 5432 5433 void mlx5_ib_drain_sq(struct ib_qp *qp) 5434 { 5435 struct ib_cq *cq = qp->send_cq; 5436 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5437 struct mlx5_ib_drain_cqe sdrain; 5438 const struct ib_send_wr *bad_swr; 5439 struct ib_rdma_wr swr = { 5440 .wr = { 5441 .next = NULL, 5442 { .wr_cqe = &sdrain.cqe, }, 5443 .opcode = IB_WR_RDMA_WRITE, 5444 }, 5445 }; 5446 int ret; 5447 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5448 struct mlx5_core_dev *mdev = dev->mdev; 5449 5450 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5451 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5452 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5453 return; 5454 } 5455 5456 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5457 init_completion(&sdrain.done); 5458 5459 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5460 if (ret) { 5461 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5462 return; 5463 } 5464 5465 handle_drain_completion(cq, &sdrain, dev); 5466 } 5467 5468 void mlx5_ib_drain_rq(struct ib_qp *qp) 5469 { 5470 struct ib_cq *cq = qp->recv_cq; 5471 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5472 struct mlx5_ib_drain_cqe rdrain; 5473 struct ib_recv_wr rwr = {}; 5474 const struct ib_recv_wr *bad_rwr; 5475 int ret; 5476 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5477 struct mlx5_core_dev *mdev = dev->mdev; 5478 5479 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5480 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5481 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5482 return; 5483 } 5484 5485 rwr.wr_cqe = &rdrain.cqe; 5486 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5487 init_completion(&rdrain.done); 5488 5489 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5490 if (ret) { 5491 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5492 return; 5493 } 5494 5495 handle_drain_completion(cq, &rdrain, dev); 5496 } 5497 5498 /* 5499 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5500 * the default counter 5501 */ 5502 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5503 { 5504 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5505 struct mlx5_ib_qp *mqp = to_mqp(qp); 5506 int err = 0; 5507 5508 mutex_lock(&mqp->mutex); 5509 if (mqp->state == IB_QPS_RESET) { 5510 qp->counter = counter; 5511 goto out; 5512 } 5513 5514 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5515 err = -EOPNOTSUPP; 5516 goto out; 5517 } 5518 5519 if (mqp->state == IB_QPS_RTS) { 5520 err = __mlx5_ib_qp_set_counter(qp, counter); 5521 if (!err) 5522 qp->counter = counter; 5523 5524 goto out; 5525 } 5526 5527 mqp->counter_pending = 1; 5528 qp->counter = counter; 5529 5530 out: 5531 mutex_unlock(&mqp->mutex); 5532 return err; 5533 } 5534