1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "qp.h" 44 #include "wr.h" 45 46 enum { 47 MLX5_IB_ACK_REQ_FREQ = 8, 48 }; 49 50 enum { 51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 53 MLX5_IB_LINK_TYPE_IB = 0, 54 MLX5_IB_LINK_TYPE_ETH = 1 55 }; 56 57 enum raw_qp_set_mask_map { 58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 60 }; 61 62 struct mlx5_modify_raw_qp_param { 63 u16 operation; 64 65 u32 set_mask; /* raw_qp_set_mask_map */ 66 67 struct mlx5_rate_limit rl; 68 69 u8 rq_q_ctr_id; 70 u32 port; 71 }; 72 73 static void get_cqs(enum ib_qp_type qp_type, 74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 76 77 static int is_qp0(enum ib_qp_type qp_type) 78 { 79 return qp_type == IB_QPT_SMI; 80 } 81 82 static int is_sqp(enum ib_qp_type qp_type) 83 { 84 return is_qp0(qp_type) || is_qp1(qp_type); 85 } 86 87 /** 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 89 * to kernel buffer 90 * 91 * @umem: User space memory where the WQ is 92 * @buffer: buffer to copy to 93 * @buflen: buffer length 94 * @wqe_index: index of WQE to copy from 95 * @wq_offset: offset to start of WQ 96 * @wq_wqe_cnt: number of WQEs in WQ 97 * @wq_wqe_shift: log2 of WQE size 98 * @bcnt: number of bytes to copy 99 * @bytes_copied: number of bytes to copy (return value) 100 * 101 * Copies from start of WQE bcnt or less bytes. 102 * Does not gurantee to copy the entire WQE. 103 * 104 * Return: zero on success, or an error code. 105 */ 106 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 107 size_t buflen, int wqe_index, 108 int wq_offset, int wq_wqe_cnt, 109 int wq_wqe_shift, int bcnt, 110 size_t *bytes_copied) 111 { 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 114 size_t copy_length; 115 int ret; 116 117 /* don't copy more than requested, more than buffer length or 118 * beyond WQ end 119 */ 120 copy_length = min_t(u32, buflen, wq_end - offset); 121 copy_length = min_t(u32, copy_length, bcnt); 122 123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 124 if (ret) 125 return ret; 126 127 if (!ret && bytes_copied) 128 *bytes_copied = copy_length; 129 130 return 0; 131 } 132 133 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 134 void *buffer, size_t buflen, size_t *bc) 135 { 136 struct mlx5_wqe_ctrl_seg *ctrl; 137 size_t bytes_copied = 0; 138 size_t wqe_length; 139 void *p; 140 int ds; 141 142 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 143 144 /* read the control segment first */ 145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 146 ctrl = p; 147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 148 wqe_length = ds * MLX5_WQE_DS_UNITS; 149 150 /* read rest of WQE if it spreads over more than one stride */ 151 while (bytes_copied < wqe_length) { 152 size_t copy_length = 153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 154 155 if (!copy_length) 156 break; 157 158 memcpy(buffer + bytes_copied, p, copy_length); 159 bytes_copied += copy_length; 160 161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 163 } 164 *bc = bytes_copied; 165 return 0; 166 } 167 168 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 169 void *buffer, size_t buflen, size_t *bc) 170 { 171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 172 struct ib_umem *umem = base->ubuffer.umem; 173 struct mlx5_ib_wq *wq = &qp->sq; 174 struct mlx5_wqe_ctrl_seg *ctrl; 175 size_t bytes_copied; 176 size_t bytes_copied2; 177 size_t wqe_length; 178 int ret; 179 int ds; 180 181 /* at first read as much as possible */ 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 183 wq->offset, wq->wqe_cnt, 184 wq->wqe_shift, buflen, 185 &bytes_copied); 186 if (ret) 187 return ret; 188 189 /* we need at least control segment size to proceed */ 190 if (bytes_copied < sizeof(*ctrl)) 191 return -EINVAL; 192 193 ctrl = buffer; 194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 195 wqe_length = ds * MLX5_WQE_DS_UNITS; 196 197 /* if we copied enough then we are done */ 198 if (bytes_copied >= wqe_length) { 199 *bc = bytes_copied; 200 return 0; 201 } 202 203 /* otherwise this a wrapped around wqe 204 * so read the remaining bytes starting 205 * from wqe_index 0 206 */ 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 208 buflen - bytes_copied, 0, wq->offset, 209 wq->wqe_cnt, wq->wqe_shift, 210 wqe_length - bytes_copied, 211 &bytes_copied2); 212 213 if (ret) 214 return ret; 215 *bc = bytes_copied + bytes_copied2; 216 return 0; 217 } 218 219 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 220 size_t buflen, size_t *bc) 221 { 222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 223 struct ib_umem *umem = base->ubuffer.umem; 224 225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 226 return -EINVAL; 227 228 if (!umem) 229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 230 buflen, bc); 231 232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 233 } 234 235 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 236 void *buffer, size_t buflen, size_t *bc) 237 { 238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 239 struct ib_umem *umem = base->ubuffer.umem; 240 struct mlx5_ib_wq *wq = &qp->rq; 241 size_t bytes_copied; 242 int ret; 243 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 245 wq->offset, wq->wqe_cnt, 246 wq->wqe_shift, buflen, 247 &bytes_copied); 248 249 if (ret) 250 return ret; 251 *bc = bytes_copied; 252 return 0; 253 } 254 255 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 256 size_t buflen, size_t *bc) 257 { 258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 259 struct ib_umem *umem = base->ubuffer.umem; 260 struct mlx5_ib_wq *wq = &qp->rq; 261 size_t wqe_size = 1 << wq->wqe_shift; 262 263 if (buflen < wqe_size) 264 return -EINVAL; 265 266 if (!umem) 267 return -EOPNOTSUPP; 268 269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 270 } 271 272 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 273 void *buffer, size_t buflen, size_t *bc) 274 { 275 struct ib_umem *umem = srq->umem; 276 size_t bytes_copied; 277 int ret; 278 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 280 srq->msrq.max, srq->msrq.wqe_shift, 281 buflen, &bytes_copied); 282 283 if (ret) 284 return ret; 285 *bc = bytes_copied; 286 return 0; 287 } 288 289 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 290 size_t buflen, size_t *bc) 291 { 292 struct ib_umem *umem = srq->umem; 293 size_t wqe_size = 1 << srq->msrq.wqe_shift; 294 295 if (buflen < wqe_size) 296 return -EINVAL; 297 298 if (!umem) 299 return -EOPNOTSUPP; 300 301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 302 } 303 304 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 305 { 306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 307 struct ib_event event; 308 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 310 /* This event is only valid for trans_qps */ 311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 312 } 313 314 if (ibqp->event_handler) { 315 event.device = ibqp->device; 316 event.element.qp = ibqp; 317 switch (type) { 318 case MLX5_EVENT_TYPE_PATH_MIG: 319 event.event = IB_EVENT_PATH_MIG; 320 break; 321 case MLX5_EVENT_TYPE_COMM_EST: 322 event.event = IB_EVENT_COMM_EST; 323 break; 324 case MLX5_EVENT_TYPE_SQ_DRAINED: 325 event.event = IB_EVENT_SQ_DRAINED; 326 break; 327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 328 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 329 break; 330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 331 event.event = IB_EVENT_QP_FATAL; 332 break; 333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 334 event.event = IB_EVENT_PATH_MIG_ERR; 335 break; 336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 337 event.event = IB_EVENT_QP_REQ_ERR; 338 break; 339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 340 event.event = IB_EVENT_QP_ACCESS_ERR; 341 break; 342 default: 343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 344 return; 345 } 346 347 ibqp->event_handler(&event, ibqp->qp_context); 348 } 349 } 350 351 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 353 { 354 int wqe_size; 355 int wq_size; 356 357 /* Sanity check RQ size before proceeding */ 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 359 return -EINVAL; 360 361 if (!has_rq) { 362 qp->rq.max_gs = 0; 363 qp->rq.wqe_cnt = 0; 364 qp->rq.wqe_shift = 0; 365 cap->max_recv_wr = 0; 366 cap->max_recv_sge = 0; 367 } else { 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 369 370 if (ucmd) { 371 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 373 return -EINVAL; 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 375 if ((1 << qp->rq.wqe_shift) / 376 sizeof(struct mlx5_wqe_data_seg) < 377 wq_sig) 378 return -EINVAL; 379 qp->rq.max_gs = 380 (1 << qp->rq.wqe_shift) / 381 sizeof(struct mlx5_wqe_data_seg) - 382 wq_sig; 383 qp->rq.max_post = qp->rq.wqe_cnt; 384 } else { 385 wqe_size = 386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 387 0; 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 389 wqe_size = roundup_pow_of_two(wqe_size); 390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 392 qp->rq.wqe_cnt = wq_size / wqe_size; 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 395 wqe_size, 396 MLX5_CAP_GEN(dev->mdev, 397 max_wqe_sz_rq)); 398 return -EINVAL; 399 } 400 qp->rq.wqe_shift = ilog2(wqe_size); 401 qp->rq.max_gs = 402 (1 << qp->rq.wqe_shift) / 403 sizeof(struct mlx5_wqe_data_seg) - 404 wq_sig; 405 qp->rq.max_post = qp->rq.wqe_cnt; 406 } 407 } 408 409 return 0; 410 } 411 412 static int sq_overhead(struct ib_qp_init_attr *attr) 413 { 414 int size = 0; 415 416 switch (attr->qp_type) { 417 case IB_QPT_XRC_INI: 418 size += sizeof(struct mlx5_wqe_xrc_seg); 419 fallthrough; 420 case IB_QPT_RC: 421 size += sizeof(struct mlx5_wqe_ctrl_seg) + 422 max(sizeof(struct mlx5_wqe_atomic_seg) + 423 sizeof(struct mlx5_wqe_raddr_seg), 424 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 425 sizeof(struct mlx5_mkey_seg) + 426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 427 MLX5_IB_UMR_OCTOWORD); 428 break; 429 430 case IB_QPT_XRC_TGT: 431 return 0; 432 433 case IB_QPT_UC: 434 size += sizeof(struct mlx5_wqe_ctrl_seg) + 435 max(sizeof(struct mlx5_wqe_raddr_seg), 436 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 437 sizeof(struct mlx5_mkey_seg)); 438 break; 439 440 case IB_QPT_UD: 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 442 size += sizeof(struct mlx5_wqe_eth_pad) + 443 sizeof(struct mlx5_wqe_eth_seg); 444 fallthrough; 445 case IB_QPT_SMI: 446 case MLX5_IB_QPT_HW_GSI: 447 size += sizeof(struct mlx5_wqe_ctrl_seg) + 448 sizeof(struct mlx5_wqe_datagram_seg); 449 break; 450 451 case MLX5_IB_QPT_REG_UMR: 452 size += sizeof(struct mlx5_wqe_ctrl_seg) + 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 454 sizeof(struct mlx5_mkey_seg); 455 break; 456 457 default: 458 return -EINVAL; 459 } 460 461 return size; 462 } 463 464 static int calc_send_wqe(struct ib_qp_init_attr *attr) 465 { 466 int inl_size = 0; 467 int size; 468 469 size = sq_overhead(attr); 470 if (size < 0) 471 return size; 472 473 if (attr->cap.max_inline_data) { 474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 475 attr->cap.max_inline_data; 476 } 477 478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 481 return MLX5_SIG_WQE_SIZE; 482 else 483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 484 } 485 486 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 487 { 488 int max_sge; 489 490 if (attr->qp_type == IB_QPT_RC) 491 max_sge = (min_t(int, wqe_size, 512) - 492 sizeof(struct mlx5_wqe_ctrl_seg) - 493 sizeof(struct mlx5_wqe_raddr_seg)) / 494 sizeof(struct mlx5_wqe_data_seg); 495 else if (attr->qp_type == IB_QPT_XRC_INI) 496 max_sge = (min_t(int, wqe_size, 512) - 497 sizeof(struct mlx5_wqe_ctrl_seg) - 498 sizeof(struct mlx5_wqe_xrc_seg) - 499 sizeof(struct mlx5_wqe_raddr_seg)) / 500 sizeof(struct mlx5_wqe_data_seg); 501 else 502 max_sge = (wqe_size - sq_overhead(attr)) / 503 sizeof(struct mlx5_wqe_data_seg); 504 505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 506 sizeof(struct mlx5_wqe_data_seg)); 507 } 508 509 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 510 struct mlx5_ib_qp *qp) 511 { 512 int wqe_size; 513 int wq_size; 514 515 if (!attr->cap.max_send_wr) 516 return 0; 517 518 wqe_size = calc_send_wqe(attr); 519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 520 if (wqe_size < 0) 521 return wqe_size; 522 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 526 return -EINVAL; 527 } 528 529 qp->max_inline_data = wqe_size - sq_overhead(attr) - 530 sizeof(struct mlx5_wqe_inline_seg); 531 attr->cap.max_inline_data = qp->max_inline_data; 532 533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 538 qp->sq.wqe_cnt, 539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 540 return -ENOMEM; 541 } 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 543 qp->sq.max_gs = get_send_sge(attr, wqe_size); 544 if (qp->sq.max_gs < attr->cap.max_send_sge) 545 return -ENOMEM; 546 547 attr->cap.max_send_sge = qp->sq.max_gs; 548 qp->sq.max_post = wq_size / wqe_size; 549 attr->cap.max_send_wr = qp->sq.max_post; 550 551 return wq_size; 552 } 553 554 static int set_user_buf_size(struct mlx5_ib_dev *dev, 555 struct mlx5_ib_qp *qp, 556 struct mlx5_ib_create_qp *ucmd, 557 struct mlx5_ib_qp_base *base, 558 struct ib_qp_init_attr *attr) 559 { 560 int desc_sz = 1 << qp->sq.wqe_shift; 561 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 565 return -EINVAL; 566 } 567 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 570 ucmd->sq_wqe_count); 571 return -EINVAL; 572 } 573 574 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 575 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 578 qp->sq.wqe_cnt, 579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 580 return -EINVAL; 581 } 582 583 if (attr->qp_type == IB_QPT_RAW_PACKET || 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 587 } else { 588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 589 (qp->sq.wqe_cnt << 6); 590 } 591 592 return 0; 593 } 594 595 static int qp_has_rq(struct ib_qp_init_attr *attr) 596 { 597 if (attr->qp_type == IB_QPT_XRC_INI || 598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 599 attr->qp_type == MLX5_IB_QPT_REG_UMR || 600 !attr->cap.max_recv_wr) 601 return 0; 602 603 return 1; 604 } 605 606 enum { 607 /* this is the first blue flame register in the array of bfregs assigned 608 * to a processes. Since we do not use it for blue flame but rather 609 * regular 64 bit doorbells, we do not need a lock for maintaiing 610 * "odd/even" order 611 */ 612 NUM_NON_BLUE_FLAME_BFREGS = 1, 613 }; 614 615 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 616 { 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 618 } 619 620 static int num_med_bfreg(struct mlx5_ib_dev *dev, 621 struct mlx5_bfreg_info *bfregi) 622 { 623 int n; 624 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 626 NUM_NON_BLUE_FLAME_BFREGS; 627 628 return n >= 0 ? n : 0; 629 } 630 631 static int first_med_bfreg(struct mlx5_ib_dev *dev, 632 struct mlx5_bfreg_info *bfregi) 633 { 634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 635 } 636 637 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 638 struct mlx5_bfreg_info *bfregi) 639 { 640 int med; 641 642 med = num_med_bfreg(dev, bfregi); 643 return ++med; 644 } 645 646 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 647 struct mlx5_bfreg_info *bfregi) 648 { 649 int i; 650 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 652 if (!bfregi->count[i]) { 653 bfregi->count[i]++; 654 return i; 655 } 656 } 657 658 return -ENOMEM; 659 } 660 661 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 662 struct mlx5_bfreg_info *bfregi) 663 { 664 int minidx = first_med_bfreg(dev, bfregi); 665 int i; 666 667 if (minidx < 0) 668 return minidx; 669 670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 671 if (bfregi->count[i] < bfregi->count[minidx]) 672 minidx = i; 673 if (!bfregi->count[minidx]) 674 break; 675 } 676 677 bfregi->count[minidx]++; 678 return minidx; 679 } 680 681 static int alloc_bfreg(struct mlx5_ib_dev *dev, 682 struct mlx5_bfreg_info *bfregi) 683 { 684 int bfregn = -ENOMEM; 685 686 if (bfregi->lib_uar_dyn) 687 return -EINVAL; 688 689 mutex_lock(&bfregi->lock); 690 if (bfregi->ver >= 2) { 691 bfregn = alloc_high_class_bfreg(dev, bfregi); 692 if (bfregn < 0) 693 bfregn = alloc_med_class_bfreg(dev, bfregi); 694 } 695 696 if (bfregn < 0) { 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 698 bfregn = 0; 699 bfregi->count[bfregn]++; 700 } 701 mutex_unlock(&bfregi->lock); 702 703 return bfregn; 704 } 705 706 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 707 { 708 mutex_lock(&bfregi->lock); 709 bfregi->count[bfregn]--; 710 mutex_unlock(&bfregi->lock); 711 } 712 713 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 714 { 715 switch (state) { 716 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 723 default: return -1; 724 } 725 } 726 727 static int to_mlx5_st(enum ib_qp_type type) 728 { 729 switch (type) { 730 case IB_QPT_RC: return MLX5_QP_ST_RC; 731 case IB_QPT_UC: return MLX5_QP_ST_UC; 732 case IB_QPT_UD: return MLX5_QP_ST_UD; 733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 734 case IB_QPT_XRC_INI: 735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 736 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 740 default: return -EINVAL; 741 } 742 } 743 744 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 745 struct mlx5_ib_cq *recv_cq); 746 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 747 struct mlx5_ib_cq *recv_cq); 748 749 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, u32 bfregn, 751 bool dyn_bfreg) 752 { 753 unsigned int bfregs_per_sys_page; 754 u32 index_of_sys_page; 755 u32 offset; 756 757 if (bfregi->lib_uar_dyn) 758 return -EINVAL; 759 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 761 MLX5_NON_FP_BFREGS_PER_UAR; 762 index_of_sys_page = bfregn / bfregs_per_sys_page; 763 764 if (dyn_bfreg) { 765 index_of_sys_page += bfregi->num_static_sys_pages; 766 767 if (index_of_sys_page >= bfregi->num_sys_pages) 768 return -EINVAL; 769 770 if (bfregn > bfregi->num_dyn_bfregs || 771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 773 return -EINVAL; 774 } 775 } 776 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 778 return bfregi->sys_pages[index_of_sys_page] + offset; 779 } 780 781 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 782 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 783 { 784 struct mlx5_ib_ucontext *context = 785 rdma_udata_to_drv_context( 786 udata, 787 struct mlx5_ib_ucontext, 788 ibucontext); 789 790 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 791 atomic_dec(&dev->delay_drop.rqs_cnt); 792 793 mlx5_ib_db_unmap_user(context, &rwq->db); 794 ib_umem_release(rwq->umem); 795 } 796 797 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 798 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 799 struct mlx5_ib_create_wq *ucmd) 800 { 801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 802 udata, struct mlx5_ib_ucontext, ibucontext); 803 unsigned long page_size = 0; 804 u32 offset = 0; 805 int err; 806 807 if (!ucmd->buf_addr) 808 return -EINVAL; 809 810 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 811 if (IS_ERR(rwq->umem)) { 812 mlx5_ib_dbg(dev, "umem_get failed\n"); 813 err = PTR_ERR(rwq->umem); 814 return err; 815 } 816 817 page_size = mlx5_umem_find_best_quantized_pgoff( 818 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 819 page_offset, 64, &rwq->rq_page_offset); 820 if (!page_size) { 821 mlx5_ib_warn(dev, "bad offset\n"); 822 err = -EINVAL; 823 goto err_umem; 824 } 825 826 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 827 rwq->page_shift = order_base_2(page_size); 828 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 829 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 830 831 mlx5_ib_dbg( 832 dev, 833 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 834 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 835 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 836 offset); 837 838 err = mlx5_ib_db_map_user(ucontext, ucmd->db_addr, &rwq->db); 839 if (err) { 840 mlx5_ib_dbg(dev, "map failed\n"); 841 goto err_umem; 842 } 843 844 return 0; 845 846 err_umem: 847 ib_umem_release(rwq->umem); 848 return err; 849 } 850 851 static int adjust_bfregn(struct mlx5_ib_dev *dev, 852 struct mlx5_bfreg_info *bfregi, int bfregn) 853 { 854 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 855 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 856 } 857 858 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 859 struct mlx5_ib_qp *qp, struct ib_udata *udata, 860 struct ib_qp_init_attr *attr, u32 **in, 861 struct mlx5_ib_create_qp_resp *resp, int *inlen, 862 struct mlx5_ib_qp_base *base, 863 struct mlx5_ib_create_qp *ucmd) 864 { 865 struct mlx5_ib_ucontext *context; 866 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 867 unsigned int page_offset_quantized = 0; 868 unsigned long page_size = 0; 869 int uar_index = 0; 870 int bfregn; 871 int ncont = 0; 872 __be64 *pas; 873 void *qpc; 874 int err; 875 u16 uid; 876 u32 uar_flags; 877 878 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 879 ibucontext); 880 uar_flags = qp->flags_en & 881 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 882 switch (uar_flags) { 883 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 884 uar_index = ucmd->bfreg_index; 885 bfregn = MLX5_IB_INVALID_BFREG; 886 break; 887 case MLX5_QP_FLAG_BFREG_INDEX: 888 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 889 ucmd->bfreg_index, true); 890 if (uar_index < 0) 891 return uar_index; 892 bfregn = MLX5_IB_INVALID_BFREG; 893 break; 894 case 0: 895 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 896 return -EINVAL; 897 bfregn = alloc_bfreg(dev, &context->bfregi); 898 if (bfregn < 0) 899 return bfregn; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 906 if (bfregn != MLX5_IB_INVALID_BFREG) 907 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 908 false); 909 910 qp->rq.offset = 0; 911 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 912 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 913 914 err = set_user_buf_size(dev, qp, ucmd, base, attr); 915 if (err) 916 goto err_bfreg; 917 918 if (ucmd->buf_addr && ubuffer->buf_size) { 919 ubuffer->buf_addr = ucmd->buf_addr; 920 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 921 ubuffer->buf_size, 0); 922 if (IS_ERR(ubuffer->umem)) { 923 err = PTR_ERR(ubuffer->umem); 924 goto err_bfreg; 925 } 926 page_size = mlx5_umem_find_best_quantized_pgoff( 927 ubuffer->umem, qpc, log_page_size, 928 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 929 &page_offset_quantized); 930 if (!page_size) { 931 err = -EINVAL; 932 goto err_umem; 933 } 934 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 935 } else { 936 ubuffer->umem = NULL; 937 } 938 939 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 940 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 941 *in = kvzalloc(*inlen, GFP_KERNEL); 942 if (!*in) { 943 err = -ENOMEM; 944 goto err_umem; 945 } 946 947 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 948 MLX5_SET(create_qp_in, *in, uid, uid); 949 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 950 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 951 if (ubuffer->umem) { 952 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 953 MLX5_SET(qpc, qpc, log_page_size, 954 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 955 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 956 } 957 MLX5_SET(qpc, qpc, uar_page, uar_index); 958 if (bfregn != MLX5_IB_INVALID_BFREG) 959 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 960 else 961 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 962 qp->bfregn = bfregn; 963 964 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &qp->db); 965 if (err) { 966 mlx5_ib_dbg(dev, "map failed\n"); 967 goto err_free; 968 } 969 970 return 0; 971 972 err_free: 973 kvfree(*in); 974 975 err_umem: 976 ib_umem_release(ubuffer->umem); 977 978 err_bfreg: 979 if (bfregn != MLX5_IB_INVALID_BFREG) 980 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 981 return err; 982 } 983 984 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 985 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 986 { 987 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 988 udata, struct mlx5_ib_ucontext, ibucontext); 989 990 if (udata) { 991 /* User QP */ 992 mlx5_ib_db_unmap_user(context, &qp->db); 993 ib_umem_release(base->ubuffer.umem); 994 995 /* 996 * Free only the BFREGs which are handled by the kernel. 997 * BFREGs of UARs allocated dynamically are handled by user. 998 */ 999 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1000 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1001 return; 1002 } 1003 1004 /* Kernel QP */ 1005 kvfree(qp->sq.wqe_head); 1006 kvfree(qp->sq.w_list); 1007 kvfree(qp->sq.wrid); 1008 kvfree(qp->sq.wr_data); 1009 kvfree(qp->rq.wrid); 1010 if (qp->db.db) 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 if (qp->buf.frags) 1013 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1014 } 1015 1016 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1017 struct ib_qp_init_attr *init_attr, 1018 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1019 struct mlx5_ib_qp_base *base) 1020 { 1021 int uar_index; 1022 void *qpc; 1023 int err; 1024 1025 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1026 qp->bf.bfreg = &dev->fp_bfreg; 1027 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1028 qp->bf.bfreg = &dev->wc_bfreg; 1029 else 1030 qp->bf.bfreg = &dev->bfreg; 1031 1032 /* We need to divide by two since each register is comprised of 1033 * two buffers of identical size, namely odd and even 1034 */ 1035 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1036 uar_index = qp->bf.bfreg->index; 1037 1038 err = calc_sq_size(dev, init_attr, qp); 1039 if (err < 0) { 1040 mlx5_ib_dbg(dev, "err %d\n", err); 1041 return err; 1042 } 1043 1044 qp->rq.offset = 0; 1045 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1046 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1047 1048 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1049 &qp->buf, dev->mdev->priv.numa_node); 1050 if (err) { 1051 mlx5_ib_dbg(dev, "err %d\n", err); 1052 return err; 1053 } 1054 1055 if (qp->rq.wqe_cnt) 1056 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1057 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1058 1059 if (qp->sq.wqe_cnt) { 1060 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1061 MLX5_SEND_WQE_BB; 1062 mlx5_init_fbc_offset(qp->buf.frags + 1063 (qp->sq.offset / PAGE_SIZE), 1064 ilog2(MLX5_SEND_WQE_BB), 1065 ilog2(qp->sq.wqe_cnt), 1066 sq_strides_offset, &qp->sq.fbc); 1067 1068 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1069 } 1070 1071 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1072 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1073 *in = kvzalloc(*inlen, GFP_KERNEL); 1074 if (!*in) { 1075 err = -ENOMEM; 1076 goto err_buf; 1077 } 1078 1079 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1080 MLX5_SET(qpc, qpc, uar_page, uar_index); 1081 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1082 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1083 1084 /* Set "fast registration enabled" for all kernel QPs */ 1085 MLX5_SET(qpc, qpc, fre, 1); 1086 MLX5_SET(qpc, qpc, rlky, 1); 1087 1088 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1089 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1090 1091 mlx5_fill_page_frag_array(&qp->buf, 1092 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1093 *in, pas)); 1094 1095 err = mlx5_db_alloc(dev->mdev, &qp->db); 1096 if (err) { 1097 mlx5_ib_dbg(dev, "err %d\n", err); 1098 goto err_free; 1099 } 1100 1101 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1102 sizeof(*qp->sq.wrid), GFP_KERNEL); 1103 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1104 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1105 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1106 sizeof(*qp->rq.wrid), GFP_KERNEL); 1107 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1108 sizeof(*qp->sq.w_list), GFP_KERNEL); 1109 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1110 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1111 1112 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1113 !qp->sq.w_list || !qp->sq.wqe_head) { 1114 err = -ENOMEM; 1115 goto err_wrid; 1116 } 1117 1118 return 0; 1119 1120 err_wrid: 1121 kvfree(qp->sq.wqe_head); 1122 kvfree(qp->sq.w_list); 1123 kvfree(qp->sq.wrid); 1124 kvfree(qp->sq.wr_data); 1125 kvfree(qp->rq.wrid); 1126 mlx5_db_free(dev->mdev, &qp->db); 1127 1128 err_free: 1129 kvfree(*in); 1130 1131 err_buf: 1132 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1133 return err; 1134 } 1135 1136 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1137 { 1138 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1139 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1140 return MLX5_SRQ_RQ; 1141 else if (!qp->has_rq) 1142 return MLX5_ZERO_LEN_RQ; 1143 1144 return MLX5_NON_ZERO_RQ; 1145 } 1146 1147 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1148 struct mlx5_ib_qp *qp, 1149 struct mlx5_ib_sq *sq, u32 tdn, 1150 struct ib_pd *pd) 1151 { 1152 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1153 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1154 1155 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1156 MLX5_SET(tisc, tisc, transport_domain, tdn); 1157 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1158 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1159 1160 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1161 } 1162 1163 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1164 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1165 { 1166 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1167 } 1168 1169 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1170 { 1171 if (sq->flow_rule) 1172 mlx5_del_flow_rules(sq->flow_rule); 1173 sq->flow_rule = NULL; 1174 } 1175 1176 static bool fr_supported(int ts_cap) 1177 { 1178 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1179 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1180 } 1181 1182 static int get_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1183 bool fr_sup, bool rt_sup) 1184 { 1185 if (cq->private_flags & MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS) { 1186 if (!rt_sup) { 1187 mlx5_ib_dbg(dev, 1188 "Real time TS format is not supported\n"); 1189 return -EOPNOTSUPP; 1190 } 1191 return MLX5_TIMESTAMP_FORMAT_REAL_TIME; 1192 } 1193 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1194 if (!fr_sup) { 1195 mlx5_ib_dbg(dev, 1196 "Free running TS format is not supported\n"); 1197 return -EOPNOTSUPP; 1198 } 1199 return MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1200 } 1201 return fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1202 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1203 } 1204 1205 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *recv_cq) 1206 { 1207 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, rq_ts_format); 1208 1209 return get_ts_format(dev, recv_cq, fr_supported(ts_cap), 1210 rt_supported(ts_cap)); 1211 } 1212 1213 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1214 { 1215 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, sq_ts_format); 1216 1217 return get_ts_format(dev, send_cq, fr_supported(ts_cap), 1218 rt_supported(ts_cap)); 1219 } 1220 1221 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1222 struct mlx5_ib_cq *recv_cq) 1223 { 1224 u8 ts_cap = MLX5_CAP_ROCE(dev->mdev, qp_ts_format); 1225 bool fr_sup = fr_supported(ts_cap); 1226 bool rt_sup = rt_supported(ts_cap); 1227 u8 default_ts = fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1228 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1229 int send_ts_format = 1230 send_cq ? get_ts_format(dev, send_cq, fr_sup, rt_sup) : 1231 default_ts; 1232 int recv_ts_format = 1233 recv_cq ? get_ts_format(dev, recv_cq, fr_sup, rt_sup) : 1234 default_ts; 1235 1236 if (send_ts_format < 0 || recv_ts_format < 0) 1237 return -EOPNOTSUPP; 1238 1239 if (send_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1240 recv_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1241 send_ts_format != recv_ts_format) { 1242 mlx5_ib_dbg( 1243 dev, 1244 "The send ts_format does not match the receive ts_format\n"); 1245 return -EOPNOTSUPP; 1246 } 1247 1248 return send_ts_format == default_ts ? recv_ts_format : send_ts_format; 1249 } 1250 1251 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1252 struct ib_udata *udata, 1253 struct mlx5_ib_sq *sq, void *qpin, 1254 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1255 { 1256 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1257 __be64 *pas; 1258 void *in; 1259 void *sqc; 1260 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1261 void *wq; 1262 int inlen; 1263 int err; 1264 unsigned int page_offset_quantized; 1265 unsigned long page_size; 1266 int ts_format; 1267 1268 ts_format = get_sq_ts_format(dev, cq); 1269 if (ts_format < 0) 1270 return ts_format; 1271 1272 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1273 ubuffer->buf_size, 0); 1274 if (IS_ERR(sq->ubuffer.umem)) 1275 return PTR_ERR(sq->ubuffer.umem); 1276 page_size = mlx5_umem_find_best_quantized_pgoff( 1277 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1278 page_offset, 64, &page_offset_quantized); 1279 if (!page_size) { 1280 err = -EINVAL; 1281 goto err_umem; 1282 } 1283 1284 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1285 sizeof(u64) * 1286 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1287 in = kvzalloc(inlen, GFP_KERNEL); 1288 if (!in) { 1289 err = -ENOMEM; 1290 goto err_umem; 1291 } 1292 1293 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1294 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1295 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1296 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1297 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1298 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1299 MLX5_SET(sqc, sqc, ts_format, ts_format); 1300 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1301 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1302 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1303 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1304 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1305 MLX5_CAP_ETH(dev->mdev, swp)) 1306 MLX5_SET(sqc, sqc, allow_swp, 1); 1307 1308 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1309 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1310 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1311 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1312 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1313 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1314 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1315 MLX5_SET(wq, wq, log_wq_pg_sz, 1316 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1317 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1318 1319 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1320 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1321 1322 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1323 1324 kvfree(in); 1325 1326 if (err) 1327 goto err_umem; 1328 1329 return 0; 1330 1331 err_umem: 1332 ib_umem_release(sq->ubuffer.umem); 1333 sq->ubuffer.umem = NULL; 1334 1335 return err; 1336 } 1337 1338 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1339 struct mlx5_ib_sq *sq) 1340 { 1341 destroy_flow_rule_vport_sq(sq); 1342 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1343 ib_umem_release(sq->ubuffer.umem); 1344 } 1345 1346 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1347 struct mlx5_ib_rq *rq, void *qpin, 1348 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1349 { 1350 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1351 __be64 *pas; 1352 void *in; 1353 void *rqc; 1354 void *wq; 1355 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1356 struct ib_umem *umem = rq->base.ubuffer.umem; 1357 unsigned int page_offset_quantized; 1358 unsigned long page_size = 0; 1359 int ts_format; 1360 size_t inlen; 1361 int err; 1362 1363 ts_format = get_rq_ts_format(dev, cq); 1364 if (ts_format < 0) 1365 return ts_format; 1366 1367 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1368 MLX5_ADAPTER_PAGE_SHIFT, 1369 page_offset, 64, 1370 &page_offset_quantized); 1371 if (!page_size) 1372 return -EINVAL; 1373 1374 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1375 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1376 in = kvzalloc(inlen, GFP_KERNEL); 1377 if (!in) 1378 return -ENOMEM; 1379 1380 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1381 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1382 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1383 MLX5_SET(rqc, rqc, vsd, 1); 1384 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1385 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1386 MLX5_SET(rqc, rqc, ts_format, ts_format); 1387 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1388 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1389 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1390 1391 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1392 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1393 1394 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1395 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1396 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1397 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1398 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1399 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1400 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1401 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1402 MLX5_SET(wq, wq, log_wq_pg_sz, 1403 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1404 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1405 1406 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1407 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1408 1409 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1410 1411 kvfree(in); 1412 1413 return err; 1414 } 1415 1416 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1417 struct mlx5_ib_rq *rq) 1418 { 1419 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1420 } 1421 1422 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1423 struct mlx5_ib_rq *rq, 1424 u32 qp_flags_en, 1425 struct ib_pd *pd) 1426 { 1427 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1428 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1429 mlx5_ib_disable_lb(dev, false, true); 1430 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1431 } 1432 1433 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1434 struct mlx5_ib_rq *rq, u32 tdn, 1435 u32 *qp_flags_en, struct ib_pd *pd, 1436 u32 *out) 1437 { 1438 u8 lb_flag = 0; 1439 u32 *in; 1440 void *tirc; 1441 int inlen; 1442 int err; 1443 1444 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1445 in = kvzalloc(inlen, GFP_KERNEL); 1446 if (!in) 1447 return -ENOMEM; 1448 1449 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1450 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1451 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1452 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1453 MLX5_SET(tirc, tirc, transport_domain, tdn); 1454 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1455 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1456 1457 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1458 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1459 1460 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1461 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1462 1463 if (dev->is_rep) { 1464 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1465 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1466 } 1467 1468 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1469 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1470 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1471 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1472 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1473 err = mlx5_ib_enable_lb(dev, false, true); 1474 1475 if (err) 1476 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1477 } 1478 kvfree(in); 1479 1480 return err; 1481 } 1482 1483 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1484 u32 *in, size_t inlen, struct ib_pd *pd, 1485 struct ib_udata *udata, 1486 struct mlx5_ib_create_qp_resp *resp, 1487 struct ib_qp_init_attr *init_attr) 1488 { 1489 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1490 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1491 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1492 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1493 udata, struct mlx5_ib_ucontext, ibucontext); 1494 int err; 1495 u32 tdn = mucontext->tdn; 1496 u16 uid = to_mpd(pd)->uid; 1497 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1498 1499 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1500 return -EINVAL; 1501 if (qp->sq.wqe_cnt) { 1502 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1503 if (err) 1504 return err; 1505 1506 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1507 to_mcq(init_attr->send_cq)); 1508 if (err) 1509 goto err_destroy_tis; 1510 1511 if (uid) { 1512 resp->tisn = sq->tisn; 1513 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1514 resp->sqn = sq->base.mqp.qpn; 1515 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1516 } 1517 1518 sq->base.container_mibqp = qp; 1519 sq->base.mqp.event = mlx5_ib_qp_event; 1520 } 1521 1522 if (qp->rq.wqe_cnt) { 1523 rq->base.container_mibqp = qp; 1524 1525 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1526 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1527 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1528 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1529 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1530 to_mcq(init_attr->recv_cq)); 1531 if (err) 1532 goto err_destroy_sq; 1533 1534 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1535 out); 1536 if (err) 1537 goto err_destroy_rq; 1538 1539 if (uid) { 1540 resp->rqn = rq->base.mqp.qpn; 1541 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1542 resp->tirn = rq->tirn; 1543 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1544 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1545 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1546 resp->tir_icm_addr = MLX5_GET( 1547 create_tir_out, out, icm_address_31_0); 1548 resp->tir_icm_addr |= 1549 (u64)MLX5_GET(create_tir_out, out, 1550 icm_address_39_32) 1551 << 32; 1552 resp->tir_icm_addr |= 1553 (u64)MLX5_GET(create_tir_out, out, 1554 icm_address_63_40) 1555 << 40; 1556 resp->comp_mask |= 1557 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1558 } 1559 } 1560 } 1561 1562 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1563 rq->base.mqp.qpn; 1564 return 0; 1565 1566 err_destroy_rq: 1567 destroy_raw_packet_qp_rq(dev, rq); 1568 err_destroy_sq: 1569 if (!qp->sq.wqe_cnt) 1570 return err; 1571 destroy_raw_packet_qp_sq(dev, sq); 1572 err_destroy_tis: 1573 destroy_raw_packet_qp_tis(dev, sq, pd); 1574 1575 return err; 1576 } 1577 1578 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1579 struct mlx5_ib_qp *qp) 1580 { 1581 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1582 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1583 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1584 1585 if (qp->rq.wqe_cnt) { 1586 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1587 destroy_raw_packet_qp_rq(dev, rq); 1588 } 1589 1590 if (qp->sq.wqe_cnt) { 1591 destroy_raw_packet_qp_sq(dev, sq); 1592 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1593 } 1594 } 1595 1596 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1597 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1598 { 1599 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1600 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1601 1602 sq->sq = &qp->sq; 1603 rq->rq = &qp->rq; 1604 sq->doorbell = &qp->db; 1605 rq->doorbell = &qp->db; 1606 } 1607 1608 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1609 { 1610 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1611 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1612 mlx5_ib_disable_lb(dev, false, true); 1613 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1614 to_mpd(qp->ibqp.pd)->uid); 1615 } 1616 1617 struct mlx5_create_qp_params { 1618 struct ib_udata *udata; 1619 size_t inlen; 1620 size_t outlen; 1621 size_t ucmd_size; 1622 void *ucmd; 1623 u8 is_rss_raw : 1; 1624 struct ib_qp_init_attr *attr; 1625 u32 uidx; 1626 struct mlx5_ib_create_qp_resp resp; 1627 }; 1628 1629 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1630 struct mlx5_ib_qp *qp, 1631 struct mlx5_create_qp_params *params) 1632 { 1633 struct ib_qp_init_attr *init_attr = params->attr; 1634 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1635 struct ib_udata *udata = params->udata; 1636 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1637 udata, struct mlx5_ib_ucontext, ibucontext); 1638 int inlen; 1639 int outlen; 1640 int err; 1641 u32 *in; 1642 u32 *out; 1643 void *tirc; 1644 void *hfso; 1645 u32 selected_fields = 0; 1646 u32 outer_l4; 1647 u32 tdn = mucontext->tdn; 1648 u8 lb_flag = 0; 1649 1650 if (ucmd->comp_mask) { 1651 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1652 return -EOPNOTSUPP; 1653 } 1654 1655 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1656 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1657 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1658 return -EOPNOTSUPP; 1659 } 1660 1661 if (dev->is_rep) 1662 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1663 1664 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1665 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1666 1667 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1668 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1669 1670 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1671 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1672 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1673 if (!in) 1674 return -ENOMEM; 1675 1676 out = in + MLX5_ST_SZ_DW(create_tir_in); 1677 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1678 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1679 MLX5_SET(tirc, tirc, disp_type, 1680 MLX5_TIRC_DISP_TYPE_INDIRECT); 1681 MLX5_SET(tirc, tirc, indirect_table, 1682 init_attr->rwq_ind_tbl->ind_tbl_num); 1683 MLX5_SET(tirc, tirc, transport_domain, tdn); 1684 1685 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1686 1687 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1688 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1689 1690 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1691 1692 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1693 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1694 else 1695 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1696 1697 switch (ucmd->rx_hash_function) { 1698 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1699 { 1700 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1701 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1702 1703 if (len != ucmd->rx_key_len) { 1704 err = -EINVAL; 1705 goto err; 1706 } 1707 1708 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1709 memcpy(rss_key, ucmd->rx_hash_key, len); 1710 break; 1711 } 1712 default: 1713 err = -EOPNOTSUPP; 1714 goto err; 1715 } 1716 1717 if (!ucmd->rx_hash_fields_mask) { 1718 /* special case when this TIR serves as steering entry without hashing */ 1719 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1720 goto create_tir; 1721 err = -EINVAL; 1722 goto err; 1723 } 1724 1725 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1726 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1727 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1728 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1729 err = -EINVAL; 1730 goto err; 1731 } 1732 1733 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1734 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1735 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1736 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1737 MLX5_L3_PROT_TYPE_IPV4); 1738 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1739 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1740 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1741 MLX5_L3_PROT_TYPE_IPV6); 1742 1743 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1744 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1745 << 0 | 1746 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1747 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1748 << 1 | 1749 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1750 1751 /* Check that only one l4 protocol is set */ 1752 if (outer_l4 & (outer_l4 - 1)) { 1753 err = -EINVAL; 1754 goto err; 1755 } 1756 1757 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1758 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1759 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1760 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1761 MLX5_L4_PROT_TYPE_TCP); 1762 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1763 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1764 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1765 MLX5_L4_PROT_TYPE_UDP); 1766 1767 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1768 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1769 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1770 1771 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1772 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1773 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1774 1775 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1776 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1777 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1778 1779 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1780 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1781 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1782 1783 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1784 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1785 1786 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1787 1788 create_tir: 1789 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1790 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1791 1792 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1793 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1794 err = mlx5_ib_enable_lb(dev, false, true); 1795 1796 if (err) 1797 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1798 to_mpd(pd)->uid); 1799 } 1800 1801 if (err) 1802 goto err; 1803 1804 if (mucontext->devx_uid) { 1805 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1806 params->resp.tirn = qp->rss_qp.tirn; 1807 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1808 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1809 params->resp.tir_icm_addr = 1810 MLX5_GET(create_tir_out, out, icm_address_31_0); 1811 params->resp.tir_icm_addr |= 1812 (u64)MLX5_GET(create_tir_out, out, 1813 icm_address_39_32) 1814 << 32; 1815 params->resp.tir_icm_addr |= 1816 (u64)MLX5_GET(create_tir_out, out, 1817 icm_address_63_40) 1818 << 40; 1819 params->resp.comp_mask |= 1820 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1821 } 1822 } 1823 1824 kvfree(in); 1825 /* qpn is reserved for that QP */ 1826 qp->trans_qp.base.mqp.qpn = 0; 1827 qp->is_rss = true; 1828 return 0; 1829 1830 err: 1831 kvfree(in); 1832 return err; 1833 } 1834 1835 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1836 struct mlx5_ib_qp *qp, 1837 struct ib_qp_init_attr *init_attr, 1838 void *qpc) 1839 { 1840 int scqe_sz; 1841 bool allow_scat_cqe = false; 1842 1843 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1844 1845 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1846 return; 1847 1848 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1849 if (scqe_sz == 128) { 1850 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1851 return; 1852 } 1853 1854 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1855 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1856 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1857 } 1858 1859 static int atomic_size_to_mode(int size_mask) 1860 { 1861 /* driver does not support atomic_size > 256B 1862 * and does not know how to translate bigger sizes 1863 */ 1864 int supported_size_mask = size_mask & 0x1ff; 1865 int log_max_size; 1866 1867 if (!supported_size_mask) 1868 return -EOPNOTSUPP; 1869 1870 log_max_size = __fls(supported_size_mask); 1871 1872 if (log_max_size > 3) 1873 return log_max_size; 1874 1875 return MLX5_ATOMIC_MODE_8B; 1876 } 1877 1878 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1879 enum ib_qp_type qp_type) 1880 { 1881 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1882 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1883 int atomic_mode = -EOPNOTSUPP; 1884 int atomic_size_mask; 1885 1886 if (!atomic) 1887 return -EOPNOTSUPP; 1888 1889 if (qp_type == MLX5_IB_QPT_DCT) 1890 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1891 else 1892 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1893 1894 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1895 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1896 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1897 1898 if (atomic_mode <= 0 && 1899 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1900 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1901 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1902 1903 return atomic_mode; 1904 } 1905 1906 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1907 struct mlx5_create_qp_params *params) 1908 { 1909 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1910 struct ib_qp_init_attr *attr = params->attr; 1911 u32 uidx = params->uidx; 1912 struct mlx5_ib_resources *devr = &dev->devr; 1913 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1914 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1915 struct mlx5_core_dev *mdev = dev->mdev; 1916 struct mlx5_ib_qp_base *base; 1917 unsigned long flags; 1918 void *qpc; 1919 u32 *in; 1920 int err; 1921 1922 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1923 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1924 1925 in = kvzalloc(inlen, GFP_KERNEL); 1926 if (!in) 1927 return -ENOMEM; 1928 1929 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd) 1930 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1931 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1932 1933 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 1934 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1935 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 1936 1937 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1938 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1939 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1940 MLX5_SET(qpc, qpc, cd_master, 1); 1941 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1942 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1943 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1944 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1945 1946 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1947 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 1948 MLX5_SET(qpc, qpc, no_sq, 1); 1949 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1950 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1951 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1952 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 1953 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1954 1955 /* 0xffffff means we ask to work with cqe version 0 */ 1956 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1957 MLX5_SET(qpc, qpc, user_index, uidx); 1958 1959 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1960 MLX5_SET(qpc, qpc, end_padding_mode, 1961 MLX5_WQ_END_PAD_MODE_ALIGN); 1962 /* Special case to clean flag */ 1963 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 1964 } 1965 1966 base = &qp->trans_qp.base; 1967 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 1968 kvfree(in); 1969 if (err) 1970 return err; 1971 1972 base->container_mibqp = qp; 1973 base->mqp.event = mlx5_ib_qp_event; 1974 if (MLX5_CAP_GEN(mdev, ece_support)) 1975 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 1976 1977 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1978 list_add_tail(&qp->qps_list, &dev->qp_list); 1979 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1980 1981 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 1982 return 0; 1983 } 1984 1985 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1986 struct mlx5_ib_qp *qp, 1987 struct mlx5_create_qp_params *params) 1988 { 1989 struct ib_qp_init_attr *init_attr = params->attr; 1990 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1991 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1992 struct ib_udata *udata = params->udata; 1993 u32 uidx = params->uidx; 1994 struct mlx5_ib_resources *devr = &dev->devr; 1995 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1996 struct mlx5_core_dev *mdev = dev->mdev; 1997 struct mlx5_ib_cq *send_cq; 1998 struct mlx5_ib_cq *recv_cq; 1999 unsigned long flags; 2000 struct mlx5_ib_qp_base *base; 2001 int ts_format; 2002 int mlx5_st; 2003 void *qpc; 2004 u32 *in; 2005 int err; 2006 2007 spin_lock_init(&qp->sq.lock); 2008 spin_lock_init(&qp->rq.lock); 2009 2010 mlx5_st = to_mlx5_st(qp->type); 2011 if (mlx5_st < 0) 2012 return -EINVAL; 2013 2014 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2015 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2016 2017 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2018 qp->underlay_qpn = init_attr->source_qpn; 2019 2020 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2021 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2022 &qp->raw_packet_qp.rq.base : 2023 &qp->trans_qp.base; 2024 2025 qp->has_rq = qp_has_rq(init_attr); 2026 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2027 if (err) { 2028 mlx5_ib_dbg(dev, "err %d\n", err); 2029 return err; 2030 } 2031 2032 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2033 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2034 return -EINVAL; 2035 2036 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2037 return -EINVAL; 2038 2039 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2040 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2041 to_mcq(init_attr->recv_cq)); 2042 if (ts_format < 0) 2043 return ts_format; 2044 } 2045 2046 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2047 &inlen, base, ucmd); 2048 if (err) 2049 return err; 2050 2051 if (is_sqp(init_attr->qp_type)) 2052 qp->port = init_attr->port_num; 2053 2054 if (MLX5_CAP_GEN(mdev, ece_support)) 2055 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2056 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2057 2058 MLX5_SET(qpc, qpc, st, mlx5_st); 2059 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2060 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2061 2062 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2063 MLX5_SET(qpc, qpc, wq_signature, 1); 2064 2065 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2066 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2067 2068 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2069 MLX5_SET(qpc, qpc, cd_master, 1); 2070 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2071 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2072 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2073 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2074 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2075 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2076 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2077 (init_attr->qp_type == IB_QPT_RC || 2078 init_attr->qp_type == IB_QPT_UC)) { 2079 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2080 2081 MLX5_SET(qpc, qpc, cs_res, 2082 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2083 MLX5_RES_SCAT_DATA32_CQE); 2084 } 2085 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2086 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2087 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2088 2089 if (qp->rq.wqe_cnt) { 2090 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2091 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2092 } 2093 2094 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2095 MLX5_SET(qpc, qpc, ts_format, ts_format); 2096 2097 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2098 2099 if (qp->sq.wqe_cnt) { 2100 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2101 } else { 2102 MLX5_SET(qpc, qpc, no_sq, 1); 2103 if (init_attr->srq && 2104 init_attr->srq->srq_type == IB_SRQT_TM) 2105 MLX5_SET(qpc, qpc, offload_type, 2106 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2107 } 2108 2109 /* Set default resources */ 2110 switch (init_attr->qp_type) { 2111 case IB_QPT_XRC_INI: 2112 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2113 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2114 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2115 break; 2116 default: 2117 if (init_attr->srq) { 2118 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2119 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2120 } else { 2121 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2122 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2123 } 2124 } 2125 2126 if (init_attr->send_cq) 2127 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2128 2129 if (init_attr->recv_cq) 2130 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2131 2132 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2133 2134 /* 0xffffff means we ask to work with cqe version 0 */ 2135 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2136 MLX5_SET(qpc, qpc, user_index, uidx); 2137 2138 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2139 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2140 MLX5_SET(qpc, qpc, end_padding_mode, 2141 MLX5_WQ_END_PAD_MODE_ALIGN); 2142 /* Special case to clean flag */ 2143 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2144 } 2145 2146 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2147 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2148 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2149 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2150 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2151 ¶ms->resp, init_attr); 2152 } else 2153 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2154 2155 kvfree(in); 2156 if (err) 2157 goto err_create; 2158 2159 base->container_mibqp = qp; 2160 base->mqp.event = mlx5_ib_qp_event; 2161 if (MLX5_CAP_GEN(mdev, ece_support)) 2162 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2163 2164 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2165 &send_cq, &recv_cq); 2166 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2167 mlx5_ib_lock_cqs(send_cq, recv_cq); 2168 /* Maintain device to QPs access, needed for further handling via reset 2169 * flow 2170 */ 2171 list_add_tail(&qp->qps_list, &dev->qp_list); 2172 /* Maintain CQ to QPs access, needed for further handling via reset flow 2173 */ 2174 if (send_cq) 2175 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2176 if (recv_cq) 2177 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2178 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2179 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2180 2181 return 0; 2182 2183 err_create: 2184 destroy_qp(dev, qp, base, udata); 2185 return err; 2186 } 2187 2188 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2189 struct mlx5_ib_qp *qp, 2190 struct mlx5_create_qp_params *params) 2191 { 2192 struct ib_qp_init_attr *attr = params->attr; 2193 u32 uidx = params->uidx; 2194 struct mlx5_ib_resources *devr = &dev->devr; 2195 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2196 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2197 struct mlx5_core_dev *mdev = dev->mdev; 2198 struct mlx5_ib_cq *send_cq; 2199 struct mlx5_ib_cq *recv_cq; 2200 unsigned long flags; 2201 struct mlx5_ib_qp_base *base; 2202 int mlx5_st; 2203 void *qpc; 2204 u32 *in; 2205 int err; 2206 2207 spin_lock_init(&qp->sq.lock); 2208 spin_lock_init(&qp->rq.lock); 2209 2210 mlx5_st = to_mlx5_st(qp->type); 2211 if (mlx5_st < 0) 2212 return -EINVAL; 2213 2214 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2215 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2216 2217 base = &qp->trans_qp.base; 2218 2219 qp->has_rq = qp_has_rq(attr); 2220 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2221 if (err) { 2222 mlx5_ib_dbg(dev, "err %d\n", err); 2223 return err; 2224 } 2225 2226 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2227 if (err) 2228 return err; 2229 2230 if (is_sqp(attr->qp_type)) 2231 qp->port = attr->port_num; 2232 2233 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2234 2235 MLX5_SET(qpc, qpc, st, mlx5_st); 2236 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2237 2238 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2239 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2240 else 2241 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2242 2243 2244 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2245 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2246 2247 if (qp->rq.wqe_cnt) { 2248 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2249 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2250 } 2251 2252 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2253 2254 if (qp->sq.wqe_cnt) 2255 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2256 else 2257 MLX5_SET(qpc, qpc, no_sq, 1); 2258 2259 if (attr->srq) { 2260 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2261 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2262 to_msrq(attr->srq)->msrq.srqn); 2263 } else { 2264 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2265 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2266 to_msrq(devr->s1)->msrq.srqn); 2267 } 2268 2269 if (attr->send_cq) 2270 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2271 2272 if (attr->recv_cq) 2273 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2274 2275 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2276 2277 /* 0xffffff means we ask to work with cqe version 0 */ 2278 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2279 MLX5_SET(qpc, qpc, user_index, uidx); 2280 2281 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2282 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2283 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2284 2285 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2286 kvfree(in); 2287 if (err) 2288 goto err_create; 2289 2290 base->container_mibqp = qp; 2291 base->mqp.event = mlx5_ib_qp_event; 2292 2293 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2294 &send_cq, &recv_cq); 2295 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2296 mlx5_ib_lock_cqs(send_cq, recv_cq); 2297 /* Maintain device to QPs access, needed for further handling via reset 2298 * flow 2299 */ 2300 list_add_tail(&qp->qps_list, &dev->qp_list); 2301 /* Maintain CQ to QPs access, needed for further handling via reset flow 2302 */ 2303 if (send_cq) 2304 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2305 if (recv_cq) 2306 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2307 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2308 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2309 2310 return 0; 2311 2312 err_create: 2313 destroy_qp(dev, qp, base, NULL); 2314 return err; 2315 } 2316 2317 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2318 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2319 { 2320 if (send_cq) { 2321 if (recv_cq) { 2322 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2323 spin_lock(&send_cq->lock); 2324 spin_lock_nested(&recv_cq->lock, 2325 SINGLE_DEPTH_NESTING); 2326 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2327 spin_lock(&send_cq->lock); 2328 __acquire(&recv_cq->lock); 2329 } else { 2330 spin_lock(&recv_cq->lock); 2331 spin_lock_nested(&send_cq->lock, 2332 SINGLE_DEPTH_NESTING); 2333 } 2334 } else { 2335 spin_lock(&send_cq->lock); 2336 __acquire(&recv_cq->lock); 2337 } 2338 } else if (recv_cq) { 2339 spin_lock(&recv_cq->lock); 2340 __acquire(&send_cq->lock); 2341 } else { 2342 __acquire(&send_cq->lock); 2343 __acquire(&recv_cq->lock); 2344 } 2345 } 2346 2347 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2348 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2349 { 2350 if (send_cq) { 2351 if (recv_cq) { 2352 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2353 spin_unlock(&recv_cq->lock); 2354 spin_unlock(&send_cq->lock); 2355 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2356 __release(&recv_cq->lock); 2357 spin_unlock(&send_cq->lock); 2358 } else { 2359 spin_unlock(&send_cq->lock); 2360 spin_unlock(&recv_cq->lock); 2361 } 2362 } else { 2363 __release(&recv_cq->lock); 2364 spin_unlock(&send_cq->lock); 2365 } 2366 } else if (recv_cq) { 2367 __release(&send_cq->lock); 2368 spin_unlock(&recv_cq->lock); 2369 } else { 2370 __release(&recv_cq->lock); 2371 __release(&send_cq->lock); 2372 } 2373 } 2374 2375 static void get_cqs(enum ib_qp_type qp_type, 2376 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2377 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2378 { 2379 switch (qp_type) { 2380 case IB_QPT_XRC_TGT: 2381 *send_cq = NULL; 2382 *recv_cq = NULL; 2383 break; 2384 case MLX5_IB_QPT_REG_UMR: 2385 case IB_QPT_XRC_INI: 2386 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2387 *recv_cq = NULL; 2388 break; 2389 2390 case IB_QPT_SMI: 2391 case MLX5_IB_QPT_HW_GSI: 2392 case IB_QPT_RC: 2393 case IB_QPT_UC: 2394 case IB_QPT_UD: 2395 case IB_QPT_RAW_PACKET: 2396 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2397 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2398 break; 2399 default: 2400 *send_cq = NULL; 2401 *recv_cq = NULL; 2402 break; 2403 } 2404 } 2405 2406 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2407 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2408 u8 lag_tx_affinity); 2409 2410 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2411 struct ib_udata *udata) 2412 { 2413 struct mlx5_ib_cq *send_cq, *recv_cq; 2414 struct mlx5_ib_qp_base *base; 2415 unsigned long flags; 2416 int err; 2417 2418 if (qp->is_rss) { 2419 destroy_rss_raw_qp_tir(dev, qp); 2420 return; 2421 } 2422 2423 base = (qp->type == IB_QPT_RAW_PACKET || 2424 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2425 &qp->raw_packet_qp.rq.base : 2426 &qp->trans_qp.base; 2427 2428 if (qp->state != IB_QPS_RESET) { 2429 if (qp->type != IB_QPT_RAW_PACKET && 2430 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2431 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2432 NULL, &base->mqp, NULL); 2433 } else { 2434 struct mlx5_modify_raw_qp_param raw_qp_param = { 2435 .operation = MLX5_CMD_OP_2RST_QP 2436 }; 2437 2438 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2439 } 2440 if (err) 2441 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2442 base->mqp.qpn); 2443 } 2444 2445 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2446 &recv_cq); 2447 2448 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2449 mlx5_ib_lock_cqs(send_cq, recv_cq); 2450 /* del from lists under both locks above to protect reset flow paths */ 2451 list_del(&qp->qps_list); 2452 if (send_cq) 2453 list_del(&qp->cq_send_list); 2454 2455 if (recv_cq) 2456 list_del(&qp->cq_recv_list); 2457 2458 if (!udata) { 2459 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2460 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2461 if (send_cq != recv_cq) 2462 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2463 NULL); 2464 } 2465 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2466 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2467 2468 if (qp->type == IB_QPT_RAW_PACKET || 2469 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2470 destroy_raw_packet_qp(dev, qp); 2471 } else { 2472 err = mlx5_core_destroy_qp(dev, &base->mqp); 2473 if (err) 2474 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2475 base->mqp.qpn); 2476 } 2477 2478 destroy_qp(dev, qp, base, udata); 2479 } 2480 2481 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2482 struct mlx5_ib_qp *qp, 2483 struct mlx5_create_qp_params *params) 2484 { 2485 struct ib_qp_init_attr *attr = params->attr; 2486 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2487 u32 uidx = params->uidx; 2488 void *dctc; 2489 2490 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2491 return -EOPNOTSUPP; 2492 2493 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2494 if (!qp->dct.in) 2495 return -ENOMEM; 2496 2497 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2498 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2499 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2500 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2501 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2502 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2503 MLX5_SET(dctc, dctc, user_index, uidx); 2504 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2505 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2506 2507 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2508 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2509 2510 if (rcqe_sz == 128) 2511 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2512 } 2513 2514 qp->state = IB_QPS_RESET; 2515 rdma_restrack_no_track(&qp->ibqp.res); 2516 return 0; 2517 } 2518 2519 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2520 enum ib_qp_type *type) 2521 { 2522 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2523 goto out; 2524 2525 switch (attr->qp_type) { 2526 case IB_QPT_XRC_TGT: 2527 case IB_QPT_XRC_INI: 2528 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2529 goto out; 2530 fallthrough; 2531 case IB_QPT_RC: 2532 case IB_QPT_UC: 2533 case IB_QPT_SMI: 2534 case MLX5_IB_QPT_HW_GSI: 2535 case IB_QPT_DRIVER: 2536 case IB_QPT_GSI: 2537 case IB_QPT_RAW_PACKET: 2538 case IB_QPT_UD: 2539 case MLX5_IB_QPT_REG_UMR: 2540 break; 2541 default: 2542 goto out; 2543 } 2544 2545 *type = attr->qp_type; 2546 return 0; 2547 2548 out: 2549 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2550 return -EOPNOTSUPP; 2551 } 2552 2553 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2554 struct ib_qp_init_attr *attr, 2555 struct ib_udata *udata) 2556 { 2557 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2558 udata, struct mlx5_ib_ucontext, ibucontext); 2559 2560 if (!udata) { 2561 /* Kernel create_qp callers */ 2562 if (attr->rwq_ind_tbl) 2563 return -EOPNOTSUPP; 2564 2565 switch (attr->qp_type) { 2566 case IB_QPT_RAW_PACKET: 2567 case IB_QPT_DRIVER: 2568 return -EOPNOTSUPP; 2569 default: 2570 return 0; 2571 } 2572 } 2573 2574 /* Userspace create_qp callers */ 2575 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2576 mlx5_ib_dbg(dev, 2577 "Raw Packet QP is only supported for CQE version > 0\n"); 2578 return -EINVAL; 2579 } 2580 2581 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2582 mlx5_ib_dbg(dev, 2583 "Wrong QP type %d for the RWQ indirect table\n", 2584 attr->qp_type); 2585 return -EINVAL; 2586 } 2587 2588 /* 2589 * We don't need to see this warning, it means that kernel code 2590 * missing ib_pd. Placed here to catch developer's mistakes. 2591 */ 2592 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2593 "There is a missing PD pointer assignment\n"); 2594 return 0; 2595 } 2596 2597 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2598 bool cond, struct mlx5_ib_qp *qp) 2599 { 2600 if (!(*flags & flag)) 2601 return; 2602 2603 if (cond) { 2604 qp->flags_en |= flag; 2605 *flags &= ~flag; 2606 return; 2607 } 2608 2609 switch (flag) { 2610 case MLX5_QP_FLAG_SCATTER_CQE: 2611 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2612 /* 2613 * We don't return error if these flags were provided, 2614 * and mlx5 doesn't have right capability. 2615 */ 2616 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2617 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2618 return; 2619 default: 2620 break; 2621 } 2622 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2623 } 2624 2625 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2626 void *ucmd, struct ib_qp_init_attr *attr) 2627 { 2628 struct mlx5_core_dev *mdev = dev->mdev; 2629 bool cond; 2630 int flags; 2631 2632 if (attr->rwq_ind_tbl) 2633 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2634 else 2635 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2636 2637 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2638 case MLX5_QP_FLAG_TYPE_DCI: 2639 qp->type = MLX5_IB_QPT_DCI; 2640 break; 2641 case MLX5_QP_FLAG_TYPE_DCT: 2642 qp->type = MLX5_IB_QPT_DCT; 2643 break; 2644 default: 2645 if (qp->type != IB_QPT_DRIVER) 2646 break; 2647 /* 2648 * It is IB_QPT_DRIVER and or no subtype or 2649 * wrong subtype were provided. 2650 */ 2651 return -EINVAL; 2652 } 2653 2654 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2655 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2656 2657 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2658 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2659 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2660 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2661 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2662 2663 if (qp->type == IB_QPT_RAW_PACKET) { 2664 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2665 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2666 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2667 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2668 cond, qp); 2669 process_vendor_flag(dev, &flags, 2670 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2671 qp); 2672 process_vendor_flag(dev, &flags, 2673 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2674 qp); 2675 } 2676 2677 if (qp->type == IB_QPT_RC) 2678 process_vendor_flag(dev, &flags, 2679 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2680 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2681 2682 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2683 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2684 2685 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2686 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2687 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2688 if (attr->rwq_ind_tbl && cond) { 2689 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2690 cond); 2691 return -EINVAL; 2692 } 2693 2694 if (flags) 2695 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2696 2697 return (flags) ? -EINVAL : 0; 2698 } 2699 2700 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2701 bool cond, struct mlx5_ib_qp *qp) 2702 { 2703 if (!(*flags & flag)) 2704 return; 2705 2706 if (cond) { 2707 qp->flags |= flag; 2708 *flags &= ~flag; 2709 return; 2710 } 2711 2712 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2713 /* 2714 * Special case, if condition didn't meet, it won't be error, 2715 * just different in-kernel flow. 2716 */ 2717 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2718 return; 2719 } 2720 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2721 } 2722 2723 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2724 struct ib_qp_init_attr *attr) 2725 { 2726 enum ib_qp_type qp_type = qp->type; 2727 struct mlx5_core_dev *mdev = dev->mdev; 2728 int create_flags = attr->create_flags; 2729 bool cond; 2730 2731 if (qp_type == MLX5_IB_QPT_DCT) 2732 return (create_flags) ? -EINVAL : 0; 2733 2734 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2735 return (create_flags) ? -EINVAL : 0; 2736 2737 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2738 mlx5_get_flow_namespace(dev->mdev, 2739 MLX5_FLOW_NAMESPACE_BYPASS), 2740 qp); 2741 process_create_flag(dev, &create_flags, 2742 IB_QP_CREATE_INTEGRITY_EN, 2743 MLX5_CAP_GEN(mdev, sho), qp); 2744 process_create_flag(dev, &create_flags, 2745 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2746 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2747 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2748 MLX5_CAP_GEN(mdev, cd), qp); 2749 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2750 MLX5_CAP_GEN(mdev, cd), qp); 2751 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2752 MLX5_CAP_GEN(mdev, cd), qp); 2753 2754 if (qp_type == IB_QPT_UD) { 2755 process_create_flag(dev, &create_flags, 2756 IB_QP_CREATE_IPOIB_UD_LSO, 2757 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2758 qp); 2759 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2760 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 2761 cond, qp); 2762 } 2763 2764 if (qp_type == IB_QPT_RAW_PACKET) { 2765 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2766 MLX5_CAP_ETH(mdev, scatter_fcs); 2767 process_create_flag(dev, &create_flags, 2768 IB_QP_CREATE_SCATTER_FCS, cond, qp); 2769 2770 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2771 MLX5_CAP_ETH(mdev, vlan_cap); 2772 process_create_flag(dev, &create_flags, 2773 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 2774 } 2775 2776 process_create_flag(dev, &create_flags, 2777 IB_QP_CREATE_PCI_WRITE_END_PADDING, 2778 MLX5_CAP_GEN(mdev, end_pad), qp); 2779 2780 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 2781 qp_type != MLX5_IB_QPT_REG_UMR, qp); 2782 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 2783 true, qp); 2784 2785 if (create_flags) { 2786 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 2787 create_flags); 2788 return -EOPNOTSUPP; 2789 } 2790 return 0; 2791 } 2792 2793 static int process_udata_size(struct mlx5_ib_dev *dev, 2794 struct mlx5_create_qp_params *params) 2795 { 2796 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 2797 struct ib_udata *udata = params->udata; 2798 size_t outlen = udata->outlen; 2799 size_t inlen = udata->inlen; 2800 2801 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 2802 params->ucmd_size = ucmd; 2803 if (!params->is_rss_raw) { 2804 /* User has old rdma-core, which doesn't support ECE */ 2805 size_t min_inlen = 2806 offsetof(struct mlx5_ib_create_qp, ece_options); 2807 2808 /* 2809 * We will check in check_ucmd_data() that user 2810 * cleared everything after inlen. 2811 */ 2812 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 2813 goto out; 2814 } 2815 2816 /* RSS RAW QP */ 2817 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 2818 return -EINVAL; 2819 2820 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 2821 return -EINVAL; 2822 2823 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 2824 params->ucmd_size = ucmd; 2825 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 2826 return -EINVAL; 2827 2828 params->inlen = min(ucmd, inlen); 2829 out: 2830 if (!params->inlen) 2831 mlx5_ib_dbg(dev, "udata is too small\n"); 2832 2833 return (params->inlen) ? 0 : -EINVAL; 2834 } 2835 2836 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2837 struct mlx5_ib_qp *qp, 2838 struct mlx5_create_qp_params *params) 2839 { 2840 int err; 2841 2842 if (params->is_rss_raw) { 2843 err = create_rss_raw_qp_tir(dev, pd, qp, params); 2844 goto out; 2845 } 2846 2847 switch (qp->type) { 2848 case MLX5_IB_QPT_DCT: 2849 err = create_dct(dev, pd, qp, params); 2850 break; 2851 case IB_QPT_XRC_TGT: 2852 err = create_xrc_tgt_qp(dev, qp, params); 2853 break; 2854 case IB_QPT_GSI: 2855 err = mlx5_ib_create_gsi(pd, qp, params->attr); 2856 break; 2857 default: 2858 if (params->udata) 2859 err = create_user_qp(dev, pd, qp, params); 2860 else 2861 err = create_kernel_qp(dev, pd, qp, params); 2862 } 2863 2864 out: 2865 if (err) { 2866 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 2867 return err; 2868 } 2869 2870 if (is_qp0(qp->type)) 2871 qp->ibqp.qp_num = 0; 2872 else if (is_qp1(qp->type)) 2873 qp->ibqp.qp_num = 1; 2874 else 2875 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2876 2877 mlx5_ib_dbg(dev, 2878 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 2879 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2880 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 2881 -1, 2882 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 2883 -1, 2884 params->resp.ece_options); 2885 2886 return 0; 2887 } 2888 2889 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2890 struct ib_qp_init_attr *attr) 2891 { 2892 int ret = 0; 2893 2894 switch (qp->type) { 2895 case MLX5_IB_QPT_DCT: 2896 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 2897 break; 2898 case MLX5_IB_QPT_DCI: 2899 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 2900 -EINVAL : 2901 0; 2902 break; 2903 case IB_QPT_RAW_PACKET: 2904 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 2905 break; 2906 default: 2907 break; 2908 } 2909 2910 if (ret) 2911 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 2912 2913 return ret; 2914 } 2915 2916 static int get_qp_uidx(struct mlx5_ib_qp *qp, 2917 struct mlx5_create_qp_params *params) 2918 { 2919 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2920 struct ib_udata *udata = params->udata; 2921 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2922 udata, struct mlx5_ib_ucontext, ibucontext); 2923 2924 if (params->is_rss_raw) 2925 return 0; 2926 2927 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 2928 } 2929 2930 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2931 { 2932 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2933 2934 if (mqp->state == IB_QPS_RTR) { 2935 int err; 2936 2937 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 2938 if (err) { 2939 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2940 return err; 2941 } 2942 } 2943 2944 kfree(mqp->dct.in); 2945 kfree(mqp); 2946 return 0; 2947 } 2948 2949 static int check_ucmd_data(struct mlx5_ib_dev *dev, 2950 struct mlx5_create_qp_params *params) 2951 { 2952 struct ib_udata *udata = params->udata; 2953 size_t size, last; 2954 int ret; 2955 2956 if (params->is_rss_raw) 2957 /* 2958 * These QPs don't have "reserved" field in their 2959 * create_qp input struct, so their data is always valid. 2960 */ 2961 last = sizeof(struct mlx5_ib_create_qp_rss); 2962 else 2963 last = offsetof(struct mlx5_ib_create_qp, reserved); 2964 2965 if (udata->inlen <= last) 2966 return 0; 2967 2968 /* 2969 * User provides different create_qp structures based on the 2970 * flow and we need to know if he cleared memory after our 2971 * struct create_qp ends. 2972 */ 2973 size = udata->inlen - last; 2974 ret = ib_is_udata_cleared(params->udata, last, size); 2975 if (!ret) 2976 mlx5_ib_dbg( 2977 dev, 2978 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 2979 udata->inlen, params->ucmd_size, last, size); 2980 return ret ? 0 : -EINVAL; 2981 } 2982 2983 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr, 2984 struct ib_udata *udata) 2985 { 2986 struct mlx5_create_qp_params params = {}; 2987 struct mlx5_ib_dev *dev; 2988 struct mlx5_ib_qp *qp; 2989 enum ib_qp_type type; 2990 int err; 2991 2992 dev = pd ? to_mdev(pd->device) : 2993 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device); 2994 2995 err = check_qp_type(dev, attr, &type); 2996 if (err) 2997 return ERR_PTR(err); 2998 2999 err = check_valid_flow(dev, pd, attr, udata); 3000 if (err) 3001 return ERR_PTR(err); 3002 3003 params.udata = udata; 3004 params.uidx = MLX5_IB_DEFAULT_UIDX; 3005 params.attr = attr; 3006 params.is_rss_raw = !!attr->rwq_ind_tbl; 3007 3008 if (udata) { 3009 err = process_udata_size(dev, ¶ms); 3010 if (err) 3011 return ERR_PTR(err); 3012 3013 err = check_ucmd_data(dev, ¶ms); 3014 if (err) 3015 return ERR_PTR(err); 3016 3017 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3018 if (!params.ucmd) 3019 return ERR_PTR(-ENOMEM); 3020 3021 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3022 if (err) 3023 goto free_ucmd; 3024 } 3025 3026 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 3027 if (!qp) { 3028 err = -ENOMEM; 3029 goto free_ucmd; 3030 } 3031 3032 mutex_init(&qp->mutex); 3033 qp->type = type; 3034 if (udata) { 3035 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3036 if (err) 3037 goto free_qp; 3038 3039 err = get_qp_uidx(qp, ¶ms); 3040 if (err) 3041 goto free_qp; 3042 } 3043 err = process_create_flags(dev, qp, attr); 3044 if (err) 3045 goto free_qp; 3046 3047 err = check_qp_attr(dev, qp, attr); 3048 if (err) 3049 goto free_qp; 3050 3051 err = create_qp(dev, pd, qp, ¶ms); 3052 if (err) 3053 goto free_qp; 3054 3055 kfree(params.ucmd); 3056 params.ucmd = NULL; 3057 3058 if (udata) 3059 /* 3060 * It is safe to copy response for all user create QP flows, 3061 * including MLX5_IB_QPT_DCT, which doesn't need it. 3062 * In that case, resp will be filled with zeros. 3063 */ 3064 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3065 if (err) 3066 goto destroy_qp; 3067 3068 return &qp->ibqp; 3069 3070 destroy_qp: 3071 switch (qp->type) { 3072 case MLX5_IB_QPT_DCT: 3073 mlx5_ib_destroy_dct(qp); 3074 break; 3075 case IB_QPT_GSI: 3076 mlx5_ib_destroy_gsi(qp); 3077 break; 3078 default: 3079 /* 3080 * These lines below are temp solution till QP allocation 3081 * will be moved to be under IB/core responsiblity. 3082 */ 3083 qp->ibqp.send_cq = attr->send_cq; 3084 qp->ibqp.recv_cq = attr->recv_cq; 3085 qp->ibqp.pd = pd; 3086 destroy_qp_common(dev, qp, udata); 3087 } 3088 3089 qp = NULL; 3090 free_qp: 3091 kfree(qp); 3092 free_ucmd: 3093 kfree(params.ucmd); 3094 return ERR_PTR(err); 3095 } 3096 3097 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3098 { 3099 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3100 struct mlx5_ib_qp *mqp = to_mqp(qp); 3101 3102 if (mqp->type == IB_QPT_GSI) 3103 return mlx5_ib_destroy_gsi(mqp); 3104 3105 if (mqp->type == MLX5_IB_QPT_DCT) 3106 return mlx5_ib_destroy_dct(mqp); 3107 3108 destroy_qp_common(dev, mqp, udata); 3109 3110 kfree(mqp); 3111 3112 return 0; 3113 } 3114 3115 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3116 const struct ib_qp_attr *attr, int attr_mask, 3117 void *qpc) 3118 { 3119 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3120 u8 dest_rd_atomic; 3121 u32 access_flags; 3122 3123 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3124 dest_rd_atomic = attr->max_dest_rd_atomic; 3125 else 3126 dest_rd_atomic = qp->trans_qp.resp_depth; 3127 3128 if (attr_mask & IB_QP_ACCESS_FLAGS) 3129 access_flags = attr->qp_access_flags; 3130 else 3131 access_flags = qp->trans_qp.atomic_rd_en; 3132 3133 if (!dest_rd_atomic) 3134 access_flags &= IB_ACCESS_REMOTE_WRITE; 3135 3136 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3137 3138 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3139 int atomic_mode; 3140 3141 atomic_mode = get_atomic_mode(dev, qp->type); 3142 if (atomic_mode < 0) 3143 return -EOPNOTSUPP; 3144 3145 MLX5_SET(qpc, qpc, rae, 1); 3146 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3147 } 3148 3149 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3150 return 0; 3151 } 3152 3153 enum { 3154 MLX5_PATH_FLAG_FL = 1 << 0, 3155 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3156 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3157 }; 3158 3159 static int mlx5_to_ib_rate_map(u8 rate) 3160 { 3161 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3162 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3163 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3164 IB_RATE_400_GBPS }; 3165 3166 if (rate < ARRAY_SIZE(rates)) 3167 return rates[rate]; 3168 3169 return rate - MLX5_STAT_RATE_OFFSET; 3170 } 3171 3172 static int ib_to_mlx5_rate_map(u8 rate) 3173 { 3174 switch (rate) { 3175 case IB_RATE_PORT_CURRENT: 3176 return 0; 3177 case IB_RATE_56_GBPS: 3178 return 1; 3179 case IB_RATE_25_GBPS: 3180 return 2; 3181 case IB_RATE_100_GBPS: 3182 return 3; 3183 case IB_RATE_200_GBPS: 3184 return 4; 3185 case IB_RATE_50_GBPS: 3186 return 5; 3187 case IB_RATE_400_GBPS: 3188 return 6; 3189 default: 3190 return rate + MLX5_STAT_RATE_OFFSET; 3191 } 3192 3193 return 0; 3194 } 3195 3196 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3197 { 3198 u32 stat_rate_support; 3199 3200 if (rate == IB_RATE_PORT_CURRENT) 3201 return 0; 3202 3203 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3204 return -EINVAL; 3205 3206 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3207 while (rate != IB_RATE_PORT_CURRENT && 3208 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3209 --rate; 3210 3211 return ib_to_mlx5_rate_map(rate); 3212 } 3213 3214 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3215 struct mlx5_ib_sq *sq, u8 sl, 3216 struct ib_pd *pd) 3217 { 3218 void *in; 3219 void *tisc; 3220 int inlen; 3221 int err; 3222 3223 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3224 in = kvzalloc(inlen, GFP_KERNEL); 3225 if (!in) 3226 return -ENOMEM; 3227 3228 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3229 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3230 3231 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3232 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3233 3234 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3235 3236 kvfree(in); 3237 3238 return err; 3239 } 3240 3241 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3242 struct mlx5_ib_sq *sq, u8 tx_affinity, 3243 struct ib_pd *pd) 3244 { 3245 void *in; 3246 void *tisc; 3247 int inlen; 3248 int err; 3249 3250 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3251 in = kvzalloc(inlen, GFP_KERNEL); 3252 if (!in) 3253 return -ENOMEM; 3254 3255 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3256 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3257 3258 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3259 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3260 3261 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3262 3263 kvfree(in); 3264 3265 return err; 3266 } 3267 3268 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3269 u32 lqpn, u32 rqpn) 3270 3271 { 3272 u32 fl = ah->grh.flow_label; 3273 3274 if (!fl) 3275 fl = rdma_calc_flow_label(lqpn, rqpn); 3276 3277 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3278 } 3279 3280 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3281 const struct rdma_ah_attr *ah, void *path, u8 port, 3282 int attr_mask, u32 path_flags, 3283 const struct ib_qp_attr *attr, bool alt) 3284 { 3285 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3286 int err; 3287 enum ib_gid_type gid_type; 3288 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3289 u8 sl = rdma_ah_get_sl(ah); 3290 3291 if (attr_mask & IB_QP_PKEY_INDEX) 3292 MLX5_SET(ads, path, pkey_index, 3293 alt ? attr->alt_pkey_index : attr->pkey_index); 3294 3295 if (ah_flags & IB_AH_GRH) { 3296 const struct ib_port_immutable *immutable; 3297 3298 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3299 if (grh->sgid_index >= immutable->gid_tbl_len) { 3300 pr_err("sgid_index (%u) too large. max is %d\n", 3301 grh->sgid_index, 3302 immutable->gid_tbl_len); 3303 return -EINVAL; 3304 } 3305 } 3306 3307 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3308 if (!(ah_flags & IB_AH_GRH)) 3309 return -EINVAL; 3310 3311 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3312 ah->roce.dmac); 3313 if ((qp->type == IB_QPT_RC || 3314 qp->type == IB_QPT_UC || 3315 qp->type == IB_QPT_XRC_INI || 3316 qp->type == IB_QPT_XRC_TGT) && 3317 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3318 (attr_mask & IB_QP_DEST_QPN)) 3319 mlx5_set_path_udp_sport(path, ah, 3320 qp->ibqp.qp_num, 3321 attr->dest_qp_num); 3322 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3323 gid_type = ah->grh.sgid_attr->gid_type; 3324 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3325 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3326 } else { 3327 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3328 MLX5_SET(ads, path, free_ar, 3329 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3330 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3331 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3332 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3333 MLX5_SET(ads, path, sl, sl); 3334 } 3335 3336 if (ah_flags & IB_AH_GRH) { 3337 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3338 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3339 MLX5_SET(ads, path, tclass, grh->traffic_class); 3340 MLX5_SET(ads, path, flow_label, grh->flow_label); 3341 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3342 sizeof(grh->dgid.raw)); 3343 } 3344 3345 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3346 if (err < 0) 3347 return err; 3348 MLX5_SET(ads, path, stat_rate, err); 3349 MLX5_SET(ads, path, vhca_port_num, port); 3350 3351 if (attr_mask & IB_QP_TIMEOUT) 3352 MLX5_SET(ads, path, ack_timeout, 3353 alt ? attr->alt_timeout : attr->timeout); 3354 3355 if ((qp->type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3356 return modify_raw_packet_eth_prio(dev->mdev, 3357 &qp->raw_packet_qp.sq, 3358 sl & 0xf, qp->ibqp.pd); 3359 3360 return 0; 3361 } 3362 3363 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3364 [MLX5_QP_STATE_INIT] = { 3365 [MLX5_QP_STATE_INIT] = { 3366 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3367 MLX5_QP_OPTPAR_RAE | 3368 MLX5_QP_OPTPAR_RWE | 3369 MLX5_QP_OPTPAR_PKEY_INDEX | 3370 MLX5_QP_OPTPAR_PRI_PORT | 3371 MLX5_QP_OPTPAR_LAG_TX_AFF, 3372 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3373 MLX5_QP_OPTPAR_PKEY_INDEX | 3374 MLX5_QP_OPTPAR_PRI_PORT | 3375 MLX5_QP_OPTPAR_LAG_TX_AFF, 3376 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3377 MLX5_QP_OPTPAR_Q_KEY | 3378 MLX5_QP_OPTPAR_PRI_PORT, 3379 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3380 MLX5_QP_OPTPAR_RAE | 3381 MLX5_QP_OPTPAR_RWE | 3382 MLX5_QP_OPTPAR_PKEY_INDEX | 3383 MLX5_QP_OPTPAR_PRI_PORT | 3384 MLX5_QP_OPTPAR_LAG_TX_AFF, 3385 }, 3386 [MLX5_QP_STATE_RTR] = { 3387 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3388 MLX5_QP_OPTPAR_RRE | 3389 MLX5_QP_OPTPAR_RAE | 3390 MLX5_QP_OPTPAR_RWE | 3391 MLX5_QP_OPTPAR_PKEY_INDEX | 3392 MLX5_QP_OPTPAR_LAG_TX_AFF, 3393 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3394 MLX5_QP_OPTPAR_RWE | 3395 MLX5_QP_OPTPAR_PKEY_INDEX | 3396 MLX5_QP_OPTPAR_LAG_TX_AFF, 3397 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3398 MLX5_QP_OPTPAR_Q_KEY, 3399 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3400 MLX5_QP_OPTPAR_Q_KEY, 3401 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3402 MLX5_QP_OPTPAR_RRE | 3403 MLX5_QP_OPTPAR_RAE | 3404 MLX5_QP_OPTPAR_RWE | 3405 MLX5_QP_OPTPAR_PKEY_INDEX | 3406 MLX5_QP_OPTPAR_LAG_TX_AFF, 3407 }, 3408 }, 3409 [MLX5_QP_STATE_RTR] = { 3410 [MLX5_QP_STATE_RTS] = { 3411 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3412 MLX5_QP_OPTPAR_RRE | 3413 MLX5_QP_OPTPAR_RAE | 3414 MLX5_QP_OPTPAR_RWE | 3415 MLX5_QP_OPTPAR_PM_STATE | 3416 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3417 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3418 MLX5_QP_OPTPAR_RWE | 3419 MLX5_QP_OPTPAR_PM_STATE, 3420 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3421 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3422 MLX5_QP_OPTPAR_RRE | 3423 MLX5_QP_OPTPAR_RAE | 3424 MLX5_QP_OPTPAR_RWE | 3425 MLX5_QP_OPTPAR_PM_STATE | 3426 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3427 }, 3428 }, 3429 [MLX5_QP_STATE_RTS] = { 3430 [MLX5_QP_STATE_RTS] = { 3431 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3432 MLX5_QP_OPTPAR_RAE | 3433 MLX5_QP_OPTPAR_RWE | 3434 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3435 MLX5_QP_OPTPAR_PM_STATE | 3436 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3437 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3438 MLX5_QP_OPTPAR_PM_STATE | 3439 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3440 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3441 MLX5_QP_OPTPAR_SRQN | 3442 MLX5_QP_OPTPAR_CQN_RCV, 3443 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3444 MLX5_QP_OPTPAR_RAE | 3445 MLX5_QP_OPTPAR_RWE | 3446 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3447 MLX5_QP_OPTPAR_PM_STATE | 3448 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3449 }, 3450 }, 3451 [MLX5_QP_STATE_SQER] = { 3452 [MLX5_QP_STATE_RTS] = { 3453 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3454 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3455 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3456 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3457 MLX5_QP_OPTPAR_RWE | 3458 MLX5_QP_OPTPAR_RAE | 3459 MLX5_QP_OPTPAR_RRE, 3460 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3461 MLX5_QP_OPTPAR_RWE | 3462 MLX5_QP_OPTPAR_RAE | 3463 MLX5_QP_OPTPAR_RRE, 3464 }, 3465 }, 3466 [MLX5_QP_STATE_SQD] = { 3467 [MLX5_QP_STATE_RTS] = { 3468 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3469 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3470 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3471 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3472 MLX5_QP_OPTPAR_RWE | 3473 MLX5_QP_OPTPAR_RAE | 3474 MLX5_QP_OPTPAR_RRE, 3475 }, 3476 }, 3477 }; 3478 3479 static int ib_nr_to_mlx5_nr(int ib_mask) 3480 { 3481 switch (ib_mask) { 3482 case IB_QP_STATE: 3483 return 0; 3484 case IB_QP_CUR_STATE: 3485 return 0; 3486 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3487 return 0; 3488 case IB_QP_ACCESS_FLAGS: 3489 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3490 MLX5_QP_OPTPAR_RAE; 3491 case IB_QP_PKEY_INDEX: 3492 return MLX5_QP_OPTPAR_PKEY_INDEX; 3493 case IB_QP_PORT: 3494 return MLX5_QP_OPTPAR_PRI_PORT; 3495 case IB_QP_QKEY: 3496 return MLX5_QP_OPTPAR_Q_KEY; 3497 case IB_QP_AV: 3498 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3499 MLX5_QP_OPTPAR_PRI_PORT; 3500 case IB_QP_PATH_MTU: 3501 return 0; 3502 case IB_QP_TIMEOUT: 3503 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3504 case IB_QP_RETRY_CNT: 3505 return MLX5_QP_OPTPAR_RETRY_COUNT; 3506 case IB_QP_RNR_RETRY: 3507 return MLX5_QP_OPTPAR_RNR_RETRY; 3508 case IB_QP_RQ_PSN: 3509 return 0; 3510 case IB_QP_MAX_QP_RD_ATOMIC: 3511 return MLX5_QP_OPTPAR_SRA_MAX; 3512 case IB_QP_ALT_PATH: 3513 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3514 case IB_QP_MIN_RNR_TIMER: 3515 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3516 case IB_QP_SQ_PSN: 3517 return 0; 3518 case IB_QP_MAX_DEST_RD_ATOMIC: 3519 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3520 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3521 case IB_QP_PATH_MIG_STATE: 3522 return MLX5_QP_OPTPAR_PM_STATE; 3523 case IB_QP_CAP: 3524 return 0; 3525 case IB_QP_DEST_QPN: 3526 return 0; 3527 } 3528 return 0; 3529 } 3530 3531 static int ib_mask_to_mlx5_opt(int ib_mask) 3532 { 3533 int result = 0; 3534 int i; 3535 3536 for (i = 0; i < 8 * sizeof(int); i++) { 3537 if ((1 << i) & ib_mask) 3538 result |= ib_nr_to_mlx5_nr(1 << i); 3539 } 3540 3541 return result; 3542 } 3543 3544 static int modify_raw_packet_qp_rq( 3545 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3546 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3547 { 3548 void *in; 3549 void *rqc; 3550 int inlen; 3551 int err; 3552 3553 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3554 in = kvzalloc(inlen, GFP_KERNEL); 3555 if (!in) 3556 return -ENOMEM; 3557 3558 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3559 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3560 3561 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3562 MLX5_SET(rqc, rqc, state, new_state); 3563 3564 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3565 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3566 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3567 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3568 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3569 } else 3570 dev_info_once( 3571 &dev->ib_dev.dev, 3572 "RAW PACKET QP counters are not supported on current FW\n"); 3573 } 3574 3575 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3576 if (err) 3577 goto out; 3578 3579 rq->state = new_state; 3580 3581 out: 3582 kvfree(in); 3583 return err; 3584 } 3585 3586 static int modify_raw_packet_qp_sq( 3587 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3588 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3589 { 3590 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3591 struct mlx5_rate_limit old_rl = ibqp->rl; 3592 struct mlx5_rate_limit new_rl = old_rl; 3593 bool new_rate_added = false; 3594 u16 rl_index = 0; 3595 void *in; 3596 void *sqc; 3597 int inlen; 3598 int err; 3599 3600 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3601 in = kvzalloc(inlen, GFP_KERNEL); 3602 if (!in) 3603 return -ENOMEM; 3604 3605 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3606 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3607 3608 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3609 MLX5_SET(sqc, sqc, state, new_state); 3610 3611 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3612 if (new_state != MLX5_SQC_STATE_RDY) 3613 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3614 __func__); 3615 else 3616 new_rl = raw_qp_param->rl; 3617 } 3618 3619 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3620 if (new_rl.rate) { 3621 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3622 if (err) { 3623 pr_err("Failed configuring rate limit(err %d): \ 3624 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3625 err, new_rl.rate, new_rl.max_burst_sz, 3626 new_rl.typical_pkt_sz); 3627 3628 goto out; 3629 } 3630 new_rate_added = true; 3631 } 3632 3633 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3634 /* index 0 means no limit */ 3635 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3636 } 3637 3638 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3639 if (err) { 3640 /* Remove new rate from table if failed */ 3641 if (new_rate_added) 3642 mlx5_rl_remove_rate(dev, &new_rl); 3643 goto out; 3644 } 3645 3646 /* Only remove the old rate after new rate was set */ 3647 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3648 (new_state != MLX5_SQC_STATE_RDY)) { 3649 mlx5_rl_remove_rate(dev, &old_rl); 3650 if (new_state != MLX5_SQC_STATE_RDY) 3651 memset(&new_rl, 0, sizeof(new_rl)); 3652 } 3653 3654 ibqp->rl = new_rl; 3655 sq->state = new_state; 3656 3657 out: 3658 kvfree(in); 3659 return err; 3660 } 3661 3662 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3663 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3664 u8 tx_affinity) 3665 { 3666 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3667 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3668 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3669 int modify_rq = !!qp->rq.wqe_cnt; 3670 int modify_sq = !!qp->sq.wqe_cnt; 3671 int rq_state; 3672 int sq_state; 3673 int err; 3674 3675 switch (raw_qp_param->operation) { 3676 case MLX5_CMD_OP_RST2INIT_QP: 3677 rq_state = MLX5_RQC_STATE_RDY; 3678 sq_state = MLX5_SQC_STATE_RST; 3679 break; 3680 case MLX5_CMD_OP_2ERR_QP: 3681 rq_state = MLX5_RQC_STATE_ERR; 3682 sq_state = MLX5_SQC_STATE_ERR; 3683 break; 3684 case MLX5_CMD_OP_2RST_QP: 3685 rq_state = MLX5_RQC_STATE_RST; 3686 sq_state = MLX5_SQC_STATE_RST; 3687 break; 3688 case MLX5_CMD_OP_RTR2RTS_QP: 3689 case MLX5_CMD_OP_RTS2RTS_QP: 3690 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3691 return -EINVAL; 3692 3693 modify_rq = 0; 3694 sq_state = MLX5_SQC_STATE_RDY; 3695 break; 3696 case MLX5_CMD_OP_INIT2INIT_QP: 3697 case MLX5_CMD_OP_INIT2RTR_QP: 3698 if (raw_qp_param->set_mask) 3699 return -EINVAL; 3700 else 3701 return 0; 3702 default: 3703 WARN_ON(1); 3704 return -EINVAL; 3705 } 3706 3707 if (modify_rq) { 3708 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3709 qp->ibqp.pd); 3710 if (err) 3711 return err; 3712 } 3713 3714 if (modify_sq) { 3715 struct mlx5_flow_handle *flow_rule; 3716 3717 if (tx_affinity) { 3718 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3719 tx_affinity, 3720 qp->ibqp.pd); 3721 if (err) 3722 return err; 3723 } 3724 3725 flow_rule = create_flow_rule_vport_sq(dev, sq, 3726 raw_qp_param->port); 3727 if (IS_ERR(flow_rule)) 3728 return PTR_ERR(flow_rule); 3729 3730 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3731 raw_qp_param, qp->ibqp.pd); 3732 if (err) { 3733 if (flow_rule) 3734 mlx5_del_flow_rules(flow_rule); 3735 return err; 3736 } 3737 3738 if (flow_rule) { 3739 destroy_flow_rule_vport_sq(sq); 3740 sq->flow_rule = flow_rule; 3741 } 3742 3743 return err; 3744 } 3745 3746 return 0; 3747 } 3748 3749 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3750 struct ib_udata *udata) 3751 { 3752 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3753 udata, struct mlx5_ib_ucontext, ibucontext); 3754 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3755 atomic_t *tx_port_affinity; 3756 3757 if (ucontext) 3758 tx_port_affinity = &ucontext->tx_port_affinity; 3759 else 3760 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3761 3762 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3763 MLX5_MAX_PORTS + 1; 3764 } 3765 3766 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3767 { 3768 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3769 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3770 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3771 (qp->type == MLX5_IB_QPT_DCI)) 3772 return true; 3773 return false; 3774 } 3775 3776 static unsigned int get_tx_affinity(struct ib_qp *qp, 3777 const struct ib_qp_attr *attr, 3778 int attr_mask, u8 init, 3779 struct ib_udata *udata) 3780 { 3781 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3782 udata, struct mlx5_ib_ucontext, ibucontext); 3783 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3784 struct mlx5_ib_qp *mqp = to_mqp(qp); 3785 struct mlx5_ib_qp_base *qp_base; 3786 unsigned int tx_affinity; 3787 3788 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 3789 qp_supports_affinity(mqp))) 3790 return 0; 3791 3792 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3793 tx_affinity = mqp->gsi_lag_port; 3794 else if (init) 3795 tx_affinity = get_tx_affinity_rr(dev, udata); 3796 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 3797 tx_affinity = 3798 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 3799 else 3800 return 0; 3801 3802 qp_base = &mqp->trans_qp.base; 3803 if (ucontext) 3804 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3805 tx_affinity, qp_base->mqp.qpn, ucontext); 3806 else 3807 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3808 tx_affinity, qp_base->mqp.qpn); 3809 return tx_affinity; 3810 } 3811 3812 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3813 struct rdma_counter *counter) 3814 { 3815 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3816 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 3817 struct mlx5_ib_qp *mqp = to_mqp(qp); 3818 struct mlx5_ib_qp_base *base; 3819 u32 set_id; 3820 u32 *qpc; 3821 3822 if (counter) 3823 set_id = counter->id; 3824 else 3825 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3826 3827 base = &mqp->trans_qp.base; 3828 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 3829 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 3830 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 3831 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 3832 MLX5_QP_OPTPAR_COUNTER_SET_ID); 3833 3834 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 3835 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3836 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 3837 } 3838 3839 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3840 const struct ib_qp_attr *attr, int attr_mask, 3841 enum ib_qp_state cur_state, 3842 enum ib_qp_state new_state, 3843 const struct mlx5_ib_modify_qp *ucmd, 3844 struct mlx5_ib_modify_qp_resp *resp, 3845 struct ib_udata *udata) 3846 { 3847 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3848 [MLX5_QP_STATE_RST] = { 3849 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3850 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3851 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3852 }, 3853 [MLX5_QP_STATE_INIT] = { 3854 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3855 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3856 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3857 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3858 }, 3859 [MLX5_QP_STATE_RTR] = { 3860 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3861 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3862 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3863 }, 3864 [MLX5_QP_STATE_RTS] = { 3865 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3866 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3867 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3868 }, 3869 [MLX5_QP_STATE_SQD] = { 3870 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3871 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3872 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD_RTS_QP, 3873 }, 3874 [MLX5_QP_STATE_SQER] = { 3875 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3876 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3877 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3878 }, 3879 [MLX5_QP_STATE_ERR] = { 3880 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3881 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3882 } 3883 }; 3884 3885 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3886 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3887 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3888 struct mlx5_ib_cq *send_cq, *recv_cq; 3889 struct mlx5_ib_pd *pd; 3890 enum mlx5_qp_state mlx5_cur, mlx5_new; 3891 void *qpc, *pri_path, *alt_path; 3892 enum mlx5_qp_optpar optpar = 0; 3893 u32 set_id = 0; 3894 int mlx5_st; 3895 int err; 3896 u16 op; 3897 u8 tx_affinity = 0; 3898 3899 mlx5_st = to_mlx5_st(qp->type); 3900 if (mlx5_st < 0) 3901 return -EINVAL; 3902 3903 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 3904 if (!qpc) 3905 return -ENOMEM; 3906 3907 pd = to_mpd(qp->ibqp.pd); 3908 MLX5_SET(qpc, qpc, st, mlx5_st); 3909 3910 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3911 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3912 } else { 3913 switch (attr->path_mig_state) { 3914 case IB_MIG_MIGRATED: 3915 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3916 break; 3917 case IB_MIG_REARM: 3918 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 3919 break; 3920 case IB_MIG_ARMED: 3921 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 3922 break; 3923 } 3924 } 3925 3926 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 3927 cur_state == IB_QPS_RESET && 3928 new_state == IB_QPS_INIT, udata); 3929 3930 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 3931 if (tx_affinity && new_state == IB_QPS_RTR && 3932 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 3933 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 3934 3935 if (is_sqp(qp->type)) { 3936 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 3937 MLX5_SET(qpc, qpc, log_msg_max, 8); 3938 } else if ((qp->type == IB_QPT_UD && 3939 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 3940 qp->type == MLX5_IB_QPT_REG_UMR) { 3941 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 3942 MLX5_SET(qpc, qpc, log_msg_max, 12); 3943 } else if (attr_mask & IB_QP_PATH_MTU) { 3944 if (attr->path_mtu < IB_MTU_256 || 3945 attr->path_mtu > IB_MTU_4096) { 3946 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3947 err = -EINVAL; 3948 goto out; 3949 } 3950 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 3951 MLX5_SET(qpc, qpc, log_msg_max, 3952 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 3953 } 3954 3955 if (attr_mask & IB_QP_DEST_QPN) 3956 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 3957 3958 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 3959 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 3960 3961 if (attr_mask & IB_QP_PKEY_INDEX) 3962 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 3963 3964 /* todo implement counter_index functionality */ 3965 3966 if (is_sqp(qp->type)) 3967 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 3968 3969 if (attr_mask & IB_QP_PORT) 3970 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 3971 3972 if (attr_mask & IB_QP_AV) { 3973 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 3974 attr_mask & IB_QP_PORT ? attr->port_num : 3975 qp->port, 3976 attr_mask, 0, attr, false); 3977 if (err) 3978 goto out; 3979 } 3980 3981 if (attr_mask & IB_QP_TIMEOUT) 3982 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 3983 3984 if (attr_mask & IB_QP_ALT_PATH) { 3985 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 3986 attr->alt_port_num, 3987 attr_mask | IB_QP_PKEY_INDEX | 3988 IB_QP_TIMEOUT, 3989 0, attr, true); 3990 if (err) 3991 goto out; 3992 } 3993 3994 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3995 &send_cq, &recv_cq); 3996 3997 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3998 if (send_cq) 3999 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 4000 if (recv_cq) 4001 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 4002 4003 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 4004 4005 if (attr_mask & IB_QP_RNR_RETRY) 4006 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 4007 4008 if (attr_mask & IB_QP_RETRY_CNT) 4009 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 4010 4011 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 4012 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 4013 4014 if (attr_mask & IB_QP_SQ_PSN) 4015 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 4016 4017 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 4018 MLX5_SET(qpc, qpc, log_rra_max, 4019 ilog2(attr->max_dest_rd_atomic)); 4020 4021 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4022 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4023 if (err) 4024 goto out; 4025 } 4026 4027 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4028 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4029 4030 if (attr_mask & IB_QP_RQ_PSN) 4031 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4032 4033 if (attr_mask & IB_QP_QKEY) 4034 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4035 4036 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4037 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4038 4039 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4040 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4041 qp->port) - 1; 4042 4043 /* Underlay port should be used - index 0 function per port */ 4044 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4045 port_num = 0; 4046 4047 if (ibqp->counter) 4048 set_id = ibqp->counter->id; 4049 else 4050 set_id = mlx5_ib_get_counters_id(dev, port_num); 4051 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4052 } 4053 4054 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4055 MLX5_SET(qpc, qpc, rlky, 1); 4056 4057 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4058 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4059 4060 mlx5_cur = to_mlx5_state(cur_state); 4061 mlx5_new = to_mlx5_state(new_state); 4062 4063 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4064 !optab[mlx5_cur][mlx5_new]) { 4065 err = -EINVAL; 4066 goto out; 4067 } 4068 4069 op = optab[mlx5_cur][mlx5_new]; 4070 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4071 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4072 4073 if (qp->type == IB_QPT_RAW_PACKET || 4074 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4075 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4076 4077 raw_qp_param.operation = op; 4078 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4079 raw_qp_param.rq_q_ctr_id = set_id; 4080 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4081 } 4082 4083 if (attr_mask & IB_QP_PORT) 4084 raw_qp_param.port = attr->port_num; 4085 4086 if (attr_mask & IB_QP_RATE_LIMIT) { 4087 raw_qp_param.rl.rate = attr->rate_limit; 4088 4089 if (ucmd->burst_info.max_burst_sz) { 4090 if (attr->rate_limit && 4091 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4092 raw_qp_param.rl.max_burst_sz = 4093 ucmd->burst_info.max_burst_sz; 4094 } else { 4095 err = -EINVAL; 4096 goto out; 4097 } 4098 } 4099 4100 if (ucmd->burst_info.typical_pkt_sz) { 4101 if (attr->rate_limit && 4102 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4103 raw_qp_param.rl.typical_pkt_sz = 4104 ucmd->burst_info.typical_pkt_sz; 4105 } else { 4106 err = -EINVAL; 4107 goto out; 4108 } 4109 } 4110 4111 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4112 } 4113 4114 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4115 } else { 4116 if (udata) { 4117 /* For the kernel flows, the resp will stay zero */ 4118 resp->ece_options = 4119 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4120 ucmd->ece_options : 0; 4121 resp->response_length = sizeof(*resp); 4122 } 4123 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4124 &resp->ece_options); 4125 } 4126 4127 if (err) 4128 goto out; 4129 4130 qp->state = new_state; 4131 4132 if (attr_mask & IB_QP_ACCESS_FLAGS) 4133 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4134 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4135 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4136 if (attr_mask & IB_QP_PORT) 4137 qp->port = attr->port_num; 4138 if (attr_mask & IB_QP_ALT_PATH) 4139 qp->trans_qp.alt_port = attr->alt_port_num; 4140 4141 /* 4142 * If we moved a kernel QP to RESET, clean up all old CQ 4143 * entries and reinitialize the QP. 4144 */ 4145 if (new_state == IB_QPS_RESET && 4146 !ibqp->uobject && qp->type != IB_QPT_XRC_TGT) { 4147 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4148 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4149 if (send_cq != recv_cq) 4150 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4151 4152 qp->rq.head = 0; 4153 qp->rq.tail = 0; 4154 qp->sq.head = 0; 4155 qp->sq.tail = 0; 4156 qp->sq.cur_post = 0; 4157 if (qp->sq.wqe_cnt) 4158 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4159 qp->sq.last_poll = 0; 4160 qp->db.db[MLX5_RCV_DBR] = 0; 4161 qp->db.db[MLX5_SND_DBR] = 0; 4162 } 4163 4164 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4165 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4166 if (!err) 4167 qp->counter_pending = 0; 4168 } 4169 4170 out: 4171 kfree(qpc); 4172 return err; 4173 } 4174 4175 static inline bool is_valid_mask(int mask, int req, int opt) 4176 { 4177 if ((mask & req) != req) 4178 return false; 4179 4180 if (mask & ~(req | opt)) 4181 return false; 4182 4183 return true; 4184 } 4185 4186 /* check valid transition for driver QP types 4187 * for now the only QP type that this function supports is DCI 4188 */ 4189 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4190 enum ib_qp_attr_mask attr_mask) 4191 { 4192 int req = IB_QP_STATE; 4193 int opt = 0; 4194 4195 if (new_state == IB_QPS_RESET) { 4196 return is_valid_mask(attr_mask, req, opt); 4197 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4198 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4199 return is_valid_mask(attr_mask, req, opt); 4200 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4201 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4202 return is_valid_mask(attr_mask, req, opt); 4203 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4204 req |= IB_QP_PATH_MTU; 4205 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4206 return is_valid_mask(attr_mask, req, opt); 4207 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4208 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4209 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4210 opt = IB_QP_MIN_RNR_TIMER; 4211 return is_valid_mask(attr_mask, req, opt); 4212 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4213 opt = IB_QP_MIN_RNR_TIMER; 4214 return is_valid_mask(attr_mask, req, opt); 4215 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4216 return is_valid_mask(attr_mask, req, opt); 4217 } 4218 return false; 4219 } 4220 4221 /* mlx5_ib_modify_dct: modify a DCT QP 4222 * valid transitions are: 4223 * RESET to INIT: must set access_flags, pkey_index and port 4224 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4225 * mtu, gid_index and hop_limit 4226 * Other transitions and attributes are illegal 4227 */ 4228 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4229 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4230 struct ib_udata *udata) 4231 { 4232 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4233 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4234 enum ib_qp_state cur_state, new_state; 4235 int required = IB_QP_STATE; 4236 void *dctc; 4237 int err; 4238 4239 if (!(attr_mask & IB_QP_STATE)) 4240 return -EINVAL; 4241 4242 cur_state = qp->state; 4243 new_state = attr->qp_state; 4244 4245 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4246 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4247 /* 4248 * DCT doesn't initialize QP till modify command is executed, 4249 * so we need to overwrite previously set ECE field if user 4250 * provided any value except zero, which means not set/not 4251 * valid. 4252 */ 4253 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4254 4255 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4256 u16 set_id; 4257 4258 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4259 if (!is_valid_mask(attr_mask, required, 0)) 4260 return -EINVAL; 4261 4262 if (attr->port_num == 0 || 4263 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4264 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4265 attr->port_num, dev->num_ports); 4266 return -EINVAL; 4267 } 4268 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4269 MLX5_SET(dctc, dctc, rre, 1); 4270 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4271 MLX5_SET(dctc, dctc, rwe, 1); 4272 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4273 int atomic_mode; 4274 4275 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4276 if (atomic_mode < 0) 4277 return -EOPNOTSUPP; 4278 4279 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4280 MLX5_SET(dctc, dctc, rae, 1); 4281 } 4282 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4283 if (mlx5_lag_is_active(dev->mdev)) 4284 MLX5_SET(dctc, dctc, port, 4285 get_tx_affinity_rr(dev, udata)); 4286 else 4287 MLX5_SET(dctc, dctc, port, attr->port_num); 4288 4289 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4290 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4291 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4292 struct mlx5_ib_modify_qp_resp resp = {}; 4293 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4294 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4295 4296 if (udata->outlen < min_resp_len) 4297 return -EINVAL; 4298 /* 4299 * If we don't have enough space for the ECE options, 4300 * simply indicate it with resp.response_length. 4301 */ 4302 resp.response_length = (udata->outlen < sizeof(resp)) ? 4303 min_resp_len : 4304 sizeof(resp); 4305 4306 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4307 if (!is_valid_mask(attr_mask, required, 0)) 4308 return -EINVAL; 4309 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4310 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4311 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4312 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4313 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4314 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4315 4316 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4317 MLX5_ST_SZ_BYTES(create_dct_in), out, 4318 sizeof(out)); 4319 if (err) 4320 return err; 4321 resp.dctn = qp->dct.mdct.mqp.qpn; 4322 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4323 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4324 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4325 if (err) { 4326 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4327 return err; 4328 } 4329 } else { 4330 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4331 return -EINVAL; 4332 } 4333 4334 qp->state = new_state; 4335 return 0; 4336 } 4337 4338 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4339 struct mlx5_ib_qp *qp) 4340 { 4341 if (dev->profile != &raw_eth_profile) 4342 return true; 4343 4344 if (qp->type == IB_QPT_RAW_PACKET || qp->type == MLX5_IB_QPT_REG_UMR) 4345 return true; 4346 4347 /* Internal QP used for wc testing, with NOPs in wq */ 4348 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 4349 return true; 4350 4351 return false; 4352 } 4353 4354 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4355 int attr_mask, struct ib_udata *udata) 4356 { 4357 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4358 struct mlx5_ib_modify_qp_resp resp = {}; 4359 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4360 struct mlx5_ib_modify_qp ucmd = {}; 4361 enum ib_qp_type qp_type; 4362 enum ib_qp_state cur_state, new_state; 4363 int err = -EINVAL; 4364 4365 if (!mlx5_ib_modify_qp_allowed(dev, qp)) 4366 return -EOPNOTSUPP; 4367 4368 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4369 return -EOPNOTSUPP; 4370 4371 if (ibqp->rwq_ind_tbl) 4372 return -ENOSYS; 4373 4374 if (udata && udata->inlen) { 4375 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4376 return -EINVAL; 4377 4378 if (udata->inlen > sizeof(ucmd) && 4379 !ib_is_udata_cleared(udata, sizeof(ucmd), 4380 udata->inlen - sizeof(ucmd))) 4381 return -EOPNOTSUPP; 4382 4383 if (ib_copy_from_udata(&ucmd, udata, 4384 min(udata->inlen, sizeof(ucmd)))) 4385 return -EFAULT; 4386 4387 if (ucmd.comp_mask || 4388 memchr_inv(&ucmd.burst_info.reserved, 0, 4389 sizeof(ucmd.burst_info.reserved))) 4390 return -EOPNOTSUPP; 4391 4392 } 4393 4394 if (qp->type == IB_QPT_GSI) 4395 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4396 4397 qp_type = (qp->type == MLX5_IB_QPT_HW_GSI) ? IB_QPT_GSI : qp->type; 4398 4399 if (qp_type == MLX5_IB_QPT_DCT) 4400 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4401 4402 mutex_lock(&qp->mutex); 4403 4404 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4405 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4406 4407 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4408 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4409 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4410 attr_mask); 4411 goto out; 4412 } 4413 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4414 qp_type != MLX5_IB_QPT_DCI && 4415 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4416 attr_mask)) { 4417 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4418 cur_state, new_state, qp->type, attr_mask); 4419 goto out; 4420 } else if (qp_type == MLX5_IB_QPT_DCI && 4421 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4422 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4423 cur_state, new_state, qp_type, attr_mask); 4424 goto out; 4425 } 4426 4427 if ((attr_mask & IB_QP_PORT) && 4428 (attr->port_num == 0 || 4429 attr->port_num > dev->num_ports)) { 4430 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4431 attr->port_num, dev->num_ports); 4432 goto out; 4433 } 4434 4435 if ((attr_mask & IB_QP_PKEY_INDEX) && 4436 attr->pkey_index >= dev->pkey_table_len) { 4437 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4438 goto out; 4439 } 4440 4441 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4442 attr->max_rd_atomic > 4443 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4444 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4445 attr->max_rd_atomic); 4446 goto out; 4447 } 4448 4449 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4450 attr->max_dest_rd_atomic > 4451 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4452 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4453 attr->max_dest_rd_atomic); 4454 goto out; 4455 } 4456 4457 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4458 err = 0; 4459 goto out; 4460 } 4461 4462 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4463 new_state, &ucmd, &resp, udata); 4464 4465 /* resp.response_length is set in ECE supported flows only */ 4466 if (!err && resp.response_length && 4467 udata->outlen >= resp.response_length) 4468 /* Return -EFAULT to the user and expect him to destroy QP. */ 4469 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4470 4471 out: 4472 mutex_unlock(&qp->mutex); 4473 return err; 4474 } 4475 4476 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4477 { 4478 switch (mlx5_state) { 4479 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4480 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4481 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4482 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4483 case MLX5_QP_STATE_SQ_DRAINING: 4484 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4485 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4486 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4487 default: return -1; 4488 } 4489 } 4490 4491 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4492 { 4493 switch (mlx5_mig_state) { 4494 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4495 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4496 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4497 default: return -1; 4498 } 4499 } 4500 4501 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4502 struct rdma_ah_attr *ah_attr, void *path) 4503 { 4504 int port = MLX5_GET(ads, path, vhca_port_num); 4505 int static_rate; 4506 4507 memset(ah_attr, 0, sizeof(*ah_attr)); 4508 4509 if (!port || port > ibdev->num_ports) 4510 return; 4511 4512 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4513 4514 rdma_ah_set_port_num(ah_attr, port); 4515 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4516 4517 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4518 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4519 4520 static_rate = MLX5_GET(ads, path, stat_rate); 4521 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4522 if (MLX5_GET(ads, path, grh) || 4523 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4524 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4525 MLX5_GET(ads, path, src_addr_index), 4526 MLX5_GET(ads, path, hop_limit), 4527 MLX5_GET(ads, path, tclass)); 4528 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4529 } 4530 } 4531 4532 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4533 struct mlx5_ib_sq *sq, 4534 u8 *sq_state) 4535 { 4536 int err; 4537 4538 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4539 if (err) 4540 goto out; 4541 sq->state = *sq_state; 4542 4543 out: 4544 return err; 4545 } 4546 4547 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4548 struct mlx5_ib_rq *rq, 4549 u8 *rq_state) 4550 { 4551 void *out; 4552 void *rqc; 4553 int inlen; 4554 int err; 4555 4556 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4557 out = kvzalloc(inlen, GFP_KERNEL); 4558 if (!out) 4559 return -ENOMEM; 4560 4561 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4562 if (err) 4563 goto out; 4564 4565 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4566 *rq_state = MLX5_GET(rqc, rqc, state); 4567 rq->state = *rq_state; 4568 4569 out: 4570 kvfree(out); 4571 return err; 4572 } 4573 4574 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4575 struct mlx5_ib_qp *qp, u8 *qp_state) 4576 { 4577 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4578 [MLX5_RQC_STATE_RST] = { 4579 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4580 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4581 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4582 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4583 }, 4584 [MLX5_RQC_STATE_RDY] = { 4585 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4586 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4587 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4588 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4589 }, 4590 [MLX5_RQC_STATE_ERR] = { 4591 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4592 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4593 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4594 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4595 }, 4596 [MLX5_RQ_STATE_NA] = { 4597 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4598 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4599 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4600 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4601 }, 4602 }; 4603 4604 *qp_state = sqrq_trans[rq_state][sq_state]; 4605 4606 if (*qp_state == MLX5_QP_STATE_BAD) { 4607 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4608 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4609 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4610 return -EINVAL; 4611 } 4612 4613 if (*qp_state == MLX5_QP_STATE) 4614 *qp_state = qp->state; 4615 4616 return 0; 4617 } 4618 4619 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4620 struct mlx5_ib_qp *qp, 4621 u8 *raw_packet_qp_state) 4622 { 4623 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4624 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4625 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4626 int err; 4627 u8 sq_state = MLX5_SQ_STATE_NA; 4628 u8 rq_state = MLX5_RQ_STATE_NA; 4629 4630 if (qp->sq.wqe_cnt) { 4631 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4632 if (err) 4633 return err; 4634 } 4635 4636 if (qp->rq.wqe_cnt) { 4637 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4638 if (err) 4639 return err; 4640 } 4641 4642 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4643 raw_packet_qp_state); 4644 } 4645 4646 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4647 struct ib_qp_attr *qp_attr) 4648 { 4649 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4650 void *qpc, *pri_path, *alt_path; 4651 u32 *outb; 4652 int err; 4653 4654 outb = kzalloc(outlen, GFP_KERNEL); 4655 if (!outb) 4656 return -ENOMEM; 4657 4658 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 4659 if (err) 4660 goto out; 4661 4662 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4663 4664 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4665 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4666 qp_attr->sq_draining = 1; 4667 4668 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4669 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4670 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4671 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4672 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4673 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4674 4675 if (MLX5_GET(qpc, qpc, rre)) 4676 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4677 if (MLX5_GET(qpc, qpc, rwe)) 4678 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4679 if (MLX5_GET(qpc, qpc, rae)) 4680 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4681 4682 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4683 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4684 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4685 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4686 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4687 4688 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4689 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4690 4691 if (qp->type == IB_QPT_RC || qp->type == IB_QPT_UC || 4692 qp->type == IB_QPT_XRC_INI || qp->type == IB_QPT_XRC_TGT) { 4693 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4694 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4695 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4696 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4697 } 4698 4699 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4700 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4701 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4702 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4703 4704 out: 4705 kfree(outb); 4706 return err; 4707 } 4708 4709 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4710 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4711 struct ib_qp_init_attr *qp_init_attr) 4712 { 4713 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4714 u32 *out; 4715 u32 access_flags = 0; 4716 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4717 void *dctc; 4718 int err; 4719 int supported_mask = IB_QP_STATE | 4720 IB_QP_ACCESS_FLAGS | 4721 IB_QP_PORT | 4722 IB_QP_MIN_RNR_TIMER | 4723 IB_QP_AV | 4724 IB_QP_PATH_MTU | 4725 IB_QP_PKEY_INDEX; 4726 4727 if (qp_attr_mask & ~supported_mask) 4728 return -EINVAL; 4729 if (mqp->state != IB_QPS_RTR) 4730 return -EINVAL; 4731 4732 out = kzalloc(outlen, GFP_KERNEL); 4733 if (!out) 4734 return -ENOMEM; 4735 4736 err = mlx5_core_dct_query(dev, dct, out, outlen); 4737 if (err) 4738 goto out; 4739 4740 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4741 4742 if (qp_attr_mask & IB_QP_STATE) 4743 qp_attr->qp_state = IB_QPS_RTR; 4744 4745 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4746 if (MLX5_GET(dctc, dctc, rre)) 4747 access_flags |= IB_ACCESS_REMOTE_READ; 4748 if (MLX5_GET(dctc, dctc, rwe)) 4749 access_flags |= IB_ACCESS_REMOTE_WRITE; 4750 if (MLX5_GET(dctc, dctc, rae)) 4751 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4752 qp_attr->qp_access_flags = access_flags; 4753 } 4754 4755 if (qp_attr_mask & IB_QP_PORT) 4756 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4757 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4758 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4759 if (qp_attr_mask & IB_QP_AV) { 4760 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4761 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4762 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4763 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4764 } 4765 if (qp_attr_mask & IB_QP_PATH_MTU) 4766 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4767 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4768 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4769 out: 4770 kfree(out); 4771 return err; 4772 } 4773 4774 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4775 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4776 { 4777 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4778 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4779 int err = 0; 4780 u8 raw_packet_qp_state; 4781 4782 if (ibqp->rwq_ind_tbl) 4783 return -ENOSYS; 4784 4785 if (qp->type == IB_QPT_GSI) 4786 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4787 qp_init_attr); 4788 4789 /* Not all of output fields are applicable, make sure to zero them */ 4790 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4791 memset(qp_attr, 0, sizeof(*qp_attr)); 4792 4793 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 4794 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4795 qp_attr_mask, qp_init_attr); 4796 4797 mutex_lock(&qp->mutex); 4798 4799 if (qp->type == IB_QPT_RAW_PACKET || 4800 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4801 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4802 if (err) 4803 goto out; 4804 qp->state = raw_packet_qp_state; 4805 qp_attr->port_num = 1; 4806 } else { 4807 err = query_qp_attr(dev, qp, qp_attr); 4808 if (err) 4809 goto out; 4810 } 4811 4812 qp_attr->qp_state = qp->state; 4813 qp_attr->cur_qp_state = qp_attr->qp_state; 4814 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4815 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4816 4817 if (!ibqp->uobject) { 4818 qp_attr->cap.max_send_wr = qp->sq.max_post; 4819 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4820 qp_init_attr->qp_context = ibqp->qp_context; 4821 } else { 4822 qp_attr->cap.max_send_wr = 0; 4823 qp_attr->cap.max_send_sge = 0; 4824 } 4825 4826 qp_init_attr->qp_type = qp->type; 4827 qp_init_attr->recv_cq = ibqp->recv_cq; 4828 qp_init_attr->send_cq = ibqp->send_cq; 4829 qp_init_attr->srq = ibqp->srq; 4830 qp_attr->cap.max_inline_data = qp->max_inline_data; 4831 4832 qp_init_attr->cap = qp_attr->cap; 4833 4834 qp_init_attr->create_flags = qp->flags; 4835 4836 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4837 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4838 4839 out: 4840 mutex_unlock(&qp->mutex); 4841 return err; 4842 } 4843 4844 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 4845 { 4846 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 4847 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 4848 4849 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4850 return -EOPNOTSUPP; 4851 4852 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 4853 } 4854 4855 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4856 { 4857 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4858 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4859 4860 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 4861 } 4862 4863 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4864 { 4865 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4866 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4867 struct ib_event event; 4868 4869 if (rwq->ibwq.event_handler) { 4870 event.device = rwq->ibwq.device; 4871 event.element.wq = &rwq->ibwq; 4872 switch (type) { 4873 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4874 event.event = IB_EVENT_WQ_FATAL; 4875 break; 4876 default: 4877 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4878 return; 4879 } 4880 4881 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4882 } 4883 } 4884 4885 static int set_delay_drop(struct mlx5_ib_dev *dev) 4886 { 4887 int err = 0; 4888 4889 mutex_lock(&dev->delay_drop.lock); 4890 if (dev->delay_drop.activate) 4891 goto out; 4892 4893 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 4894 if (err) 4895 goto out; 4896 4897 dev->delay_drop.activate = true; 4898 out: 4899 mutex_unlock(&dev->delay_drop.lock); 4900 4901 if (!err) 4902 atomic_inc(&dev->delay_drop.rqs_cnt); 4903 return err; 4904 } 4905 4906 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4907 struct ib_wq_init_attr *init_attr) 4908 { 4909 struct mlx5_ib_dev *dev; 4910 int has_net_offloads; 4911 __be64 *rq_pas0; 4912 int ts_format; 4913 void *in; 4914 void *rqc; 4915 void *wq; 4916 int inlen; 4917 int err; 4918 4919 dev = to_mdev(pd->device); 4920 4921 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 4922 if (ts_format < 0) 4923 return ts_format; 4924 4925 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4926 in = kvzalloc(inlen, GFP_KERNEL); 4927 if (!in) 4928 return -ENOMEM; 4929 4930 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4931 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4932 MLX5_SET(rqc, rqc, mem_rq_type, 4933 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4934 MLX5_SET(rqc, rqc, ts_format, ts_format); 4935 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4936 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4937 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4938 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4939 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4940 MLX5_SET(wq, wq, wq_type, 4941 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 4942 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 4943 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 4944 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 4945 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 4946 err = -EOPNOTSUPP; 4947 goto out; 4948 } else { 4949 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4950 } 4951 } 4952 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4953 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 4954 /* 4955 * In Firmware number of strides in each WQE is: 4956 * "512 * 2^single_wqe_log_num_of_strides" 4957 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 4958 * accepted as 0 to 9 4959 */ 4960 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 4961 2, 3, 4, 5, 6, 7, 8, 9 }; 4962 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 4963 MLX5_SET(wq, wq, log_wqe_stride_size, 4964 rwq->single_stride_log_num_of_bytes - 4965 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 4966 MLX5_SET(wq, wq, log_wqe_num_of_strides, 4967 fw_map[rwq->log_num_strides - 4968 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 4969 } 4970 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4971 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4972 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4973 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4974 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4975 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4976 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4977 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4978 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4979 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4980 err = -EOPNOTSUPP; 4981 goto out; 4982 } 4983 } else { 4984 MLX5_SET(rqc, rqc, vsd, 1); 4985 } 4986 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4987 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4988 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4989 err = -EOPNOTSUPP; 4990 goto out; 4991 } 4992 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4993 } 4994 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4995 if (!(dev->ib_dev.attrs.raw_packet_caps & 4996 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4997 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4998 err = -EOPNOTSUPP; 4999 goto out; 5000 } 5001 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5002 } 5003 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5004 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 5005 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 5006 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5007 err = set_delay_drop(dev); 5008 if (err) { 5009 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5010 err); 5011 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5012 } else { 5013 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5014 } 5015 } 5016 out: 5017 kvfree(in); 5018 return err; 5019 } 5020 5021 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5022 struct ib_wq_init_attr *wq_init_attr, 5023 struct mlx5_ib_create_wq *ucmd, 5024 struct mlx5_ib_rwq *rwq) 5025 { 5026 /* Sanity check RQ size before proceeding */ 5027 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5028 return -EINVAL; 5029 5030 if (!ucmd->rq_wqe_count) 5031 return -EINVAL; 5032 5033 rwq->wqe_count = ucmd->rq_wqe_count; 5034 rwq->wqe_shift = ucmd->rq_wqe_shift; 5035 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5036 return -EINVAL; 5037 5038 rwq->log_rq_stride = rwq->wqe_shift; 5039 rwq->log_rq_size = ilog2(rwq->wqe_count); 5040 return 0; 5041 } 5042 5043 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5044 { 5045 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5046 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5047 return false; 5048 5049 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5050 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5051 return false; 5052 5053 return true; 5054 } 5055 5056 static int prepare_user_rq(struct ib_pd *pd, 5057 struct ib_wq_init_attr *init_attr, 5058 struct ib_udata *udata, 5059 struct mlx5_ib_rwq *rwq) 5060 { 5061 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5062 struct mlx5_ib_create_wq ucmd = {}; 5063 int err; 5064 size_t required_cmd_sz; 5065 5066 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 5067 single_stride_log_num_of_bytes); 5068 if (udata->inlen < required_cmd_sz) { 5069 mlx5_ib_dbg(dev, "invalid inlen\n"); 5070 return -EINVAL; 5071 } 5072 5073 if (udata->inlen > sizeof(ucmd) && 5074 !ib_is_udata_cleared(udata, sizeof(ucmd), 5075 udata->inlen - sizeof(ucmd))) { 5076 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5077 return -EOPNOTSUPP; 5078 } 5079 5080 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5081 mlx5_ib_dbg(dev, "copy failed\n"); 5082 return -EFAULT; 5083 } 5084 5085 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5086 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5087 return -EOPNOTSUPP; 5088 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5089 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5090 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5091 return -EOPNOTSUPP; 5092 } 5093 if ((ucmd.single_stride_log_num_of_bytes < 5094 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5095 (ucmd.single_stride_log_num_of_bytes > 5096 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5097 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5098 ucmd.single_stride_log_num_of_bytes, 5099 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5100 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5101 return -EINVAL; 5102 } 5103 if (!log_of_strides_valid(dev, 5104 ucmd.single_wqe_log_num_of_strides)) { 5105 mlx5_ib_dbg( 5106 dev, 5107 "Invalid log num strides (%u. Range is %u - %u)\n", 5108 ucmd.single_wqe_log_num_of_strides, 5109 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5110 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5111 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5112 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5113 return -EINVAL; 5114 } 5115 rwq->single_stride_log_num_of_bytes = 5116 ucmd.single_stride_log_num_of_bytes; 5117 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5118 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5119 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5120 } 5121 5122 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5123 if (err) { 5124 mlx5_ib_dbg(dev, "err %d\n", err); 5125 return err; 5126 } 5127 5128 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5129 if (err) { 5130 mlx5_ib_dbg(dev, "err %d\n", err); 5131 return err; 5132 } 5133 5134 rwq->user_index = ucmd.user_index; 5135 return 0; 5136 } 5137 5138 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5139 struct ib_wq_init_attr *init_attr, 5140 struct ib_udata *udata) 5141 { 5142 struct mlx5_ib_dev *dev; 5143 struct mlx5_ib_rwq *rwq; 5144 struct mlx5_ib_create_wq_resp resp = {}; 5145 size_t min_resp_len; 5146 int err; 5147 5148 if (!udata) 5149 return ERR_PTR(-ENOSYS); 5150 5151 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5152 if (udata->outlen && udata->outlen < min_resp_len) 5153 return ERR_PTR(-EINVAL); 5154 5155 if (!capable(CAP_SYS_RAWIO) && 5156 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5157 return ERR_PTR(-EPERM); 5158 5159 dev = to_mdev(pd->device); 5160 switch (init_attr->wq_type) { 5161 case IB_WQT_RQ: 5162 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5163 if (!rwq) 5164 return ERR_PTR(-ENOMEM); 5165 err = prepare_user_rq(pd, init_attr, udata, rwq); 5166 if (err) 5167 goto err; 5168 err = create_rq(rwq, pd, init_attr); 5169 if (err) 5170 goto err_user_rq; 5171 break; 5172 default: 5173 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5174 init_attr->wq_type); 5175 return ERR_PTR(-EINVAL); 5176 } 5177 5178 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5179 rwq->ibwq.state = IB_WQS_RESET; 5180 if (udata->outlen) { 5181 resp.response_length = offsetofend( 5182 struct mlx5_ib_create_wq_resp, response_length); 5183 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5184 if (err) 5185 goto err_copy; 5186 } 5187 5188 rwq->core_qp.event = mlx5_ib_wq_event; 5189 rwq->ibwq.event_handler = init_attr->event_handler; 5190 return &rwq->ibwq; 5191 5192 err_copy: 5193 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5194 err_user_rq: 5195 destroy_user_rq(dev, pd, rwq, udata); 5196 err: 5197 kfree(rwq); 5198 return ERR_PTR(err); 5199 } 5200 5201 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5202 { 5203 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5204 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5205 int ret; 5206 5207 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5208 if (ret) 5209 return ret; 5210 destroy_user_rq(dev, wq->pd, rwq, udata); 5211 kfree(rwq); 5212 return 0; 5213 } 5214 5215 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5216 struct ib_rwq_ind_table_init_attr *init_attr, 5217 struct ib_udata *udata) 5218 { 5219 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5220 to_mrwq_ind_table(ib_rwq_ind_table); 5221 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5222 int sz = 1 << init_attr->log_ind_tbl_size; 5223 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5224 size_t min_resp_len; 5225 int inlen; 5226 int err; 5227 int i; 5228 u32 *in; 5229 void *rqtc; 5230 5231 if (udata->inlen > 0 && 5232 !ib_is_udata_cleared(udata, 0, 5233 udata->inlen)) 5234 return -EOPNOTSUPP; 5235 5236 if (init_attr->log_ind_tbl_size > 5237 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5238 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5239 init_attr->log_ind_tbl_size, 5240 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5241 return -EINVAL; 5242 } 5243 5244 min_resp_len = 5245 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5246 if (udata->outlen && udata->outlen < min_resp_len) 5247 return -EINVAL; 5248 5249 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5250 in = kvzalloc(inlen, GFP_KERNEL); 5251 if (!in) 5252 return -ENOMEM; 5253 5254 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5255 5256 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5257 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5258 5259 for (i = 0; i < sz; i++) 5260 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5261 5262 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5263 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5264 5265 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5266 kvfree(in); 5267 if (err) 5268 return err; 5269 5270 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5271 if (udata->outlen) { 5272 resp.response_length = 5273 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5274 response_length); 5275 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5276 if (err) 5277 goto err_copy; 5278 } 5279 5280 return 0; 5281 5282 err_copy: 5283 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5284 return err; 5285 } 5286 5287 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5288 { 5289 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5290 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5291 5292 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5293 } 5294 5295 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5296 u32 wq_attr_mask, struct ib_udata *udata) 5297 { 5298 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5299 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5300 struct mlx5_ib_modify_wq ucmd = {}; 5301 size_t required_cmd_sz; 5302 int curr_wq_state; 5303 int wq_state; 5304 int inlen; 5305 int err; 5306 void *rqc; 5307 void *in; 5308 5309 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5310 if (udata->inlen < required_cmd_sz) 5311 return -EINVAL; 5312 5313 if (udata->inlen > sizeof(ucmd) && 5314 !ib_is_udata_cleared(udata, sizeof(ucmd), 5315 udata->inlen - sizeof(ucmd))) 5316 return -EOPNOTSUPP; 5317 5318 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5319 return -EFAULT; 5320 5321 if (ucmd.comp_mask || ucmd.reserved) 5322 return -EOPNOTSUPP; 5323 5324 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5325 in = kvzalloc(inlen, GFP_KERNEL); 5326 if (!in) 5327 return -ENOMEM; 5328 5329 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5330 5331 curr_wq_state = wq_attr->curr_wq_state; 5332 wq_state = wq_attr->wq_state; 5333 if (curr_wq_state == IB_WQS_ERR) 5334 curr_wq_state = MLX5_RQC_STATE_ERR; 5335 if (wq_state == IB_WQS_ERR) 5336 wq_state = MLX5_RQC_STATE_ERR; 5337 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5338 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5339 MLX5_SET(rqc, rqc, state, wq_state); 5340 5341 if (wq_attr_mask & IB_WQ_FLAGS) { 5342 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5343 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5344 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5345 mlx5_ib_dbg(dev, "VLAN offloads are not " 5346 "supported\n"); 5347 err = -EOPNOTSUPP; 5348 goto out; 5349 } 5350 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5351 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5352 MLX5_SET(rqc, rqc, vsd, 5353 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5354 } 5355 5356 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5357 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5358 err = -EOPNOTSUPP; 5359 goto out; 5360 } 5361 } 5362 5363 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5364 u16 set_id; 5365 5366 set_id = mlx5_ib_get_counters_id(dev, 0); 5367 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5368 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5369 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5370 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5371 } else 5372 dev_info_once( 5373 &dev->ib_dev.dev, 5374 "Receive WQ counters are not supported on current FW\n"); 5375 } 5376 5377 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5378 if (!err) 5379 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5380 5381 out: 5382 kvfree(in); 5383 return err; 5384 } 5385 5386 struct mlx5_ib_drain_cqe { 5387 struct ib_cqe cqe; 5388 struct completion done; 5389 }; 5390 5391 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5392 { 5393 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5394 struct mlx5_ib_drain_cqe, 5395 cqe); 5396 5397 complete(&cqe->done); 5398 } 5399 5400 /* This function returns only once the drained WR was completed */ 5401 static void handle_drain_completion(struct ib_cq *cq, 5402 struct mlx5_ib_drain_cqe *sdrain, 5403 struct mlx5_ib_dev *dev) 5404 { 5405 struct mlx5_core_dev *mdev = dev->mdev; 5406 5407 if (cq->poll_ctx == IB_POLL_DIRECT) { 5408 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5409 ib_process_cq_direct(cq, -1); 5410 return; 5411 } 5412 5413 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5414 struct mlx5_ib_cq *mcq = to_mcq(cq); 5415 bool triggered = false; 5416 unsigned long flags; 5417 5418 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5419 /* Make sure that the CQ handler won't run if wasn't run yet */ 5420 if (!mcq->mcq.reset_notify_added) 5421 mcq->mcq.reset_notify_added = 1; 5422 else 5423 triggered = true; 5424 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5425 5426 if (triggered) { 5427 /* Wait for any scheduled/running task to be ended */ 5428 switch (cq->poll_ctx) { 5429 case IB_POLL_SOFTIRQ: 5430 irq_poll_disable(&cq->iop); 5431 irq_poll_enable(&cq->iop); 5432 break; 5433 case IB_POLL_WORKQUEUE: 5434 cancel_work_sync(&cq->work); 5435 break; 5436 default: 5437 WARN_ON_ONCE(1); 5438 } 5439 } 5440 5441 /* Run the CQ handler - this makes sure that the drain WR will 5442 * be processed if wasn't processed yet. 5443 */ 5444 mcq->mcq.comp(&mcq->mcq, NULL); 5445 } 5446 5447 wait_for_completion(&sdrain->done); 5448 } 5449 5450 void mlx5_ib_drain_sq(struct ib_qp *qp) 5451 { 5452 struct ib_cq *cq = qp->send_cq; 5453 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5454 struct mlx5_ib_drain_cqe sdrain; 5455 const struct ib_send_wr *bad_swr; 5456 struct ib_rdma_wr swr = { 5457 .wr = { 5458 .next = NULL, 5459 { .wr_cqe = &sdrain.cqe, }, 5460 .opcode = IB_WR_RDMA_WRITE, 5461 }, 5462 }; 5463 int ret; 5464 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5465 struct mlx5_core_dev *mdev = dev->mdev; 5466 5467 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5468 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5469 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5470 return; 5471 } 5472 5473 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5474 init_completion(&sdrain.done); 5475 5476 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5477 if (ret) { 5478 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5479 return; 5480 } 5481 5482 handle_drain_completion(cq, &sdrain, dev); 5483 } 5484 5485 void mlx5_ib_drain_rq(struct ib_qp *qp) 5486 { 5487 struct ib_cq *cq = qp->recv_cq; 5488 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5489 struct mlx5_ib_drain_cqe rdrain; 5490 struct ib_recv_wr rwr = {}; 5491 const struct ib_recv_wr *bad_rwr; 5492 int ret; 5493 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5494 struct mlx5_core_dev *mdev = dev->mdev; 5495 5496 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5497 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5498 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5499 return; 5500 } 5501 5502 rwr.wr_cqe = &rdrain.cqe; 5503 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5504 init_completion(&rdrain.done); 5505 5506 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5507 if (ret) { 5508 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5509 return; 5510 } 5511 5512 handle_drain_completion(cq, &rdrain, dev); 5513 } 5514 5515 /* 5516 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5517 * the default counter 5518 */ 5519 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5520 { 5521 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5522 struct mlx5_ib_qp *mqp = to_mqp(qp); 5523 int err = 0; 5524 5525 mutex_lock(&mqp->mutex); 5526 if (mqp->state == IB_QPS_RESET) { 5527 qp->counter = counter; 5528 goto out; 5529 } 5530 5531 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5532 err = -EOPNOTSUPP; 5533 goto out; 5534 } 5535 5536 if (mqp->state == IB_QPS_RTS) { 5537 err = __mlx5_ib_qp_set_counter(qp, counter); 5538 if (!err) 5539 qp->counter = counter; 5540 5541 goto out; 5542 } 5543 5544 mqp->counter_pending = 1; 5545 qp->counter = counter; 5546 5547 out: 5548 mutex_unlock(&mqp->mutex); 5549 return err; 5550 } 5551