1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "qp.h" 44 #include "wr.h" 45 46 enum { 47 MLX5_IB_ACK_REQ_FREQ = 8, 48 }; 49 50 enum { 51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 53 MLX5_IB_LINK_TYPE_IB = 0, 54 MLX5_IB_LINK_TYPE_ETH = 1 55 }; 56 57 enum raw_qp_set_mask_map { 58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 60 }; 61 62 struct mlx5_modify_raw_qp_param { 63 u16 operation; 64 65 u32 set_mask; /* raw_qp_set_mask_map */ 66 67 struct mlx5_rate_limit rl; 68 69 u8 rq_q_ctr_id; 70 u16 port; 71 }; 72 73 static void get_cqs(enum ib_qp_type qp_type, 74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 76 77 static int is_qp0(enum ib_qp_type qp_type) 78 { 79 return qp_type == IB_QPT_SMI; 80 } 81 82 static int is_sqp(enum ib_qp_type qp_type) 83 { 84 return is_qp0(qp_type) || is_qp1(qp_type); 85 } 86 87 /** 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 89 * to kernel buffer 90 * 91 * @umem: User space memory where the WQ is 92 * @buffer: buffer to copy to 93 * @buflen: buffer length 94 * @wqe_index: index of WQE to copy from 95 * @wq_offset: offset to start of WQ 96 * @wq_wqe_cnt: number of WQEs in WQ 97 * @wq_wqe_shift: log2 of WQE size 98 * @bcnt: number of bytes to copy 99 * @bytes_copied: number of bytes to copy (return value) 100 * 101 * Copies from start of WQE bcnt or less bytes. 102 * Does not gurantee to copy the entire WQE. 103 * 104 * Return: zero on success, or an error code. 105 */ 106 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 107 size_t buflen, int wqe_index, 108 int wq_offset, int wq_wqe_cnt, 109 int wq_wqe_shift, int bcnt, 110 size_t *bytes_copied) 111 { 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 114 size_t copy_length; 115 int ret; 116 117 /* don't copy more than requested, more than buffer length or 118 * beyond WQ end 119 */ 120 copy_length = min_t(u32, buflen, wq_end - offset); 121 copy_length = min_t(u32, copy_length, bcnt); 122 123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 124 if (ret) 125 return ret; 126 127 if (!ret && bytes_copied) 128 *bytes_copied = copy_length; 129 130 return 0; 131 } 132 133 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 134 void *buffer, size_t buflen, size_t *bc) 135 { 136 struct mlx5_wqe_ctrl_seg *ctrl; 137 size_t bytes_copied = 0; 138 size_t wqe_length; 139 void *p; 140 int ds; 141 142 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 143 144 /* read the control segment first */ 145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 146 ctrl = p; 147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 148 wqe_length = ds * MLX5_WQE_DS_UNITS; 149 150 /* read rest of WQE if it spreads over more than one stride */ 151 while (bytes_copied < wqe_length) { 152 size_t copy_length = 153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 154 155 if (!copy_length) 156 break; 157 158 memcpy(buffer + bytes_copied, p, copy_length); 159 bytes_copied += copy_length; 160 161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 163 } 164 *bc = bytes_copied; 165 return 0; 166 } 167 168 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 169 void *buffer, size_t buflen, size_t *bc) 170 { 171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 172 struct ib_umem *umem = base->ubuffer.umem; 173 struct mlx5_ib_wq *wq = &qp->sq; 174 struct mlx5_wqe_ctrl_seg *ctrl; 175 size_t bytes_copied; 176 size_t bytes_copied2; 177 size_t wqe_length; 178 int ret; 179 int ds; 180 181 /* at first read as much as possible */ 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 183 wq->offset, wq->wqe_cnt, 184 wq->wqe_shift, buflen, 185 &bytes_copied); 186 if (ret) 187 return ret; 188 189 /* we need at least control segment size to proceed */ 190 if (bytes_copied < sizeof(*ctrl)) 191 return -EINVAL; 192 193 ctrl = buffer; 194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 195 wqe_length = ds * MLX5_WQE_DS_UNITS; 196 197 /* if we copied enough then we are done */ 198 if (bytes_copied >= wqe_length) { 199 *bc = bytes_copied; 200 return 0; 201 } 202 203 /* otherwise this a wrapped around wqe 204 * so read the remaining bytes starting 205 * from wqe_index 0 206 */ 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 208 buflen - bytes_copied, 0, wq->offset, 209 wq->wqe_cnt, wq->wqe_shift, 210 wqe_length - bytes_copied, 211 &bytes_copied2); 212 213 if (ret) 214 return ret; 215 *bc = bytes_copied + bytes_copied2; 216 return 0; 217 } 218 219 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 220 size_t buflen, size_t *bc) 221 { 222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 223 struct ib_umem *umem = base->ubuffer.umem; 224 225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 226 return -EINVAL; 227 228 if (!umem) 229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 230 buflen, bc); 231 232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 233 } 234 235 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 236 void *buffer, size_t buflen, size_t *bc) 237 { 238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 239 struct ib_umem *umem = base->ubuffer.umem; 240 struct mlx5_ib_wq *wq = &qp->rq; 241 size_t bytes_copied; 242 int ret; 243 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 245 wq->offset, wq->wqe_cnt, 246 wq->wqe_shift, buflen, 247 &bytes_copied); 248 249 if (ret) 250 return ret; 251 *bc = bytes_copied; 252 return 0; 253 } 254 255 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 256 size_t buflen, size_t *bc) 257 { 258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 259 struct ib_umem *umem = base->ubuffer.umem; 260 struct mlx5_ib_wq *wq = &qp->rq; 261 size_t wqe_size = 1 << wq->wqe_shift; 262 263 if (buflen < wqe_size) 264 return -EINVAL; 265 266 if (!umem) 267 return -EOPNOTSUPP; 268 269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 270 } 271 272 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 273 void *buffer, size_t buflen, size_t *bc) 274 { 275 struct ib_umem *umem = srq->umem; 276 size_t bytes_copied; 277 int ret; 278 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 280 srq->msrq.max, srq->msrq.wqe_shift, 281 buflen, &bytes_copied); 282 283 if (ret) 284 return ret; 285 *bc = bytes_copied; 286 return 0; 287 } 288 289 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 290 size_t buflen, size_t *bc) 291 { 292 struct ib_umem *umem = srq->umem; 293 size_t wqe_size = 1 << srq->msrq.wqe_shift; 294 295 if (buflen < wqe_size) 296 return -EINVAL; 297 298 if (!umem) 299 return -EOPNOTSUPP; 300 301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 302 } 303 304 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 305 { 306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 307 struct ib_event event; 308 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 310 /* This event is only valid for trans_qps */ 311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 312 } 313 314 if (ibqp->event_handler) { 315 event.device = ibqp->device; 316 event.element.qp = ibqp; 317 switch (type) { 318 case MLX5_EVENT_TYPE_PATH_MIG: 319 event.event = IB_EVENT_PATH_MIG; 320 break; 321 case MLX5_EVENT_TYPE_COMM_EST: 322 event.event = IB_EVENT_COMM_EST; 323 break; 324 case MLX5_EVENT_TYPE_SQ_DRAINED: 325 event.event = IB_EVENT_SQ_DRAINED; 326 break; 327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 328 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 329 break; 330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 331 event.event = IB_EVENT_QP_FATAL; 332 break; 333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 334 event.event = IB_EVENT_PATH_MIG_ERR; 335 break; 336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 337 event.event = IB_EVENT_QP_REQ_ERR; 338 break; 339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 340 event.event = IB_EVENT_QP_ACCESS_ERR; 341 break; 342 default: 343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 344 return; 345 } 346 347 ibqp->event_handler(&event, ibqp->qp_context); 348 } 349 } 350 351 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 353 { 354 int wqe_size; 355 int wq_size; 356 357 /* Sanity check RQ size before proceeding */ 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 359 return -EINVAL; 360 361 if (!has_rq) { 362 qp->rq.max_gs = 0; 363 qp->rq.wqe_cnt = 0; 364 qp->rq.wqe_shift = 0; 365 cap->max_recv_wr = 0; 366 cap->max_recv_sge = 0; 367 } else { 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 369 370 if (ucmd) { 371 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 373 return -EINVAL; 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 375 if ((1 << qp->rq.wqe_shift) / 376 sizeof(struct mlx5_wqe_data_seg) < 377 wq_sig) 378 return -EINVAL; 379 qp->rq.max_gs = 380 (1 << qp->rq.wqe_shift) / 381 sizeof(struct mlx5_wqe_data_seg) - 382 wq_sig; 383 qp->rq.max_post = qp->rq.wqe_cnt; 384 } else { 385 wqe_size = 386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 387 0; 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 389 wqe_size = roundup_pow_of_two(wqe_size); 390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 392 qp->rq.wqe_cnt = wq_size / wqe_size; 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 395 wqe_size, 396 MLX5_CAP_GEN(dev->mdev, 397 max_wqe_sz_rq)); 398 return -EINVAL; 399 } 400 qp->rq.wqe_shift = ilog2(wqe_size); 401 qp->rq.max_gs = 402 (1 << qp->rq.wqe_shift) / 403 sizeof(struct mlx5_wqe_data_seg) - 404 wq_sig; 405 qp->rq.max_post = qp->rq.wqe_cnt; 406 } 407 } 408 409 return 0; 410 } 411 412 static int sq_overhead(struct ib_qp_init_attr *attr) 413 { 414 int size = 0; 415 416 switch (attr->qp_type) { 417 case IB_QPT_XRC_INI: 418 size += sizeof(struct mlx5_wqe_xrc_seg); 419 fallthrough; 420 case IB_QPT_RC: 421 size += sizeof(struct mlx5_wqe_ctrl_seg) + 422 max(sizeof(struct mlx5_wqe_atomic_seg) + 423 sizeof(struct mlx5_wqe_raddr_seg), 424 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 425 sizeof(struct mlx5_mkey_seg) + 426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 427 MLX5_IB_UMR_OCTOWORD); 428 break; 429 430 case IB_QPT_XRC_TGT: 431 return 0; 432 433 case IB_QPT_UC: 434 size += sizeof(struct mlx5_wqe_ctrl_seg) + 435 max(sizeof(struct mlx5_wqe_raddr_seg), 436 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 437 sizeof(struct mlx5_mkey_seg)); 438 break; 439 440 case IB_QPT_UD: 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 442 size += sizeof(struct mlx5_wqe_eth_pad) + 443 sizeof(struct mlx5_wqe_eth_seg); 444 fallthrough; 445 case IB_QPT_SMI: 446 case MLX5_IB_QPT_HW_GSI: 447 size += sizeof(struct mlx5_wqe_ctrl_seg) + 448 sizeof(struct mlx5_wqe_datagram_seg); 449 break; 450 451 case MLX5_IB_QPT_REG_UMR: 452 size += sizeof(struct mlx5_wqe_ctrl_seg) + 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 454 sizeof(struct mlx5_mkey_seg); 455 break; 456 457 default: 458 return -EINVAL; 459 } 460 461 return size; 462 } 463 464 static int calc_send_wqe(struct ib_qp_init_attr *attr) 465 { 466 int inl_size = 0; 467 int size; 468 469 size = sq_overhead(attr); 470 if (size < 0) 471 return size; 472 473 if (attr->cap.max_inline_data) { 474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 475 attr->cap.max_inline_data; 476 } 477 478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 481 return MLX5_SIG_WQE_SIZE; 482 else 483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 484 } 485 486 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 487 { 488 int max_sge; 489 490 if (attr->qp_type == IB_QPT_RC) 491 max_sge = (min_t(int, wqe_size, 512) - 492 sizeof(struct mlx5_wqe_ctrl_seg) - 493 sizeof(struct mlx5_wqe_raddr_seg)) / 494 sizeof(struct mlx5_wqe_data_seg); 495 else if (attr->qp_type == IB_QPT_XRC_INI) 496 max_sge = (min_t(int, wqe_size, 512) - 497 sizeof(struct mlx5_wqe_ctrl_seg) - 498 sizeof(struct mlx5_wqe_xrc_seg) - 499 sizeof(struct mlx5_wqe_raddr_seg)) / 500 sizeof(struct mlx5_wqe_data_seg); 501 else 502 max_sge = (wqe_size - sq_overhead(attr)) / 503 sizeof(struct mlx5_wqe_data_seg); 504 505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 506 sizeof(struct mlx5_wqe_data_seg)); 507 } 508 509 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 510 struct mlx5_ib_qp *qp) 511 { 512 int wqe_size; 513 int wq_size; 514 515 if (!attr->cap.max_send_wr) 516 return 0; 517 518 wqe_size = calc_send_wqe(attr); 519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 520 if (wqe_size < 0) 521 return wqe_size; 522 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 526 return -EINVAL; 527 } 528 529 qp->max_inline_data = wqe_size - sq_overhead(attr) - 530 sizeof(struct mlx5_wqe_inline_seg); 531 attr->cap.max_inline_data = qp->max_inline_data; 532 533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 538 qp->sq.wqe_cnt, 539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 540 return -ENOMEM; 541 } 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 543 qp->sq.max_gs = get_send_sge(attr, wqe_size); 544 if (qp->sq.max_gs < attr->cap.max_send_sge) 545 return -ENOMEM; 546 547 attr->cap.max_send_sge = qp->sq.max_gs; 548 qp->sq.max_post = wq_size / wqe_size; 549 attr->cap.max_send_wr = qp->sq.max_post; 550 551 return wq_size; 552 } 553 554 static int set_user_buf_size(struct mlx5_ib_dev *dev, 555 struct mlx5_ib_qp *qp, 556 struct mlx5_ib_create_qp *ucmd, 557 struct mlx5_ib_qp_base *base, 558 struct ib_qp_init_attr *attr) 559 { 560 int desc_sz = 1 << qp->sq.wqe_shift; 561 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 565 return -EINVAL; 566 } 567 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 570 ucmd->sq_wqe_count); 571 return -EINVAL; 572 } 573 574 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 575 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 578 qp->sq.wqe_cnt, 579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 580 return -EINVAL; 581 } 582 583 if (attr->qp_type == IB_QPT_RAW_PACKET || 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 587 } else { 588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 589 (qp->sq.wqe_cnt << 6); 590 } 591 592 return 0; 593 } 594 595 static int qp_has_rq(struct ib_qp_init_attr *attr) 596 { 597 if (attr->qp_type == IB_QPT_XRC_INI || 598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 599 attr->qp_type == MLX5_IB_QPT_REG_UMR || 600 !attr->cap.max_recv_wr) 601 return 0; 602 603 return 1; 604 } 605 606 enum { 607 /* this is the first blue flame register in the array of bfregs assigned 608 * to a processes. Since we do not use it for blue flame but rather 609 * regular 64 bit doorbells, we do not need a lock for maintaiing 610 * "odd/even" order 611 */ 612 NUM_NON_BLUE_FLAME_BFREGS = 1, 613 }; 614 615 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 616 { 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 618 } 619 620 static int num_med_bfreg(struct mlx5_ib_dev *dev, 621 struct mlx5_bfreg_info *bfregi) 622 { 623 int n; 624 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 626 NUM_NON_BLUE_FLAME_BFREGS; 627 628 return n >= 0 ? n : 0; 629 } 630 631 static int first_med_bfreg(struct mlx5_ib_dev *dev, 632 struct mlx5_bfreg_info *bfregi) 633 { 634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 635 } 636 637 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 638 struct mlx5_bfreg_info *bfregi) 639 { 640 int med; 641 642 med = num_med_bfreg(dev, bfregi); 643 return ++med; 644 } 645 646 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 647 struct mlx5_bfreg_info *bfregi) 648 { 649 int i; 650 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 652 if (!bfregi->count[i]) { 653 bfregi->count[i]++; 654 return i; 655 } 656 } 657 658 return -ENOMEM; 659 } 660 661 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 662 struct mlx5_bfreg_info *bfregi) 663 { 664 int minidx = first_med_bfreg(dev, bfregi); 665 int i; 666 667 if (minidx < 0) 668 return minidx; 669 670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 671 if (bfregi->count[i] < bfregi->count[minidx]) 672 minidx = i; 673 if (!bfregi->count[minidx]) 674 break; 675 } 676 677 bfregi->count[minidx]++; 678 return minidx; 679 } 680 681 static int alloc_bfreg(struct mlx5_ib_dev *dev, 682 struct mlx5_bfreg_info *bfregi) 683 { 684 int bfregn = -ENOMEM; 685 686 if (bfregi->lib_uar_dyn) 687 return -EINVAL; 688 689 mutex_lock(&bfregi->lock); 690 if (bfregi->ver >= 2) { 691 bfregn = alloc_high_class_bfreg(dev, bfregi); 692 if (bfregn < 0) 693 bfregn = alloc_med_class_bfreg(dev, bfregi); 694 } 695 696 if (bfregn < 0) { 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 698 bfregn = 0; 699 bfregi->count[bfregn]++; 700 } 701 mutex_unlock(&bfregi->lock); 702 703 return bfregn; 704 } 705 706 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 707 { 708 mutex_lock(&bfregi->lock); 709 bfregi->count[bfregn]--; 710 mutex_unlock(&bfregi->lock); 711 } 712 713 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 714 { 715 switch (state) { 716 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 723 default: return -1; 724 } 725 } 726 727 static int to_mlx5_st(enum ib_qp_type type) 728 { 729 switch (type) { 730 case IB_QPT_RC: return MLX5_QP_ST_RC; 731 case IB_QPT_UC: return MLX5_QP_ST_UC; 732 case IB_QPT_UD: return MLX5_QP_ST_UD; 733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 734 case IB_QPT_XRC_INI: 735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 736 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 740 default: return -EINVAL; 741 } 742 } 743 744 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 745 struct mlx5_ib_cq *recv_cq); 746 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 747 struct mlx5_ib_cq *recv_cq); 748 749 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, u32 bfregn, 751 bool dyn_bfreg) 752 { 753 unsigned int bfregs_per_sys_page; 754 u32 index_of_sys_page; 755 u32 offset; 756 757 if (bfregi->lib_uar_dyn) 758 return -EINVAL; 759 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 761 MLX5_NON_FP_BFREGS_PER_UAR; 762 index_of_sys_page = bfregn / bfregs_per_sys_page; 763 764 if (dyn_bfreg) { 765 index_of_sys_page += bfregi->num_static_sys_pages; 766 767 if (index_of_sys_page >= bfregi->num_sys_pages) 768 return -EINVAL; 769 770 if (bfregn > bfregi->num_dyn_bfregs || 771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 773 return -EINVAL; 774 } 775 } 776 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 778 return bfregi->sys_pages[index_of_sys_page] + offset; 779 } 780 781 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, 782 unsigned long addr, size_t size, 783 struct ib_umem **umem, int *npages, int *page_shift, 784 int *ncont, u32 *offset) 785 { 786 int err; 787 788 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0); 789 if (IS_ERR(*umem)) { 790 mlx5_ib_dbg(dev, "umem_get failed\n"); 791 return PTR_ERR(*umem); 792 } 793 794 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 795 796 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 797 if (err) { 798 mlx5_ib_warn(dev, "bad offset\n"); 799 goto err_umem; 800 } 801 802 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 803 addr, size, *npages, *page_shift, *ncont, *offset); 804 805 return 0; 806 807 err_umem: 808 ib_umem_release(*umem); 809 *umem = NULL; 810 811 return err; 812 } 813 814 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 815 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 816 { 817 struct mlx5_ib_ucontext *context = 818 rdma_udata_to_drv_context( 819 udata, 820 struct mlx5_ib_ucontext, 821 ibucontext); 822 823 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 824 atomic_dec(&dev->delay_drop.rqs_cnt); 825 826 mlx5_ib_db_unmap_user(context, &rwq->db); 827 ib_umem_release(rwq->umem); 828 } 829 830 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 831 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 832 struct mlx5_ib_create_wq *ucmd) 833 { 834 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 835 udata, struct mlx5_ib_ucontext, ibucontext); 836 int page_shift = 0; 837 int npages; 838 u32 offset = 0; 839 int ncont = 0; 840 int err; 841 842 if (!ucmd->buf_addr) 843 return -EINVAL; 844 845 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 846 if (IS_ERR(rwq->umem)) { 847 mlx5_ib_dbg(dev, "umem_get failed\n"); 848 err = PTR_ERR(rwq->umem); 849 return err; 850 } 851 852 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 853 &ncont, NULL); 854 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 855 &rwq->rq_page_offset); 856 if (err) { 857 mlx5_ib_warn(dev, "bad offset\n"); 858 goto err_umem; 859 } 860 861 rwq->rq_num_pas = ncont; 862 rwq->page_shift = page_shift; 863 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 864 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 865 866 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 867 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 868 npages, page_shift, ncont, offset); 869 870 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 871 if (err) { 872 mlx5_ib_dbg(dev, "map failed\n"); 873 goto err_umem; 874 } 875 876 return 0; 877 878 err_umem: 879 ib_umem_release(rwq->umem); 880 return err; 881 } 882 883 static int adjust_bfregn(struct mlx5_ib_dev *dev, 884 struct mlx5_bfreg_info *bfregi, int bfregn) 885 { 886 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 887 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 888 } 889 890 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 891 struct mlx5_ib_qp *qp, struct ib_udata *udata, 892 struct ib_qp_init_attr *attr, u32 **in, 893 struct mlx5_ib_create_qp_resp *resp, int *inlen, 894 struct mlx5_ib_qp_base *base, 895 struct mlx5_ib_create_qp *ucmd) 896 { 897 struct mlx5_ib_ucontext *context; 898 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 899 int page_shift = 0; 900 int uar_index = 0; 901 int npages; 902 u32 offset = 0; 903 int bfregn; 904 int ncont = 0; 905 __be64 *pas; 906 void *qpc; 907 int err; 908 u16 uid; 909 u32 uar_flags; 910 911 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 912 ibucontext); 913 uar_flags = qp->flags_en & 914 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 915 switch (uar_flags) { 916 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 917 uar_index = ucmd->bfreg_index; 918 bfregn = MLX5_IB_INVALID_BFREG; 919 break; 920 case MLX5_QP_FLAG_BFREG_INDEX: 921 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 922 ucmd->bfreg_index, true); 923 if (uar_index < 0) 924 return uar_index; 925 bfregn = MLX5_IB_INVALID_BFREG; 926 break; 927 case 0: 928 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 929 return -EINVAL; 930 bfregn = alloc_bfreg(dev, &context->bfregi); 931 if (bfregn < 0) 932 return bfregn; 933 break; 934 default: 935 return -EINVAL; 936 } 937 938 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 939 if (bfregn != MLX5_IB_INVALID_BFREG) 940 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 941 false); 942 943 qp->rq.offset = 0; 944 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 945 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 946 947 err = set_user_buf_size(dev, qp, ucmd, base, attr); 948 if (err) 949 goto err_bfreg; 950 951 if (ucmd->buf_addr && ubuffer->buf_size) { 952 ubuffer->buf_addr = ucmd->buf_addr; 953 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, 954 ubuffer->buf_size, &ubuffer->umem, 955 &npages, &page_shift, &ncont, &offset); 956 if (err) 957 goto err_bfreg; 958 } else { 959 ubuffer->umem = NULL; 960 } 961 962 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 963 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 964 *in = kvzalloc(*inlen, GFP_KERNEL); 965 if (!*in) { 966 err = -ENOMEM; 967 goto err_umem; 968 } 969 970 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 971 MLX5_SET(create_qp_in, *in, uid, uid); 972 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 973 if (ubuffer->umem) 974 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 975 976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 977 978 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 979 MLX5_SET(qpc, qpc, page_offset, offset); 980 981 MLX5_SET(qpc, qpc, uar_page, uar_index); 982 if (bfregn != MLX5_IB_INVALID_BFREG) 983 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 984 else 985 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 986 qp->bfregn = bfregn; 987 988 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db); 989 if (err) { 990 mlx5_ib_dbg(dev, "map failed\n"); 991 goto err_free; 992 } 993 994 return 0; 995 996 err_free: 997 kvfree(*in); 998 999 err_umem: 1000 ib_umem_release(ubuffer->umem); 1001 1002 err_bfreg: 1003 if (bfregn != MLX5_IB_INVALID_BFREG) 1004 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1005 return err; 1006 } 1007 1008 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1009 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 1010 { 1011 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1012 udata, struct mlx5_ib_ucontext, ibucontext); 1013 1014 if (udata) { 1015 /* User QP */ 1016 mlx5_ib_db_unmap_user(context, &qp->db); 1017 ib_umem_release(base->ubuffer.umem); 1018 1019 /* 1020 * Free only the BFREGs which are handled by the kernel. 1021 * BFREGs of UARs allocated dynamically are handled by user. 1022 */ 1023 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1024 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1025 return; 1026 } 1027 1028 /* Kernel QP */ 1029 kvfree(qp->sq.wqe_head); 1030 kvfree(qp->sq.w_list); 1031 kvfree(qp->sq.wrid); 1032 kvfree(qp->sq.wr_data); 1033 kvfree(qp->rq.wrid); 1034 if (qp->db.db) 1035 mlx5_db_free(dev->mdev, &qp->db); 1036 if (qp->buf.frags) 1037 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1038 } 1039 1040 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1041 struct ib_qp_init_attr *init_attr, 1042 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1043 struct mlx5_ib_qp_base *base) 1044 { 1045 int uar_index; 1046 void *qpc; 1047 int err; 1048 1049 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1050 qp->bf.bfreg = &dev->fp_bfreg; 1051 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1052 qp->bf.bfreg = &dev->wc_bfreg; 1053 else 1054 qp->bf.bfreg = &dev->bfreg; 1055 1056 /* We need to divide by two since each register is comprised of 1057 * two buffers of identical size, namely odd and even 1058 */ 1059 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1060 uar_index = qp->bf.bfreg->index; 1061 1062 err = calc_sq_size(dev, init_attr, qp); 1063 if (err < 0) { 1064 mlx5_ib_dbg(dev, "err %d\n", err); 1065 return err; 1066 } 1067 1068 qp->rq.offset = 0; 1069 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1070 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1071 1072 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1073 &qp->buf, dev->mdev->priv.numa_node); 1074 if (err) { 1075 mlx5_ib_dbg(dev, "err %d\n", err); 1076 return err; 1077 } 1078 1079 if (qp->rq.wqe_cnt) 1080 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1081 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1082 1083 if (qp->sq.wqe_cnt) { 1084 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1085 MLX5_SEND_WQE_BB; 1086 mlx5_init_fbc_offset(qp->buf.frags + 1087 (qp->sq.offset / PAGE_SIZE), 1088 ilog2(MLX5_SEND_WQE_BB), 1089 ilog2(qp->sq.wqe_cnt), 1090 sq_strides_offset, &qp->sq.fbc); 1091 1092 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1093 } 1094 1095 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1096 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1097 *in = kvzalloc(*inlen, GFP_KERNEL); 1098 if (!*in) { 1099 err = -ENOMEM; 1100 goto err_buf; 1101 } 1102 1103 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1104 MLX5_SET(qpc, qpc, uar_page, uar_index); 1105 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1106 1107 /* Set "fast registration enabled" for all kernel QPs */ 1108 MLX5_SET(qpc, qpc, fre, 1); 1109 MLX5_SET(qpc, qpc, rlky, 1); 1110 1111 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1112 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1113 1114 mlx5_fill_page_frag_array(&qp->buf, 1115 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1116 *in, pas)); 1117 1118 err = mlx5_db_alloc(dev->mdev, &qp->db); 1119 if (err) { 1120 mlx5_ib_dbg(dev, "err %d\n", err); 1121 goto err_free; 1122 } 1123 1124 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1125 sizeof(*qp->sq.wrid), GFP_KERNEL); 1126 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1127 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1128 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1129 sizeof(*qp->rq.wrid), GFP_KERNEL); 1130 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1131 sizeof(*qp->sq.w_list), GFP_KERNEL); 1132 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1133 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1134 1135 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1136 !qp->sq.w_list || !qp->sq.wqe_head) { 1137 err = -ENOMEM; 1138 goto err_wrid; 1139 } 1140 1141 return 0; 1142 1143 err_wrid: 1144 kvfree(qp->sq.wqe_head); 1145 kvfree(qp->sq.w_list); 1146 kvfree(qp->sq.wrid); 1147 kvfree(qp->sq.wr_data); 1148 kvfree(qp->rq.wrid); 1149 mlx5_db_free(dev->mdev, &qp->db); 1150 1151 err_free: 1152 kvfree(*in); 1153 1154 err_buf: 1155 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1156 return err; 1157 } 1158 1159 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1160 { 1161 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1162 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1163 return MLX5_SRQ_RQ; 1164 else if (!qp->has_rq) 1165 return MLX5_ZERO_LEN_RQ; 1166 1167 return MLX5_NON_ZERO_RQ; 1168 } 1169 1170 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1171 struct mlx5_ib_qp *qp, 1172 struct mlx5_ib_sq *sq, u32 tdn, 1173 struct ib_pd *pd) 1174 { 1175 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1176 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1177 1178 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1179 MLX5_SET(tisc, tisc, transport_domain, tdn); 1180 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1181 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1182 1183 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1184 } 1185 1186 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1187 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1188 { 1189 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1190 } 1191 1192 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1193 { 1194 if (sq->flow_rule) 1195 mlx5_del_flow_rules(sq->flow_rule); 1196 sq->flow_rule = NULL; 1197 } 1198 1199 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1200 struct ib_udata *udata, 1201 struct mlx5_ib_sq *sq, void *qpin, 1202 struct ib_pd *pd) 1203 { 1204 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1205 __be64 *pas; 1206 void *in; 1207 void *sqc; 1208 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1209 void *wq; 1210 int inlen; 1211 int err; 1212 int page_shift = 0; 1213 int npages; 1214 int ncont = 0; 1215 u32 offset = 0; 1216 1217 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, 1218 &sq->ubuffer.umem, &npages, &page_shift, &ncont, 1219 &offset); 1220 if (err) 1221 return err; 1222 1223 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1224 in = kvzalloc(inlen, GFP_KERNEL); 1225 if (!in) { 1226 err = -ENOMEM; 1227 goto err_umem; 1228 } 1229 1230 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1231 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1232 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1233 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1234 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1235 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1236 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1237 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1238 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1239 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1240 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1241 MLX5_CAP_ETH(dev->mdev, swp)) 1242 MLX5_SET(sqc, sqc, allow_swp, 1); 1243 1244 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1245 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1246 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1247 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1248 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1249 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1250 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1251 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1252 MLX5_SET(wq, wq, page_offset, offset); 1253 1254 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1255 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1256 1257 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1258 1259 kvfree(in); 1260 1261 if (err) 1262 goto err_umem; 1263 1264 return 0; 1265 1266 err_umem: 1267 ib_umem_release(sq->ubuffer.umem); 1268 sq->ubuffer.umem = NULL; 1269 1270 return err; 1271 } 1272 1273 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1274 struct mlx5_ib_sq *sq) 1275 { 1276 destroy_flow_rule_vport_sq(sq); 1277 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1278 ib_umem_release(sq->ubuffer.umem); 1279 } 1280 1281 static size_t get_rq_pas_size(void *qpc) 1282 { 1283 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1284 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1285 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1286 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1287 u32 po_quanta = 1 << (log_page_size - 6); 1288 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1289 u32 page_size = 1 << log_page_size; 1290 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1291 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1292 1293 return rq_num_pas * sizeof(u64); 1294 } 1295 1296 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1297 struct mlx5_ib_rq *rq, void *qpin, 1298 size_t qpinlen, struct ib_pd *pd) 1299 { 1300 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1301 __be64 *pas; 1302 __be64 *qp_pas; 1303 void *in; 1304 void *rqc; 1305 void *wq; 1306 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1307 size_t rq_pas_size = get_rq_pas_size(qpc); 1308 size_t inlen; 1309 int err; 1310 1311 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1312 return -EINVAL; 1313 1314 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1315 in = kvzalloc(inlen, GFP_KERNEL); 1316 if (!in) 1317 return -ENOMEM; 1318 1319 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1320 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1321 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1322 MLX5_SET(rqc, rqc, vsd, 1); 1323 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1324 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1325 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1326 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1327 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1328 1329 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1330 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1331 1332 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1333 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1334 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1335 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1336 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1337 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1338 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1339 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1340 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1341 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1342 1343 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1344 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1345 memcpy(pas, qp_pas, rq_pas_size); 1346 1347 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1348 1349 kvfree(in); 1350 1351 return err; 1352 } 1353 1354 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1355 struct mlx5_ib_rq *rq) 1356 { 1357 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1358 } 1359 1360 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1361 struct mlx5_ib_rq *rq, 1362 u32 qp_flags_en, 1363 struct ib_pd *pd) 1364 { 1365 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1366 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1367 mlx5_ib_disable_lb(dev, false, true); 1368 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1369 } 1370 1371 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1372 struct mlx5_ib_rq *rq, u32 tdn, 1373 u32 *qp_flags_en, struct ib_pd *pd, 1374 u32 *out) 1375 { 1376 u8 lb_flag = 0; 1377 u32 *in; 1378 void *tirc; 1379 int inlen; 1380 int err; 1381 1382 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1383 in = kvzalloc(inlen, GFP_KERNEL); 1384 if (!in) 1385 return -ENOMEM; 1386 1387 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1388 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1389 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1390 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1391 MLX5_SET(tirc, tirc, transport_domain, tdn); 1392 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1393 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1394 1395 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1396 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1397 1398 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1399 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1400 1401 if (dev->is_rep) { 1402 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1403 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1404 } 1405 1406 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1407 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1408 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1409 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1410 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1411 err = mlx5_ib_enable_lb(dev, false, true); 1412 1413 if (err) 1414 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1415 } 1416 kvfree(in); 1417 1418 return err; 1419 } 1420 1421 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1422 u32 *in, size_t inlen, 1423 struct ib_pd *pd, 1424 struct ib_udata *udata, 1425 struct mlx5_ib_create_qp_resp *resp) 1426 { 1427 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1428 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1429 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1430 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1431 udata, struct mlx5_ib_ucontext, ibucontext); 1432 int err; 1433 u32 tdn = mucontext->tdn; 1434 u16 uid = to_mpd(pd)->uid; 1435 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1436 1437 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1438 return -EINVAL; 1439 if (qp->sq.wqe_cnt) { 1440 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1441 if (err) 1442 return err; 1443 1444 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); 1445 if (err) 1446 goto err_destroy_tis; 1447 1448 if (uid) { 1449 resp->tisn = sq->tisn; 1450 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1451 resp->sqn = sq->base.mqp.qpn; 1452 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1453 } 1454 1455 sq->base.container_mibqp = qp; 1456 sq->base.mqp.event = mlx5_ib_qp_event; 1457 } 1458 1459 if (qp->rq.wqe_cnt) { 1460 rq->base.container_mibqp = qp; 1461 1462 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1463 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1464 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1465 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1466 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1467 if (err) 1468 goto err_destroy_sq; 1469 1470 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1471 out); 1472 if (err) 1473 goto err_destroy_rq; 1474 1475 if (uid) { 1476 resp->rqn = rq->base.mqp.qpn; 1477 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1478 resp->tirn = rq->tirn; 1479 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1480 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1481 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1482 resp->tir_icm_addr = MLX5_GET( 1483 create_tir_out, out, icm_address_31_0); 1484 resp->tir_icm_addr |= 1485 (u64)MLX5_GET(create_tir_out, out, 1486 icm_address_39_32) 1487 << 32; 1488 resp->tir_icm_addr |= 1489 (u64)MLX5_GET(create_tir_out, out, 1490 icm_address_63_40) 1491 << 40; 1492 resp->comp_mask |= 1493 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1494 } 1495 } 1496 } 1497 1498 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1499 rq->base.mqp.qpn; 1500 return 0; 1501 1502 err_destroy_rq: 1503 destroy_raw_packet_qp_rq(dev, rq); 1504 err_destroy_sq: 1505 if (!qp->sq.wqe_cnt) 1506 return err; 1507 destroy_raw_packet_qp_sq(dev, sq); 1508 err_destroy_tis: 1509 destroy_raw_packet_qp_tis(dev, sq, pd); 1510 1511 return err; 1512 } 1513 1514 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1515 struct mlx5_ib_qp *qp) 1516 { 1517 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1518 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1519 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1520 1521 if (qp->rq.wqe_cnt) { 1522 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1523 destroy_raw_packet_qp_rq(dev, rq); 1524 } 1525 1526 if (qp->sq.wqe_cnt) { 1527 destroy_raw_packet_qp_sq(dev, sq); 1528 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1529 } 1530 } 1531 1532 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1533 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1534 { 1535 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1536 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1537 1538 sq->sq = &qp->sq; 1539 rq->rq = &qp->rq; 1540 sq->doorbell = &qp->db; 1541 rq->doorbell = &qp->db; 1542 } 1543 1544 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1545 { 1546 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1547 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1548 mlx5_ib_disable_lb(dev, false, true); 1549 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1550 to_mpd(qp->ibqp.pd)->uid); 1551 } 1552 1553 struct mlx5_create_qp_params { 1554 struct ib_udata *udata; 1555 size_t inlen; 1556 size_t outlen; 1557 size_t ucmd_size; 1558 void *ucmd; 1559 u8 is_rss_raw : 1; 1560 struct ib_qp_init_attr *attr; 1561 u32 uidx; 1562 struct mlx5_ib_create_qp_resp resp; 1563 }; 1564 1565 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1566 struct mlx5_ib_qp *qp, 1567 struct mlx5_create_qp_params *params) 1568 { 1569 struct ib_qp_init_attr *init_attr = params->attr; 1570 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1571 struct ib_udata *udata = params->udata; 1572 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1573 udata, struct mlx5_ib_ucontext, ibucontext); 1574 int inlen; 1575 int outlen; 1576 int err; 1577 u32 *in; 1578 u32 *out; 1579 void *tirc; 1580 void *hfso; 1581 u32 selected_fields = 0; 1582 u32 outer_l4; 1583 u32 tdn = mucontext->tdn; 1584 u8 lb_flag = 0; 1585 1586 if (ucmd->comp_mask) { 1587 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1588 return -EOPNOTSUPP; 1589 } 1590 1591 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1592 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1593 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1594 return -EOPNOTSUPP; 1595 } 1596 1597 if (dev->is_rep) 1598 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1599 1600 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1601 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1602 1603 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1604 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1605 1606 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1607 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1608 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1609 if (!in) 1610 return -ENOMEM; 1611 1612 out = in + MLX5_ST_SZ_DW(create_tir_in); 1613 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1614 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1615 MLX5_SET(tirc, tirc, disp_type, 1616 MLX5_TIRC_DISP_TYPE_INDIRECT); 1617 MLX5_SET(tirc, tirc, indirect_table, 1618 init_attr->rwq_ind_tbl->ind_tbl_num); 1619 MLX5_SET(tirc, tirc, transport_domain, tdn); 1620 1621 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1622 1623 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1624 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1625 1626 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1627 1628 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1629 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1630 else 1631 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1632 1633 switch (ucmd->rx_hash_function) { 1634 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1635 { 1636 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1637 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1638 1639 if (len != ucmd->rx_key_len) { 1640 err = -EINVAL; 1641 goto err; 1642 } 1643 1644 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1645 memcpy(rss_key, ucmd->rx_hash_key, len); 1646 break; 1647 } 1648 default: 1649 err = -EOPNOTSUPP; 1650 goto err; 1651 } 1652 1653 if (!ucmd->rx_hash_fields_mask) { 1654 /* special case when this TIR serves as steering entry without hashing */ 1655 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1656 goto create_tir; 1657 err = -EINVAL; 1658 goto err; 1659 } 1660 1661 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1662 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1663 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1664 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1665 err = -EINVAL; 1666 goto err; 1667 } 1668 1669 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1670 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1671 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1672 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1673 MLX5_L3_PROT_TYPE_IPV4); 1674 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1675 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1676 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1677 MLX5_L3_PROT_TYPE_IPV6); 1678 1679 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1680 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1681 << 0 | 1682 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1683 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1684 << 1 | 1685 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1686 1687 /* Check that only one l4 protocol is set */ 1688 if (outer_l4 & (outer_l4 - 1)) { 1689 err = -EINVAL; 1690 goto err; 1691 } 1692 1693 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1694 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1695 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1696 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1697 MLX5_L4_PROT_TYPE_TCP); 1698 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1699 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1700 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1701 MLX5_L4_PROT_TYPE_UDP); 1702 1703 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1704 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1705 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1706 1707 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1708 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1709 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1710 1711 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1712 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1713 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1714 1715 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1716 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1717 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1718 1719 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1720 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1721 1722 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1723 1724 create_tir: 1725 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1726 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1727 1728 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1729 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1730 err = mlx5_ib_enable_lb(dev, false, true); 1731 1732 if (err) 1733 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1734 to_mpd(pd)->uid); 1735 } 1736 1737 if (err) 1738 goto err; 1739 1740 if (mucontext->devx_uid) { 1741 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1742 params->resp.tirn = qp->rss_qp.tirn; 1743 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1744 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1745 params->resp.tir_icm_addr = 1746 MLX5_GET(create_tir_out, out, icm_address_31_0); 1747 params->resp.tir_icm_addr |= 1748 (u64)MLX5_GET(create_tir_out, out, 1749 icm_address_39_32) 1750 << 32; 1751 params->resp.tir_icm_addr |= 1752 (u64)MLX5_GET(create_tir_out, out, 1753 icm_address_63_40) 1754 << 40; 1755 params->resp.comp_mask |= 1756 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1757 } 1758 } 1759 1760 kvfree(in); 1761 /* qpn is reserved for that QP */ 1762 qp->trans_qp.base.mqp.qpn = 0; 1763 qp->is_rss = true; 1764 return 0; 1765 1766 err: 1767 kvfree(in); 1768 return err; 1769 } 1770 1771 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1772 struct mlx5_ib_qp *qp, 1773 struct ib_qp_init_attr *init_attr, 1774 void *qpc) 1775 { 1776 int scqe_sz; 1777 bool allow_scat_cqe = false; 1778 1779 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1780 1781 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1782 return; 1783 1784 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1785 if (scqe_sz == 128) { 1786 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1787 return; 1788 } 1789 1790 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1791 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1792 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1793 } 1794 1795 static int atomic_size_to_mode(int size_mask) 1796 { 1797 /* driver does not support atomic_size > 256B 1798 * and does not know how to translate bigger sizes 1799 */ 1800 int supported_size_mask = size_mask & 0x1ff; 1801 int log_max_size; 1802 1803 if (!supported_size_mask) 1804 return -EOPNOTSUPP; 1805 1806 log_max_size = __fls(supported_size_mask); 1807 1808 if (log_max_size > 3) 1809 return log_max_size; 1810 1811 return MLX5_ATOMIC_MODE_8B; 1812 } 1813 1814 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1815 enum ib_qp_type qp_type) 1816 { 1817 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1818 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1819 int atomic_mode = -EOPNOTSUPP; 1820 int atomic_size_mask; 1821 1822 if (!atomic) 1823 return -EOPNOTSUPP; 1824 1825 if (qp_type == MLX5_IB_QPT_DCT) 1826 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1827 else 1828 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1829 1830 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1831 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1832 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1833 1834 if (atomic_mode <= 0 && 1835 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1836 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1837 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1838 1839 return atomic_mode; 1840 } 1841 1842 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1843 struct mlx5_create_qp_params *params) 1844 { 1845 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1846 struct ib_qp_init_attr *attr = params->attr; 1847 u32 uidx = params->uidx; 1848 struct mlx5_ib_resources *devr = &dev->devr; 1849 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1850 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1851 struct mlx5_core_dev *mdev = dev->mdev; 1852 struct mlx5_ib_qp_base *base; 1853 unsigned long flags; 1854 void *qpc; 1855 u32 *in; 1856 int err; 1857 1858 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1859 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1860 1861 in = kvzalloc(inlen, GFP_KERNEL); 1862 if (!in) 1863 return -ENOMEM; 1864 1865 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd) 1866 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1867 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1868 1869 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 1870 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1871 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 1872 1873 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1874 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1875 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1876 MLX5_SET(qpc, qpc, cd_master, 1); 1877 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1878 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1879 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1880 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1881 1882 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 1883 MLX5_SET(qpc, qpc, no_sq, 1); 1884 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1885 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1886 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1887 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 1888 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1889 1890 /* 0xffffff means we ask to work with cqe version 0 */ 1891 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1892 MLX5_SET(qpc, qpc, user_index, uidx); 1893 1894 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1895 MLX5_SET(qpc, qpc, end_padding_mode, 1896 MLX5_WQ_END_PAD_MODE_ALIGN); 1897 /* Special case to clean flag */ 1898 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 1899 } 1900 1901 base = &qp->trans_qp.base; 1902 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 1903 kvfree(in); 1904 if (err) 1905 return err; 1906 1907 base->container_mibqp = qp; 1908 base->mqp.event = mlx5_ib_qp_event; 1909 if (MLX5_CAP_GEN(mdev, ece_support)) 1910 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 1911 1912 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1913 list_add_tail(&qp->qps_list, &dev->qp_list); 1914 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1915 1916 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 1917 return 0; 1918 } 1919 1920 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1921 struct mlx5_ib_qp *qp, 1922 struct mlx5_create_qp_params *params) 1923 { 1924 struct ib_qp_init_attr *init_attr = params->attr; 1925 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1926 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1927 struct ib_udata *udata = params->udata; 1928 u32 uidx = params->uidx; 1929 struct mlx5_ib_resources *devr = &dev->devr; 1930 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1931 struct mlx5_core_dev *mdev = dev->mdev; 1932 struct mlx5_ib_cq *send_cq; 1933 struct mlx5_ib_cq *recv_cq; 1934 unsigned long flags; 1935 struct mlx5_ib_qp_base *base; 1936 int mlx5_st; 1937 void *qpc; 1938 u32 *in; 1939 int err; 1940 1941 spin_lock_init(&qp->sq.lock); 1942 spin_lock_init(&qp->rq.lock); 1943 1944 mlx5_st = to_mlx5_st(qp->type); 1945 if (mlx5_st < 0) 1946 return -EINVAL; 1947 1948 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1949 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1950 1951 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1952 qp->underlay_qpn = init_attr->source_qpn; 1953 1954 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1955 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 1956 &qp->raw_packet_qp.rq.base : 1957 &qp->trans_qp.base; 1958 1959 qp->has_rq = qp_has_rq(init_attr); 1960 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 1961 if (err) { 1962 mlx5_ib_dbg(dev, "err %d\n", err); 1963 return err; 1964 } 1965 1966 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 1967 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 1968 return -EINVAL; 1969 1970 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 1971 return -EINVAL; 1972 1973 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 1974 &inlen, base, ucmd); 1975 if (err) 1976 return err; 1977 1978 if (is_sqp(init_attr->qp_type)) 1979 qp->port = init_attr->port_num; 1980 1981 if (MLX5_CAP_GEN(mdev, ece_support)) 1982 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1983 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1984 1985 MLX5_SET(qpc, qpc, st, mlx5_st); 1986 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1987 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 1988 1989 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 1990 MLX5_SET(qpc, qpc, wq_signature, 1); 1991 1992 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1993 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1994 1995 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1996 MLX5_SET(qpc, qpc, cd_master, 1); 1997 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1998 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1999 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2000 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2001 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2002 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2003 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2004 (init_attr->qp_type == IB_QPT_RC || 2005 init_attr->qp_type == IB_QPT_UC)) { 2006 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2007 2008 MLX5_SET(qpc, qpc, cs_res, 2009 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2010 MLX5_RES_SCAT_DATA32_CQE); 2011 } 2012 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2013 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2014 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2015 2016 if (qp->rq.wqe_cnt) { 2017 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2018 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2019 } 2020 2021 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2022 2023 if (qp->sq.wqe_cnt) { 2024 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2025 } else { 2026 MLX5_SET(qpc, qpc, no_sq, 1); 2027 if (init_attr->srq && 2028 init_attr->srq->srq_type == IB_SRQT_TM) 2029 MLX5_SET(qpc, qpc, offload_type, 2030 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2031 } 2032 2033 /* Set default resources */ 2034 switch (init_attr->qp_type) { 2035 case IB_QPT_XRC_INI: 2036 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2037 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2038 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2039 break; 2040 default: 2041 if (init_attr->srq) { 2042 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2043 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2044 } else { 2045 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2046 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2047 } 2048 } 2049 2050 if (init_attr->send_cq) 2051 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2052 2053 if (init_attr->recv_cq) 2054 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2055 2056 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2057 2058 /* 0xffffff means we ask to work with cqe version 0 */ 2059 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2060 MLX5_SET(qpc, qpc, user_index, uidx); 2061 2062 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2063 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2064 MLX5_SET(qpc, qpc, end_padding_mode, 2065 MLX5_WQ_END_PAD_MODE_ALIGN); 2066 /* Special case to clean flag */ 2067 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2068 } 2069 2070 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2071 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2072 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2073 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2074 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2075 ¶ms->resp); 2076 } else 2077 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2078 2079 kvfree(in); 2080 if (err) 2081 goto err_create; 2082 2083 base->container_mibqp = qp; 2084 base->mqp.event = mlx5_ib_qp_event; 2085 if (MLX5_CAP_GEN(mdev, ece_support)) 2086 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2087 2088 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2089 &send_cq, &recv_cq); 2090 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2091 mlx5_ib_lock_cqs(send_cq, recv_cq); 2092 /* Maintain device to QPs access, needed for further handling via reset 2093 * flow 2094 */ 2095 list_add_tail(&qp->qps_list, &dev->qp_list); 2096 /* Maintain CQ to QPs access, needed for further handling via reset flow 2097 */ 2098 if (send_cq) 2099 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2100 if (recv_cq) 2101 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2102 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2103 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2104 2105 return 0; 2106 2107 err_create: 2108 destroy_qp(dev, qp, base, udata); 2109 return err; 2110 } 2111 2112 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2113 struct mlx5_ib_qp *qp, 2114 struct mlx5_create_qp_params *params) 2115 { 2116 struct ib_qp_init_attr *attr = params->attr; 2117 u32 uidx = params->uidx; 2118 struct mlx5_ib_resources *devr = &dev->devr; 2119 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2120 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2121 struct mlx5_core_dev *mdev = dev->mdev; 2122 struct mlx5_ib_cq *send_cq; 2123 struct mlx5_ib_cq *recv_cq; 2124 unsigned long flags; 2125 struct mlx5_ib_qp_base *base; 2126 int mlx5_st; 2127 void *qpc; 2128 u32 *in; 2129 int err; 2130 2131 spin_lock_init(&qp->sq.lock); 2132 spin_lock_init(&qp->rq.lock); 2133 2134 mlx5_st = to_mlx5_st(qp->type); 2135 if (mlx5_st < 0) 2136 return -EINVAL; 2137 2138 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2139 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2140 2141 base = &qp->trans_qp.base; 2142 2143 qp->has_rq = qp_has_rq(attr); 2144 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2145 if (err) { 2146 mlx5_ib_dbg(dev, "err %d\n", err); 2147 return err; 2148 } 2149 2150 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2151 if (err) 2152 return err; 2153 2154 if (is_sqp(attr->qp_type)) 2155 qp->port = attr->port_num; 2156 2157 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2158 2159 MLX5_SET(qpc, qpc, st, mlx5_st); 2160 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2161 2162 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2163 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2164 else 2165 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2166 2167 2168 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2169 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2170 2171 if (qp->rq.wqe_cnt) { 2172 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2173 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2174 } 2175 2176 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2177 2178 if (qp->sq.wqe_cnt) 2179 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2180 else 2181 MLX5_SET(qpc, qpc, no_sq, 1); 2182 2183 if (attr->srq) { 2184 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2185 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2186 to_msrq(attr->srq)->msrq.srqn); 2187 } else { 2188 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2189 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2190 to_msrq(devr->s1)->msrq.srqn); 2191 } 2192 2193 if (attr->send_cq) 2194 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2195 2196 if (attr->recv_cq) 2197 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2198 2199 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2200 2201 /* 0xffffff means we ask to work with cqe version 0 */ 2202 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2203 MLX5_SET(qpc, qpc, user_index, uidx); 2204 2205 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2206 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2207 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2208 2209 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2210 kvfree(in); 2211 if (err) 2212 goto err_create; 2213 2214 base->container_mibqp = qp; 2215 base->mqp.event = mlx5_ib_qp_event; 2216 2217 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2218 &send_cq, &recv_cq); 2219 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2220 mlx5_ib_lock_cqs(send_cq, recv_cq); 2221 /* Maintain device to QPs access, needed for further handling via reset 2222 * flow 2223 */ 2224 list_add_tail(&qp->qps_list, &dev->qp_list); 2225 /* Maintain CQ to QPs access, needed for further handling via reset flow 2226 */ 2227 if (send_cq) 2228 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2229 if (recv_cq) 2230 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2231 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2232 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2233 2234 return 0; 2235 2236 err_create: 2237 destroy_qp(dev, qp, base, NULL); 2238 return err; 2239 } 2240 2241 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2242 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2243 { 2244 if (send_cq) { 2245 if (recv_cq) { 2246 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2247 spin_lock(&send_cq->lock); 2248 spin_lock_nested(&recv_cq->lock, 2249 SINGLE_DEPTH_NESTING); 2250 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2251 spin_lock(&send_cq->lock); 2252 __acquire(&recv_cq->lock); 2253 } else { 2254 spin_lock(&recv_cq->lock); 2255 spin_lock_nested(&send_cq->lock, 2256 SINGLE_DEPTH_NESTING); 2257 } 2258 } else { 2259 spin_lock(&send_cq->lock); 2260 __acquire(&recv_cq->lock); 2261 } 2262 } else if (recv_cq) { 2263 spin_lock(&recv_cq->lock); 2264 __acquire(&send_cq->lock); 2265 } else { 2266 __acquire(&send_cq->lock); 2267 __acquire(&recv_cq->lock); 2268 } 2269 } 2270 2271 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2272 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2273 { 2274 if (send_cq) { 2275 if (recv_cq) { 2276 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2277 spin_unlock(&recv_cq->lock); 2278 spin_unlock(&send_cq->lock); 2279 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2280 __release(&recv_cq->lock); 2281 spin_unlock(&send_cq->lock); 2282 } else { 2283 spin_unlock(&send_cq->lock); 2284 spin_unlock(&recv_cq->lock); 2285 } 2286 } else { 2287 __release(&recv_cq->lock); 2288 spin_unlock(&send_cq->lock); 2289 } 2290 } else if (recv_cq) { 2291 __release(&send_cq->lock); 2292 spin_unlock(&recv_cq->lock); 2293 } else { 2294 __release(&recv_cq->lock); 2295 __release(&send_cq->lock); 2296 } 2297 } 2298 2299 static void get_cqs(enum ib_qp_type qp_type, 2300 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2301 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2302 { 2303 switch (qp_type) { 2304 case IB_QPT_XRC_TGT: 2305 *send_cq = NULL; 2306 *recv_cq = NULL; 2307 break; 2308 case MLX5_IB_QPT_REG_UMR: 2309 case IB_QPT_XRC_INI: 2310 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2311 *recv_cq = NULL; 2312 break; 2313 2314 case IB_QPT_SMI: 2315 case MLX5_IB_QPT_HW_GSI: 2316 case IB_QPT_RC: 2317 case IB_QPT_UC: 2318 case IB_QPT_UD: 2319 case IB_QPT_RAW_PACKET: 2320 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2321 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2322 break; 2323 default: 2324 *send_cq = NULL; 2325 *recv_cq = NULL; 2326 break; 2327 } 2328 } 2329 2330 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2331 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2332 u8 lag_tx_affinity); 2333 2334 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2335 struct ib_udata *udata) 2336 { 2337 struct mlx5_ib_cq *send_cq, *recv_cq; 2338 struct mlx5_ib_qp_base *base; 2339 unsigned long flags; 2340 int err; 2341 2342 if (qp->is_rss) { 2343 destroy_rss_raw_qp_tir(dev, qp); 2344 return; 2345 } 2346 2347 base = (qp->type == IB_QPT_RAW_PACKET || 2348 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2349 &qp->raw_packet_qp.rq.base : 2350 &qp->trans_qp.base; 2351 2352 if (qp->state != IB_QPS_RESET) { 2353 if (qp->type != IB_QPT_RAW_PACKET && 2354 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2355 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2356 NULL, &base->mqp, NULL); 2357 } else { 2358 struct mlx5_modify_raw_qp_param raw_qp_param = { 2359 .operation = MLX5_CMD_OP_2RST_QP 2360 }; 2361 2362 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2363 } 2364 if (err) 2365 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2366 base->mqp.qpn); 2367 } 2368 2369 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2370 &recv_cq); 2371 2372 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2373 mlx5_ib_lock_cqs(send_cq, recv_cq); 2374 /* del from lists under both locks above to protect reset flow paths */ 2375 list_del(&qp->qps_list); 2376 if (send_cq) 2377 list_del(&qp->cq_send_list); 2378 2379 if (recv_cq) 2380 list_del(&qp->cq_recv_list); 2381 2382 if (!udata) { 2383 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2384 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2385 if (send_cq != recv_cq) 2386 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2387 NULL); 2388 } 2389 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2390 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2391 2392 if (qp->type == IB_QPT_RAW_PACKET || 2393 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2394 destroy_raw_packet_qp(dev, qp); 2395 } else { 2396 err = mlx5_core_destroy_qp(dev, &base->mqp); 2397 if (err) 2398 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2399 base->mqp.qpn); 2400 } 2401 2402 destroy_qp(dev, qp, base, udata); 2403 } 2404 2405 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2406 struct mlx5_ib_qp *qp, 2407 struct mlx5_create_qp_params *params) 2408 { 2409 struct ib_qp_init_attr *attr = params->attr; 2410 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2411 u32 uidx = params->uidx; 2412 void *dctc; 2413 2414 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2415 return -EOPNOTSUPP; 2416 2417 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2418 if (!qp->dct.in) 2419 return -ENOMEM; 2420 2421 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2422 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2423 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2424 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2425 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2426 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2427 MLX5_SET(dctc, dctc, user_index, uidx); 2428 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2429 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2430 2431 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2432 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2433 2434 if (rcqe_sz == 128) 2435 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2436 } 2437 2438 qp->state = IB_QPS_RESET; 2439 2440 return 0; 2441 } 2442 2443 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2444 enum ib_qp_type *type) 2445 { 2446 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2447 goto out; 2448 2449 switch (attr->qp_type) { 2450 case IB_QPT_XRC_TGT: 2451 case IB_QPT_XRC_INI: 2452 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2453 goto out; 2454 fallthrough; 2455 case IB_QPT_RC: 2456 case IB_QPT_UC: 2457 case IB_QPT_SMI: 2458 case MLX5_IB_QPT_HW_GSI: 2459 case IB_QPT_DRIVER: 2460 case IB_QPT_GSI: 2461 if (dev->profile == &raw_eth_profile) 2462 goto out; 2463 case IB_QPT_RAW_PACKET: 2464 case IB_QPT_UD: 2465 case MLX5_IB_QPT_REG_UMR: 2466 break; 2467 default: 2468 goto out; 2469 } 2470 2471 *type = attr->qp_type; 2472 return 0; 2473 2474 out: 2475 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2476 return -EOPNOTSUPP; 2477 } 2478 2479 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2480 struct ib_qp_init_attr *attr, 2481 struct ib_udata *udata) 2482 { 2483 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2484 udata, struct mlx5_ib_ucontext, ibucontext); 2485 2486 if (!udata) { 2487 /* Kernel create_qp callers */ 2488 if (attr->rwq_ind_tbl) 2489 return -EOPNOTSUPP; 2490 2491 switch (attr->qp_type) { 2492 case IB_QPT_RAW_PACKET: 2493 case IB_QPT_DRIVER: 2494 return -EOPNOTSUPP; 2495 default: 2496 return 0; 2497 } 2498 } 2499 2500 /* Userspace create_qp callers */ 2501 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2502 mlx5_ib_dbg(dev, 2503 "Raw Packet QP is only supported for CQE version > 0\n"); 2504 return -EINVAL; 2505 } 2506 2507 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2508 mlx5_ib_dbg(dev, 2509 "Wrong QP type %d for the RWQ indirect table\n", 2510 attr->qp_type); 2511 return -EINVAL; 2512 } 2513 2514 /* 2515 * We don't need to see this warning, it means that kernel code 2516 * missing ib_pd. Placed here to catch developer's mistakes. 2517 */ 2518 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2519 "There is a missing PD pointer assignment\n"); 2520 return 0; 2521 } 2522 2523 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2524 bool cond, struct mlx5_ib_qp *qp) 2525 { 2526 if (!(*flags & flag)) 2527 return; 2528 2529 if (cond) { 2530 qp->flags_en |= flag; 2531 *flags &= ~flag; 2532 return; 2533 } 2534 2535 switch (flag) { 2536 case MLX5_QP_FLAG_SCATTER_CQE: 2537 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2538 /* 2539 * We don't return error if these flags were provided, 2540 * and mlx5 doesn't have right capability. 2541 */ 2542 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2543 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2544 return; 2545 default: 2546 break; 2547 } 2548 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2549 } 2550 2551 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2552 void *ucmd, struct ib_qp_init_attr *attr) 2553 { 2554 struct mlx5_core_dev *mdev = dev->mdev; 2555 bool cond; 2556 int flags; 2557 2558 if (attr->rwq_ind_tbl) 2559 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2560 else 2561 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2562 2563 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2564 case MLX5_QP_FLAG_TYPE_DCI: 2565 qp->type = MLX5_IB_QPT_DCI; 2566 break; 2567 case MLX5_QP_FLAG_TYPE_DCT: 2568 qp->type = MLX5_IB_QPT_DCT; 2569 break; 2570 default: 2571 if (qp->type != IB_QPT_DRIVER) 2572 break; 2573 /* 2574 * It is IB_QPT_DRIVER and or no subtype or 2575 * wrong subtype were provided. 2576 */ 2577 return -EINVAL; 2578 } 2579 2580 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2581 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2582 2583 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2584 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2585 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2586 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2587 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2588 2589 if (qp->type == IB_QPT_RAW_PACKET) { 2590 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2591 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2592 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2593 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2594 cond, qp); 2595 process_vendor_flag(dev, &flags, 2596 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2597 qp); 2598 process_vendor_flag(dev, &flags, 2599 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2600 qp); 2601 } 2602 2603 if (qp->type == IB_QPT_RC) 2604 process_vendor_flag(dev, &flags, 2605 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2606 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2607 2608 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2609 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2610 2611 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2612 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2613 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2614 if (attr->rwq_ind_tbl && cond) { 2615 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2616 cond); 2617 return -EINVAL; 2618 } 2619 2620 if (flags) 2621 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2622 2623 return (flags) ? -EINVAL : 0; 2624 } 2625 2626 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2627 bool cond, struct mlx5_ib_qp *qp) 2628 { 2629 if (!(*flags & flag)) 2630 return; 2631 2632 if (cond) { 2633 qp->flags |= flag; 2634 *flags &= ~flag; 2635 return; 2636 } 2637 2638 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2639 /* 2640 * Special case, if condition didn't meet, it won't be error, 2641 * just different in-kernel flow. 2642 */ 2643 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2644 return; 2645 } 2646 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2647 } 2648 2649 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2650 struct ib_qp_init_attr *attr) 2651 { 2652 enum ib_qp_type qp_type = qp->type; 2653 struct mlx5_core_dev *mdev = dev->mdev; 2654 int create_flags = attr->create_flags; 2655 bool cond; 2656 2657 if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile) 2658 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST) 2659 return -EINVAL; 2660 2661 if (qp_type == MLX5_IB_QPT_DCT) 2662 return (create_flags) ? -EINVAL : 0; 2663 2664 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2665 return (create_flags) ? -EINVAL : 0; 2666 2667 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2668 mlx5_get_flow_namespace(dev->mdev, 2669 MLX5_FLOW_NAMESPACE_BYPASS), 2670 qp); 2671 process_create_flag(dev, &create_flags, 2672 IB_QP_CREATE_INTEGRITY_EN, 2673 MLX5_CAP_GEN(mdev, sho), qp); 2674 process_create_flag(dev, &create_flags, 2675 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2676 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2677 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2678 MLX5_CAP_GEN(mdev, cd), qp); 2679 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2680 MLX5_CAP_GEN(mdev, cd), qp); 2681 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2682 MLX5_CAP_GEN(mdev, cd), qp); 2683 2684 if (qp_type == IB_QPT_UD) { 2685 process_create_flag(dev, &create_flags, 2686 IB_QP_CREATE_IPOIB_UD_LSO, 2687 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2688 qp); 2689 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2690 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 2691 cond, qp); 2692 } 2693 2694 if (qp_type == IB_QPT_RAW_PACKET) { 2695 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2696 MLX5_CAP_ETH(mdev, scatter_fcs); 2697 process_create_flag(dev, &create_flags, 2698 IB_QP_CREATE_SCATTER_FCS, cond, qp); 2699 2700 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2701 MLX5_CAP_ETH(mdev, vlan_cap); 2702 process_create_flag(dev, &create_flags, 2703 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 2704 } 2705 2706 process_create_flag(dev, &create_flags, 2707 IB_QP_CREATE_PCI_WRITE_END_PADDING, 2708 MLX5_CAP_GEN(mdev, end_pad), qp); 2709 2710 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 2711 qp_type != MLX5_IB_QPT_REG_UMR, qp); 2712 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 2713 true, qp); 2714 2715 if (create_flags) 2716 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 2717 create_flags); 2718 2719 return (create_flags) ? -EINVAL : 0; 2720 } 2721 2722 static int process_udata_size(struct mlx5_ib_dev *dev, 2723 struct mlx5_create_qp_params *params) 2724 { 2725 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 2726 struct ib_udata *udata = params->udata; 2727 size_t outlen = udata->outlen; 2728 size_t inlen = udata->inlen; 2729 2730 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 2731 params->ucmd_size = ucmd; 2732 if (!params->is_rss_raw) { 2733 /* User has old rdma-core, which doesn't support ECE */ 2734 size_t min_inlen = 2735 offsetof(struct mlx5_ib_create_qp, ece_options); 2736 2737 /* 2738 * We will check in check_ucmd_data() that user 2739 * cleared everything after inlen. 2740 */ 2741 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 2742 goto out; 2743 } 2744 2745 /* RSS RAW QP */ 2746 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 2747 return -EINVAL; 2748 2749 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 2750 return -EINVAL; 2751 2752 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 2753 params->ucmd_size = ucmd; 2754 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 2755 return -EINVAL; 2756 2757 params->inlen = min(ucmd, inlen); 2758 out: 2759 if (!params->inlen) 2760 mlx5_ib_dbg(dev, "udata is too small\n"); 2761 2762 return (params->inlen) ? 0 : -EINVAL; 2763 } 2764 2765 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2766 struct mlx5_ib_qp *qp, 2767 struct mlx5_create_qp_params *params) 2768 { 2769 int err; 2770 2771 if (params->is_rss_raw) { 2772 err = create_rss_raw_qp_tir(dev, pd, qp, params); 2773 goto out; 2774 } 2775 2776 switch (qp->type) { 2777 case MLX5_IB_QPT_DCT: 2778 err = create_dct(dev, pd, qp, params); 2779 break; 2780 case IB_QPT_XRC_TGT: 2781 err = create_xrc_tgt_qp(dev, qp, params); 2782 break; 2783 case IB_QPT_GSI: 2784 err = mlx5_ib_create_gsi(pd, qp, params->attr); 2785 break; 2786 default: 2787 if (params->udata) 2788 err = create_user_qp(dev, pd, qp, params); 2789 else 2790 err = create_kernel_qp(dev, pd, qp, params); 2791 } 2792 2793 out: 2794 if (err) { 2795 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 2796 return err; 2797 } 2798 2799 if (is_qp0(qp->type)) 2800 qp->ibqp.qp_num = 0; 2801 else if (is_qp1(qp->type)) 2802 qp->ibqp.qp_num = 1; 2803 else 2804 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2805 2806 mlx5_ib_dbg(dev, 2807 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 2808 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2809 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 2810 -1, 2811 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 2812 -1, 2813 params->resp.ece_options); 2814 2815 return 0; 2816 } 2817 2818 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2819 struct ib_qp_init_attr *attr) 2820 { 2821 int ret = 0; 2822 2823 switch (qp->type) { 2824 case MLX5_IB_QPT_DCT: 2825 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 2826 break; 2827 case MLX5_IB_QPT_DCI: 2828 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 2829 -EINVAL : 2830 0; 2831 break; 2832 case IB_QPT_RAW_PACKET: 2833 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 2834 break; 2835 default: 2836 break; 2837 } 2838 2839 if (ret) 2840 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 2841 2842 return ret; 2843 } 2844 2845 static int get_qp_uidx(struct mlx5_ib_qp *qp, 2846 struct mlx5_create_qp_params *params) 2847 { 2848 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2849 struct ib_udata *udata = params->udata; 2850 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2851 udata, struct mlx5_ib_ucontext, ibucontext); 2852 2853 if (params->is_rss_raw) 2854 return 0; 2855 2856 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 2857 } 2858 2859 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2860 { 2861 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2862 2863 if (mqp->state == IB_QPS_RTR) { 2864 int err; 2865 2866 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 2867 if (err) { 2868 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2869 return err; 2870 } 2871 } 2872 2873 kfree(mqp->dct.in); 2874 kfree(mqp); 2875 return 0; 2876 } 2877 2878 static int check_ucmd_data(struct mlx5_ib_dev *dev, 2879 struct mlx5_create_qp_params *params) 2880 { 2881 struct ib_udata *udata = params->udata; 2882 size_t size, last; 2883 int ret; 2884 2885 if (params->is_rss_raw) 2886 /* 2887 * These QPs don't have "reserved" field in their 2888 * create_qp input struct, so their data is always valid. 2889 */ 2890 last = sizeof(struct mlx5_ib_create_qp_rss); 2891 else 2892 last = offsetof(struct mlx5_ib_create_qp, reserved); 2893 2894 if (udata->inlen <= last) 2895 return 0; 2896 2897 /* 2898 * User provides different create_qp structures based on the 2899 * flow and we need to know if he cleared memory after our 2900 * struct create_qp ends. 2901 */ 2902 size = udata->inlen - last; 2903 ret = ib_is_udata_cleared(params->udata, last, size); 2904 if (!ret) 2905 mlx5_ib_dbg( 2906 dev, 2907 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 2908 udata->inlen, params->ucmd_size, last, size); 2909 return ret ? 0 : -EINVAL; 2910 } 2911 2912 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr, 2913 struct ib_udata *udata) 2914 { 2915 struct mlx5_create_qp_params params = {}; 2916 struct mlx5_ib_dev *dev; 2917 struct mlx5_ib_qp *qp; 2918 enum ib_qp_type type; 2919 int err; 2920 2921 dev = pd ? to_mdev(pd->device) : 2922 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device); 2923 2924 err = check_qp_type(dev, attr, &type); 2925 if (err) 2926 return ERR_PTR(err); 2927 2928 err = check_valid_flow(dev, pd, attr, udata); 2929 if (err) 2930 return ERR_PTR(err); 2931 2932 params.udata = udata; 2933 params.uidx = MLX5_IB_DEFAULT_UIDX; 2934 params.attr = attr; 2935 params.is_rss_raw = !!attr->rwq_ind_tbl; 2936 2937 if (udata) { 2938 err = process_udata_size(dev, ¶ms); 2939 if (err) 2940 return ERR_PTR(err); 2941 2942 err = check_ucmd_data(dev, ¶ms); 2943 if (err) 2944 return ERR_PTR(err); 2945 2946 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 2947 if (!params.ucmd) 2948 return ERR_PTR(-ENOMEM); 2949 2950 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 2951 if (err) 2952 goto free_ucmd; 2953 } 2954 2955 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2956 if (!qp) { 2957 err = -ENOMEM; 2958 goto free_ucmd; 2959 } 2960 2961 mutex_init(&qp->mutex); 2962 qp->type = type; 2963 if (udata) { 2964 err = process_vendor_flags(dev, qp, params.ucmd, attr); 2965 if (err) 2966 goto free_qp; 2967 2968 err = get_qp_uidx(qp, ¶ms); 2969 if (err) 2970 goto free_qp; 2971 } 2972 err = process_create_flags(dev, qp, attr); 2973 if (err) 2974 goto free_qp; 2975 2976 err = check_qp_attr(dev, qp, attr); 2977 if (err) 2978 goto free_qp; 2979 2980 err = create_qp(dev, pd, qp, ¶ms); 2981 if (err) 2982 goto free_qp; 2983 2984 kfree(params.ucmd); 2985 params.ucmd = NULL; 2986 2987 if (udata) 2988 /* 2989 * It is safe to copy response for all user create QP flows, 2990 * including MLX5_IB_QPT_DCT, which doesn't need it. 2991 * In that case, resp will be filled with zeros. 2992 */ 2993 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 2994 if (err) 2995 goto destroy_qp; 2996 2997 return &qp->ibqp; 2998 2999 destroy_qp: 3000 switch (qp->type) { 3001 case MLX5_IB_QPT_DCT: 3002 mlx5_ib_destroy_dct(qp); 3003 break; 3004 case IB_QPT_GSI: 3005 mlx5_ib_destroy_gsi(qp); 3006 break; 3007 default: 3008 /* 3009 * These lines below are temp solution till QP allocation 3010 * will be moved to be under IB/core responsiblity. 3011 */ 3012 qp->ibqp.send_cq = attr->send_cq; 3013 qp->ibqp.recv_cq = attr->recv_cq; 3014 qp->ibqp.pd = pd; 3015 destroy_qp_common(dev, qp, udata); 3016 } 3017 3018 qp = NULL; 3019 free_qp: 3020 kfree(qp); 3021 free_ucmd: 3022 kfree(params.ucmd); 3023 return ERR_PTR(err); 3024 } 3025 3026 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3027 { 3028 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3029 struct mlx5_ib_qp *mqp = to_mqp(qp); 3030 3031 if (unlikely(qp->qp_type == IB_QPT_GSI)) 3032 return mlx5_ib_destroy_gsi(mqp); 3033 3034 if (mqp->type == MLX5_IB_QPT_DCT) 3035 return mlx5_ib_destroy_dct(mqp); 3036 3037 destroy_qp_common(dev, mqp, udata); 3038 3039 kfree(mqp); 3040 3041 return 0; 3042 } 3043 3044 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3045 const struct ib_qp_attr *attr, int attr_mask, 3046 void *qpc) 3047 { 3048 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3049 u8 dest_rd_atomic; 3050 u32 access_flags; 3051 3052 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3053 dest_rd_atomic = attr->max_dest_rd_atomic; 3054 else 3055 dest_rd_atomic = qp->trans_qp.resp_depth; 3056 3057 if (attr_mask & IB_QP_ACCESS_FLAGS) 3058 access_flags = attr->qp_access_flags; 3059 else 3060 access_flags = qp->trans_qp.atomic_rd_en; 3061 3062 if (!dest_rd_atomic) 3063 access_flags &= IB_ACCESS_REMOTE_WRITE; 3064 3065 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3066 3067 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3068 int atomic_mode; 3069 3070 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 3071 if (atomic_mode < 0) 3072 return -EOPNOTSUPP; 3073 3074 MLX5_SET(qpc, qpc, rae, 1); 3075 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3076 } 3077 3078 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3079 return 0; 3080 } 3081 3082 enum { 3083 MLX5_PATH_FLAG_FL = 1 << 0, 3084 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3085 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3086 }; 3087 3088 static int ib_to_mlx5_rate_map(u8 rate) 3089 { 3090 switch (rate) { 3091 case IB_RATE_PORT_CURRENT: 3092 return 0; 3093 case IB_RATE_56_GBPS: 3094 return 1; 3095 case IB_RATE_25_GBPS: 3096 return 2; 3097 case IB_RATE_100_GBPS: 3098 return 3; 3099 case IB_RATE_200_GBPS: 3100 return 4; 3101 case IB_RATE_50_GBPS: 3102 return 5; 3103 default: 3104 return rate + MLX5_STAT_RATE_OFFSET; 3105 }; 3106 3107 return 0; 3108 } 3109 3110 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3111 { 3112 u32 stat_rate_support; 3113 3114 if (rate == IB_RATE_PORT_CURRENT) 3115 return 0; 3116 3117 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3118 return -EINVAL; 3119 3120 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3121 while (rate != IB_RATE_PORT_CURRENT && 3122 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3123 --rate; 3124 3125 return ib_to_mlx5_rate_map(rate); 3126 } 3127 3128 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3129 struct mlx5_ib_sq *sq, u8 sl, 3130 struct ib_pd *pd) 3131 { 3132 void *in; 3133 void *tisc; 3134 int inlen; 3135 int err; 3136 3137 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3138 in = kvzalloc(inlen, GFP_KERNEL); 3139 if (!in) 3140 return -ENOMEM; 3141 3142 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3143 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3144 3145 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3146 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3147 3148 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3149 3150 kvfree(in); 3151 3152 return err; 3153 } 3154 3155 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3156 struct mlx5_ib_sq *sq, u8 tx_affinity, 3157 struct ib_pd *pd) 3158 { 3159 void *in; 3160 void *tisc; 3161 int inlen; 3162 int err; 3163 3164 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3165 in = kvzalloc(inlen, GFP_KERNEL); 3166 if (!in) 3167 return -ENOMEM; 3168 3169 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3170 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3171 3172 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3173 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3174 3175 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3176 3177 kvfree(in); 3178 3179 return err; 3180 } 3181 3182 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3183 u32 lqpn, u32 rqpn) 3184 3185 { 3186 u32 fl = ah->grh.flow_label; 3187 3188 if (!fl) 3189 fl = rdma_calc_flow_label(lqpn, rqpn); 3190 3191 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3192 } 3193 3194 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3195 const struct rdma_ah_attr *ah, void *path, u8 port, 3196 int attr_mask, u32 path_flags, 3197 const struct ib_qp_attr *attr, bool alt) 3198 { 3199 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3200 int err; 3201 enum ib_gid_type gid_type; 3202 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3203 u8 sl = rdma_ah_get_sl(ah); 3204 3205 if (attr_mask & IB_QP_PKEY_INDEX) 3206 MLX5_SET(ads, path, pkey_index, 3207 alt ? attr->alt_pkey_index : attr->pkey_index); 3208 3209 if (ah_flags & IB_AH_GRH) { 3210 if (grh->sgid_index >= 3211 dev->mdev->port_caps[port - 1].gid_table_len) { 3212 pr_err("sgid_index (%u) too large. max is %d\n", 3213 grh->sgid_index, 3214 dev->mdev->port_caps[port - 1].gid_table_len); 3215 return -EINVAL; 3216 } 3217 } 3218 3219 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3220 if (!(ah_flags & IB_AH_GRH)) 3221 return -EINVAL; 3222 3223 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3224 ah->roce.dmac); 3225 if ((qp->ibqp.qp_type == IB_QPT_RC || 3226 qp->ibqp.qp_type == IB_QPT_UC || 3227 qp->ibqp.qp_type == IB_QPT_XRC_INI || 3228 qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 3229 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3230 (attr_mask & IB_QP_DEST_QPN)) 3231 mlx5_set_path_udp_sport(path, ah, 3232 qp->ibqp.qp_num, 3233 attr->dest_qp_num); 3234 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3235 gid_type = ah->grh.sgid_attr->gid_type; 3236 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3237 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3238 } else { 3239 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3240 MLX5_SET(ads, path, free_ar, 3241 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3242 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3243 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3244 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3245 MLX5_SET(ads, path, sl, sl); 3246 } 3247 3248 if (ah_flags & IB_AH_GRH) { 3249 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3250 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3251 MLX5_SET(ads, path, tclass, grh->traffic_class); 3252 MLX5_SET(ads, path, flow_label, grh->flow_label); 3253 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3254 sizeof(grh->dgid.raw)); 3255 } 3256 3257 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3258 if (err < 0) 3259 return err; 3260 MLX5_SET(ads, path, stat_rate, err); 3261 MLX5_SET(ads, path, vhca_port_num, port); 3262 3263 if (attr_mask & IB_QP_TIMEOUT) 3264 MLX5_SET(ads, path, ack_timeout, 3265 alt ? attr->alt_timeout : attr->timeout); 3266 3267 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3268 return modify_raw_packet_eth_prio(dev->mdev, 3269 &qp->raw_packet_qp.sq, 3270 sl & 0xf, qp->ibqp.pd); 3271 3272 return 0; 3273 } 3274 3275 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3276 [MLX5_QP_STATE_INIT] = { 3277 [MLX5_QP_STATE_INIT] = { 3278 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3279 MLX5_QP_OPTPAR_RAE | 3280 MLX5_QP_OPTPAR_RWE | 3281 MLX5_QP_OPTPAR_PKEY_INDEX | 3282 MLX5_QP_OPTPAR_PRI_PORT | 3283 MLX5_QP_OPTPAR_LAG_TX_AFF, 3284 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3285 MLX5_QP_OPTPAR_PKEY_INDEX | 3286 MLX5_QP_OPTPAR_PRI_PORT | 3287 MLX5_QP_OPTPAR_LAG_TX_AFF, 3288 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3289 MLX5_QP_OPTPAR_Q_KEY | 3290 MLX5_QP_OPTPAR_PRI_PORT, 3291 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3292 MLX5_QP_OPTPAR_RAE | 3293 MLX5_QP_OPTPAR_RWE | 3294 MLX5_QP_OPTPAR_PKEY_INDEX | 3295 MLX5_QP_OPTPAR_PRI_PORT | 3296 MLX5_QP_OPTPAR_LAG_TX_AFF, 3297 }, 3298 [MLX5_QP_STATE_RTR] = { 3299 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3300 MLX5_QP_OPTPAR_RRE | 3301 MLX5_QP_OPTPAR_RAE | 3302 MLX5_QP_OPTPAR_RWE | 3303 MLX5_QP_OPTPAR_PKEY_INDEX | 3304 MLX5_QP_OPTPAR_LAG_TX_AFF, 3305 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3306 MLX5_QP_OPTPAR_RWE | 3307 MLX5_QP_OPTPAR_PKEY_INDEX | 3308 MLX5_QP_OPTPAR_LAG_TX_AFF, 3309 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3310 MLX5_QP_OPTPAR_Q_KEY, 3311 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3312 MLX5_QP_OPTPAR_Q_KEY, 3313 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3314 MLX5_QP_OPTPAR_RRE | 3315 MLX5_QP_OPTPAR_RAE | 3316 MLX5_QP_OPTPAR_RWE | 3317 MLX5_QP_OPTPAR_PKEY_INDEX | 3318 MLX5_QP_OPTPAR_LAG_TX_AFF, 3319 }, 3320 }, 3321 [MLX5_QP_STATE_RTR] = { 3322 [MLX5_QP_STATE_RTS] = { 3323 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3324 MLX5_QP_OPTPAR_RRE | 3325 MLX5_QP_OPTPAR_RAE | 3326 MLX5_QP_OPTPAR_RWE | 3327 MLX5_QP_OPTPAR_PM_STATE | 3328 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3329 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3330 MLX5_QP_OPTPAR_RWE | 3331 MLX5_QP_OPTPAR_PM_STATE, 3332 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3333 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3334 MLX5_QP_OPTPAR_RRE | 3335 MLX5_QP_OPTPAR_RAE | 3336 MLX5_QP_OPTPAR_RWE | 3337 MLX5_QP_OPTPAR_PM_STATE | 3338 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3339 }, 3340 }, 3341 [MLX5_QP_STATE_RTS] = { 3342 [MLX5_QP_STATE_RTS] = { 3343 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3344 MLX5_QP_OPTPAR_RAE | 3345 MLX5_QP_OPTPAR_RWE | 3346 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3347 MLX5_QP_OPTPAR_PM_STATE | 3348 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3349 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3350 MLX5_QP_OPTPAR_PM_STATE | 3351 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3352 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3353 MLX5_QP_OPTPAR_SRQN | 3354 MLX5_QP_OPTPAR_CQN_RCV, 3355 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3356 MLX5_QP_OPTPAR_RAE | 3357 MLX5_QP_OPTPAR_RWE | 3358 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3359 MLX5_QP_OPTPAR_PM_STATE | 3360 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3361 }, 3362 }, 3363 [MLX5_QP_STATE_SQER] = { 3364 [MLX5_QP_STATE_RTS] = { 3365 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3366 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3367 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3368 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3369 MLX5_QP_OPTPAR_RWE | 3370 MLX5_QP_OPTPAR_RAE | 3371 MLX5_QP_OPTPAR_RRE, 3372 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3373 MLX5_QP_OPTPAR_RWE | 3374 MLX5_QP_OPTPAR_RAE | 3375 MLX5_QP_OPTPAR_RRE, 3376 }, 3377 }, 3378 }; 3379 3380 static int ib_nr_to_mlx5_nr(int ib_mask) 3381 { 3382 switch (ib_mask) { 3383 case IB_QP_STATE: 3384 return 0; 3385 case IB_QP_CUR_STATE: 3386 return 0; 3387 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3388 return 0; 3389 case IB_QP_ACCESS_FLAGS: 3390 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3391 MLX5_QP_OPTPAR_RAE; 3392 case IB_QP_PKEY_INDEX: 3393 return MLX5_QP_OPTPAR_PKEY_INDEX; 3394 case IB_QP_PORT: 3395 return MLX5_QP_OPTPAR_PRI_PORT; 3396 case IB_QP_QKEY: 3397 return MLX5_QP_OPTPAR_Q_KEY; 3398 case IB_QP_AV: 3399 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3400 MLX5_QP_OPTPAR_PRI_PORT; 3401 case IB_QP_PATH_MTU: 3402 return 0; 3403 case IB_QP_TIMEOUT: 3404 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3405 case IB_QP_RETRY_CNT: 3406 return MLX5_QP_OPTPAR_RETRY_COUNT; 3407 case IB_QP_RNR_RETRY: 3408 return MLX5_QP_OPTPAR_RNR_RETRY; 3409 case IB_QP_RQ_PSN: 3410 return 0; 3411 case IB_QP_MAX_QP_RD_ATOMIC: 3412 return MLX5_QP_OPTPAR_SRA_MAX; 3413 case IB_QP_ALT_PATH: 3414 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3415 case IB_QP_MIN_RNR_TIMER: 3416 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3417 case IB_QP_SQ_PSN: 3418 return 0; 3419 case IB_QP_MAX_DEST_RD_ATOMIC: 3420 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3421 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3422 case IB_QP_PATH_MIG_STATE: 3423 return MLX5_QP_OPTPAR_PM_STATE; 3424 case IB_QP_CAP: 3425 return 0; 3426 case IB_QP_DEST_QPN: 3427 return 0; 3428 } 3429 return 0; 3430 } 3431 3432 static int ib_mask_to_mlx5_opt(int ib_mask) 3433 { 3434 int result = 0; 3435 int i; 3436 3437 for (i = 0; i < 8 * sizeof(int); i++) { 3438 if ((1 << i) & ib_mask) 3439 result |= ib_nr_to_mlx5_nr(1 << i); 3440 } 3441 3442 return result; 3443 } 3444 3445 static int modify_raw_packet_qp_rq( 3446 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3447 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3448 { 3449 void *in; 3450 void *rqc; 3451 int inlen; 3452 int err; 3453 3454 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3455 in = kvzalloc(inlen, GFP_KERNEL); 3456 if (!in) 3457 return -ENOMEM; 3458 3459 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3460 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3461 3462 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3463 MLX5_SET(rqc, rqc, state, new_state); 3464 3465 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3466 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3467 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3468 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3469 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3470 } else 3471 dev_info_once( 3472 &dev->ib_dev.dev, 3473 "RAW PACKET QP counters are not supported on current FW\n"); 3474 } 3475 3476 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3477 if (err) 3478 goto out; 3479 3480 rq->state = new_state; 3481 3482 out: 3483 kvfree(in); 3484 return err; 3485 } 3486 3487 static int modify_raw_packet_qp_sq( 3488 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3489 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3490 { 3491 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3492 struct mlx5_rate_limit old_rl = ibqp->rl; 3493 struct mlx5_rate_limit new_rl = old_rl; 3494 bool new_rate_added = false; 3495 u16 rl_index = 0; 3496 void *in; 3497 void *sqc; 3498 int inlen; 3499 int err; 3500 3501 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3502 in = kvzalloc(inlen, GFP_KERNEL); 3503 if (!in) 3504 return -ENOMEM; 3505 3506 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3507 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3508 3509 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3510 MLX5_SET(sqc, sqc, state, new_state); 3511 3512 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3513 if (new_state != MLX5_SQC_STATE_RDY) 3514 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3515 __func__); 3516 else 3517 new_rl = raw_qp_param->rl; 3518 } 3519 3520 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3521 if (new_rl.rate) { 3522 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3523 if (err) { 3524 pr_err("Failed configuring rate limit(err %d): \ 3525 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3526 err, new_rl.rate, new_rl.max_burst_sz, 3527 new_rl.typical_pkt_sz); 3528 3529 goto out; 3530 } 3531 new_rate_added = true; 3532 } 3533 3534 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3535 /* index 0 means no limit */ 3536 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3537 } 3538 3539 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3540 if (err) { 3541 /* Remove new rate from table if failed */ 3542 if (new_rate_added) 3543 mlx5_rl_remove_rate(dev, &new_rl); 3544 goto out; 3545 } 3546 3547 /* Only remove the old rate after new rate was set */ 3548 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3549 (new_state != MLX5_SQC_STATE_RDY)) { 3550 mlx5_rl_remove_rate(dev, &old_rl); 3551 if (new_state != MLX5_SQC_STATE_RDY) 3552 memset(&new_rl, 0, sizeof(new_rl)); 3553 } 3554 3555 ibqp->rl = new_rl; 3556 sq->state = new_state; 3557 3558 out: 3559 kvfree(in); 3560 return err; 3561 } 3562 3563 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3564 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3565 u8 tx_affinity) 3566 { 3567 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3568 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3569 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3570 int modify_rq = !!qp->rq.wqe_cnt; 3571 int modify_sq = !!qp->sq.wqe_cnt; 3572 int rq_state; 3573 int sq_state; 3574 int err; 3575 3576 switch (raw_qp_param->operation) { 3577 case MLX5_CMD_OP_RST2INIT_QP: 3578 rq_state = MLX5_RQC_STATE_RDY; 3579 sq_state = MLX5_SQC_STATE_RST; 3580 break; 3581 case MLX5_CMD_OP_2ERR_QP: 3582 rq_state = MLX5_RQC_STATE_ERR; 3583 sq_state = MLX5_SQC_STATE_ERR; 3584 break; 3585 case MLX5_CMD_OP_2RST_QP: 3586 rq_state = MLX5_RQC_STATE_RST; 3587 sq_state = MLX5_SQC_STATE_RST; 3588 break; 3589 case MLX5_CMD_OP_RTR2RTS_QP: 3590 case MLX5_CMD_OP_RTS2RTS_QP: 3591 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3592 return -EINVAL; 3593 3594 modify_rq = 0; 3595 sq_state = MLX5_SQC_STATE_RDY; 3596 break; 3597 case MLX5_CMD_OP_INIT2INIT_QP: 3598 case MLX5_CMD_OP_INIT2RTR_QP: 3599 if (raw_qp_param->set_mask) 3600 return -EINVAL; 3601 else 3602 return 0; 3603 default: 3604 WARN_ON(1); 3605 return -EINVAL; 3606 } 3607 3608 if (modify_rq) { 3609 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3610 qp->ibqp.pd); 3611 if (err) 3612 return err; 3613 } 3614 3615 if (modify_sq) { 3616 struct mlx5_flow_handle *flow_rule; 3617 3618 if (tx_affinity) { 3619 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3620 tx_affinity, 3621 qp->ibqp.pd); 3622 if (err) 3623 return err; 3624 } 3625 3626 flow_rule = create_flow_rule_vport_sq(dev, sq, 3627 raw_qp_param->port); 3628 if (IS_ERR(flow_rule)) 3629 return PTR_ERR(flow_rule); 3630 3631 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3632 raw_qp_param, qp->ibqp.pd); 3633 if (err) { 3634 if (flow_rule) 3635 mlx5_del_flow_rules(flow_rule); 3636 return err; 3637 } 3638 3639 if (flow_rule) { 3640 destroy_flow_rule_vport_sq(sq); 3641 sq->flow_rule = flow_rule; 3642 } 3643 3644 return err; 3645 } 3646 3647 return 0; 3648 } 3649 3650 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3651 struct ib_udata *udata) 3652 { 3653 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3654 udata, struct mlx5_ib_ucontext, ibucontext); 3655 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3656 atomic_t *tx_port_affinity; 3657 3658 if (ucontext) 3659 tx_port_affinity = &ucontext->tx_port_affinity; 3660 else 3661 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3662 3663 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3664 MLX5_MAX_PORTS + 1; 3665 } 3666 3667 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3668 { 3669 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3670 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3671 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3672 (qp->type == MLX5_IB_QPT_DCI)) 3673 return true; 3674 return false; 3675 } 3676 3677 static unsigned int get_tx_affinity(struct ib_qp *qp, 3678 const struct ib_qp_attr *attr, 3679 int attr_mask, u8 init, 3680 struct ib_udata *udata) 3681 { 3682 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3683 udata, struct mlx5_ib_ucontext, ibucontext); 3684 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3685 struct mlx5_ib_qp *mqp = to_mqp(qp); 3686 struct mlx5_ib_qp_base *qp_base; 3687 unsigned int tx_affinity; 3688 3689 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 3690 qp_supports_affinity(mqp))) 3691 return 0; 3692 3693 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3694 tx_affinity = mqp->gsi_lag_port; 3695 else if (init) 3696 tx_affinity = get_tx_affinity_rr(dev, udata); 3697 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 3698 tx_affinity = 3699 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 3700 else 3701 return 0; 3702 3703 qp_base = &mqp->trans_qp.base; 3704 if (ucontext) 3705 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3706 tx_affinity, qp_base->mqp.qpn, ucontext); 3707 else 3708 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3709 tx_affinity, qp_base->mqp.qpn); 3710 return tx_affinity; 3711 } 3712 3713 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3714 struct rdma_counter *counter) 3715 { 3716 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3717 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 3718 struct mlx5_ib_qp *mqp = to_mqp(qp); 3719 struct mlx5_ib_qp_base *base; 3720 u32 set_id; 3721 u32 *qpc; 3722 3723 if (counter) 3724 set_id = counter->id; 3725 else 3726 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3727 3728 base = &mqp->trans_qp.base; 3729 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 3730 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 3731 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 3732 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 3733 MLX5_QP_OPTPAR_COUNTER_SET_ID); 3734 3735 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 3736 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3737 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 3738 } 3739 3740 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3741 const struct ib_qp_attr *attr, int attr_mask, 3742 enum ib_qp_state cur_state, 3743 enum ib_qp_state new_state, 3744 const struct mlx5_ib_modify_qp *ucmd, 3745 struct mlx5_ib_modify_qp_resp *resp, 3746 struct ib_udata *udata) 3747 { 3748 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3749 [MLX5_QP_STATE_RST] = { 3750 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3751 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3752 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3753 }, 3754 [MLX5_QP_STATE_INIT] = { 3755 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3756 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3757 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3758 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3759 }, 3760 [MLX5_QP_STATE_RTR] = { 3761 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3762 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3763 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3764 }, 3765 [MLX5_QP_STATE_RTS] = { 3766 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3767 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3768 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3769 }, 3770 [MLX5_QP_STATE_SQD] = { 3771 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3772 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3773 }, 3774 [MLX5_QP_STATE_SQER] = { 3775 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3776 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3777 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3778 }, 3779 [MLX5_QP_STATE_ERR] = { 3780 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3781 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3782 } 3783 }; 3784 3785 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3786 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3787 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3788 struct mlx5_ib_cq *send_cq, *recv_cq; 3789 struct mlx5_ib_pd *pd; 3790 enum mlx5_qp_state mlx5_cur, mlx5_new; 3791 void *qpc, *pri_path, *alt_path; 3792 enum mlx5_qp_optpar optpar = 0; 3793 u32 set_id = 0; 3794 int mlx5_st; 3795 int err; 3796 u16 op; 3797 u8 tx_affinity = 0; 3798 3799 mlx5_st = to_mlx5_st(qp->type); 3800 if (mlx5_st < 0) 3801 return -EINVAL; 3802 3803 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 3804 if (!qpc) 3805 return -ENOMEM; 3806 3807 pd = to_mpd(qp->ibqp.pd); 3808 MLX5_SET(qpc, qpc, st, mlx5_st); 3809 3810 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3811 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3812 } else { 3813 switch (attr->path_mig_state) { 3814 case IB_MIG_MIGRATED: 3815 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3816 break; 3817 case IB_MIG_REARM: 3818 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 3819 break; 3820 case IB_MIG_ARMED: 3821 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 3822 break; 3823 } 3824 } 3825 3826 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 3827 cur_state == IB_QPS_RESET && 3828 new_state == IB_QPS_INIT, udata); 3829 3830 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 3831 if (tx_affinity && new_state == IB_QPS_RTR && 3832 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 3833 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 3834 3835 if (is_sqp(ibqp->qp_type)) { 3836 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 3837 MLX5_SET(qpc, qpc, log_msg_max, 8); 3838 } else if ((ibqp->qp_type == IB_QPT_UD && 3839 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 3840 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3841 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 3842 MLX5_SET(qpc, qpc, log_msg_max, 12); 3843 } else if (attr_mask & IB_QP_PATH_MTU) { 3844 if (attr->path_mtu < IB_MTU_256 || 3845 attr->path_mtu > IB_MTU_4096) { 3846 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3847 err = -EINVAL; 3848 goto out; 3849 } 3850 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 3851 MLX5_SET(qpc, qpc, log_msg_max, 3852 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 3853 } 3854 3855 if (attr_mask & IB_QP_DEST_QPN) 3856 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 3857 3858 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 3859 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 3860 3861 if (attr_mask & IB_QP_PKEY_INDEX) 3862 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 3863 3864 /* todo implement counter_index functionality */ 3865 3866 if (is_sqp(ibqp->qp_type)) 3867 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 3868 3869 if (attr_mask & IB_QP_PORT) 3870 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 3871 3872 if (attr_mask & IB_QP_AV) { 3873 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 3874 attr_mask & IB_QP_PORT ? attr->port_num : 3875 qp->port, 3876 attr_mask, 0, attr, false); 3877 if (err) 3878 goto out; 3879 } 3880 3881 if (attr_mask & IB_QP_TIMEOUT) 3882 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 3883 3884 if (attr_mask & IB_QP_ALT_PATH) { 3885 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 3886 attr->alt_port_num, 3887 attr_mask | IB_QP_PKEY_INDEX | 3888 IB_QP_TIMEOUT, 3889 0, attr, true); 3890 if (err) 3891 goto out; 3892 } 3893 3894 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3895 &send_cq, &recv_cq); 3896 3897 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3898 if (send_cq) 3899 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 3900 if (recv_cq) 3901 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 3902 3903 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 3904 3905 if (attr_mask & IB_QP_RNR_RETRY) 3906 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 3907 3908 if (attr_mask & IB_QP_RETRY_CNT) 3909 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 3910 3911 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 3912 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 3913 3914 if (attr_mask & IB_QP_SQ_PSN) 3915 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 3916 3917 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 3918 MLX5_SET(qpc, qpc, log_rra_max, 3919 ilog2(attr->max_dest_rd_atomic)); 3920 3921 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3922 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 3923 if (err) 3924 goto out; 3925 } 3926 3927 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3928 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 3929 3930 if (attr_mask & IB_QP_RQ_PSN) 3931 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 3932 3933 if (attr_mask & IB_QP_QKEY) 3934 MLX5_SET(qpc, qpc, q_key, attr->qkey); 3935 3936 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3937 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 3938 3939 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3940 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3941 qp->port) - 1; 3942 3943 /* Underlay port should be used - index 0 function per port */ 3944 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 3945 port_num = 0; 3946 3947 if (ibqp->counter) 3948 set_id = ibqp->counter->id; 3949 else 3950 set_id = mlx5_ib_get_counters_id(dev, port_num); 3951 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3952 } 3953 3954 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3955 MLX5_SET(qpc, qpc, rlky, 1); 3956 3957 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3958 MLX5_SET(qpc, qpc, deth_sqpn, 1); 3959 3960 mlx5_cur = to_mlx5_state(cur_state); 3961 mlx5_new = to_mlx5_state(new_state); 3962 3963 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3964 !optab[mlx5_cur][mlx5_new]) { 3965 err = -EINVAL; 3966 goto out; 3967 } 3968 3969 op = optab[mlx5_cur][mlx5_new]; 3970 optpar |= ib_mask_to_mlx5_opt(attr_mask); 3971 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3972 3973 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3974 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 3975 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3976 3977 raw_qp_param.operation = op; 3978 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3979 raw_qp_param.rq_q_ctr_id = set_id; 3980 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3981 } 3982 3983 if (attr_mask & IB_QP_PORT) 3984 raw_qp_param.port = attr->port_num; 3985 3986 if (attr_mask & IB_QP_RATE_LIMIT) { 3987 raw_qp_param.rl.rate = attr->rate_limit; 3988 3989 if (ucmd->burst_info.max_burst_sz) { 3990 if (attr->rate_limit && 3991 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3992 raw_qp_param.rl.max_burst_sz = 3993 ucmd->burst_info.max_burst_sz; 3994 } else { 3995 err = -EINVAL; 3996 goto out; 3997 } 3998 } 3999 4000 if (ucmd->burst_info.typical_pkt_sz) { 4001 if (attr->rate_limit && 4002 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4003 raw_qp_param.rl.typical_pkt_sz = 4004 ucmd->burst_info.typical_pkt_sz; 4005 } else { 4006 err = -EINVAL; 4007 goto out; 4008 } 4009 } 4010 4011 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4012 } 4013 4014 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4015 } else { 4016 if (udata) { 4017 /* For the kernel flows, the resp will stay zero */ 4018 resp->ece_options = 4019 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4020 ucmd->ece_options : 0; 4021 resp->response_length = sizeof(*resp); 4022 } 4023 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4024 &resp->ece_options); 4025 } 4026 4027 if (err) 4028 goto out; 4029 4030 qp->state = new_state; 4031 4032 if (attr_mask & IB_QP_ACCESS_FLAGS) 4033 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4034 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4035 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4036 if (attr_mask & IB_QP_PORT) 4037 qp->port = attr->port_num; 4038 if (attr_mask & IB_QP_ALT_PATH) 4039 qp->trans_qp.alt_port = attr->alt_port_num; 4040 4041 /* 4042 * If we moved a kernel QP to RESET, clean up all old CQ 4043 * entries and reinitialize the QP. 4044 */ 4045 if (new_state == IB_QPS_RESET && 4046 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 4047 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4048 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4049 if (send_cq != recv_cq) 4050 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4051 4052 qp->rq.head = 0; 4053 qp->rq.tail = 0; 4054 qp->sq.head = 0; 4055 qp->sq.tail = 0; 4056 qp->sq.cur_post = 0; 4057 if (qp->sq.wqe_cnt) 4058 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4059 qp->sq.last_poll = 0; 4060 qp->db.db[MLX5_RCV_DBR] = 0; 4061 qp->db.db[MLX5_SND_DBR] = 0; 4062 } 4063 4064 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4065 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4066 if (!err) 4067 qp->counter_pending = 0; 4068 } 4069 4070 out: 4071 kfree(qpc); 4072 return err; 4073 } 4074 4075 static inline bool is_valid_mask(int mask, int req, int opt) 4076 { 4077 if ((mask & req) != req) 4078 return false; 4079 4080 if (mask & ~(req | opt)) 4081 return false; 4082 4083 return true; 4084 } 4085 4086 /* check valid transition for driver QP types 4087 * for now the only QP type that this function supports is DCI 4088 */ 4089 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4090 enum ib_qp_attr_mask attr_mask) 4091 { 4092 int req = IB_QP_STATE; 4093 int opt = 0; 4094 4095 if (new_state == IB_QPS_RESET) { 4096 return is_valid_mask(attr_mask, req, opt); 4097 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4098 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4099 return is_valid_mask(attr_mask, req, opt); 4100 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4101 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4102 return is_valid_mask(attr_mask, req, opt); 4103 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4104 req |= IB_QP_PATH_MTU; 4105 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4106 return is_valid_mask(attr_mask, req, opt); 4107 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4108 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4109 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4110 opt = IB_QP_MIN_RNR_TIMER; 4111 return is_valid_mask(attr_mask, req, opt); 4112 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4113 opt = IB_QP_MIN_RNR_TIMER; 4114 return is_valid_mask(attr_mask, req, opt); 4115 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4116 return is_valid_mask(attr_mask, req, opt); 4117 } 4118 return false; 4119 } 4120 4121 /* mlx5_ib_modify_dct: modify a DCT QP 4122 * valid transitions are: 4123 * RESET to INIT: must set access_flags, pkey_index and port 4124 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4125 * mtu, gid_index and hop_limit 4126 * Other transitions and attributes are illegal 4127 */ 4128 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4129 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4130 struct ib_udata *udata) 4131 { 4132 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4133 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4134 enum ib_qp_state cur_state, new_state; 4135 int required = IB_QP_STATE; 4136 void *dctc; 4137 int err; 4138 4139 if (!(attr_mask & IB_QP_STATE)) 4140 return -EINVAL; 4141 4142 cur_state = qp->state; 4143 new_state = attr->qp_state; 4144 4145 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4146 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4147 /* 4148 * DCT doesn't initialize QP till modify command is executed, 4149 * so we need to overwrite previously set ECE field if user 4150 * provided any value except zero, which means not set/not 4151 * valid. 4152 */ 4153 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4154 4155 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4156 u16 set_id; 4157 4158 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4159 if (!is_valid_mask(attr_mask, required, 0)) 4160 return -EINVAL; 4161 4162 if (attr->port_num == 0 || 4163 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4164 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4165 attr->port_num, dev->num_ports); 4166 return -EINVAL; 4167 } 4168 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4169 MLX5_SET(dctc, dctc, rre, 1); 4170 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4171 MLX5_SET(dctc, dctc, rwe, 1); 4172 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4173 int atomic_mode; 4174 4175 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4176 if (atomic_mode < 0) 4177 return -EOPNOTSUPP; 4178 4179 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4180 MLX5_SET(dctc, dctc, rae, 1); 4181 } 4182 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4183 if (mlx5_lag_is_active(dev->mdev)) 4184 MLX5_SET(dctc, dctc, port, 4185 get_tx_affinity_rr(dev, udata)); 4186 else 4187 MLX5_SET(dctc, dctc, port, attr->port_num); 4188 4189 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4190 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4191 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4192 struct mlx5_ib_modify_qp_resp resp = {}; 4193 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4194 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4195 4196 if (udata->outlen < min_resp_len) 4197 return -EINVAL; 4198 /* 4199 * If we don't have enough space for the ECE options, 4200 * simply indicate it with resp.response_length. 4201 */ 4202 resp.response_length = (udata->outlen < sizeof(resp)) ? 4203 min_resp_len : 4204 sizeof(resp); 4205 4206 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4207 if (!is_valid_mask(attr_mask, required, 0)) 4208 return -EINVAL; 4209 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4210 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4211 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4212 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4213 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4214 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4215 4216 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4217 MLX5_ST_SZ_BYTES(create_dct_in), out, 4218 sizeof(out)); 4219 if (err) 4220 return err; 4221 resp.dctn = qp->dct.mdct.mqp.qpn; 4222 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4223 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4224 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4225 if (err) { 4226 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4227 return err; 4228 } 4229 } else { 4230 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4231 return -EINVAL; 4232 } 4233 4234 qp->state = new_state; 4235 return 0; 4236 } 4237 4238 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4239 int attr_mask, struct ib_udata *udata) 4240 { 4241 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4242 struct mlx5_ib_modify_qp_resp resp = {}; 4243 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4244 struct mlx5_ib_modify_qp ucmd = {}; 4245 enum ib_qp_type qp_type; 4246 enum ib_qp_state cur_state, new_state; 4247 int err = -EINVAL; 4248 int port; 4249 4250 if (ibqp->rwq_ind_tbl) 4251 return -ENOSYS; 4252 4253 if (udata && udata->inlen) { 4254 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4255 return -EINVAL; 4256 4257 if (udata->inlen > sizeof(ucmd) && 4258 !ib_is_udata_cleared(udata, sizeof(ucmd), 4259 udata->inlen - sizeof(ucmd))) 4260 return -EOPNOTSUPP; 4261 4262 if (ib_copy_from_udata(&ucmd, udata, 4263 min(udata->inlen, sizeof(ucmd)))) 4264 return -EFAULT; 4265 4266 if (ucmd.comp_mask || 4267 memchr_inv(&ucmd.burst_info.reserved, 0, 4268 sizeof(ucmd.burst_info.reserved))) 4269 return -EOPNOTSUPP; 4270 4271 } 4272 4273 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4274 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4275 4276 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI : 4277 qp->type; 4278 4279 if (qp_type == MLX5_IB_QPT_DCT) 4280 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4281 4282 mutex_lock(&qp->mutex); 4283 4284 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4285 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4286 4287 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 4288 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 4289 } 4290 4291 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4292 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4293 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4294 attr_mask); 4295 goto out; 4296 } 4297 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4298 qp_type != MLX5_IB_QPT_DCI && 4299 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4300 attr_mask)) { 4301 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4302 cur_state, new_state, ibqp->qp_type, attr_mask); 4303 goto out; 4304 } else if (qp_type == MLX5_IB_QPT_DCI && 4305 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4306 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4307 cur_state, new_state, qp_type, attr_mask); 4308 goto out; 4309 } 4310 4311 if ((attr_mask & IB_QP_PORT) && 4312 (attr->port_num == 0 || 4313 attr->port_num > dev->num_ports)) { 4314 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4315 attr->port_num, dev->num_ports); 4316 goto out; 4317 } 4318 4319 if (attr_mask & IB_QP_PKEY_INDEX) { 4320 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 4321 if (attr->pkey_index >= 4322 dev->mdev->port_caps[port - 1].pkey_table_len) { 4323 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 4324 attr->pkey_index); 4325 goto out; 4326 } 4327 } 4328 4329 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4330 attr->max_rd_atomic > 4331 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4332 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4333 attr->max_rd_atomic); 4334 goto out; 4335 } 4336 4337 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4338 attr->max_dest_rd_atomic > 4339 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4340 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4341 attr->max_dest_rd_atomic); 4342 goto out; 4343 } 4344 4345 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4346 err = 0; 4347 goto out; 4348 } 4349 4350 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4351 new_state, &ucmd, &resp, udata); 4352 4353 /* resp.response_length is set in ECE supported flows only */ 4354 if (!err && resp.response_length && 4355 udata->outlen >= resp.response_length) 4356 /* Return -EFAULT to the user and expect him to destroy QP. */ 4357 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4358 4359 out: 4360 mutex_unlock(&qp->mutex); 4361 return err; 4362 } 4363 4364 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4365 { 4366 switch (mlx5_state) { 4367 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4368 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4369 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4370 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4371 case MLX5_QP_STATE_SQ_DRAINING: 4372 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4373 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4374 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4375 default: return -1; 4376 } 4377 } 4378 4379 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4380 { 4381 switch (mlx5_mig_state) { 4382 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4383 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4384 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4385 default: return -1; 4386 } 4387 } 4388 4389 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4390 struct rdma_ah_attr *ah_attr, void *path) 4391 { 4392 int port = MLX5_GET(ads, path, vhca_port_num); 4393 int static_rate; 4394 4395 memset(ah_attr, 0, sizeof(*ah_attr)); 4396 4397 if (!port || port > ibdev->num_ports) 4398 return; 4399 4400 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4401 4402 rdma_ah_set_port_num(ah_attr, port); 4403 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4404 4405 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4406 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4407 4408 static_rate = MLX5_GET(ads, path, stat_rate); 4409 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0); 4410 if (MLX5_GET(ads, path, grh) || 4411 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4412 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4413 MLX5_GET(ads, path, src_addr_index), 4414 MLX5_GET(ads, path, hop_limit), 4415 MLX5_GET(ads, path, tclass)); 4416 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4417 } 4418 } 4419 4420 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4421 struct mlx5_ib_sq *sq, 4422 u8 *sq_state) 4423 { 4424 int err; 4425 4426 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4427 if (err) 4428 goto out; 4429 sq->state = *sq_state; 4430 4431 out: 4432 return err; 4433 } 4434 4435 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4436 struct mlx5_ib_rq *rq, 4437 u8 *rq_state) 4438 { 4439 void *out; 4440 void *rqc; 4441 int inlen; 4442 int err; 4443 4444 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4445 out = kvzalloc(inlen, GFP_KERNEL); 4446 if (!out) 4447 return -ENOMEM; 4448 4449 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4450 if (err) 4451 goto out; 4452 4453 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4454 *rq_state = MLX5_GET(rqc, rqc, state); 4455 rq->state = *rq_state; 4456 4457 out: 4458 kvfree(out); 4459 return err; 4460 } 4461 4462 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4463 struct mlx5_ib_qp *qp, u8 *qp_state) 4464 { 4465 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4466 [MLX5_RQC_STATE_RST] = { 4467 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4468 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4469 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4470 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4471 }, 4472 [MLX5_RQC_STATE_RDY] = { 4473 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4474 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4475 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4476 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4477 }, 4478 [MLX5_RQC_STATE_ERR] = { 4479 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4480 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4481 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4482 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4483 }, 4484 [MLX5_RQ_STATE_NA] = { 4485 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4486 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4487 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4488 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4489 }, 4490 }; 4491 4492 *qp_state = sqrq_trans[rq_state][sq_state]; 4493 4494 if (*qp_state == MLX5_QP_STATE_BAD) { 4495 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4496 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4497 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4498 return -EINVAL; 4499 } 4500 4501 if (*qp_state == MLX5_QP_STATE) 4502 *qp_state = qp->state; 4503 4504 return 0; 4505 } 4506 4507 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4508 struct mlx5_ib_qp *qp, 4509 u8 *raw_packet_qp_state) 4510 { 4511 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4512 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4513 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4514 int err; 4515 u8 sq_state = MLX5_SQ_STATE_NA; 4516 u8 rq_state = MLX5_RQ_STATE_NA; 4517 4518 if (qp->sq.wqe_cnt) { 4519 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4520 if (err) 4521 return err; 4522 } 4523 4524 if (qp->rq.wqe_cnt) { 4525 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4526 if (err) 4527 return err; 4528 } 4529 4530 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4531 raw_packet_qp_state); 4532 } 4533 4534 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4535 struct ib_qp_attr *qp_attr) 4536 { 4537 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4538 void *qpc, *pri_path, *alt_path; 4539 u32 *outb; 4540 int err; 4541 4542 outb = kzalloc(outlen, GFP_KERNEL); 4543 if (!outb) 4544 return -ENOMEM; 4545 4546 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 4547 if (err) 4548 goto out; 4549 4550 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4551 4552 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4553 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4554 qp_attr->sq_draining = 1; 4555 4556 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4557 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4558 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4559 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4560 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4561 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4562 4563 if (MLX5_GET(qpc, qpc, rre)) 4564 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4565 if (MLX5_GET(qpc, qpc, rwe)) 4566 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4567 if (MLX5_GET(qpc, qpc, rae)) 4568 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4569 4570 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4571 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4572 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4573 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4574 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4575 4576 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4577 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4578 4579 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4580 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4581 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4582 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4583 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4584 } 4585 4586 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4587 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4588 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4589 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4590 4591 out: 4592 kfree(outb); 4593 return err; 4594 } 4595 4596 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4597 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4598 struct ib_qp_init_attr *qp_init_attr) 4599 { 4600 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4601 u32 *out; 4602 u32 access_flags = 0; 4603 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4604 void *dctc; 4605 int err; 4606 int supported_mask = IB_QP_STATE | 4607 IB_QP_ACCESS_FLAGS | 4608 IB_QP_PORT | 4609 IB_QP_MIN_RNR_TIMER | 4610 IB_QP_AV | 4611 IB_QP_PATH_MTU | 4612 IB_QP_PKEY_INDEX; 4613 4614 if (qp_attr_mask & ~supported_mask) 4615 return -EINVAL; 4616 if (mqp->state != IB_QPS_RTR) 4617 return -EINVAL; 4618 4619 out = kzalloc(outlen, GFP_KERNEL); 4620 if (!out) 4621 return -ENOMEM; 4622 4623 err = mlx5_core_dct_query(dev, dct, out, outlen); 4624 if (err) 4625 goto out; 4626 4627 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4628 4629 if (qp_attr_mask & IB_QP_STATE) 4630 qp_attr->qp_state = IB_QPS_RTR; 4631 4632 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4633 if (MLX5_GET(dctc, dctc, rre)) 4634 access_flags |= IB_ACCESS_REMOTE_READ; 4635 if (MLX5_GET(dctc, dctc, rwe)) 4636 access_flags |= IB_ACCESS_REMOTE_WRITE; 4637 if (MLX5_GET(dctc, dctc, rae)) 4638 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4639 qp_attr->qp_access_flags = access_flags; 4640 } 4641 4642 if (qp_attr_mask & IB_QP_PORT) 4643 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4644 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4645 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4646 if (qp_attr_mask & IB_QP_AV) { 4647 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4648 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4649 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4650 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4651 } 4652 if (qp_attr_mask & IB_QP_PATH_MTU) 4653 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4654 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4655 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4656 out: 4657 kfree(out); 4658 return err; 4659 } 4660 4661 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4662 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4663 { 4664 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4665 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4666 int err = 0; 4667 u8 raw_packet_qp_state; 4668 4669 if (ibqp->rwq_ind_tbl) 4670 return -ENOSYS; 4671 4672 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4673 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4674 qp_init_attr); 4675 4676 /* Not all of output fields are applicable, make sure to zero them */ 4677 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4678 memset(qp_attr, 0, sizeof(*qp_attr)); 4679 4680 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 4681 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4682 qp_attr_mask, qp_init_attr); 4683 4684 mutex_lock(&qp->mutex); 4685 4686 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4687 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4688 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4689 if (err) 4690 goto out; 4691 qp->state = raw_packet_qp_state; 4692 qp_attr->port_num = 1; 4693 } else { 4694 err = query_qp_attr(dev, qp, qp_attr); 4695 if (err) 4696 goto out; 4697 } 4698 4699 qp_attr->qp_state = qp->state; 4700 qp_attr->cur_qp_state = qp_attr->qp_state; 4701 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4702 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4703 4704 if (!ibqp->uobject) { 4705 qp_attr->cap.max_send_wr = qp->sq.max_post; 4706 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4707 qp_init_attr->qp_context = ibqp->qp_context; 4708 } else { 4709 qp_attr->cap.max_send_wr = 0; 4710 qp_attr->cap.max_send_sge = 0; 4711 } 4712 4713 qp_init_attr->qp_type = ibqp->qp_type; 4714 qp_init_attr->recv_cq = ibqp->recv_cq; 4715 qp_init_attr->send_cq = ibqp->send_cq; 4716 qp_init_attr->srq = ibqp->srq; 4717 qp_attr->cap.max_inline_data = qp->max_inline_data; 4718 4719 qp_init_attr->cap = qp_attr->cap; 4720 4721 qp_init_attr->create_flags = qp->flags; 4722 4723 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4724 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4725 4726 out: 4727 mutex_unlock(&qp->mutex); 4728 return err; 4729 } 4730 4731 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 4732 { 4733 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 4734 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 4735 4736 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4737 return -EOPNOTSUPP; 4738 4739 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 4740 } 4741 4742 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4743 { 4744 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4745 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4746 4747 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 4748 } 4749 4750 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4751 { 4752 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4753 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4754 struct ib_event event; 4755 4756 if (rwq->ibwq.event_handler) { 4757 event.device = rwq->ibwq.device; 4758 event.element.wq = &rwq->ibwq; 4759 switch (type) { 4760 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4761 event.event = IB_EVENT_WQ_FATAL; 4762 break; 4763 default: 4764 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4765 return; 4766 } 4767 4768 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4769 } 4770 } 4771 4772 static int set_delay_drop(struct mlx5_ib_dev *dev) 4773 { 4774 int err = 0; 4775 4776 mutex_lock(&dev->delay_drop.lock); 4777 if (dev->delay_drop.activate) 4778 goto out; 4779 4780 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 4781 if (err) 4782 goto out; 4783 4784 dev->delay_drop.activate = true; 4785 out: 4786 mutex_unlock(&dev->delay_drop.lock); 4787 4788 if (!err) 4789 atomic_inc(&dev->delay_drop.rqs_cnt); 4790 return err; 4791 } 4792 4793 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4794 struct ib_wq_init_attr *init_attr) 4795 { 4796 struct mlx5_ib_dev *dev; 4797 int has_net_offloads; 4798 __be64 *rq_pas0; 4799 void *in; 4800 void *rqc; 4801 void *wq; 4802 int inlen; 4803 int err; 4804 4805 dev = to_mdev(pd->device); 4806 4807 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4808 in = kvzalloc(inlen, GFP_KERNEL); 4809 if (!in) 4810 return -ENOMEM; 4811 4812 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4813 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4814 MLX5_SET(rqc, rqc, mem_rq_type, 4815 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4816 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4817 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4818 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4819 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4820 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4821 MLX5_SET(wq, wq, wq_type, 4822 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 4823 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 4824 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 4825 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 4826 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 4827 err = -EOPNOTSUPP; 4828 goto out; 4829 } else { 4830 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4831 } 4832 } 4833 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4834 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 4835 /* 4836 * In Firmware number of strides in each WQE is: 4837 * "512 * 2^single_wqe_log_num_of_strides" 4838 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 4839 * accepted as 0 to 9 4840 */ 4841 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 4842 2, 3, 4, 5, 6, 7, 8, 9 }; 4843 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 4844 MLX5_SET(wq, wq, log_wqe_stride_size, 4845 rwq->single_stride_log_num_of_bytes - 4846 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 4847 MLX5_SET(wq, wq, log_wqe_num_of_strides, 4848 fw_map[rwq->log_num_strides - 4849 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 4850 } 4851 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4852 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4853 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4854 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4855 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4856 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4857 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4858 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4859 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4860 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4861 err = -EOPNOTSUPP; 4862 goto out; 4863 } 4864 } else { 4865 MLX5_SET(rqc, rqc, vsd, 1); 4866 } 4867 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4868 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4869 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4870 err = -EOPNOTSUPP; 4871 goto out; 4872 } 4873 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4874 } 4875 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4876 if (!(dev->ib_dev.attrs.raw_packet_caps & 4877 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4878 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4879 err = -EOPNOTSUPP; 4880 goto out; 4881 } 4882 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4883 } 4884 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4885 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4886 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 4887 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4888 err = set_delay_drop(dev); 4889 if (err) { 4890 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4891 err); 4892 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 4893 } else { 4894 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4895 } 4896 } 4897 out: 4898 kvfree(in); 4899 return err; 4900 } 4901 4902 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4903 struct ib_wq_init_attr *wq_init_attr, 4904 struct mlx5_ib_create_wq *ucmd, 4905 struct mlx5_ib_rwq *rwq) 4906 { 4907 /* Sanity check RQ size before proceeding */ 4908 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4909 return -EINVAL; 4910 4911 if (!ucmd->rq_wqe_count) 4912 return -EINVAL; 4913 4914 rwq->wqe_count = ucmd->rq_wqe_count; 4915 rwq->wqe_shift = ucmd->rq_wqe_shift; 4916 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 4917 return -EINVAL; 4918 4919 rwq->log_rq_stride = rwq->wqe_shift; 4920 rwq->log_rq_size = ilog2(rwq->wqe_count); 4921 return 0; 4922 } 4923 4924 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 4925 { 4926 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 4927 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 4928 return false; 4929 4930 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 4931 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 4932 return false; 4933 4934 return true; 4935 } 4936 4937 static int prepare_user_rq(struct ib_pd *pd, 4938 struct ib_wq_init_attr *init_attr, 4939 struct ib_udata *udata, 4940 struct mlx5_ib_rwq *rwq) 4941 { 4942 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4943 struct mlx5_ib_create_wq ucmd = {}; 4944 int err; 4945 size_t required_cmd_sz; 4946 4947 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 4948 single_stride_log_num_of_bytes); 4949 if (udata->inlen < required_cmd_sz) { 4950 mlx5_ib_dbg(dev, "invalid inlen\n"); 4951 return -EINVAL; 4952 } 4953 4954 if (udata->inlen > sizeof(ucmd) && 4955 !ib_is_udata_cleared(udata, sizeof(ucmd), 4956 udata->inlen - sizeof(ucmd))) { 4957 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4958 return -EOPNOTSUPP; 4959 } 4960 4961 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4962 mlx5_ib_dbg(dev, "copy failed\n"); 4963 return -EFAULT; 4964 } 4965 4966 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 4967 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4968 return -EOPNOTSUPP; 4969 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 4970 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 4971 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 4972 return -EOPNOTSUPP; 4973 } 4974 if ((ucmd.single_stride_log_num_of_bytes < 4975 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 4976 (ucmd.single_stride_log_num_of_bytes > 4977 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 4978 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 4979 ucmd.single_stride_log_num_of_bytes, 4980 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 4981 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 4982 return -EINVAL; 4983 } 4984 if (!log_of_strides_valid(dev, 4985 ucmd.single_wqe_log_num_of_strides)) { 4986 mlx5_ib_dbg( 4987 dev, 4988 "Invalid log num strides (%u. Range is %u - %u)\n", 4989 ucmd.single_wqe_log_num_of_strides, 4990 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 4991 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 4992 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 4993 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 4994 return -EINVAL; 4995 } 4996 rwq->single_stride_log_num_of_bytes = 4997 ucmd.single_stride_log_num_of_bytes; 4998 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 4999 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5000 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5001 } 5002 5003 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5004 if (err) { 5005 mlx5_ib_dbg(dev, "err %d\n", err); 5006 return err; 5007 } 5008 5009 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5010 if (err) { 5011 mlx5_ib_dbg(dev, "err %d\n", err); 5012 return err; 5013 } 5014 5015 rwq->user_index = ucmd.user_index; 5016 return 0; 5017 } 5018 5019 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5020 struct ib_wq_init_attr *init_attr, 5021 struct ib_udata *udata) 5022 { 5023 struct mlx5_ib_dev *dev; 5024 struct mlx5_ib_rwq *rwq; 5025 struct mlx5_ib_create_wq_resp resp = {}; 5026 size_t min_resp_len; 5027 int err; 5028 5029 if (!udata) 5030 return ERR_PTR(-ENOSYS); 5031 5032 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5033 if (udata->outlen && udata->outlen < min_resp_len) 5034 return ERR_PTR(-EINVAL); 5035 5036 if (!capable(CAP_SYS_RAWIO) && 5037 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5038 return ERR_PTR(-EPERM); 5039 5040 dev = to_mdev(pd->device); 5041 switch (init_attr->wq_type) { 5042 case IB_WQT_RQ: 5043 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5044 if (!rwq) 5045 return ERR_PTR(-ENOMEM); 5046 err = prepare_user_rq(pd, init_attr, udata, rwq); 5047 if (err) 5048 goto err; 5049 err = create_rq(rwq, pd, init_attr); 5050 if (err) 5051 goto err_user_rq; 5052 break; 5053 default: 5054 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5055 init_attr->wq_type); 5056 return ERR_PTR(-EINVAL); 5057 } 5058 5059 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5060 rwq->ibwq.state = IB_WQS_RESET; 5061 if (udata->outlen) { 5062 resp.response_length = offsetofend( 5063 struct mlx5_ib_create_wq_resp, response_length); 5064 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5065 if (err) 5066 goto err_copy; 5067 } 5068 5069 rwq->core_qp.event = mlx5_ib_wq_event; 5070 rwq->ibwq.event_handler = init_attr->event_handler; 5071 return &rwq->ibwq; 5072 5073 err_copy: 5074 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5075 err_user_rq: 5076 destroy_user_rq(dev, pd, rwq, udata); 5077 err: 5078 kfree(rwq); 5079 return ERR_PTR(err); 5080 } 5081 5082 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5083 { 5084 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5085 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5086 int ret; 5087 5088 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5089 if (ret) 5090 return ret; 5091 destroy_user_rq(dev, wq->pd, rwq, udata); 5092 kfree(rwq); 5093 return 0; 5094 } 5095 5096 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5097 struct ib_rwq_ind_table_init_attr *init_attr, 5098 struct ib_udata *udata) 5099 { 5100 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5101 to_mrwq_ind_table(ib_rwq_ind_table); 5102 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5103 int sz = 1 << init_attr->log_ind_tbl_size; 5104 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5105 size_t min_resp_len; 5106 int inlen; 5107 int err; 5108 int i; 5109 u32 *in; 5110 void *rqtc; 5111 5112 if (udata->inlen > 0 && 5113 !ib_is_udata_cleared(udata, 0, 5114 udata->inlen)) 5115 return -EOPNOTSUPP; 5116 5117 if (init_attr->log_ind_tbl_size > 5118 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5119 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5120 init_attr->log_ind_tbl_size, 5121 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5122 return -EINVAL; 5123 } 5124 5125 min_resp_len = 5126 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5127 if (udata->outlen && udata->outlen < min_resp_len) 5128 return -EINVAL; 5129 5130 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5131 in = kvzalloc(inlen, GFP_KERNEL); 5132 if (!in) 5133 return -ENOMEM; 5134 5135 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5136 5137 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5138 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5139 5140 for (i = 0; i < sz; i++) 5141 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5142 5143 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5144 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5145 5146 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5147 kvfree(in); 5148 if (err) 5149 return err; 5150 5151 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5152 if (udata->outlen) { 5153 resp.response_length = 5154 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5155 response_length); 5156 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5157 if (err) 5158 goto err_copy; 5159 } 5160 5161 return 0; 5162 5163 err_copy: 5164 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5165 return err; 5166 } 5167 5168 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5169 { 5170 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5171 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5172 5173 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5174 } 5175 5176 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5177 u32 wq_attr_mask, struct ib_udata *udata) 5178 { 5179 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5180 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5181 struct mlx5_ib_modify_wq ucmd = {}; 5182 size_t required_cmd_sz; 5183 int curr_wq_state; 5184 int wq_state; 5185 int inlen; 5186 int err; 5187 void *rqc; 5188 void *in; 5189 5190 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5191 if (udata->inlen < required_cmd_sz) 5192 return -EINVAL; 5193 5194 if (udata->inlen > sizeof(ucmd) && 5195 !ib_is_udata_cleared(udata, sizeof(ucmd), 5196 udata->inlen - sizeof(ucmd))) 5197 return -EOPNOTSUPP; 5198 5199 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5200 return -EFAULT; 5201 5202 if (ucmd.comp_mask || ucmd.reserved) 5203 return -EOPNOTSUPP; 5204 5205 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5206 in = kvzalloc(inlen, GFP_KERNEL); 5207 if (!in) 5208 return -ENOMEM; 5209 5210 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5211 5212 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5213 wq_attr->curr_wq_state : wq->state; 5214 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5215 wq_attr->wq_state : curr_wq_state; 5216 if (curr_wq_state == IB_WQS_ERR) 5217 curr_wq_state = MLX5_RQC_STATE_ERR; 5218 if (wq_state == IB_WQS_ERR) 5219 wq_state = MLX5_RQC_STATE_ERR; 5220 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5221 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5222 MLX5_SET(rqc, rqc, state, wq_state); 5223 5224 if (wq_attr_mask & IB_WQ_FLAGS) { 5225 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5226 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5227 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5228 mlx5_ib_dbg(dev, "VLAN offloads are not " 5229 "supported\n"); 5230 err = -EOPNOTSUPP; 5231 goto out; 5232 } 5233 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5234 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5235 MLX5_SET(rqc, rqc, vsd, 5236 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5237 } 5238 5239 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5240 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5241 err = -EOPNOTSUPP; 5242 goto out; 5243 } 5244 } 5245 5246 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5247 u16 set_id; 5248 5249 set_id = mlx5_ib_get_counters_id(dev, 0); 5250 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5251 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5252 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5253 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5254 } else 5255 dev_info_once( 5256 &dev->ib_dev.dev, 5257 "Receive WQ counters are not supported on current FW\n"); 5258 } 5259 5260 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5261 if (!err) 5262 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5263 5264 out: 5265 kvfree(in); 5266 return err; 5267 } 5268 5269 struct mlx5_ib_drain_cqe { 5270 struct ib_cqe cqe; 5271 struct completion done; 5272 }; 5273 5274 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5275 { 5276 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5277 struct mlx5_ib_drain_cqe, 5278 cqe); 5279 5280 complete(&cqe->done); 5281 } 5282 5283 /* This function returns only once the drained WR was completed */ 5284 static void handle_drain_completion(struct ib_cq *cq, 5285 struct mlx5_ib_drain_cqe *sdrain, 5286 struct mlx5_ib_dev *dev) 5287 { 5288 struct mlx5_core_dev *mdev = dev->mdev; 5289 5290 if (cq->poll_ctx == IB_POLL_DIRECT) { 5291 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5292 ib_process_cq_direct(cq, -1); 5293 return; 5294 } 5295 5296 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5297 struct mlx5_ib_cq *mcq = to_mcq(cq); 5298 bool triggered = false; 5299 unsigned long flags; 5300 5301 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5302 /* Make sure that the CQ handler won't run if wasn't run yet */ 5303 if (!mcq->mcq.reset_notify_added) 5304 mcq->mcq.reset_notify_added = 1; 5305 else 5306 triggered = true; 5307 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5308 5309 if (triggered) { 5310 /* Wait for any scheduled/running task to be ended */ 5311 switch (cq->poll_ctx) { 5312 case IB_POLL_SOFTIRQ: 5313 irq_poll_disable(&cq->iop); 5314 irq_poll_enable(&cq->iop); 5315 break; 5316 case IB_POLL_WORKQUEUE: 5317 cancel_work_sync(&cq->work); 5318 break; 5319 default: 5320 WARN_ON_ONCE(1); 5321 } 5322 } 5323 5324 /* Run the CQ handler - this makes sure that the drain WR will 5325 * be processed if wasn't processed yet. 5326 */ 5327 mcq->mcq.comp(&mcq->mcq, NULL); 5328 } 5329 5330 wait_for_completion(&sdrain->done); 5331 } 5332 5333 void mlx5_ib_drain_sq(struct ib_qp *qp) 5334 { 5335 struct ib_cq *cq = qp->send_cq; 5336 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5337 struct mlx5_ib_drain_cqe sdrain; 5338 const struct ib_send_wr *bad_swr; 5339 struct ib_rdma_wr swr = { 5340 .wr = { 5341 .next = NULL, 5342 { .wr_cqe = &sdrain.cqe, }, 5343 .opcode = IB_WR_RDMA_WRITE, 5344 }, 5345 }; 5346 int ret; 5347 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5348 struct mlx5_core_dev *mdev = dev->mdev; 5349 5350 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5351 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5352 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5353 return; 5354 } 5355 5356 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5357 init_completion(&sdrain.done); 5358 5359 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5360 if (ret) { 5361 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5362 return; 5363 } 5364 5365 handle_drain_completion(cq, &sdrain, dev); 5366 } 5367 5368 void mlx5_ib_drain_rq(struct ib_qp *qp) 5369 { 5370 struct ib_cq *cq = qp->recv_cq; 5371 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5372 struct mlx5_ib_drain_cqe rdrain; 5373 struct ib_recv_wr rwr = {}; 5374 const struct ib_recv_wr *bad_rwr; 5375 int ret; 5376 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5377 struct mlx5_core_dev *mdev = dev->mdev; 5378 5379 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5380 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5381 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5382 return; 5383 } 5384 5385 rwr.wr_cqe = &rdrain.cqe; 5386 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5387 init_completion(&rdrain.done); 5388 5389 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5390 if (ret) { 5391 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5392 return; 5393 } 5394 5395 handle_drain_completion(cq, &rdrain, dev); 5396 } 5397 5398 /** 5399 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5400 * the default counter 5401 */ 5402 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5403 { 5404 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5405 struct mlx5_ib_qp *mqp = to_mqp(qp); 5406 int err = 0; 5407 5408 mutex_lock(&mqp->mutex); 5409 if (mqp->state == IB_QPS_RESET) { 5410 qp->counter = counter; 5411 goto out; 5412 } 5413 5414 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5415 err = -EOPNOTSUPP; 5416 goto out; 5417 } 5418 5419 if (mqp->state == IB_QPS_RTS) { 5420 err = __mlx5_ib_qp_set_counter(qp, counter); 5421 if (!err) 5422 qp->counter = counter; 5423 5424 goto out; 5425 } 5426 5427 mqp->counter_pending = 1; 5428 qp->counter = counter; 5429 5430 out: 5431 mutex_unlock(&mqp->mutex); 5432 return err; 5433 } 5434