1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include "mlx5_ib.h" 38 #include "user.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 MLX5_IB_CACHE_LINE_SIZE = 64, 57 }; 58 59 static const u32 mlx5_ib_opcode[] = { 60 [IB_WR_SEND] = MLX5_OPCODE_SEND, 61 [IB_WR_LSO] = MLX5_OPCODE_LSO, 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 74 }; 75 76 struct mlx5_wqe_eth_pad { 77 u8 rsvd0[16]; 78 }; 79 80 static int is_qp0(enum ib_qp_type qp_type) 81 { 82 return qp_type == IB_QPT_SMI; 83 } 84 85 static int is_sqp(enum ib_qp_type qp_type) 86 { 87 return is_qp0(qp_type) || is_qp1(qp_type); 88 } 89 90 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 91 { 92 return mlx5_buf_offset(&qp->buf, offset); 93 } 94 95 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 96 { 97 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 98 } 99 100 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 101 { 102 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 103 } 104 105 /** 106 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 107 * 108 * @qp: QP to copy from. 109 * @send: copy from the send queue when non-zero, use the receive queue 110 * otherwise. 111 * @wqe_index: index to start copying from. For send work queues, the 112 * wqe_index is in units of MLX5_SEND_WQE_BB. 113 * For receive work queue, it is the number of work queue 114 * element in the queue. 115 * @buffer: destination buffer. 116 * @length: maximum number of bytes to copy. 117 * 118 * Copies at least a single WQE, but may copy more data. 119 * 120 * Return: the number of bytes copied, or an error code. 121 */ 122 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 123 void *buffer, u32 length, 124 struct mlx5_ib_qp_base *base) 125 { 126 struct ib_device *ibdev = qp->ibqp.device; 127 struct mlx5_ib_dev *dev = to_mdev(ibdev); 128 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 129 size_t offset; 130 size_t wq_end; 131 struct ib_umem *umem = base->ubuffer.umem; 132 u32 first_copy_length; 133 int wqe_length; 134 int ret; 135 136 if (wq->wqe_cnt == 0) { 137 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 138 qp->ibqp.qp_type); 139 return -EINVAL; 140 } 141 142 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 143 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 144 145 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 146 return -EINVAL; 147 148 if (offset > umem->length || 149 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 150 return -EINVAL; 151 152 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 153 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 154 if (ret) 155 return ret; 156 157 if (send) { 158 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 159 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 160 161 wqe_length = ds * MLX5_WQE_DS_UNITS; 162 } else { 163 wqe_length = 1 << wq->wqe_shift; 164 } 165 166 if (wqe_length <= first_copy_length) 167 return first_copy_length; 168 169 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 170 wqe_length - first_copy_length); 171 if (ret) 172 return ret; 173 174 return wqe_length; 175 } 176 177 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 178 { 179 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 180 struct ib_event event; 181 182 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 183 /* This event is only valid for trans_qps */ 184 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 185 } 186 187 if (ibqp->event_handler) { 188 event.device = ibqp->device; 189 event.element.qp = ibqp; 190 switch (type) { 191 case MLX5_EVENT_TYPE_PATH_MIG: 192 event.event = IB_EVENT_PATH_MIG; 193 break; 194 case MLX5_EVENT_TYPE_COMM_EST: 195 event.event = IB_EVENT_COMM_EST; 196 break; 197 case MLX5_EVENT_TYPE_SQ_DRAINED: 198 event.event = IB_EVENT_SQ_DRAINED; 199 break; 200 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 201 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 202 break; 203 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 204 event.event = IB_EVENT_QP_FATAL; 205 break; 206 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 207 event.event = IB_EVENT_PATH_MIG_ERR; 208 break; 209 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 210 event.event = IB_EVENT_QP_REQ_ERR; 211 break; 212 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 213 event.event = IB_EVENT_QP_ACCESS_ERR; 214 break; 215 default: 216 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 217 return; 218 } 219 220 ibqp->event_handler(&event, ibqp->qp_context); 221 } 222 } 223 224 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 225 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 226 { 227 int wqe_size; 228 int wq_size; 229 230 /* Sanity check RQ size before proceeding */ 231 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 232 return -EINVAL; 233 234 if (!has_rq) { 235 qp->rq.max_gs = 0; 236 qp->rq.wqe_cnt = 0; 237 qp->rq.wqe_shift = 0; 238 } else { 239 if (ucmd) { 240 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 241 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 242 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 243 qp->rq.max_post = qp->rq.wqe_cnt; 244 } else { 245 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 246 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 247 wqe_size = roundup_pow_of_two(wqe_size); 248 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 249 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 250 qp->rq.wqe_cnt = wq_size / wqe_size; 251 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 252 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 253 wqe_size, 254 MLX5_CAP_GEN(dev->mdev, 255 max_wqe_sz_rq)); 256 return -EINVAL; 257 } 258 qp->rq.wqe_shift = ilog2(wqe_size); 259 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 260 qp->rq.max_post = qp->rq.wqe_cnt; 261 } 262 } 263 264 return 0; 265 } 266 267 static int sq_overhead(struct ib_qp_init_attr *attr) 268 { 269 int size = 0; 270 271 switch (attr->qp_type) { 272 case IB_QPT_XRC_INI: 273 size += sizeof(struct mlx5_wqe_xrc_seg); 274 /* fall through */ 275 case IB_QPT_RC: 276 size += sizeof(struct mlx5_wqe_ctrl_seg) + 277 max(sizeof(struct mlx5_wqe_atomic_seg) + 278 sizeof(struct mlx5_wqe_raddr_seg), 279 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 280 sizeof(struct mlx5_mkey_seg)); 281 break; 282 283 case IB_QPT_XRC_TGT: 284 return 0; 285 286 case IB_QPT_UC: 287 size += sizeof(struct mlx5_wqe_ctrl_seg) + 288 max(sizeof(struct mlx5_wqe_raddr_seg), 289 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 290 sizeof(struct mlx5_mkey_seg)); 291 break; 292 293 case IB_QPT_UD: 294 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 295 size += sizeof(struct mlx5_wqe_eth_pad) + 296 sizeof(struct mlx5_wqe_eth_seg); 297 /* fall through */ 298 case IB_QPT_SMI: 299 case MLX5_IB_QPT_HW_GSI: 300 size += sizeof(struct mlx5_wqe_ctrl_seg) + 301 sizeof(struct mlx5_wqe_datagram_seg); 302 break; 303 304 case MLX5_IB_QPT_REG_UMR: 305 size += sizeof(struct mlx5_wqe_ctrl_seg) + 306 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 307 sizeof(struct mlx5_mkey_seg); 308 break; 309 310 default: 311 return -EINVAL; 312 } 313 314 return size; 315 } 316 317 static int calc_send_wqe(struct ib_qp_init_attr *attr) 318 { 319 int inl_size = 0; 320 int size; 321 322 size = sq_overhead(attr); 323 if (size < 0) 324 return size; 325 326 if (attr->cap.max_inline_data) { 327 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 328 attr->cap.max_inline_data; 329 } 330 331 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 332 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 333 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 334 return MLX5_SIG_WQE_SIZE; 335 else 336 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 337 } 338 339 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 340 struct mlx5_ib_qp *qp) 341 { 342 int wqe_size; 343 int wq_size; 344 345 if (!attr->cap.max_send_wr) 346 return 0; 347 348 wqe_size = calc_send_wqe(attr); 349 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 350 if (wqe_size < 0) 351 return wqe_size; 352 353 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 354 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 355 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 356 return -EINVAL; 357 } 358 359 qp->max_inline_data = wqe_size - sq_overhead(attr) - 360 sizeof(struct mlx5_wqe_inline_seg); 361 attr->cap.max_inline_data = qp->max_inline_data; 362 363 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 364 qp->signature_en = true; 365 366 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 367 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 368 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 369 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 370 qp->sq.wqe_cnt, 371 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 372 return -ENOMEM; 373 } 374 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 375 qp->sq.max_gs = attr->cap.max_send_sge; 376 qp->sq.max_post = wq_size / wqe_size; 377 attr->cap.max_send_wr = qp->sq.max_post; 378 379 return wq_size; 380 } 381 382 static int set_user_buf_size(struct mlx5_ib_dev *dev, 383 struct mlx5_ib_qp *qp, 384 struct mlx5_ib_create_qp *ucmd, 385 struct mlx5_ib_qp_base *base, 386 struct ib_qp_init_attr *attr) 387 { 388 int desc_sz = 1 << qp->sq.wqe_shift; 389 390 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 391 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 392 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 393 return -EINVAL; 394 } 395 396 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 397 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 398 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 399 return -EINVAL; 400 } 401 402 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 403 404 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 405 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 406 qp->sq.wqe_cnt, 407 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 408 return -EINVAL; 409 } 410 411 if (attr->qp_type == IB_QPT_RAW_PACKET) { 412 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 413 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 414 } else { 415 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 416 (qp->sq.wqe_cnt << 6); 417 } 418 419 return 0; 420 } 421 422 static int qp_has_rq(struct ib_qp_init_attr *attr) 423 { 424 if (attr->qp_type == IB_QPT_XRC_INI || 425 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 426 attr->qp_type == MLX5_IB_QPT_REG_UMR || 427 !attr->cap.max_recv_wr) 428 return 0; 429 430 return 1; 431 } 432 433 static int first_med_uuar(void) 434 { 435 return 1; 436 } 437 438 static int next_uuar(int n) 439 { 440 n++; 441 442 while (((n % 4) & 2)) 443 n++; 444 445 return n; 446 } 447 448 static int num_med_uuar(struct mlx5_uuar_info *uuari) 449 { 450 int n; 451 452 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 453 uuari->num_low_latency_uuars - 1; 454 455 return n >= 0 ? n : 0; 456 } 457 458 static int max_uuari(struct mlx5_uuar_info *uuari) 459 { 460 return uuari->num_uars * 4; 461 } 462 463 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 464 { 465 int med; 466 int i; 467 int t; 468 469 med = num_med_uuar(uuari); 470 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 471 t++; 472 if (t == med) 473 return next_uuar(i); 474 } 475 476 return 0; 477 } 478 479 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 480 { 481 int i; 482 483 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 484 if (!test_bit(i, uuari->bitmap)) { 485 set_bit(i, uuari->bitmap); 486 uuari->count[i]++; 487 return i; 488 } 489 } 490 491 return -ENOMEM; 492 } 493 494 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 495 { 496 int minidx = first_med_uuar(); 497 int i; 498 499 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 500 if (uuari->count[i] < uuari->count[minidx]) 501 minidx = i; 502 } 503 504 uuari->count[minidx]++; 505 return minidx; 506 } 507 508 static int alloc_uuar(struct mlx5_uuar_info *uuari, 509 enum mlx5_ib_latency_class lat) 510 { 511 int uuarn = -EINVAL; 512 513 mutex_lock(&uuari->lock); 514 switch (lat) { 515 case MLX5_IB_LATENCY_CLASS_LOW: 516 uuarn = 0; 517 uuari->count[uuarn]++; 518 break; 519 520 case MLX5_IB_LATENCY_CLASS_MEDIUM: 521 if (uuari->ver < 2) 522 uuarn = -ENOMEM; 523 else 524 uuarn = alloc_med_class_uuar(uuari); 525 break; 526 527 case MLX5_IB_LATENCY_CLASS_HIGH: 528 if (uuari->ver < 2) 529 uuarn = -ENOMEM; 530 else 531 uuarn = alloc_high_class_uuar(uuari); 532 break; 533 534 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 535 uuarn = 2; 536 break; 537 } 538 mutex_unlock(&uuari->lock); 539 540 return uuarn; 541 } 542 543 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 544 { 545 clear_bit(uuarn, uuari->bitmap); 546 --uuari->count[uuarn]; 547 } 548 549 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 550 { 551 clear_bit(uuarn, uuari->bitmap); 552 --uuari->count[uuarn]; 553 } 554 555 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 556 { 557 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 558 int high_uuar = nuuars - uuari->num_low_latency_uuars; 559 560 mutex_lock(&uuari->lock); 561 if (uuarn == 0) { 562 --uuari->count[uuarn]; 563 goto out; 564 } 565 566 if (uuarn < high_uuar) { 567 free_med_class_uuar(uuari, uuarn); 568 goto out; 569 } 570 571 free_high_class_uuar(uuari, uuarn); 572 573 out: 574 mutex_unlock(&uuari->lock); 575 } 576 577 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 578 { 579 switch (state) { 580 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 581 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 582 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 583 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 584 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 585 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 586 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 587 default: return -1; 588 } 589 } 590 591 static int to_mlx5_st(enum ib_qp_type type) 592 { 593 switch (type) { 594 case IB_QPT_RC: return MLX5_QP_ST_RC; 595 case IB_QPT_UC: return MLX5_QP_ST_UC; 596 case IB_QPT_UD: return MLX5_QP_ST_UD; 597 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 598 case IB_QPT_XRC_INI: 599 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 600 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 601 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 602 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 603 case IB_QPT_RAW_PACKET: 604 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 605 case IB_QPT_MAX: 606 default: return -EINVAL; 607 } 608 } 609 610 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 611 { 612 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 613 } 614 615 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 616 struct ib_pd *pd, 617 unsigned long addr, size_t size, 618 struct ib_umem **umem, 619 int *npages, int *page_shift, int *ncont, 620 u32 *offset) 621 { 622 int err; 623 624 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 625 if (IS_ERR(*umem)) { 626 mlx5_ib_dbg(dev, "umem_get failed\n"); 627 return PTR_ERR(*umem); 628 } 629 630 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL); 631 632 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 633 if (err) { 634 mlx5_ib_warn(dev, "bad offset\n"); 635 goto err_umem; 636 } 637 638 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 639 addr, size, *npages, *page_shift, *ncont, *offset); 640 641 return 0; 642 643 err_umem: 644 ib_umem_release(*umem); 645 *umem = NULL; 646 647 return err; 648 } 649 650 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 651 struct mlx5_ib_qp *qp, struct ib_udata *udata, 652 struct ib_qp_init_attr *attr, 653 struct mlx5_create_qp_mbox_in **in, 654 struct mlx5_ib_create_qp_resp *resp, int *inlen, 655 struct mlx5_ib_qp_base *base) 656 { 657 struct mlx5_ib_ucontext *context; 658 struct mlx5_ib_create_qp ucmd; 659 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 660 int page_shift = 0; 661 int uar_index; 662 int npages; 663 u32 offset = 0; 664 int uuarn; 665 int ncont = 0; 666 int err; 667 668 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 669 if (err) { 670 mlx5_ib_dbg(dev, "copy failed\n"); 671 return err; 672 } 673 674 context = to_mucontext(pd->uobject->context); 675 /* 676 * TBD: should come from the verbs when we have the API 677 */ 678 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 679 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 680 uuarn = MLX5_CROSS_CHANNEL_UUAR; 681 else { 682 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 683 if (uuarn < 0) { 684 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 685 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 686 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 687 if (uuarn < 0) { 688 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 689 mlx5_ib_dbg(dev, "reverting to high latency\n"); 690 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 691 if (uuarn < 0) { 692 mlx5_ib_warn(dev, "uuar allocation failed\n"); 693 return uuarn; 694 } 695 } 696 } 697 } 698 699 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 700 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 701 702 qp->rq.offset = 0; 703 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 704 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 705 706 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 707 if (err) 708 goto err_uuar; 709 710 if (ucmd.buf_addr && ubuffer->buf_size) { 711 ubuffer->buf_addr = ucmd.buf_addr; 712 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 713 ubuffer->buf_size, 714 &ubuffer->umem, &npages, &page_shift, 715 &ncont, &offset); 716 if (err) 717 goto err_uuar; 718 } else { 719 ubuffer->umem = NULL; 720 } 721 722 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont; 723 *in = mlx5_vzalloc(*inlen); 724 if (!*in) { 725 err = -ENOMEM; 726 goto err_umem; 727 } 728 if (ubuffer->umem) 729 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, 730 (*in)->pas, 0); 731 (*in)->ctx.log_pg_sz_remote_qpn = 732 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 733 (*in)->ctx.params2 = cpu_to_be32(offset << 6); 734 735 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 736 resp->uuar_index = uuarn; 737 qp->uuarn = uuarn; 738 739 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 740 if (err) { 741 mlx5_ib_dbg(dev, "map failed\n"); 742 goto err_free; 743 } 744 745 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 746 if (err) { 747 mlx5_ib_dbg(dev, "copy failed\n"); 748 goto err_unmap; 749 } 750 qp->create_type = MLX5_QP_USER; 751 752 return 0; 753 754 err_unmap: 755 mlx5_ib_db_unmap_user(context, &qp->db); 756 757 err_free: 758 kvfree(*in); 759 760 err_umem: 761 if (ubuffer->umem) 762 ib_umem_release(ubuffer->umem); 763 764 err_uuar: 765 free_uuar(&context->uuari, uuarn); 766 return err; 767 } 768 769 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp, 770 struct mlx5_ib_qp_base *base) 771 { 772 struct mlx5_ib_ucontext *context; 773 774 context = to_mucontext(pd->uobject->context); 775 mlx5_ib_db_unmap_user(context, &qp->db); 776 if (base->ubuffer.umem) 777 ib_umem_release(base->ubuffer.umem); 778 free_uuar(&context->uuari, qp->uuarn); 779 } 780 781 static int create_kernel_qp(struct mlx5_ib_dev *dev, 782 struct ib_qp_init_attr *init_attr, 783 struct mlx5_ib_qp *qp, 784 struct mlx5_create_qp_mbox_in **in, int *inlen, 785 struct mlx5_ib_qp_base *base) 786 { 787 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 788 struct mlx5_uuar_info *uuari; 789 int uar_index; 790 int uuarn; 791 int err; 792 793 uuari = &dev->mdev->priv.uuari; 794 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 795 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 796 IB_QP_CREATE_IPOIB_UD_LSO | 797 mlx5_ib_create_qp_sqpn_qp1())) 798 return -EINVAL; 799 800 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 801 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 802 803 uuarn = alloc_uuar(uuari, lc); 804 if (uuarn < 0) { 805 mlx5_ib_dbg(dev, "\n"); 806 return -ENOMEM; 807 } 808 809 qp->bf = &uuari->bfs[uuarn]; 810 uar_index = qp->bf->uar->index; 811 812 err = calc_sq_size(dev, init_attr, qp); 813 if (err < 0) { 814 mlx5_ib_dbg(dev, "err %d\n", err); 815 goto err_uuar; 816 } 817 818 qp->rq.offset = 0; 819 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 820 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 821 822 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 823 if (err) { 824 mlx5_ib_dbg(dev, "err %d\n", err); 825 goto err_uuar; 826 } 827 828 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 829 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages; 830 *in = mlx5_vzalloc(*inlen); 831 if (!*in) { 832 err = -ENOMEM; 833 goto err_buf; 834 } 835 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 836 (*in)->ctx.log_pg_sz_remote_qpn = 837 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 838 /* Set "fast registration enabled" for all kernel QPs */ 839 (*in)->ctx.params1 |= cpu_to_be32(1 << 11); 840 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4); 841 842 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 843 (*in)->ctx.deth_sqpn = cpu_to_be32(1); 844 qp->flags |= MLX5_IB_QP_SQPN_QP1; 845 } 846 847 mlx5_fill_page_array(&qp->buf, (*in)->pas); 848 849 err = mlx5_db_alloc(dev->mdev, &qp->db); 850 if (err) { 851 mlx5_ib_dbg(dev, "err %d\n", err); 852 goto err_free; 853 } 854 855 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 856 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 857 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 858 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 859 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 860 861 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 862 !qp->sq.w_list || !qp->sq.wqe_head) { 863 err = -ENOMEM; 864 goto err_wrid; 865 } 866 qp->create_type = MLX5_QP_KERNEL; 867 868 return 0; 869 870 err_wrid: 871 mlx5_db_free(dev->mdev, &qp->db); 872 kfree(qp->sq.wqe_head); 873 kfree(qp->sq.w_list); 874 kfree(qp->sq.wrid); 875 kfree(qp->sq.wr_data); 876 kfree(qp->rq.wrid); 877 878 err_free: 879 kvfree(*in); 880 881 err_buf: 882 mlx5_buf_free(dev->mdev, &qp->buf); 883 884 err_uuar: 885 free_uuar(&dev->mdev->priv.uuari, uuarn); 886 return err; 887 } 888 889 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 890 { 891 mlx5_db_free(dev->mdev, &qp->db); 892 kfree(qp->sq.wqe_head); 893 kfree(qp->sq.w_list); 894 kfree(qp->sq.wrid); 895 kfree(qp->sq.wr_data); 896 kfree(qp->rq.wrid); 897 mlx5_buf_free(dev->mdev, &qp->buf); 898 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn); 899 } 900 901 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 902 { 903 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 904 (attr->qp_type == IB_QPT_XRC_INI)) 905 return cpu_to_be32(MLX5_SRQ_RQ); 906 else if (!qp->has_rq) 907 return cpu_to_be32(MLX5_ZERO_LEN_RQ); 908 else 909 return cpu_to_be32(MLX5_NON_ZERO_RQ); 910 } 911 912 static int is_connected(enum ib_qp_type qp_type) 913 { 914 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 915 return 1; 916 917 return 0; 918 } 919 920 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 921 struct mlx5_ib_sq *sq, u32 tdn) 922 { 923 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 924 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 925 926 memset(in, 0, sizeof(in)); 927 928 MLX5_SET(tisc, tisc, transport_domain, tdn); 929 930 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 931 } 932 933 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 934 struct mlx5_ib_sq *sq) 935 { 936 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 937 } 938 939 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 940 struct mlx5_ib_sq *sq, void *qpin, 941 struct ib_pd *pd) 942 { 943 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 944 __be64 *pas; 945 void *in; 946 void *sqc; 947 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 948 void *wq; 949 int inlen; 950 int err; 951 int page_shift = 0; 952 int npages; 953 int ncont = 0; 954 u32 offset = 0; 955 956 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 957 &sq->ubuffer.umem, &npages, &page_shift, 958 &ncont, &offset); 959 if (err) 960 return err; 961 962 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 963 in = mlx5_vzalloc(inlen); 964 if (!in) { 965 err = -ENOMEM; 966 goto err_umem; 967 } 968 969 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 970 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 971 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 972 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 973 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 974 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 975 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 976 977 wq = MLX5_ADDR_OF(sqc, sqc, wq); 978 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 979 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 980 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 981 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 982 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 983 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 984 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 985 MLX5_SET(wq, wq, page_offset, offset); 986 987 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 988 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 989 990 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 991 992 kvfree(in); 993 994 if (err) 995 goto err_umem; 996 997 return 0; 998 999 err_umem: 1000 ib_umem_release(sq->ubuffer.umem); 1001 sq->ubuffer.umem = NULL; 1002 1003 return err; 1004 } 1005 1006 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1007 struct mlx5_ib_sq *sq) 1008 { 1009 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1010 ib_umem_release(sq->ubuffer.umem); 1011 } 1012 1013 static int get_rq_pas_size(void *qpc) 1014 { 1015 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1016 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1017 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1018 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1019 u32 po_quanta = 1 << (log_page_size - 6); 1020 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1021 u32 page_size = 1 << log_page_size; 1022 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1023 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1024 1025 return rq_num_pas * sizeof(u64); 1026 } 1027 1028 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1029 struct mlx5_ib_rq *rq, void *qpin) 1030 { 1031 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1032 __be64 *pas; 1033 __be64 *qp_pas; 1034 void *in; 1035 void *rqc; 1036 void *wq; 1037 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1038 int inlen; 1039 int err; 1040 u32 rq_pas_size = get_rq_pas_size(qpc); 1041 1042 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1043 in = mlx5_vzalloc(inlen); 1044 if (!in) 1045 return -ENOMEM; 1046 1047 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1048 MLX5_SET(rqc, rqc, vsd, 1); 1049 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1050 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1051 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1052 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1053 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1054 1055 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1056 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1057 1058 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1059 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1060 MLX5_SET(wq, wq, end_padding_mode, 1061 MLX5_GET(qpc, qpc, end_padding_mode)); 1062 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1063 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1064 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1065 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1066 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1067 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1068 1069 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1070 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1071 memcpy(pas, qp_pas, rq_pas_size); 1072 1073 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1074 1075 kvfree(in); 1076 1077 return err; 1078 } 1079 1080 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1081 struct mlx5_ib_rq *rq) 1082 { 1083 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1084 } 1085 1086 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1087 struct mlx5_ib_rq *rq, u32 tdn) 1088 { 1089 u32 *in; 1090 void *tirc; 1091 int inlen; 1092 int err; 1093 1094 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1095 in = mlx5_vzalloc(inlen); 1096 if (!in) 1097 return -ENOMEM; 1098 1099 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1100 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1101 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1102 MLX5_SET(tirc, tirc, transport_domain, tdn); 1103 1104 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1105 1106 kvfree(in); 1107 1108 return err; 1109 } 1110 1111 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1112 struct mlx5_ib_rq *rq) 1113 { 1114 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1115 } 1116 1117 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1118 struct mlx5_create_qp_mbox_in *in, 1119 struct ib_pd *pd) 1120 { 1121 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1122 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1123 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1124 struct ib_uobject *uobj = pd->uobject; 1125 struct ib_ucontext *ucontext = uobj->context; 1126 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1127 int err; 1128 u32 tdn = mucontext->tdn; 1129 1130 if (qp->sq.wqe_cnt) { 1131 err = create_raw_packet_qp_tis(dev, sq, tdn); 1132 if (err) 1133 return err; 1134 1135 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1136 if (err) 1137 goto err_destroy_tis; 1138 1139 sq->base.container_mibqp = qp; 1140 } 1141 1142 if (qp->rq.wqe_cnt) { 1143 rq->base.container_mibqp = qp; 1144 1145 err = create_raw_packet_qp_rq(dev, rq, in); 1146 if (err) 1147 goto err_destroy_sq; 1148 1149 1150 err = create_raw_packet_qp_tir(dev, rq, tdn); 1151 if (err) 1152 goto err_destroy_rq; 1153 } 1154 1155 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1156 rq->base.mqp.qpn; 1157 1158 return 0; 1159 1160 err_destroy_rq: 1161 destroy_raw_packet_qp_rq(dev, rq); 1162 err_destroy_sq: 1163 if (!qp->sq.wqe_cnt) 1164 return err; 1165 destroy_raw_packet_qp_sq(dev, sq); 1166 err_destroy_tis: 1167 destroy_raw_packet_qp_tis(dev, sq); 1168 1169 return err; 1170 } 1171 1172 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1173 struct mlx5_ib_qp *qp) 1174 { 1175 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1176 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1177 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1178 1179 if (qp->rq.wqe_cnt) { 1180 destroy_raw_packet_qp_tir(dev, rq); 1181 destroy_raw_packet_qp_rq(dev, rq); 1182 } 1183 1184 if (qp->sq.wqe_cnt) { 1185 destroy_raw_packet_qp_sq(dev, sq); 1186 destroy_raw_packet_qp_tis(dev, sq); 1187 } 1188 } 1189 1190 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1191 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1192 { 1193 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1194 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1195 1196 sq->sq = &qp->sq; 1197 rq->rq = &qp->rq; 1198 sq->doorbell = &qp->db; 1199 rq->doorbell = &qp->db; 1200 } 1201 1202 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1203 struct ib_qp_init_attr *init_attr, 1204 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1205 { 1206 struct mlx5_ib_resources *devr = &dev->devr; 1207 struct mlx5_core_dev *mdev = dev->mdev; 1208 struct mlx5_ib_qp_base *base; 1209 struct mlx5_ib_create_qp_resp resp; 1210 struct mlx5_create_qp_mbox_in *in; 1211 struct mlx5_ib_create_qp ucmd; 1212 int inlen = sizeof(*in); 1213 int err; 1214 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1215 void *qpc; 1216 1217 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1218 &qp->raw_packet_qp.rq.base : 1219 &qp->trans_qp.base; 1220 1221 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1222 mlx5_ib_odp_create_qp(qp); 1223 1224 mutex_init(&qp->mutex); 1225 spin_lock_init(&qp->sq.lock); 1226 spin_lock_init(&qp->rq.lock); 1227 1228 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1229 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1230 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1231 return -EINVAL; 1232 } else { 1233 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1234 } 1235 } 1236 1237 if (init_attr->create_flags & 1238 (IB_QP_CREATE_CROSS_CHANNEL | 1239 IB_QP_CREATE_MANAGED_SEND | 1240 IB_QP_CREATE_MANAGED_RECV)) { 1241 if (!MLX5_CAP_GEN(mdev, cd)) { 1242 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1243 return -EINVAL; 1244 } 1245 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1246 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1247 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1248 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1249 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1250 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1251 } 1252 1253 if (init_attr->qp_type == IB_QPT_UD && 1254 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1255 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1256 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1257 return -EOPNOTSUPP; 1258 } 1259 1260 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1261 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1262 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1263 return -EOPNOTSUPP; 1264 } 1265 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1266 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1267 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1268 return -EOPNOTSUPP; 1269 } 1270 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1271 } 1272 1273 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1274 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1275 1276 if (pd && pd->uobject) { 1277 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1278 mlx5_ib_dbg(dev, "copy failed\n"); 1279 return -EFAULT; 1280 } 1281 1282 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1283 &ucmd, udata->inlen, &uidx); 1284 if (err) 1285 return err; 1286 1287 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1288 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1289 } else { 1290 qp->wq_sig = !!wq_signature; 1291 } 1292 1293 qp->has_rq = qp_has_rq(init_attr); 1294 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1295 qp, (pd && pd->uobject) ? &ucmd : NULL); 1296 if (err) { 1297 mlx5_ib_dbg(dev, "err %d\n", err); 1298 return err; 1299 } 1300 1301 if (pd) { 1302 if (pd->uobject) { 1303 __u32 max_wqes = 1304 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1305 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1306 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1307 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1308 mlx5_ib_dbg(dev, "invalid rq params\n"); 1309 return -EINVAL; 1310 } 1311 if (ucmd.sq_wqe_count > max_wqes) { 1312 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1313 ucmd.sq_wqe_count, max_wqes); 1314 return -EINVAL; 1315 } 1316 if (init_attr->create_flags & 1317 mlx5_ib_create_qp_sqpn_qp1()) { 1318 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1319 return -EINVAL; 1320 } 1321 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1322 &resp, &inlen, base); 1323 if (err) 1324 mlx5_ib_dbg(dev, "err %d\n", err); 1325 } else { 1326 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1327 base); 1328 if (err) 1329 mlx5_ib_dbg(dev, "err %d\n", err); 1330 } 1331 1332 if (err) 1333 return err; 1334 } else { 1335 in = mlx5_vzalloc(sizeof(*in)); 1336 if (!in) 1337 return -ENOMEM; 1338 1339 qp->create_type = MLX5_QP_EMPTY; 1340 } 1341 1342 if (is_sqp(init_attr->qp_type)) 1343 qp->port = init_attr->port_num; 1344 1345 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 | 1346 MLX5_QP_PM_MIGRATED << 11); 1347 1348 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1349 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn); 1350 else 1351 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE); 1352 1353 if (qp->wq_sig) 1354 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG); 1355 1356 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1357 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST); 1358 1359 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1360 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER); 1361 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1362 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND); 1363 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1364 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV); 1365 1366 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1367 int rcqe_sz; 1368 int scqe_sz; 1369 1370 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1371 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1372 1373 if (rcqe_sz == 128) 1374 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE; 1375 else 1376 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE; 1377 1378 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1379 if (scqe_sz == 128) 1380 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE; 1381 else 1382 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE; 1383 } 1384 } 1385 1386 if (qp->rq.wqe_cnt) { 1387 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4); 1388 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3; 1389 } 1390 1391 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr); 1392 1393 if (qp->sq.wqe_cnt) 1394 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11); 1395 else 1396 in->ctx.sq_crq_size |= cpu_to_be16(0x8000); 1397 1398 /* Set default resources */ 1399 switch (init_attr->qp_type) { 1400 case IB_QPT_XRC_TGT: 1401 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1402 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1403 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1404 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn); 1405 break; 1406 case IB_QPT_XRC_INI: 1407 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1408 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1409 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1410 break; 1411 default: 1412 if (init_attr->srq) { 1413 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn); 1414 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn); 1415 } else { 1416 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1417 in->ctx.rq_type_srqn |= 1418 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn); 1419 } 1420 } 1421 1422 if (init_attr->send_cq) 1423 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn); 1424 1425 if (init_attr->recv_cq) 1426 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn); 1427 1428 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma); 1429 1430 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) { 1431 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1432 /* 0xffffff means we ask to work with cqe version 0 */ 1433 MLX5_SET(qpc, qpc, user_index, uidx); 1434 } 1435 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1436 if (init_attr->qp_type == IB_QPT_UD && 1437 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1438 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1439 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1440 qp->flags |= MLX5_IB_QP_LSO; 1441 } 1442 1443 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1444 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1445 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1446 err = create_raw_packet_qp(dev, qp, in, pd); 1447 } else { 1448 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1449 } 1450 1451 if (err) { 1452 mlx5_ib_dbg(dev, "create qp failed\n"); 1453 goto err_create; 1454 } 1455 1456 kvfree(in); 1457 1458 base->container_mibqp = qp; 1459 base->mqp.event = mlx5_ib_qp_event; 1460 1461 return 0; 1462 1463 err_create: 1464 if (qp->create_type == MLX5_QP_USER) 1465 destroy_qp_user(pd, qp, base); 1466 else if (qp->create_type == MLX5_QP_KERNEL) 1467 destroy_qp_kernel(dev, qp); 1468 1469 kvfree(in); 1470 return err; 1471 } 1472 1473 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1474 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1475 { 1476 if (send_cq) { 1477 if (recv_cq) { 1478 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1479 spin_lock_irq(&send_cq->lock); 1480 spin_lock_nested(&recv_cq->lock, 1481 SINGLE_DEPTH_NESTING); 1482 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1483 spin_lock_irq(&send_cq->lock); 1484 __acquire(&recv_cq->lock); 1485 } else { 1486 spin_lock_irq(&recv_cq->lock); 1487 spin_lock_nested(&send_cq->lock, 1488 SINGLE_DEPTH_NESTING); 1489 } 1490 } else { 1491 spin_lock_irq(&send_cq->lock); 1492 __acquire(&recv_cq->lock); 1493 } 1494 } else if (recv_cq) { 1495 spin_lock_irq(&recv_cq->lock); 1496 __acquire(&send_cq->lock); 1497 } else { 1498 __acquire(&send_cq->lock); 1499 __acquire(&recv_cq->lock); 1500 } 1501 } 1502 1503 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1504 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1505 { 1506 if (send_cq) { 1507 if (recv_cq) { 1508 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1509 spin_unlock(&recv_cq->lock); 1510 spin_unlock_irq(&send_cq->lock); 1511 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1512 __release(&recv_cq->lock); 1513 spin_unlock_irq(&send_cq->lock); 1514 } else { 1515 spin_unlock(&send_cq->lock); 1516 spin_unlock_irq(&recv_cq->lock); 1517 } 1518 } else { 1519 __release(&recv_cq->lock); 1520 spin_unlock_irq(&send_cq->lock); 1521 } 1522 } else if (recv_cq) { 1523 __release(&send_cq->lock); 1524 spin_unlock_irq(&recv_cq->lock); 1525 } else { 1526 __release(&recv_cq->lock); 1527 __release(&send_cq->lock); 1528 } 1529 } 1530 1531 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1532 { 1533 return to_mpd(qp->ibqp.pd); 1534 } 1535 1536 static void get_cqs(struct mlx5_ib_qp *qp, 1537 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1538 { 1539 switch (qp->ibqp.qp_type) { 1540 case IB_QPT_XRC_TGT: 1541 *send_cq = NULL; 1542 *recv_cq = NULL; 1543 break; 1544 case MLX5_IB_QPT_REG_UMR: 1545 case IB_QPT_XRC_INI: 1546 *send_cq = to_mcq(qp->ibqp.send_cq); 1547 *recv_cq = NULL; 1548 break; 1549 1550 case IB_QPT_SMI: 1551 case MLX5_IB_QPT_HW_GSI: 1552 case IB_QPT_RC: 1553 case IB_QPT_UC: 1554 case IB_QPT_UD: 1555 case IB_QPT_RAW_IPV6: 1556 case IB_QPT_RAW_ETHERTYPE: 1557 case IB_QPT_RAW_PACKET: 1558 *send_cq = to_mcq(qp->ibqp.send_cq); 1559 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1560 break; 1561 1562 case IB_QPT_MAX: 1563 default: 1564 *send_cq = NULL; 1565 *recv_cq = NULL; 1566 break; 1567 } 1568 } 1569 1570 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1571 u16 operation); 1572 1573 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1574 { 1575 struct mlx5_ib_cq *send_cq, *recv_cq; 1576 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1577 struct mlx5_modify_qp_mbox_in *in; 1578 int err; 1579 1580 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 1581 &qp->raw_packet_qp.rq.base : 1582 &qp->trans_qp.base; 1583 1584 in = kzalloc(sizeof(*in), GFP_KERNEL); 1585 if (!in) 1586 return; 1587 1588 if (qp->state != IB_QPS_RESET) { 1589 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 1590 mlx5_ib_qp_disable_pagefaults(qp); 1591 err = mlx5_core_qp_modify(dev->mdev, 1592 MLX5_CMD_OP_2RST_QP, in, 0, 1593 &base->mqp); 1594 } else { 1595 err = modify_raw_packet_qp(dev, qp, 1596 MLX5_CMD_OP_2RST_QP); 1597 } 1598 if (err) 1599 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1600 base->mqp.qpn); 1601 } 1602 1603 get_cqs(qp, &send_cq, &recv_cq); 1604 1605 if (qp->create_type == MLX5_QP_KERNEL) { 1606 mlx5_ib_lock_cqs(send_cq, recv_cq); 1607 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 1608 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1609 if (send_cq != recv_cq) 1610 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 1611 NULL); 1612 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1613 } 1614 1615 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1616 destroy_raw_packet_qp(dev, qp); 1617 } else { 1618 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 1619 if (err) 1620 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 1621 base->mqp.qpn); 1622 } 1623 1624 kfree(in); 1625 1626 if (qp->create_type == MLX5_QP_KERNEL) 1627 destroy_qp_kernel(dev, qp); 1628 else if (qp->create_type == MLX5_QP_USER) 1629 destroy_qp_user(&get_pd(qp)->ibpd, qp, base); 1630 } 1631 1632 static const char *ib_qp_type_str(enum ib_qp_type type) 1633 { 1634 switch (type) { 1635 case IB_QPT_SMI: 1636 return "IB_QPT_SMI"; 1637 case IB_QPT_GSI: 1638 return "IB_QPT_GSI"; 1639 case IB_QPT_RC: 1640 return "IB_QPT_RC"; 1641 case IB_QPT_UC: 1642 return "IB_QPT_UC"; 1643 case IB_QPT_UD: 1644 return "IB_QPT_UD"; 1645 case IB_QPT_RAW_IPV6: 1646 return "IB_QPT_RAW_IPV6"; 1647 case IB_QPT_RAW_ETHERTYPE: 1648 return "IB_QPT_RAW_ETHERTYPE"; 1649 case IB_QPT_XRC_INI: 1650 return "IB_QPT_XRC_INI"; 1651 case IB_QPT_XRC_TGT: 1652 return "IB_QPT_XRC_TGT"; 1653 case IB_QPT_RAW_PACKET: 1654 return "IB_QPT_RAW_PACKET"; 1655 case MLX5_IB_QPT_REG_UMR: 1656 return "MLX5_IB_QPT_REG_UMR"; 1657 case IB_QPT_MAX: 1658 default: 1659 return "Invalid QP type"; 1660 } 1661 } 1662 1663 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1664 struct ib_qp_init_attr *init_attr, 1665 struct ib_udata *udata) 1666 { 1667 struct mlx5_ib_dev *dev; 1668 struct mlx5_ib_qp *qp; 1669 u16 xrcdn = 0; 1670 int err; 1671 1672 if (pd) { 1673 dev = to_mdev(pd->device); 1674 1675 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1676 if (!pd->uobject) { 1677 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 1678 return ERR_PTR(-EINVAL); 1679 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 1680 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 1681 return ERR_PTR(-EINVAL); 1682 } 1683 } 1684 } else { 1685 /* being cautious here */ 1686 if (init_attr->qp_type != IB_QPT_XRC_TGT && 1687 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 1688 pr_warn("%s: no PD for transport %s\n", __func__, 1689 ib_qp_type_str(init_attr->qp_type)); 1690 return ERR_PTR(-EINVAL); 1691 } 1692 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 1693 } 1694 1695 switch (init_attr->qp_type) { 1696 case IB_QPT_XRC_TGT: 1697 case IB_QPT_XRC_INI: 1698 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 1699 mlx5_ib_dbg(dev, "XRC not supported\n"); 1700 return ERR_PTR(-ENOSYS); 1701 } 1702 init_attr->recv_cq = NULL; 1703 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 1704 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1705 init_attr->send_cq = NULL; 1706 } 1707 1708 /* fall through */ 1709 case IB_QPT_RAW_PACKET: 1710 case IB_QPT_RC: 1711 case IB_QPT_UC: 1712 case IB_QPT_UD: 1713 case IB_QPT_SMI: 1714 case MLX5_IB_QPT_HW_GSI: 1715 case MLX5_IB_QPT_REG_UMR: 1716 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1717 if (!qp) 1718 return ERR_PTR(-ENOMEM); 1719 1720 err = create_qp_common(dev, pd, init_attr, udata, qp); 1721 if (err) { 1722 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 1723 kfree(qp); 1724 return ERR_PTR(err); 1725 } 1726 1727 if (is_qp0(init_attr->qp_type)) 1728 qp->ibqp.qp_num = 0; 1729 else if (is_qp1(init_attr->qp_type)) 1730 qp->ibqp.qp_num = 1; 1731 else 1732 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 1733 1734 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 1735 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 1736 to_mcq(init_attr->recv_cq)->mcq.cqn, 1737 to_mcq(init_attr->send_cq)->mcq.cqn); 1738 1739 qp->trans_qp.xrcdn = xrcdn; 1740 1741 break; 1742 1743 case IB_QPT_GSI: 1744 return mlx5_ib_gsi_create_qp(pd, init_attr); 1745 1746 case IB_QPT_RAW_IPV6: 1747 case IB_QPT_RAW_ETHERTYPE: 1748 case IB_QPT_MAX: 1749 default: 1750 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 1751 init_attr->qp_type); 1752 /* Don't support raw QPs */ 1753 return ERR_PTR(-EINVAL); 1754 } 1755 1756 return &qp->ibqp; 1757 } 1758 1759 int mlx5_ib_destroy_qp(struct ib_qp *qp) 1760 { 1761 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1762 struct mlx5_ib_qp *mqp = to_mqp(qp); 1763 1764 if (unlikely(qp->qp_type == IB_QPT_GSI)) 1765 return mlx5_ib_gsi_destroy_qp(qp); 1766 1767 destroy_qp_common(dev, mqp); 1768 1769 kfree(mqp); 1770 1771 return 0; 1772 } 1773 1774 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 1775 int attr_mask) 1776 { 1777 u32 hw_access_flags = 0; 1778 u8 dest_rd_atomic; 1779 u32 access_flags; 1780 1781 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1782 dest_rd_atomic = attr->max_dest_rd_atomic; 1783 else 1784 dest_rd_atomic = qp->trans_qp.resp_depth; 1785 1786 if (attr_mask & IB_QP_ACCESS_FLAGS) 1787 access_flags = attr->qp_access_flags; 1788 else 1789 access_flags = qp->trans_qp.atomic_rd_en; 1790 1791 if (!dest_rd_atomic) 1792 access_flags &= IB_ACCESS_REMOTE_WRITE; 1793 1794 if (access_flags & IB_ACCESS_REMOTE_READ) 1795 hw_access_flags |= MLX5_QP_BIT_RRE; 1796 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1797 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 1798 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1799 hw_access_flags |= MLX5_QP_BIT_RWE; 1800 1801 return cpu_to_be32(hw_access_flags); 1802 } 1803 1804 enum { 1805 MLX5_PATH_FLAG_FL = 1 << 0, 1806 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 1807 MLX5_PATH_FLAG_COUNTER = 1 << 2, 1808 }; 1809 1810 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 1811 { 1812 if (rate == IB_RATE_PORT_CURRENT) { 1813 return 0; 1814 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 1815 return -EINVAL; 1816 } else { 1817 while (rate != IB_RATE_2_5_GBPS && 1818 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 1819 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 1820 --rate; 1821 } 1822 1823 return rate + MLX5_STAT_RATE_OFFSET; 1824 } 1825 1826 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 1827 struct mlx5_ib_sq *sq, u8 sl) 1828 { 1829 void *in; 1830 void *tisc; 1831 int inlen; 1832 int err; 1833 1834 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 1835 in = mlx5_vzalloc(inlen); 1836 if (!in) 1837 return -ENOMEM; 1838 1839 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 1840 1841 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 1842 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 1843 1844 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 1845 1846 kvfree(in); 1847 1848 return err; 1849 } 1850 1851 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1852 const struct ib_ah_attr *ah, 1853 struct mlx5_qp_path *path, u8 port, int attr_mask, 1854 u32 path_flags, const struct ib_qp_attr *attr) 1855 { 1856 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 1857 int err; 1858 1859 if (attr_mask & IB_QP_PKEY_INDEX) 1860 path->pkey_index = attr->pkey_index; 1861 1862 if (ah->ah_flags & IB_AH_GRH) { 1863 if (ah->grh.sgid_index >= 1864 dev->mdev->port_caps[port - 1].gid_table_len) { 1865 pr_err("sgid_index (%u) too large. max is %d\n", 1866 ah->grh.sgid_index, 1867 dev->mdev->port_caps[port - 1].gid_table_len); 1868 return -EINVAL; 1869 } 1870 } 1871 1872 if (ll == IB_LINK_LAYER_ETHERNET) { 1873 if (!(ah->ah_flags & IB_AH_GRH)) 1874 return -EINVAL; 1875 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 1876 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 1877 ah->grh.sgid_index); 1878 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 1879 } else { 1880 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 1881 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 1882 0; 1883 path->rlid = cpu_to_be16(ah->dlid); 1884 path->grh_mlid = ah->src_path_bits & 0x7f; 1885 if (ah->ah_flags & IB_AH_GRH) 1886 path->grh_mlid |= 1 << 7; 1887 path->dci_cfi_prio_sl = ah->sl & 0xf; 1888 } 1889 1890 if (ah->ah_flags & IB_AH_GRH) { 1891 path->mgid_index = ah->grh.sgid_index; 1892 path->hop_limit = ah->grh.hop_limit; 1893 path->tclass_flowlabel = 1894 cpu_to_be32((ah->grh.traffic_class << 20) | 1895 (ah->grh.flow_label)); 1896 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1897 } 1898 1899 err = ib_rate_to_mlx5(dev, ah->static_rate); 1900 if (err < 0) 1901 return err; 1902 path->static_rate = err; 1903 path->port = port; 1904 1905 if (attr_mask & IB_QP_TIMEOUT) 1906 path->ackto_lt = attr->timeout << 3; 1907 1908 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 1909 return modify_raw_packet_eth_prio(dev->mdev, 1910 &qp->raw_packet_qp.sq, 1911 ah->sl & 0xf); 1912 1913 return 0; 1914 } 1915 1916 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 1917 [MLX5_QP_STATE_INIT] = { 1918 [MLX5_QP_STATE_INIT] = { 1919 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1920 MLX5_QP_OPTPAR_RAE | 1921 MLX5_QP_OPTPAR_RWE | 1922 MLX5_QP_OPTPAR_PKEY_INDEX | 1923 MLX5_QP_OPTPAR_PRI_PORT, 1924 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1925 MLX5_QP_OPTPAR_PKEY_INDEX | 1926 MLX5_QP_OPTPAR_PRI_PORT, 1927 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1928 MLX5_QP_OPTPAR_Q_KEY | 1929 MLX5_QP_OPTPAR_PRI_PORT, 1930 }, 1931 [MLX5_QP_STATE_RTR] = { 1932 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1933 MLX5_QP_OPTPAR_RRE | 1934 MLX5_QP_OPTPAR_RAE | 1935 MLX5_QP_OPTPAR_RWE | 1936 MLX5_QP_OPTPAR_PKEY_INDEX, 1937 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1938 MLX5_QP_OPTPAR_RWE | 1939 MLX5_QP_OPTPAR_PKEY_INDEX, 1940 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1941 MLX5_QP_OPTPAR_Q_KEY, 1942 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 1943 MLX5_QP_OPTPAR_Q_KEY, 1944 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1945 MLX5_QP_OPTPAR_RRE | 1946 MLX5_QP_OPTPAR_RAE | 1947 MLX5_QP_OPTPAR_RWE | 1948 MLX5_QP_OPTPAR_PKEY_INDEX, 1949 }, 1950 }, 1951 [MLX5_QP_STATE_RTR] = { 1952 [MLX5_QP_STATE_RTS] = { 1953 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1954 MLX5_QP_OPTPAR_RRE | 1955 MLX5_QP_OPTPAR_RAE | 1956 MLX5_QP_OPTPAR_RWE | 1957 MLX5_QP_OPTPAR_PM_STATE | 1958 MLX5_QP_OPTPAR_RNR_TIMEOUT, 1959 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1960 MLX5_QP_OPTPAR_RWE | 1961 MLX5_QP_OPTPAR_PM_STATE, 1962 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1963 }, 1964 }, 1965 [MLX5_QP_STATE_RTS] = { 1966 [MLX5_QP_STATE_RTS] = { 1967 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1968 MLX5_QP_OPTPAR_RAE | 1969 MLX5_QP_OPTPAR_RWE | 1970 MLX5_QP_OPTPAR_RNR_TIMEOUT | 1971 MLX5_QP_OPTPAR_PM_STATE | 1972 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1973 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1974 MLX5_QP_OPTPAR_PM_STATE | 1975 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1976 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 1977 MLX5_QP_OPTPAR_SRQN | 1978 MLX5_QP_OPTPAR_CQN_RCV, 1979 }, 1980 }, 1981 [MLX5_QP_STATE_SQER] = { 1982 [MLX5_QP_STATE_RTS] = { 1983 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1984 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 1985 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 1986 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 1987 MLX5_QP_OPTPAR_RWE | 1988 MLX5_QP_OPTPAR_RAE | 1989 MLX5_QP_OPTPAR_RRE, 1990 }, 1991 }, 1992 }; 1993 1994 static int ib_nr_to_mlx5_nr(int ib_mask) 1995 { 1996 switch (ib_mask) { 1997 case IB_QP_STATE: 1998 return 0; 1999 case IB_QP_CUR_STATE: 2000 return 0; 2001 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2002 return 0; 2003 case IB_QP_ACCESS_FLAGS: 2004 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2005 MLX5_QP_OPTPAR_RAE; 2006 case IB_QP_PKEY_INDEX: 2007 return MLX5_QP_OPTPAR_PKEY_INDEX; 2008 case IB_QP_PORT: 2009 return MLX5_QP_OPTPAR_PRI_PORT; 2010 case IB_QP_QKEY: 2011 return MLX5_QP_OPTPAR_Q_KEY; 2012 case IB_QP_AV: 2013 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2014 MLX5_QP_OPTPAR_PRI_PORT; 2015 case IB_QP_PATH_MTU: 2016 return 0; 2017 case IB_QP_TIMEOUT: 2018 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2019 case IB_QP_RETRY_CNT: 2020 return MLX5_QP_OPTPAR_RETRY_COUNT; 2021 case IB_QP_RNR_RETRY: 2022 return MLX5_QP_OPTPAR_RNR_RETRY; 2023 case IB_QP_RQ_PSN: 2024 return 0; 2025 case IB_QP_MAX_QP_RD_ATOMIC: 2026 return MLX5_QP_OPTPAR_SRA_MAX; 2027 case IB_QP_ALT_PATH: 2028 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2029 case IB_QP_MIN_RNR_TIMER: 2030 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2031 case IB_QP_SQ_PSN: 2032 return 0; 2033 case IB_QP_MAX_DEST_RD_ATOMIC: 2034 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2035 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2036 case IB_QP_PATH_MIG_STATE: 2037 return MLX5_QP_OPTPAR_PM_STATE; 2038 case IB_QP_CAP: 2039 return 0; 2040 case IB_QP_DEST_QPN: 2041 return 0; 2042 } 2043 return 0; 2044 } 2045 2046 static int ib_mask_to_mlx5_opt(int ib_mask) 2047 { 2048 int result = 0; 2049 int i; 2050 2051 for (i = 0; i < 8 * sizeof(int); i++) { 2052 if ((1 << i) & ib_mask) 2053 result |= ib_nr_to_mlx5_nr(1 << i); 2054 } 2055 2056 return result; 2057 } 2058 2059 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev, 2060 struct mlx5_ib_rq *rq, int new_state) 2061 { 2062 void *in; 2063 void *rqc; 2064 int inlen; 2065 int err; 2066 2067 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2068 in = mlx5_vzalloc(inlen); 2069 if (!in) 2070 return -ENOMEM; 2071 2072 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2073 2074 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2075 MLX5_SET(rqc, rqc, state, new_state); 2076 2077 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen); 2078 if (err) 2079 goto out; 2080 2081 rq->state = new_state; 2082 2083 out: 2084 kvfree(in); 2085 return err; 2086 } 2087 2088 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2089 struct mlx5_ib_sq *sq, int new_state) 2090 { 2091 void *in; 2092 void *sqc; 2093 int inlen; 2094 int err; 2095 2096 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2097 in = mlx5_vzalloc(inlen); 2098 if (!in) 2099 return -ENOMEM; 2100 2101 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2102 2103 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2104 MLX5_SET(sqc, sqc, state, new_state); 2105 2106 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2107 if (err) 2108 goto out; 2109 2110 sq->state = new_state; 2111 2112 out: 2113 kvfree(in); 2114 return err; 2115 } 2116 2117 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2118 u16 operation) 2119 { 2120 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2121 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2122 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2123 int rq_state; 2124 int sq_state; 2125 int err; 2126 2127 switch (operation) { 2128 case MLX5_CMD_OP_RST2INIT_QP: 2129 rq_state = MLX5_RQC_STATE_RDY; 2130 sq_state = MLX5_SQC_STATE_RDY; 2131 break; 2132 case MLX5_CMD_OP_2ERR_QP: 2133 rq_state = MLX5_RQC_STATE_ERR; 2134 sq_state = MLX5_SQC_STATE_ERR; 2135 break; 2136 case MLX5_CMD_OP_2RST_QP: 2137 rq_state = MLX5_RQC_STATE_RST; 2138 sq_state = MLX5_SQC_STATE_RST; 2139 break; 2140 case MLX5_CMD_OP_INIT2INIT_QP: 2141 case MLX5_CMD_OP_INIT2RTR_QP: 2142 case MLX5_CMD_OP_RTR2RTS_QP: 2143 case MLX5_CMD_OP_RTS2RTS_QP: 2144 /* Nothing to do here... */ 2145 return 0; 2146 default: 2147 WARN_ON(1); 2148 return -EINVAL; 2149 } 2150 2151 if (qp->rq.wqe_cnt) { 2152 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state); 2153 if (err) 2154 return err; 2155 } 2156 2157 if (qp->sq.wqe_cnt) 2158 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state); 2159 2160 return 0; 2161 } 2162 2163 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2164 const struct ib_qp_attr *attr, int attr_mask, 2165 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2166 { 2167 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2168 [MLX5_QP_STATE_RST] = { 2169 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2170 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2171 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2172 }, 2173 [MLX5_QP_STATE_INIT] = { 2174 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2175 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2176 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2177 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2178 }, 2179 [MLX5_QP_STATE_RTR] = { 2180 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2181 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2182 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2183 }, 2184 [MLX5_QP_STATE_RTS] = { 2185 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2186 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2187 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2188 }, 2189 [MLX5_QP_STATE_SQD] = { 2190 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2191 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2192 }, 2193 [MLX5_QP_STATE_SQER] = { 2194 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2195 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2196 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2197 }, 2198 [MLX5_QP_STATE_ERR] = { 2199 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2200 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2201 } 2202 }; 2203 2204 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2205 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2206 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2207 struct mlx5_ib_cq *send_cq, *recv_cq; 2208 struct mlx5_qp_context *context; 2209 struct mlx5_modify_qp_mbox_in *in; 2210 struct mlx5_ib_pd *pd; 2211 enum mlx5_qp_state mlx5_cur, mlx5_new; 2212 enum mlx5_qp_optpar optpar; 2213 int sqd_event; 2214 int mlx5_st; 2215 int err; 2216 u16 op; 2217 2218 in = kzalloc(sizeof(*in), GFP_KERNEL); 2219 if (!in) 2220 return -ENOMEM; 2221 2222 context = &in->ctx; 2223 err = to_mlx5_st(ibqp->qp_type); 2224 if (err < 0) { 2225 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2226 goto out; 2227 } 2228 2229 context->flags = cpu_to_be32(err << 16); 2230 2231 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2232 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2233 } else { 2234 switch (attr->path_mig_state) { 2235 case IB_MIG_MIGRATED: 2236 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2237 break; 2238 case IB_MIG_REARM: 2239 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2240 break; 2241 case IB_MIG_ARMED: 2242 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2243 break; 2244 } 2245 } 2246 2247 if (is_sqp(ibqp->qp_type)) { 2248 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2249 } else if (ibqp->qp_type == IB_QPT_UD || 2250 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2251 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2252 } else if (attr_mask & IB_QP_PATH_MTU) { 2253 if (attr->path_mtu < IB_MTU_256 || 2254 attr->path_mtu > IB_MTU_4096) { 2255 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2256 err = -EINVAL; 2257 goto out; 2258 } 2259 context->mtu_msgmax = (attr->path_mtu << 5) | 2260 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2261 } 2262 2263 if (attr_mask & IB_QP_DEST_QPN) 2264 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2265 2266 if (attr_mask & IB_QP_PKEY_INDEX) 2267 context->pri_path.pkey_index = attr->pkey_index; 2268 2269 /* todo implement counter_index functionality */ 2270 2271 if (is_sqp(ibqp->qp_type)) 2272 context->pri_path.port = qp->port; 2273 2274 if (attr_mask & IB_QP_PORT) 2275 context->pri_path.port = attr->port_num; 2276 2277 if (attr_mask & IB_QP_AV) { 2278 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2279 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2280 attr_mask, 0, attr); 2281 if (err) 2282 goto out; 2283 } 2284 2285 if (attr_mask & IB_QP_TIMEOUT) 2286 context->pri_path.ackto_lt |= attr->timeout << 3; 2287 2288 if (attr_mask & IB_QP_ALT_PATH) { 2289 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2290 &context->alt_path, 2291 attr->alt_port_num, attr_mask, 0, attr); 2292 if (err) 2293 goto out; 2294 } 2295 2296 pd = get_pd(qp); 2297 get_cqs(qp, &send_cq, &recv_cq); 2298 2299 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2300 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2301 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2302 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2303 2304 if (attr_mask & IB_QP_RNR_RETRY) 2305 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2306 2307 if (attr_mask & IB_QP_RETRY_CNT) 2308 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2309 2310 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2311 if (attr->max_rd_atomic) 2312 context->params1 |= 2313 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2314 } 2315 2316 if (attr_mask & IB_QP_SQ_PSN) 2317 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2318 2319 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2320 if (attr->max_dest_rd_atomic) 2321 context->params2 |= 2322 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2323 } 2324 2325 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2326 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2327 2328 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2329 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2330 2331 if (attr_mask & IB_QP_RQ_PSN) 2332 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2333 2334 if (attr_mask & IB_QP_QKEY) 2335 context->qkey = cpu_to_be32(attr->qkey); 2336 2337 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2338 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2339 2340 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2341 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2342 sqd_event = 1; 2343 else 2344 sqd_event = 0; 2345 2346 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2347 context->sq_crq_size |= cpu_to_be16(1 << 4); 2348 2349 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2350 context->deth_sqpn = cpu_to_be32(1); 2351 2352 mlx5_cur = to_mlx5_state(cur_state); 2353 mlx5_new = to_mlx5_state(new_state); 2354 mlx5_st = to_mlx5_st(ibqp->qp_type); 2355 if (mlx5_st < 0) 2356 goto out; 2357 2358 /* If moving to a reset or error state, we must disable page faults on 2359 * this QP and flush all current page faults. Otherwise a stale page 2360 * fault may attempt to work on this QP after it is reset and moved 2361 * again to RTS, and may cause the driver and the device to get out of 2362 * sync. */ 2363 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2364 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2365 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2366 mlx5_ib_qp_disable_pagefaults(qp); 2367 2368 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2369 !optab[mlx5_cur][mlx5_new]) 2370 goto out; 2371 2372 op = optab[mlx5_cur][mlx5_new]; 2373 optpar = ib_mask_to_mlx5_opt(attr_mask); 2374 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2375 in->optparam = cpu_to_be32(optpar); 2376 2377 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) 2378 err = modify_raw_packet_qp(dev, qp, op); 2379 else 2380 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event, 2381 &base->mqp); 2382 if (err) 2383 goto out; 2384 2385 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2386 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2387 mlx5_ib_qp_enable_pagefaults(qp); 2388 2389 qp->state = new_state; 2390 2391 if (attr_mask & IB_QP_ACCESS_FLAGS) 2392 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2393 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2394 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2395 if (attr_mask & IB_QP_PORT) 2396 qp->port = attr->port_num; 2397 if (attr_mask & IB_QP_ALT_PATH) 2398 qp->trans_qp.alt_port = attr->alt_port_num; 2399 2400 /* 2401 * If we moved a kernel QP to RESET, clean up all old CQ 2402 * entries and reinitialize the QP. 2403 */ 2404 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2405 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2406 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2407 if (send_cq != recv_cq) 2408 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2409 2410 qp->rq.head = 0; 2411 qp->rq.tail = 0; 2412 qp->sq.head = 0; 2413 qp->sq.tail = 0; 2414 qp->sq.cur_post = 0; 2415 qp->sq.last_poll = 0; 2416 qp->db.db[MLX5_RCV_DBR] = 0; 2417 qp->db.db[MLX5_SND_DBR] = 0; 2418 } 2419 2420 out: 2421 kfree(in); 2422 return err; 2423 } 2424 2425 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2426 int attr_mask, struct ib_udata *udata) 2427 { 2428 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2429 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2430 enum ib_qp_type qp_type; 2431 enum ib_qp_state cur_state, new_state; 2432 int err = -EINVAL; 2433 int port; 2434 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2435 2436 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2437 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2438 2439 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2440 IB_QPT_GSI : ibqp->qp_type; 2441 2442 mutex_lock(&qp->mutex); 2443 2444 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2445 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2446 2447 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 2448 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2449 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 2450 } 2451 2452 if (qp_type != MLX5_IB_QPT_REG_UMR && 2453 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 2454 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2455 cur_state, new_state, ibqp->qp_type, attr_mask); 2456 goto out; 2457 } 2458 2459 if ((attr_mask & IB_QP_PORT) && 2460 (attr->port_num == 0 || 2461 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2462 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2463 attr->port_num, dev->num_ports); 2464 goto out; 2465 } 2466 2467 if (attr_mask & IB_QP_PKEY_INDEX) { 2468 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2469 if (attr->pkey_index >= 2470 dev->mdev->port_caps[port - 1].pkey_table_len) { 2471 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 2472 attr->pkey_index); 2473 goto out; 2474 } 2475 } 2476 2477 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2478 attr->max_rd_atomic > 2479 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 2480 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 2481 attr->max_rd_atomic); 2482 goto out; 2483 } 2484 2485 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2486 attr->max_dest_rd_atomic > 2487 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 2488 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 2489 attr->max_dest_rd_atomic); 2490 goto out; 2491 } 2492 2493 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2494 err = 0; 2495 goto out; 2496 } 2497 2498 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2499 2500 out: 2501 mutex_unlock(&qp->mutex); 2502 return err; 2503 } 2504 2505 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2506 { 2507 struct mlx5_ib_cq *cq; 2508 unsigned cur; 2509 2510 cur = wq->head - wq->tail; 2511 if (likely(cur + nreq < wq->max_post)) 2512 return 0; 2513 2514 cq = to_mcq(ib_cq); 2515 spin_lock(&cq->lock); 2516 cur = wq->head - wq->tail; 2517 spin_unlock(&cq->lock); 2518 2519 return cur + nreq >= wq->max_post; 2520 } 2521 2522 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 2523 u64 remote_addr, u32 rkey) 2524 { 2525 rseg->raddr = cpu_to_be64(remote_addr); 2526 rseg->rkey = cpu_to_be32(rkey); 2527 rseg->reserved = 0; 2528 } 2529 2530 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 2531 struct ib_send_wr *wr, void *qend, 2532 struct mlx5_ib_qp *qp, int *size) 2533 { 2534 void *seg = eseg; 2535 2536 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 2537 2538 if (wr->send_flags & IB_SEND_IP_CSUM) 2539 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 2540 MLX5_ETH_WQE_L4_CSUM; 2541 2542 seg += sizeof(struct mlx5_wqe_eth_seg); 2543 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 2544 2545 if (wr->opcode == IB_WR_LSO) { 2546 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 2547 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 2548 u64 left, leftlen, copysz; 2549 void *pdata = ud_wr->header; 2550 2551 left = ud_wr->hlen; 2552 eseg->mss = cpu_to_be16(ud_wr->mss); 2553 eseg->inline_hdr_sz = cpu_to_be16(left); 2554 2555 /* 2556 * check if there is space till the end of queue, if yes, 2557 * copy all in one shot, otherwise copy till the end of queue, 2558 * rollback and than the copy the left 2559 */ 2560 leftlen = qend - (void *)eseg->inline_hdr_start; 2561 copysz = min_t(u64, leftlen, left); 2562 2563 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 2564 2565 if (likely(copysz > size_of_inl_hdr_start)) { 2566 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 2567 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 2568 } 2569 2570 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 2571 seg = mlx5_get_send_wqe(qp, 0); 2572 left -= copysz; 2573 pdata += copysz; 2574 memcpy(seg, pdata, left); 2575 seg += ALIGN(left, 16); 2576 *size += ALIGN(left, 16) / 16; 2577 } 2578 } 2579 2580 return seg; 2581 } 2582 2583 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 2584 struct ib_send_wr *wr) 2585 { 2586 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 2587 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 2588 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 2589 } 2590 2591 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 2592 { 2593 dseg->byte_count = cpu_to_be32(sg->length); 2594 dseg->lkey = cpu_to_be32(sg->lkey); 2595 dseg->addr = cpu_to_be64(sg->addr); 2596 } 2597 2598 static __be16 get_klm_octo(int npages) 2599 { 2600 return cpu_to_be16(ALIGN(npages, 8) / 2); 2601 } 2602 2603 static __be64 frwr_mkey_mask(void) 2604 { 2605 u64 result; 2606 2607 result = MLX5_MKEY_MASK_LEN | 2608 MLX5_MKEY_MASK_PAGE_SIZE | 2609 MLX5_MKEY_MASK_START_ADDR | 2610 MLX5_MKEY_MASK_EN_RINVAL | 2611 MLX5_MKEY_MASK_KEY | 2612 MLX5_MKEY_MASK_LR | 2613 MLX5_MKEY_MASK_LW | 2614 MLX5_MKEY_MASK_RR | 2615 MLX5_MKEY_MASK_RW | 2616 MLX5_MKEY_MASK_A | 2617 MLX5_MKEY_MASK_SMALL_FENCE | 2618 MLX5_MKEY_MASK_FREE; 2619 2620 return cpu_to_be64(result); 2621 } 2622 2623 static __be64 sig_mkey_mask(void) 2624 { 2625 u64 result; 2626 2627 result = MLX5_MKEY_MASK_LEN | 2628 MLX5_MKEY_MASK_PAGE_SIZE | 2629 MLX5_MKEY_MASK_START_ADDR | 2630 MLX5_MKEY_MASK_EN_SIGERR | 2631 MLX5_MKEY_MASK_EN_RINVAL | 2632 MLX5_MKEY_MASK_KEY | 2633 MLX5_MKEY_MASK_LR | 2634 MLX5_MKEY_MASK_LW | 2635 MLX5_MKEY_MASK_RR | 2636 MLX5_MKEY_MASK_RW | 2637 MLX5_MKEY_MASK_SMALL_FENCE | 2638 MLX5_MKEY_MASK_FREE | 2639 MLX5_MKEY_MASK_BSF_EN; 2640 2641 return cpu_to_be64(result); 2642 } 2643 2644 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 2645 struct mlx5_ib_mr *mr) 2646 { 2647 int ndescs = mr->ndescs; 2648 2649 memset(umr, 0, sizeof(*umr)); 2650 2651 if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 2652 /* KLMs take twice the size of MTTs */ 2653 ndescs *= 2; 2654 2655 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 2656 umr->klm_octowords = get_klm_octo(ndescs); 2657 umr->mkey_mask = frwr_mkey_mask(); 2658 } 2659 2660 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 2661 { 2662 memset(umr, 0, sizeof(*umr)); 2663 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 2664 umr->flags = 1 << 7; 2665 } 2666 2667 static __be64 get_umr_reg_mr_mask(void) 2668 { 2669 u64 result; 2670 2671 result = MLX5_MKEY_MASK_LEN | 2672 MLX5_MKEY_MASK_PAGE_SIZE | 2673 MLX5_MKEY_MASK_START_ADDR | 2674 MLX5_MKEY_MASK_PD | 2675 MLX5_MKEY_MASK_LR | 2676 MLX5_MKEY_MASK_LW | 2677 MLX5_MKEY_MASK_KEY | 2678 MLX5_MKEY_MASK_RR | 2679 MLX5_MKEY_MASK_RW | 2680 MLX5_MKEY_MASK_A | 2681 MLX5_MKEY_MASK_FREE; 2682 2683 return cpu_to_be64(result); 2684 } 2685 2686 static __be64 get_umr_unreg_mr_mask(void) 2687 { 2688 u64 result; 2689 2690 result = MLX5_MKEY_MASK_FREE; 2691 2692 return cpu_to_be64(result); 2693 } 2694 2695 static __be64 get_umr_update_mtt_mask(void) 2696 { 2697 u64 result; 2698 2699 result = MLX5_MKEY_MASK_FREE; 2700 2701 return cpu_to_be64(result); 2702 } 2703 2704 static __be64 get_umr_update_translation_mask(void) 2705 { 2706 u64 result; 2707 2708 result = MLX5_MKEY_MASK_LEN | 2709 MLX5_MKEY_MASK_PAGE_SIZE | 2710 MLX5_MKEY_MASK_START_ADDR | 2711 MLX5_MKEY_MASK_KEY | 2712 MLX5_MKEY_MASK_FREE; 2713 2714 return cpu_to_be64(result); 2715 } 2716 2717 static __be64 get_umr_update_access_mask(void) 2718 { 2719 u64 result; 2720 2721 result = MLX5_MKEY_MASK_LW | 2722 MLX5_MKEY_MASK_RR | 2723 MLX5_MKEY_MASK_RW | 2724 MLX5_MKEY_MASK_A | 2725 MLX5_MKEY_MASK_KEY | 2726 MLX5_MKEY_MASK_FREE; 2727 2728 return cpu_to_be64(result); 2729 } 2730 2731 static __be64 get_umr_update_pd_mask(void) 2732 { 2733 u64 result; 2734 2735 result = MLX5_MKEY_MASK_PD | 2736 MLX5_MKEY_MASK_KEY | 2737 MLX5_MKEY_MASK_FREE; 2738 2739 return cpu_to_be64(result); 2740 } 2741 2742 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 2743 struct ib_send_wr *wr) 2744 { 2745 struct mlx5_umr_wr *umrwr = umr_wr(wr); 2746 2747 memset(umr, 0, sizeof(*umr)); 2748 2749 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 2750 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 2751 else 2752 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 2753 2754 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 2755 umr->klm_octowords = get_klm_octo(umrwr->npages); 2756 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 2757 umr->mkey_mask = get_umr_update_mtt_mask(); 2758 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 2759 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 2760 } 2761 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 2762 umr->mkey_mask |= get_umr_update_translation_mask(); 2763 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 2764 umr->mkey_mask |= get_umr_update_access_mask(); 2765 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 2766 umr->mkey_mask |= get_umr_update_pd_mask(); 2767 if (!umr->mkey_mask) 2768 umr->mkey_mask = get_umr_reg_mr_mask(); 2769 } else { 2770 umr->mkey_mask = get_umr_unreg_mr_mask(); 2771 } 2772 2773 if (!wr->num_sge) 2774 umr->flags |= MLX5_UMR_INLINE; 2775 } 2776 2777 static u8 get_umr_flags(int acc) 2778 { 2779 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 2780 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 2781 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 2782 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 2783 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 2784 } 2785 2786 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 2787 struct mlx5_ib_mr *mr, 2788 u32 key, int access) 2789 { 2790 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 2791 2792 memset(seg, 0, sizeof(*seg)); 2793 2794 if (mr->access_mode == MLX5_ACCESS_MODE_MTT) 2795 seg->log2_page_size = ilog2(mr->ibmr.page_size); 2796 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 2797 /* KLMs take twice the size of MTTs */ 2798 ndescs *= 2; 2799 2800 seg->flags = get_umr_flags(access) | mr->access_mode; 2801 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 2802 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 2803 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 2804 seg->len = cpu_to_be64(mr->ibmr.length); 2805 seg->xlt_oct_size = cpu_to_be32(ndescs); 2806 } 2807 2808 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 2809 { 2810 memset(seg, 0, sizeof(*seg)); 2811 seg->status = MLX5_MKEY_STATUS_FREE; 2812 } 2813 2814 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 2815 { 2816 struct mlx5_umr_wr *umrwr = umr_wr(wr); 2817 2818 memset(seg, 0, sizeof(*seg)); 2819 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 2820 seg->status = MLX5_MKEY_STATUS_FREE; 2821 return; 2822 } 2823 2824 seg->flags = convert_access(umrwr->access_flags); 2825 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 2826 if (umrwr->pd) 2827 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 2828 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 2829 } 2830 seg->len = cpu_to_be64(umrwr->length); 2831 seg->log2_page_size = umrwr->page_shift; 2832 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 2833 mlx5_mkey_variant(umrwr->mkey)); 2834 } 2835 2836 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 2837 struct mlx5_ib_mr *mr, 2838 struct mlx5_ib_pd *pd) 2839 { 2840 int bcount = mr->desc_size * mr->ndescs; 2841 2842 dseg->addr = cpu_to_be64(mr->desc_map); 2843 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 2844 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 2845 } 2846 2847 static __be32 send_ieth(struct ib_send_wr *wr) 2848 { 2849 switch (wr->opcode) { 2850 case IB_WR_SEND_WITH_IMM: 2851 case IB_WR_RDMA_WRITE_WITH_IMM: 2852 return wr->ex.imm_data; 2853 2854 case IB_WR_SEND_WITH_INV: 2855 return cpu_to_be32(wr->ex.invalidate_rkey); 2856 2857 default: 2858 return 0; 2859 } 2860 } 2861 2862 static u8 calc_sig(void *wqe, int size) 2863 { 2864 u8 *p = wqe; 2865 u8 res = 0; 2866 int i; 2867 2868 for (i = 0; i < size; i++) 2869 res ^= p[i]; 2870 2871 return ~res; 2872 } 2873 2874 static u8 wq_sig(void *wqe) 2875 { 2876 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 2877 } 2878 2879 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 2880 void *wqe, int *sz) 2881 { 2882 struct mlx5_wqe_inline_seg *seg; 2883 void *qend = qp->sq.qend; 2884 void *addr; 2885 int inl = 0; 2886 int copy; 2887 int len; 2888 int i; 2889 2890 seg = wqe; 2891 wqe += sizeof(*seg); 2892 for (i = 0; i < wr->num_sge; i++) { 2893 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 2894 len = wr->sg_list[i].length; 2895 inl += len; 2896 2897 if (unlikely(inl > qp->max_inline_data)) 2898 return -ENOMEM; 2899 2900 if (unlikely(wqe + len > qend)) { 2901 copy = qend - wqe; 2902 memcpy(wqe, addr, copy); 2903 addr += copy; 2904 len -= copy; 2905 wqe = mlx5_get_send_wqe(qp, 0); 2906 } 2907 memcpy(wqe, addr, len); 2908 wqe += len; 2909 } 2910 2911 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 2912 2913 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 2914 2915 return 0; 2916 } 2917 2918 static u16 prot_field_size(enum ib_signature_type type) 2919 { 2920 switch (type) { 2921 case IB_SIG_TYPE_T10_DIF: 2922 return MLX5_DIF_SIZE; 2923 default: 2924 return 0; 2925 } 2926 } 2927 2928 static u8 bs_selector(int block_size) 2929 { 2930 switch (block_size) { 2931 case 512: return 0x1; 2932 case 520: return 0x2; 2933 case 4096: return 0x3; 2934 case 4160: return 0x4; 2935 case 1073741824: return 0x5; 2936 default: return 0; 2937 } 2938 } 2939 2940 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 2941 struct mlx5_bsf_inl *inl) 2942 { 2943 /* Valid inline section and allow BSF refresh */ 2944 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 2945 MLX5_BSF_REFRESH_DIF); 2946 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 2947 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 2948 /* repeating block */ 2949 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 2950 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 2951 MLX5_DIF_CRC : MLX5_DIF_IPCS; 2952 2953 if (domain->sig.dif.ref_remap) 2954 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 2955 2956 if (domain->sig.dif.app_escape) { 2957 if (domain->sig.dif.ref_escape) 2958 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 2959 else 2960 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 2961 } 2962 2963 inl->dif_app_bitmask_check = 2964 cpu_to_be16(domain->sig.dif.apptag_check_mask); 2965 } 2966 2967 static int mlx5_set_bsf(struct ib_mr *sig_mr, 2968 struct ib_sig_attrs *sig_attrs, 2969 struct mlx5_bsf *bsf, u32 data_size) 2970 { 2971 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 2972 struct mlx5_bsf_basic *basic = &bsf->basic; 2973 struct ib_sig_domain *mem = &sig_attrs->mem; 2974 struct ib_sig_domain *wire = &sig_attrs->wire; 2975 2976 memset(bsf, 0, sizeof(*bsf)); 2977 2978 /* Basic + Extended + Inline */ 2979 basic->bsf_size_sbs = 1 << 7; 2980 /* Input domain check byte mask */ 2981 basic->check_byte_mask = sig_attrs->check_mask; 2982 basic->raw_data_size = cpu_to_be32(data_size); 2983 2984 /* Memory domain */ 2985 switch (sig_attrs->mem.sig_type) { 2986 case IB_SIG_TYPE_NONE: 2987 break; 2988 case IB_SIG_TYPE_T10_DIF: 2989 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 2990 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 2991 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 2992 break; 2993 default: 2994 return -EINVAL; 2995 } 2996 2997 /* Wire domain */ 2998 switch (sig_attrs->wire.sig_type) { 2999 case IB_SIG_TYPE_NONE: 3000 break; 3001 case IB_SIG_TYPE_T10_DIF: 3002 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3003 mem->sig_type == wire->sig_type) { 3004 /* Same block structure */ 3005 basic->bsf_size_sbs |= 1 << 4; 3006 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3007 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3008 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3009 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3010 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3011 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3012 } else 3013 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3014 3015 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3016 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3017 break; 3018 default: 3019 return -EINVAL; 3020 } 3021 3022 return 0; 3023 } 3024 3025 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3026 struct mlx5_ib_qp *qp, void **seg, int *size) 3027 { 3028 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3029 struct ib_mr *sig_mr = wr->sig_mr; 3030 struct mlx5_bsf *bsf; 3031 u32 data_len = wr->wr.sg_list->length; 3032 u32 data_key = wr->wr.sg_list->lkey; 3033 u64 data_va = wr->wr.sg_list->addr; 3034 int ret; 3035 int wqe_size; 3036 3037 if (!wr->prot || 3038 (data_key == wr->prot->lkey && 3039 data_va == wr->prot->addr && 3040 data_len == wr->prot->length)) { 3041 /** 3042 * Source domain doesn't contain signature information 3043 * or data and protection are interleaved in memory. 3044 * So need construct: 3045 * ------------------ 3046 * | data_klm | 3047 * ------------------ 3048 * | BSF | 3049 * ------------------ 3050 **/ 3051 struct mlx5_klm *data_klm = *seg; 3052 3053 data_klm->bcount = cpu_to_be32(data_len); 3054 data_klm->key = cpu_to_be32(data_key); 3055 data_klm->va = cpu_to_be64(data_va); 3056 wqe_size = ALIGN(sizeof(*data_klm), 64); 3057 } else { 3058 /** 3059 * Source domain contains signature information 3060 * So need construct a strided block format: 3061 * --------------------------- 3062 * | stride_block_ctrl | 3063 * --------------------------- 3064 * | data_klm | 3065 * --------------------------- 3066 * | prot_klm | 3067 * --------------------------- 3068 * | BSF | 3069 * --------------------------- 3070 **/ 3071 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3072 struct mlx5_stride_block_entry *data_sentry; 3073 struct mlx5_stride_block_entry *prot_sentry; 3074 u32 prot_key = wr->prot->lkey; 3075 u64 prot_va = wr->prot->addr; 3076 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3077 int prot_size; 3078 3079 sblock_ctrl = *seg; 3080 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3081 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3082 3083 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3084 if (!prot_size) { 3085 pr_err("Bad block size given: %u\n", block_size); 3086 return -EINVAL; 3087 } 3088 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3089 prot_size); 3090 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3091 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3092 sblock_ctrl->num_entries = cpu_to_be16(2); 3093 3094 data_sentry->bcount = cpu_to_be16(block_size); 3095 data_sentry->key = cpu_to_be32(data_key); 3096 data_sentry->va = cpu_to_be64(data_va); 3097 data_sentry->stride = cpu_to_be16(block_size); 3098 3099 prot_sentry->bcount = cpu_to_be16(prot_size); 3100 prot_sentry->key = cpu_to_be32(prot_key); 3101 prot_sentry->va = cpu_to_be64(prot_va); 3102 prot_sentry->stride = cpu_to_be16(prot_size); 3103 3104 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3105 sizeof(*prot_sentry), 64); 3106 } 3107 3108 *seg += wqe_size; 3109 *size += wqe_size / 16; 3110 if (unlikely((*seg == qp->sq.qend))) 3111 *seg = mlx5_get_send_wqe(qp, 0); 3112 3113 bsf = *seg; 3114 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3115 if (ret) 3116 return -EINVAL; 3117 3118 *seg += sizeof(*bsf); 3119 *size += sizeof(*bsf) / 16; 3120 if (unlikely((*seg == qp->sq.qend))) 3121 *seg = mlx5_get_send_wqe(qp, 0); 3122 3123 return 0; 3124 } 3125 3126 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3127 struct ib_sig_handover_wr *wr, u32 nelements, 3128 u32 length, u32 pdn) 3129 { 3130 struct ib_mr *sig_mr = wr->sig_mr; 3131 u32 sig_key = sig_mr->rkey; 3132 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3133 3134 memset(seg, 0, sizeof(*seg)); 3135 3136 seg->flags = get_umr_flags(wr->access_flags) | 3137 MLX5_ACCESS_MODE_KLM; 3138 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3139 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3140 MLX5_MKEY_BSF_EN | pdn); 3141 seg->len = cpu_to_be64(length); 3142 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3143 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3144 } 3145 3146 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3147 u32 nelements) 3148 { 3149 memset(umr, 0, sizeof(*umr)); 3150 3151 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3152 umr->klm_octowords = get_klm_octo(nelements); 3153 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3154 umr->mkey_mask = sig_mkey_mask(); 3155 } 3156 3157 3158 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3159 void **seg, int *size) 3160 { 3161 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3162 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3163 u32 pdn = get_pd(qp)->pdn; 3164 u32 klm_oct_size; 3165 int region_len, ret; 3166 3167 if (unlikely(wr->wr.num_sge != 1) || 3168 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3169 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3170 unlikely(!sig_mr->sig->sig_status_checked)) 3171 return -EINVAL; 3172 3173 /* length of the protected region, data + protection */ 3174 region_len = wr->wr.sg_list->length; 3175 if (wr->prot && 3176 (wr->prot->lkey != wr->wr.sg_list->lkey || 3177 wr->prot->addr != wr->wr.sg_list->addr || 3178 wr->prot->length != wr->wr.sg_list->length)) 3179 region_len += wr->prot->length; 3180 3181 /** 3182 * KLM octoword size - if protection was provided 3183 * then we use strided block format (3 octowords), 3184 * else we use single KLM (1 octoword) 3185 **/ 3186 klm_oct_size = wr->prot ? 3 : 1; 3187 3188 set_sig_umr_segment(*seg, klm_oct_size); 3189 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3190 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3191 if (unlikely((*seg == qp->sq.qend))) 3192 *seg = mlx5_get_send_wqe(qp, 0); 3193 3194 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3195 *seg += sizeof(struct mlx5_mkey_seg); 3196 *size += sizeof(struct mlx5_mkey_seg) / 16; 3197 if (unlikely((*seg == qp->sq.qend))) 3198 *seg = mlx5_get_send_wqe(qp, 0); 3199 3200 ret = set_sig_data_segment(wr, qp, seg, size); 3201 if (ret) 3202 return ret; 3203 3204 sig_mr->sig->sig_status_checked = false; 3205 return 0; 3206 } 3207 3208 static int set_psv_wr(struct ib_sig_domain *domain, 3209 u32 psv_idx, void **seg, int *size) 3210 { 3211 struct mlx5_seg_set_psv *psv_seg = *seg; 3212 3213 memset(psv_seg, 0, sizeof(*psv_seg)); 3214 psv_seg->psv_num = cpu_to_be32(psv_idx); 3215 switch (domain->sig_type) { 3216 case IB_SIG_TYPE_NONE: 3217 break; 3218 case IB_SIG_TYPE_T10_DIF: 3219 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3220 domain->sig.dif.app_tag); 3221 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3222 break; 3223 default: 3224 pr_err("Bad signature type given.\n"); 3225 return 1; 3226 } 3227 3228 *seg += sizeof(*psv_seg); 3229 *size += sizeof(*psv_seg) / 16; 3230 3231 return 0; 3232 } 3233 3234 static int set_reg_wr(struct mlx5_ib_qp *qp, 3235 struct ib_reg_wr *wr, 3236 void **seg, int *size) 3237 { 3238 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3239 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3240 3241 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3242 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3243 "Invalid IB_SEND_INLINE send flag\n"); 3244 return -EINVAL; 3245 } 3246 3247 set_reg_umr_seg(*seg, mr); 3248 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3249 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3250 if (unlikely((*seg == qp->sq.qend))) 3251 *seg = mlx5_get_send_wqe(qp, 0); 3252 3253 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3254 *seg += sizeof(struct mlx5_mkey_seg); 3255 *size += sizeof(struct mlx5_mkey_seg) / 16; 3256 if (unlikely((*seg == qp->sq.qend))) 3257 *seg = mlx5_get_send_wqe(qp, 0); 3258 3259 set_reg_data_seg(*seg, mr, pd); 3260 *seg += sizeof(struct mlx5_wqe_data_seg); 3261 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3262 3263 return 0; 3264 } 3265 3266 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3267 { 3268 set_linv_umr_seg(*seg); 3269 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3270 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3271 if (unlikely((*seg == qp->sq.qend))) 3272 *seg = mlx5_get_send_wqe(qp, 0); 3273 set_linv_mkey_seg(*seg); 3274 *seg += sizeof(struct mlx5_mkey_seg); 3275 *size += sizeof(struct mlx5_mkey_seg) / 16; 3276 if (unlikely((*seg == qp->sq.qend))) 3277 *seg = mlx5_get_send_wqe(qp, 0); 3278 } 3279 3280 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3281 { 3282 __be32 *p = NULL; 3283 int tidx = idx; 3284 int i, j; 3285 3286 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3287 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3288 if ((i & 0xf) == 0) { 3289 void *buf = mlx5_get_send_wqe(qp, tidx); 3290 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3291 p = buf; 3292 j = 0; 3293 } 3294 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3295 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3296 be32_to_cpu(p[j + 3])); 3297 } 3298 } 3299 3300 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 3301 unsigned bytecnt, struct mlx5_ib_qp *qp) 3302 { 3303 while (bytecnt > 0) { 3304 __iowrite64_copy(dst++, src++, 8); 3305 __iowrite64_copy(dst++, src++, 8); 3306 __iowrite64_copy(dst++, src++, 8); 3307 __iowrite64_copy(dst++, src++, 8); 3308 __iowrite64_copy(dst++, src++, 8); 3309 __iowrite64_copy(dst++, src++, 8); 3310 __iowrite64_copy(dst++, src++, 8); 3311 __iowrite64_copy(dst++, src++, 8); 3312 bytecnt -= 64; 3313 if (unlikely(src == qp->sq.qend)) 3314 src = mlx5_get_send_wqe(qp, 0); 3315 } 3316 } 3317 3318 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 3319 { 3320 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3321 wr->send_flags & IB_SEND_FENCE)) 3322 return MLX5_FENCE_MODE_STRONG_ORDERING; 3323 3324 if (unlikely(fence)) { 3325 if (wr->send_flags & IB_SEND_FENCE) 3326 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3327 else 3328 return fence; 3329 3330 } else { 3331 return 0; 3332 } 3333 } 3334 3335 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3336 struct mlx5_wqe_ctrl_seg **ctrl, 3337 struct ib_send_wr *wr, unsigned *idx, 3338 int *size, int nreq) 3339 { 3340 int err = 0; 3341 3342 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) { 3343 err = -ENOMEM; 3344 return err; 3345 } 3346 3347 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3348 *seg = mlx5_get_send_wqe(qp, *idx); 3349 *ctrl = *seg; 3350 *(uint32_t *)(*seg + 8) = 0; 3351 (*ctrl)->imm = send_ieth(wr); 3352 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3353 (wr->send_flags & IB_SEND_SIGNALED ? 3354 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3355 (wr->send_flags & IB_SEND_SOLICITED ? 3356 MLX5_WQE_CTRL_SOLICITED : 0); 3357 3358 *seg += sizeof(**ctrl); 3359 *size = sizeof(**ctrl) / 16; 3360 3361 return err; 3362 } 3363 3364 static void finish_wqe(struct mlx5_ib_qp *qp, 3365 struct mlx5_wqe_ctrl_seg *ctrl, 3366 u8 size, unsigned idx, u64 wr_id, 3367 int nreq, u8 fence, u8 next_fence, 3368 u32 mlx5_opcode) 3369 { 3370 u8 opmod = 0; 3371 3372 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3373 mlx5_opcode | ((u32)opmod << 24)); 3374 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3375 ctrl->fm_ce_se |= fence; 3376 qp->fm_cache = next_fence; 3377 if (unlikely(qp->wq_sig)) 3378 ctrl->signature = wq_sig(ctrl); 3379 3380 qp->sq.wrid[idx] = wr_id; 3381 qp->sq.w_list[idx].opcode = mlx5_opcode; 3382 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3383 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3384 qp->sq.w_list[idx].next = qp->sq.cur_post; 3385 } 3386 3387 3388 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3389 struct ib_send_wr **bad_wr) 3390 { 3391 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3392 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3393 struct mlx5_ib_qp *qp; 3394 struct mlx5_ib_mr *mr; 3395 struct mlx5_wqe_data_seg *dpseg; 3396 struct mlx5_wqe_xrc_seg *xrc; 3397 struct mlx5_bf *bf; 3398 int uninitialized_var(size); 3399 void *qend; 3400 unsigned long flags; 3401 unsigned idx; 3402 int err = 0; 3403 int inl = 0; 3404 int num_sge; 3405 void *seg; 3406 int nreq; 3407 int i; 3408 u8 next_fence = 0; 3409 u8 fence; 3410 3411 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3412 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3413 3414 qp = to_mqp(ibqp); 3415 bf = qp->bf; 3416 qend = qp->sq.qend; 3417 3418 spin_lock_irqsave(&qp->sq.lock, flags); 3419 3420 for (nreq = 0; wr; nreq++, wr = wr->next) { 3421 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3422 mlx5_ib_warn(dev, "\n"); 3423 err = -EINVAL; 3424 *bad_wr = wr; 3425 goto out; 3426 } 3427 3428 fence = qp->fm_cache; 3429 num_sge = wr->num_sge; 3430 if (unlikely(num_sge > qp->sq.max_gs)) { 3431 mlx5_ib_warn(dev, "\n"); 3432 err = -ENOMEM; 3433 *bad_wr = wr; 3434 goto out; 3435 } 3436 3437 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3438 if (err) { 3439 mlx5_ib_warn(dev, "\n"); 3440 err = -ENOMEM; 3441 *bad_wr = wr; 3442 goto out; 3443 } 3444 3445 switch (ibqp->qp_type) { 3446 case IB_QPT_XRC_INI: 3447 xrc = seg; 3448 seg += sizeof(*xrc); 3449 size += sizeof(*xrc) / 16; 3450 /* fall through */ 3451 case IB_QPT_RC: 3452 switch (wr->opcode) { 3453 case IB_WR_RDMA_READ: 3454 case IB_WR_RDMA_WRITE: 3455 case IB_WR_RDMA_WRITE_WITH_IMM: 3456 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3457 rdma_wr(wr)->rkey); 3458 seg += sizeof(struct mlx5_wqe_raddr_seg); 3459 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3460 break; 3461 3462 case IB_WR_ATOMIC_CMP_AND_SWP: 3463 case IB_WR_ATOMIC_FETCH_AND_ADD: 3464 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3465 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3466 err = -ENOSYS; 3467 *bad_wr = wr; 3468 goto out; 3469 3470 case IB_WR_LOCAL_INV: 3471 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3472 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3473 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3474 set_linv_wr(qp, &seg, &size); 3475 num_sge = 0; 3476 break; 3477 3478 case IB_WR_REG_MR: 3479 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3480 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3481 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3482 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3483 if (err) { 3484 *bad_wr = wr; 3485 goto out; 3486 } 3487 num_sge = 0; 3488 break; 3489 3490 case IB_WR_REG_SIG_MR: 3491 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3492 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3493 3494 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3495 err = set_sig_umr_wr(wr, qp, &seg, &size); 3496 if (err) { 3497 mlx5_ib_warn(dev, "\n"); 3498 *bad_wr = wr; 3499 goto out; 3500 } 3501 3502 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3503 nreq, get_fence(fence, wr), 3504 next_fence, MLX5_OPCODE_UMR); 3505 /* 3506 * SET_PSV WQEs are not signaled and solicited 3507 * on error 3508 */ 3509 wr->send_flags &= ~IB_SEND_SIGNALED; 3510 wr->send_flags |= IB_SEND_SOLICITED; 3511 err = begin_wqe(qp, &seg, &ctrl, wr, 3512 &idx, &size, nreq); 3513 if (err) { 3514 mlx5_ib_warn(dev, "\n"); 3515 err = -ENOMEM; 3516 *bad_wr = wr; 3517 goto out; 3518 } 3519 3520 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 3521 mr->sig->psv_memory.psv_idx, &seg, 3522 &size); 3523 if (err) { 3524 mlx5_ib_warn(dev, "\n"); 3525 *bad_wr = wr; 3526 goto out; 3527 } 3528 3529 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3530 nreq, get_fence(fence, wr), 3531 next_fence, MLX5_OPCODE_SET_PSV); 3532 err = begin_wqe(qp, &seg, &ctrl, wr, 3533 &idx, &size, nreq); 3534 if (err) { 3535 mlx5_ib_warn(dev, "\n"); 3536 err = -ENOMEM; 3537 *bad_wr = wr; 3538 goto out; 3539 } 3540 3541 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3542 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 3543 mr->sig->psv_wire.psv_idx, &seg, 3544 &size); 3545 if (err) { 3546 mlx5_ib_warn(dev, "\n"); 3547 *bad_wr = wr; 3548 goto out; 3549 } 3550 3551 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3552 nreq, get_fence(fence, wr), 3553 next_fence, MLX5_OPCODE_SET_PSV); 3554 num_sge = 0; 3555 goto skip_psv; 3556 3557 default: 3558 break; 3559 } 3560 break; 3561 3562 case IB_QPT_UC: 3563 switch (wr->opcode) { 3564 case IB_WR_RDMA_WRITE: 3565 case IB_WR_RDMA_WRITE_WITH_IMM: 3566 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3567 rdma_wr(wr)->rkey); 3568 seg += sizeof(struct mlx5_wqe_raddr_seg); 3569 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3570 break; 3571 3572 default: 3573 break; 3574 } 3575 break; 3576 3577 case IB_QPT_SMI: 3578 case MLX5_IB_QPT_HW_GSI: 3579 set_datagram_seg(seg, wr); 3580 seg += sizeof(struct mlx5_wqe_datagram_seg); 3581 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 3582 if (unlikely((seg == qend))) 3583 seg = mlx5_get_send_wqe(qp, 0); 3584 break; 3585 case IB_QPT_UD: 3586 set_datagram_seg(seg, wr); 3587 seg += sizeof(struct mlx5_wqe_datagram_seg); 3588 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 3589 3590 if (unlikely((seg == qend))) 3591 seg = mlx5_get_send_wqe(qp, 0); 3592 3593 /* handle qp that supports ud offload */ 3594 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 3595 struct mlx5_wqe_eth_pad *pad; 3596 3597 pad = seg; 3598 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 3599 seg += sizeof(struct mlx5_wqe_eth_pad); 3600 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 3601 3602 seg = set_eth_seg(seg, wr, qend, qp, &size); 3603 3604 if (unlikely((seg == qend))) 3605 seg = mlx5_get_send_wqe(qp, 0); 3606 } 3607 break; 3608 case MLX5_IB_QPT_REG_UMR: 3609 if (wr->opcode != MLX5_IB_WR_UMR) { 3610 err = -EINVAL; 3611 mlx5_ib_warn(dev, "bad opcode\n"); 3612 goto out; 3613 } 3614 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 3615 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 3616 set_reg_umr_segment(seg, wr); 3617 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3618 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3619 if (unlikely((seg == qend))) 3620 seg = mlx5_get_send_wqe(qp, 0); 3621 set_reg_mkey_segment(seg, wr); 3622 seg += sizeof(struct mlx5_mkey_seg); 3623 size += sizeof(struct mlx5_mkey_seg) / 16; 3624 if (unlikely((seg == qend))) 3625 seg = mlx5_get_send_wqe(qp, 0); 3626 break; 3627 3628 default: 3629 break; 3630 } 3631 3632 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 3633 int uninitialized_var(sz); 3634 3635 err = set_data_inl_seg(qp, wr, seg, &sz); 3636 if (unlikely(err)) { 3637 mlx5_ib_warn(dev, "\n"); 3638 *bad_wr = wr; 3639 goto out; 3640 } 3641 inl = 1; 3642 size += sz; 3643 } else { 3644 dpseg = seg; 3645 for (i = 0; i < num_sge; i++) { 3646 if (unlikely(dpseg == qend)) { 3647 seg = mlx5_get_send_wqe(qp, 0); 3648 dpseg = seg; 3649 } 3650 if (likely(wr->sg_list[i].length)) { 3651 set_data_ptr_seg(dpseg, wr->sg_list + i); 3652 size += sizeof(struct mlx5_wqe_data_seg) / 16; 3653 dpseg++; 3654 } 3655 } 3656 } 3657 3658 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3659 get_fence(fence, wr), next_fence, 3660 mlx5_ib_opcode[wr->opcode]); 3661 skip_psv: 3662 if (0) 3663 dump_wqe(qp, idx, size); 3664 } 3665 3666 out: 3667 if (likely(nreq)) { 3668 qp->sq.head += nreq; 3669 3670 /* Make sure that descriptors are written before 3671 * updating doorbell record and ringing the doorbell 3672 */ 3673 wmb(); 3674 3675 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 3676 3677 /* Make sure doorbell record is visible to the HCA before 3678 * we hit doorbell */ 3679 wmb(); 3680 3681 if (bf->need_lock) 3682 spin_lock(&bf->lock); 3683 else 3684 __acquire(&bf->lock); 3685 3686 /* TBD enable WC */ 3687 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 3688 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 3689 /* wc_wmb(); */ 3690 } else { 3691 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 3692 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 3693 /* Make sure doorbells don't leak out of SQ spinlock 3694 * and reach the HCA out of order. 3695 */ 3696 mmiowb(); 3697 } 3698 bf->offset ^= bf->buf_size; 3699 if (bf->need_lock) 3700 spin_unlock(&bf->lock); 3701 else 3702 __release(&bf->lock); 3703 } 3704 3705 spin_unlock_irqrestore(&qp->sq.lock, flags); 3706 3707 return err; 3708 } 3709 3710 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 3711 { 3712 sig->signature = calc_sig(sig, size); 3713 } 3714 3715 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 3716 struct ib_recv_wr **bad_wr) 3717 { 3718 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3719 struct mlx5_wqe_data_seg *scat; 3720 struct mlx5_rwqe_sig *sig; 3721 unsigned long flags; 3722 int err = 0; 3723 int nreq; 3724 int ind; 3725 int i; 3726 3727 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3728 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 3729 3730 spin_lock_irqsave(&qp->rq.lock, flags); 3731 3732 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3733 3734 for (nreq = 0; wr; nreq++, wr = wr->next) { 3735 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3736 err = -ENOMEM; 3737 *bad_wr = wr; 3738 goto out; 3739 } 3740 3741 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3742 err = -EINVAL; 3743 *bad_wr = wr; 3744 goto out; 3745 } 3746 3747 scat = get_recv_wqe(qp, ind); 3748 if (qp->wq_sig) 3749 scat++; 3750 3751 for (i = 0; i < wr->num_sge; i++) 3752 set_data_ptr_seg(scat + i, wr->sg_list + i); 3753 3754 if (i < qp->rq.max_gs) { 3755 scat[i].byte_count = 0; 3756 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 3757 scat[i].addr = 0; 3758 } 3759 3760 if (qp->wq_sig) { 3761 sig = (struct mlx5_rwqe_sig *)scat; 3762 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 3763 } 3764 3765 qp->rq.wrid[ind] = wr->wr_id; 3766 3767 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3768 } 3769 3770 out: 3771 if (likely(nreq)) { 3772 qp->rq.head += nreq; 3773 3774 /* Make sure that descriptors are written before 3775 * doorbell record. 3776 */ 3777 wmb(); 3778 3779 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3780 } 3781 3782 spin_unlock_irqrestore(&qp->rq.lock, flags); 3783 3784 return err; 3785 } 3786 3787 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 3788 { 3789 switch (mlx5_state) { 3790 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 3791 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 3792 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 3793 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 3794 case MLX5_QP_STATE_SQ_DRAINING: 3795 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 3796 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 3797 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 3798 default: return -1; 3799 } 3800 } 3801 3802 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 3803 { 3804 switch (mlx5_mig_state) { 3805 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 3806 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 3807 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3808 default: return -1; 3809 } 3810 } 3811 3812 static int to_ib_qp_access_flags(int mlx5_flags) 3813 { 3814 int ib_flags = 0; 3815 3816 if (mlx5_flags & MLX5_QP_BIT_RRE) 3817 ib_flags |= IB_ACCESS_REMOTE_READ; 3818 if (mlx5_flags & MLX5_QP_BIT_RWE) 3819 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3820 if (mlx5_flags & MLX5_QP_BIT_RAE) 3821 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3822 3823 return ib_flags; 3824 } 3825 3826 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 3827 struct mlx5_qp_path *path) 3828 { 3829 struct mlx5_core_dev *dev = ibdev->mdev; 3830 3831 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 3832 ib_ah_attr->port_num = path->port; 3833 3834 if (ib_ah_attr->port_num == 0 || 3835 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 3836 return; 3837 3838 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 3839 3840 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3841 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 3842 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3843 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 3844 if (ib_ah_attr->ah_flags) { 3845 ib_ah_attr->grh.sgid_index = path->mgid_index; 3846 ib_ah_attr->grh.hop_limit = path->hop_limit; 3847 ib_ah_attr->grh.traffic_class = 3848 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3849 ib_ah_attr->grh.flow_label = 3850 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3851 memcpy(ib_ah_attr->grh.dgid.raw, 3852 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 3853 } 3854 } 3855 3856 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 3857 struct mlx5_ib_sq *sq, 3858 u8 *sq_state) 3859 { 3860 void *out; 3861 void *sqc; 3862 int inlen; 3863 int err; 3864 3865 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 3866 out = mlx5_vzalloc(inlen); 3867 if (!out) 3868 return -ENOMEM; 3869 3870 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 3871 if (err) 3872 goto out; 3873 3874 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 3875 *sq_state = MLX5_GET(sqc, sqc, state); 3876 sq->state = *sq_state; 3877 3878 out: 3879 kvfree(out); 3880 return err; 3881 } 3882 3883 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 3884 struct mlx5_ib_rq *rq, 3885 u8 *rq_state) 3886 { 3887 void *out; 3888 void *rqc; 3889 int inlen; 3890 int err; 3891 3892 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 3893 out = mlx5_vzalloc(inlen); 3894 if (!out) 3895 return -ENOMEM; 3896 3897 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 3898 if (err) 3899 goto out; 3900 3901 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 3902 *rq_state = MLX5_GET(rqc, rqc, state); 3903 rq->state = *rq_state; 3904 3905 out: 3906 kvfree(out); 3907 return err; 3908 } 3909 3910 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 3911 struct mlx5_ib_qp *qp, u8 *qp_state) 3912 { 3913 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 3914 [MLX5_RQC_STATE_RST] = { 3915 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 3916 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 3917 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 3918 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 3919 }, 3920 [MLX5_RQC_STATE_RDY] = { 3921 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 3922 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 3923 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 3924 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 3925 }, 3926 [MLX5_RQC_STATE_ERR] = { 3927 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 3928 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 3929 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 3930 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 3931 }, 3932 [MLX5_RQ_STATE_NA] = { 3933 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 3934 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 3935 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 3936 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 3937 }, 3938 }; 3939 3940 *qp_state = sqrq_trans[rq_state][sq_state]; 3941 3942 if (*qp_state == MLX5_QP_STATE_BAD) { 3943 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 3944 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 3945 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 3946 return -EINVAL; 3947 } 3948 3949 if (*qp_state == MLX5_QP_STATE) 3950 *qp_state = qp->state; 3951 3952 return 0; 3953 } 3954 3955 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 3956 struct mlx5_ib_qp *qp, 3957 u8 *raw_packet_qp_state) 3958 { 3959 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3960 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3961 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3962 int err; 3963 u8 sq_state = MLX5_SQ_STATE_NA; 3964 u8 rq_state = MLX5_RQ_STATE_NA; 3965 3966 if (qp->sq.wqe_cnt) { 3967 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 3968 if (err) 3969 return err; 3970 } 3971 3972 if (qp->rq.wqe_cnt) { 3973 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 3974 if (err) 3975 return err; 3976 } 3977 3978 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 3979 raw_packet_qp_state); 3980 } 3981 3982 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3983 struct ib_qp_attr *qp_attr) 3984 { 3985 struct mlx5_query_qp_mbox_out *outb; 3986 struct mlx5_qp_context *context; 3987 int mlx5_state; 3988 int err = 0; 3989 3990 outb = kzalloc(sizeof(*outb), GFP_KERNEL); 3991 if (!outb) 3992 return -ENOMEM; 3993 3994 context = &outb->ctx; 3995 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 3996 sizeof(*outb)); 3997 if (err) 3998 goto out; 3999 4000 mlx5_state = be32_to_cpu(context->flags) >> 28; 4001 4002 qp->state = to_ib_qp_state(mlx5_state); 4003 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4004 qp_attr->path_mig_state = 4005 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4006 qp_attr->qkey = be32_to_cpu(context->qkey); 4007 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4008 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4009 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4010 qp_attr->qp_access_flags = 4011 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4012 4013 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4014 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4015 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4016 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f; 4017 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4018 } 4019 4020 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f; 4021 qp_attr->port_num = context->pri_path.port; 4022 4023 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4024 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4025 4026 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4027 4028 qp_attr->max_dest_rd_atomic = 4029 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4030 qp_attr->min_rnr_timer = 4031 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4032 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4033 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4034 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4035 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4036 4037 out: 4038 kfree(outb); 4039 return err; 4040 } 4041 4042 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4043 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4044 { 4045 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4046 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4047 int err = 0; 4048 u8 raw_packet_qp_state; 4049 4050 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4051 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4052 qp_init_attr); 4053 4054 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4055 /* 4056 * Wait for any outstanding page faults, in case the user frees memory 4057 * based upon this query's result. 4058 */ 4059 flush_workqueue(mlx5_ib_page_fault_wq); 4060 #endif 4061 4062 mutex_lock(&qp->mutex); 4063 4064 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4065 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4066 if (err) 4067 goto out; 4068 qp->state = raw_packet_qp_state; 4069 qp_attr->port_num = 1; 4070 } else { 4071 err = query_qp_attr(dev, qp, qp_attr); 4072 if (err) 4073 goto out; 4074 } 4075 4076 qp_attr->qp_state = qp->state; 4077 qp_attr->cur_qp_state = qp_attr->qp_state; 4078 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4079 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4080 4081 if (!ibqp->uobject) { 4082 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4083 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4084 } else { 4085 qp_attr->cap.max_send_wr = 0; 4086 qp_attr->cap.max_send_sge = 0; 4087 } 4088 4089 /* We don't support inline sends for kernel QPs (yet), and we 4090 * don't know what userspace's value should be. 4091 */ 4092 qp_attr->cap.max_inline_data = 0; 4093 4094 qp_init_attr->cap = qp_attr->cap; 4095 4096 qp_init_attr->create_flags = 0; 4097 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4098 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4099 4100 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4101 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4102 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4103 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4104 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4105 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4106 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4107 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 4108 4109 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4110 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4111 4112 out: 4113 mutex_unlock(&qp->mutex); 4114 return err; 4115 } 4116 4117 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4118 struct ib_ucontext *context, 4119 struct ib_udata *udata) 4120 { 4121 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4122 struct mlx5_ib_xrcd *xrcd; 4123 int err; 4124 4125 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4126 return ERR_PTR(-ENOSYS); 4127 4128 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4129 if (!xrcd) 4130 return ERR_PTR(-ENOMEM); 4131 4132 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4133 if (err) { 4134 kfree(xrcd); 4135 return ERR_PTR(-ENOMEM); 4136 } 4137 4138 return &xrcd->ibxrcd; 4139 } 4140 4141 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4142 { 4143 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4144 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4145 int err; 4146 4147 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4148 if (err) { 4149 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4150 return err; 4151 } 4152 4153 kfree(xrcd); 4154 4155 return 0; 4156 } 4157