1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 #include "cmd.h" 41 42 /* not supported currently */ 43 static int wq_signature; 44 45 enum { 46 MLX5_IB_ACK_REQ_FREQ = 8, 47 }; 48 49 enum { 50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 52 MLX5_IB_LINK_TYPE_IB = 0, 53 MLX5_IB_LINK_TYPE_ETH = 1 54 }; 55 56 enum { 57 MLX5_IB_SQ_STRIDE = 6, 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, 59 }; 60 61 static const u32 mlx5_ib_opcode[] = { 62 [IB_WR_SEND] = MLX5_OPCODE_SEND, 63 [IB_WR_LSO] = MLX5_OPCODE_LSO, 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 76 }; 77 78 struct mlx5_wqe_eth_pad { 79 u8 rsvd0[16]; 80 }; 81 82 enum raw_qp_set_mask_map { 83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 85 }; 86 87 struct mlx5_modify_raw_qp_param { 88 u16 operation; 89 90 u32 set_mask; /* raw_qp_set_mask_map */ 91 92 struct mlx5_rate_limit rl; 93 94 u8 rq_q_ctr_id; 95 }; 96 97 static void get_cqs(enum ib_qp_type qp_type, 98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 100 101 static int is_qp0(enum ib_qp_type qp_type) 102 { 103 return qp_type == IB_QPT_SMI; 104 } 105 106 static int is_sqp(enum ib_qp_type qp_type) 107 { 108 return is_qp0(qp_type) || is_qp1(qp_type); 109 } 110 111 /** 112 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 113 * 114 * @qp: QP to copy from. 115 * @send: copy from the send queue when non-zero, use the receive queue 116 * otherwise. 117 * @wqe_index: index to start copying from. For send work queues, the 118 * wqe_index is in units of MLX5_SEND_WQE_BB. 119 * For receive work queue, it is the number of work queue 120 * element in the queue. 121 * @buffer: destination buffer. 122 * @length: maximum number of bytes to copy. 123 * 124 * Copies at least a single WQE, but may copy more data. 125 * 126 * Return: the number of bytes copied, or an error code. 127 */ 128 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 129 void *buffer, u32 length, 130 struct mlx5_ib_qp_base *base) 131 { 132 struct ib_device *ibdev = qp->ibqp.device; 133 struct mlx5_ib_dev *dev = to_mdev(ibdev); 134 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 135 size_t offset; 136 size_t wq_end; 137 struct ib_umem *umem = base->ubuffer.umem; 138 u32 first_copy_length; 139 int wqe_length; 140 int ret; 141 142 if (wq->wqe_cnt == 0) { 143 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 144 qp->ibqp.qp_type); 145 return -EINVAL; 146 } 147 148 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 149 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 150 151 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 152 return -EINVAL; 153 154 if (offset > umem->length || 155 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 156 return -EINVAL; 157 158 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 159 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 160 if (ret) 161 return ret; 162 163 if (send) { 164 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 165 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 166 167 wqe_length = ds * MLX5_WQE_DS_UNITS; 168 } else { 169 wqe_length = 1 << wq->wqe_shift; 170 } 171 172 if (wqe_length <= first_copy_length) 173 return first_copy_length; 174 175 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 176 wqe_length - first_copy_length); 177 if (ret) 178 return ret; 179 180 return wqe_length; 181 } 182 183 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 184 { 185 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 186 struct ib_event event; 187 188 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 189 /* This event is only valid for trans_qps */ 190 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 191 } 192 193 if (ibqp->event_handler) { 194 event.device = ibqp->device; 195 event.element.qp = ibqp; 196 switch (type) { 197 case MLX5_EVENT_TYPE_PATH_MIG: 198 event.event = IB_EVENT_PATH_MIG; 199 break; 200 case MLX5_EVENT_TYPE_COMM_EST: 201 event.event = IB_EVENT_COMM_EST; 202 break; 203 case MLX5_EVENT_TYPE_SQ_DRAINED: 204 event.event = IB_EVENT_SQ_DRAINED; 205 break; 206 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 207 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 208 break; 209 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 210 event.event = IB_EVENT_QP_FATAL; 211 break; 212 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 213 event.event = IB_EVENT_PATH_MIG_ERR; 214 break; 215 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 216 event.event = IB_EVENT_QP_REQ_ERR; 217 break; 218 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 219 event.event = IB_EVENT_QP_ACCESS_ERR; 220 break; 221 default: 222 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 223 return; 224 } 225 226 ibqp->event_handler(&event, ibqp->qp_context); 227 } 228 } 229 230 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 231 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 232 { 233 int wqe_size; 234 int wq_size; 235 236 /* Sanity check RQ size before proceeding */ 237 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 238 return -EINVAL; 239 240 if (!has_rq) { 241 qp->rq.max_gs = 0; 242 qp->rq.wqe_cnt = 0; 243 qp->rq.wqe_shift = 0; 244 cap->max_recv_wr = 0; 245 cap->max_recv_sge = 0; 246 } else { 247 if (ucmd) { 248 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 249 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 250 return -EINVAL; 251 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 252 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) 253 return -EINVAL; 254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 255 qp->rq.max_post = qp->rq.wqe_cnt; 256 } else { 257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 259 wqe_size = roundup_pow_of_two(wqe_size); 260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 262 qp->rq.wqe_cnt = wq_size / wqe_size; 263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 265 wqe_size, 266 MLX5_CAP_GEN(dev->mdev, 267 max_wqe_sz_rq)); 268 return -EINVAL; 269 } 270 qp->rq.wqe_shift = ilog2(wqe_size); 271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 272 qp->rq.max_post = qp->rq.wqe_cnt; 273 } 274 } 275 276 return 0; 277 } 278 279 static int sq_overhead(struct ib_qp_init_attr *attr) 280 { 281 int size = 0; 282 283 switch (attr->qp_type) { 284 case IB_QPT_XRC_INI: 285 size += sizeof(struct mlx5_wqe_xrc_seg); 286 /* fall through */ 287 case IB_QPT_RC: 288 size += sizeof(struct mlx5_wqe_ctrl_seg) + 289 max(sizeof(struct mlx5_wqe_atomic_seg) + 290 sizeof(struct mlx5_wqe_raddr_seg), 291 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 292 sizeof(struct mlx5_mkey_seg) + 293 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 294 MLX5_IB_UMR_OCTOWORD); 295 break; 296 297 case IB_QPT_XRC_TGT: 298 return 0; 299 300 case IB_QPT_UC: 301 size += sizeof(struct mlx5_wqe_ctrl_seg) + 302 max(sizeof(struct mlx5_wqe_raddr_seg), 303 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 304 sizeof(struct mlx5_mkey_seg)); 305 break; 306 307 case IB_QPT_UD: 308 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 309 size += sizeof(struct mlx5_wqe_eth_pad) + 310 sizeof(struct mlx5_wqe_eth_seg); 311 /* fall through */ 312 case IB_QPT_SMI: 313 case MLX5_IB_QPT_HW_GSI: 314 size += sizeof(struct mlx5_wqe_ctrl_seg) + 315 sizeof(struct mlx5_wqe_datagram_seg); 316 break; 317 318 case MLX5_IB_QPT_REG_UMR: 319 size += sizeof(struct mlx5_wqe_ctrl_seg) + 320 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 321 sizeof(struct mlx5_mkey_seg); 322 break; 323 324 default: 325 return -EINVAL; 326 } 327 328 return size; 329 } 330 331 static int calc_send_wqe(struct ib_qp_init_attr *attr) 332 { 333 int inl_size = 0; 334 int size; 335 336 size = sq_overhead(attr); 337 if (size < 0) 338 return size; 339 340 if (attr->cap.max_inline_data) { 341 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 342 attr->cap.max_inline_data; 343 } 344 345 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 346 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 347 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 348 return MLX5_SIG_WQE_SIZE; 349 else 350 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 351 } 352 353 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 354 { 355 int max_sge; 356 357 if (attr->qp_type == IB_QPT_RC) 358 max_sge = (min_t(int, wqe_size, 512) - 359 sizeof(struct mlx5_wqe_ctrl_seg) - 360 sizeof(struct mlx5_wqe_raddr_seg)) / 361 sizeof(struct mlx5_wqe_data_seg); 362 else if (attr->qp_type == IB_QPT_XRC_INI) 363 max_sge = (min_t(int, wqe_size, 512) - 364 sizeof(struct mlx5_wqe_ctrl_seg) - 365 sizeof(struct mlx5_wqe_xrc_seg) - 366 sizeof(struct mlx5_wqe_raddr_seg)) / 367 sizeof(struct mlx5_wqe_data_seg); 368 else 369 max_sge = (wqe_size - sq_overhead(attr)) / 370 sizeof(struct mlx5_wqe_data_seg); 371 372 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 373 sizeof(struct mlx5_wqe_data_seg)); 374 } 375 376 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 377 struct mlx5_ib_qp *qp) 378 { 379 int wqe_size; 380 int wq_size; 381 382 if (!attr->cap.max_send_wr) 383 return 0; 384 385 wqe_size = calc_send_wqe(attr); 386 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 387 if (wqe_size < 0) 388 return wqe_size; 389 390 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 391 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 392 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 393 return -EINVAL; 394 } 395 396 qp->max_inline_data = wqe_size - sq_overhead(attr) - 397 sizeof(struct mlx5_wqe_inline_seg); 398 attr->cap.max_inline_data = qp->max_inline_data; 399 400 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 401 qp->signature_en = true; 402 403 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 404 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 405 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 406 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 407 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 408 qp->sq.wqe_cnt, 409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 410 return -ENOMEM; 411 } 412 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 413 qp->sq.max_gs = get_send_sge(attr, wqe_size); 414 if (qp->sq.max_gs < attr->cap.max_send_sge) 415 return -ENOMEM; 416 417 attr->cap.max_send_sge = qp->sq.max_gs; 418 qp->sq.max_post = wq_size / wqe_size; 419 attr->cap.max_send_wr = qp->sq.max_post; 420 421 return wq_size; 422 } 423 424 static int set_user_buf_size(struct mlx5_ib_dev *dev, 425 struct mlx5_ib_qp *qp, 426 struct mlx5_ib_create_qp *ucmd, 427 struct mlx5_ib_qp_base *base, 428 struct ib_qp_init_attr *attr) 429 { 430 int desc_sz = 1 << qp->sq.wqe_shift; 431 432 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 433 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 434 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 435 return -EINVAL; 436 } 437 438 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 439 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 440 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 441 return -EINVAL; 442 } 443 444 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 445 446 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 447 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 448 qp->sq.wqe_cnt, 449 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 450 return -EINVAL; 451 } 452 453 if (attr->qp_type == IB_QPT_RAW_PACKET || 454 qp->flags & MLX5_IB_QP_UNDERLAY) { 455 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 456 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 457 } else { 458 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 459 (qp->sq.wqe_cnt << 6); 460 } 461 462 return 0; 463 } 464 465 static int qp_has_rq(struct ib_qp_init_attr *attr) 466 { 467 if (attr->qp_type == IB_QPT_XRC_INI || 468 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 469 attr->qp_type == MLX5_IB_QPT_REG_UMR || 470 !attr->cap.max_recv_wr) 471 return 0; 472 473 return 1; 474 } 475 476 enum { 477 /* this is the first blue flame register in the array of bfregs assigned 478 * to a processes. Since we do not use it for blue flame but rather 479 * regular 64 bit doorbells, we do not need a lock for maintaiing 480 * "odd/even" order 481 */ 482 NUM_NON_BLUE_FLAME_BFREGS = 1, 483 }; 484 485 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 486 { 487 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 488 } 489 490 static int num_med_bfreg(struct mlx5_ib_dev *dev, 491 struct mlx5_bfreg_info *bfregi) 492 { 493 int n; 494 495 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 496 NUM_NON_BLUE_FLAME_BFREGS; 497 498 return n >= 0 ? n : 0; 499 } 500 501 static int first_med_bfreg(struct mlx5_ib_dev *dev, 502 struct mlx5_bfreg_info *bfregi) 503 { 504 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 505 } 506 507 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 508 struct mlx5_bfreg_info *bfregi) 509 { 510 int med; 511 512 med = num_med_bfreg(dev, bfregi); 513 return ++med; 514 } 515 516 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 517 struct mlx5_bfreg_info *bfregi) 518 { 519 int i; 520 521 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 522 if (!bfregi->count[i]) { 523 bfregi->count[i]++; 524 return i; 525 } 526 } 527 528 return -ENOMEM; 529 } 530 531 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 532 struct mlx5_bfreg_info *bfregi) 533 { 534 int minidx = first_med_bfreg(dev, bfregi); 535 int i; 536 537 if (minidx < 0) 538 return minidx; 539 540 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 541 if (bfregi->count[i] < bfregi->count[minidx]) 542 minidx = i; 543 if (!bfregi->count[minidx]) 544 break; 545 } 546 547 bfregi->count[minidx]++; 548 return minidx; 549 } 550 551 static int alloc_bfreg(struct mlx5_ib_dev *dev, 552 struct mlx5_bfreg_info *bfregi) 553 { 554 int bfregn = -ENOMEM; 555 556 mutex_lock(&bfregi->lock); 557 if (bfregi->ver >= 2) { 558 bfregn = alloc_high_class_bfreg(dev, bfregi); 559 if (bfregn < 0) 560 bfregn = alloc_med_class_bfreg(dev, bfregi); 561 } 562 563 if (bfregn < 0) { 564 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 565 bfregn = 0; 566 bfregi->count[bfregn]++; 567 } 568 mutex_unlock(&bfregi->lock); 569 570 return bfregn; 571 } 572 573 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 574 { 575 mutex_lock(&bfregi->lock); 576 bfregi->count[bfregn]--; 577 mutex_unlock(&bfregi->lock); 578 } 579 580 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 581 { 582 switch (state) { 583 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 584 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 585 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 586 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 587 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 588 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 589 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 590 default: return -1; 591 } 592 } 593 594 static int to_mlx5_st(enum ib_qp_type type) 595 { 596 switch (type) { 597 case IB_QPT_RC: return MLX5_QP_ST_RC; 598 case IB_QPT_UC: return MLX5_QP_ST_UC; 599 case IB_QPT_UD: return MLX5_QP_ST_UD; 600 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 601 case IB_QPT_XRC_INI: 602 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 603 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 604 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 605 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 606 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 607 case IB_QPT_RAW_PACKET: 608 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 609 case IB_QPT_MAX: 610 default: return -EINVAL; 611 } 612 } 613 614 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 615 struct mlx5_ib_cq *recv_cq); 616 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 617 struct mlx5_ib_cq *recv_cq); 618 619 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 620 struct mlx5_bfreg_info *bfregi, u32 bfregn, 621 bool dyn_bfreg) 622 { 623 unsigned int bfregs_per_sys_page; 624 u32 index_of_sys_page; 625 u32 offset; 626 627 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 628 MLX5_NON_FP_BFREGS_PER_UAR; 629 index_of_sys_page = bfregn / bfregs_per_sys_page; 630 631 if (dyn_bfreg) { 632 index_of_sys_page += bfregi->num_static_sys_pages; 633 634 if (index_of_sys_page >= bfregi->num_sys_pages) 635 return -EINVAL; 636 637 if (bfregn > bfregi->num_dyn_bfregs || 638 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 639 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 640 return -EINVAL; 641 } 642 } 643 644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 645 return bfregi->sys_pages[index_of_sys_page] + offset; 646 } 647 648 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 649 struct ib_pd *pd, 650 unsigned long addr, size_t size, 651 struct ib_umem **umem, 652 int *npages, int *page_shift, int *ncont, 653 u32 *offset) 654 { 655 int err; 656 657 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 658 if (IS_ERR(*umem)) { 659 mlx5_ib_dbg(dev, "umem_get failed\n"); 660 return PTR_ERR(*umem); 661 } 662 663 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 664 665 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 666 if (err) { 667 mlx5_ib_warn(dev, "bad offset\n"); 668 goto err_umem; 669 } 670 671 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 672 addr, size, *npages, *page_shift, *ncont, *offset); 673 674 return 0; 675 676 err_umem: 677 ib_umem_release(*umem); 678 *umem = NULL; 679 680 return err; 681 } 682 683 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 684 struct mlx5_ib_rwq *rwq) 685 { 686 struct mlx5_ib_ucontext *context; 687 688 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 689 atomic_dec(&dev->delay_drop.rqs_cnt); 690 691 context = to_mucontext(pd->uobject->context); 692 mlx5_ib_db_unmap_user(context, &rwq->db); 693 if (rwq->umem) 694 ib_umem_release(rwq->umem); 695 } 696 697 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 698 struct mlx5_ib_rwq *rwq, 699 struct mlx5_ib_create_wq *ucmd) 700 { 701 struct mlx5_ib_ucontext *context; 702 int page_shift = 0; 703 int npages; 704 u32 offset = 0; 705 int ncont = 0; 706 int err; 707 708 if (!ucmd->buf_addr) 709 return -EINVAL; 710 711 context = to_mucontext(pd->uobject->context); 712 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 713 rwq->buf_size, 0, 0); 714 if (IS_ERR(rwq->umem)) { 715 mlx5_ib_dbg(dev, "umem_get failed\n"); 716 err = PTR_ERR(rwq->umem); 717 return err; 718 } 719 720 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 721 &ncont, NULL); 722 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 723 &rwq->rq_page_offset); 724 if (err) { 725 mlx5_ib_warn(dev, "bad offset\n"); 726 goto err_umem; 727 } 728 729 rwq->rq_num_pas = ncont; 730 rwq->page_shift = page_shift; 731 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 732 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 733 734 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 735 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 736 npages, page_shift, ncont, offset); 737 738 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 739 if (err) { 740 mlx5_ib_dbg(dev, "map failed\n"); 741 goto err_umem; 742 } 743 744 rwq->create_type = MLX5_WQ_USER; 745 return 0; 746 747 err_umem: 748 ib_umem_release(rwq->umem); 749 return err; 750 } 751 752 static int adjust_bfregn(struct mlx5_ib_dev *dev, 753 struct mlx5_bfreg_info *bfregi, int bfregn) 754 { 755 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 756 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 757 } 758 759 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 760 struct mlx5_ib_qp *qp, struct ib_udata *udata, 761 struct ib_qp_init_attr *attr, 762 u32 **in, 763 struct mlx5_ib_create_qp_resp *resp, int *inlen, 764 struct mlx5_ib_qp_base *base) 765 { 766 struct mlx5_ib_ucontext *context; 767 struct mlx5_ib_create_qp ucmd; 768 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 769 int page_shift = 0; 770 int uar_index = 0; 771 int npages; 772 u32 offset = 0; 773 int bfregn; 774 int ncont = 0; 775 __be64 *pas; 776 void *qpc; 777 int err; 778 u16 uid; 779 780 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 781 if (err) { 782 mlx5_ib_dbg(dev, "copy failed\n"); 783 return err; 784 } 785 786 context = to_mucontext(pd->uobject->context); 787 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 788 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 789 ucmd.bfreg_index, true); 790 if (uar_index < 0) 791 return uar_index; 792 793 bfregn = MLX5_IB_INVALID_BFREG; 794 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 795 /* 796 * TBD: should come from the verbs when we have the API 797 */ 798 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 799 bfregn = MLX5_CROSS_CHANNEL_BFREG; 800 } 801 else { 802 bfregn = alloc_bfreg(dev, &context->bfregi); 803 if (bfregn < 0) 804 return bfregn; 805 } 806 807 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 808 if (bfregn != MLX5_IB_INVALID_BFREG) 809 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 810 false); 811 812 qp->rq.offset = 0; 813 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 814 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 815 816 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 817 if (err) 818 goto err_bfreg; 819 820 if (ucmd.buf_addr && ubuffer->buf_size) { 821 ubuffer->buf_addr = ucmd.buf_addr; 822 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 823 ubuffer->buf_size, 824 &ubuffer->umem, &npages, &page_shift, 825 &ncont, &offset); 826 if (err) 827 goto err_bfreg; 828 } else { 829 ubuffer->umem = NULL; 830 } 831 832 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 833 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 834 *in = kvzalloc(*inlen, GFP_KERNEL); 835 if (!*in) { 836 err = -ENOMEM; 837 goto err_umem; 838 } 839 840 uid = (attr->qp_type != IB_QPT_XRC_TGT && 841 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 842 MLX5_SET(create_qp_in, *in, uid, uid); 843 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 844 if (ubuffer->umem) 845 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 846 847 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 848 849 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 850 MLX5_SET(qpc, qpc, page_offset, offset); 851 852 MLX5_SET(qpc, qpc, uar_page, uar_index); 853 if (bfregn != MLX5_IB_INVALID_BFREG) 854 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 855 else 856 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 857 qp->bfregn = bfregn; 858 859 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 860 if (err) { 861 mlx5_ib_dbg(dev, "map failed\n"); 862 goto err_free; 863 } 864 865 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 866 if (err) { 867 mlx5_ib_dbg(dev, "copy failed\n"); 868 goto err_unmap; 869 } 870 qp->create_type = MLX5_QP_USER; 871 872 return 0; 873 874 err_unmap: 875 mlx5_ib_db_unmap_user(context, &qp->db); 876 877 err_free: 878 kvfree(*in); 879 880 err_umem: 881 if (ubuffer->umem) 882 ib_umem_release(ubuffer->umem); 883 884 err_bfreg: 885 if (bfregn != MLX5_IB_INVALID_BFREG) 886 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 887 return err; 888 } 889 890 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 891 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 892 { 893 struct mlx5_ib_ucontext *context; 894 895 context = to_mucontext(pd->uobject->context); 896 mlx5_ib_db_unmap_user(context, &qp->db); 897 if (base->ubuffer.umem) 898 ib_umem_release(base->ubuffer.umem); 899 900 /* 901 * Free only the BFREGs which are handled by the kernel. 902 * BFREGs of UARs allocated dynamically are handled by user. 903 */ 904 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 905 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 906 } 907 908 /* get_sq_edge - Get the next nearby edge. 909 * 910 * An 'edge' is defined as the first following address after the end 911 * of the fragment or the SQ. Accordingly, during the WQE construction 912 * which repetitively increases the pointer to write the next data, it 913 * simply should check if it gets to an edge. 914 * 915 * @sq - SQ buffer. 916 * @idx - Stride index in the SQ buffer. 917 * 918 * Return: 919 * The new edge. 920 */ 921 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) 922 { 923 void *fragment_end; 924 925 fragment_end = mlx5_frag_buf_get_wqe 926 (&sq->fbc, 927 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); 928 929 return fragment_end + MLX5_SEND_WQE_BB; 930 } 931 932 static int create_kernel_qp(struct mlx5_ib_dev *dev, 933 struct ib_qp_init_attr *init_attr, 934 struct mlx5_ib_qp *qp, 935 u32 **in, int *inlen, 936 struct mlx5_ib_qp_base *base) 937 { 938 int uar_index; 939 void *qpc; 940 int err; 941 942 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 943 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 944 IB_QP_CREATE_IPOIB_UD_LSO | 945 IB_QP_CREATE_NETIF_QP | 946 mlx5_ib_create_qp_sqpn_qp1())) 947 return -EINVAL; 948 949 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 950 qp->bf.bfreg = &dev->fp_bfreg; 951 else 952 qp->bf.bfreg = &dev->bfreg; 953 954 /* We need to divide by two since each register is comprised of 955 * two buffers of identical size, namely odd and even 956 */ 957 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 958 uar_index = qp->bf.bfreg->index; 959 960 err = calc_sq_size(dev, init_attr, qp); 961 if (err < 0) { 962 mlx5_ib_dbg(dev, "err %d\n", err); 963 return err; 964 } 965 966 qp->rq.offset = 0; 967 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 968 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 969 970 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 971 &qp->buf, dev->mdev->priv.numa_node); 972 if (err) { 973 mlx5_ib_dbg(dev, "err %d\n", err); 974 return err; 975 } 976 977 if (qp->rq.wqe_cnt) 978 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 979 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 980 981 if (qp->sq.wqe_cnt) { 982 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 983 MLX5_SEND_WQE_BB; 984 mlx5_init_fbc_offset(qp->buf.frags + 985 (qp->sq.offset / PAGE_SIZE), 986 ilog2(MLX5_SEND_WQE_BB), 987 ilog2(qp->sq.wqe_cnt), 988 sq_strides_offset, &qp->sq.fbc); 989 990 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 991 } 992 993 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 994 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 995 *in = kvzalloc(*inlen, GFP_KERNEL); 996 if (!*in) { 997 err = -ENOMEM; 998 goto err_buf; 999 } 1000 1001 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1002 MLX5_SET(qpc, qpc, uar_page, uar_index); 1003 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1004 1005 /* Set "fast registration enabled" for all kernel QPs */ 1006 MLX5_SET(qpc, qpc, fre, 1); 1007 MLX5_SET(qpc, qpc, rlky, 1); 1008 1009 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 1010 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1011 qp->flags |= MLX5_IB_QP_SQPN_QP1; 1012 } 1013 1014 mlx5_fill_page_frag_array(&qp->buf, 1015 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1016 *in, pas)); 1017 1018 err = mlx5_db_alloc(dev->mdev, &qp->db); 1019 if (err) { 1020 mlx5_ib_dbg(dev, "err %d\n", err); 1021 goto err_free; 1022 } 1023 1024 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1025 sizeof(*qp->sq.wrid), GFP_KERNEL); 1026 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1027 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1028 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1029 sizeof(*qp->rq.wrid), GFP_KERNEL); 1030 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1031 sizeof(*qp->sq.w_list), GFP_KERNEL); 1032 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1033 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1034 1035 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1036 !qp->sq.w_list || !qp->sq.wqe_head) { 1037 err = -ENOMEM; 1038 goto err_wrid; 1039 } 1040 qp->create_type = MLX5_QP_KERNEL; 1041 1042 return 0; 1043 1044 err_wrid: 1045 kvfree(qp->sq.wqe_head); 1046 kvfree(qp->sq.w_list); 1047 kvfree(qp->sq.wrid); 1048 kvfree(qp->sq.wr_data); 1049 kvfree(qp->rq.wrid); 1050 mlx5_db_free(dev->mdev, &qp->db); 1051 1052 err_free: 1053 kvfree(*in); 1054 1055 err_buf: 1056 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1057 return err; 1058 } 1059 1060 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1061 { 1062 kvfree(qp->sq.wqe_head); 1063 kvfree(qp->sq.w_list); 1064 kvfree(qp->sq.wrid); 1065 kvfree(qp->sq.wr_data); 1066 kvfree(qp->rq.wrid); 1067 mlx5_db_free(dev->mdev, &qp->db); 1068 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1069 } 1070 1071 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1072 { 1073 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1074 (attr->qp_type == MLX5_IB_QPT_DCI) || 1075 (attr->qp_type == IB_QPT_XRC_INI)) 1076 return MLX5_SRQ_RQ; 1077 else if (!qp->has_rq) 1078 return MLX5_ZERO_LEN_RQ; 1079 else 1080 return MLX5_NON_ZERO_RQ; 1081 } 1082 1083 static int is_connected(enum ib_qp_type qp_type) 1084 { 1085 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || 1086 qp_type == MLX5_IB_QPT_DCI) 1087 return 1; 1088 1089 return 0; 1090 } 1091 1092 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1093 struct mlx5_ib_qp *qp, 1094 struct mlx5_ib_sq *sq, u32 tdn, 1095 struct ib_pd *pd) 1096 { 1097 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1098 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1099 1100 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1101 MLX5_SET(tisc, tisc, transport_domain, tdn); 1102 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1103 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1104 1105 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1106 } 1107 1108 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1109 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1110 { 1111 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1112 } 1113 1114 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1115 struct mlx5_ib_sq *sq) 1116 { 1117 if (sq->flow_rule) 1118 mlx5_del_flow_rules(sq->flow_rule); 1119 } 1120 1121 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1122 struct mlx5_ib_sq *sq, void *qpin, 1123 struct ib_pd *pd) 1124 { 1125 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1126 __be64 *pas; 1127 void *in; 1128 void *sqc; 1129 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1130 void *wq; 1131 int inlen; 1132 int err; 1133 int page_shift = 0; 1134 int npages; 1135 int ncont = 0; 1136 u32 offset = 0; 1137 1138 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1139 &sq->ubuffer.umem, &npages, &page_shift, 1140 &ncont, &offset); 1141 if (err) 1142 return err; 1143 1144 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1145 in = kvzalloc(inlen, GFP_KERNEL); 1146 if (!in) { 1147 err = -ENOMEM; 1148 goto err_umem; 1149 } 1150 1151 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1152 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1153 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1154 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1155 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1156 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1157 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1158 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1159 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1160 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1161 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1162 MLX5_CAP_ETH(dev->mdev, swp)) 1163 MLX5_SET(sqc, sqc, allow_swp, 1); 1164 1165 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1166 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1167 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1168 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1169 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1170 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1171 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1172 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1173 MLX5_SET(wq, wq, page_offset, offset); 1174 1175 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1176 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1177 1178 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1179 1180 kvfree(in); 1181 1182 if (err) 1183 goto err_umem; 1184 1185 err = create_flow_rule_vport_sq(dev, sq); 1186 if (err) 1187 goto err_flow; 1188 1189 return 0; 1190 1191 err_flow: 1192 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1193 1194 err_umem: 1195 ib_umem_release(sq->ubuffer.umem); 1196 sq->ubuffer.umem = NULL; 1197 1198 return err; 1199 } 1200 1201 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1202 struct mlx5_ib_sq *sq) 1203 { 1204 destroy_flow_rule_vport_sq(dev, sq); 1205 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1206 ib_umem_release(sq->ubuffer.umem); 1207 } 1208 1209 static size_t get_rq_pas_size(void *qpc) 1210 { 1211 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1212 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1213 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1214 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1215 u32 po_quanta = 1 << (log_page_size - 6); 1216 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1217 u32 page_size = 1 << log_page_size; 1218 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1219 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1220 1221 return rq_num_pas * sizeof(u64); 1222 } 1223 1224 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1225 struct mlx5_ib_rq *rq, void *qpin, 1226 size_t qpinlen, struct ib_pd *pd) 1227 { 1228 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1229 __be64 *pas; 1230 __be64 *qp_pas; 1231 void *in; 1232 void *rqc; 1233 void *wq; 1234 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1235 size_t rq_pas_size = get_rq_pas_size(qpc); 1236 size_t inlen; 1237 int err; 1238 1239 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1240 return -EINVAL; 1241 1242 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1243 in = kvzalloc(inlen, GFP_KERNEL); 1244 if (!in) 1245 return -ENOMEM; 1246 1247 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1248 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1249 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1250 MLX5_SET(rqc, rqc, vsd, 1); 1251 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1252 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1253 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1254 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1255 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1256 1257 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1258 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1259 1260 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1261 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1262 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1263 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1264 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1265 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1266 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1267 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1268 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1269 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1270 1271 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1272 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1273 memcpy(pas, qp_pas, rq_pas_size); 1274 1275 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1276 1277 kvfree(in); 1278 1279 return err; 1280 } 1281 1282 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1283 struct mlx5_ib_rq *rq) 1284 { 1285 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1286 } 1287 1288 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1289 { 1290 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1291 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1292 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1293 } 1294 1295 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1296 struct mlx5_ib_rq *rq, 1297 u32 qp_flags_en, 1298 struct ib_pd *pd) 1299 { 1300 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1301 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1302 mlx5_ib_disable_lb(dev, false, true); 1303 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1304 } 1305 1306 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1307 struct mlx5_ib_rq *rq, u32 tdn, 1308 u32 *qp_flags_en, 1309 struct ib_pd *pd) 1310 { 1311 u8 lb_flag = 0; 1312 u32 *in; 1313 void *tirc; 1314 int inlen; 1315 int err; 1316 1317 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1318 in = kvzalloc(inlen, GFP_KERNEL); 1319 if (!in) 1320 return -ENOMEM; 1321 1322 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1323 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1324 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1325 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1326 MLX5_SET(tirc, tirc, transport_domain, tdn); 1327 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1328 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1329 1330 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1331 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1332 1333 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1334 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1335 1336 if (dev->rep) { 1337 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1338 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1339 } 1340 1341 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1342 1343 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1344 1345 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1346 err = mlx5_ib_enable_lb(dev, false, true); 1347 1348 if (err) 1349 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1350 } 1351 kvfree(in); 1352 1353 return err; 1354 } 1355 1356 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1357 u32 *in, size_t inlen, 1358 struct ib_pd *pd, 1359 struct ib_udata *udata, 1360 struct mlx5_ib_create_qp_resp *resp) 1361 { 1362 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1363 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1364 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1365 struct ib_uobject *uobj = pd->uobject; 1366 struct ib_ucontext *ucontext = uobj->context; 1367 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1368 int err; 1369 u32 tdn = mucontext->tdn; 1370 u16 uid = to_mpd(pd)->uid; 1371 1372 if (qp->sq.wqe_cnt) { 1373 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1374 if (err) 1375 return err; 1376 1377 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1378 if (err) 1379 goto err_destroy_tis; 1380 1381 if (uid) { 1382 resp->tisn = sq->tisn; 1383 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1384 resp->sqn = sq->base.mqp.qpn; 1385 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1386 } 1387 1388 sq->base.container_mibqp = qp; 1389 sq->base.mqp.event = mlx5_ib_qp_event; 1390 } 1391 1392 if (qp->rq.wqe_cnt) { 1393 rq->base.container_mibqp = qp; 1394 1395 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1396 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1397 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1398 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1399 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); 1400 if (err) 1401 goto err_destroy_sq; 1402 1403 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd); 1404 if (err) 1405 goto err_destroy_rq; 1406 1407 if (uid) { 1408 resp->rqn = rq->base.mqp.qpn; 1409 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1410 resp->tirn = rq->tirn; 1411 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1412 } 1413 } 1414 1415 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1416 rq->base.mqp.qpn; 1417 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); 1418 if (err) 1419 goto err_destroy_tir; 1420 1421 return 0; 1422 1423 err_destroy_tir: 1424 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); 1425 err_destroy_rq: 1426 destroy_raw_packet_qp_rq(dev, rq); 1427 err_destroy_sq: 1428 if (!qp->sq.wqe_cnt) 1429 return err; 1430 destroy_raw_packet_qp_sq(dev, sq); 1431 err_destroy_tis: 1432 destroy_raw_packet_qp_tis(dev, sq, pd); 1433 1434 return err; 1435 } 1436 1437 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1438 struct mlx5_ib_qp *qp) 1439 { 1440 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1441 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1442 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1443 1444 if (qp->rq.wqe_cnt) { 1445 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1446 destroy_raw_packet_qp_rq(dev, rq); 1447 } 1448 1449 if (qp->sq.wqe_cnt) { 1450 destroy_raw_packet_qp_sq(dev, sq); 1451 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1452 } 1453 } 1454 1455 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1456 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1457 { 1458 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1459 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1460 1461 sq->sq = &qp->sq; 1462 rq->rq = &qp->rq; 1463 sq->doorbell = &qp->db; 1464 rq->doorbell = &qp->db; 1465 } 1466 1467 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1468 { 1469 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1470 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1471 mlx5_ib_disable_lb(dev, false, true); 1472 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1473 to_mpd(qp->ibqp.pd)->uid); 1474 } 1475 1476 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1477 struct ib_pd *pd, 1478 struct ib_qp_init_attr *init_attr, 1479 struct ib_udata *udata) 1480 { 1481 struct ib_uobject *uobj = pd->uobject; 1482 struct ib_ucontext *ucontext = uobj->context; 1483 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1484 struct mlx5_ib_create_qp_resp resp = {}; 1485 int inlen; 1486 int err; 1487 u32 *in; 1488 void *tirc; 1489 void *hfso; 1490 u32 selected_fields = 0; 1491 u32 outer_l4; 1492 size_t min_resp_len; 1493 u32 tdn = mucontext->tdn; 1494 struct mlx5_ib_create_qp_rss ucmd = {}; 1495 size_t required_cmd_sz; 1496 u8 lb_flag = 0; 1497 1498 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1499 return -EOPNOTSUPP; 1500 1501 if (init_attr->create_flags || init_attr->send_cq) 1502 return -EINVAL; 1503 1504 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1505 if (udata->outlen < min_resp_len) 1506 return -EINVAL; 1507 1508 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1509 if (udata->inlen < required_cmd_sz) { 1510 mlx5_ib_dbg(dev, "invalid inlen\n"); 1511 return -EINVAL; 1512 } 1513 1514 if (udata->inlen > sizeof(ucmd) && 1515 !ib_is_udata_cleared(udata, sizeof(ucmd), 1516 udata->inlen - sizeof(ucmd))) { 1517 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1518 return -EOPNOTSUPP; 1519 } 1520 1521 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1522 mlx5_ib_dbg(dev, "copy failed\n"); 1523 return -EFAULT; 1524 } 1525 1526 if (ucmd.comp_mask) { 1527 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1528 return -EOPNOTSUPP; 1529 } 1530 1531 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1532 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1533 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { 1534 mlx5_ib_dbg(dev, "invalid flags\n"); 1535 return -EOPNOTSUPP; 1536 } 1537 1538 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1539 !tunnel_offload_supported(dev->mdev)) { 1540 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1541 return -EOPNOTSUPP; 1542 } 1543 1544 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1545 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1546 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1547 return -EOPNOTSUPP; 1548 } 1549 1550 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) { 1551 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1552 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1553 } 1554 1555 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1556 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1557 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1558 } 1559 1560 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1561 if (err) { 1562 mlx5_ib_dbg(dev, "copy failed\n"); 1563 return -EINVAL; 1564 } 1565 1566 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1567 in = kvzalloc(inlen, GFP_KERNEL); 1568 if (!in) 1569 return -ENOMEM; 1570 1571 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1572 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1573 MLX5_SET(tirc, tirc, disp_type, 1574 MLX5_TIRC_DISP_TYPE_INDIRECT); 1575 MLX5_SET(tirc, tirc, indirect_table, 1576 init_attr->rwq_ind_tbl->ind_tbl_num); 1577 MLX5_SET(tirc, tirc, transport_domain, tdn); 1578 1579 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1580 1581 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1582 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1583 1584 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1585 1586 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1587 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1588 else 1589 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1590 1591 switch (ucmd.rx_hash_function) { 1592 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1593 { 1594 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1595 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1596 1597 if (len != ucmd.rx_key_len) { 1598 err = -EINVAL; 1599 goto err; 1600 } 1601 1602 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1603 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1604 memcpy(rss_key, ucmd.rx_hash_key, len); 1605 break; 1606 } 1607 default: 1608 err = -EOPNOTSUPP; 1609 goto err; 1610 } 1611 1612 if (!ucmd.rx_hash_fields_mask) { 1613 /* special case when this TIR serves as steering entry without hashing */ 1614 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1615 goto create_tir; 1616 err = -EINVAL; 1617 goto err; 1618 } 1619 1620 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1621 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1622 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1623 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1624 err = -EINVAL; 1625 goto err; 1626 } 1627 1628 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1629 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1630 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1631 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1632 MLX5_L3_PROT_TYPE_IPV4); 1633 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1634 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1635 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1636 MLX5_L3_PROT_TYPE_IPV6); 1637 1638 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1639 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | 1640 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1641 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | 1642 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1643 1644 /* Check that only one l4 protocol is set */ 1645 if (outer_l4 & (outer_l4 - 1)) { 1646 err = -EINVAL; 1647 goto err; 1648 } 1649 1650 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1651 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1652 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1653 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1654 MLX5_L4_PROT_TYPE_TCP); 1655 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1656 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1657 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1658 MLX5_L4_PROT_TYPE_UDP); 1659 1660 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1661 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1662 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1663 1664 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1665 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1666 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1667 1668 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1669 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1670 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1671 1672 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1673 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1674 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1675 1676 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1677 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1678 1679 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1680 1681 create_tir: 1682 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1683 1684 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1685 err = mlx5_ib_enable_lb(dev, false, true); 1686 1687 if (err) 1688 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1689 to_mpd(pd)->uid); 1690 } 1691 1692 if (err) 1693 goto err; 1694 1695 if (mucontext->devx_uid) { 1696 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1697 resp.tirn = qp->rss_qp.tirn; 1698 } 1699 1700 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 1701 if (err) 1702 goto err_copy; 1703 1704 kvfree(in); 1705 /* qpn is reserved for that QP */ 1706 qp->trans_qp.base.mqp.qpn = 0; 1707 qp->flags |= MLX5_IB_QP_RSS; 1708 return 0; 1709 1710 err_copy: 1711 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); 1712 err: 1713 kvfree(in); 1714 return err; 1715 } 1716 1717 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, 1718 void *qpc) 1719 { 1720 int rcqe_sz; 1721 1722 if (init_attr->qp_type == MLX5_IB_QPT_DCI) 1723 return; 1724 1725 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1726 1727 if (rcqe_sz == 128) { 1728 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1729 return; 1730 } 1731 1732 if (init_attr->qp_type != MLX5_IB_QPT_DCT) 1733 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1734 } 1735 1736 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1737 struct ib_qp_init_attr *init_attr, 1738 struct mlx5_ib_create_qp *ucmd, 1739 void *qpc) 1740 { 1741 enum ib_qp_type qpt = init_attr->qp_type; 1742 int scqe_sz; 1743 bool allow_scat_cqe = 0; 1744 1745 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) 1746 return; 1747 1748 if (ucmd) 1749 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1750 1751 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1752 return; 1753 1754 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1755 if (scqe_sz == 128) { 1756 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1757 return; 1758 } 1759 1760 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1761 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1762 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1763 } 1764 1765 static int atomic_size_to_mode(int size_mask) 1766 { 1767 /* driver does not support atomic_size > 256B 1768 * and does not know how to translate bigger sizes 1769 */ 1770 int supported_size_mask = size_mask & 0x1ff; 1771 int log_max_size; 1772 1773 if (!supported_size_mask) 1774 return -EOPNOTSUPP; 1775 1776 log_max_size = __fls(supported_size_mask); 1777 1778 if (log_max_size > 3) 1779 return log_max_size; 1780 1781 return MLX5_ATOMIC_MODE_8B; 1782 } 1783 1784 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1785 enum ib_qp_type qp_type) 1786 { 1787 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1788 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1789 int atomic_mode = -EOPNOTSUPP; 1790 int atomic_size_mask; 1791 1792 if (!atomic) 1793 return -EOPNOTSUPP; 1794 1795 if (qp_type == MLX5_IB_QPT_DCT) 1796 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1797 else 1798 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1799 1800 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1801 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1802 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1803 1804 if (atomic_mode <= 0 && 1805 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1806 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1807 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1808 1809 return atomic_mode; 1810 } 1811 1812 static inline bool check_flags_mask(uint64_t input, uint64_t supported) 1813 { 1814 return (input & ~supported) == 0; 1815 } 1816 1817 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1818 struct ib_qp_init_attr *init_attr, 1819 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1820 { 1821 struct mlx5_ib_resources *devr = &dev->devr; 1822 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1823 struct mlx5_core_dev *mdev = dev->mdev; 1824 struct mlx5_ib_create_qp_resp resp = {}; 1825 struct mlx5_ib_cq *send_cq; 1826 struct mlx5_ib_cq *recv_cq; 1827 unsigned long flags; 1828 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1829 struct mlx5_ib_create_qp ucmd; 1830 struct mlx5_ib_qp_base *base; 1831 int mlx5_st; 1832 void *qpc; 1833 u32 *in; 1834 int err; 1835 1836 mutex_init(&qp->mutex); 1837 spin_lock_init(&qp->sq.lock); 1838 spin_lock_init(&qp->rq.lock); 1839 1840 mlx5_st = to_mlx5_st(init_attr->qp_type); 1841 if (mlx5_st < 0) 1842 return -EINVAL; 1843 1844 if (init_attr->rwq_ind_tbl) { 1845 if (!udata) 1846 return -ENOSYS; 1847 1848 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1849 return err; 1850 } 1851 1852 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1853 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1854 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1855 return -EINVAL; 1856 } else { 1857 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1858 } 1859 } 1860 1861 if (init_attr->create_flags & 1862 (IB_QP_CREATE_CROSS_CHANNEL | 1863 IB_QP_CREATE_MANAGED_SEND | 1864 IB_QP_CREATE_MANAGED_RECV)) { 1865 if (!MLX5_CAP_GEN(mdev, cd)) { 1866 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1867 return -EINVAL; 1868 } 1869 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1870 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1871 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1872 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1873 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1874 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1875 } 1876 1877 if (init_attr->qp_type == IB_QPT_UD && 1878 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1879 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1880 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1881 return -EOPNOTSUPP; 1882 } 1883 1884 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1885 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1886 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1887 return -EOPNOTSUPP; 1888 } 1889 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1890 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1891 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1892 return -EOPNOTSUPP; 1893 } 1894 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1895 } 1896 1897 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1898 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1899 1900 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1901 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1902 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1903 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1904 return -EOPNOTSUPP; 1905 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1906 } 1907 1908 if (udata) { 1909 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1910 mlx5_ib_dbg(dev, "copy failed\n"); 1911 return -EFAULT; 1912 } 1913 1914 if (!check_flags_mask(ucmd.flags, 1915 MLX5_QP_FLAG_SIGNATURE | 1916 MLX5_QP_FLAG_SCATTER_CQE | 1917 MLX5_QP_FLAG_TUNNEL_OFFLOADS | 1918 MLX5_QP_FLAG_BFREG_INDEX | 1919 MLX5_QP_FLAG_TYPE_DCT | 1920 MLX5_QP_FLAG_TYPE_DCI | 1921 MLX5_QP_FLAG_ALLOW_SCATTER_CQE | 1922 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)) 1923 return -EINVAL; 1924 1925 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1926 &ucmd, udata->inlen, &uidx); 1927 if (err) 1928 return err; 1929 1930 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1931 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) 1932 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1933 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1934 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1935 !tunnel_offload_supported(mdev)) { 1936 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1937 return -EOPNOTSUPP; 1938 } 1939 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; 1940 } 1941 1942 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { 1943 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1944 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); 1945 return -EOPNOTSUPP; 1946 } 1947 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1948 } 1949 1950 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { 1951 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1952 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); 1953 return -EOPNOTSUPP; 1954 } 1955 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; 1956 } 1957 1958 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { 1959 if (init_attr->qp_type != IB_QPT_RC || 1960 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { 1961 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); 1962 return -EOPNOTSUPP; 1963 } 1964 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; 1965 } 1966 1967 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1968 if (init_attr->qp_type != IB_QPT_UD || 1969 (MLX5_CAP_GEN(dev->mdev, port_type) != 1970 MLX5_CAP_PORT_TYPE_IB) || 1971 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1972 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1973 return -EOPNOTSUPP; 1974 } 1975 1976 qp->flags |= MLX5_IB_QP_UNDERLAY; 1977 qp->underlay_qpn = init_attr->source_qpn; 1978 } 1979 } else { 1980 qp->wq_sig = !!wq_signature; 1981 } 1982 1983 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1984 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1985 &qp->raw_packet_qp.rq.base : 1986 &qp->trans_qp.base; 1987 1988 qp->has_rq = qp_has_rq(init_attr); 1989 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1990 qp, udata ? &ucmd : NULL); 1991 if (err) { 1992 mlx5_ib_dbg(dev, "err %d\n", err); 1993 return err; 1994 } 1995 1996 if (pd) { 1997 if (udata) { 1998 __u32 max_wqes = 1999 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 2000 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 2001 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 2002 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 2003 mlx5_ib_dbg(dev, "invalid rq params\n"); 2004 return -EINVAL; 2005 } 2006 if (ucmd.sq_wqe_count > max_wqes) { 2007 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 2008 ucmd.sq_wqe_count, max_wqes); 2009 return -EINVAL; 2010 } 2011 if (init_attr->create_flags & 2012 mlx5_ib_create_qp_sqpn_qp1()) { 2013 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 2014 return -EINVAL; 2015 } 2016 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 2017 &resp, &inlen, base); 2018 if (err) 2019 mlx5_ib_dbg(dev, "err %d\n", err); 2020 } else { 2021 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 2022 base); 2023 if (err) 2024 mlx5_ib_dbg(dev, "err %d\n", err); 2025 } 2026 2027 if (err) 2028 return err; 2029 } else { 2030 in = kvzalloc(inlen, GFP_KERNEL); 2031 if (!in) 2032 return -ENOMEM; 2033 2034 qp->create_type = MLX5_QP_EMPTY; 2035 } 2036 2037 if (is_sqp(init_attr->qp_type)) 2038 qp->port = init_attr->port_num; 2039 2040 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2041 2042 MLX5_SET(qpc, qpc, st, mlx5_st); 2043 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2044 2045 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 2046 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2047 else 2048 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2049 2050 2051 if (qp->wq_sig) 2052 MLX5_SET(qpc, qpc, wq_signature, 1); 2053 2054 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 2055 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2056 2057 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 2058 MLX5_SET(qpc, qpc, cd_master, 1); 2059 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 2060 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2061 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 2062 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2063 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) 2064 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2065 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 2066 configure_responder_scat_cqe(init_attr, qpc); 2067 configure_requester_scat_cqe(dev, init_attr, 2068 udata ? &ucmd : NULL, 2069 qpc); 2070 } 2071 2072 if (qp->rq.wqe_cnt) { 2073 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2074 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2075 } 2076 2077 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2078 2079 if (qp->sq.wqe_cnt) { 2080 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2081 } else { 2082 MLX5_SET(qpc, qpc, no_sq, 1); 2083 if (init_attr->srq && 2084 init_attr->srq->srq_type == IB_SRQT_TM) 2085 MLX5_SET(qpc, qpc, offload_type, 2086 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2087 } 2088 2089 /* Set default resources */ 2090 switch (init_attr->qp_type) { 2091 case IB_QPT_XRC_TGT: 2092 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2093 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2094 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2095 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 2096 break; 2097 case IB_QPT_XRC_INI: 2098 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2099 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2100 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2101 break; 2102 default: 2103 if (init_attr->srq) { 2104 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 2105 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2106 } else { 2107 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 2108 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2109 } 2110 } 2111 2112 if (init_attr->send_cq) 2113 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2114 2115 if (init_attr->recv_cq) 2116 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2117 2118 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2119 2120 /* 0xffffff means we ask to work with cqe version 0 */ 2121 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2122 MLX5_SET(qpc, qpc, user_index, uidx); 2123 2124 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2125 if (init_attr->qp_type == IB_QPT_UD && 2126 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 2127 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2128 qp->flags |= MLX5_IB_QP_LSO; 2129 } 2130 2131 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2132 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 2133 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 2134 err = -EOPNOTSUPP; 2135 goto err; 2136 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2137 MLX5_SET(qpc, qpc, end_padding_mode, 2138 MLX5_WQ_END_PAD_MODE_ALIGN); 2139 } else { 2140 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 2141 } 2142 } 2143 2144 if (inlen < 0) { 2145 err = -EINVAL; 2146 goto err; 2147 } 2148 2149 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2150 qp->flags & MLX5_IB_QP_UNDERLAY) { 2151 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 2152 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2153 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2154 &resp); 2155 } else { 2156 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 2157 } 2158 2159 if (err) { 2160 mlx5_ib_dbg(dev, "create qp failed\n"); 2161 goto err_create; 2162 } 2163 2164 kvfree(in); 2165 2166 base->container_mibqp = qp; 2167 base->mqp.event = mlx5_ib_qp_event; 2168 2169 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 2170 &send_cq, &recv_cq); 2171 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2172 mlx5_ib_lock_cqs(send_cq, recv_cq); 2173 /* Maintain device to QPs access, needed for further handling via reset 2174 * flow 2175 */ 2176 list_add_tail(&qp->qps_list, &dev->qp_list); 2177 /* Maintain CQ to QPs access, needed for further handling via reset flow 2178 */ 2179 if (send_cq) 2180 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2181 if (recv_cq) 2182 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2183 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2184 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2185 2186 return 0; 2187 2188 err_create: 2189 if (qp->create_type == MLX5_QP_USER) 2190 destroy_qp_user(dev, pd, qp, base); 2191 else if (qp->create_type == MLX5_QP_KERNEL) 2192 destroy_qp_kernel(dev, qp); 2193 2194 err: 2195 kvfree(in); 2196 return err; 2197 } 2198 2199 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2200 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2201 { 2202 if (send_cq) { 2203 if (recv_cq) { 2204 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2205 spin_lock(&send_cq->lock); 2206 spin_lock_nested(&recv_cq->lock, 2207 SINGLE_DEPTH_NESTING); 2208 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2209 spin_lock(&send_cq->lock); 2210 __acquire(&recv_cq->lock); 2211 } else { 2212 spin_lock(&recv_cq->lock); 2213 spin_lock_nested(&send_cq->lock, 2214 SINGLE_DEPTH_NESTING); 2215 } 2216 } else { 2217 spin_lock(&send_cq->lock); 2218 __acquire(&recv_cq->lock); 2219 } 2220 } else if (recv_cq) { 2221 spin_lock(&recv_cq->lock); 2222 __acquire(&send_cq->lock); 2223 } else { 2224 __acquire(&send_cq->lock); 2225 __acquire(&recv_cq->lock); 2226 } 2227 } 2228 2229 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2230 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2231 { 2232 if (send_cq) { 2233 if (recv_cq) { 2234 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2235 spin_unlock(&recv_cq->lock); 2236 spin_unlock(&send_cq->lock); 2237 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2238 __release(&recv_cq->lock); 2239 spin_unlock(&send_cq->lock); 2240 } else { 2241 spin_unlock(&send_cq->lock); 2242 spin_unlock(&recv_cq->lock); 2243 } 2244 } else { 2245 __release(&recv_cq->lock); 2246 spin_unlock(&send_cq->lock); 2247 } 2248 } else if (recv_cq) { 2249 __release(&send_cq->lock); 2250 spin_unlock(&recv_cq->lock); 2251 } else { 2252 __release(&recv_cq->lock); 2253 __release(&send_cq->lock); 2254 } 2255 } 2256 2257 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2258 { 2259 return to_mpd(qp->ibqp.pd); 2260 } 2261 2262 static void get_cqs(enum ib_qp_type qp_type, 2263 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2264 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2265 { 2266 switch (qp_type) { 2267 case IB_QPT_XRC_TGT: 2268 *send_cq = NULL; 2269 *recv_cq = NULL; 2270 break; 2271 case MLX5_IB_QPT_REG_UMR: 2272 case IB_QPT_XRC_INI: 2273 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2274 *recv_cq = NULL; 2275 break; 2276 2277 case IB_QPT_SMI: 2278 case MLX5_IB_QPT_HW_GSI: 2279 case IB_QPT_RC: 2280 case IB_QPT_UC: 2281 case IB_QPT_UD: 2282 case IB_QPT_RAW_IPV6: 2283 case IB_QPT_RAW_ETHERTYPE: 2284 case IB_QPT_RAW_PACKET: 2285 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2286 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2287 break; 2288 2289 case IB_QPT_MAX: 2290 default: 2291 *send_cq = NULL; 2292 *recv_cq = NULL; 2293 break; 2294 } 2295 } 2296 2297 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2298 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2299 u8 lag_tx_affinity); 2300 2301 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2302 { 2303 struct mlx5_ib_cq *send_cq, *recv_cq; 2304 struct mlx5_ib_qp_base *base; 2305 unsigned long flags; 2306 int err; 2307 2308 if (qp->ibqp.rwq_ind_tbl) { 2309 destroy_rss_raw_qp_tir(dev, qp); 2310 return; 2311 } 2312 2313 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2314 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2315 &qp->raw_packet_qp.rq.base : 2316 &qp->trans_qp.base; 2317 2318 if (qp->state != IB_QPS_RESET) { 2319 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2320 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2321 err = mlx5_core_qp_modify(dev->mdev, 2322 MLX5_CMD_OP_2RST_QP, 0, 2323 NULL, &base->mqp); 2324 } else { 2325 struct mlx5_modify_raw_qp_param raw_qp_param = { 2326 .operation = MLX5_CMD_OP_2RST_QP 2327 }; 2328 2329 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2330 } 2331 if (err) 2332 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2333 base->mqp.qpn); 2334 } 2335 2336 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2337 &send_cq, &recv_cq); 2338 2339 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2340 mlx5_ib_lock_cqs(send_cq, recv_cq); 2341 /* del from lists under both locks above to protect reset flow paths */ 2342 list_del(&qp->qps_list); 2343 if (send_cq) 2344 list_del(&qp->cq_send_list); 2345 2346 if (recv_cq) 2347 list_del(&qp->cq_recv_list); 2348 2349 if (qp->create_type == MLX5_QP_KERNEL) { 2350 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2351 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2352 if (send_cq != recv_cq) 2353 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2354 NULL); 2355 } 2356 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2357 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2358 2359 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2360 qp->flags & MLX5_IB_QP_UNDERLAY) { 2361 destroy_raw_packet_qp(dev, qp); 2362 } else { 2363 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2364 if (err) 2365 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2366 base->mqp.qpn); 2367 } 2368 2369 if (qp->create_type == MLX5_QP_KERNEL) 2370 destroy_qp_kernel(dev, qp); 2371 else if (qp->create_type == MLX5_QP_USER) 2372 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2373 } 2374 2375 static const char *ib_qp_type_str(enum ib_qp_type type) 2376 { 2377 switch (type) { 2378 case IB_QPT_SMI: 2379 return "IB_QPT_SMI"; 2380 case IB_QPT_GSI: 2381 return "IB_QPT_GSI"; 2382 case IB_QPT_RC: 2383 return "IB_QPT_RC"; 2384 case IB_QPT_UC: 2385 return "IB_QPT_UC"; 2386 case IB_QPT_UD: 2387 return "IB_QPT_UD"; 2388 case IB_QPT_RAW_IPV6: 2389 return "IB_QPT_RAW_IPV6"; 2390 case IB_QPT_RAW_ETHERTYPE: 2391 return "IB_QPT_RAW_ETHERTYPE"; 2392 case IB_QPT_XRC_INI: 2393 return "IB_QPT_XRC_INI"; 2394 case IB_QPT_XRC_TGT: 2395 return "IB_QPT_XRC_TGT"; 2396 case IB_QPT_RAW_PACKET: 2397 return "IB_QPT_RAW_PACKET"; 2398 case MLX5_IB_QPT_REG_UMR: 2399 return "MLX5_IB_QPT_REG_UMR"; 2400 case IB_QPT_DRIVER: 2401 return "IB_QPT_DRIVER"; 2402 case IB_QPT_MAX: 2403 default: 2404 return "Invalid QP type"; 2405 } 2406 } 2407 2408 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2409 struct ib_qp_init_attr *attr, 2410 struct mlx5_ib_create_qp *ucmd) 2411 { 2412 struct mlx5_ib_qp *qp; 2413 int err = 0; 2414 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2415 void *dctc; 2416 2417 if (!attr->srq || !attr->recv_cq) 2418 return ERR_PTR(-EINVAL); 2419 2420 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2421 ucmd, sizeof(*ucmd), &uidx); 2422 if (err) 2423 return ERR_PTR(err); 2424 2425 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2426 if (!qp) 2427 return ERR_PTR(-ENOMEM); 2428 2429 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2430 if (!qp->dct.in) { 2431 err = -ENOMEM; 2432 goto err_free; 2433 } 2434 2435 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2436 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2437 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2438 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2439 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2440 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2441 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2442 MLX5_SET(dctc, dctc, user_index, uidx); 2443 2444 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) 2445 configure_responder_scat_cqe(attr, dctc); 2446 2447 qp->state = IB_QPS_RESET; 2448 2449 return &qp->ibqp; 2450 err_free: 2451 kfree(qp); 2452 return ERR_PTR(err); 2453 } 2454 2455 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2456 struct ib_qp_init_attr *init_attr, 2457 struct mlx5_ib_create_qp *ucmd, 2458 struct ib_udata *udata) 2459 { 2460 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2461 int err; 2462 2463 if (!udata) 2464 return -EINVAL; 2465 2466 if (udata->inlen < sizeof(*ucmd)) { 2467 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2468 return -EINVAL; 2469 } 2470 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2471 if (err) 2472 return err; 2473 2474 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2475 init_attr->qp_type = MLX5_IB_QPT_DCI; 2476 } else { 2477 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2478 init_attr->qp_type = MLX5_IB_QPT_DCT; 2479 } else { 2480 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2481 return -EINVAL; 2482 } 2483 } 2484 2485 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2486 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2487 return -EOPNOTSUPP; 2488 } 2489 2490 return 0; 2491 } 2492 2493 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2494 struct ib_qp_init_attr *verbs_init_attr, 2495 struct ib_udata *udata) 2496 { 2497 struct mlx5_ib_dev *dev; 2498 struct mlx5_ib_qp *qp; 2499 u16 xrcdn = 0; 2500 int err; 2501 struct ib_qp_init_attr mlx_init_attr; 2502 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2503 2504 if (pd) { 2505 dev = to_mdev(pd->device); 2506 2507 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2508 if (!udata) { 2509 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2510 return ERR_PTR(-EINVAL); 2511 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2512 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2513 return ERR_PTR(-EINVAL); 2514 } 2515 } 2516 } else { 2517 /* being cautious here */ 2518 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2519 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2520 pr_warn("%s: no PD for transport %s\n", __func__, 2521 ib_qp_type_str(init_attr->qp_type)); 2522 return ERR_PTR(-EINVAL); 2523 } 2524 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2525 } 2526 2527 if (init_attr->qp_type == IB_QPT_DRIVER) { 2528 struct mlx5_ib_create_qp ucmd; 2529 2530 init_attr = &mlx_init_attr; 2531 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2532 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2533 if (err) 2534 return ERR_PTR(err); 2535 2536 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2537 if (init_attr->cap.max_recv_wr || 2538 init_attr->cap.max_recv_sge) { 2539 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2540 return ERR_PTR(-EINVAL); 2541 } 2542 } else { 2543 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2544 } 2545 } 2546 2547 switch (init_attr->qp_type) { 2548 case IB_QPT_XRC_TGT: 2549 case IB_QPT_XRC_INI: 2550 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2551 mlx5_ib_dbg(dev, "XRC not supported\n"); 2552 return ERR_PTR(-ENOSYS); 2553 } 2554 init_attr->recv_cq = NULL; 2555 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2556 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2557 init_attr->send_cq = NULL; 2558 } 2559 2560 /* fall through */ 2561 case IB_QPT_RAW_PACKET: 2562 case IB_QPT_RC: 2563 case IB_QPT_UC: 2564 case IB_QPT_UD: 2565 case IB_QPT_SMI: 2566 case MLX5_IB_QPT_HW_GSI: 2567 case MLX5_IB_QPT_REG_UMR: 2568 case MLX5_IB_QPT_DCI: 2569 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2570 if (!qp) 2571 return ERR_PTR(-ENOMEM); 2572 2573 err = create_qp_common(dev, pd, init_attr, udata, qp); 2574 if (err) { 2575 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2576 kfree(qp); 2577 return ERR_PTR(err); 2578 } 2579 2580 if (is_qp0(init_attr->qp_type)) 2581 qp->ibqp.qp_num = 0; 2582 else if (is_qp1(init_attr->qp_type)) 2583 qp->ibqp.qp_num = 1; 2584 else 2585 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2586 2587 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2588 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2589 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2590 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2591 2592 qp->trans_qp.xrcdn = xrcdn; 2593 2594 break; 2595 2596 case IB_QPT_GSI: 2597 return mlx5_ib_gsi_create_qp(pd, init_attr); 2598 2599 case IB_QPT_RAW_IPV6: 2600 case IB_QPT_RAW_ETHERTYPE: 2601 case IB_QPT_MAX: 2602 default: 2603 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2604 init_attr->qp_type); 2605 /* Don't support raw QPs */ 2606 return ERR_PTR(-EINVAL); 2607 } 2608 2609 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2610 qp->qp_sub_type = init_attr->qp_type; 2611 2612 return &qp->ibqp; 2613 } 2614 2615 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2616 { 2617 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2618 2619 if (mqp->state == IB_QPS_RTR) { 2620 int err; 2621 2622 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2623 if (err) { 2624 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2625 return err; 2626 } 2627 } 2628 2629 kfree(mqp->dct.in); 2630 kfree(mqp); 2631 return 0; 2632 } 2633 2634 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2635 { 2636 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2637 struct mlx5_ib_qp *mqp = to_mqp(qp); 2638 2639 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2640 return mlx5_ib_gsi_destroy_qp(qp); 2641 2642 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2643 return mlx5_ib_destroy_dct(mqp); 2644 2645 destroy_qp_common(dev, mqp); 2646 2647 kfree(mqp); 2648 2649 return 0; 2650 } 2651 2652 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2653 const struct ib_qp_attr *attr, 2654 int attr_mask, __be32 *hw_access_flags) 2655 { 2656 u8 dest_rd_atomic; 2657 u32 access_flags; 2658 2659 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2660 2661 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2662 dest_rd_atomic = attr->max_dest_rd_atomic; 2663 else 2664 dest_rd_atomic = qp->trans_qp.resp_depth; 2665 2666 if (attr_mask & IB_QP_ACCESS_FLAGS) 2667 access_flags = attr->qp_access_flags; 2668 else 2669 access_flags = qp->trans_qp.atomic_rd_en; 2670 2671 if (!dest_rd_atomic) 2672 access_flags &= IB_ACCESS_REMOTE_WRITE; 2673 2674 if (access_flags & IB_ACCESS_REMOTE_READ) 2675 *hw_access_flags |= MLX5_QP_BIT_RRE; 2676 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2677 int atomic_mode; 2678 2679 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2680 if (atomic_mode < 0) 2681 return -EOPNOTSUPP; 2682 2683 *hw_access_flags |= MLX5_QP_BIT_RAE; 2684 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; 2685 } 2686 2687 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2688 *hw_access_flags |= MLX5_QP_BIT_RWE; 2689 2690 *hw_access_flags = cpu_to_be32(*hw_access_flags); 2691 2692 return 0; 2693 } 2694 2695 enum { 2696 MLX5_PATH_FLAG_FL = 1 << 0, 2697 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2698 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2699 }; 2700 2701 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2702 { 2703 if (rate == IB_RATE_PORT_CURRENT) 2704 return 0; 2705 2706 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 2707 return -EINVAL; 2708 2709 while (rate != IB_RATE_PORT_CURRENT && 2710 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2711 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2712 --rate; 2713 2714 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; 2715 } 2716 2717 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2718 struct mlx5_ib_sq *sq, u8 sl, 2719 struct ib_pd *pd) 2720 { 2721 void *in; 2722 void *tisc; 2723 int inlen; 2724 int err; 2725 2726 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2727 in = kvzalloc(inlen, GFP_KERNEL); 2728 if (!in) 2729 return -ENOMEM; 2730 2731 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2732 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2733 2734 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2735 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2736 2737 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2738 2739 kvfree(in); 2740 2741 return err; 2742 } 2743 2744 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2745 struct mlx5_ib_sq *sq, u8 tx_affinity, 2746 struct ib_pd *pd) 2747 { 2748 void *in; 2749 void *tisc; 2750 int inlen; 2751 int err; 2752 2753 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2754 in = kvzalloc(inlen, GFP_KERNEL); 2755 if (!in) 2756 return -ENOMEM; 2757 2758 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2759 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2760 2761 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2762 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2763 2764 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2765 2766 kvfree(in); 2767 2768 return err; 2769 } 2770 2771 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2772 const struct rdma_ah_attr *ah, 2773 struct mlx5_qp_path *path, u8 port, int attr_mask, 2774 u32 path_flags, const struct ib_qp_attr *attr, 2775 bool alt) 2776 { 2777 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2778 int err; 2779 enum ib_gid_type gid_type; 2780 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2781 u8 sl = rdma_ah_get_sl(ah); 2782 2783 if (attr_mask & IB_QP_PKEY_INDEX) 2784 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2785 attr->pkey_index); 2786 2787 if (ah_flags & IB_AH_GRH) { 2788 if (grh->sgid_index >= 2789 dev->mdev->port_caps[port - 1].gid_table_len) { 2790 pr_err("sgid_index (%u) too large. max is %d\n", 2791 grh->sgid_index, 2792 dev->mdev->port_caps[port - 1].gid_table_len); 2793 return -EINVAL; 2794 } 2795 } 2796 2797 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2798 if (!(ah_flags & IB_AH_GRH)) 2799 return -EINVAL; 2800 2801 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2802 if (qp->ibqp.qp_type == IB_QPT_RC || 2803 qp->ibqp.qp_type == IB_QPT_UC || 2804 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2805 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2806 path->udp_sport = 2807 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); 2808 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2809 gid_type = ah->grh.sgid_attr->gid_type; 2810 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2811 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2812 } else { 2813 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2814 path->fl_free_ar |= 2815 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2816 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2817 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2818 if (ah_flags & IB_AH_GRH) 2819 path->grh_mlid |= 1 << 7; 2820 path->dci_cfi_prio_sl = sl & 0xf; 2821 } 2822 2823 if (ah_flags & IB_AH_GRH) { 2824 path->mgid_index = grh->sgid_index; 2825 path->hop_limit = grh->hop_limit; 2826 path->tclass_flowlabel = 2827 cpu_to_be32((grh->traffic_class << 20) | 2828 (grh->flow_label)); 2829 memcpy(path->rgid, grh->dgid.raw, 16); 2830 } 2831 2832 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2833 if (err < 0) 2834 return err; 2835 path->static_rate = err; 2836 path->port = port; 2837 2838 if (attr_mask & IB_QP_TIMEOUT) 2839 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2840 2841 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2842 return modify_raw_packet_eth_prio(dev->mdev, 2843 &qp->raw_packet_qp.sq, 2844 sl & 0xf, qp->ibqp.pd); 2845 2846 return 0; 2847 } 2848 2849 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2850 [MLX5_QP_STATE_INIT] = { 2851 [MLX5_QP_STATE_INIT] = { 2852 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2853 MLX5_QP_OPTPAR_RAE | 2854 MLX5_QP_OPTPAR_RWE | 2855 MLX5_QP_OPTPAR_PKEY_INDEX | 2856 MLX5_QP_OPTPAR_PRI_PORT, 2857 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2858 MLX5_QP_OPTPAR_PKEY_INDEX | 2859 MLX5_QP_OPTPAR_PRI_PORT, 2860 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2861 MLX5_QP_OPTPAR_Q_KEY | 2862 MLX5_QP_OPTPAR_PRI_PORT, 2863 }, 2864 [MLX5_QP_STATE_RTR] = { 2865 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2866 MLX5_QP_OPTPAR_RRE | 2867 MLX5_QP_OPTPAR_RAE | 2868 MLX5_QP_OPTPAR_RWE | 2869 MLX5_QP_OPTPAR_PKEY_INDEX, 2870 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2871 MLX5_QP_OPTPAR_RWE | 2872 MLX5_QP_OPTPAR_PKEY_INDEX, 2873 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2874 MLX5_QP_OPTPAR_Q_KEY, 2875 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2876 MLX5_QP_OPTPAR_Q_KEY, 2877 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2878 MLX5_QP_OPTPAR_RRE | 2879 MLX5_QP_OPTPAR_RAE | 2880 MLX5_QP_OPTPAR_RWE | 2881 MLX5_QP_OPTPAR_PKEY_INDEX, 2882 }, 2883 }, 2884 [MLX5_QP_STATE_RTR] = { 2885 [MLX5_QP_STATE_RTS] = { 2886 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2887 MLX5_QP_OPTPAR_RRE | 2888 MLX5_QP_OPTPAR_RAE | 2889 MLX5_QP_OPTPAR_RWE | 2890 MLX5_QP_OPTPAR_PM_STATE | 2891 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2892 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2893 MLX5_QP_OPTPAR_RWE | 2894 MLX5_QP_OPTPAR_PM_STATE, 2895 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2896 }, 2897 }, 2898 [MLX5_QP_STATE_RTS] = { 2899 [MLX5_QP_STATE_RTS] = { 2900 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2901 MLX5_QP_OPTPAR_RAE | 2902 MLX5_QP_OPTPAR_RWE | 2903 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2904 MLX5_QP_OPTPAR_PM_STATE | 2905 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2906 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2907 MLX5_QP_OPTPAR_PM_STATE | 2908 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2909 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2910 MLX5_QP_OPTPAR_SRQN | 2911 MLX5_QP_OPTPAR_CQN_RCV, 2912 }, 2913 }, 2914 [MLX5_QP_STATE_SQER] = { 2915 [MLX5_QP_STATE_RTS] = { 2916 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2917 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2918 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2919 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2920 MLX5_QP_OPTPAR_RWE | 2921 MLX5_QP_OPTPAR_RAE | 2922 MLX5_QP_OPTPAR_RRE, 2923 }, 2924 }, 2925 }; 2926 2927 static int ib_nr_to_mlx5_nr(int ib_mask) 2928 { 2929 switch (ib_mask) { 2930 case IB_QP_STATE: 2931 return 0; 2932 case IB_QP_CUR_STATE: 2933 return 0; 2934 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2935 return 0; 2936 case IB_QP_ACCESS_FLAGS: 2937 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2938 MLX5_QP_OPTPAR_RAE; 2939 case IB_QP_PKEY_INDEX: 2940 return MLX5_QP_OPTPAR_PKEY_INDEX; 2941 case IB_QP_PORT: 2942 return MLX5_QP_OPTPAR_PRI_PORT; 2943 case IB_QP_QKEY: 2944 return MLX5_QP_OPTPAR_Q_KEY; 2945 case IB_QP_AV: 2946 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2947 MLX5_QP_OPTPAR_PRI_PORT; 2948 case IB_QP_PATH_MTU: 2949 return 0; 2950 case IB_QP_TIMEOUT: 2951 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2952 case IB_QP_RETRY_CNT: 2953 return MLX5_QP_OPTPAR_RETRY_COUNT; 2954 case IB_QP_RNR_RETRY: 2955 return MLX5_QP_OPTPAR_RNR_RETRY; 2956 case IB_QP_RQ_PSN: 2957 return 0; 2958 case IB_QP_MAX_QP_RD_ATOMIC: 2959 return MLX5_QP_OPTPAR_SRA_MAX; 2960 case IB_QP_ALT_PATH: 2961 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2962 case IB_QP_MIN_RNR_TIMER: 2963 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2964 case IB_QP_SQ_PSN: 2965 return 0; 2966 case IB_QP_MAX_DEST_RD_ATOMIC: 2967 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2968 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2969 case IB_QP_PATH_MIG_STATE: 2970 return MLX5_QP_OPTPAR_PM_STATE; 2971 case IB_QP_CAP: 2972 return 0; 2973 case IB_QP_DEST_QPN: 2974 return 0; 2975 } 2976 return 0; 2977 } 2978 2979 static int ib_mask_to_mlx5_opt(int ib_mask) 2980 { 2981 int result = 0; 2982 int i; 2983 2984 for (i = 0; i < 8 * sizeof(int); i++) { 2985 if ((1 << i) & ib_mask) 2986 result |= ib_nr_to_mlx5_nr(1 << i); 2987 } 2988 2989 return result; 2990 } 2991 2992 static int modify_raw_packet_qp_rq( 2993 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 2994 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 2995 { 2996 void *in; 2997 void *rqc; 2998 int inlen; 2999 int err; 3000 3001 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3002 in = kvzalloc(inlen, GFP_KERNEL); 3003 if (!in) 3004 return -ENOMEM; 3005 3006 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3007 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3008 3009 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3010 MLX5_SET(rqc, rqc, state, new_state); 3011 3012 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3013 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3014 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3015 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3016 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3017 } else 3018 dev_info_once( 3019 &dev->ib_dev.dev, 3020 "RAW PACKET QP counters are not supported on current FW\n"); 3021 } 3022 3023 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 3024 if (err) 3025 goto out; 3026 3027 rq->state = new_state; 3028 3029 out: 3030 kvfree(in); 3031 return err; 3032 } 3033 3034 static int modify_raw_packet_qp_sq( 3035 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3036 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3037 { 3038 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3039 struct mlx5_rate_limit old_rl = ibqp->rl; 3040 struct mlx5_rate_limit new_rl = old_rl; 3041 bool new_rate_added = false; 3042 u16 rl_index = 0; 3043 void *in; 3044 void *sqc; 3045 int inlen; 3046 int err; 3047 3048 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3049 in = kvzalloc(inlen, GFP_KERNEL); 3050 if (!in) 3051 return -ENOMEM; 3052 3053 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3054 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3055 3056 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3057 MLX5_SET(sqc, sqc, state, new_state); 3058 3059 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3060 if (new_state != MLX5_SQC_STATE_RDY) 3061 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3062 __func__); 3063 else 3064 new_rl = raw_qp_param->rl; 3065 } 3066 3067 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3068 if (new_rl.rate) { 3069 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3070 if (err) { 3071 pr_err("Failed configuring rate limit(err %d): \ 3072 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3073 err, new_rl.rate, new_rl.max_burst_sz, 3074 new_rl.typical_pkt_sz); 3075 3076 goto out; 3077 } 3078 new_rate_added = true; 3079 } 3080 3081 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3082 /* index 0 means no limit */ 3083 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3084 } 3085 3086 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 3087 if (err) { 3088 /* Remove new rate from table if failed */ 3089 if (new_rate_added) 3090 mlx5_rl_remove_rate(dev, &new_rl); 3091 goto out; 3092 } 3093 3094 /* Only remove the old rate after new rate was set */ 3095 if ((old_rl.rate && 3096 !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3097 (new_state != MLX5_SQC_STATE_RDY)) 3098 mlx5_rl_remove_rate(dev, &old_rl); 3099 3100 ibqp->rl = new_rl; 3101 sq->state = new_state; 3102 3103 out: 3104 kvfree(in); 3105 return err; 3106 } 3107 3108 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3109 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3110 u8 tx_affinity) 3111 { 3112 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3113 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3114 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3115 int modify_rq = !!qp->rq.wqe_cnt; 3116 int modify_sq = !!qp->sq.wqe_cnt; 3117 int rq_state; 3118 int sq_state; 3119 int err; 3120 3121 switch (raw_qp_param->operation) { 3122 case MLX5_CMD_OP_RST2INIT_QP: 3123 rq_state = MLX5_RQC_STATE_RDY; 3124 sq_state = MLX5_SQC_STATE_RDY; 3125 break; 3126 case MLX5_CMD_OP_2ERR_QP: 3127 rq_state = MLX5_RQC_STATE_ERR; 3128 sq_state = MLX5_SQC_STATE_ERR; 3129 break; 3130 case MLX5_CMD_OP_2RST_QP: 3131 rq_state = MLX5_RQC_STATE_RST; 3132 sq_state = MLX5_SQC_STATE_RST; 3133 break; 3134 case MLX5_CMD_OP_RTR2RTS_QP: 3135 case MLX5_CMD_OP_RTS2RTS_QP: 3136 if (raw_qp_param->set_mask == 3137 MLX5_RAW_QP_RATE_LIMIT) { 3138 modify_rq = 0; 3139 sq_state = sq->state; 3140 } else { 3141 return raw_qp_param->set_mask ? -EINVAL : 0; 3142 } 3143 break; 3144 case MLX5_CMD_OP_INIT2INIT_QP: 3145 case MLX5_CMD_OP_INIT2RTR_QP: 3146 if (raw_qp_param->set_mask) 3147 return -EINVAL; 3148 else 3149 return 0; 3150 default: 3151 WARN_ON(1); 3152 return -EINVAL; 3153 } 3154 3155 if (modify_rq) { 3156 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3157 qp->ibqp.pd); 3158 if (err) 3159 return err; 3160 } 3161 3162 if (modify_sq) { 3163 if (tx_affinity) { 3164 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3165 tx_affinity, 3166 qp->ibqp.pd); 3167 if (err) 3168 return err; 3169 } 3170 3171 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3172 raw_qp_param, qp->ibqp.pd); 3173 } 3174 3175 return 0; 3176 } 3177 3178 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, 3179 struct mlx5_ib_pd *pd, 3180 struct mlx5_ib_qp_base *qp_base, 3181 u8 port_num) 3182 { 3183 struct mlx5_ib_ucontext *ucontext = NULL; 3184 unsigned int tx_port_affinity; 3185 3186 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context) 3187 ucontext = to_mucontext(pd->ibpd.uobject->context); 3188 3189 if (ucontext) { 3190 tx_port_affinity = (unsigned int)atomic_add_return( 3191 1, &ucontext->tx_port_affinity) % 3192 MLX5_MAX_PORTS + 3193 1; 3194 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3195 tx_port_affinity, qp_base->mqp.qpn, ucontext); 3196 } else { 3197 tx_port_affinity = 3198 (unsigned int)atomic_add_return( 3199 1, &dev->roce[port_num].tx_port_affinity) % 3200 MLX5_MAX_PORTS + 3201 1; 3202 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3203 tx_port_affinity, qp_base->mqp.qpn); 3204 } 3205 3206 return tx_port_affinity; 3207 } 3208 3209 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3210 const struct ib_qp_attr *attr, int attr_mask, 3211 enum ib_qp_state cur_state, enum ib_qp_state new_state, 3212 const struct mlx5_ib_modify_qp *ucmd) 3213 { 3214 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3215 [MLX5_QP_STATE_RST] = { 3216 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3217 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3218 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3219 }, 3220 [MLX5_QP_STATE_INIT] = { 3221 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3222 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3223 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3224 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3225 }, 3226 [MLX5_QP_STATE_RTR] = { 3227 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3228 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3229 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3230 }, 3231 [MLX5_QP_STATE_RTS] = { 3232 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3233 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3234 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3235 }, 3236 [MLX5_QP_STATE_SQD] = { 3237 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3238 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3239 }, 3240 [MLX5_QP_STATE_SQER] = { 3241 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3242 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3243 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3244 }, 3245 [MLX5_QP_STATE_ERR] = { 3246 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3247 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3248 } 3249 }; 3250 3251 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3252 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3253 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3254 struct mlx5_ib_cq *send_cq, *recv_cq; 3255 struct mlx5_qp_context *context; 3256 struct mlx5_ib_pd *pd; 3257 struct mlx5_ib_port *mibport = NULL; 3258 enum mlx5_qp_state mlx5_cur, mlx5_new; 3259 enum mlx5_qp_optpar optpar; 3260 int mlx5_st; 3261 int err; 3262 u16 op; 3263 u8 tx_affinity = 0; 3264 3265 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3266 qp->qp_sub_type : ibqp->qp_type); 3267 if (mlx5_st < 0) 3268 return -EINVAL; 3269 3270 context = kzalloc(sizeof(*context), GFP_KERNEL); 3271 if (!context) 3272 return -ENOMEM; 3273 3274 pd = get_pd(qp); 3275 context->flags = cpu_to_be32(mlx5_st << 16); 3276 3277 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3278 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3279 } else { 3280 switch (attr->path_mig_state) { 3281 case IB_MIG_MIGRATED: 3282 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 3283 break; 3284 case IB_MIG_REARM: 3285 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 3286 break; 3287 case IB_MIG_ARMED: 3288 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 3289 break; 3290 } 3291 } 3292 3293 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 3294 if ((ibqp->qp_type == IB_QPT_RC) || 3295 (ibqp->qp_type == IB_QPT_UD && 3296 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 3297 (ibqp->qp_type == IB_QPT_UC) || 3298 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 3299 (ibqp->qp_type == IB_QPT_XRC_INI) || 3300 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 3301 if (dev->lag_active) { 3302 u8 p = mlx5_core_native_port_num(dev->mdev); 3303 tx_affinity = get_tx_affinity(dev, pd, base, p); 3304 context->flags |= cpu_to_be32(tx_affinity << 24); 3305 } 3306 } 3307 } 3308 3309 if (is_sqp(ibqp->qp_type)) { 3310 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3311 } else if ((ibqp->qp_type == IB_QPT_UD && 3312 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3313 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3314 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3315 } else if (attr_mask & IB_QP_PATH_MTU) { 3316 if (attr->path_mtu < IB_MTU_256 || 3317 attr->path_mtu > IB_MTU_4096) { 3318 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3319 err = -EINVAL; 3320 goto out; 3321 } 3322 context->mtu_msgmax = (attr->path_mtu << 5) | 3323 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3324 } 3325 3326 if (attr_mask & IB_QP_DEST_QPN) 3327 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3328 3329 if (attr_mask & IB_QP_PKEY_INDEX) 3330 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3331 3332 /* todo implement counter_index functionality */ 3333 3334 if (is_sqp(ibqp->qp_type)) 3335 context->pri_path.port = qp->port; 3336 3337 if (attr_mask & IB_QP_PORT) 3338 context->pri_path.port = attr->port_num; 3339 3340 if (attr_mask & IB_QP_AV) { 3341 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3342 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3343 attr_mask, 0, attr, false); 3344 if (err) 3345 goto out; 3346 } 3347 3348 if (attr_mask & IB_QP_TIMEOUT) 3349 context->pri_path.ackto_lt |= attr->timeout << 3; 3350 3351 if (attr_mask & IB_QP_ALT_PATH) { 3352 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3353 &context->alt_path, 3354 attr->alt_port_num, 3355 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3356 0, attr, true); 3357 if (err) 3358 goto out; 3359 } 3360 3361 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3362 &send_cq, &recv_cq); 3363 3364 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3365 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3366 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3367 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3368 3369 if (attr_mask & IB_QP_RNR_RETRY) 3370 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3371 3372 if (attr_mask & IB_QP_RETRY_CNT) 3373 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3374 3375 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3376 if (attr->max_rd_atomic) 3377 context->params1 |= 3378 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3379 } 3380 3381 if (attr_mask & IB_QP_SQ_PSN) 3382 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3383 3384 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3385 if (attr->max_dest_rd_atomic) 3386 context->params2 |= 3387 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3388 } 3389 3390 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3391 __be32 access_flags = 0; 3392 3393 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 3394 if (err) 3395 goto out; 3396 3397 context->params2 |= access_flags; 3398 } 3399 3400 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3401 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3402 3403 if (attr_mask & IB_QP_RQ_PSN) 3404 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3405 3406 if (attr_mask & IB_QP_QKEY) 3407 context->qkey = cpu_to_be32(attr->qkey); 3408 3409 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3410 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3411 3412 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3413 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3414 qp->port) - 1; 3415 3416 /* Underlay port should be used - index 0 function per port */ 3417 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3418 port_num = 0; 3419 3420 mibport = &dev->port[port_num]; 3421 context->qp_counter_set_usr_page |= 3422 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3423 } 3424 3425 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3426 context->sq_crq_size |= cpu_to_be16(1 << 4); 3427 3428 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3429 context->deth_sqpn = cpu_to_be32(1); 3430 3431 mlx5_cur = to_mlx5_state(cur_state); 3432 mlx5_new = to_mlx5_state(new_state); 3433 3434 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3435 !optab[mlx5_cur][mlx5_new]) { 3436 err = -EINVAL; 3437 goto out; 3438 } 3439 3440 op = optab[mlx5_cur][mlx5_new]; 3441 optpar = ib_mask_to_mlx5_opt(attr_mask); 3442 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3443 3444 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3445 qp->flags & MLX5_IB_QP_UNDERLAY) { 3446 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3447 3448 raw_qp_param.operation = op; 3449 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3450 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3451 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3452 } 3453 3454 if (attr_mask & IB_QP_RATE_LIMIT) { 3455 raw_qp_param.rl.rate = attr->rate_limit; 3456 3457 if (ucmd->burst_info.max_burst_sz) { 3458 if (attr->rate_limit && 3459 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3460 raw_qp_param.rl.max_burst_sz = 3461 ucmd->burst_info.max_burst_sz; 3462 } else { 3463 err = -EINVAL; 3464 goto out; 3465 } 3466 } 3467 3468 if (ucmd->burst_info.typical_pkt_sz) { 3469 if (attr->rate_limit && 3470 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3471 raw_qp_param.rl.typical_pkt_sz = 3472 ucmd->burst_info.typical_pkt_sz; 3473 } else { 3474 err = -EINVAL; 3475 goto out; 3476 } 3477 } 3478 3479 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3480 } 3481 3482 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3483 } else { 3484 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3485 &base->mqp); 3486 } 3487 3488 if (err) 3489 goto out; 3490 3491 qp->state = new_state; 3492 3493 if (attr_mask & IB_QP_ACCESS_FLAGS) 3494 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3495 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3496 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3497 if (attr_mask & IB_QP_PORT) 3498 qp->port = attr->port_num; 3499 if (attr_mask & IB_QP_ALT_PATH) 3500 qp->trans_qp.alt_port = attr->alt_port_num; 3501 3502 /* 3503 * If we moved a kernel QP to RESET, clean up all old CQ 3504 * entries and reinitialize the QP. 3505 */ 3506 if (new_state == IB_QPS_RESET && 3507 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 3508 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3509 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3510 if (send_cq != recv_cq) 3511 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3512 3513 qp->rq.head = 0; 3514 qp->rq.tail = 0; 3515 qp->sq.head = 0; 3516 qp->sq.tail = 0; 3517 qp->sq.cur_post = 0; 3518 if (qp->sq.wqe_cnt) 3519 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 3520 qp->db.db[MLX5_RCV_DBR] = 0; 3521 qp->db.db[MLX5_SND_DBR] = 0; 3522 } 3523 3524 out: 3525 kfree(context); 3526 return err; 3527 } 3528 3529 static inline bool is_valid_mask(int mask, int req, int opt) 3530 { 3531 if ((mask & req) != req) 3532 return false; 3533 3534 if (mask & ~(req | opt)) 3535 return false; 3536 3537 return true; 3538 } 3539 3540 /* check valid transition for driver QP types 3541 * for now the only QP type that this function supports is DCI 3542 */ 3543 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3544 enum ib_qp_attr_mask attr_mask) 3545 { 3546 int req = IB_QP_STATE; 3547 int opt = 0; 3548 3549 if (new_state == IB_QPS_RESET) { 3550 return is_valid_mask(attr_mask, req, opt); 3551 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3552 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3553 return is_valid_mask(attr_mask, req, opt); 3554 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3555 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3556 return is_valid_mask(attr_mask, req, opt); 3557 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3558 req |= IB_QP_PATH_MTU; 3559 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 3560 return is_valid_mask(attr_mask, req, opt); 3561 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3562 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3563 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3564 opt = IB_QP_MIN_RNR_TIMER; 3565 return is_valid_mask(attr_mask, req, opt); 3566 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3567 opt = IB_QP_MIN_RNR_TIMER; 3568 return is_valid_mask(attr_mask, req, opt); 3569 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3570 return is_valid_mask(attr_mask, req, opt); 3571 } 3572 return false; 3573 } 3574 3575 /* mlx5_ib_modify_dct: modify a DCT QP 3576 * valid transitions are: 3577 * RESET to INIT: must set access_flags, pkey_index and port 3578 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3579 * mtu, gid_index and hop_limit 3580 * Other transitions and attributes are illegal 3581 */ 3582 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3583 int attr_mask, struct ib_udata *udata) 3584 { 3585 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3586 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3587 enum ib_qp_state cur_state, new_state; 3588 int err = 0; 3589 int required = IB_QP_STATE; 3590 void *dctc; 3591 3592 if (!(attr_mask & IB_QP_STATE)) 3593 return -EINVAL; 3594 3595 cur_state = qp->state; 3596 new_state = attr->qp_state; 3597 3598 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3599 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3600 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3601 if (!is_valid_mask(attr_mask, required, 0)) 3602 return -EINVAL; 3603 3604 if (attr->port_num == 0 || 3605 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3606 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3607 attr->port_num, dev->num_ports); 3608 return -EINVAL; 3609 } 3610 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3611 MLX5_SET(dctc, dctc, rre, 1); 3612 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3613 MLX5_SET(dctc, dctc, rwe, 1); 3614 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3615 int atomic_mode; 3616 3617 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 3618 if (atomic_mode < 0) 3619 return -EOPNOTSUPP; 3620 3621 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 3622 MLX5_SET(dctc, dctc, rae, 1); 3623 } 3624 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3625 MLX5_SET(dctc, dctc, port, attr->port_num); 3626 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3627 3628 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3629 struct mlx5_ib_modify_qp_resp resp = {}; 3630 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3631 sizeof(resp.dctn); 3632 3633 if (udata->outlen < min_resp_len) 3634 return -EINVAL; 3635 resp.response_length = min_resp_len; 3636 3637 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3638 if (!is_valid_mask(attr_mask, required, 0)) 3639 return -EINVAL; 3640 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3641 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3642 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3643 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3644 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3645 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3646 3647 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3648 MLX5_ST_SZ_BYTES(create_dct_in)); 3649 if (err) 3650 return err; 3651 resp.dctn = qp->dct.mdct.mqp.qpn; 3652 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3653 if (err) { 3654 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3655 return err; 3656 } 3657 } else { 3658 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3659 return -EINVAL; 3660 } 3661 if (err) 3662 qp->state = IB_QPS_ERR; 3663 else 3664 qp->state = new_state; 3665 return err; 3666 } 3667 3668 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3669 int attr_mask, struct ib_udata *udata) 3670 { 3671 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3672 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3673 struct mlx5_ib_modify_qp ucmd = {}; 3674 enum ib_qp_type qp_type; 3675 enum ib_qp_state cur_state, new_state; 3676 size_t required_cmd_sz; 3677 int err = -EINVAL; 3678 int port; 3679 3680 if (ibqp->rwq_ind_tbl) 3681 return -ENOSYS; 3682 3683 if (udata && udata->inlen) { 3684 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 3685 sizeof(ucmd.reserved); 3686 if (udata->inlen < required_cmd_sz) 3687 return -EINVAL; 3688 3689 if (udata->inlen > sizeof(ucmd) && 3690 !ib_is_udata_cleared(udata, sizeof(ucmd), 3691 udata->inlen - sizeof(ucmd))) 3692 return -EOPNOTSUPP; 3693 3694 if (ib_copy_from_udata(&ucmd, udata, 3695 min(udata->inlen, sizeof(ucmd)))) 3696 return -EFAULT; 3697 3698 if (ucmd.comp_mask || 3699 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || 3700 memchr_inv(&ucmd.burst_info.reserved, 0, 3701 sizeof(ucmd.burst_info.reserved))) 3702 return -EOPNOTSUPP; 3703 } 3704 3705 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3706 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3707 3708 if (ibqp->qp_type == IB_QPT_DRIVER) 3709 qp_type = qp->qp_sub_type; 3710 else 3711 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3712 IB_QPT_GSI : ibqp->qp_type; 3713 3714 if (qp_type == MLX5_IB_QPT_DCT) 3715 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3716 3717 mutex_lock(&qp->mutex); 3718 3719 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3720 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3721 3722 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3723 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3724 } 3725 3726 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3727 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3728 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3729 attr_mask); 3730 goto out; 3731 } 3732 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3733 qp_type != MLX5_IB_QPT_DCI && 3734 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 3735 attr_mask)) { 3736 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3737 cur_state, new_state, ibqp->qp_type, attr_mask); 3738 goto out; 3739 } else if (qp_type == MLX5_IB_QPT_DCI && 3740 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3741 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3742 cur_state, new_state, qp_type, attr_mask); 3743 goto out; 3744 } 3745 3746 if ((attr_mask & IB_QP_PORT) && 3747 (attr->port_num == 0 || 3748 attr->port_num > dev->num_ports)) { 3749 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3750 attr->port_num, dev->num_ports); 3751 goto out; 3752 } 3753 3754 if (attr_mask & IB_QP_PKEY_INDEX) { 3755 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3756 if (attr->pkey_index >= 3757 dev->mdev->port_caps[port - 1].pkey_table_len) { 3758 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3759 attr->pkey_index); 3760 goto out; 3761 } 3762 } 3763 3764 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3765 attr->max_rd_atomic > 3766 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3767 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3768 attr->max_rd_atomic); 3769 goto out; 3770 } 3771 3772 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3773 attr->max_dest_rd_atomic > 3774 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3775 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3776 attr->max_dest_rd_atomic); 3777 goto out; 3778 } 3779 3780 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3781 err = 0; 3782 goto out; 3783 } 3784 3785 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 3786 new_state, &ucmd); 3787 3788 out: 3789 mutex_unlock(&qp->mutex); 3790 return err; 3791 } 3792 3793 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3794 u32 wqe_sz, void **cur_edge) 3795 { 3796 u32 idx; 3797 3798 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); 3799 *cur_edge = get_sq_edge(sq, idx); 3800 3801 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); 3802 } 3803 3804 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the 3805 * next nearby edge and get new address translation for current WQE position. 3806 * @sq - SQ buffer. 3807 * @seg: Current WQE position (16B aligned). 3808 * @wqe_sz: Total current WQE size [16B]. 3809 * @cur_edge: Updated current edge. 3810 */ 3811 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, 3812 u32 wqe_sz, void **cur_edge) 3813 { 3814 if (likely(*seg != *cur_edge)) 3815 return; 3816 3817 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); 3818 } 3819 3820 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's 3821 * pointers. At the end @seg is aligned to 16B regardless the copied size. 3822 * @sq - SQ buffer. 3823 * @cur_edge: Updated current edge. 3824 * @seg: Current WQE position (16B aligned). 3825 * @wqe_sz: Total current WQE size [16B]. 3826 * @src: Pointer to copy from. 3827 * @n: Number of bytes to copy. 3828 */ 3829 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, 3830 void **seg, u32 *wqe_sz, const void *src, 3831 size_t n) 3832 { 3833 while (likely(n)) { 3834 size_t leftlen = *cur_edge - *seg; 3835 size_t copysz = min_t(size_t, leftlen, n); 3836 size_t stride; 3837 3838 memcpy(*seg, src, copysz); 3839 3840 n -= copysz; 3841 src += copysz; 3842 stride = !n ? ALIGN(copysz, 16) : copysz; 3843 *seg += stride; 3844 *wqe_sz += stride >> 4; 3845 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); 3846 } 3847 } 3848 3849 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3850 { 3851 struct mlx5_ib_cq *cq; 3852 unsigned cur; 3853 3854 cur = wq->head - wq->tail; 3855 if (likely(cur + nreq < wq->max_post)) 3856 return 0; 3857 3858 cq = to_mcq(ib_cq); 3859 spin_lock(&cq->lock); 3860 cur = wq->head - wq->tail; 3861 spin_unlock(&cq->lock); 3862 3863 return cur + nreq >= wq->max_post; 3864 } 3865 3866 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3867 u64 remote_addr, u32 rkey) 3868 { 3869 rseg->raddr = cpu_to_be64(remote_addr); 3870 rseg->rkey = cpu_to_be32(rkey); 3871 rseg->reserved = 0; 3872 } 3873 3874 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 3875 void **seg, int *size, void **cur_edge) 3876 { 3877 struct mlx5_wqe_eth_seg *eseg = *seg; 3878 3879 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3880 3881 if (wr->send_flags & IB_SEND_IP_CSUM) 3882 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3883 MLX5_ETH_WQE_L4_CSUM; 3884 3885 if (wr->opcode == IB_WR_LSO) { 3886 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3887 size_t left, copysz; 3888 void *pdata = ud_wr->header; 3889 size_t stride; 3890 3891 left = ud_wr->hlen; 3892 eseg->mss = cpu_to_be16(ud_wr->mss); 3893 eseg->inline_hdr.sz = cpu_to_be16(left); 3894 3895 /* memcpy_send_wqe should get a 16B align address. Hence, we 3896 * first copy up to the current edge and then, if needed, 3897 * fall-through to memcpy_send_wqe. 3898 */ 3899 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, 3900 left); 3901 memcpy(eseg->inline_hdr.start, pdata, copysz); 3902 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - 3903 sizeof(eseg->inline_hdr.start) + copysz, 16); 3904 *size += stride / 16; 3905 *seg += stride; 3906 3907 if (copysz < left) { 3908 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 3909 left -= copysz; 3910 pdata += copysz; 3911 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, 3912 left); 3913 } 3914 3915 return; 3916 } 3917 3918 *seg += sizeof(struct mlx5_wqe_eth_seg); 3919 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3920 } 3921 3922 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3923 const struct ib_send_wr *wr) 3924 { 3925 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3926 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3927 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3928 } 3929 3930 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3931 { 3932 dseg->byte_count = cpu_to_be32(sg->length); 3933 dseg->lkey = cpu_to_be32(sg->lkey); 3934 dseg->addr = cpu_to_be64(sg->addr); 3935 } 3936 3937 static u64 get_xlt_octo(u64 bytes) 3938 { 3939 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3940 MLX5_IB_UMR_OCTOWORD; 3941 } 3942 3943 static __be64 frwr_mkey_mask(void) 3944 { 3945 u64 result; 3946 3947 result = MLX5_MKEY_MASK_LEN | 3948 MLX5_MKEY_MASK_PAGE_SIZE | 3949 MLX5_MKEY_MASK_START_ADDR | 3950 MLX5_MKEY_MASK_EN_RINVAL | 3951 MLX5_MKEY_MASK_KEY | 3952 MLX5_MKEY_MASK_LR | 3953 MLX5_MKEY_MASK_LW | 3954 MLX5_MKEY_MASK_RR | 3955 MLX5_MKEY_MASK_RW | 3956 MLX5_MKEY_MASK_A | 3957 MLX5_MKEY_MASK_SMALL_FENCE | 3958 MLX5_MKEY_MASK_FREE; 3959 3960 return cpu_to_be64(result); 3961 } 3962 3963 static __be64 sig_mkey_mask(void) 3964 { 3965 u64 result; 3966 3967 result = MLX5_MKEY_MASK_LEN | 3968 MLX5_MKEY_MASK_PAGE_SIZE | 3969 MLX5_MKEY_MASK_START_ADDR | 3970 MLX5_MKEY_MASK_EN_SIGERR | 3971 MLX5_MKEY_MASK_EN_RINVAL | 3972 MLX5_MKEY_MASK_KEY | 3973 MLX5_MKEY_MASK_LR | 3974 MLX5_MKEY_MASK_LW | 3975 MLX5_MKEY_MASK_RR | 3976 MLX5_MKEY_MASK_RW | 3977 MLX5_MKEY_MASK_SMALL_FENCE | 3978 MLX5_MKEY_MASK_FREE | 3979 MLX5_MKEY_MASK_BSF_EN; 3980 3981 return cpu_to_be64(result); 3982 } 3983 3984 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3985 struct mlx5_ib_mr *mr, bool umr_inline) 3986 { 3987 int size = mr->ndescs * mr->desc_size; 3988 3989 memset(umr, 0, sizeof(*umr)); 3990 3991 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3992 if (umr_inline) 3993 umr->flags |= MLX5_UMR_INLINE; 3994 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3995 umr->mkey_mask = frwr_mkey_mask(); 3996 } 3997 3998 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3999 { 4000 memset(umr, 0, sizeof(*umr)); 4001 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 4002 umr->flags = MLX5_UMR_INLINE; 4003 } 4004 4005 static __be64 get_umr_enable_mr_mask(void) 4006 { 4007 u64 result; 4008 4009 result = MLX5_MKEY_MASK_KEY | 4010 MLX5_MKEY_MASK_FREE; 4011 4012 return cpu_to_be64(result); 4013 } 4014 4015 static __be64 get_umr_disable_mr_mask(void) 4016 { 4017 u64 result; 4018 4019 result = MLX5_MKEY_MASK_FREE; 4020 4021 return cpu_to_be64(result); 4022 } 4023 4024 static __be64 get_umr_update_translation_mask(void) 4025 { 4026 u64 result; 4027 4028 result = MLX5_MKEY_MASK_LEN | 4029 MLX5_MKEY_MASK_PAGE_SIZE | 4030 MLX5_MKEY_MASK_START_ADDR; 4031 4032 return cpu_to_be64(result); 4033 } 4034 4035 static __be64 get_umr_update_access_mask(int atomic) 4036 { 4037 u64 result; 4038 4039 result = MLX5_MKEY_MASK_LR | 4040 MLX5_MKEY_MASK_LW | 4041 MLX5_MKEY_MASK_RR | 4042 MLX5_MKEY_MASK_RW; 4043 4044 if (atomic) 4045 result |= MLX5_MKEY_MASK_A; 4046 4047 return cpu_to_be64(result); 4048 } 4049 4050 static __be64 get_umr_update_pd_mask(void) 4051 { 4052 u64 result; 4053 4054 result = MLX5_MKEY_MASK_PD; 4055 4056 return cpu_to_be64(result); 4057 } 4058 4059 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 4060 { 4061 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && 4062 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || 4063 (mask & MLX5_MKEY_MASK_A && 4064 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) 4065 return -EPERM; 4066 return 0; 4067 } 4068 4069 static int set_reg_umr_segment(struct mlx5_ib_dev *dev, 4070 struct mlx5_wqe_umr_ctrl_seg *umr, 4071 const struct ib_send_wr *wr, int atomic) 4072 { 4073 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4074 4075 memset(umr, 0, sizeof(*umr)); 4076 4077 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 4078 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 4079 else 4080 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 4081 4082 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 4083 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 4084 u64 offset = get_xlt_octo(umrwr->offset); 4085 4086 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 4087 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 4088 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 4089 } 4090 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 4091 umr->mkey_mask |= get_umr_update_translation_mask(); 4092 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 4093 umr->mkey_mask |= get_umr_update_access_mask(atomic); 4094 umr->mkey_mask |= get_umr_update_pd_mask(); 4095 } 4096 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 4097 umr->mkey_mask |= get_umr_enable_mr_mask(); 4098 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4099 umr->mkey_mask |= get_umr_disable_mr_mask(); 4100 4101 if (!wr->num_sge) 4102 umr->flags |= MLX5_UMR_INLINE; 4103 4104 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); 4105 } 4106 4107 static u8 get_umr_flags(int acc) 4108 { 4109 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 4110 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 4111 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 4112 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 4113 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 4114 } 4115 4116 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 4117 struct mlx5_ib_mr *mr, 4118 u32 key, int access) 4119 { 4120 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 4121 4122 memset(seg, 0, sizeof(*seg)); 4123 4124 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 4125 seg->log2_page_size = ilog2(mr->ibmr.page_size); 4126 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 4127 /* KLMs take twice the size of MTTs */ 4128 ndescs *= 2; 4129 4130 seg->flags = get_umr_flags(access) | mr->access_mode; 4131 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 4132 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 4133 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 4134 seg->len = cpu_to_be64(mr->ibmr.length); 4135 seg->xlt_oct_size = cpu_to_be32(ndescs); 4136 } 4137 4138 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 4139 { 4140 memset(seg, 0, sizeof(*seg)); 4141 seg->status = MLX5_MKEY_STATUS_FREE; 4142 } 4143 4144 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, 4145 const struct ib_send_wr *wr) 4146 { 4147 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 4148 4149 memset(seg, 0, sizeof(*seg)); 4150 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 4151 seg->status = MLX5_MKEY_STATUS_FREE; 4152 4153 seg->flags = convert_access(umrwr->access_flags); 4154 if (umrwr->pd) 4155 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 4156 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 4157 !umrwr->length) 4158 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 4159 4160 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 4161 seg->len = cpu_to_be64(umrwr->length); 4162 seg->log2_page_size = umrwr->page_shift; 4163 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 4164 mlx5_mkey_variant(umrwr->mkey)); 4165 } 4166 4167 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 4168 struct mlx5_ib_mr *mr, 4169 struct mlx5_ib_pd *pd) 4170 { 4171 int bcount = mr->desc_size * mr->ndescs; 4172 4173 dseg->addr = cpu_to_be64(mr->desc_map); 4174 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 4175 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 4176 } 4177 4178 static __be32 send_ieth(const struct ib_send_wr *wr) 4179 { 4180 switch (wr->opcode) { 4181 case IB_WR_SEND_WITH_IMM: 4182 case IB_WR_RDMA_WRITE_WITH_IMM: 4183 return wr->ex.imm_data; 4184 4185 case IB_WR_SEND_WITH_INV: 4186 return cpu_to_be32(wr->ex.invalidate_rkey); 4187 4188 default: 4189 return 0; 4190 } 4191 } 4192 4193 static u8 calc_sig(void *wqe, int size) 4194 { 4195 u8 *p = wqe; 4196 u8 res = 0; 4197 int i; 4198 4199 for (i = 0; i < size; i++) 4200 res ^= p[i]; 4201 4202 return ~res; 4203 } 4204 4205 static u8 wq_sig(void *wqe) 4206 { 4207 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 4208 } 4209 4210 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 4211 void **wqe, int *wqe_sz, void **cur_edge) 4212 { 4213 struct mlx5_wqe_inline_seg *seg; 4214 size_t offset; 4215 int inl = 0; 4216 int i; 4217 4218 seg = *wqe; 4219 *wqe += sizeof(*seg); 4220 offset = sizeof(*seg); 4221 4222 for (i = 0; i < wr->num_sge; i++) { 4223 size_t len = wr->sg_list[i].length; 4224 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); 4225 4226 inl += len; 4227 4228 if (unlikely(inl > qp->max_inline_data)) 4229 return -ENOMEM; 4230 4231 while (likely(len)) { 4232 size_t leftlen; 4233 size_t copysz; 4234 4235 handle_post_send_edge(&qp->sq, wqe, 4236 *wqe_sz + (offset >> 4), 4237 cur_edge); 4238 4239 leftlen = *cur_edge - *wqe; 4240 copysz = min_t(size_t, leftlen, len); 4241 4242 memcpy(*wqe, addr, copysz); 4243 len -= copysz; 4244 addr += copysz; 4245 *wqe += copysz; 4246 offset += copysz; 4247 } 4248 } 4249 4250 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 4251 4252 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 4253 4254 return 0; 4255 } 4256 4257 static u16 prot_field_size(enum ib_signature_type type) 4258 { 4259 switch (type) { 4260 case IB_SIG_TYPE_T10_DIF: 4261 return MLX5_DIF_SIZE; 4262 default: 4263 return 0; 4264 } 4265 } 4266 4267 static u8 bs_selector(int block_size) 4268 { 4269 switch (block_size) { 4270 case 512: return 0x1; 4271 case 520: return 0x2; 4272 case 4096: return 0x3; 4273 case 4160: return 0x4; 4274 case 1073741824: return 0x5; 4275 default: return 0; 4276 } 4277 } 4278 4279 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 4280 struct mlx5_bsf_inl *inl) 4281 { 4282 /* Valid inline section and allow BSF refresh */ 4283 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 4284 MLX5_BSF_REFRESH_DIF); 4285 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 4286 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 4287 /* repeating block */ 4288 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 4289 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 4290 MLX5_DIF_CRC : MLX5_DIF_IPCS; 4291 4292 if (domain->sig.dif.ref_remap) 4293 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 4294 4295 if (domain->sig.dif.app_escape) { 4296 if (domain->sig.dif.ref_escape) 4297 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 4298 else 4299 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 4300 } 4301 4302 inl->dif_app_bitmask_check = 4303 cpu_to_be16(domain->sig.dif.apptag_check_mask); 4304 } 4305 4306 static int mlx5_set_bsf(struct ib_mr *sig_mr, 4307 struct ib_sig_attrs *sig_attrs, 4308 struct mlx5_bsf *bsf, u32 data_size) 4309 { 4310 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 4311 struct mlx5_bsf_basic *basic = &bsf->basic; 4312 struct ib_sig_domain *mem = &sig_attrs->mem; 4313 struct ib_sig_domain *wire = &sig_attrs->wire; 4314 4315 memset(bsf, 0, sizeof(*bsf)); 4316 4317 /* Basic + Extended + Inline */ 4318 basic->bsf_size_sbs = 1 << 7; 4319 /* Input domain check byte mask */ 4320 basic->check_byte_mask = sig_attrs->check_mask; 4321 basic->raw_data_size = cpu_to_be32(data_size); 4322 4323 /* Memory domain */ 4324 switch (sig_attrs->mem.sig_type) { 4325 case IB_SIG_TYPE_NONE: 4326 break; 4327 case IB_SIG_TYPE_T10_DIF: 4328 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 4329 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 4330 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 4331 break; 4332 default: 4333 return -EINVAL; 4334 } 4335 4336 /* Wire domain */ 4337 switch (sig_attrs->wire.sig_type) { 4338 case IB_SIG_TYPE_NONE: 4339 break; 4340 case IB_SIG_TYPE_T10_DIF: 4341 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 4342 mem->sig_type == wire->sig_type) { 4343 /* Same block structure */ 4344 basic->bsf_size_sbs |= 1 << 4; 4345 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 4346 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 4347 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 4348 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 4349 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 4350 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 4351 } else 4352 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 4353 4354 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 4355 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 4356 break; 4357 default: 4358 return -EINVAL; 4359 } 4360 4361 return 0; 4362 } 4363 4364 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 4365 struct mlx5_ib_qp *qp, void **seg, 4366 int *size, void **cur_edge) 4367 { 4368 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 4369 struct ib_mr *sig_mr = wr->sig_mr; 4370 struct mlx5_bsf *bsf; 4371 u32 data_len = wr->wr.sg_list->length; 4372 u32 data_key = wr->wr.sg_list->lkey; 4373 u64 data_va = wr->wr.sg_list->addr; 4374 int ret; 4375 int wqe_size; 4376 4377 if (!wr->prot || 4378 (data_key == wr->prot->lkey && 4379 data_va == wr->prot->addr && 4380 data_len == wr->prot->length)) { 4381 /** 4382 * Source domain doesn't contain signature information 4383 * or data and protection are interleaved in memory. 4384 * So need construct: 4385 * ------------------ 4386 * | data_klm | 4387 * ------------------ 4388 * | BSF | 4389 * ------------------ 4390 **/ 4391 struct mlx5_klm *data_klm = *seg; 4392 4393 data_klm->bcount = cpu_to_be32(data_len); 4394 data_klm->key = cpu_to_be32(data_key); 4395 data_klm->va = cpu_to_be64(data_va); 4396 wqe_size = ALIGN(sizeof(*data_klm), 64); 4397 } else { 4398 /** 4399 * Source domain contains signature information 4400 * So need construct a strided block format: 4401 * --------------------------- 4402 * | stride_block_ctrl | 4403 * --------------------------- 4404 * | data_klm | 4405 * --------------------------- 4406 * | prot_klm | 4407 * --------------------------- 4408 * | BSF | 4409 * --------------------------- 4410 **/ 4411 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 4412 struct mlx5_stride_block_entry *data_sentry; 4413 struct mlx5_stride_block_entry *prot_sentry; 4414 u32 prot_key = wr->prot->lkey; 4415 u64 prot_va = wr->prot->addr; 4416 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 4417 int prot_size; 4418 4419 sblock_ctrl = *seg; 4420 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 4421 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 4422 4423 prot_size = prot_field_size(sig_attrs->mem.sig_type); 4424 if (!prot_size) { 4425 pr_err("Bad block size given: %u\n", block_size); 4426 return -EINVAL; 4427 } 4428 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 4429 prot_size); 4430 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 4431 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 4432 sblock_ctrl->num_entries = cpu_to_be16(2); 4433 4434 data_sentry->bcount = cpu_to_be16(block_size); 4435 data_sentry->key = cpu_to_be32(data_key); 4436 data_sentry->va = cpu_to_be64(data_va); 4437 data_sentry->stride = cpu_to_be16(block_size); 4438 4439 prot_sentry->bcount = cpu_to_be16(prot_size); 4440 prot_sentry->key = cpu_to_be32(prot_key); 4441 prot_sentry->va = cpu_to_be64(prot_va); 4442 prot_sentry->stride = cpu_to_be16(prot_size); 4443 4444 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4445 sizeof(*prot_sentry), 64); 4446 } 4447 4448 *seg += wqe_size; 4449 *size += wqe_size / 16; 4450 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4451 4452 bsf = *seg; 4453 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4454 if (ret) 4455 return -EINVAL; 4456 4457 *seg += sizeof(*bsf); 4458 *size += sizeof(*bsf) / 16; 4459 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4460 4461 return 0; 4462 } 4463 4464 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4465 const struct ib_sig_handover_wr *wr, u32 size, 4466 u32 length, u32 pdn) 4467 { 4468 struct ib_mr *sig_mr = wr->sig_mr; 4469 u32 sig_key = sig_mr->rkey; 4470 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4471 4472 memset(seg, 0, sizeof(*seg)); 4473 4474 seg->flags = get_umr_flags(wr->access_flags) | 4475 MLX5_MKC_ACCESS_MODE_KLMS; 4476 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4477 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4478 MLX5_MKEY_BSF_EN | pdn); 4479 seg->len = cpu_to_be64(length); 4480 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4481 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4482 } 4483 4484 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4485 u32 size) 4486 { 4487 memset(umr, 0, sizeof(*umr)); 4488 4489 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4490 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4491 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4492 umr->mkey_mask = sig_mkey_mask(); 4493 } 4494 4495 4496 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, 4497 struct mlx5_ib_qp *qp, void **seg, int *size, 4498 void **cur_edge) 4499 { 4500 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4501 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4502 u32 pdn = get_pd(qp)->pdn; 4503 u32 xlt_size; 4504 int region_len, ret; 4505 4506 if (unlikely(wr->wr.num_sge != 1) || 4507 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4508 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4509 unlikely(!sig_mr->sig->sig_status_checked)) 4510 return -EINVAL; 4511 4512 /* length of the protected region, data + protection */ 4513 region_len = wr->wr.sg_list->length; 4514 if (wr->prot && 4515 (wr->prot->lkey != wr->wr.sg_list->lkey || 4516 wr->prot->addr != wr->wr.sg_list->addr || 4517 wr->prot->length != wr->wr.sg_list->length)) 4518 region_len += wr->prot->length; 4519 4520 /** 4521 * KLM octoword size - if protection was provided 4522 * then we use strided block format (3 octowords), 4523 * else we use single KLM (1 octoword) 4524 **/ 4525 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4526 4527 set_sig_umr_segment(*seg, xlt_size); 4528 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4529 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4530 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4531 4532 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4533 *seg += sizeof(struct mlx5_mkey_seg); 4534 *size += sizeof(struct mlx5_mkey_seg) / 16; 4535 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4536 4537 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge); 4538 if (ret) 4539 return ret; 4540 4541 sig_mr->sig->sig_status_checked = false; 4542 return 0; 4543 } 4544 4545 static int set_psv_wr(struct ib_sig_domain *domain, 4546 u32 psv_idx, void **seg, int *size) 4547 { 4548 struct mlx5_seg_set_psv *psv_seg = *seg; 4549 4550 memset(psv_seg, 0, sizeof(*psv_seg)); 4551 psv_seg->psv_num = cpu_to_be32(psv_idx); 4552 switch (domain->sig_type) { 4553 case IB_SIG_TYPE_NONE: 4554 break; 4555 case IB_SIG_TYPE_T10_DIF: 4556 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4557 domain->sig.dif.app_tag); 4558 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4559 break; 4560 default: 4561 pr_err("Bad signature type (%d) is given.\n", 4562 domain->sig_type); 4563 return -EINVAL; 4564 } 4565 4566 *seg += sizeof(*psv_seg); 4567 *size += sizeof(*psv_seg) / 16; 4568 4569 return 0; 4570 } 4571 4572 static int set_reg_wr(struct mlx5_ib_qp *qp, 4573 const struct ib_reg_wr *wr, 4574 void **seg, int *size, void **cur_edge) 4575 { 4576 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4577 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4578 size_t mr_list_size = mr->ndescs * mr->desc_size; 4579 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; 4580 4581 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4582 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4583 "Invalid IB_SEND_INLINE send flag\n"); 4584 return -EINVAL; 4585 } 4586 4587 set_reg_umr_seg(*seg, mr, umr_inline); 4588 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4589 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4590 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4591 4592 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4593 *seg += sizeof(struct mlx5_mkey_seg); 4594 *size += sizeof(struct mlx5_mkey_seg) / 16; 4595 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4596 4597 if (umr_inline) { 4598 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, 4599 mr_list_size); 4600 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); 4601 } else { 4602 set_reg_data_seg(*seg, mr, pd); 4603 *seg += sizeof(struct mlx5_wqe_data_seg); 4604 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4605 } 4606 return 0; 4607 } 4608 4609 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, 4610 void **cur_edge) 4611 { 4612 set_linv_umr_seg(*seg); 4613 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4614 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4615 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4616 set_linv_mkey_seg(*seg); 4617 *seg += sizeof(struct mlx5_mkey_seg); 4618 *size += sizeof(struct mlx5_mkey_seg) / 16; 4619 handle_post_send_edge(&qp->sq, seg, *size, cur_edge); 4620 } 4621 4622 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) 4623 { 4624 __be32 *p = NULL; 4625 u32 tidx = idx; 4626 int i, j; 4627 4628 pr_debug("dump WQE index %u:\n", idx); 4629 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4630 if ((i & 0xf) == 0) { 4631 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4632 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx); 4633 pr_debug("WQBB at %p:\n", (void *)p); 4634 j = 0; 4635 } 4636 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4637 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4638 be32_to_cpu(p[j + 3])); 4639 } 4640 } 4641 4642 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4643 struct mlx5_wqe_ctrl_seg **ctrl, 4644 const struct ib_send_wr *wr, unsigned int *idx, 4645 int *size, void **cur_edge, int nreq, 4646 bool send_signaled, bool solicited) 4647 { 4648 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4649 return -ENOMEM; 4650 4651 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4652 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); 4653 *ctrl = *seg; 4654 *(uint32_t *)(*seg + 8) = 0; 4655 (*ctrl)->imm = send_ieth(wr); 4656 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4657 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4658 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 4659 4660 *seg += sizeof(**ctrl); 4661 *size = sizeof(**ctrl) / 16; 4662 *cur_edge = qp->sq.cur_edge; 4663 4664 return 0; 4665 } 4666 4667 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4668 struct mlx5_wqe_ctrl_seg **ctrl, 4669 const struct ib_send_wr *wr, unsigned *idx, 4670 int *size, void **cur_edge, int nreq) 4671 { 4672 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, 4673 wr->send_flags & IB_SEND_SIGNALED, 4674 wr->send_flags & IB_SEND_SOLICITED); 4675 } 4676 4677 static void finish_wqe(struct mlx5_ib_qp *qp, 4678 struct mlx5_wqe_ctrl_seg *ctrl, 4679 void *seg, u8 size, void *cur_edge, 4680 unsigned int idx, u64 wr_id, int nreq, u8 fence, 4681 u32 mlx5_opcode) 4682 { 4683 u8 opmod = 0; 4684 4685 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4686 mlx5_opcode | ((u32)opmod << 24)); 4687 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4688 ctrl->fm_ce_se |= fence; 4689 if (unlikely(qp->wq_sig)) 4690 ctrl->signature = wq_sig(ctrl); 4691 4692 qp->sq.wrid[idx] = wr_id; 4693 qp->sq.w_list[idx].opcode = mlx5_opcode; 4694 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4695 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4696 qp->sq.w_list[idx].next = qp->sq.cur_post; 4697 4698 /* We save the edge which was possibly updated during the WQE 4699 * construction, into SQ's cache. 4700 */ 4701 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); 4702 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? 4703 get_sq_edge(&qp->sq, qp->sq.cur_post & 4704 (qp->sq.wqe_cnt - 1)) : 4705 cur_edge; 4706 } 4707 4708 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 4709 const struct ib_send_wr **bad_wr, bool drain) 4710 { 4711 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4712 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4713 struct mlx5_core_dev *mdev = dev->mdev; 4714 struct mlx5_ib_qp *qp; 4715 struct mlx5_ib_mr *mr; 4716 struct mlx5_wqe_xrc_seg *xrc; 4717 struct mlx5_bf *bf; 4718 void *cur_edge; 4719 int uninitialized_var(size); 4720 unsigned long flags; 4721 unsigned idx; 4722 int err = 0; 4723 int num_sge; 4724 void *seg; 4725 int nreq; 4726 int i; 4727 u8 next_fence = 0; 4728 u8 fence; 4729 4730 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 4731 !drain)) { 4732 *bad_wr = wr; 4733 return -EIO; 4734 } 4735 4736 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4737 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4738 4739 qp = to_mqp(ibqp); 4740 bf = &qp->bf; 4741 4742 spin_lock_irqsave(&qp->sq.lock, flags); 4743 4744 for (nreq = 0; wr; nreq++, wr = wr->next) { 4745 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4746 mlx5_ib_warn(dev, "\n"); 4747 err = -EINVAL; 4748 *bad_wr = wr; 4749 goto out; 4750 } 4751 4752 num_sge = wr->num_sge; 4753 if (unlikely(num_sge > qp->sq.max_gs)) { 4754 mlx5_ib_warn(dev, "\n"); 4755 err = -EINVAL; 4756 *bad_wr = wr; 4757 goto out; 4758 } 4759 4760 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, 4761 nreq); 4762 if (err) { 4763 mlx5_ib_warn(dev, "\n"); 4764 err = -ENOMEM; 4765 *bad_wr = wr; 4766 goto out; 4767 } 4768 4769 if (wr->opcode == IB_WR_REG_MR) { 4770 fence = dev->umr_fence; 4771 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4772 } else { 4773 if (wr->send_flags & IB_SEND_FENCE) { 4774 if (qp->next_fence) 4775 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4776 else 4777 fence = MLX5_FENCE_MODE_FENCE; 4778 } else { 4779 fence = qp->next_fence; 4780 } 4781 } 4782 4783 switch (ibqp->qp_type) { 4784 case IB_QPT_XRC_INI: 4785 xrc = seg; 4786 seg += sizeof(*xrc); 4787 size += sizeof(*xrc) / 16; 4788 /* fall through */ 4789 case IB_QPT_RC: 4790 switch (wr->opcode) { 4791 case IB_WR_RDMA_READ: 4792 case IB_WR_RDMA_WRITE: 4793 case IB_WR_RDMA_WRITE_WITH_IMM: 4794 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4795 rdma_wr(wr)->rkey); 4796 seg += sizeof(struct mlx5_wqe_raddr_seg); 4797 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4798 break; 4799 4800 case IB_WR_ATOMIC_CMP_AND_SWP: 4801 case IB_WR_ATOMIC_FETCH_AND_ADD: 4802 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4803 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4804 err = -ENOSYS; 4805 *bad_wr = wr; 4806 goto out; 4807 4808 case IB_WR_LOCAL_INV: 4809 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4810 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4811 set_linv_wr(qp, &seg, &size, &cur_edge); 4812 num_sge = 0; 4813 break; 4814 4815 case IB_WR_REG_MR: 4816 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4817 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4818 err = set_reg_wr(qp, reg_wr(wr), &seg, &size, 4819 &cur_edge); 4820 if (err) { 4821 *bad_wr = wr; 4822 goto out; 4823 } 4824 num_sge = 0; 4825 break; 4826 4827 case IB_WR_REG_SIG_MR: 4828 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4829 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4830 4831 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4832 err = set_sig_umr_wr(wr, qp, &seg, &size, 4833 &cur_edge); 4834 if (err) { 4835 mlx5_ib_warn(dev, "\n"); 4836 *bad_wr = wr; 4837 goto out; 4838 } 4839 4840 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4841 wr->wr_id, nreq, fence, 4842 MLX5_OPCODE_UMR); 4843 /* 4844 * SET_PSV WQEs are not signaled and solicited 4845 * on error 4846 */ 4847 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4848 &size, &cur_edge, nreq, false, 4849 true); 4850 if (err) { 4851 mlx5_ib_warn(dev, "\n"); 4852 err = -ENOMEM; 4853 *bad_wr = wr; 4854 goto out; 4855 } 4856 4857 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4858 mr->sig->psv_memory.psv_idx, &seg, 4859 &size); 4860 if (err) { 4861 mlx5_ib_warn(dev, "\n"); 4862 *bad_wr = wr; 4863 goto out; 4864 } 4865 4866 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4867 wr->wr_id, nreq, fence, 4868 MLX5_OPCODE_SET_PSV); 4869 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, 4870 &size, &cur_edge, nreq, false, 4871 true); 4872 if (err) { 4873 mlx5_ib_warn(dev, "\n"); 4874 err = -ENOMEM; 4875 *bad_wr = wr; 4876 goto out; 4877 } 4878 4879 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4880 mr->sig->psv_wire.psv_idx, &seg, 4881 &size); 4882 if (err) { 4883 mlx5_ib_warn(dev, "\n"); 4884 *bad_wr = wr; 4885 goto out; 4886 } 4887 4888 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, 4889 wr->wr_id, nreq, fence, 4890 MLX5_OPCODE_SET_PSV); 4891 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4892 num_sge = 0; 4893 goto skip_psv; 4894 4895 default: 4896 break; 4897 } 4898 break; 4899 4900 case IB_QPT_UC: 4901 switch (wr->opcode) { 4902 case IB_WR_RDMA_WRITE: 4903 case IB_WR_RDMA_WRITE_WITH_IMM: 4904 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4905 rdma_wr(wr)->rkey); 4906 seg += sizeof(struct mlx5_wqe_raddr_seg); 4907 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4908 break; 4909 4910 default: 4911 break; 4912 } 4913 break; 4914 4915 case IB_QPT_SMI: 4916 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4917 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4918 err = -EPERM; 4919 *bad_wr = wr; 4920 goto out; 4921 } 4922 /* fall through */ 4923 case MLX5_IB_QPT_HW_GSI: 4924 set_datagram_seg(seg, wr); 4925 seg += sizeof(struct mlx5_wqe_datagram_seg); 4926 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4927 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4928 4929 break; 4930 case IB_QPT_UD: 4931 set_datagram_seg(seg, wr); 4932 seg += sizeof(struct mlx5_wqe_datagram_seg); 4933 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4934 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4935 4936 /* handle qp that supports ud offload */ 4937 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4938 struct mlx5_wqe_eth_pad *pad; 4939 4940 pad = seg; 4941 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4942 seg += sizeof(struct mlx5_wqe_eth_pad); 4943 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4944 set_eth_seg(wr, qp, &seg, &size, &cur_edge); 4945 handle_post_send_edge(&qp->sq, &seg, size, 4946 &cur_edge); 4947 } 4948 break; 4949 case MLX5_IB_QPT_REG_UMR: 4950 if (wr->opcode != MLX5_IB_WR_UMR) { 4951 err = -EINVAL; 4952 mlx5_ib_warn(dev, "bad opcode\n"); 4953 goto out; 4954 } 4955 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4956 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4957 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4958 if (unlikely(err)) 4959 goto out; 4960 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4961 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4962 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4963 set_reg_mkey_segment(seg, wr); 4964 seg += sizeof(struct mlx5_mkey_seg); 4965 size += sizeof(struct mlx5_mkey_seg) / 16; 4966 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); 4967 break; 4968 4969 default: 4970 break; 4971 } 4972 4973 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4974 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); 4975 if (unlikely(err)) { 4976 mlx5_ib_warn(dev, "\n"); 4977 *bad_wr = wr; 4978 goto out; 4979 } 4980 } else { 4981 for (i = 0; i < num_sge; i++) { 4982 handle_post_send_edge(&qp->sq, &seg, size, 4983 &cur_edge); 4984 if (likely(wr->sg_list[i].length)) { 4985 set_data_ptr_seg 4986 ((struct mlx5_wqe_data_seg *)seg, 4987 wr->sg_list + i); 4988 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4989 seg += sizeof(struct mlx5_wqe_data_seg); 4990 } 4991 } 4992 } 4993 4994 qp->next_fence = next_fence; 4995 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, 4996 fence, mlx5_ib_opcode[wr->opcode]); 4997 skip_psv: 4998 if (0) 4999 dump_wqe(qp, idx, size); 5000 } 5001 5002 out: 5003 if (likely(nreq)) { 5004 qp->sq.head += nreq; 5005 5006 /* Make sure that descriptors are written before 5007 * updating doorbell record and ringing the doorbell 5008 */ 5009 wmb(); 5010 5011 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 5012 5013 /* Make sure doorbell record is visible to the HCA before 5014 * we hit doorbell */ 5015 wmb(); 5016 5017 /* currently we support only regular doorbells */ 5018 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 5019 /* Make sure doorbells don't leak out of SQ spinlock 5020 * and reach the HCA out of order. 5021 */ 5022 mmiowb(); 5023 bf->offset ^= bf->buf_size; 5024 } 5025 5026 spin_unlock_irqrestore(&qp->sq.lock, flags); 5027 5028 return err; 5029 } 5030 5031 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 5032 const struct ib_send_wr **bad_wr) 5033 { 5034 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); 5035 } 5036 5037 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 5038 { 5039 sig->signature = calc_sig(sig, size); 5040 } 5041 5042 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5043 const struct ib_recv_wr **bad_wr, bool drain) 5044 { 5045 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5046 struct mlx5_wqe_data_seg *scat; 5047 struct mlx5_rwqe_sig *sig; 5048 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5049 struct mlx5_core_dev *mdev = dev->mdev; 5050 unsigned long flags; 5051 int err = 0; 5052 int nreq; 5053 int ind; 5054 int i; 5055 5056 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && 5057 !drain)) { 5058 *bad_wr = wr; 5059 return -EIO; 5060 } 5061 5062 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5063 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 5064 5065 spin_lock_irqsave(&qp->rq.lock, flags); 5066 5067 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 5068 5069 for (nreq = 0; wr; nreq++, wr = wr->next) { 5070 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 5071 err = -ENOMEM; 5072 *bad_wr = wr; 5073 goto out; 5074 } 5075 5076 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 5077 err = -EINVAL; 5078 *bad_wr = wr; 5079 goto out; 5080 } 5081 5082 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); 5083 if (qp->wq_sig) 5084 scat++; 5085 5086 for (i = 0; i < wr->num_sge; i++) 5087 set_data_ptr_seg(scat + i, wr->sg_list + i); 5088 5089 if (i < qp->rq.max_gs) { 5090 scat[i].byte_count = 0; 5091 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 5092 scat[i].addr = 0; 5093 } 5094 5095 if (qp->wq_sig) { 5096 sig = (struct mlx5_rwqe_sig *)scat; 5097 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 5098 } 5099 5100 qp->rq.wrid[ind] = wr->wr_id; 5101 5102 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 5103 } 5104 5105 out: 5106 if (likely(nreq)) { 5107 qp->rq.head += nreq; 5108 5109 /* Make sure that descriptors are written before 5110 * doorbell record. 5111 */ 5112 wmb(); 5113 5114 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 5115 } 5116 5117 spin_unlock_irqrestore(&qp->rq.lock, flags); 5118 5119 return err; 5120 } 5121 5122 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 5123 const struct ib_recv_wr **bad_wr) 5124 { 5125 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); 5126 } 5127 5128 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 5129 { 5130 switch (mlx5_state) { 5131 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 5132 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 5133 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 5134 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 5135 case MLX5_QP_STATE_SQ_DRAINING: 5136 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 5137 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 5138 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 5139 default: return -1; 5140 } 5141 } 5142 5143 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 5144 { 5145 switch (mlx5_mig_state) { 5146 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 5147 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 5148 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 5149 default: return -1; 5150 } 5151 } 5152 5153 static int to_ib_qp_access_flags(int mlx5_flags) 5154 { 5155 int ib_flags = 0; 5156 5157 if (mlx5_flags & MLX5_QP_BIT_RRE) 5158 ib_flags |= IB_ACCESS_REMOTE_READ; 5159 if (mlx5_flags & MLX5_QP_BIT_RWE) 5160 ib_flags |= IB_ACCESS_REMOTE_WRITE; 5161 if (mlx5_flags & MLX5_QP_BIT_RAE) 5162 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 5163 5164 return ib_flags; 5165 } 5166 5167 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 5168 struct rdma_ah_attr *ah_attr, 5169 struct mlx5_qp_path *path) 5170 { 5171 5172 memset(ah_attr, 0, sizeof(*ah_attr)); 5173 5174 if (!path->port || path->port > ibdev->num_ports) 5175 return; 5176 5177 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 5178 5179 rdma_ah_set_port_num(ah_attr, path->port); 5180 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 5181 5182 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 5183 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 5184 rdma_ah_set_static_rate(ah_attr, 5185 path->static_rate ? path->static_rate - 5 : 0); 5186 if (path->grh_mlid & (1 << 7)) { 5187 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 5188 5189 rdma_ah_set_grh(ah_attr, NULL, 5190 tc_fl & 0xfffff, 5191 path->mgid_index, 5192 path->hop_limit, 5193 (tc_fl >> 20) & 0xff); 5194 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 5195 } 5196 } 5197 5198 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 5199 struct mlx5_ib_sq *sq, 5200 u8 *sq_state) 5201 { 5202 int err; 5203 5204 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 5205 if (err) 5206 goto out; 5207 sq->state = *sq_state; 5208 5209 out: 5210 return err; 5211 } 5212 5213 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 5214 struct mlx5_ib_rq *rq, 5215 u8 *rq_state) 5216 { 5217 void *out; 5218 void *rqc; 5219 int inlen; 5220 int err; 5221 5222 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 5223 out = kvzalloc(inlen, GFP_KERNEL); 5224 if (!out) 5225 return -ENOMEM; 5226 5227 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 5228 if (err) 5229 goto out; 5230 5231 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 5232 *rq_state = MLX5_GET(rqc, rqc, state); 5233 rq->state = *rq_state; 5234 5235 out: 5236 kvfree(out); 5237 return err; 5238 } 5239 5240 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 5241 struct mlx5_ib_qp *qp, u8 *qp_state) 5242 { 5243 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 5244 [MLX5_RQC_STATE_RST] = { 5245 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5246 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5247 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 5248 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 5249 }, 5250 [MLX5_RQC_STATE_RDY] = { 5251 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5252 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5253 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 5254 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 5255 }, 5256 [MLX5_RQC_STATE_ERR] = { 5257 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 5258 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 5259 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 5260 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 5261 }, 5262 [MLX5_RQ_STATE_NA] = { 5263 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 5264 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 5265 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 5266 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 5267 }, 5268 }; 5269 5270 *qp_state = sqrq_trans[rq_state][sq_state]; 5271 5272 if (*qp_state == MLX5_QP_STATE_BAD) { 5273 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 5274 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 5275 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 5276 return -EINVAL; 5277 } 5278 5279 if (*qp_state == MLX5_QP_STATE) 5280 *qp_state = qp->state; 5281 5282 return 0; 5283 } 5284 5285 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 5286 struct mlx5_ib_qp *qp, 5287 u8 *raw_packet_qp_state) 5288 { 5289 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 5290 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 5291 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 5292 int err; 5293 u8 sq_state = MLX5_SQ_STATE_NA; 5294 u8 rq_state = MLX5_RQ_STATE_NA; 5295 5296 if (qp->sq.wqe_cnt) { 5297 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 5298 if (err) 5299 return err; 5300 } 5301 5302 if (qp->rq.wqe_cnt) { 5303 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 5304 if (err) 5305 return err; 5306 } 5307 5308 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 5309 raw_packet_qp_state); 5310 } 5311 5312 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 5313 struct ib_qp_attr *qp_attr) 5314 { 5315 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 5316 struct mlx5_qp_context *context; 5317 int mlx5_state; 5318 u32 *outb; 5319 int err = 0; 5320 5321 outb = kzalloc(outlen, GFP_KERNEL); 5322 if (!outb) 5323 return -ENOMEM; 5324 5325 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 5326 outlen); 5327 if (err) 5328 goto out; 5329 5330 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 5331 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 5332 5333 mlx5_state = be32_to_cpu(context->flags) >> 28; 5334 5335 qp->state = to_ib_qp_state(mlx5_state); 5336 qp_attr->path_mtu = context->mtu_msgmax >> 5; 5337 qp_attr->path_mig_state = 5338 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 5339 qp_attr->qkey = be32_to_cpu(context->qkey); 5340 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 5341 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 5342 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 5343 qp_attr->qp_access_flags = 5344 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 5345 5346 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 5347 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 5348 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 5349 qp_attr->alt_pkey_index = 5350 be16_to_cpu(context->alt_path.pkey_index); 5351 qp_attr->alt_port_num = 5352 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 5353 } 5354 5355 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 5356 qp_attr->port_num = context->pri_path.port; 5357 5358 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 5359 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 5360 5361 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 5362 5363 qp_attr->max_dest_rd_atomic = 5364 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 5365 qp_attr->min_rnr_timer = 5366 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 5367 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 5368 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 5369 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 5370 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 5371 5372 out: 5373 kfree(outb); 5374 return err; 5375 } 5376 5377 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5378 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5379 struct ib_qp_init_attr *qp_init_attr) 5380 { 5381 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5382 u32 *out; 5383 u32 access_flags = 0; 5384 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5385 void *dctc; 5386 int err; 5387 int supported_mask = IB_QP_STATE | 5388 IB_QP_ACCESS_FLAGS | 5389 IB_QP_PORT | 5390 IB_QP_MIN_RNR_TIMER | 5391 IB_QP_AV | 5392 IB_QP_PATH_MTU | 5393 IB_QP_PKEY_INDEX; 5394 5395 if (qp_attr_mask & ~supported_mask) 5396 return -EINVAL; 5397 if (mqp->state != IB_QPS_RTR) 5398 return -EINVAL; 5399 5400 out = kzalloc(outlen, GFP_KERNEL); 5401 if (!out) 5402 return -ENOMEM; 5403 5404 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 5405 if (err) 5406 goto out; 5407 5408 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5409 5410 if (qp_attr_mask & IB_QP_STATE) 5411 qp_attr->qp_state = IB_QPS_RTR; 5412 5413 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5414 if (MLX5_GET(dctc, dctc, rre)) 5415 access_flags |= IB_ACCESS_REMOTE_READ; 5416 if (MLX5_GET(dctc, dctc, rwe)) 5417 access_flags |= IB_ACCESS_REMOTE_WRITE; 5418 if (MLX5_GET(dctc, dctc, rae)) 5419 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5420 qp_attr->qp_access_flags = access_flags; 5421 } 5422 5423 if (qp_attr_mask & IB_QP_PORT) 5424 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5425 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5426 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5427 if (qp_attr_mask & IB_QP_AV) { 5428 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5429 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5430 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5431 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5432 } 5433 if (qp_attr_mask & IB_QP_PATH_MTU) 5434 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5435 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5436 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5437 out: 5438 kfree(out); 5439 return err; 5440 } 5441 5442 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5443 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5444 { 5445 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5446 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5447 int err = 0; 5448 u8 raw_packet_qp_state; 5449 5450 if (ibqp->rwq_ind_tbl) 5451 return -ENOSYS; 5452 5453 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 5454 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5455 qp_init_attr); 5456 5457 /* Not all of output fields are applicable, make sure to zero them */ 5458 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5459 memset(qp_attr, 0, sizeof(*qp_attr)); 5460 5461 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5462 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5463 qp_attr_mask, qp_init_attr); 5464 5465 mutex_lock(&qp->mutex); 5466 5467 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5468 qp->flags & MLX5_IB_QP_UNDERLAY) { 5469 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5470 if (err) 5471 goto out; 5472 qp->state = raw_packet_qp_state; 5473 qp_attr->port_num = 1; 5474 } else { 5475 err = query_qp_attr(dev, qp, qp_attr); 5476 if (err) 5477 goto out; 5478 } 5479 5480 qp_attr->qp_state = qp->state; 5481 qp_attr->cur_qp_state = qp_attr->qp_state; 5482 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5483 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5484 5485 if (!ibqp->uobject) { 5486 qp_attr->cap.max_send_wr = qp->sq.max_post; 5487 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5488 qp_init_attr->qp_context = ibqp->qp_context; 5489 } else { 5490 qp_attr->cap.max_send_wr = 0; 5491 qp_attr->cap.max_send_sge = 0; 5492 } 5493 5494 qp_init_attr->qp_type = ibqp->qp_type; 5495 qp_init_attr->recv_cq = ibqp->recv_cq; 5496 qp_init_attr->send_cq = ibqp->send_cq; 5497 qp_init_attr->srq = ibqp->srq; 5498 qp_attr->cap.max_inline_data = qp->max_inline_data; 5499 5500 qp_init_attr->cap = qp_attr->cap; 5501 5502 qp_init_attr->create_flags = 0; 5503 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5504 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5505 5506 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5507 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5508 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5509 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5510 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5511 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5512 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5513 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5514 5515 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5516 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5517 5518 out: 5519 mutex_unlock(&qp->mutex); 5520 return err; 5521 } 5522 5523 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5524 struct ib_ucontext *context, 5525 struct ib_udata *udata) 5526 { 5527 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5528 struct mlx5_ib_xrcd *xrcd; 5529 int err; 5530 5531 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5532 return ERR_PTR(-ENOSYS); 5533 5534 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5535 if (!xrcd) 5536 return ERR_PTR(-ENOMEM); 5537 5538 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5539 if (err) { 5540 kfree(xrcd); 5541 return ERR_PTR(-ENOMEM); 5542 } 5543 5544 return &xrcd->ibxrcd; 5545 } 5546 5547 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5548 { 5549 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5550 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5551 int err; 5552 5553 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5554 if (err) 5555 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5556 5557 kfree(xrcd); 5558 return 0; 5559 } 5560 5561 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5562 { 5563 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5564 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5565 struct ib_event event; 5566 5567 if (rwq->ibwq.event_handler) { 5568 event.device = rwq->ibwq.device; 5569 event.element.wq = &rwq->ibwq; 5570 switch (type) { 5571 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5572 event.event = IB_EVENT_WQ_FATAL; 5573 break; 5574 default: 5575 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5576 return; 5577 } 5578 5579 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5580 } 5581 } 5582 5583 static int set_delay_drop(struct mlx5_ib_dev *dev) 5584 { 5585 int err = 0; 5586 5587 mutex_lock(&dev->delay_drop.lock); 5588 if (dev->delay_drop.activate) 5589 goto out; 5590 5591 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5592 if (err) 5593 goto out; 5594 5595 dev->delay_drop.activate = true; 5596 out: 5597 mutex_unlock(&dev->delay_drop.lock); 5598 5599 if (!err) 5600 atomic_inc(&dev->delay_drop.rqs_cnt); 5601 return err; 5602 } 5603 5604 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5605 struct ib_wq_init_attr *init_attr) 5606 { 5607 struct mlx5_ib_dev *dev; 5608 int has_net_offloads; 5609 __be64 *rq_pas0; 5610 void *in; 5611 void *rqc; 5612 void *wq; 5613 int inlen; 5614 int err; 5615 5616 dev = to_mdev(pd->device); 5617 5618 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5619 in = kvzalloc(inlen, GFP_KERNEL); 5620 if (!in) 5621 return -ENOMEM; 5622 5623 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5624 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5625 MLX5_SET(rqc, rqc, mem_rq_type, 5626 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5627 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5628 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5629 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5630 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5631 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5632 MLX5_SET(wq, wq, wq_type, 5633 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5634 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5635 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5636 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5637 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5638 err = -EOPNOTSUPP; 5639 goto out; 5640 } else { 5641 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5642 } 5643 } 5644 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5645 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5646 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5647 MLX5_SET(wq, wq, log_wqe_stride_size, 5648 rwq->single_stride_log_num_of_bytes - 5649 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5650 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5651 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5652 } 5653 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5654 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5655 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5656 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5657 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5658 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5659 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5660 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5661 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5662 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5663 err = -EOPNOTSUPP; 5664 goto out; 5665 } 5666 } else { 5667 MLX5_SET(rqc, rqc, vsd, 1); 5668 } 5669 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5670 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5671 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5672 err = -EOPNOTSUPP; 5673 goto out; 5674 } 5675 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5676 } 5677 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5678 if (!(dev->ib_dev.attrs.raw_packet_caps & 5679 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5680 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5681 err = -EOPNOTSUPP; 5682 goto out; 5683 } 5684 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5685 } 5686 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5687 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5688 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5689 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5690 err = set_delay_drop(dev); 5691 if (err) { 5692 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5693 err); 5694 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5695 } else { 5696 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5697 } 5698 } 5699 out: 5700 kvfree(in); 5701 return err; 5702 } 5703 5704 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5705 struct ib_wq_init_attr *wq_init_attr, 5706 struct mlx5_ib_create_wq *ucmd, 5707 struct mlx5_ib_rwq *rwq) 5708 { 5709 /* Sanity check RQ size before proceeding */ 5710 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5711 return -EINVAL; 5712 5713 if (!ucmd->rq_wqe_count) 5714 return -EINVAL; 5715 5716 rwq->wqe_count = ucmd->rq_wqe_count; 5717 rwq->wqe_shift = ucmd->rq_wqe_shift; 5718 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5719 return -EINVAL; 5720 5721 rwq->log_rq_stride = rwq->wqe_shift; 5722 rwq->log_rq_size = ilog2(rwq->wqe_count); 5723 return 0; 5724 } 5725 5726 static int prepare_user_rq(struct ib_pd *pd, 5727 struct ib_wq_init_attr *init_attr, 5728 struct ib_udata *udata, 5729 struct mlx5_ib_rwq *rwq) 5730 { 5731 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5732 struct mlx5_ib_create_wq ucmd = {}; 5733 int err; 5734 size_t required_cmd_sz; 5735 5736 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5737 + sizeof(ucmd.single_stride_log_num_of_bytes); 5738 if (udata->inlen < required_cmd_sz) { 5739 mlx5_ib_dbg(dev, "invalid inlen\n"); 5740 return -EINVAL; 5741 } 5742 5743 if (udata->inlen > sizeof(ucmd) && 5744 !ib_is_udata_cleared(udata, sizeof(ucmd), 5745 udata->inlen - sizeof(ucmd))) { 5746 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5747 return -EOPNOTSUPP; 5748 } 5749 5750 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5751 mlx5_ib_dbg(dev, "copy failed\n"); 5752 return -EFAULT; 5753 } 5754 5755 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5756 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5757 return -EOPNOTSUPP; 5758 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5759 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5760 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5761 return -EOPNOTSUPP; 5762 } 5763 if ((ucmd.single_stride_log_num_of_bytes < 5764 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5765 (ucmd.single_stride_log_num_of_bytes > 5766 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5767 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5768 ucmd.single_stride_log_num_of_bytes, 5769 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5770 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5771 return -EINVAL; 5772 } 5773 if ((ucmd.single_wqe_log_num_of_strides > 5774 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5775 (ucmd.single_wqe_log_num_of_strides < 5776 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5777 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5778 ucmd.single_wqe_log_num_of_strides, 5779 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5780 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5781 return -EINVAL; 5782 } 5783 rwq->single_stride_log_num_of_bytes = 5784 ucmd.single_stride_log_num_of_bytes; 5785 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5786 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5787 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5788 } 5789 5790 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5791 if (err) { 5792 mlx5_ib_dbg(dev, "err %d\n", err); 5793 return err; 5794 } 5795 5796 err = create_user_rq(dev, pd, rwq, &ucmd); 5797 if (err) { 5798 mlx5_ib_dbg(dev, "err %d\n", err); 5799 return err; 5800 } 5801 5802 rwq->user_index = ucmd.user_index; 5803 return 0; 5804 } 5805 5806 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5807 struct ib_wq_init_attr *init_attr, 5808 struct ib_udata *udata) 5809 { 5810 struct mlx5_ib_dev *dev; 5811 struct mlx5_ib_rwq *rwq; 5812 struct mlx5_ib_create_wq_resp resp = {}; 5813 size_t min_resp_len; 5814 int err; 5815 5816 if (!udata) 5817 return ERR_PTR(-ENOSYS); 5818 5819 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5820 if (udata->outlen && udata->outlen < min_resp_len) 5821 return ERR_PTR(-EINVAL); 5822 5823 dev = to_mdev(pd->device); 5824 switch (init_attr->wq_type) { 5825 case IB_WQT_RQ: 5826 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5827 if (!rwq) 5828 return ERR_PTR(-ENOMEM); 5829 err = prepare_user_rq(pd, init_attr, udata, rwq); 5830 if (err) 5831 goto err; 5832 err = create_rq(rwq, pd, init_attr); 5833 if (err) 5834 goto err_user_rq; 5835 break; 5836 default: 5837 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5838 init_attr->wq_type); 5839 return ERR_PTR(-EINVAL); 5840 } 5841 5842 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5843 rwq->ibwq.state = IB_WQS_RESET; 5844 if (udata->outlen) { 5845 resp.response_length = offsetof(typeof(resp), response_length) + 5846 sizeof(resp.response_length); 5847 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5848 if (err) 5849 goto err_copy; 5850 } 5851 5852 rwq->core_qp.event = mlx5_ib_wq_event; 5853 rwq->ibwq.event_handler = init_attr->event_handler; 5854 return &rwq->ibwq; 5855 5856 err_copy: 5857 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5858 err_user_rq: 5859 destroy_user_rq(dev, pd, rwq); 5860 err: 5861 kfree(rwq); 5862 return ERR_PTR(err); 5863 } 5864 5865 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5866 { 5867 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5868 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5869 5870 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5871 destroy_user_rq(dev, wq->pd, rwq); 5872 kfree(rwq); 5873 5874 return 0; 5875 } 5876 5877 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5878 struct ib_rwq_ind_table_init_attr *init_attr, 5879 struct ib_udata *udata) 5880 { 5881 struct mlx5_ib_dev *dev = to_mdev(device); 5882 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5883 int sz = 1 << init_attr->log_ind_tbl_size; 5884 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5885 size_t min_resp_len; 5886 int inlen; 5887 int err; 5888 int i; 5889 u32 *in; 5890 void *rqtc; 5891 5892 if (udata->inlen > 0 && 5893 !ib_is_udata_cleared(udata, 0, 5894 udata->inlen)) 5895 return ERR_PTR(-EOPNOTSUPP); 5896 5897 if (init_attr->log_ind_tbl_size > 5898 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5899 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5900 init_attr->log_ind_tbl_size, 5901 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5902 return ERR_PTR(-EINVAL); 5903 } 5904 5905 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5906 if (udata->outlen && udata->outlen < min_resp_len) 5907 return ERR_PTR(-EINVAL); 5908 5909 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5910 if (!rwq_ind_tbl) 5911 return ERR_PTR(-ENOMEM); 5912 5913 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5914 in = kvzalloc(inlen, GFP_KERNEL); 5915 if (!in) { 5916 err = -ENOMEM; 5917 goto err; 5918 } 5919 5920 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5921 5922 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5923 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5924 5925 for (i = 0; i < sz; i++) 5926 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5927 5928 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5929 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5930 5931 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5932 kvfree(in); 5933 5934 if (err) 5935 goto err; 5936 5937 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5938 if (udata->outlen) { 5939 resp.response_length = offsetof(typeof(resp), response_length) + 5940 sizeof(resp.response_length); 5941 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5942 if (err) 5943 goto err_copy; 5944 } 5945 5946 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5947 5948 err_copy: 5949 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5950 err: 5951 kfree(rwq_ind_tbl); 5952 return ERR_PTR(err); 5953 } 5954 5955 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5956 { 5957 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5958 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5959 5960 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5961 5962 kfree(rwq_ind_tbl); 5963 return 0; 5964 } 5965 5966 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5967 u32 wq_attr_mask, struct ib_udata *udata) 5968 { 5969 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5970 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5971 struct mlx5_ib_modify_wq ucmd = {}; 5972 size_t required_cmd_sz; 5973 int curr_wq_state; 5974 int wq_state; 5975 int inlen; 5976 int err; 5977 void *rqc; 5978 void *in; 5979 5980 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5981 if (udata->inlen < required_cmd_sz) 5982 return -EINVAL; 5983 5984 if (udata->inlen > sizeof(ucmd) && 5985 !ib_is_udata_cleared(udata, sizeof(ucmd), 5986 udata->inlen - sizeof(ucmd))) 5987 return -EOPNOTSUPP; 5988 5989 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5990 return -EFAULT; 5991 5992 if (ucmd.comp_mask || ucmd.reserved) 5993 return -EOPNOTSUPP; 5994 5995 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5996 in = kvzalloc(inlen, GFP_KERNEL); 5997 if (!in) 5998 return -ENOMEM; 5999 6000 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 6001 6002 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 6003 wq_attr->curr_wq_state : wq->state; 6004 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 6005 wq_attr->wq_state : curr_wq_state; 6006 if (curr_wq_state == IB_WQS_ERR) 6007 curr_wq_state = MLX5_RQC_STATE_ERR; 6008 if (wq_state == IB_WQS_ERR) 6009 wq_state = MLX5_RQC_STATE_ERR; 6010 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 6011 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 6012 MLX5_SET(rqc, rqc, state, wq_state); 6013 6014 if (wq_attr_mask & IB_WQ_FLAGS) { 6015 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 6016 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 6017 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 6018 mlx5_ib_dbg(dev, "VLAN offloads are not " 6019 "supported\n"); 6020 err = -EOPNOTSUPP; 6021 goto out; 6022 } 6023 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6024 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 6025 MLX5_SET(rqc, rqc, vsd, 6026 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 6027 } 6028 6029 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 6030 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 6031 err = -EOPNOTSUPP; 6032 goto out; 6033 } 6034 } 6035 6036 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 6037 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 6038 MLX5_SET64(modify_rq_in, in, modify_bitmask, 6039 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 6040 MLX5_SET(rqc, rqc, counter_set_id, 6041 dev->port->cnts.set_id); 6042 } else 6043 dev_info_once( 6044 &dev->ib_dev.dev, 6045 "Receive WQ counters are not supported on current FW\n"); 6046 } 6047 6048 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 6049 if (!err) 6050 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 6051 6052 out: 6053 kvfree(in); 6054 return err; 6055 } 6056 6057 struct mlx5_ib_drain_cqe { 6058 struct ib_cqe cqe; 6059 struct completion done; 6060 }; 6061 6062 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 6063 { 6064 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 6065 struct mlx5_ib_drain_cqe, 6066 cqe); 6067 6068 complete(&cqe->done); 6069 } 6070 6071 /* This function returns only once the drained WR was completed */ 6072 static void handle_drain_completion(struct ib_cq *cq, 6073 struct mlx5_ib_drain_cqe *sdrain, 6074 struct mlx5_ib_dev *dev) 6075 { 6076 struct mlx5_core_dev *mdev = dev->mdev; 6077 6078 if (cq->poll_ctx == IB_POLL_DIRECT) { 6079 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 6080 ib_process_cq_direct(cq, -1); 6081 return; 6082 } 6083 6084 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6085 struct mlx5_ib_cq *mcq = to_mcq(cq); 6086 bool triggered = false; 6087 unsigned long flags; 6088 6089 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 6090 /* Make sure that the CQ handler won't run if wasn't run yet */ 6091 if (!mcq->mcq.reset_notify_added) 6092 mcq->mcq.reset_notify_added = 1; 6093 else 6094 triggered = true; 6095 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 6096 6097 if (triggered) { 6098 /* Wait for any scheduled/running task to be ended */ 6099 switch (cq->poll_ctx) { 6100 case IB_POLL_SOFTIRQ: 6101 irq_poll_disable(&cq->iop); 6102 irq_poll_enable(&cq->iop); 6103 break; 6104 case IB_POLL_WORKQUEUE: 6105 cancel_work_sync(&cq->work); 6106 break; 6107 default: 6108 WARN_ON_ONCE(1); 6109 } 6110 } 6111 6112 /* Run the CQ handler - this makes sure that the drain WR will 6113 * be processed if wasn't processed yet. 6114 */ 6115 mcq->mcq.comp(&mcq->mcq); 6116 } 6117 6118 wait_for_completion(&sdrain->done); 6119 } 6120 6121 void mlx5_ib_drain_sq(struct ib_qp *qp) 6122 { 6123 struct ib_cq *cq = qp->send_cq; 6124 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6125 struct mlx5_ib_drain_cqe sdrain; 6126 const struct ib_send_wr *bad_swr; 6127 struct ib_rdma_wr swr = { 6128 .wr = { 6129 .next = NULL, 6130 { .wr_cqe = &sdrain.cqe, }, 6131 .opcode = IB_WR_RDMA_WRITE, 6132 }, 6133 }; 6134 int ret; 6135 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6136 struct mlx5_core_dev *mdev = dev->mdev; 6137 6138 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6139 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6140 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6141 return; 6142 } 6143 6144 sdrain.cqe.done = mlx5_ib_drain_qp_done; 6145 init_completion(&sdrain.done); 6146 6147 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); 6148 if (ret) { 6149 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 6150 return; 6151 } 6152 6153 handle_drain_completion(cq, &sdrain, dev); 6154 } 6155 6156 void mlx5_ib_drain_rq(struct ib_qp *qp) 6157 { 6158 struct ib_cq *cq = qp->recv_cq; 6159 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 6160 struct mlx5_ib_drain_cqe rdrain; 6161 struct ib_recv_wr rwr = {}; 6162 const struct ib_recv_wr *bad_rwr; 6163 int ret; 6164 struct mlx5_ib_dev *dev = to_mdev(qp->device); 6165 struct mlx5_core_dev *mdev = dev->mdev; 6166 6167 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 6168 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 6169 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6170 return; 6171 } 6172 6173 rwr.wr_cqe = &rdrain.cqe; 6174 rdrain.cqe.done = mlx5_ib_drain_qp_done; 6175 init_completion(&rdrain.done); 6176 6177 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); 6178 if (ret) { 6179 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 6180 return; 6181 } 6182 6183 handle_drain_completion(cq, &rdrain, dev); 6184 } 6185