1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <rdma/ib_umem.h> 34 #include <rdma/ib_umem_odp.h> 35 #include <linux/kernel.h> 36 #include <linux/dma-buf.h> 37 #include <linux/dma-resv.h> 38 39 #include "mlx5_ib.h" 40 #include "cmd.h" 41 #include "qp.h" 42 43 #include <linux/mlx5/eq.h> 44 45 /* Contains the details of a pagefault. */ 46 struct mlx5_pagefault { 47 u32 bytes_committed; 48 u32 token; 49 u8 event_subtype; 50 u8 type; 51 union { 52 /* Initiator or send message responder pagefault details. */ 53 struct { 54 /* Received packet size, only valid for responders. */ 55 u32 packet_size; 56 /* 57 * Number of resource holding WQE, depends on type. 58 */ 59 u32 wq_num; 60 /* 61 * WQE index. Refers to either the send queue or 62 * receive queue, according to event_subtype. 63 */ 64 u16 wqe_index; 65 } wqe; 66 /* RDMA responder pagefault details */ 67 struct { 68 u32 r_key; 69 /* 70 * Received packet size, minimal size page fault 71 * resolution required for forward progress. 72 */ 73 u32 packet_size; 74 u32 rdma_op_len; 75 u64 rdma_va; 76 } rdma; 77 }; 78 79 struct mlx5_ib_pf_eq *eq; 80 struct work_struct work; 81 }; 82 83 #define MAX_PREFETCH_LEN (4*1024*1024U) 84 85 /* Timeout in ms to wait for an active mmu notifier to complete when handling 86 * a pagefault. */ 87 #define MMU_NOTIFIER_TIMEOUT 1000 88 89 #define MLX5_IMR_MTT_BITS (30 - PAGE_SHIFT) 90 #define MLX5_IMR_MTT_SHIFT (MLX5_IMR_MTT_BITS + PAGE_SHIFT) 91 #define MLX5_IMR_MTT_ENTRIES BIT_ULL(MLX5_IMR_MTT_BITS) 92 #define MLX5_IMR_MTT_SIZE BIT_ULL(MLX5_IMR_MTT_SHIFT) 93 #define MLX5_IMR_MTT_MASK (~(MLX5_IMR_MTT_SIZE - 1)) 94 95 #define MLX5_KSM_PAGE_SHIFT MLX5_IMR_MTT_SHIFT 96 97 static u64 mlx5_imr_ksm_entries; 98 99 static void populate_klm(struct mlx5_klm *pklm, size_t idx, size_t nentries, 100 struct mlx5_ib_mr *imr, int flags) 101 { 102 struct mlx5_klm *end = pklm + nentries; 103 104 if (flags & MLX5_IB_UPD_XLT_ZAP) { 105 for (; pklm != end; pklm++, idx++) { 106 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE); 107 pklm->key = cpu_to_be32(mr_to_mdev(imr)->null_mkey); 108 pklm->va = 0; 109 } 110 return; 111 } 112 113 /* 114 * The locking here is pretty subtle. Ideally the implicit_children 115 * xarray would be protected by the umem_mutex, however that is not 116 * possible. Instead this uses a weaker update-then-lock pattern: 117 * 118 * xa_store() 119 * mutex_lock(umem_mutex) 120 * mlx5_ib_update_xlt() 121 * mutex_unlock(umem_mutex) 122 * destroy lkey 123 * 124 * ie any change the xarray must be followed by the locked update_xlt 125 * before destroying. 126 * 127 * The umem_mutex provides the acquire/release semantic needed to make 128 * the xa_store() visible to a racing thread. 129 */ 130 lockdep_assert_held(&to_ib_umem_odp(imr->umem)->umem_mutex); 131 132 for (; pklm != end; pklm++, idx++) { 133 struct mlx5_ib_mr *mtt = xa_load(&imr->implicit_children, idx); 134 135 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE); 136 if (mtt) { 137 pklm->key = cpu_to_be32(mtt->ibmr.lkey); 138 pklm->va = cpu_to_be64(idx * MLX5_IMR_MTT_SIZE); 139 } else { 140 pklm->key = cpu_to_be32(mr_to_mdev(imr)->null_mkey); 141 pklm->va = 0; 142 } 143 } 144 } 145 146 static u64 umem_dma_to_mtt(dma_addr_t umem_dma) 147 { 148 u64 mtt_entry = umem_dma & ODP_DMA_ADDR_MASK; 149 150 if (umem_dma & ODP_READ_ALLOWED_BIT) 151 mtt_entry |= MLX5_IB_MTT_READ; 152 if (umem_dma & ODP_WRITE_ALLOWED_BIT) 153 mtt_entry |= MLX5_IB_MTT_WRITE; 154 155 return mtt_entry; 156 } 157 158 static void populate_mtt(__be64 *pas, size_t idx, size_t nentries, 159 struct mlx5_ib_mr *mr, int flags) 160 { 161 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 162 dma_addr_t pa; 163 size_t i; 164 165 if (flags & MLX5_IB_UPD_XLT_ZAP) 166 return; 167 168 for (i = 0; i < nentries; i++) { 169 pa = odp->dma_list[idx + i]; 170 pas[i] = cpu_to_be64(umem_dma_to_mtt(pa)); 171 } 172 } 173 174 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 175 struct mlx5_ib_mr *mr, int flags) 176 { 177 if (flags & MLX5_IB_UPD_XLT_INDIRECT) { 178 populate_klm(xlt, idx, nentries, mr, flags); 179 } else { 180 populate_mtt(xlt, idx, nentries, mr, flags); 181 } 182 } 183 184 /* 185 * This must be called after the mr has been removed from implicit_children. 186 * NOTE: The MR does not necessarily have to be 187 * empty here, parallel page faults could have raced with the free process and 188 * added pages to it. 189 */ 190 static void free_implicit_child_mr_work(struct work_struct *work) 191 { 192 struct mlx5_ib_mr *mr = 193 container_of(work, struct mlx5_ib_mr, odp_destroy.work); 194 struct mlx5_ib_mr *imr = mr->parent; 195 struct ib_umem_odp *odp_imr = to_ib_umem_odp(imr->umem); 196 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 197 198 mlx5r_deref_wait_odp_mkey(&mr->mmkey); 199 200 mutex_lock(&odp_imr->umem_mutex); 201 mlx5_ib_update_xlt(mr->parent, ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT, 202 1, 0, 203 MLX5_IB_UPD_XLT_INDIRECT | MLX5_IB_UPD_XLT_ATOMIC); 204 mutex_unlock(&odp_imr->umem_mutex); 205 mlx5_ib_dereg_mr(&mr->ibmr, NULL); 206 207 mlx5r_deref_odp_mkey(&imr->mmkey); 208 } 209 210 static void destroy_unused_implicit_child_mr(struct mlx5_ib_mr *mr) 211 { 212 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 213 unsigned long idx = ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT; 214 struct mlx5_ib_mr *imr = mr->parent; 215 216 if (!refcount_inc_not_zero(&imr->mmkey.usecount)) 217 return; 218 219 xa_erase(&imr->implicit_children, idx); 220 221 /* Freeing a MR is a sleeping operation, so bounce to a work queue */ 222 INIT_WORK(&mr->odp_destroy.work, free_implicit_child_mr_work); 223 queue_work(system_unbound_wq, &mr->odp_destroy.work); 224 } 225 226 static bool mlx5_ib_invalidate_range(struct mmu_interval_notifier *mni, 227 const struct mmu_notifier_range *range, 228 unsigned long cur_seq) 229 { 230 struct ib_umem_odp *umem_odp = 231 container_of(mni, struct ib_umem_odp, notifier); 232 struct mlx5_ib_mr *mr; 233 const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT / 234 sizeof(struct mlx5_mtt)) - 1; 235 u64 idx = 0, blk_start_idx = 0; 236 u64 invalidations = 0; 237 unsigned long start; 238 unsigned long end; 239 int in_block = 0; 240 u64 addr; 241 242 if (!mmu_notifier_range_blockable(range)) 243 return false; 244 245 mutex_lock(&umem_odp->umem_mutex); 246 mmu_interval_set_seq(mni, cur_seq); 247 /* 248 * If npages is zero then umem_odp->private may not be setup yet. This 249 * does not complete until after the first page is mapped for DMA. 250 */ 251 if (!umem_odp->npages) 252 goto out; 253 mr = umem_odp->private; 254 255 start = max_t(u64, ib_umem_start(umem_odp), range->start); 256 end = min_t(u64, ib_umem_end(umem_odp), range->end); 257 258 /* 259 * Iteration one - zap the HW's MTTs. The notifiers_count ensures that 260 * while we are doing the invalidation, no page fault will attempt to 261 * overwrite the same MTTs. Concurent invalidations might race us, 262 * but they will write 0s as well, so no difference in the end result. 263 */ 264 for (addr = start; addr < end; addr += BIT(umem_odp->page_shift)) { 265 idx = (addr - ib_umem_start(umem_odp)) >> umem_odp->page_shift; 266 /* 267 * Strive to write the MTTs in chunks, but avoid overwriting 268 * non-existing MTTs. The huristic here can be improved to 269 * estimate the cost of another UMR vs. the cost of bigger 270 * UMR. 271 */ 272 if (umem_odp->dma_list[idx] & 273 (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) { 274 if (!in_block) { 275 blk_start_idx = idx; 276 in_block = 1; 277 } 278 279 /* Count page invalidations */ 280 invalidations += idx - blk_start_idx + 1; 281 } else { 282 u64 umr_offset = idx & umr_block_mask; 283 284 if (in_block && umr_offset == 0) { 285 mlx5_ib_update_xlt(mr, blk_start_idx, 286 idx - blk_start_idx, 0, 287 MLX5_IB_UPD_XLT_ZAP | 288 MLX5_IB_UPD_XLT_ATOMIC); 289 in_block = 0; 290 } 291 } 292 } 293 if (in_block) 294 mlx5_ib_update_xlt(mr, blk_start_idx, 295 idx - blk_start_idx + 1, 0, 296 MLX5_IB_UPD_XLT_ZAP | 297 MLX5_IB_UPD_XLT_ATOMIC); 298 299 mlx5_update_odp_stats(mr, invalidations, invalidations); 300 301 /* 302 * We are now sure that the device will not access the 303 * memory. We can safely unmap it, and mark it as dirty if 304 * needed. 305 */ 306 307 ib_umem_odp_unmap_dma_pages(umem_odp, start, end); 308 309 if (unlikely(!umem_odp->npages && mr->parent)) 310 destroy_unused_implicit_child_mr(mr); 311 out: 312 mutex_unlock(&umem_odp->umem_mutex); 313 return true; 314 } 315 316 const struct mmu_interval_notifier_ops mlx5_mn_ops = { 317 .invalidate = mlx5_ib_invalidate_range, 318 }; 319 320 static void internal_fill_odp_caps(struct mlx5_ib_dev *dev) 321 { 322 struct ib_odp_caps *caps = &dev->odp_caps; 323 324 memset(caps, 0, sizeof(*caps)); 325 326 if (!MLX5_CAP_GEN(dev->mdev, pg) || 327 !mlx5_ib_can_load_pas_with_umr(dev, 0)) 328 return; 329 330 caps->general_caps = IB_ODP_SUPPORT; 331 332 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) 333 dev->odp_max_size = U64_MAX; 334 else 335 dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT); 336 337 if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send)) 338 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND; 339 340 if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.srq_receive)) 341 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV; 342 343 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send)) 344 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND; 345 346 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive)) 347 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV; 348 349 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write)) 350 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE; 351 352 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read)) 353 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ; 354 355 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.atomic)) 356 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_ATOMIC; 357 358 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.srq_receive)) 359 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV; 360 361 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.send)) 362 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SEND; 363 364 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.receive)) 365 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_RECV; 366 367 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.write)) 368 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_WRITE; 369 370 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.read)) 371 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_READ; 372 373 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.atomic)) 374 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_ATOMIC; 375 376 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.srq_receive)) 377 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV; 378 379 if (MLX5_CAP_GEN(dev->mdev, fixed_buffer_size) && 380 MLX5_CAP_GEN(dev->mdev, null_mkey) && 381 MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && 382 !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled)) 383 caps->general_caps |= IB_ODP_SUPPORT_IMPLICIT; 384 } 385 386 static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev, 387 struct mlx5_pagefault *pfault, 388 int error) 389 { 390 int wq_num = pfault->event_subtype == MLX5_PFAULT_SUBTYPE_WQE ? 391 pfault->wqe.wq_num : pfault->token; 392 u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)] = {}; 393 int err; 394 395 MLX5_SET(page_fault_resume_in, in, opcode, MLX5_CMD_OP_PAGE_FAULT_RESUME); 396 MLX5_SET(page_fault_resume_in, in, page_fault_type, pfault->type); 397 MLX5_SET(page_fault_resume_in, in, token, pfault->token); 398 MLX5_SET(page_fault_resume_in, in, wq_number, wq_num); 399 MLX5_SET(page_fault_resume_in, in, error, !!error); 400 401 err = mlx5_cmd_exec_in(dev->mdev, page_fault_resume, in); 402 if (err) 403 mlx5_ib_err(dev, "Failed to resolve the page fault on WQ 0x%x err %d\n", 404 wq_num, err); 405 } 406 407 static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr, 408 unsigned long idx) 409 { 410 struct ib_umem_odp *odp; 411 struct mlx5_ib_mr *mr; 412 struct mlx5_ib_mr *ret; 413 int err; 414 415 odp = ib_umem_odp_alloc_child(to_ib_umem_odp(imr->umem), 416 idx * MLX5_IMR_MTT_SIZE, 417 MLX5_IMR_MTT_SIZE, &mlx5_mn_ops); 418 if (IS_ERR(odp)) 419 return ERR_CAST(odp); 420 421 ret = mr = mlx5_mr_cache_alloc( 422 mr_to_mdev(imr), MLX5_IMR_MTT_CACHE_ENTRY, imr->access_flags); 423 if (IS_ERR(mr)) { 424 ib_umem_odp_release(odp); 425 return mr; 426 } 427 428 mr->ibmr.pd = imr->ibmr.pd; 429 mr->ibmr.device = &mr_to_mdev(imr)->ib_dev; 430 mr->umem = &odp->umem; 431 mr->ibmr.lkey = mr->mmkey.key; 432 mr->ibmr.rkey = mr->mmkey.key; 433 mr->mmkey.iova = idx * MLX5_IMR_MTT_SIZE; 434 mr->parent = imr; 435 odp->private = mr; 436 437 /* 438 * First refcount is owned by the xarray and second refconut 439 * is returned to the caller. 440 */ 441 refcount_set(&mr->mmkey.usecount, 2); 442 443 err = mlx5_ib_update_xlt(mr, 0, 444 MLX5_IMR_MTT_ENTRIES, 445 PAGE_SHIFT, 446 MLX5_IB_UPD_XLT_ZAP | 447 MLX5_IB_UPD_XLT_ENABLE); 448 if (err) { 449 ret = ERR_PTR(err); 450 goto out_mr; 451 } 452 453 xa_lock(&imr->implicit_children); 454 ret = __xa_cmpxchg(&imr->implicit_children, idx, NULL, mr, 455 GFP_KERNEL); 456 if (unlikely(ret)) { 457 if (xa_is_err(ret)) { 458 ret = ERR_PTR(xa_err(ret)); 459 goto out_lock; 460 } 461 /* 462 * Another thread beat us to creating the child mr, use 463 * theirs. 464 */ 465 refcount_inc(&ret->mmkey.usecount); 466 goto out_lock; 467 } 468 xa_unlock(&imr->implicit_children); 469 470 mlx5_ib_dbg(mr_to_mdev(imr), "key %x mr %p\n", mr->mmkey.key, mr); 471 return mr; 472 473 out_lock: 474 xa_unlock(&imr->implicit_children); 475 out_mr: 476 mlx5_ib_dereg_mr(&mr->ibmr, NULL); 477 return ret; 478 } 479 480 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 481 struct ib_udata *udata, 482 int access_flags) 483 { 484 struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device); 485 struct ib_umem_odp *umem_odp; 486 struct mlx5_ib_mr *imr; 487 int err; 488 489 if (!mlx5_ib_can_load_pas_with_umr(dev, 490 MLX5_IMR_MTT_ENTRIES * PAGE_SIZE)) 491 return ERR_PTR(-EOPNOTSUPP); 492 493 umem_odp = ib_umem_odp_alloc_implicit(&dev->ib_dev, access_flags); 494 if (IS_ERR(umem_odp)) 495 return ERR_CAST(umem_odp); 496 497 imr = mlx5_mr_cache_alloc(dev, MLX5_IMR_KSM_CACHE_ENTRY, access_flags); 498 if (IS_ERR(imr)) { 499 ib_umem_odp_release(umem_odp); 500 return imr; 501 } 502 503 imr->ibmr.pd = &pd->ibpd; 504 imr->mmkey.iova = 0; 505 imr->umem = &umem_odp->umem; 506 imr->ibmr.lkey = imr->mmkey.key; 507 imr->ibmr.rkey = imr->mmkey.key; 508 imr->ibmr.device = &dev->ib_dev; 509 imr->umem = &umem_odp->umem; 510 imr->is_odp_implicit = true; 511 xa_init(&imr->implicit_children); 512 513 err = mlx5_ib_update_xlt(imr, 0, 514 mlx5_imr_ksm_entries, 515 MLX5_KSM_PAGE_SHIFT, 516 MLX5_IB_UPD_XLT_INDIRECT | 517 MLX5_IB_UPD_XLT_ZAP | 518 MLX5_IB_UPD_XLT_ENABLE); 519 if (err) 520 goto out_mr; 521 522 err = mlx5r_store_odp_mkey(dev, &imr->mmkey); 523 if (err) 524 goto out_mr; 525 526 mlx5_ib_dbg(dev, "key %x mr %p\n", imr->mmkey.key, imr); 527 return imr; 528 out_mr: 529 mlx5_ib_err(dev, "Failed to register MKEY %d\n", err); 530 mlx5_ib_dereg_mr(&imr->ibmr, NULL); 531 return ERR_PTR(err); 532 } 533 534 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr) 535 { 536 struct mlx5_ib_mr *mtt; 537 unsigned long idx; 538 539 /* 540 * If this is an implicit MR it is already invalidated so we can just 541 * delete the children mkeys. 542 */ 543 xa_for_each(&mr->implicit_children, idx, mtt) { 544 xa_erase(&mr->implicit_children, idx); 545 mlx5_ib_dereg_mr(&mtt->ibmr, NULL); 546 } 547 } 548 549 #define MLX5_PF_FLAGS_DOWNGRADE BIT(1) 550 #define MLX5_PF_FLAGS_SNAPSHOT BIT(2) 551 #define MLX5_PF_FLAGS_ENABLE BIT(3) 552 static int pagefault_real_mr(struct mlx5_ib_mr *mr, struct ib_umem_odp *odp, 553 u64 user_va, size_t bcnt, u32 *bytes_mapped, 554 u32 flags) 555 { 556 int page_shift, ret, np; 557 bool downgrade = flags & MLX5_PF_FLAGS_DOWNGRADE; 558 u64 access_mask; 559 u64 start_idx; 560 bool fault = !(flags & MLX5_PF_FLAGS_SNAPSHOT); 561 u32 xlt_flags = MLX5_IB_UPD_XLT_ATOMIC; 562 563 if (flags & MLX5_PF_FLAGS_ENABLE) 564 xlt_flags |= MLX5_IB_UPD_XLT_ENABLE; 565 566 page_shift = odp->page_shift; 567 start_idx = (user_va - ib_umem_start(odp)) >> page_shift; 568 access_mask = ODP_READ_ALLOWED_BIT; 569 570 if (odp->umem.writable && !downgrade) 571 access_mask |= ODP_WRITE_ALLOWED_BIT; 572 573 np = ib_umem_odp_map_dma_and_lock(odp, user_va, bcnt, access_mask, fault); 574 if (np < 0) 575 return np; 576 577 /* 578 * No need to check whether the MTTs really belong to this MR, since 579 * ib_umem_odp_map_dma_and_lock already checks this. 580 */ 581 ret = mlx5_ib_update_xlt(mr, start_idx, np, page_shift, xlt_flags); 582 mutex_unlock(&odp->umem_mutex); 583 584 if (ret < 0) { 585 if (ret != -EAGAIN) 586 mlx5_ib_err(mr_to_mdev(mr), 587 "Failed to update mkey page tables\n"); 588 goto out; 589 } 590 591 if (bytes_mapped) { 592 u32 new_mappings = (np << page_shift) - 593 (user_va - round_down(user_va, 1 << page_shift)); 594 595 *bytes_mapped += min_t(u32, new_mappings, bcnt); 596 } 597 598 return np << (page_shift - PAGE_SHIFT); 599 600 out: 601 return ret; 602 } 603 604 static int pagefault_implicit_mr(struct mlx5_ib_mr *imr, 605 struct ib_umem_odp *odp_imr, u64 user_va, 606 size_t bcnt, u32 *bytes_mapped, u32 flags) 607 { 608 unsigned long end_idx = (user_va + bcnt - 1) >> MLX5_IMR_MTT_SHIFT; 609 unsigned long upd_start_idx = end_idx + 1; 610 unsigned long upd_len = 0; 611 unsigned long npages = 0; 612 int err; 613 int ret; 614 615 if (unlikely(user_va >= mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE || 616 mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE - user_va < bcnt)) 617 return -EFAULT; 618 619 /* Fault each child mr that intersects with our interval. */ 620 while (bcnt) { 621 unsigned long idx = user_va >> MLX5_IMR_MTT_SHIFT; 622 struct ib_umem_odp *umem_odp; 623 struct mlx5_ib_mr *mtt; 624 u64 len; 625 626 xa_lock(&imr->implicit_children); 627 mtt = xa_load(&imr->implicit_children, idx); 628 if (unlikely(!mtt)) { 629 xa_unlock(&imr->implicit_children); 630 mtt = implicit_get_child_mr(imr, idx); 631 if (IS_ERR(mtt)) { 632 ret = PTR_ERR(mtt); 633 goto out; 634 } 635 upd_start_idx = min(upd_start_idx, idx); 636 upd_len = idx - upd_start_idx + 1; 637 } else { 638 refcount_inc(&mtt->mmkey.usecount); 639 xa_unlock(&imr->implicit_children); 640 } 641 642 umem_odp = to_ib_umem_odp(mtt->umem); 643 len = min_t(u64, user_va + bcnt, ib_umem_end(umem_odp)) - 644 user_va; 645 646 ret = pagefault_real_mr(mtt, umem_odp, user_va, len, 647 bytes_mapped, flags); 648 649 mlx5r_deref_odp_mkey(&mtt->mmkey); 650 651 if (ret < 0) 652 goto out; 653 user_va += len; 654 bcnt -= len; 655 npages += ret; 656 } 657 658 ret = npages; 659 660 /* 661 * Any time the implicit_children are changed we must perform an 662 * update of the xlt before exiting to ensure the HW and the 663 * implicit_children remains synchronized. 664 */ 665 out: 666 if (likely(!upd_len)) 667 return ret; 668 669 /* 670 * Notice this is not strictly ordered right, the KSM is updated after 671 * the implicit_children is updated, so a parallel page fault could 672 * see a MR that is not yet visible in the KSM. This is similar to a 673 * parallel page fault seeing a MR that is being concurrently removed 674 * from the KSM. Both of these improbable situations are resolved 675 * safely by resuming the HW and then taking another page fault. The 676 * next pagefault handler will see the new information. 677 */ 678 mutex_lock(&odp_imr->umem_mutex); 679 err = mlx5_ib_update_xlt(imr, upd_start_idx, upd_len, 0, 680 MLX5_IB_UPD_XLT_INDIRECT | 681 MLX5_IB_UPD_XLT_ATOMIC); 682 mutex_unlock(&odp_imr->umem_mutex); 683 if (err) { 684 mlx5_ib_err(mr_to_mdev(imr), "Failed to update PAS\n"); 685 return err; 686 } 687 return ret; 688 } 689 690 static int pagefault_dmabuf_mr(struct mlx5_ib_mr *mr, size_t bcnt, 691 u32 *bytes_mapped, u32 flags) 692 { 693 struct ib_umem_dmabuf *umem_dmabuf = to_ib_umem_dmabuf(mr->umem); 694 u32 xlt_flags = 0; 695 int err; 696 unsigned int page_size; 697 698 if (flags & MLX5_PF_FLAGS_ENABLE) 699 xlt_flags |= MLX5_IB_UPD_XLT_ENABLE; 700 701 dma_resv_lock(umem_dmabuf->attach->dmabuf->resv, NULL); 702 err = ib_umem_dmabuf_map_pages(umem_dmabuf); 703 if (err) { 704 dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv); 705 return err; 706 } 707 708 page_size = mlx5_umem_find_best_pgsz(&umem_dmabuf->umem, mkc, 709 log_page_size, 0, 710 umem_dmabuf->umem.iova); 711 if (unlikely(page_size < PAGE_SIZE)) { 712 ib_umem_dmabuf_unmap_pages(umem_dmabuf); 713 err = -EINVAL; 714 } else { 715 err = mlx5_ib_update_mr_pas(mr, xlt_flags); 716 } 717 dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv); 718 719 if (err) 720 return err; 721 722 if (bytes_mapped) 723 *bytes_mapped += bcnt; 724 725 return ib_umem_num_pages(mr->umem); 726 } 727 728 /* 729 * Returns: 730 * -EFAULT: The io_virt->bcnt is not within the MR, it covers pages that are 731 * not accessible, or the MR is no longer valid. 732 * -EAGAIN/-ENOMEM: The operation should be retried 733 * 734 * -EINVAL/others: General internal malfunction 735 * >0: Number of pages mapped 736 */ 737 static int pagefault_mr(struct mlx5_ib_mr *mr, u64 io_virt, size_t bcnt, 738 u32 *bytes_mapped, u32 flags) 739 { 740 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 741 742 if (unlikely(io_virt < mr->mmkey.iova)) 743 return -EFAULT; 744 745 if (mr->umem->is_dmabuf) 746 return pagefault_dmabuf_mr(mr, bcnt, bytes_mapped, flags); 747 748 if (!odp->is_implicit_odp) { 749 u64 user_va; 750 751 if (check_add_overflow(io_virt - mr->mmkey.iova, 752 (u64)odp->umem.address, &user_va)) 753 return -EFAULT; 754 if (unlikely(user_va >= ib_umem_end(odp) || 755 ib_umem_end(odp) - user_va < bcnt)) 756 return -EFAULT; 757 return pagefault_real_mr(mr, odp, user_va, bcnt, bytes_mapped, 758 flags); 759 } 760 return pagefault_implicit_mr(mr, odp, io_virt, bcnt, bytes_mapped, 761 flags); 762 } 763 764 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 765 { 766 int ret; 767 768 ret = pagefault_real_mr(mr, to_ib_umem_odp(mr->umem), mr->umem->address, 769 mr->umem->length, NULL, 770 MLX5_PF_FLAGS_SNAPSHOT | MLX5_PF_FLAGS_ENABLE); 771 return ret >= 0 ? 0 : ret; 772 } 773 774 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 775 { 776 int ret; 777 778 ret = pagefault_dmabuf_mr(mr, mr->umem->length, NULL, 779 MLX5_PF_FLAGS_ENABLE); 780 781 return ret >= 0 ? 0 : ret; 782 } 783 784 struct pf_frame { 785 struct pf_frame *next; 786 u32 key; 787 u64 io_virt; 788 size_t bcnt; 789 int depth; 790 }; 791 792 static bool mkey_is_eq(struct mlx5_core_mkey *mmkey, u32 key) 793 { 794 if (!mmkey) 795 return false; 796 if (mmkey->type == MLX5_MKEY_MW) 797 return mlx5_base_mkey(mmkey->key) == mlx5_base_mkey(key); 798 return mmkey->key == key; 799 } 800 801 static int get_indirect_num_descs(struct mlx5_core_mkey *mmkey) 802 { 803 struct mlx5_ib_mw *mw; 804 struct mlx5_ib_devx_mr *devx_mr; 805 806 if (mmkey->type == MLX5_MKEY_MW) { 807 mw = container_of(mmkey, struct mlx5_ib_mw, mmkey); 808 return mw->ndescs; 809 } 810 811 devx_mr = container_of(mmkey, struct mlx5_ib_devx_mr, 812 mmkey); 813 return devx_mr->ndescs; 814 } 815 816 /* 817 * Handle a single data segment in a page-fault WQE or RDMA region. 818 * 819 * Returns number of OS pages retrieved on success. The caller may continue to 820 * the next data segment. 821 * Can return the following error codes: 822 * -EAGAIN to designate a temporary error. The caller will abort handling the 823 * page fault and resolve it. 824 * -EFAULT when there's an error mapping the requested pages. The caller will 825 * abort the page fault handling. 826 */ 827 static int pagefault_single_data_segment(struct mlx5_ib_dev *dev, 828 struct ib_pd *pd, u32 key, 829 u64 io_virt, size_t bcnt, 830 u32 *bytes_committed, 831 u32 *bytes_mapped) 832 { 833 int npages = 0, ret, i, outlen, cur_outlen = 0, depth = 0; 834 struct pf_frame *head = NULL, *frame; 835 struct mlx5_core_mkey *mmkey; 836 struct mlx5_ib_mr *mr; 837 struct mlx5_klm *pklm; 838 u32 *out = NULL; 839 size_t offset; 840 int ndescs; 841 842 io_virt += *bytes_committed; 843 bcnt -= *bytes_committed; 844 845 next_mr: 846 xa_lock(&dev->odp_mkeys); 847 mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(key)); 848 if (!mmkey) { 849 xa_unlock(&dev->odp_mkeys); 850 mlx5_ib_dbg( 851 dev, 852 "skipping non ODP MR (lkey=0x%06x) in page fault handler.\n", 853 key); 854 if (bytes_mapped) 855 *bytes_mapped += bcnt; 856 /* 857 * The user could specify a SGL with multiple lkeys and only 858 * some of them are ODP. Treat the non-ODP ones as fully 859 * faulted. 860 */ 861 ret = 0; 862 goto end; 863 } 864 refcount_inc(&mmkey->usecount); 865 xa_unlock(&dev->odp_mkeys); 866 867 if (!mkey_is_eq(mmkey, key)) { 868 mlx5_ib_dbg(dev, "failed to find mkey %x\n", key); 869 ret = -EFAULT; 870 goto end; 871 } 872 873 switch (mmkey->type) { 874 case MLX5_MKEY_MR: 875 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey); 876 877 ret = pagefault_mr(mr, io_virt, bcnt, bytes_mapped, 0); 878 if (ret < 0) 879 goto end; 880 881 mlx5_update_odp_stats(mr, faults, ret); 882 883 npages += ret; 884 ret = 0; 885 break; 886 887 case MLX5_MKEY_MW: 888 case MLX5_MKEY_INDIRECT_DEVX: 889 ndescs = get_indirect_num_descs(mmkey); 890 891 if (depth >= MLX5_CAP_GEN(dev->mdev, max_indirection)) { 892 mlx5_ib_dbg(dev, "indirection level exceeded\n"); 893 ret = -EFAULT; 894 goto end; 895 } 896 897 outlen = MLX5_ST_SZ_BYTES(query_mkey_out) + 898 sizeof(*pklm) * (ndescs - 2); 899 900 if (outlen > cur_outlen) { 901 kfree(out); 902 out = kzalloc(outlen, GFP_KERNEL); 903 if (!out) { 904 ret = -ENOMEM; 905 goto end; 906 } 907 cur_outlen = outlen; 908 } 909 910 pklm = (struct mlx5_klm *)MLX5_ADDR_OF(query_mkey_out, out, 911 bsf0_klm0_pas_mtt0_1); 912 913 ret = mlx5_core_query_mkey(dev->mdev, mmkey, out, outlen); 914 if (ret) 915 goto end; 916 917 offset = io_virt - MLX5_GET64(query_mkey_out, out, 918 memory_key_mkey_entry.start_addr); 919 920 for (i = 0; bcnt && i < ndescs; i++, pklm++) { 921 if (offset >= be32_to_cpu(pklm->bcount)) { 922 offset -= be32_to_cpu(pklm->bcount); 923 continue; 924 } 925 926 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 927 if (!frame) { 928 ret = -ENOMEM; 929 goto end; 930 } 931 932 frame->key = be32_to_cpu(pklm->key); 933 frame->io_virt = be64_to_cpu(pklm->va) + offset; 934 frame->bcnt = min_t(size_t, bcnt, 935 be32_to_cpu(pklm->bcount) - offset); 936 frame->depth = depth + 1; 937 frame->next = head; 938 head = frame; 939 940 bcnt -= frame->bcnt; 941 offset = 0; 942 } 943 break; 944 945 default: 946 mlx5_ib_dbg(dev, "wrong mkey type %d\n", mmkey->type); 947 ret = -EFAULT; 948 goto end; 949 } 950 951 if (head) { 952 frame = head; 953 head = frame->next; 954 955 key = frame->key; 956 io_virt = frame->io_virt; 957 bcnt = frame->bcnt; 958 depth = frame->depth; 959 kfree(frame); 960 961 mlx5r_deref_odp_mkey(mmkey); 962 goto next_mr; 963 } 964 965 end: 966 if (mmkey) 967 mlx5r_deref_odp_mkey(mmkey); 968 while (head) { 969 frame = head; 970 head = frame->next; 971 kfree(frame); 972 } 973 kfree(out); 974 975 *bytes_committed = 0; 976 return ret ? ret : npages; 977 } 978 979 /* 980 * Parse a series of data segments for page fault handling. 981 * 982 * @dev: Pointer to mlx5 IB device 983 * @pfault: contains page fault information. 984 * @wqe: points at the first data segment in the WQE. 985 * @wqe_end: points after the end of the WQE. 986 * @bytes_mapped: receives the number of bytes that the function was able to 987 * map. This allows the caller to decide intelligently whether 988 * enough memory was mapped to resolve the page fault 989 * successfully (e.g. enough for the next MTU, or the entire 990 * WQE). 991 * @total_wqe_bytes: receives the total data size of this WQE in bytes (minus 992 * the committed bytes). 993 * @receive_queue: receive WQE end of sg list 994 * 995 * Returns the number of pages loaded if positive, zero for an empty WQE, or a 996 * negative error code. 997 */ 998 static int pagefault_data_segments(struct mlx5_ib_dev *dev, 999 struct mlx5_pagefault *pfault, 1000 void *wqe, 1001 void *wqe_end, u32 *bytes_mapped, 1002 u32 *total_wqe_bytes, bool receive_queue) 1003 { 1004 int ret = 0, npages = 0; 1005 u64 io_virt; 1006 u32 key; 1007 u32 byte_count; 1008 size_t bcnt; 1009 int inline_segment; 1010 1011 if (bytes_mapped) 1012 *bytes_mapped = 0; 1013 if (total_wqe_bytes) 1014 *total_wqe_bytes = 0; 1015 1016 while (wqe < wqe_end) { 1017 struct mlx5_wqe_data_seg *dseg = wqe; 1018 1019 io_virt = be64_to_cpu(dseg->addr); 1020 key = be32_to_cpu(dseg->lkey); 1021 byte_count = be32_to_cpu(dseg->byte_count); 1022 inline_segment = !!(byte_count & MLX5_INLINE_SEG); 1023 bcnt = byte_count & ~MLX5_INLINE_SEG; 1024 1025 if (inline_segment) { 1026 bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK; 1027 wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt, 1028 16); 1029 } else { 1030 wqe += sizeof(*dseg); 1031 } 1032 1033 /* receive WQE end of sg list. */ 1034 if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY && 1035 io_virt == 0) 1036 break; 1037 1038 if (!inline_segment && total_wqe_bytes) { 1039 *total_wqe_bytes += bcnt - min_t(size_t, bcnt, 1040 pfault->bytes_committed); 1041 } 1042 1043 /* A zero length data segment designates a length of 2GB. */ 1044 if (bcnt == 0) 1045 bcnt = 1U << 31; 1046 1047 if (inline_segment || bcnt <= pfault->bytes_committed) { 1048 pfault->bytes_committed -= 1049 min_t(size_t, bcnt, 1050 pfault->bytes_committed); 1051 continue; 1052 } 1053 1054 ret = pagefault_single_data_segment(dev, NULL, key, 1055 io_virt, bcnt, 1056 &pfault->bytes_committed, 1057 bytes_mapped); 1058 if (ret < 0) 1059 break; 1060 npages += ret; 1061 } 1062 1063 return ret < 0 ? ret : npages; 1064 } 1065 1066 /* 1067 * Parse initiator WQE. Advances the wqe pointer to point at the 1068 * scatter-gather list, and set wqe_end to the end of the WQE. 1069 */ 1070 static int mlx5_ib_mr_initiator_pfault_handler( 1071 struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault, 1072 struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length) 1073 { 1074 struct mlx5_wqe_ctrl_seg *ctrl = *wqe; 1075 u16 wqe_index = pfault->wqe.wqe_index; 1076 struct mlx5_base_av *av; 1077 unsigned ds, opcode; 1078 u32 qpn = qp->trans_qp.base.mqp.qpn; 1079 1080 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 1081 if (ds * MLX5_WQE_DS_UNITS > wqe_length) { 1082 mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n", 1083 ds, wqe_length); 1084 return -EFAULT; 1085 } 1086 1087 if (ds == 0) { 1088 mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n", 1089 wqe_index, qpn); 1090 return -EFAULT; 1091 } 1092 1093 *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS; 1094 *wqe += sizeof(*ctrl); 1095 1096 opcode = be32_to_cpu(ctrl->opmod_idx_opcode) & 1097 MLX5_WQE_CTRL_OPCODE_MASK; 1098 1099 if (qp->ibqp.qp_type == IB_QPT_XRC_INI) 1100 *wqe += sizeof(struct mlx5_wqe_xrc_seg); 1101 1102 if (qp->type == IB_QPT_UD || qp->type == MLX5_IB_QPT_DCI) { 1103 av = *wqe; 1104 if (av->dqp_dct & cpu_to_be32(MLX5_EXTENDED_UD_AV)) 1105 *wqe += sizeof(struct mlx5_av); 1106 else 1107 *wqe += sizeof(struct mlx5_base_av); 1108 } 1109 1110 switch (opcode) { 1111 case MLX5_OPCODE_RDMA_WRITE: 1112 case MLX5_OPCODE_RDMA_WRITE_IMM: 1113 case MLX5_OPCODE_RDMA_READ: 1114 *wqe += sizeof(struct mlx5_wqe_raddr_seg); 1115 break; 1116 case MLX5_OPCODE_ATOMIC_CS: 1117 case MLX5_OPCODE_ATOMIC_FA: 1118 *wqe += sizeof(struct mlx5_wqe_raddr_seg); 1119 *wqe += sizeof(struct mlx5_wqe_atomic_seg); 1120 break; 1121 } 1122 1123 return 0; 1124 } 1125 1126 /* 1127 * Parse responder WQE and set wqe_end to the end of the WQE. 1128 */ 1129 static int mlx5_ib_mr_responder_pfault_handler_srq(struct mlx5_ib_dev *dev, 1130 struct mlx5_ib_srq *srq, 1131 void **wqe, void **wqe_end, 1132 int wqe_length) 1133 { 1134 int wqe_size = 1 << srq->msrq.wqe_shift; 1135 1136 if (wqe_size > wqe_length) { 1137 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n"); 1138 return -EFAULT; 1139 } 1140 1141 *wqe_end = *wqe + wqe_size; 1142 *wqe += sizeof(struct mlx5_wqe_srq_next_seg); 1143 1144 return 0; 1145 } 1146 1147 static int mlx5_ib_mr_responder_pfault_handler_rq(struct mlx5_ib_dev *dev, 1148 struct mlx5_ib_qp *qp, 1149 void *wqe, void **wqe_end, 1150 int wqe_length) 1151 { 1152 struct mlx5_ib_wq *wq = &qp->rq; 1153 int wqe_size = 1 << wq->wqe_shift; 1154 1155 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) { 1156 mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n"); 1157 return -EFAULT; 1158 } 1159 1160 if (wqe_size > wqe_length) { 1161 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n"); 1162 return -EFAULT; 1163 } 1164 1165 *wqe_end = wqe + wqe_size; 1166 1167 return 0; 1168 } 1169 1170 static inline struct mlx5_core_rsc_common *odp_get_rsc(struct mlx5_ib_dev *dev, 1171 u32 wq_num, int pf_type) 1172 { 1173 struct mlx5_core_rsc_common *common = NULL; 1174 struct mlx5_core_srq *srq; 1175 1176 switch (pf_type) { 1177 case MLX5_WQE_PF_TYPE_RMP: 1178 srq = mlx5_cmd_get_srq(dev, wq_num); 1179 if (srq) 1180 common = &srq->common; 1181 break; 1182 case MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE: 1183 case MLX5_WQE_PF_TYPE_RESP: 1184 case MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC: 1185 common = mlx5_core_res_hold(dev, wq_num, MLX5_RES_QP); 1186 break; 1187 default: 1188 break; 1189 } 1190 1191 return common; 1192 } 1193 1194 static inline struct mlx5_ib_qp *res_to_qp(struct mlx5_core_rsc_common *res) 1195 { 1196 struct mlx5_core_qp *mqp = (struct mlx5_core_qp *)res; 1197 1198 return to_mibqp(mqp); 1199 } 1200 1201 static inline struct mlx5_ib_srq *res_to_srq(struct mlx5_core_rsc_common *res) 1202 { 1203 struct mlx5_core_srq *msrq = 1204 container_of(res, struct mlx5_core_srq, common); 1205 1206 return to_mibsrq(msrq); 1207 } 1208 1209 static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev *dev, 1210 struct mlx5_pagefault *pfault) 1211 { 1212 bool sq = pfault->type & MLX5_PFAULT_REQUESTOR; 1213 u16 wqe_index = pfault->wqe.wqe_index; 1214 void *wqe, *wqe_start = NULL, *wqe_end = NULL; 1215 u32 bytes_mapped, total_wqe_bytes; 1216 struct mlx5_core_rsc_common *res; 1217 int resume_with_error = 1; 1218 struct mlx5_ib_qp *qp; 1219 size_t bytes_copied; 1220 int ret = 0; 1221 1222 res = odp_get_rsc(dev, pfault->wqe.wq_num, pfault->type); 1223 if (!res) { 1224 mlx5_ib_dbg(dev, "wqe page fault for missing resource %d\n", pfault->wqe.wq_num); 1225 return; 1226 } 1227 1228 if (res->res != MLX5_RES_QP && res->res != MLX5_RES_SRQ && 1229 res->res != MLX5_RES_XSRQ) { 1230 mlx5_ib_err(dev, "wqe page fault for unsupported type %d\n", 1231 pfault->type); 1232 goto resolve_page_fault; 1233 } 1234 1235 wqe_start = (void *)__get_free_page(GFP_KERNEL); 1236 if (!wqe_start) { 1237 mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n"); 1238 goto resolve_page_fault; 1239 } 1240 1241 wqe = wqe_start; 1242 qp = (res->res == MLX5_RES_QP) ? res_to_qp(res) : NULL; 1243 if (qp && sq) { 1244 ret = mlx5_ib_read_wqe_sq(qp, wqe_index, wqe, PAGE_SIZE, 1245 &bytes_copied); 1246 if (ret) 1247 goto read_user; 1248 ret = mlx5_ib_mr_initiator_pfault_handler( 1249 dev, pfault, qp, &wqe, &wqe_end, bytes_copied); 1250 } else if (qp && !sq) { 1251 ret = mlx5_ib_read_wqe_rq(qp, wqe_index, wqe, PAGE_SIZE, 1252 &bytes_copied); 1253 if (ret) 1254 goto read_user; 1255 ret = mlx5_ib_mr_responder_pfault_handler_rq( 1256 dev, qp, wqe, &wqe_end, bytes_copied); 1257 } else if (!qp) { 1258 struct mlx5_ib_srq *srq = res_to_srq(res); 1259 1260 ret = mlx5_ib_read_wqe_srq(srq, wqe_index, wqe, PAGE_SIZE, 1261 &bytes_copied); 1262 if (ret) 1263 goto read_user; 1264 ret = mlx5_ib_mr_responder_pfault_handler_srq( 1265 dev, srq, &wqe, &wqe_end, bytes_copied); 1266 } 1267 1268 if (ret < 0 || wqe >= wqe_end) 1269 goto resolve_page_fault; 1270 1271 ret = pagefault_data_segments(dev, pfault, wqe, wqe_end, &bytes_mapped, 1272 &total_wqe_bytes, !sq); 1273 if (ret == -EAGAIN) 1274 goto out; 1275 1276 if (ret < 0 || total_wqe_bytes > bytes_mapped) 1277 goto resolve_page_fault; 1278 1279 out: 1280 ret = 0; 1281 resume_with_error = 0; 1282 1283 read_user: 1284 if (ret) 1285 mlx5_ib_err( 1286 dev, 1287 "Failed reading a WQE following page fault, error %d, wqe_index %x, qpn %x\n", 1288 ret, wqe_index, pfault->token); 1289 1290 resolve_page_fault: 1291 mlx5_ib_page_fault_resume(dev, pfault, resume_with_error); 1292 mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, type: 0x%x\n", 1293 pfault->wqe.wq_num, resume_with_error, 1294 pfault->type); 1295 mlx5_core_res_put(res); 1296 free_page((unsigned long)wqe_start); 1297 } 1298 1299 static int pages_in_range(u64 address, u32 length) 1300 { 1301 return (ALIGN(address + length, PAGE_SIZE) - 1302 (address & PAGE_MASK)) >> PAGE_SHIFT; 1303 } 1304 1305 static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev, 1306 struct mlx5_pagefault *pfault) 1307 { 1308 u64 address; 1309 u32 length; 1310 u32 prefetch_len = pfault->bytes_committed; 1311 int prefetch_activated = 0; 1312 u32 rkey = pfault->rdma.r_key; 1313 int ret; 1314 1315 /* The RDMA responder handler handles the page fault in two parts. 1316 * First it brings the necessary pages for the current packet 1317 * (and uses the pfault context), and then (after resuming the QP) 1318 * prefetches more pages. The second operation cannot use the pfault 1319 * context and therefore uses the dummy_pfault context allocated on 1320 * the stack */ 1321 pfault->rdma.rdma_va += pfault->bytes_committed; 1322 pfault->rdma.rdma_op_len -= min(pfault->bytes_committed, 1323 pfault->rdma.rdma_op_len); 1324 pfault->bytes_committed = 0; 1325 1326 address = pfault->rdma.rdma_va; 1327 length = pfault->rdma.rdma_op_len; 1328 1329 /* For some operations, the hardware cannot tell the exact message 1330 * length, and in those cases it reports zero. Use prefetch 1331 * logic. */ 1332 if (length == 0) { 1333 prefetch_activated = 1; 1334 length = pfault->rdma.packet_size; 1335 prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len); 1336 } 1337 1338 ret = pagefault_single_data_segment(dev, NULL, rkey, address, length, 1339 &pfault->bytes_committed, NULL); 1340 if (ret == -EAGAIN) { 1341 /* We're racing with an invalidation, don't prefetch */ 1342 prefetch_activated = 0; 1343 } else if (ret < 0 || pages_in_range(address, length) > ret) { 1344 mlx5_ib_page_fault_resume(dev, pfault, 1); 1345 if (ret != -ENOENT) 1346 mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n", 1347 ret, pfault->token, pfault->type); 1348 return; 1349 } 1350 1351 mlx5_ib_page_fault_resume(dev, pfault, 0); 1352 mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x, type: 0x%x, prefetch_activated: %d\n", 1353 pfault->token, pfault->type, 1354 prefetch_activated); 1355 1356 /* At this point, there might be a new pagefault already arriving in 1357 * the eq, switch to the dummy pagefault for the rest of the 1358 * processing. We're still OK with the objects being alive as the 1359 * work-queue is being fenced. */ 1360 1361 if (prefetch_activated) { 1362 u32 bytes_committed = 0; 1363 1364 ret = pagefault_single_data_segment(dev, NULL, rkey, address, 1365 prefetch_len, 1366 &bytes_committed, NULL); 1367 if (ret < 0 && ret != -EAGAIN) { 1368 mlx5_ib_dbg(dev, "Prefetch failed. ret: %d, QP 0x%x, address: 0x%.16llx, length = 0x%.16x\n", 1369 ret, pfault->token, address, prefetch_len); 1370 } 1371 } 1372 } 1373 1374 static void mlx5_ib_pfault(struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault) 1375 { 1376 u8 event_subtype = pfault->event_subtype; 1377 1378 switch (event_subtype) { 1379 case MLX5_PFAULT_SUBTYPE_WQE: 1380 mlx5_ib_mr_wqe_pfault_handler(dev, pfault); 1381 break; 1382 case MLX5_PFAULT_SUBTYPE_RDMA: 1383 mlx5_ib_mr_rdma_pfault_handler(dev, pfault); 1384 break; 1385 default: 1386 mlx5_ib_err(dev, "Invalid page fault event subtype: 0x%x\n", 1387 event_subtype); 1388 mlx5_ib_page_fault_resume(dev, pfault, 1); 1389 } 1390 } 1391 1392 static void mlx5_ib_eqe_pf_action(struct work_struct *work) 1393 { 1394 struct mlx5_pagefault *pfault = container_of(work, 1395 struct mlx5_pagefault, 1396 work); 1397 struct mlx5_ib_pf_eq *eq = pfault->eq; 1398 1399 mlx5_ib_pfault(eq->dev, pfault); 1400 mempool_free(pfault, eq->pool); 1401 } 1402 1403 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq) 1404 { 1405 struct mlx5_eqe_page_fault *pf_eqe; 1406 struct mlx5_pagefault *pfault; 1407 struct mlx5_eqe *eqe; 1408 int cc = 0; 1409 1410 while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) { 1411 pfault = mempool_alloc(eq->pool, GFP_ATOMIC); 1412 if (!pfault) { 1413 schedule_work(&eq->work); 1414 break; 1415 } 1416 1417 pf_eqe = &eqe->data.page_fault; 1418 pfault->event_subtype = eqe->sub_type; 1419 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed); 1420 1421 mlx5_ib_dbg(eq->dev, 1422 "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n", 1423 eqe->sub_type, pfault->bytes_committed); 1424 1425 switch (eqe->sub_type) { 1426 case MLX5_PFAULT_SUBTYPE_RDMA: 1427 /* RDMA based event */ 1428 pfault->type = 1429 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24; 1430 pfault->token = 1431 be32_to_cpu(pf_eqe->rdma.pftype_token) & 1432 MLX5_24BIT_MASK; 1433 pfault->rdma.r_key = 1434 be32_to_cpu(pf_eqe->rdma.r_key); 1435 pfault->rdma.packet_size = 1436 be16_to_cpu(pf_eqe->rdma.packet_length); 1437 pfault->rdma.rdma_op_len = 1438 be32_to_cpu(pf_eqe->rdma.rdma_op_len); 1439 pfault->rdma.rdma_va = 1440 be64_to_cpu(pf_eqe->rdma.rdma_va); 1441 mlx5_ib_dbg(eq->dev, 1442 "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n", 1443 pfault->type, pfault->token, 1444 pfault->rdma.r_key); 1445 mlx5_ib_dbg(eq->dev, 1446 "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n", 1447 pfault->rdma.rdma_op_len, 1448 pfault->rdma.rdma_va); 1449 break; 1450 1451 case MLX5_PFAULT_SUBTYPE_WQE: 1452 /* WQE based event */ 1453 pfault->type = 1454 (be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24) & 0x7; 1455 pfault->token = 1456 be32_to_cpu(pf_eqe->wqe.token); 1457 pfault->wqe.wq_num = 1458 be32_to_cpu(pf_eqe->wqe.pftype_wq) & 1459 MLX5_24BIT_MASK; 1460 pfault->wqe.wqe_index = 1461 be16_to_cpu(pf_eqe->wqe.wqe_index); 1462 pfault->wqe.packet_size = 1463 be16_to_cpu(pf_eqe->wqe.packet_length); 1464 mlx5_ib_dbg(eq->dev, 1465 "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n", 1466 pfault->type, pfault->token, 1467 pfault->wqe.wq_num, 1468 pfault->wqe.wqe_index); 1469 break; 1470 1471 default: 1472 mlx5_ib_warn(eq->dev, 1473 "Unsupported page fault event sub-type: 0x%02hhx\n", 1474 eqe->sub_type); 1475 /* Unsupported page faults should still be 1476 * resolved by the page fault handler 1477 */ 1478 } 1479 1480 pfault->eq = eq; 1481 INIT_WORK(&pfault->work, mlx5_ib_eqe_pf_action); 1482 queue_work(eq->wq, &pfault->work); 1483 1484 cc = mlx5_eq_update_cc(eq->core, ++cc); 1485 } 1486 1487 mlx5_eq_update_ci(eq->core, cc, 1); 1488 } 1489 1490 static int mlx5_ib_eq_pf_int(struct notifier_block *nb, unsigned long type, 1491 void *data) 1492 { 1493 struct mlx5_ib_pf_eq *eq = 1494 container_of(nb, struct mlx5_ib_pf_eq, irq_nb); 1495 unsigned long flags; 1496 1497 if (spin_trylock_irqsave(&eq->lock, flags)) { 1498 mlx5_ib_eq_pf_process(eq); 1499 spin_unlock_irqrestore(&eq->lock, flags); 1500 } else { 1501 schedule_work(&eq->work); 1502 } 1503 1504 return IRQ_HANDLED; 1505 } 1506 1507 /* mempool_refill() was proposed but unfortunately wasn't accepted 1508 * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html 1509 * Cheap workaround. 1510 */ 1511 static void mempool_refill(mempool_t *pool) 1512 { 1513 while (pool->curr_nr < pool->min_nr) 1514 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool); 1515 } 1516 1517 static void mlx5_ib_eq_pf_action(struct work_struct *work) 1518 { 1519 struct mlx5_ib_pf_eq *eq = 1520 container_of(work, struct mlx5_ib_pf_eq, work); 1521 1522 mempool_refill(eq->pool); 1523 1524 spin_lock_irq(&eq->lock); 1525 mlx5_ib_eq_pf_process(eq); 1526 spin_unlock_irq(&eq->lock); 1527 } 1528 1529 enum { 1530 MLX5_IB_NUM_PF_EQE = 0x1000, 1531 MLX5_IB_NUM_PF_DRAIN = 64, 1532 }; 1533 1534 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq) 1535 { 1536 struct mlx5_eq_param param = {}; 1537 int err = 0; 1538 1539 mutex_lock(&dev->odp_eq_mutex); 1540 if (eq->core) 1541 goto unlock; 1542 INIT_WORK(&eq->work, mlx5_ib_eq_pf_action); 1543 spin_lock_init(&eq->lock); 1544 eq->dev = dev; 1545 1546 eq->pool = mempool_create_kmalloc_pool(MLX5_IB_NUM_PF_DRAIN, 1547 sizeof(struct mlx5_pagefault)); 1548 if (!eq->pool) { 1549 err = -ENOMEM; 1550 goto unlock; 1551 } 1552 1553 eq->wq = alloc_workqueue("mlx5_ib_page_fault", 1554 WQ_HIGHPRI | WQ_UNBOUND | WQ_MEM_RECLAIM, 1555 MLX5_NUM_CMD_EQE); 1556 if (!eq->wq) { 1557 err = -ENOMEM; 1558 goto err_mempool; 1559 } 1560 1561 eq->irq_nb.notifier_call = mlx5_ib_eq_pf_int; 1562 param = (struct mlx5_eq_param){ 1563 .irq_index = 0, 1564 .nent = MLX5_IB_NUM_PF_EQE, 1565 }; 1566 param.mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_FAULT; 1567 eq->core = mlx5_eq_create_generic(dev->mdev, ¶m); 1568 if (IS_ERR(eq->core)) { 1569 err = PTR_ERR(eq->core); 1570 goto err_wq; 1571 } 1572 err = mlx5_eq_enable(dev->mdev, eq->core, &eq->irq_nb); 1573 if (err) { 1574 mlx5_ib_err(dev, "failed to enable odp EQ %d\n", err); 1575 goto err_eq; 1576 } 1577 1578 mutex_unlock(&dev->odp_eq_mutex); 1579 return 0; 1580 err_eq: 1581 mlx5_eq_destroy_generic(dev->mdev, eq->core); 1582 err_wq: 1583 eq->core = NULL; 1584 destroy_workqueue(eq->wq); 1585 err_mempool: 1586 mempool_destroy(eq->pool); 1587 unlock: 1588 mutex_unlock(&dev->odp_eq_mutex); 1589 return err; 1590 } 1591 1592 static int 1593 mlx5_ib_odp_destroy_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq) 1594 { 1595 int err; 1596 1597 if (!eq->core) 1598 return 0; 1599 mlx5_eq_disable(dev->mdev, eq->core, &eq->irq_nb); 1600 err = mlx5_eq_destroy_generic(dev->mdev, eq->core); 1601 cancel_work_sync(&eq->work); 1602 destroy_workqueue(eq->wq); 1603 mempool_destroy(eq->pool); 1604 1605 return err; 1606 } 1607 1608 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) 1609 { 1610 if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) 1611 return; 1612 1613 switch (ent->order - 2) { 1614 case MLX5_IMR_MTT_CACHE_ENTRY: 1615 ent->page = PAGE_SHIFT; 1616 ent->xlt = MLX5_IMR_MTT_ENTRIES * 1617 sizeof(struct mlx5_mtt) / 1618 MLX5_IB_UMR_OCTOWORD; 1619 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; 1620 ent->limit = 0; 1621 break; 1622 1623 case MLX5_IMR_KSM_CACHE_ENTRY: 1624 ent->page = MLX5_KSM_PAGE_SHIFT; 1625 ent->xlt = mlx5_imr_ksm_entries * 1626 sizeof(struct mlx5_klm) / 1627 MLX5_IB_UMR_OCTOWORD; 1628 ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM; 1629 ent->limit = 0; 1630 break; 1631 } 1632 } 1633 1634 static const struct ib_device_ops mlx5_ib_dev_odp_ops = { 1635 .advise_mr = mlx5_ib_advise_mr, 1636 }; 1637 1638 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *dev) 1639 { 1640 int ret = 0; 1641 1642 internal_fill_odp_caps(dev); 1643 1644 if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT)) 1645 return ret; 1646 1647 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_odp_ops); 1648 1649 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT) { 1650 ret = mlx5_cmd_null_mkey(dev->mdev, &dev->null_mkey); 1651 if (ret) { 1652 mlx5_ib_err(dev, "Error getting null_mkey %d\n", ret); 1653 return ret; 1654 } 1655 } 1656 1657 mutex_init(&dev->odp_eq_mutex); 1658 return ret; 1659 } 1660 1661 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *dev) 1662 { 1663 if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT)) 1664 return; 1665 1666 mlx5_ib_odp_destroy_eq(dev, &dev->odp_pf_eq); 1667 } 1668 1669 int mlx5_ib_odp_init(void) 1670 { 1671 mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) - 1672 MLX5_IMR_MTT_BITS); 1673 1674 return 0; 1675 } 1676 1677 struct prefetch_mr_work { 1678 struct work_struct work; 1679 u32 pf_flags; 1680 u32 num_sge; 1681 struct { 1682 u64 io_virt; 1683 struct mlx5_ib_mr *mr; 1684 size_t length; 1685 } frags[]; 1686 }; 1687 1688 static void destroy_prefetch_work(struct prefetch_mr_work *work) 1689 { 1690 u32 i; 1691 1692 for (i = 0; i < work->num_sge; ++i) 1693 mlx5r_deref_odp_mkey(&work->frags[i].mr->mmkey); 1694 1695 kvfree(work); 1696 } 1697 1698 static struct mlx5_ib_mr * 1699 get_prefetchable_mr(struct ib_pd *pd, enum ib_uverbs_advise_mr_advice advice, 1700 u32 lkey) 1701 { 1702 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1703 struct mlx5_core_mkey *mmkey; 1704 struct mlx5_ib_mr *mr = NULL; 1705 1706 xa_lock(&dev->odp_mkeys); 1707 mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(lkey)); 1708 if (!mmkey || mmkey->key != lkey || mmkey->type != MLX5_MKEY_MR) 1709 goto end; 1710 1711 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey); 1712 1713 if (mr->ibmr.pd != pd) { 1714 mr = NULL; 1715 goto end; 1716 } 1717 1718 /* prefetch with write-access must be supported by the MR */ 1719 if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE && 1720 !mr->umem->writable) { 1721 mr = NULL; 1722 goto end; 1723 } 1724 1725 refcount_inc(&mmkey->usecount); 1726 end: 1727 xa_unlock(&dev->odp_mkeys); 1728 return mr; 1729 } 1730 1731 static void mlx5_ib_prefetch_mr_work(struct work_struct *w) 1732 { 1733 struct prefetch_mr_work *work = 1734 container_of(w, struct prefetch_mr_work, work); 1735 u32 bytes_mapped = 0; 1736 int ret; 1737 u32 i; 1738 1739 /* We rely on IB/core that work is executed if we have num_sge != 0 only. */ 1740 WARN_ON(!work->num_sge); 1741 for (i = 0; i < work->num_sge; ++i) { 1742 ret = pagefault_mr(work->frags[i].mr, work->frags[i].io_virt, 1743 work->frags[i].length, &bytes_mapped, 1744 work->pf_flags); 1745 if (ret <= 0) 1746 continue; 1747 mlx5_update_odp_stats(work->frags[i].mr, prefetch, ret); 1748 } 1749 1750 destroy_prefetch_work(work); 1751 } 1752 1753 static bool init_prefetch_work(struct ib_pd *pd, 1754 enum ib_uverbs_advise_mr_advice advice, 1755 u32 pf_flags, struct prefetch_mr_work *work, 1756 struct ib_sge *sg_list, u32 num_sge) 1757 { 1758 u32 i; 1759 1760 INIT_WORK(&work->work, mlx5_ib_prefetch_mr_work); 1761 work->pf_flags = pf_flags; 1762 1763 for (i = 0; i < num_sge; ++i) { 1764 work->frags[i].io_virt = sg_list[i].addr; 1765 work->frags[i].length = sg_list[i].length; 1766 work->frags[i].mr = 1767 get_prefetchable_mr(pd, advice, sg_list[i].lkey); 1768 if (!work->frags[i].mr) { 1769 work->num_sge = i; 1770 return false; 1771 } 1772 } 1773 work->num_sge = num_sge; 1774 return true; 1775 } 1776 1777 static int mlx5_ib_prefetch_sg_list(struct ib_pd *pd, 1778 enum ib_uverbs_advise_mr_advice advice, 1779 u32 pf_flags, struct ib_sge *sg_list, 1780 u32 num_sge) 1781 { 1782 u32 bytes_mapped = 0; 1783 int ret = 0; 1784 u32 i; 1785 1786 for (i = 0; i < num_sge; ++i) { 1787 struct mlx5_ib_mr *mr; 1788 1789 mr = get_prefetchable_mr(pd, advice, sg_list[i].lkey); 1790 if (!mr) 1791 return -ENOENT; 1792 ret = pagefault_mr(mr, sg_list[i].addr, sg_list[i].length, 1793 &bytes_mapped, pf_flags); 1794 if (ret < 0) { 1795 mlx5r_deref_odp_mkey(&mr->mmkey); 1796 return ret; 1797 } 1798 mlx5_update_odp_stats(mr, prefetch, ret); 1799 mlx5r_deref_odp_mkey(&mr->mmkey); 1800 } 1801 1802 return 0; 1803 } 1804 1805 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1806 enum ib_uverbs_advise_mr_advice advice, 1807 u32 flags, struct ib_sge *sg_list, u32 num_sge) 1808 { 1809 u32 pf_flags = 0; 1810 struct prefetch_mr_work *work; 1811 1812 if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH) 1813 pf_flags |= MLX5_PF_FLAGS_DOWNGRADE; 1814 1815 if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT) 1816 pf_flags |= MLX5_PF_FLAGS_SNAPSHOT; 1817 1818 if (flags & IB_UVERBS_ADVISE_MR_FLAG_FLUSH) 1819 return mlx5_ib_prefetch_sg_list(pd, advice, pf_flags, sg_list, 1820 num_sge); 1821 1822 work = kvzalloc(struct_size(work, frags, num_sge), GFP_KERNEL); 1823 if (!work) 1824 return -ENOMEM; 1825 1826 if (!init_prefetch_work(pd, advice, pf_flags, work, sg_list, num_sge)) { 1827 destroy_prefetch_work(work); 1828 return -EINVAL; 1829 } 1830 queue_work(system_unbound_wq, &work->work); 1831 return 0; 1832 } 1833