1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <rdma/ib_umem.h> 34 #include <rdma/ib_umem_odp.h> 35 #include <linux/kernel.h> 36 #include <linux/dma-buf.h> 37 #include <linux/dma-resv.h> 38 39 #include "mlx5_ib.h" 40 #include "cmd.h" 41 #include "qp.h" 42 43 #include <linux/mlx5/eq.h> 44 45 /* Contains the details of a pagefault. */ 46 struct mlx5_pagefault { 47 u32 bytes_committed; 48 u32 token; 49 u8 event_subtype; 50 u8 type; 51 union { 52 /* Initiator or send message responder pagefault details. */ 53 struct { 54 /* Received packet size, only valid for responders. */ 55 u32 packet_size; 56 /* 57 * Number of resource holding WQE, depends on type. 58 */ 59 u32 wq_num; 60 /* 61 * WQE index. Refers to either the send queue or 62 * receive queue, according to event_subtype. 63 */ 64 u16 wqe_index; 65 } wqe; 66 /* RDMA responder pagefault details */ 67 struct { 68 u32 r_key; 69 /* 70 * Received packet size, minimal size page fault 71 * resolution required for forward progress. 72 */ 73 u32 packet_size; 74 u32 rdma_op_len; 75 u64 rdma_va; 76 } rdma; 77 }; 78 79 struct mlx5_ib_pf_eq *eq; 80 struct work_struct work; 81 }; 82 83 #define MAX_PREFETCH_LEN (4*1024*1024U) 84 85 /* Timeout in ms to wait for an active mmu notifier to complete when handling 86 * a pagefault. */ 87 #define MMU_NOTIFIER_TIMEOUT 1000 88 89 #define MLX5_IMR_MTT_BITS (30 - PAGE_SHIFT) 90 #define MLX5_IMR_MTT_SHIFT (MLX5_IMR_MTT_BITS + PAGE_SHIFT) 91 #define MLX5_IMR_MTT_ENTRIES BIT_ULL(MLX5_IMR_MTT_BITS) 92 #define MLX5_IMR_MTT_SIZE BIT_ULL(MLX5_IMR_MTT_SHIFT) 93 #define MLX5_IMR_MTT_MASK (~(MLX5_IMR_MTT_SIZE - 1)) 94 95 #define MLX5_KSM_PAGE_SHIFT MLX5_IMR_MTT_SHIFT 96 97 static u64 mlx5_imr_ksm_entries; 98 99 static void populate_klm(struct mlx5_klm *pklm, size_t idx, size_t nentries, 100 struct mlx5_ib_mr *imr, int flags) 101 { 102 struct mlx5_klm *end = pklm + nentries; 103 104 if (flags & MLX5_IB_UPD_XLT_ZAP) { 105 for (; pklm != end; pklm++, idx++) { 106 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE); 107 pklm->key = cpu_to_be32(mr_to_mdev(imr)->null_mkey); 108 pklm->va = 0; 109 } 110 return; 111 } 112 113 /* 114 * The locking here is pretty subtle. Ideally the implicit_children 115 * xarray would be protected by the umem_mutex, however that is not 116 * possible. Instead this uses a weaker update-then-lock pattern: 117 * 118 * xa_store() 119 * mutex_lock(umem_mutex) 120 * mlx5_ib_update_xlt() 121 * mutex_unlock(umem_mutex) 122 * destroy lkey 123 * 124 * ie any change the xarray must be followed by the locked update_xlt 125 * before destroying. 126 * 127 * The umem_mutex provides the acquire/release semantic needed to make 128 * the xa_store() visible to a racing thread. 129 */ 130 lockdep_assert_held(&to_ib_umem_odp(imr->umem)->umem_mutex); 131 132 for (; pklm != end; pklm++, idx++) { 133 struct mlx5_ib_mr *mtt = xa_load(&imr->implicit_children, idx); 134 135 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE); 136 if (mtt) { 137 pklm->key = cpu_to_be32(mtt->ibmr.lkey); 138 pklm->va = cpu_to_be64(idx * MLX5_IMR_MTT_SIZE); 139 } else { 140 pklm->key = cpu_to_be32(mr_to_mdev(imr)->null_mkey); 141 pklm->va = 0; 142 } 143 } 144 } 145 146 static u64 umem_dma_to_mtt(dma_addr_t umem_dma) 147 { 148 u64 mtt_entry = umem_dma & ODP_DMA_ADDR_MASK; 149 150 if (umem_dma & ODP_READ_ALLOWED_BIT) 151 mtt_entry |= MLX5_IB_MTT_READ; 152 if (umem_dma & ODP_WRITE_ALLOWED_BIT) 153 mtt_entry |= MLX5_IB_MTT_WRITE; 154 155 return mtt_entry; 156 } 157 158 static void populate_mtt(__be64 *pas, size_t idx, size_t nentries, 159 struct mlx5_ib_mr *mr, int flags) 160 { 161 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 162 dma_addr_t pa; 163 size_t i; 164 165 if (flags & MLX5_IB_UPD_XLT_ZAP) 166 return; 167 168 for (i = 0; i < nentries; i++) { 169 pa = odp->dma_list[idx + i]; 170 pas[i] = cpu_to_be64(umem_dma_to_mtt(pa)); 171 } 172 } 173 174 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 175 struct mlx5_ib_mr *mr, int flags) 176 { 177 if (flags & MLX5_IB_UPD_XLT_INDIRECT) { 178 populate_klm(xlt, idx, nentries, mr, flags); 179 } else { 180 populate_mtt(xlt, idx, nentries, mr, flags); 181 } 182 } 183 184 /* 185 * This must be called after the mr has been removed from implicit_children. 186 * NOTE: The MR does not necessarily have to be 187 * empty here, parallel page faults could have raced with the free process and 188 * added pages to it. 189 */ 190 static void free_implicit_child_mr_work(struct work_struct *work) 191 { 192 struct mlx5_ib_mr *mr = 193 container_of(work, struct mlx5_ib_mr, odp_destroy.work); 194 struct mlx5_ib_mr *imr = mr->parent; 195 struct ib_umem_odp *odp_imr = to_ib_umem_odp(imr->umem); 196 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 197 198 mlx5r_deref_wait_odp_mkey(&mr->mmkey); 199 200 mutex_lock(&odp_imr->umem_mutex); 201 mlx5_ib_update_xlt(mr->parent, ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT, 202 1, 0, 203 MLX5_IB_UPD_XLT_INDIRECT | MLX5_IB_UPD_XLT_ATOMIC); 204 mutex_unlock(&odp_imr->umem_mutex); 205 mlx5_ib_dereg_mr(&mr->ibmr, NULL); 206 207 mlx5r_deref_odp_mkey(&imr->mmkey); 208 } 209 210 static void destroy_unused_implicit_child_mr(struct mlx5_ib_mr *mr) 211 { 212 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 213 unsigned long idx = ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT; 214 struct mlx5_ib_mr *imr = mr->parent; 215 216 if (!refcount_inc_not_zero(&imr->mmkey.usecount)) 217 return; 218 219 xa_erase(&imr->implicit_children, idx); 220 221 /* Freeing a MR is a sleeping operation, so bounce to a work queue */ 222 INIT_WORK(&mr->odp_destroy.work, free_implicit_child_mr_work); 223 queue_work(system_unbound_wq, &mr->odp_destroy.work); 224 } 225 226 static bool mlx5_ib_invalidate_range(struct mmu_interval_notifier *mni, 227 const struct mmu_notifier_range *range, 228 unsigned long cur_seq) 229 { 230 struct ib_umem_odp *umem_odp = 231 container_of(mni, struct ib_umem_odp, notifier); 232 struct mlx5_ib_mr *mr; 233 const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT / 234 sizeof(struct mlx5_mtt)) - 1; 235 u64 idx = 0, blk_start_idx = 0; 236 u64 invalidations = 0; 237 unsigned long start; 238 unsigned long end; 239 int in_block = 0; 240 u64 addr; 241 242 if (!mmu_notifier_range_blockable(range)) 243 return false; 244 245 mutex_lock(&umem_odp->umem_mutex); 246 mmu_interval_set_seq(mni, cur_seq); 247 /* 248 * If npages is zero then umem_odp->private may not be setup yet. This 249 * does not complete until after the first page is mapped for DMA. 250 */ 251 if (!umem_odp->npages) 252 goto out; 253 mr = umem_odp->private; 254 255 start = max_t(u64, ib_umem_start(umem_odp), range->start); 256 end = min_t(u64, ib_umem_end(umem_odp), range->end); 257 258 /* 259 * Iteration one - zap the HW's MTTs. The notifiers_count ensures that 260 * while we are doing the invalidation, no page fault will attempt to 261 * overwrite the same MTTs. Concurent invalidations might race us, 262 * but they will write 0s as well, so no difference in the end result. 263 */ 264 for (addr = start; addr < end; addr += BIT(umem_odp->page_shift)) { 265 idx = (addr - ib_umem_start(umem_odp)) >> umem_odp->page_shift; 266 /* 267 * Strive to write the MTTs in chunks, but avoid overwriting 268 * non-existing MTTs. The huristic here can be improved to 269 * estimate the cost of another UMR vs. the cost of bigger 270 * UMR. 271 */ 272 if (umem_odp->dma_list[idx] & 273 (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) { 274 if (!in_block) { 275 blk_start_idx = idx; 276 in_block = 1; 277 } 278 279 /* Count page invalidations */ 280 invalidations += idx - blk_start_idx + 1; 281 } else { 282 u64 umr_offset = idx & umr_block_mask; 283 284 if (in_block && umr_offset == 0) { 285 mlx5_ib_update_xlt(mr, blk_start_idx, 286 idx - blk_start_idx, 0, 287 MLX5_IB_UPD_XLT_ZAP | 288 MLX5_IB_UPD_XLT_ATOMIC); 289 in_block = 0; 290 } 291 } 292 } 293 if (in_block) 294 mlx5_ib_update_xlt(mr, blk_start_idx, 295 idx - blk_start_idx + 1, 0, 296 MLX5_IB_UPD_XLT_ZAP | 297 MLX5_IB_UPD_XLT_ATOMIC); 298 299 mlx5_update_odp_stats(mr, invalidations, invalidations); 300 301 /* 302 * We are now sure that the device will not access the 303 * memory. We can safely unmap it, and mark it as dirty if 304 * needed. 305 */ 306 307 ib_umem_odp_unmap_dma_pages(umem_odp, start, end); 308 309 if (unlikely(!umem_odp->npages && mr->parent)) 310 destroy_unused_implicit_child_mr(mr); 311 out: 312 mutex_unlock(&umem_odp->umem_mutex); 313 return true; 314 } 315 316 const struct mmu_interval_notifier_ops mlx5_mn_ops = { 317 .invalidate = mlx5_ib_invalidate_range, 318 }; 319 320 static void internal_fill_odp_caps(struct mlx5_ib_dev *dev) 321 { 322 struct ib_odp_caps *caps = &dev->odp_caps; 323 324 memset(caps, 0, sizeof(*caps)); 325 326 if (!MLX5_CAP_GEN(dev->mdev, pg) || 327 !mlx5_ib_can_load_pas_with_umr(dev, 0)) 328 return; 329 330 caps->general_caps = IB_ODP_SUPPORT; 331 332 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) 333 dev->odp_max_size = U64_MAX; 334 else 335 dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT); 336 337 if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send)) 338 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND; 339 340 if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.srq_receive)) 341 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV; 342 343 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send)) 344 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND; 345 346 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive)) 347 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV; 348 349 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write)) 350 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE; 351 352 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read)) 353 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ; 354 355 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.atomic)) 356 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_ATOMIC; 357 358 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.srq_receive)) 359 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV; 360 361 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.send)) 362 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SEND; 363 364 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.receive)) 365 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_RECV; 366 367 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.write)) 368 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_WRITE; 369 370 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.read)) 371 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_READ; 372 373 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.atomic)) 374 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_ATOMIC; 375 376 if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.srq_receive)) 377 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV; 378 379 if (MLX5_CAP_GEN(dev->mdev, fixed_buffer_size) && 380 MLX5_CAP_GEN(dev->mdev, null_mkey) && 381 MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && 382 !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled)) 383 caps->general_caps |= IB_ODP_SUPPORT_IMPLICIT; 384 } 385 386 static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev, 387 struct mlx5_pagefault *pfault, 388 int error) 389 { 390 int wq_num = pfault->event_subtype == MLX5_PFAULT_SUBTYPE_WQE ? 391 pfault->wqe.wq_num : pfault->token; 392 u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)] = {}; 393 int err; 394 395 MLX5_SET(page_fault_resume_in, in, opcode, MLX5_CMD_OP_PAGE_FAULT_RESUME); 396 MLX5_SET(page_fault_resume_in, in, page_fault_type, pfault->type); 397 MLX5_SET(page_fault_resume_in, in, token, pfault->token); 398 MLX5_SET(page_fault_resume_in, in, wq_number, wq_num); 399 MLX5_SET(page_fault_resume_in, in, error, !!error); 400 401 err = mlx5_cmd_exec_in(dev->mdev, page_fault_resume, in); 402 if (err) 403 mlx5_ib_err(dev, "Failed to resolve the page fault on WQ 0x%x err %d\n", 404 wq_num, err); 405 } 406 407 static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr, 408 unsigned long idx) 409 { 410 struct mlx5_ib_dev *dev = mr_to_mdev(imr); 411 struct ib_umem_odp *odp; 412 struct mlx5_ib_mr *mr; 413 struct mlx5_ib_mr *ret; 414 int err; 415 416 odp = ib_umem_odp_alloc_child(to_ib_umem_odp(imr->umem), 417 idx * MLX5_IMR_MTT_SIZE, 418 MLX5_IMR_MTT_SIZE, &mlx5_mn_ops); 419 if (IS_ERR(odp)) 420 return ERR_CAST(odp); 421 422 mr = mlx5_mr_cache_alloc(dev, &dev->cache.ent[MLX5_IMR_MTT_CACHE_ENTRY], 423 imr->access_flags); 424 if (IS_ERR(mr)) { 425 ib_umem_odp_release(odp); 426 return mr; 427 } 428 429 mr->access_flags = imr->access_flags; 430 mr->ibmr.pd = imr->ibmr.pd; 431 mr->ibmr.device = &mr_to_mdev(imr)->ib_dev; 432 mr->umem = &odp->umem; 433 mr->ibmr.lkey = mr->mmkey.key; 434 mr->ibmr.rkey = mr->mmkey.key; 435 mr->ibmr.iova = idx * MLX5_IMR_MTT_SIZE; 436 mr->parent = imr; 437 odp->private = mr; 438 439 /* 440 * First refcount is owned by the xarray and second refconut 441 * is returned to the caller. 442 */ 443 refcount_set(&mr->mmkey.usecount, 2); 444 445 err = mlx5_ib_update_xlt(mr, 0, 446 MLX5_IMR_MTT_ENTRIES, 447 PAGE_SHIFT, 448 MLX5_IB_UPD_XLT_ZAP | 449 MLX5_IB_UPD_XLT_ENABLE); 450 if (err) { 451 ret = ERR_PTR(err); 452 goto out_mr; 453 } 454 455 xa_lock(&imr->implicit_children); 456 ret = __xa_cmpxchg(&imr->implicit_children, idx, NULL, mr, 457 GFP_KERNEL); 458 if (unlikely(ret)) { 459 if (xa_is_err(ret)) { 460 ret = ERR_PTR(xa_err(ret)); 461 goto out_lock; 462 } 463 /* 464 * Another thread beat us to creating the child mr, use 465 * theirs. 466 */ 467 refcount_inc(&ret->mmkey.usecount); 468 goto out_lock; 469 } 470 xa_unlock(&imr->implicit_children); 471 472 mlx5_ib_dbg(mr_to_mdev(imr), "key %x mr %p\n", mr->mmkey.key, mr); 473 return mr; 474 475 out_lock: 476 xa_unlock(&imr->implicit_children); 477 out_mr: 478 mlx5_ib_dereg_mr(&mr->ibmr, NULL); 479 return ret; 480 } 481 482 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 483 int access_flags) 484 { 485 struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device); 486 struct ib_umem_odp *umem_odp; 487 struct mlx5_ib_mr *imr; 488 int err; 489 490 if (!mlx5_ib_can_load_pas_with_umr(dev, 491 MLX5_IMR_MTT_ENTRIES * PAGE_SIZE)) 492 return ERR_PTR(-EOPNOTSUPP); 493 494 umem_odp = ib_umem_odp_alloc_implicit(&dev->ib_dev, access_flags); 495 if (IS_ERR(umem_odp)) 496 return ERR_CAST(umem_odp); 497 498 imr = mlx5_mr_cache_alloc(dev, 499 &dev->cache.ent[MLX5_IMR_KSM_CACHE_ENTRY], 500 access_flags); 501 if (IS_ERR(imr)) { 502 ib_umem_odp_release(umem_odp); 503 return imr; 504 } 505 506 imr->access_flags = access_flags; 507 imr->ibmr.pd = &pd->ibpd; 508 imr->ibmr.iova = 0; 509 imr->umem = &umem_odp->umem; 510 imr->ibmr.lkey = imr->mmkey.key; 511 imr->ibmr.rkey = imr->mmkey.key; 512 imr->ibmr.device = &dev->ib_dev; 513 imr->umem = &umem_odp->umem; 514 imr->is_odp_implicit = true; 515 xa_init(&imr->implicit_children); 516 517 err = mlx5_ib_update_xlt(imr, 0, 518 mlx5_imr_ksm_entries, 519 MLX5_KSM_PAGE_SHIFT, 520 MLX5_IB_UPD_XLT_INDIRECT | 521 MLX5_IB_UPD_XLT_ZAP | 522 MLX5_IB_UPD_XLT_ENABLE); 523 if (err) 524 goto out_mr; 525 526 err = mlx5r_store_odp_mkey(dev, &imr->mmkey); 527 if (err) 528 goto out_mr; 529 530 mlx5_ib_dbg(dev, "key %x mr %p\n", imr->mmkey.key, imr); 531 return imr; 532 out_mr: 533 mlx5_ib_err(dev, "Failed to register MKEY %d\n", err); 534 mlx5_ib_dereg_mr(&imr->ibmr, NULL); 535 return ERR_PTR(err); 536 } 537 538 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr) 539 { 540 struct mlx5_ib_mr *mtt; 541 unsigned long idx; 542 543 /* 544 * If this is an implicit MR it is already invalidated so we can just 545 * delete the children mkeys. 546 */ 547 xa_for_each(&mr->implicit_children, idx, mtt) { 548 xa_erase(&mr->implicit_children, idx); 549 mlx5_ib_dereg_mr(&mtt->ibmr, NULL); 550 } 551 } 552 553 #define MLX5_PF_FLAGS_DOWNGRADE BIT(1) 554 #define MLX5_PF_FLAGS_SNAPSHOT BIT(2) 555 #define MLX5_PF_FLAGS_ENABLE BIT(3) 556 static int pagefault_real_mr(struct mlx5_ib_mr *mr, struct ib_umem_odp *odp, 557 u64 user_va, size_t bcnt, u32 *bytes_mapped, 558 u32 flags) 559 { 560 int page_shift, ret, np; 561 bool downgrade = flags & MLX5_PF_FLAGS_DOWNGRADE; 562 u64 access_mask; 563 u64 start_idx; 564 bool fault = !(flags & MLX5_PF_FLAGS_SNAPSHOT); 565 u32 xlt_flags = MLX5_IB_UPD_XLT_ATOMIC; 566 567 if (flags & MLX5_PF_FLAGS_ENABLE) 568 xlt_flags |= MLX5_IB_UPD_XLT_ENABLE; 569 570 page_shift = odp->page_shift; 571 start_idx = (user_va - ib_umem_start(odp)) >> page_shift; 572 access_mask = ODP_READ_ALLOWED_BIT; 573 574 if (odp->umem.writable && !downgrade) 575 access_mask |= ODP_WRITE_ALLOWED_BIT; 576 577 np = ib_umem_odp_map_dma_and_lock(odp, user_va, bcnt, access_mask, fault); 578 if (np < 0) 579 return np; 580 581 /* 582 * No need to check whether the MTTs really belong to this MR, since 583 * ib_umem_odp_map_dma_and_lock already checks this. 584 */ 585 ret = mlx5_ib_update_xlt(mr, start_idx, np, page_shift, xlt_flags); 586 mutex_unlock(&odp->umem_mutex); 587 588 if (ret < 0) { 589 if (ret != -EAGAIN) 590 mlx5_ib_err(mr_to_mdev(mr), 591 "Failed to update mkey page tables\n"); 592 goto out; 593 } 594 595 if (bytes_mapped) { 596 u32 new_mappings = (np << page_shift) - 597 (user_va - round_down(user_va, 1 << page_shift)); 598 599 *bytes_mapped += min_t(u32, new_mappings, bcnt); 600 } 601 602 return np << (page_shift - PAGE_SHIFT); 603 604 out: 605 return ret; 606 } 607 608 static int pagefault_implicit_mr(struct mlx5_ib_mr *imr, 609 struct ib_umem_odp *odp_imr, u64 user_va, 610 size_t bcnt, u32 *bytes_mapped, u32 flags) 611 { 612 unsigned long end_idx = (user_va + bcnt - 1) >> MLX5_IMR_MTT_SHIFT; 613 unsigned long upd_start_idx = end_idx + 1; 614 unsigned long upd_len = 0; 615 unsigned long npages = 0; 616 int err; 617 int ret; 618 619 if (unlikely(user_va >= mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE || 620 mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE - user_va < bcnt)) 621 return -EFAULT; 622 623 /* Fault each child mr that intersects with our interval. */ 624 while (bcnt) { 625 unsigned long idx = user_va >> MLX5_IMR_MTT_SHIFT; 626 struct ib_umem_odp *umem_odp; 627 struct mlx5_ib_mr *mtt; 628 u64 len; 629 630 xa_lock(&imr->implicit_children); 631 mtt = xa_load(&imr->implicit_children, idx); 632 if (unlikely(!mtt)) { 633 xa_unlock(&imr->implicit_children); 634 mtt = implicit_get_child_mr(imr, idx); 635 if (IS_ERR(mtt)) { 636 ret = PTR_ERR(mtt); 637 goto out; 638 } 639 upd_start_idx = min(upd_start_idx, idx); 640 upd_len = idx - upd_start_idx + 1; 641 } else { 642 refcount_inc(&mtt->mmkey.usecount); 643 xa_unlock(&imr->implicit_children); 644 } 645 646 umem_odp = to_ib_umem_odp(mtt->umem); 647 len = min_t(u64, user_va + bcnt, ib_umem_end(umem_odp)) - 648 user_va; 649 650 ret = pagefault_real_mr(mtt, umem_odp, user_va, len, 651 bytes_mapped, flags); 652 653 mlx5r_deref_odp_mkey(&mtt->mmkey); 654 655 if (ret < 0) 656 goto out; 657 user_va += len; 658 bcnt -= len; 659 npages += ret; 660 } 661 662 ret = npages; 663 664 /* 665 * Any time the implicit_children are changed we must perform an 666 * update of the xlt before exiting to ensure the HW and the 667 * implicit_children remains synchronized. 668 */ 669 out: 670 if (likely(!upd_len)) 671 return ret; 672 673 /* 674 * Notice this is not strictly ordered right, the KSM is updated after 675 * the implicit_children is updated, so a parallel page fault could 676 * see a MR that is not yet visible in the KSM. This is similar to a 677 * parallel page fault seeing a MR that is being concurrently removed 678 * from the KSM. Both of these improbable situations are resolved 679 * safely by resuming the HW and then taking another page fault. The 680 * next pagefault handler will see the new information. 681 */ 682 mutex_lock(&odp_imr->umem_mutex); 683 err = mlx5_ib_update_xlt(imr, upd_start_idx, upd_len, 0, 684 MLX5_IB_UPD_XLT_INDIRECT | 685 MLX5_IB_UPD_XLT_ATOMIC); 686 mutex_unlock(&odp_imr->umem_mutex); 687 if (err) { 688 mlx5_ib_err(mr_to_mdev(imr), "Failed to update PAS\n"); 689 return err; 690 } 691 return ret; 692 } 693 694 static int pagefault_dmabuf_mr(struct mlx5_ib_mr *mr, size_t bcnt, 695 u32 *bytes_mapped, u32 flags) 696 { 697 struct ib_umem_dmabuf *umem_dmabuf = to_ib_umem_dmabuf(mr->umem); 698 u32 xlt_flags = 0; 699 int err; 700 unsigned int page_size; 701 702 if (flags & MLX5_PF_FLAGS_ENABLE) 703 xlt_flags |= MLX5_IB_UPD_XLT_ENABLE; 704 705 dma_resv_lock(umem_dmabuf->attach->dmabuf->resv, NULL); 706 err = ib_umem_dmabuf_map_pages(umem_dmabuf); 707 if (err) { 708 dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv); 709 return err; 710 } 711 712 page_size = mlx5_umem_find_best_pgsz(&umem_dmabuf->umem, mkc, 713 log_page_size, 0, 714 umem_dmabuf->umem.iova); 715 if (unlikely(page_size < PAGE_SIZE)) { 716 ib_umem_dmabuf_unmap_pages(umem_dmabuf); 717 err = -EINVAL; 718 } else { 719 err = mlx5_ib_update_mr_pas(mr, xlt_flags); 720 } 721 dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv); 722 723 if (err) 724 return err; 725 726 if (bytes_mapped) 727 *bytes_mapped += bcnt; 728 729 return ib_umem_num_pages(mr->umem); 730 } 731 732 /* 733 * Returns: 734 * -EFAULT: The io_virt->bcnt is not within the MR, it covers pages that are 735 * not accessible, or the MR is no longer valid. 736 * -EAGAIN/-ENOMEM: The operation should be retried 737 * 738 * -EINVAL/others: General internal malfunction 739 * >0: Number of pages mapped 740 */ 741 static int pagefault_mr(struct mlx5_ib_mr *mr, u64 io_virt, size_t bcnt, 742 u32 *bytes_mapped, u32 flags) 743 { 744 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 745 746 if (unlikely(io_virt < mr->ibmr.iova)) 747 return -EFAULT; 748 749 if (mr->umem->is_dmabuf) 750 return pagefault_dmabuf_mr(mr, bcnt, bytes_mapped, flags); 751 752 if (!odp->is_implicit_odp) { 753 u64 user_va; 754 755 if (check_add_overflow(io_virt - mr->ibmr.iova, 756 (u64)odp->umem.address, &user_va)) 757 return -EFAULT; 758 if (unlikely(user_va >= ib_umem_end(odp) || 759 ib_umem_end(odp) - user_va < bcnt)) 760 return -EFAULT; 761 return pagefault_real_mr(mr, odp, user_va, bcnt, bytes_mapped, 762 flags); 763 } 764 return pagefault_implicit_mr(mr, odp, io_virt, bcnt, bytes_mapped, 765 flags); 766 } 767 768 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 769 { 770 int ret; 771 772 ret = pagefault_real_mr(mr, to_ib_umem_odp(mr->umem), mr->umem->address, 773 mr->umem->length, NULL, 774 MLX5_PF_FLAGS_SNAPSHOT | MLX5_PF_FLAGS_ENABLE); 775 return ret >= 0 ? 0 : ret; 776 } 777 778 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 779 { 780 int ret; 781 782 ret = pagefault_dmabuf_mr(mr, mr->umem->length, NULL, 783 MLX5_PF_FLAGS_ENABLE); 784 785 return ret >= 0 ? 0 : ret; 786 } 787 788 struct pf_frame { 789 struct pf_frame *next; 790 u32 key; 791 u64 io_virt; 792 size_t bcnt; 793 int depth; 794 }; 795 796 static bool mkey_is_eq(struct mlx5_ib_mkey *mmkey, u32 key) 797 { 798 if (!mmkey) 799 return false; 800 if (mmkey->type == MLX5_MKEY_MW) 801 return mlx5_base_mkey(mmkey->key) == mlx5_base_mkey(key); 802 return mmkey->key == key; 803 } 804 805 /* 806 * Handle a single data segment in a page-fault WQE or RDMA region. 807 * 808 * Returns number of OS pages retrieved on success. The caller may continue to 809 * the next data segment. 810 * Can return the following error codes: 811 * -EAGAIN to designate a temporary error. The caller will abort handling the 812 * page fault and resolve it. 813 * -EFAULT when there's an error mapping the requested pages. The caller will 814 * abort the page fault handling. 815 */ 816 static int pagefault_single_data_segment(struct mlx5_ib_dev *dev, 817 struct ib_pd *pd, u32 key, 818 u64 io_virt, size_t bcnt, 819 u32 *bytes_committed, 820 u32 *bytes_mapped) 821 { 822 int npages = 0, ret, i, outlen, cur_outlen = 0, depth = 0; 823 struct pf_frame *head = NULL, *frame; 824 struct mlx5_ib_mkey *mmkey; 825 struct mlx5_ib_mr *mr; 826 struct mlx5_klm *pklm; 827 u32 *out = NULL; 828 size_t offset; 829 830 io_virt += *bytes_committed; 831 bcnt -= *bytes_committed; 832 833 next_mr: 834 xa_lock(&dev->odp_mkeys); 835 mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(key)); 836 if (!mmkey) { 837 xa_unlock(&dev->odp_mkeys); 838 mlx5_ib_dbg( 839 dev, 840 "skipping non ODP MR (lkey=0x%06x) in page fault handler.\n", 841 key); 842 if (bytes_mapped) 843 *bytes_mapped += bcnt; 844 /* 845 * The user could specify a SGL with multiple lkeys and only 846 * some of them are ODP. Treat the non-ODP ones as fully 847 * faulted. 848 */ 849 ret = 0; 850 goto end; 851 } 852 refcount_inc(&mmkey->usecount); 853 xa_unlock(&dev->odp_mkeys); 854 855 if (!mkey_is_eq(mmkey, key)) { 856 mlx5_ib_dbg(dev, "failed to find mkey %x\n", key); 857 ret = -EFAULT; 858 goto end; 859 } 860 861 switch (mmkey->type) { 862 case MLX5_MKEY_MR: 863 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey); 864 865 ret = pagefault_mr(mr, io_virt, bcnt, bytes_mapped, 0); 866 if (ret < 0) 867 goto end; 868 869 mlx5_update_odp_stats(mr, faults, ret); 870 871 npages += ret; 872 ret = 0; 873 break; 874 875 case MLX5_MKEY_MW: 876 case MLX5_MKEY_INDIRECT_DEVX: 877 if (depth >= MLX5_CAP_GEN(dev->mdev, max_indirection)) { 878 mlx5_ib_dbg(dev, "indirection level exceeded\n"); 879 ret = -EFAULT; 880 goto end; 881 } 882 883 outlen = MLX5_ST_SZ_BYTES(query_mkey_out) + 884 sizeof(*pklm) * (mmkey->ndescs - 2); 885 886 if (outlen > cur_outlen) { 887 kfree(out); 888 out = kzalloc(outlen, GFP_KERNEL); 889 if (!out) { 890 ret = -ENOMEM; 891 goto end; 892 } 893 cur_outlen = outlen; 894 } 895 896 pklm = (struct mlx5_klm *)MLX5_ADDR_OF(query_mkey_out, out, 897 bsf0_klm0_pas_mtt0_1); 898 899 ret = mlx5_core_query_mkey(dev->mdev, mmkey->key, out, outlen); 900 if (ret) 901 goto end; 902 903 offset = io_virt - MLX5_GET64(query_mkey_out, out, 904 memory_key_mkey_entry.start_addr); 905 906 for (i = 0; bcnt && i < mmkey->ndescs; i++, pklm++) { 907 if (offset >= be32_to_cpu(pklm->bcount)) { 908 offset -= be32_to_cpu(pklm->bcount); 909 continue; 910 } 911 912 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 913 if (!frame) { 914 ret = -ENOMEM; 915 goto end; 916 } 917 918 frame->key = be32_to_cpu(pklm->key); 919 frame->io_virt = be64_to_cpu(pklm->va) + offset; 920 frame->bcnt = min_t(size_t, bcnt, 921 be32_to_cpu(pklm->bcount) - offset); 922 frame->depth = depth + 1; 923 frame->next = head; 924 head = frame; 925 926 bcnt -= frame->bcnt; 927 offset = 0; 928 } 929 break; 930 931 default: 932 mlx5_ib_dbg(dev, "wrong mkey type %d\n", mmkey->type); 933 ret = -EFAULT; 934 goto end; 935 } 936 937 if (head) { 938 frame = head; 939 head = frame->next; 940 941 key = frame->key; 942 io_virt = frame->io_virt; 943 bcnt = frame->bcnt; 944 depth = frame->depth; 945 kfree(frame); 946 947 mlx5r_deref_odp_mkey(mmkey); 948 goto next_mr; 949 } 950 951 end: 952 if (mmkey) 953 mlx5r_deref_odp_mkey(mmkey); 954 while (head) { 955 frame = head; 956 head = frame->next; 957 kfree(frame); 958 } 959 kfree(out); 960 961 *bytes_committed = 0; 962 return ret ? ret : npages; 963 } 964 965 /* 966 * Parse a series of data segments for page fault handling. 967 * 968 * @dev: Pointer to mlx5 IB device 969 * @pfault: contains page fault information. 970 * @wqe: points at the first data segment in the WQE. 971 * @wqe_end: points after the end of the WQE. 972 * @bytes_mapped: receives the number of bytes that the function was able to 973 * map. This allows the caller to decide intelligently whether 974 * enough memory was mapped to resolve the page fault 975 * successfully (e.g. enough for the next MTU, or the entire 976 * WQE). 977 * @total_wqe_bytes: receives the total data size of this WQE in bytes (minus 978 * the committed bytes). 979 * @receive_queue: receive WQE end of sg list 980 * 981 * Returns the number of pages loaded if positive, zero for an empty WQE, or a 982 * negative error code. 983 */ 984 static int pagefault_data_segments(struct mlx5_ib_dev *dev, 985 struct mlx5_pagefault *pfault, 986 void *wqe, 987 void *wqe_end, u32 *bytes_mapped, 988 u32 *total_wqe_bytes, bool receive_queue) 989 { 990 int ret = 0, npages = 0; 991 u64 io_virt; 992 u32 key; 993 u32 byte_count; 994 size_t bcnt; 995 int inline_segment; 996 997 if (bytes_mapped) 998 *bytes_mapped = 0; 999 if (total_wqe_bytes) 1000 *total_wqe_bytes = 0; 1001 1002 while (wqe < wqe_end) { 1003 struct mlx5_wqe_data_seg *dseg = wqe; 1004 1005 io_virt = be64_to_cpu(dseg->addr); 1006 key = be32_to_cpu(dseg->lkey); 1007 byte_count = be32_to_cpu(dseg->byte_count); 1008 inline_segment = !!(byte_count & MLX5_INLINE_SEG); 1009 bcnt = byte_count & ~MLX5_INLINE_SEG; 1010 1011 if (inline_segment) { 1012 bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK; 1013 wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt, 1014 16); 1015 } else { 1016 wqe += sizeof(*dseg); 1017 } 1018 1019 /* receive WQE end of sg list. */ 1020 if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY && 1021 io_virt == 0) 1022 break; 1023 1024 if (!inline_segment && total_wqe_bytes) { 1025 *total_wqe_bytes += bcnt - min_t(size_t, bcnt, 1026 pfault->bytes_committed); 1027 } 1028 1029 /* A zero length data segment designates a length of 2GB. */ 1030 if (bcnt == 0) 1031 bcnt = 1U << 31; 1032 1033 if (inline_segment || bcnt <= pfault->bytes_committed) { 1034 pfault->bytes_committed -= 1035 min_t(size_t, bcnt, 1036 pfault->bytes_committed); 1037 continue; 1038 } 1039 1040 ret = pagefault_single_data_segment(dev, NULL, key, 1041 io_virt, bcnt, 1042 &pfault->bytes_committed, 1043 bytes_mapped); 1044 if (ret < 0) 1045 break; 1046 npages += ret; 1047 } 1048 1049 return ret < 0 ? ret : npages; 1050 } 1051 1052 /* 1053 * Parse initiator WQE. Advances the wqe pointer to point at the 1054 * scatter-gather list, and set wqe_end to the end of the WQE. 1055 */ 1056 static int mlx5_ib_mr_initiator_pfault_handler( 1057 struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault, 1058 struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length) 1059 { 1060 struct mlx5_wqe_ctrl_seg *ctrl = *wqe; 1061 u16 wqe_index = pfault->wqe.wqe_index; 1062 struct mlx5_base_av *av; 1063 unsigned ds, opcode; 1064 u32 qpn = qp->trans_qp.base.mqp.qpn; 1065 1066 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 1067 if (ds * MLX5_WQE_DS_UNITS > wqe_length) { 1068 mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n", 1069 ds, wqe_length); 1070 return -EFAULT; 1071 } 1072 1073 if (ds == 0) { 1074 mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n", 1075 wqe_index, qpn); 1076 return -EFAULT; 1077 } 1078 1079 *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS; 1080 *wqe += sizeof(*ctrl); 1081 1082 opcode = be32_to_cpu(ctrl->opmod_idx_opcode) & 1083 MLX5_WQE_CTRL_OPCODE_MASK; 1084 1085 if (qp->type == IB_QPT_XRC_INI) 1086 *wqe += sizeof(struct mlx5_wqe_xrc_seg); 1087 1088 if (qp->type == IB_QPT_UD || qp->type == MLX5_IB_QPT_DCI) { 1089 av = *wqe; 1090 if (av->dqp_dct & cpu_to_be32(MLX5_EXTENDED_UD_AV)) 1091 *wqe += sizeof(struct mlx5_av); 1092 else 1093 *wqe += sizeof(struct mlx5_base_av); 1094 } 1095 1096 switch (opcode) { 1097 case MLX5_OPCODE_RDMA_WRITE: 1098 case MLX5_OPCODE_RDMA_WRITE_IMM: 1099 case MLX5_OPCODE_RDMA_READ: 1100 *wqe += sizeof(struct mlx5_wqe_raddr_seg); 1101 break; 1102 case MLX5_OPCODE_ATOMIC_CS: 1103 case MLX5_OPCODE_ATOMIC_FA: 1104 *wqe += sizeof(struct mlx5_wqe_raddr_seg); 1105 *wqe += sizeof(struct mlx5_wqe_atomic_seg); 1106 break; 1107 } 1108 1109 return 0; 1110 } 1111 1112 /* 1113 * Parse responder WQE and set wqe_end to the end of the WQE. 1114 */ 1115 static int mlx5_ib_mr_responder_pfault_handler_srq(struct mlx5_ib_dev *dev, 1116 struct mlx5_ib_srq *srq, 1117 void **wqe, void **wqe_end, 1118 int wqe_length) 1119 { 1120 int wqe_size = 1 << srq->msrq.wqe_shift; 1121 1122 if (wqe_size > wqe_length) { 1123 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n"); 1124 return -EFAULT; 1125 } 1126 1127 *wqe_end = *wqe + wqe_size; 1128 *wqe += sizeof(struct mlx5_wqe_srq_next_seg); 1129 1130 return 0; 1131 } 1132 1133 static int mlx5_ib_mr_responder_pfault_handler_rq(struct mlx5_ib_dev *dev, 1134 struct mlx5_ib_qp *qp, 1135 void *wqe, void **wqe_end, 1136 int wqe_length) 1137 { 1138 struct mlx5_ib_wq *wq = &qp->rq; 1139 int wqe_size = 1 << wq->wqe_shift; 1140 1141 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) { 1142 mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n"); 1143 return -EFAULT; 1144 } 1145 1146 if (wqe_size > wqe_length) { 1147 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n"); 1148 return -EFAULT; 1149 } 1150 1151 *wqe_end = wqe + wqe_size; 1152 1153 return 0; 1154 } 1155 1156 static inline struct mlx5_core_rsc_common *odp_get_rsc(struct mlx5_ib_dev *dev, 1157 u32 wq_num, int pf_type) 1158 { 1159 struct mlx5_core_rsc_common *common = NULL; 1160 struct mlx5_core_srq *srq; 1161 1162 switch (pf_type) { 1163 case MLX5_WQE_PF_TYPE_RMP: 1164 srq = mlx5_cmd_get_srq(dev, wq_num); 1165 if (srq) 1166 common = &srq->common; 1167 break; 1168 case MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE: 1169 case MLX5_WQE_PF_TYPE_RESP: 1170 case MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC: 1171 common = mlx5_core_res_hold(dev, wq_num, MLX5_RES_QP); 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 return common; 1178 } 1179 1180 static inline struct mlx5_ib_qp *res_to_qp(struct mlx5_core_rsc_common *res) 1181 { 1182 struct mlx5_core_qp *mqp = (struct mlx5_core_qp *)res; 1183 1184 return to_mibqp(mqp); 1185 } 1186 1187 static inline struct mlx5_ib_srq *res_to_srq(struct mlx5_core_rsc_common *res) 1188 { 1189 struct mlx5_core_srq *msrq = 1190 container_of(res, struct mlx5_core_srq, common); 1191 1192 return to_mibsrq(msrq); 1193 } 1194 1195 static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev *dev, 1196 struct mlx5_pagefault *pfault) 1197 { 1198 bool sq = pfault->type & MLX5_PFAULT_REQUESTOR; 1199 u16 wqe_index = pfault->wqe.wqe_index; 1200 void *wqe, *wqe_start = NULL, *wqe_end = NULL; 1201 u32 bytes_mapped, total_wqe_bytes; 1202 struct mlx5_core_rsc_common *res; 1203 int resume_with_error = 1; 1204 struct mlx5_ib_qp *qp; 1205 size_t bytes_copied; 1206 int ret = 0; 1207 1208 res = odp_get_rsc(dev, pfault->wqe.wq_num, pfault->type); 1209 if (!res) { 1210 mlx5_ib_dbg(dev, "wqe page fault for missing resource %d\n", pfault->wqe.wq_num); 1211 return; 1212 } 1213 1214 if (res->res != MLX5_RES_QP && res->res != MLX5_RES_SRQ && 1215 res->res != MLX5_RES_XSRQ) { 1216 mlx5_ib_err(dev, "wqe page fault for unsupported type %d\n", 1217 pfault->type); 1218 goto resolve_page_fault; 1219 } 1220 1221 wqe_start = (void *)__get_free_page(GFP_KERNEL); 1222 if (!wqe_start) { 1223 mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n"); 1224 goto resolve_page_fault; 1225 } 1226 1227 wqe = wqe_start; 1228 qp = (res->res == MLX5_RES_QP) ? res_to_qp(res) : NULL; 1229 if (qp && sq) { 1230 ret = mlx5_ib_read_wqe_sq(qp, wqe_index, wqe, PAGE_SIZE, 1231 &bytes_copied); 1232 if (ret) 1233 goto read_user; 1234 ret = mlx5_ib_mr_initiator_pfault_handler( 1235 dev, pfault, qp, &wqe, &wqe_end, bytes_copied); 1236 } else if (qp && !sq) { 1237 ret = mlx5_ib_read_wqe_rq(qp, wqe_index, wqe, PAGE_SIZE, 1238 &bytes_copied); 1239 if (ret) 1240 goto read_user; 1241 ret = mlx5_ib_mr_responder_pfault_handler_rq( 1242 dev, qp, wqe, &wqe_end, bytes_copied); 1243 } else if (!qp) { 1244 struct mlx5_ib_srq *srq = res_to_srq(res); 1245 1246 ret = mlx5_ib_read_wqe_srq(srq, wqe_index, wqe, PAGE_SIZE, 1247 &bytes_copied); 1248 if (ret) 1249 goto read_user; 1250 ret = mlx5_ib_mr_responder_pfault_handler_srq( 1251 dev, srq, &wqe, &wqe_end, bytes_copied); 1252 } 1253 1254 if (ret < 0 || wqe >= wqe_end) 1255 goto resolve_page_fault; 1256 1257 ret = pagefault_data_segments(dev, pfault, wqe, wqe_end, &bytes_mapped, 1258 &total_wqe_bytes, !sq); 1259 if (ret == -EAGAIN) 1260 goto out; 1261 1262 if (ret < 0 || total_wqe_bytes > bytes_mapped) 1263 goto resolve_page_fault; 1264 1265 out: 1266 ret = 0; 1267 resume_with_error = 0; 1268 1269 read_user: 1270 if (ret) 1271 mlx5_ib_err( 1272 dev, 1273 "Failed reading a WQE following page fault, error %d, wqe_index %x, qpn %x\n", 1274 ret, wqe_index, pfault->token); 1275 1276 resolve_page_fault: 1277 mlx5_ib_page_fault_resume(dev, pfault, resume_with_error); 1278 mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, type: 0x%x\n", 1279 pfault->wqe.wq_num, resume_with_error, 1280 pfault->type); 1281 mlx5_core_res_put(res); 1282 free_page((unsigned long)wqe_start); 1283 } 1284 1285 static int pages_in_range(u64 address, u32 length) 1286 { 1287 return (ALIGN(address + length, PAGE_SIZE) - 1288 (address & PAGE_MASK)) >> PAGE_SHIFT; 1289 } 1290 1291 static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev, 1292 struct mlx5_pagefault *pfault) 1293 { 1294 u64 address; 1295 u32 length; 1296 u32 prefetch_len = pfault->bytes_committed; 1297 int prefetch_activated = 0; 1298 u32 rkey = pfault->rdma.r_key; 1299 int ret; 1300 1301 /* The RDMA responder handler handles the page fault in two parts. 1302 * First it brings the necessary pages for the current packet 1303 * (and uses the pfault context), and then (after resuming the QP) 1304 * prefetches more pages. The second operation cannot use the pfault 1305 * context and therefore uses the dummy_pfault context allocated on 1306 * the stack */ 1307 pfault->rdma.rdma_va += pfault->bytes_committed; 1308 pfault->rdma.rdma_op_len -= min(pfault->bytes_committed, 1309 pfault->rdma.rdma_op_len); 1310 pfault->bytes_committed = 0; 1311 1312 address = pfault->rdma.rdma_va; 1313 length = pfault->rdma.rdma_op_len; 1314 1315 /* For some operations, the hardware cannot tell the exact message 1316 * length, and in those cases it reports zero. Use prefetch 1317 * logic. */ 1318 if (length == 0) { 1319 prefetch_activated = 1; 1320 length = pfault->rdma.packet_size; 1321 prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len); 1322 } 1323 1324 ret = pagefault_single_data_segment(dev, NULL, rkey, address, length, 1325 &pfault->bytes_committed, NULL); 1326 if (ret == -EAGAIN) { 1327 /* We're racing with an invalidation, don't prefetch */ 1328 prefetch_activated = 0; 1329 } else if (ret < 0 || pages_in_range(address, length) > ret) { 1330 mlx5_ib_page_fault_resume(dev, pfault, 1); 1331 if (ret != -ENOENT) 1332 mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n", 1333 ret, pfault->token, pfault->type); 1334 return; 1335 } 1336 1337 mlx5_ib_page_fault_resume(dev, pfault, 0); 1338 mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x, type: 0x%x, prefetch_activated: %d\n", 1339 pfault->token, pfault->type, 1340 prefetch_activated); 1341 1342 /* At this point, there might be a new pagefault already arriving in 1343 * the eq, switch to the dummy pagefault for the rest of the 1344 * processing. We're still OK with the objects being alive as the 1345 * work-queue is being fenced. */ 1346 1347 if (prefetch_activated) { 1348 u32 bytes_committed = 0; 1349 1350 ret = pagefault_single_data_segment(dev, NULL, rkey, address, 1351 prefetch_len, 1352 &bytes_committed, NULL); 1353 if (ret < 0 && ret != -EAGAIN) { 1354 mlx5_ib_dbg(dev, "Prefetch failed. ret: %d, QP 0x%x, address: 0x%.16llx, length = 0x%.16x\n", 1355 ret, pfault->token, address, prefetch_len); 1356 } 1357 } 1358 } 1359 1360 static void mlx5_ib_pfault(struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault) 1361 { 1362 u8 event_subtype = pfault->event_subtype; 1363 1364 switch (event_subtype) { 1365 case MLX5_PFAULT_SUBTYPE_WQE: 1366 mlx5_ib_mr_wqe_pfault_handler(dev, pfault); 1367 break; 1368 case MLX5_PFAULT_SUBTYPE_RDMA: 1369 mlx5_ib_mr_rdma_pfault_handler(dev, pfault); 1370 break; 1371 default: 1372 mlx5_ib_err(dev, "Invalid page fault event subtype: 0x%x\n", 1373 event_subtype); 1374 mlx5_ib_page_fault_resume(dev, pfault, 1); 1375 } 1376 } 1377 1378 static void mlx5_ib_eqe_pf_action(struct work_struct *work) 1379 { 1380 struct mlx5_pagefault *pfault = container_of(work, 1381 struct mlx5_pagefault, 1382 work); 1383 struct mlx5_ib_pf_eq *eq = pfault->eq; 1384 1385 mlx5_ib_pfault(eq->dev, pfault); 1386 mempool_free(pfault, eq->pool); 1387 } 1388 1389 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq) 1390 { 1391 struct mlx5_eqe_page_fault *pf_eqe; 1392 struct mlx5_pagefault *pfault; 1393 struct mlx5_eqe *eqe; 1394 int cc = 0; 1395 1396 while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) { 1397 pfault = mempool_alloc(eq->pool, GFP_ATOMIC); 1398 if (!pfault) { 1399 schedule_work(&eq->work); 1400 break; 1401 } 1402 1403 pf_eqe = &eqe->data.page_fault; 1404 pfault->event_subtype = eqe->sub_type; 1405 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed); 1406 1407 mlx5_ib_dbg(eq->dev, 1408 "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n", 1409 eqe->sub_type, pfault->bytes_committed); 1410 1411 switch (eqe->sub_type) { 1412 case MLX5_PFAULT_SUBTYPE_RDMA: 1413 /* RDMA based event */ 1414 pfault->type = 1415 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24; 1416 pfault->token = 1417 be32_to_cpu(pf_eqe->rdma.pftype_token) & 1418 MLX5_24BIT_MASK; 1419 pfault->rdma.r_key = 1420 be32_to_cpu(pf_eqe->rdma.r_key); 1421 pfault->rdma.packet_size = 1422 be16_to_cpu(pf_eqe->rdma.packet_length); 1423 pfault->rdma.rdma_op_len = 1424 be32_to_cpu(pf_eqe->rdma.rdma_op_len); 1425 pfault->rdma.rdma_va = 1426 be64_to_cpu(pf_eqe->rdma.rdma_va); 1427 mlx5_ib_dbg(eq->dev, 1428 "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n", 1429 pfault->type, pfault->token, 1430 pfault->rdma.r_key); 1431 mlx5_ib_dbg(eq->dev, 1432 "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n", 1433 pfault->rdma.rdma_op_len, 1434 pfault->rdma.rdma_va); 1435 break; 1436 1437 case MLX5_PFAULT_SUBTYPE_WQE: 1438 /* WQE based event */ 1439 pfault->type = 1440 (be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24) & 0x7; 1441 pfault->token = 1442 be32_to_cpu(pf_eqe->wqe.token); 1443 pfault->wqe.wq_num = 1444 be32_to_cpu(pf_eqe->wqe.pftype_wq) & 1445 MLX5_24BIT_MASK; 1446 pfault->wqe.wqe_index = 1447 be16_to_cpu(pf_eqe->wqe.wqe_index); 1448 pfault->wqe.packet_size = 1449 be16_to_cpu(pf_eqe->wqe.packet_length); 1450 mlx5_ib_dbg(eq->dev, 1451 "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n", 1452 pfault->type, pfault->token, 1453 pfault->wqe.wq_num, 1454 pfault->wqe.wqe_index); 1455 break; 1456 1457 default: 1458 mlx5_ib_warn(eq->dev, 1459 "Unsupported page fault event sub-type: 0x%02hhx\n", 1460 eqe->sub_type); 1461 /* Unsupported page faults should still be 1462 * resolved by the page fault handler 1463 */ 1464 } 1465 1466 pfault->eq = eq; 1467 INIT_WORK(&pfault->work, mlx5_ib_eqe_pf_action); 1468 queue_work(eq->wq, &pfault->work); 1469 1470 cc = mlx5_eq_update_cc(eq->core, ++cc); 1471 } 1472 1473 mlx5_eq_update_ci(eq->core, cc, 1); 1474 } 1475 1476 static int mlx5_ib_eq_pf_int(struct notifier_block *nb, unsigned long type, 1477 void *data) 1478 { 1479 struct mlx5_ib_pf_eq *eq = 1480 container_of(nb, struct mlx5_ib_pf_eq, irq_nb); 1481 unsigned long flags; 1482 1483 if (spin_trylock_irqsave(&eq->lock, flags)) { 1484 mlx5_ib_eq_pf_process(eq); 1485 spin_unlock_irqrestore(&eq->lock, flags); 1486 } else { 1487 schedule_work(&eq->work); 1488 } 1489 1490 return IRQ_HANDLED; 1491 } 1492 1493 /* mempool_refill() was proposed but unfortunately wasn't accepted 1494 * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html 1495 * Cheap workaround. 1496 */ 1497 static void mempool_refill(mempool_t *pool) 1498 { 1499 while (pool->curr_nr < pool->min_nr) 1500 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool); 1501 } 1502 1503 static void mlx5_ib_eq_pf_action(struct work_struct *work) 1504 { 1505 struct mlx5_ib_pf_eq *eq = 1506 container_of(work, struct mlx5_ib_pf_eq, work); 1507 1508 mempool_refill(eq->pool); 1509 1510 spin_lock_irq(&eq->lock); 1511 mlx5_ib_eq_pf_process(eq); 1512 spin_unlock_irq(&eq->lock); 1513 } 1514 1515 enum { 1516 MLX5_IB_NUM_PF_EQE = 0x1000, 1517 MLX5_IB_NUM_PF_DRAIN = 64, 1518 }; 1519 1520 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq) 1521 { 1522 struct mlx5_eq_param param = {}; 1523 int err = 0; 1524 1525 mutex_lock(&dev->odp_eq_mutex); 1526 if (eq->core) 1527 goto unlock; 1528 INIT_WORK(&eq->work, mlx5_ib_eq_pf_action); 1529 spin_lock_init(&eq->lock); 1530 eq->dev = dev; 1531 1532 eq->pool = mempool_create_kmalloc_pool(MLX5_IB_NUM_PF_DRAIN, 1533 sizeof(struct mlx5_pagefault)); 1534 if (!eq->pool) { 1535 err = -ENOMEM; 1536 goto unlock; 1537 } 1538 1539 eq->wq = alloc_workqueue("mlx5_ib_page_fault", 1540 WQ_HIGHPRI | WQ_UNBOUND | WQ_MEM_RECLAIM, 1541 MLX5_NUM_CMD_EQE); 1542 if (!eq->wq) { 1543 err = -ENOMEM; 1544 goto err_mempool; 1545 } 1546 1547 eq->irq_nb.notifier_call = mlx5_ib_eq_pf_int; 1548 param = (struct mlx5_eq_param) { 1549 .nent = MLX5_IB_NUM_PF_EQE, 1550 }; 1551 param.mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_FAULT; 1552 eq->core = mlx5_eq_create_generic(dev->mdev, ¶m); 1553 if (IS_ERR(eq->core)) { 1554 err = PTR_ERR(eq->core); 1555 goto err_wq; 1556 } 1557 err = mlx5_eq_enable(dev->mdev, eq->core, &eq->irq_nb); 1558 if (err) { 1559 mlx5_ib_err(dev, "failed to enable odp EQ %d\n", err); 1560 goto err_eq; 1561 } 1562 1563 mutex_unlock(&dev->odp_eq_mutex); 1564 return 0; 1565 err_eq: 1566 mlx5_eq_destroy_generic(dev->mdev, eq->core); 1567 err_wq: 1568 eq->core = NULL; 1569 destroy_workqueue(eq->wq); 1570 err_mempool: 1571 mempool_destroy(eq->pool); 1572 unlock: 1573 mutex_unlock(&dev->odp_eq_mutex); 1574 return err; 1575 } 1576 1577 static int 1578 mlx5_ib_odp_destroy_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq) 1579 { 1580 int err; 1581 1582 if (!eq->core) 1583 return 0; 1584 mlx5_eq_disable(dev->mdev, eq->core, &eq->irq_nb); 1585 err = mlx5_eq_destroy_generic(dev->mdev, eq->core); 1586 cancel_work_sync(&eq->work); 1587 destroy_workqueue(eq->wq); 1588 mempool_destroy(eq->pool); 1589 1590 return err; 1591 } 1592 1593 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) 1594 { 1595 if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) 1596 return; 1597 1598 switch (ent->order - 2) { 1599 case MLX5_IMR_MTT_CACHE_ENTRY: 1600 ent->page = PAGE_SHIFT; 1601 ent->ndescs = MLX5_IMR_MTT_ENTRIES; 1602 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; 1603 ent->limit = 0; 1604 break; 1605 1606 case MLX5_IMR_KSM_CACHE_ENTRY: 1607 ent->page = MLX5_KSM_PAGE_SHIFT; 1608 ent->ndescs = mlx5_imr_ksm_entries; 1609 ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM; 1610 ent->limit = 0; 1611 break; 1612 } 1613 } 1614 1615 static const struct ib_device_ops mlx5_ib_dev_odp_ops = { 1616 .advise_mr = mlx5_ib_advise_mr, 1617 }; 1618 1619 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *dev) 1620 { 1621 int ret = 0; 1622 1623 internal_fill_odp_caps(dev); 1624 1625 if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT)) 1626 return ret; 1627 1628 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_odp_ops); 1629 1630 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT) { 1631 ret = mlx5_cmd_null_mkey(dev->mdev, &dev->null_mkey); 1632 if (ret) { 1633 mlx5_ib_err(dev, "Error getting null_mkey %d\n", ret); 1634 return ret; 1635 } 1636 } 1637 1638 mutex_init(&dev->odp_eq_mutex); 1639 return ret; 1640 } 1641 1642 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *dev) 1643 { 1644 if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT)) 1645 return; 1646 1647 mlx5_ib_odp_destroy_eq(dev, &dev->odp_pf_eq); 1648 } 1649 1650 int mlx5_ib_odp_init(void) 1651 { 1652 mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) - 1653 MLX5_IMR_MTT_BITS); 1654 1655 return 0; 1656 } 1657 1658 struct prefetch_mr_work { 1659 struct work_struct work; 1660 u32 pf_flags; 1661 u32 num_sge; 1662 struct { 1663 u64 io_virt; 1664 struct mlx5_ib_mr *mr; 1665 size_t length; 1666 } frags[]; 1667 }; 1668 1669 static void destroy_prefetch_work(struct prefetch_mr_work *work) 1670 { 1671 u32 i; 1672 1673 for (i = 0; i < work->num_sge; ++i) 1674 mlx5r_deref_odp_mkey(&work->frags[i].mr->mmkey); 1675 1676 kvfree(work); 1677 } 1678 1679 static struct mlx5_ib_mr * 1680 get_prefetchable_mr(struct ib_pd *pd, enum ib_uverbs_advise_mr_advice advice, 1681 u32 lkey) 1682 { 1683 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1684 struct mlx5_ib_mr *mr = NULL; 1685 struct mlx5_ib_mkey *mmkey; 1686 1687 xa_lock(&dev->odp_mkeys); 1688 mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(lkey)); 1689 if (!mmkey || mmkey->key != lkey) { 1690 mr = ERR_PTR(-ENOENT); 1691 goto end; 1692 } 1693 if (mmkey->type != MLX5_MKEY_MR) { 1694 mr = ERR_PTR(-EINVAL); 1695 goto end; 1696 } 1697 1698 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey); 1699 1700 if (mr->ibmr.pd != pd) { 1701 mr = ERR_PTR(-EPERM); 1702 goto end; 1703 } 1704 1705 /* prefetch with write-access must be supported by the MR */ 1706 if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE && 1707 !mr->umem->writable) { 1708 mr = ERR_PTR(-EPERM); 1709 goto end; 1710 } 1711 1712 refcount_inc(&mmkey->usecount); 1713 end: 1714 xa_unlock(&dev->odp_mkeys); 1715 return mr; 1716 } 1717 1718 static void mlx5_ib_prefetch_mr_work(struct work_struct *w) 1719 { 1720 struct prefetch_mr_work *work = 1721 container_of(w, struct prefetch_mr_work, work); 1722 u32 bytes_mapped = 0; 1723 int ret; 1724 u32 i; 1725 1726 /* We rely on IB/core that work is executed if we have num_sge != 0 only. */ 1727 WARN_ON(!work->num_sge); 1728 for (i = 0; i < work->num_sge; ++i) { 1729 ret = pagefault_mr(work->frags[i].mr, work->frags[i].io_virt, 1730 work->frags[i].length, &bytes_mapped, 1731 work->pf_flags); 1732 if (ret <= 0) 1733 continue; 1734 mlx5_update_odp_stats(work->frags[i].mr, prefetch, ret); 1735 } 1736 1737 destroy_prefetch_work(work); 1738 } 1739 1740 static int init_prefetch_work(struct ib_pd *pd, 1741 enum ib_uverbs_advise_mr_advice advice, 1742 u32 pf_flags, struct prefetch_mr_work *work, 1743 struct ib_sge *sg_list, u32 num_sge) 1744 { 1745 u32 i; 1746 1747 INIT_WORK(&work->work, mlx5_ib_prefetch_mr_work); 1748 work->pf_flags = pf_flags; 1749 1750 for (i = 0; i < num_sge; ++i) { 1751 struct mlx5_ib_mr *mr; 1752 1753 mr = get_prefetchable_mr(pd, advice, sg_list[i].lkey); 1754 if (IS_ERR(mr)) { 1755 work->num_sge = i; 1756 return PTR_ERR(mr); 1757 } 1758 work->frags[i].io_virt = sg_list[i].addr; 1759 work->frags[i].length = sg_list[i].length; 1760 work->frags[i].mr = mr; 1761 } 1762 work->num_sge = num_sge; 1763 return 0; 1764 } 1765 1766 static int mlx5_ib_prefetch_sg_list(struct ib_pd *pd, 1767 enum ib_uverbs_advise_mr_advice advice, 1768 u32 pf_flags, struct ib_sge *sg_list, 1769 u32 num_sge) 1770 { 1771 u32 bytes_mapped = 0; 1772 int ret = 0; 1773 u32 i; 1774 1775 for (i = 0; i < num_sge; ++i) { 1776 struct mlx5_ib_mr *mr; 1777 1778 mr = get_prefetchable_mr(pd, advice, sg_list[i].lkey); 1779 if (IS_ERR(mr)) 1780 return PTR_ERR(mr); 1781 ret = pagefault_mr(mr, sg_list[i].addr, sg_list[i].length, 1782 &bytes_mapped, pf_flags); 1783 if (ret < 0) { 1784 mlx5r_deref_odp_mkey(&mr->mmkey); 1785 return ret; 1786 } 1787 mlx5_update_odp_stats(mr, prefetch, ret); 1788 mlx5r_deref_odp_mkey(&mr->mmkey); 1789 } 1790 1791 return 0; 1792 } 1793 1794 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1795 enum ib_uverbs_advise_mr_advice advice, 1796 u32 flags, struct ib_sge *sg_list, u32 num_sge) 1797 { 1798 u32 pf_flags = 0; 1799 struct prefetch_mr_work *work; 1800 int rc; 1801 1802 if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH) 1803 pf_flags |= MLX5_PF_FLAGS_DOWNGRADE; 1804 1805 if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT) 1806 pf_flags |= MLX5_PF_FLAGS_SNAPSHOT; 1807 1808 if (flags & IB_UVERBS_ADVISE_MR_FLAG_FLUSH) 1809 return mlx5_ib_prefetch_sg_list(pd, advice, pf_flags, sg_list, 1810 num_sge); 1811 1812 work = kvzalloc(struct_size(work, frags, num_sge), GFP_KERNEL); 1813 if (!work) 1814 return -ENOMEM; 1815 1816 rc = init_prefetch_work(pd, advice, pf_flags, work, sg_list, num_sge); 1817 if (rc) { 1818 destroy_prefetch_work(work); 1819 return rc; 1820 } 1821 queue_work(system_unbound_wq, &work->work); 1822 return 0; 1823 } 1824