1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 34 #include <linux/kref.h> 35 #include <linux/random.h> 36 #include <linux/debugfs.h> 37 #include <linux/export.h> 38 #include <linux/delay.h> 39 #include <rdma/ib_umem.h> 40 #include <rdma/ib_umem_odp.h> 41 #include <rdma/ib_verbs.h> 42 #include "mlx5_ib.h" 43 44 enum { 45 MAX_PENDING_REG_MR = 8, 46 }; 47 48 #define MLX5_UMR_ALIGN 2048 49 50 static int clean_mr(struct mlx5_ib_mr *mr); 51 static int use_umr(struct mlx5_ib_dev *dev, int order); 52 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 53 54 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 55 { 56 int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); 57 58 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 59 /* Wait until all page fault handlers using the mr complete. */ 60 synchronize_srcu(&dev->mr_srcu); 61 #endif 62 63 return err; 64 } 65 66 static int order2idx(struct mlx5_ib_dev *dev, int order) 67 { 68 struct mlx5_mr_cache *cache = &dev->cache; 69 70 if (order < cache->ent[0].order) 71 return 0; 72 else 73 return order - cache->ent[0].order; 74 } 75 76 static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) 77 { 78 return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= 79 length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); 80 } 81 82 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 83 static void update_odp_mr(struct mlx5_ib_mr *mr) 84 { 85 if (mr->umem->odp_data) { 86 /* 87 * This barrier prevents the compiler from moving the 88 * setting of umem->odp_data->private to point to our 89 * MR, before reg_umr finished, to ensure that the MR 90 * initialization have finished before starting to 91 * handle invalidations. 92 */ 93 smp_wmb(); 94 mr->umem->odp_data->private = mr; 95 /* 96 * Make sure we will see the new 97 * umem->odp_data->private value in the invalidation 98 * routines, before we can get page faults on the 99 * MR. Page faults can happen once we put the MR in 100 * the tree, below this line. Without the barrier, 101 * there can be a fault handling and an invalidation 102 * before umem->odp_data->private == mr is visible to 103 * the invalidation handler. 104 */ 105 smp_wmb(); 106 } 107 } 108 #endif 109 110 static void reg_mr_callback(int status, void *context) 111 { 112 struct mlx5_ib_mr *mr = context; 113 struct mlx5_ib_dev *dev = mr->dev; 114 struct mlx5_mr_cache *cache = &dev->cache; 115 int c = order2idx(dev, mr->order); 116 struct mlx5_cache_ent *ent = &cache->ent[c]; 117 u8 key; 118 unsigned long flags; 119 struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table; 120 int err; 121 122 spin_lock_irqsave(&ent->lock, flags); 123 ent->pending--; 124 spin_unlock_irqrestore(&ent->lock, flags); 125 if (status) { 126 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); 127 kfree(mr); 128 dev->fill_delay = 1; 129 mod_timer(&dev->delay_timer, jiffies + HZ); 130 return; 131 } 132 133 mr->mmkey.type = MLX5_MKEY_MR; 134 spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); 135 key = dev->mdev->priv.mkey_key++; 136 spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); 137 mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key; 138 139 cache->last_add = jiffies; 140 141 spin_lock_irqsave(&ent->lock, flags); 142 list_add_tail(&mr->list, &ent->head); 143 ent->cur++; 144 ent->size++; 145 spin_unlock_irqrestore(&ent->lock, flags); 146 147 write_lock_irqsave(&table->lock, flags); 148 err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key), 149 &mr->mmkey); 150 if (err) 151 pr_err("Error inserting to mkey tree. 0x%x\n", -err); 152 write_unlock_irqrestore(&table->lock, flags); 153 154 if (!completion_done(&ent->compl)) 155 complete(&ent->compl); 156 } 157 158 static int add_keys(struct mlx5_ib_dev *dev, int c, int num) 159 { 160 struct mlx5_mr_cache *cache = &dev->cache; 161 struct mlx5_cache_ent *ent = &cache->ent[c]; 162 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 163 struct mlx5_ib_mr *mr; 164 void *mkc; 165 u32 *in; 166 int err = 0; 167 int i; 168 169 in = kzalloc(inlen, GFP_KERNEL); 170 if (!in) 171 return -ENOMEM; 172 173 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 174 for (i = 0; i < num; i++) { 175 if (ent->pending >= MAX_PENDING_REG_MR) { 176 err = -EAGAIN; 177 break; 178 } 179 180 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 181 if (!mr) { 182 err = -ENOMEM; 183 break; 184 } 185 mr->order = ent->order; 186 mr->umred = 1; 187 mr->dev = dev; 188 189 MLX5_SET(mkc, mkc, free, 1); 190 MLX5_SET(mkc, mkc, umr_en, 1); 191 MLX5_SET(mkc, mkc, access_mode, ent->access_mode); 192 193 MLX5_SET(mkc, mkc, qpn, 0xffffff); 194 MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt); 195 MLX5_SET(mkc, mkc, log_page_size, ent->page); 196 197 spin_lock_irq(&ent->lock); 198 ent->pending++; 199 spin_unlock_irq(&ent->lock); 200 err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey, 201 in, inlen, 202 mr->out, sizeof(mr->out), 203 reg_mr_callback, mr); 204 if (err) { 205 spin_lock_irq(&ent->lock); 206 ent->pending--; 207 spin_unlock_irq(&ent->lock); 208 mlx5_ib_warn(dev, "create mkey failed %d\n", err); 209 kfree(mr); 210 break; 211 } 212 } 213 214 kfree(in); 215 return err; 216 } 217 218 static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) 219 { 220 struct mlx5_mr_cache *cache = &dev->cache; 221 struct mlx5_cache_ent *ent = &cache->ent[c]; 222 struct mlx5_ib_mr *mr; 223 int err; 224 int i; 225 226 for (i = 0; i < num; i++) { 227 spin_lock_irq(&ent->lock); 228 if (list_empty(&ent->head)) { 229 spin_unlock_irq(&ent->lock); 230 return; 231 } 232 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); 233 list_del(&mr->list); 234 ent->cur--; 235 ent->size--; 236 spin_unlock_irq(&ent->lock); 237 err = destroy_mkey(dev, mr); 238 if (err) 239 mlx5_ib_warn(dev, "failed destroy mkey\n"); 240 else 241 kfree(mr); 242 } 243 } 244 245 static ssize_t size_write(struct file *filp, const char __user *buf, 246 size_t count, loff_t *pos) 247 { 248 struct mlx5_cache_ent *ent = filp->private_data; 249 struct mlx5_ib_dev *dev = ent->dev; 250 char lbuf[20]; 251 u32 var; 252 int err; 253 int c; 254 255 if (copy_from_user(lbuf, buf, sizeof(lbuf))) 256 return -EFAULT; 257 258 c = order2idx(dev, ent->order); 259 lbuf[sizeof(lbuf) - 1] = 0; 260 261 if (sscanf(lbuf, "%u", &var) != 1) 262 return -EINVAL; 263 264 if (var < ent->limit) 265 return -EINVAL; 266 267 if (var > ent->size) { 268 do { 269 err = add_keys(dev, c, var - ent->size); 270 if (err && err != -EAGAIN) 271 return err; 272 273 usleep_range(3000, 5000); 274 } while (err); 275 } else if (var < ent->size) { 276 remove_keys(dev, c, ent->size - var); 277 } 278 279 return count; 280 } 281 282 static ssize_t size_read(struct file *filp, char __user *buf, size_t count, 283 loff_t *pos) 284 { 285 struct mlx5_cache_ent *ent = filp->private_data; 286 char lbuf[20]; 287 int err; 288 289 if (*pos) 290 return 0; 291 292 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); 293 if (err < 0) 294 return err; 295 296 if (copy_to_user(buf, lbuf, err)) 297 return -EFAULT; 298 299 *pos += err; 300 301 return err; 302 } 303 304 static const struct file_operations size_fops = { 305 .owner = THIS_MODULE, 306 .open = simple_open, 307 .write = size_write, 308 .read = size_read, 309 }; 310 311 static ssize_t limit_write(struct file *filp, const char __user *buf, 312 size_t count, loff_t *pos) 313 { 314 struct mlx5_cache_ent *ent = filp->private_data; 315 struct mlx5_ib_dev *dev = ent->dev; 316 char lbuf[20]; 317 u32 var; 318 int err; 319 int c; 320 321 if (copy_from_user(lbuf, buf, sizeof(lbuf))) 322 return -EFAULT; 323 324 c = order2idx(dev, ent->order); 325 lbuf[sizeof(lbuf) - 1] = 0; 326 327 if (sscanf(lbuf, "%u", &var) != 1) 328 return -EINVAL; 329 330 if (var > ent->size) 331 return -EINVAL; 332 333 ent->limit = var; 334 335 if (ent->cur < ent->limit) { 336 err = add_keys(dev, c, 2 * ent->limit - ent->cur); 337 if (err) 338 return err; 339 } 340 341 return count; 342 } 343 344 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, 345 loff_t *pos) 346 { 347 struct mlx5_cache_ent *ent = filp->private_data; 348 char lbuf[20]; 349 int err; 350 351 if (*pos) 352 return 0; 353 354 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); 355 if (err < 0) 356 return err; 357 358 if (copy_to_user(buf, lbuf, err)) 359 return -EFAULT; 360 361 *pos += err; 362 363 return err; 364 } 365 366 static const struct file_operations limit_fops = { 367 .owner = THIS_MODULE, 368 .open = simple_open, 369 .write = limit_write, 370 .read = limit_read, 371 }; 372 373 static int someone_adding(struct mlx5_mr_cache *cache) 374 { 375 int i; 376 377 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 378 if (cache->ent[i].cur < cache->ent[i].limit) 379 return 1; 380 } 381 382 return 0; 383 } 384 385 static void __cache_work_func(struct mlx5_cache_ent *ent) 386 { 387 struct mlx5_ib_dev *dev = ent->dev; 388 struct mlx5_mr_cache *cache = &dev->cache; 389 int i = order2idx(dev, ent->order); 390 int err; 391 392 if (cache->stopped) 393 return; 394 395 ent = &dev->cache.ent[i]; 396 if (ent->cur < 2 * ent->limit && !dev->fill_delay) { 397 err = add_keys(dev, i, 1); 398 if (ent->cur < 2 * ent->limit) { 399 if (err == -EAGAIN) { 400 mlx5_ib_dbg(dev, "returned eagain, order %d\n", 401 i + 2); 402 queue_delayed_work(cache->wq, &ent->dwork, 403 msecs_to_jiffies(3)); 404 } else if (err) { 405 mlx5_ib_warn(dev, "command failed order %d, err %d\n", 406 i + 2, err); 407 queue_delayed_work(cache->wq, &ent->dwork, 408 msecs_to_jiffies(1000)); 409 } else { 410 queue_work(cache->wq, &ent->work); 411 } 412 } 413 } else if (ent->cur > 2 * ent->limit) { 414 /* 415 * The remove_keys() logic is performed as garbage collection 416 * task. Such task is intended to be run when no other active 417 * processes are running. 418 * 419 * The need_resched() will return TRUE if there are user tasks 420 * to be activated in near future. 421 * 422 * In such case, we don't execute remove_keys() and postpone 423 * the garbage collection work to try to run in next cycle, 424 * in order to free CPU resources to other tasks. 425 */ 426 if (!need_resched() && !someone_adding(cache) && 427 time_after(jiffies, cache->last_add + 300 * HZ)) { 428 remove_keys(dev, i, 1); 429 if (ent->cur > ent->limit) 430 queue_work(cache->wq, &ent->work); 431 } else { 432 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); 433 } 434 } 435 } 436 437 static void delayed_cache_work_func(struct work_struct *work) 438 { 439 struct mlx5_cache_ent *ent; 440 441 ent = container_of(work, struct mlx5_cache_ent, dwork.work); 442 __cache_work_func(ent); 443 } 444 445 static void cache_work_func(struct work_struct *work) 446 { 447 struct mlx5_cache_ent *ent; 448 449 ent = container_of(work, struct mlx5_cache_ent, work); 450 __cache_work_func(ent); 451 } 452 453 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry) 454 { 455 struct mlx5_mr_cache *cache = &dev->cache; 456 struct mlx5_cache_ent *ent; 457 struct mlx5_ib_mr *mr; 458 int err; 459 460 if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) { 461 mlx5_ib_err(dev, "cache entry %d is out of range\n", entry); 462 return NULL; 463 } 464 465 ent = &cache->ent[entry]; 466 while (1) { 467 spin_lock_irq(&ent->lock); 468 if (list_empty(&ent->head)) { 469 spin_unlock_irq(&ent->lock); 470 471 err = add_keys(dev, entry, 1); 472 if (err && err != -EAGAIN) 473 return ERR_PTR(err); 474 475 wait_for_completion(&ent->compl); 476 } else { 477 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, 478 list); 479 list_del(&mr->list); 480 ent->cur--; 481 spin_unlock_irq(&ent->lock); 482 if (ent->cur < ent->limit) 483 queue_work(cache->wq, &ent->work); 484 return mr; 485 } 486 } 487 } 488 489 static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) 490 { 491 struct mlx5_mr_cache *cache = &dev->cache; 492 struct mlx5_ib_mr *mr = NULL; 493 struct mlx5_cache_ent *ent; 494 int c; 495 int i; 496 497 c = order2idx(dev, order); 498 if (c < 0 || c > MAX_UMR_CACHE_ENTRY) { 499 mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); 500 return NULL; 501 } 502 503 for (i = c; i < MAX_UMR_CACHE_ENTRY; i++) { 504 ent = &cache->ent[i]; 505 506 mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); 507 508 spin_lock_irq(&ent->lock); 509 if (!list_empty(&ent->head)) { 510 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, 511 list); 512 list_del(&mr->list); 513 ent->cur--; 514 spin_unlock_irq(&ent->lock); 515 if (ent->cur < ent->limit) 516 queue_work(cache->wq, &ent->work); 517 break; 518 } 519 spin_unlock_irq(&ent->lock); 520 521 queue_work(cache->wq, &ent->work); 522 } 523 524 if (!mr) 525 cache->ent[c].miss++; 526 527 return mr; 528 } 529 530 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 531 { 532 struct mlx5_mr_cache *cache = &dev->cache; 533 struct mlx5_cache_ent *ent; 534 int shrink = 0; 535 int c; 536 537 c = order2idx(dev, mr->order); 538 if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { 539 mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); 540 return; 541 } 542 543 if (unreg_umr(dev, mr)) 544 return; 545 546 ent = &cache->ent[c]; 547 spin_lock_irq(&ent->lock); 548 list_add_tail(&mr->list, &ent->head); 549 ent->cur++; 550 if (ent->cur > 2 * ent->limit) 551 shrink = 1; 552 spin_unlock_irq(&ent->lock); 553 554 if (shrink) 555 queue_work(cache->wq, &ent->work); 556 } 557 558 static void clean_keys(struct mlx5_ib_dev *dev, int c) 559 { 560 struct mlx5_mr_cache *cache = &dev->cache; 561 struct mlx5_cache_ent *ent = &cache->ent[c]; 562 struct mlx5_ib_mr *mr; 563 int err; 564 565 cancel_delayed_work(&ent->dwork); 566 while (1) { 567 spin_lock_irq(&ent->lock); 568 if (list_empty(&ent->head)) { 569 spin_unlock_irq(&ent->lock); 570 return; 571 } 572 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); 573 list_del(&mr->list); 574 ent->cur--; 575 ent->size--; 576 spin_unlock_irq(&ent->lock); 577 err = destroy_mkey(dev, mr); 578 if (err) 579 mlx5_ib_warn(dev, "failed destroy mkey\n"); 580 else 581 kfree(mr); 582 } 583 } 584 585 static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) 586 { 587 struct mlx5_mr_cache *cache = &dev->cache; 588 struct mlx5_cache_ent *ent; 589 int i; 590 591 if (!mlx5_debugfs_root) 592 return 0; 593 594 cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); 595 if (!cache->root) 596 return -ENOMEM; 597 598 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 599 ent = &cache->ent[i]; 600 sprintf(ent->name, "%d", ent->order); 601 ent->dir = debugfs_create_dir(ent->name, cache->root); 602 if (!ent->dir) 603 return -ENOMEM; 604 605 ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, 606 &size_fops); 607 if (!ent->fsize) 608 return -ENOMEM; 609 610 ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, 611 &limit_fops); 612 if (!ent->flimit) 613 return -ENOMEM; 614 615 ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, 616 &ent->cur); 617 if (!ent->fcur) 618 return -ENOMEM; 619 620 ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, 621 &ent->miss); 622 if (!ent->fmiss) 623 return -ENOMEM; 624 } 625 626 return 0; 627 } 628 629 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) 630 { 631 if (!mlx5_debugfs_root) 632 return; 633 634 debugfs_remove_recursive(dev->cache.root); 635 } 636 637 static void delay_time_func(unsigned long ctx) 638 { 639 struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx; 640 641 dev->fill_delay = 0; 642 } 643 644 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) 645 { 646 struct mlx5_mr_cache *cache = &dev->cache; 647 struct mlx5_cache_ent *ent; 648 int err; 649 int i; 650 651 mutex_init(&dev->slow_path_mutex); 652 cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); 653 if (!cache->wq) { 654 mlx5_ib_warn(dev, "failed to create work queue\n"); 655 return -ENOMEM; 656 } 657 658 setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev); 659 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 660 ent = &cache->ent[i]; 661 INIT_LIST_HEAD(&ent->head); 662 spin_lock_init(&ent->lock); 663 ent->order = i + 2; 664 ent->dev = dev; 665 ent->limit = 0; 666 667 init_completion(&ent->compl); 668 INIT_WORK(&ent->work, cache_work_func); 669 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); 670 queue_work(cache->wq, &ent->work); 671 672 if (i > MAX_UMR_CACHE_ENTRY) { 673 mlx5_odp_init_mr_cache_entry(ent); 674 continue; 675 } 676 677 if (!use_umr(dev, ent->order)) 678 continue; 679 680 ent->page = PAGE_SHIFT; 681 ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) / 682 MLX5_IB_UMR_OCTOWORD; 683 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; 684 if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && 685 mlx5_core_is_pf(dev->mdev)) 686 ent->limit = dev->mdev->profile->mr_cache[i].limit; 687 else 688 ent->limit = 0; 689 } 690 691 err = mlx5_mr_cache_debugfs_init(dev); 692 if (err) 693 mlx5_ib_warn(dev, "cache debugfs failure\n"); 694 695 return 0; 696 } 697 698 static void wait_for_async_commands(struct mlx5_ib_dev *dev) 699 { 700 struct mlx5_mr_cache *cache = &dev->cache; 701 struct mlx5_cache_ent *ent; 702 int total = 0; 703 int i; 704 int j; 705 706 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 707 ent = &cache->ent[i]; 708 for (j = 0 ; j < 1000; j++) { 709 if (!ent->pending) 710 break; 711 msleep(50); 712 } 713 } 714 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 715 ent = &cache->ent[i]; 716 total += ent->pending; 717 } 718 719 if (total) 720 mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total); 721 else 722 mlx5_ib_warn(dev, "done with all pending requests\n"); 723 } 724 725 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) 726 { 727 int i; 728 729 dev->cache.stopped = 1; 730 flush_workqueue(dev->cache.wq); 731 732 mlx5_mr_cache_debugfs_cleanup(dev); 733 734 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) 735 clean_keys(dev, i); 736 737 destroy_workqueue(dev->cache.wq); 738 wait_for_async_commands(dev); 739 del_timer_sync(&dev->delay_timer); 740 741 return 0; 742 } 743 744 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) 745 { 746 struct mlx5_ib_dev *dev = to_mdev(pd->device); 747 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 748 struct mlx5_core_dev *mdev = dev->mdev; 749 struct mlx5_ib_mr *mr; 750 void *mkc; 751 u32 *in; 752 int err; 753 754 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 755 if (!mr) 756 return ERR_PTR(-ENOMEM); 757 758 in = kzalloc(inlen, GFP_KERNEL); 759 if (!in) { 760 err = -ENOMEM; 761 goto err_free; 762 } 763 764 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 765 766 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA); 767 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); 768 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); 769 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); 770 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); 771 MLX5_SET(mkc, mkc, lr, 1); 772 773 MLX5_SET(mkc, mkc, length64, 1); 774 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 775 MLX5_SET(mkc, mkc, qpn, 0xffffff); 776 MLX5_SET64(mkc, mkc, start_addr, 0); 777 778 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); 779 if (err) 780 goto err_in; 781 782 kfree(in); 783 mr->mmkey.type = MLX5_MKEY_MR; 784 mr->ibmr.lkey = mr->mmkey.key; 785 mr->ibmr.rkey = mr->mmkey.key; 786 mr->umem = NULL; 787 788 return &mr->ibmr; 789 790 err_in: 791 kfree(in); 792 793 err_free: 794 kfree(mr); 795 796 return ERR_PTR(err); 797 } 798 799 static int get_octo_len(u64 addr, u64 len, int page_size) 800 { 801 u64 offset; 802 int npages; 803 804 offset = addr & (page_size - 1); 805 npages = ALIGN(len + offset, page_size) >> ilog2(page_size); 806 return (npages + 1) / 2; 807 } 808 809 static int use_umr(struct mlx5_ib_dev *dev, int order) 810 { 811 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) 812 return order <= MAX_UMR_CACHE_ENTRY + 2; 813 return order <= MLX5_MAX_UMR_SHIFT; 814 } 815 816 static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length, 817 int access_flags, struct ib_umem **umem, 818 int *npages, int *page_shift, int *ncont, 819 int *order) 820 { 821 struct mlx5_ib_dev *dev = to_mdev(pd->device); 822 int err; 823 824 *umem = ib_umem_get(pd->uobject->context, start, length, 825 access_flags, 0); 826 err = PTR_ERR_OR_ZERO(*umem); 827 if (err < 0) { 828 mlx5_ib_err(dev, "umem get failed (%ld)\n", PTR_ERR(umem)); 829 return err; 830 } 831 832 mlx5_ib_cont_pages(*umem, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages, 833 page_shift, ncont, order); 834 if (!*npages) { 835 mlx5_ib_warn(dev, "avoid zero region\n"); 836 ib_umem_release(*umem); 837 return -EINVAL; 838 } 839 840 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", 841 *npages, *ncont, *order, *page_shift); 842 843 return 0; 844 } 845 846 static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) 847 { 848 struct mlx5_ib_umr_context *context = 849 container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); 850 851 context->status = wc->status; 852 complete(&context->done); 853 } 854 855 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) 856 { 857 context->cqe.done = mlx5_ib_umr_done; 858 context->status = -1; 859 init_completion(&context->done); 860 } 861 862 static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev, 863 struct mlx5_umr_wr *umrwr) 864 { 865 struct umr_common *umrc = &dev->umrc; 866 struct ib_send_wr *bad; 867 int err; 868 struct mlx5_ib_umr_context umr_context; 869 870 mlx5_ib_init_umr_context(&umr_context); 871 umrwr->wr.wr_cqe = &umr_context.cqe; 872 873 down(&umrc->sem); 874 err = ib_post_send(umrc->qp, &umrwr->wr, &bad); 875 if (err) { 876 mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err); 877 } else { 878 wait_for_completion(&umr_context.done); 879 if (umr_context.status != IB_WC_SUCCESS) { 880 mlx5_ib_warn(dev, "reg umr failed (%u)\n", 881 umr_context.status); 882 err = -EFAULT; 883 } 884 } 885 up(&umrc->sem); 886 return err; 887 } 888 889 static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem, 890 u64 virt_addr, u64 len, int npages, 891 int page_shift, int order, int access_flags) 892 { 893 struct mlx5_ib_dev *dev = to_mdev(pd->device); 894 struct mlx5_ib_mr *mr; 895 int err = 0; 896 int i; 897 898 for (i = 0; i < 1; i++) { 899 mr = alloc_cached_mr(dev, order); 900 if (mr) 901 break; 902 903 err = add_keys(dev, order2idx(dev, order), 1); 904 if (err && err != -EAGAIN) { 905 mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); 906 break; 907 } 908 } 909 910 if (!mr) 911 return ERR_PTR(-EAGAIN); 912 913 mr->ibmr.pd = pd; 914 mr->umem = umem; 915 mr->access_flags = access_flags; 916 mr->desc_size = sizeof(struct mlx5_mtt); 917 mr->mmkey.iova = virt_addr; 918 mr->mmkey.size = len; 919 mr->mmkey.pd = to_mpd(pd)->pdn; 920 921 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, 922 MLX5_IB_UPD_XLT_ENABLE); 923 924 if (err) { 925 mlx5_mr_cache_free(dev, mr); 926 return ERR_PTR(err); 927 } 928 929 mr->live = 1; 930 931 return mr; 932 } 933 934 static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages, 935 void *xlt, int page_shift, size_t size, 936 int flags) 937 { 938 struct mlx5_ib_dev *dev = mr->dev; 939 struct ib_umem *umem = mr->umem; 940 if (flags & MLX5_IB_UPD_XLT_INDIRECT) { 941 mlx5_odp_populate_klm(xlt, idx, npages, mr, flags); 942 return npages; 943 } 944 945 npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx); 946 947 if (!(flags & MLX5_IB_UPD_XLT_ZAP)) { 948 __mlx5_ib_populate_pas(dev, umem, page_shift, 949 idx, npages, xlt, 950 MLX5_IB_MTT_PRESENT); 951 /* Clear padding after the pages 952 * brought from the umem. 953 */ 954 memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0, 955 size - npages * sizeof(struct mlx5_mtt)); 956 } 957 958 return npages; 959 } 960 961 #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \ 962 MLX5_UMR_MTT_ALIGNMENT) 963 #define MLX5_SPARE_UMR_CHUNK 0x10000 964 965 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 966 int page_shift, int flags) 967 { 968 struct mlx5_ib_dev *dev = mr->dev; 969 struct device *ddev = dev->ib_dev.dev.parent; 970 struct mlx5_ib_ucontext *uctx = NULL; 971 int size; 972 void *xlt; 973 dma_addr_t dma; 974 struct mlx5_umr_wr wr; 975 struct ib_sge sg; 976 int err = 0; 977 int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) 978 ? sizeof(struct mlx5_klm) 979 : sizeof(struct mlx5_mtt); 980 const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size; 981 const int page_mask = page_align - 1; 982 size_t pages_mapped = 0; 983 size_t pages_to_map = 0; 984 size_t pages_iter = 0; 985 gfp_t gfp; 986 987 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, 988 * so we need to align the offset and length accordingly 989 */ 990 if (idx & page_mask) { 991 npages += idx & page_mask; 992 idx &= ~page_mask; 993 } 994 995 gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL; 996 gfp |= __GFP_ZERO | __GFP_NOWARN; 997 998 pages_to_map = ALIGN(npages, page_align); 999 size = desc_size * pages_to_map; 1000 size = min_t(int, size, MLX5_MAX_UMR_CHUNK); 1001 1002 xlt = (void *)__get_free_pages(gfp, get_order(size)); 1003 if (!xlt && size > MLX5_SPARE_UMR_CHUNK) { 1004 mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n", 1005 size, get_order(size), MLX5_SPARE_UMR_CHUNK); 1006 1007 size = MLX5_SPARE_UMR_CHUNK; 1008 xlt = (void *)__get_free_pages(gfp, get_order(size)); 1009 } 1010 1011 if (!xlt) { 1012 uctx = to_mucontext(mr->ibmr.pd->uobject->context); 1013 mlx5_ib_warn(dev, "Using XLT emergency buffer\n"); 1014 size = PAGE_SIZE; 1015 xlt = (void *)uctx->upd_xlt_page; 1016 mutex_lock(&uctx->upd_xlt_page_mutex); 1017 memset(xlt, 0, size); 1018 } 1019 pages_iter = size / desc_size; 1020 dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE); 1021 if (dma_mapping_error(ddev, dma)) { 1022 mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); 1023 err = -ENOMEM; 1024 goto free_xlt; 1025 } 1026 1027 sg.addr = dma; 1028 sg.lkey = dev->umrc.pd->local_dma_lkey; 1029 1030 memset(&wr, 0, sizeof(wr)); 1031 wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT; 1032 if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) 1033 wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE; 1034 wr.wr.sg_list = &sg; 1035 wr.wr.num_sge = 1; 1036 wr.wr.opcode = MLX5_IB_WR_UMR; 1037 1038 wr.pd = mr->ibmr.pd; 1039 wr.mkey = mr->mmkey.key; 1040 wr.length = mr->mmkey.size; 1041 wr.virt_addr = mr->mmkey.iova; 1042 wr.access_flags = mr->access_flags; 1043 wr.page_shift = page_shift; 1044 1045 for (pages_mapped = 0; 1046 pages_mapped < pages_to_map && !err; 1047 pages_mapped += pages_iter, idx += pages_iter) { 1048 npages = min_t(int, pages_iter, pages_to_map - pages_mapped); 1049 dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); 1050 npages = populate_xlt(mr, idx, npages, xlt, 1051 page_shift, size, flags); 1052 1053 dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); 1054 1055 sg.length = ALIGN(npages * desc_size, 1056 MLX5_UMR_MTT_ALIGNMENT); 1057 1058 if (pages_mapped + pages_iter >= pages_to_map) { 1059 if (flags & MLX5_IB_UPD_XLT_ENABLE) 1060 wr.wr.send_flags |= 1061 MLX5_IB_SEND_UMR_ENABLE_MR | 1062 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS | 1063 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; 1064 if (flags & MLX5_IB_UPD_XLT_PD || 1065 flags & MLX5_IB_UPD_XLT_ACCESS) 1066 wr.wr.send_flags |= 1067 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; 1068 if (flags & MLX5_IB_UPD_XLT_ADDR) 1069 wr.wr.send_flags |= 1070 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; 1071 } 1072 1073 wr.offset = idx * desc_size; 1074 wr.xlt_size = sg.length; 1075 1076 err = mlx5_ib_post_send_wait(dev, &wr); 1077 } 1078 dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); 1079 1080 free_xlt: 1081 if (uctx) 1082 mutex_unlock(&uctx->upd_xlt_page_mutex); 1083 else 1084 free_pages((unsigned long)xlt, get_order(size)); 1085 1086 return err; 1087 } 1088 1089 /* 1090 * If ibmr is NULL it will be allocated by reg_create. 1091 * Else, the given ibmr will be used. 1092 */ 1093 static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, 1094 u64 virt_addr, u64 length, 1095 struct ib_umem *umem, int npages, 1096 int page_shift, int access_flags) 1097 { 1098 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1099 struct mlx5_ib_mr *mr; 1100 __be64 *pas; 1101 void *mkc; 1102 int inlen; 1103 u32 *in; 1104 int err; 1105 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); 1106 1107 mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); 1108 if (!mr) 1109 return ERR_PTR(-ENOMEM); 1110 1111 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + 1112 sizeof(*pas) * ((npages + 1) / 2) * 2; 1113 in = mlx5_vzalloc(inlen); 1114 if (!in) { 1115 err = -ENOMEM; 1116 goto err_1; 1117 } 1118 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 1119 if (!(access_flags & IB_ACCESS_ON_DEMAND)) 1120 mlx5_ib_populate_pas(dev, umem, page_shift, pas, 1121 pg_cap ? MLX5_IB_MTT_PRESENT : 0); 1122 1123 /* The pg_access bit allows setting the access flags 1124 * in the page list submitted with the command. */ 1125 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); 1126 1127 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1128 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); 1129 MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 1130 MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 1131 MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); 1132 MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); 1133 MLX5_SET(mkc, mkc, lr, 1); 1134 1135 MLX5_SET64(mkc, mkc, start_addr, virt_addr); 1136 MLX5_SET64(mkc, mkc, len, length); 1137 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 1138 MLX5_SET(mkc, mkc, bsf_octword_size, 0); 1139 MLX5_SET(mkc, mkc, translations_octword_size, 1140 get_octo_len(virt_addr, length, 1 << page_shift)); 1141 MLX5_SET(mkc, mkc, log_page_size, page_shift); 1142 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1143 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 1144 get_octo_len(virt_addr, length, 1 << page_shift)); 1145 1146 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); 1147 if (err) { 1148 mlx5_ib_warn(dev, "create mkey failed\n"); 1149 goto err_2; 1150 } 1151 mr->mmkey.type = MLX5_MKEY_MR; 1152 mr->desc_size = sizeof(struct mlx5_mtt); 1153 mr->umem = umem; 1154 mr->dev = dev; 1155 mr->live = 1; 1156 kvfree(in); 1157 1158 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); 1159 1160 return mr; 1161 1162 err_2: 1163 kvfree(in); 1164 1165 err_1: 1166 if (!ibmr) 1167 kfree(mr); 1168 1169 return ERR_PTR(err); 1170 } 1171 1172 static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, 1173 int npages, u64 length, int access_flags) 1174 { 1175 mr->npages = npages; 1176 atomic_add(npages, &dev->mdev->priv.reg_pages); 1177 mr->ibmr.lkey = mr->mmkey.key; 1178 mr->ibmr.rkey = mr->mmkey.key; 1179 mr->ibmr.length = length; 1180 mr->access_flags = access_flags; 1181 } 1182 1183 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1184 u64 virt_addr, int access_flags, 1185 struct ib_udata *udata) 1186 { 1187 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1188 struct mlx5_ib_mr *mr = NULL; 1189 struct ib_umem *umem; 1190 int page_shift; 1191 int npages; 1192 int ncont; 1193 int order; 1194 int err; 1195 1196 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", 1197 start, virt_addr, length, access_flags); 1198 1199 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1200 if (!start && length == U64_MAX) { 1201 if (!(access_flags & IB_ACCESS_ON_DEMAND) || 1202 !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) 1203 return ERR_PTR(-EINVAL); 1204 1205 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags); 1206 return &mr->ibmr; 1207 } 1208 #endif 1209 1210 err = mr_umem_get(pd, start, length, access_flags, &umem, &npages, 1211 &page_shift, &ncont, &order); 1212 1213 if (err < 0) 1214 return ERR_PTR(err); 1215 1216 if (use_umr(dev, order)) { 1217 mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift, 1218 order, access_flags); 1219 if (PTR_ERR(mr) == -EAGAIN) { 1220 mlx5_ib_dbg(dev, "cache empty for order %d", order); 1221 mr = NULL; 1222 } 1223 } else if (access_flags & IB_ACCESS_ON_DEMAND && 1224 !MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { 1225 err = -EINVAL; 1226 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB"); 1227 goto error; 1228 } 1229 1230 if (!mr) { 1231 mutex_lock(&dev->slow_path_mutex); 1232 mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, 1233 page_shift, access_flags); 1234 mutex_unlock(&dev->slow_path_mutex); 1235 } 1236 1237 if (IS_ERR(mr)) { 1238 err = PTR_ERR(mr); 1239 goto error; 1240 } 1241 1242 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); 1243 1244 mr->umem = umem; 1245 set_mr_fileds(dev, mr, npages, length, access_flags); 1246 1247 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1248 update_odp_mr(mr); 1249 #endif 1250 1251 return &mr->ibmr; 1252 1253 error: 1254 ib_umem_release(umem); 1255 return ERR_PTR(err); 1256 } 1257 1258 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 1259 { 1260 struct mlx5_core_dev *mdev = dev->mdev; 1261 struct mlx5_umr_wr umrwr = {}; 1262 1263 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) 1264 return 0; 1265 1266 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR | 1267 MLX5_IB_SEND_UMR_FAIL_IF_FREE; 1268 umrwr.wr.opcode = MLX5_IB_WR_UMR; 1269 umrwr.mkey = mr->mmkey.key; 1270 1271 return mlx5_ib_post_send_wait(dev, &umrwr); 1272 } 1273 1274 static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, 1275 int access_flags, int flags) 1276 { 1277 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1278 struct mlx5_umr_wr umrwr = {}; 1279 int err; 1280 1281 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; 1282 1283 umrwr.wr.opcode = MLX5_IB_WR_UMR; 1284 umrwr.mkey = mr->mmkey.key; 1285 1286 if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) { 1287 umrwr.pd = pd; 1288 umrwr.access_flags = access_flags; 1289 umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; 1290 } 1291 1292 err = mlx5_ib_post_send_wait(dev, &umrwr); 1293 1294 return err; 1295 } 1296 1297 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1298 u64 length, u64 virt_addr, int new_access_flags, 1299 struct ib_pd *new_pd, struct ib_udata *udata) 1300 { 1301 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); 1302 struct mlx5_ib_mr *mr = to_mmr(ib_mr); 1303 struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; 1304 int access_flags = flags & IB_MR_REREG_ACCESS ? 1305 new_access_flags : 1306 mr->access_flags; 1307 u64 addr = (flags & IB_MR_REREG_TRANS) ? virt_addr : mr->umem->address; 1308 u64 len = (flags & IB_MR_REREG_TRANS) ? length : mr->umem->length; 1309 int page_shift = 0; 1310 int upd_flags = 0; 1311 int npages = 0; 1312 int ncont = 0; 1313 int order = 0; 1314 int err; 1315 1316 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", 1317 start, virt_addr, length, access_flags); 1318 1319 atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); 1320 1321 if (flags != IB_MR_REREG_PD) { 1322 /* 1323 * Replace umem. This needs to be done whether or not UMR is 1324 * used. 1325 */ 1326 flags |= IB_MR_REREG_TRANS; 1327 ib_umem_release(mr->umem); 1328 err = mr_umem_get(pd, addr, len, access_flags, &mr->umem, 1329 &npages, &page_shift, &ncont, &order); 1330 if (err < 0) { 1331 clean_mr(mr); 1332 return err; 1333 } 1334 } 1335 1336 if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) { 1337 /* 1338 * UMR can't be used - MKey needs to be replaced. 1339 */ 1340 if (mr->umred) { 1341 err = unreg_umr(dev, mr); 1342 if (err) 1343 mlx5_ib_warn(dev, "Failed to unregister MR\n"); 1344 } else { 1345 err = destroy_mkey(dev, mr); 1346 if (err) 1347 mlx5_ib_warn(dev, "Failed to destroy MKey\n"); 1348 } 1349 if (err) 1350 return err; 1351 1352 mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, 1353 page_shift, access_flags); 1354 1355 if (IS_ERR(mr)) 1356 return PTR_ERR(mr); 1357 1358 mr->umred = 0; 1359 } else { 1360 /* 1361 * Send a UMR WQE 1362 */ 1363 mr->ibmr.pd = pd; 1364 mr->access_flags = access_flags; 1365 mr->mmkey.iova = addr; 1366 mr->mmkey.size = len; 1367 mr->mmkey.pd = to_mpd(pd)->pdn; 1368 1369 if (flags & IB_MR_REREG_TRANS) { 1370 upd_flags = MLX5_IB_UPD_XLT_ADDR; 1371 if (flags & IB_MR_REREG_PD) 1372 upd_flags |= MLX5_IB_UPD_XLT_PD; 1373 if (flags & IB_MR_REREG_ACCESS) 1374 upd_flags |= MLX5_IB_UPD_XLT_ACCESS; 1375 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, 1376 upd_flags); 1377 } else { 1378 err = rereg_umr(pd, mr, access_flags, flags); 1379 } 1380 1381 if (err) { 1382 mlx5_ib_warn(dev, "Failed to rereg UMR\n"); 1383 ib_umem_release(mr->umem); 1384 clean_mr(mr); 1385 return err; 1386 } 1387 } 1388 1389 set_mr_fileds(dev, mr, npages, len, access_flags); 1390 1391 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1392 update_odp_mr(mr); 1393 #endif 1394 return 0; 1395 } 1396 1397 static int 1398 mlx5_alloc_priv_descs(struct ib_device *device, 1399 struct mlx5_ib_mr *mr, 1400 int ndescs, 1401 int desc_size) 1402 { 1403 int size = ndescs * desc_size; 1404 int add_size; 1405 int ret; 1406 1407 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); 1408 1409 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); 1410 if (!mr->descs_alloc) 1411 return -ENOMEM; 1412 1413 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); 1414 1415 mr->desc_map = dma_map_single(device->dev.parent, mr->descs, 1416 size, DMA_TO_DEVICE); 1417 if (dma_mapping_error(device->dev.parent, mr->desc_map)) { 1418 ret = -ENOMEM; 1419 goto err; 1420 } 1421 1422 return 0; 1423 err: 1424 kfree(mr->descs_alloc); 1425 1426 return ret; 1427 } 1428 1429 static void 1430 mlx5_free_priv_descs(struct mlx5_ib_mr *mr) 1431 { 1432 if (mr->descs) { 1433 struct ib_device *device = mr->ibmr.device; 1434 int size = mr->max_descs * mr->desc_size; 1435 1436 dma_unmap_single(device->dev.parent, mr->desc_map, 1437 size, DMA_TO_DEVICE); 1438 kfree(mr->descs_alloc); 1439 mr->descs = NULL; 1440 } 1441 } 1442 1443 static int clean_mr(struct mlx5_ib_mr *mr) 1444 { 1445 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); 1446 int umred = mr->umred; 1447 int err; 1448 1449 if (mr->sig) { 1450 if (mlx5_core_destroy_psv(dev->mdev, 1451 mr->sig->psv_memory.psv_idx)) 1452 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", 1453 mr->sig->psv_memory.psv_idx); 1454 if (mlx5_core_destroy_psv(dev->mdev, 1455 mr->sig->psv_wire.psv_idx)) 1456 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", 1457 mr->sig->psv_wire.psv_idx); 1458 kfree(mr->sig); 1459 mr->sig = NULL; 1460 } 1461 1462 mlx5_free_priv_descs(mr); 1463 1464 if (!umred) { 1465 err = destroy_mkey(dev, mr); 1466 if (err) { 1467 mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n", 1468 mr->mmkey.key, err); 1469 return err; 1470 } 1471 } else { 1472 mlx5_mr_cache_free(dev, mr); 1473 } 1474 1475 if (!umred) 1476 kfree(mr); 1477 1478 return 0; 1479 } 1480 1481 int mlx5_ib_dereg_mr(struct ib_mr *ibmr) 1482 { 1483 struct mlx5_ib_dev *dev = to_mdev(ibmr->device); 1484 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1485 int npages = mr->npages; 1486 struct ib_umem *umem = mr->umem; 1487 1488 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1489 if (umem && umem->odp_data) { 1490 /* Prevent new page faults from succeeding */ 1491 mr->live = 0; 1492 /* Wait for all running page-fault handlers to finish. */ 1493 synchronize_srcu(&dev->mr_srcu); 1494 /* Destroy all page mappings */ 1495 if (umem->odp_data->page_list) 1496 mlx5_ib_invalidate_range(umem, ib_umem_start(umem), 1497 ib_umem_end(umem)); 1498 else 1499 mlx5_ib_free_implicit_mr(mr); 1500 /* 1501 * We kill the umem before the MR for ODP, 1502 * so that there will not be any invalidations in 1503 * flight, looking at the *mr struct. 1504 */ 1505 ib_umem_release(umem); 1506 atomic_sub(npages, &dev->mdev->priv.reg_pages); 1507 1508 /* Avoid double-freeing the umem. */ 1509 umem = NULL; 1510 } 1511 #endif 1512 1513 clean_mr(mr); 1514 1515 if (umem) { 1516 ib_umem_release(umem); 1517 atomic_sub(npages, &dev->mdev->priv.reg_pages); 1518 } 1519 1520 return 0; 1521 } 1522 1523 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 1524 enum ib_mr_type mr_type, 1525 u32 max_num_sg) 1526 { 1527 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1528 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1529 int ndescs = ALIGN(max_num_sg, 4); 1530 struct mlx5_ib_mr *mr; 1531 void *mkc; 1532 u32 *in; 1533 int err; 1534 1535 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1536 if (!mr) 1537 return ERR_PTR(-ENOMEM); 1538 1539 in = kzalloc(inlen, GFP_KERNEL); 1540 if (!in) { 1541 err = -ENOMEM; 1542 goto err_free; 1543 } 1544 1545 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1546 MLX5_SET(mkc, mkc, free, 1); 1547 MLX5_SET(mkc, mkc, translations_octword_size, ndescs); 1548 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1549 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 1550 1551 if (mr_type == IB_MR_TYPE_MEM_REG) { 1552 mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT; 1553 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); 1554 err = mlx5_alloc_priv_descs(pd->device, mr, 1555 ndescs, sizeof(struct mlx5_mtt)); 1556 if (err) 1557 goto err_free_in; 1558 1559 mr->desc_size = sizeof(struct mlx5_mtt); 1560 mr->max_descs = ndescs; 1561 } else if (mr_type == IB_MR_TYPE_SG_GAPS) { 1562 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; 1563 1564 err = mlx5_alloc_priv_descs(pd->device, mr, 1565 ndescs, sizeof(struct mlx5_klm)); 1566 if (err) 1567 goto err_free_in; 1568 mr->desc_size = sizeof(struct mlx5_klm); 1569 mr->max_descs = ndescs; 1570 } else if (mr_type == IB_MR_TYPE_SIGNATURE) { 1571 u32 psv_index[2]; 1572 1573 MLX5_SET(mkc, mkc, bsf_en, 1); 1574 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); 1575 mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); 1576 if (!mr->sig) { 1577 err = -ENOMEM; 1578 goto err_free_in; 1579 } 1580 1581 /* create mem & wire PSVs */ 1582 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, 1583 2, psv_index); 1584 if (err) 1585 goto err_free_sig; 1586 1587 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; 1588 mr->sig->psv_memory.psv_idx = psv_index[0]; 1589 mr->sig->psv_wire.psv_idx = psv_index[1]; 1590 1591 mr->sig->sig_status_checked = true; 1592 mr->sig->sig_err_exists = false; 1593 /* Next UMR, Arm SIGERR */ 1594 ++mr->sig->sigerr_count; 1595 } else { 1596 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); 1597 err = -EINVAL; 1598 goto err_free_in; 1599 } 1600 1601 MLX5_SET(mkc, mkc, access_mode, mr->access_mode); 1602 MLX5_SET(mkc, mkc, umr_en, 1); 1603 1604 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); 1605 if (err) 1606 goto err_destroy_psv; 1607 1608 mr->mmkey.type = MLX5_MKEY_MR; 1609 mr->ibmr.lkey = mr->mmkey.key; 1610 mr->ibmr.rkey = mr->mmkey.key; 1611 mr->umem = NULL; 1612 kfree(in); 1613 1614 return &mr->ibmr; 1615 1616 err_destroy_psv: 1617 if (mr->sig) { 1618 if (mlx5_core_destroy_psv(dev->mdev, 1619 mr->sig->psv_memory.psv_idx)) 1620 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", 1621 mr->sig->psv_memory.psv_idx); 1622 if (mlx5_core_destroy_psv(dev->mdev, 1623 mr->sig->psv_wire.psv_idx)) 1624 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", 1625 mr->sig->psv_wire.psv_idx); 1626 } 1627 mlx5_free_priv_descs(mr); 1628 err_free_sig: 1629 kfree(mr->sig); 1630 err_free_in: 1631 kfree(in); 1632 err_free: 1633 kfree(mr); 1634 return ERR_PTR(err); 1635 } 1636 1637 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1638 struct ib_udata *udata) 1639 { 1640 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1641 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1642 struct mlx5_ib_mw *mw = NULL; 1643 u32 *in = NULL; 1644 void *mkc; 1645 int ndescs; 1646 int err; 1647 struct mlx5_ib_alloc_mw req = {}; 1648 struct { 1649 __u32 comp_mask; 1650 __u32 response_length; 1651 } resp = {}; 1652 1653 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1654 if (err) 1655 return ERR_PTR(err); 1656 1657 if (req.comp_mask || req.reserved1 || req.reserved2) 1658 return ERR_PTR(-EOPNOTSUPP); 1659 1660 if (udata->inlen > sizeof(req) && 1661 !ib_is_udata_cleared(udata, sizeof(req), 1662 udata->inlen - sizeof(req))) 1663 return ERR_PTR(-EOPNOTSUPP); 1664 1665 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); 1666 1667 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 1668 in = kzalloc(inlen, GFP_KERNEL); 1669 if (!mw || !in) { 1670 err = -ENOMEM; 1671 goto free; 1672 } 1673 1674 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1675 1676 MLX5_SET(mkc, mkc, free, 1); 1677 MLX5_SET(mkc, mkc, translations_octword_size, ndescs); 1678 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 1679 MLX5_SET(mkc, mkc, umr_en, 1); 1680 MLX5_SET(mkc, mkc, lr, 1); 1681 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS); 1682 MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); 1683 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1684 1685 err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen); 1686 if (err) 1687 goto free; 1688 1689 mw->mmkey.type = MLX5_MKEY_MW; 1690 mw->ibmw.rkey = mw->mmkey.key; 1691 mw->ndescs = ndescs; 1692 1693 resp.response_length = min(offsetof(typeof(resp), response_length) + 1694 sizeof(resp.response_length), udata->outlen); 1695 if (resp.response_length) { 1696 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1697 if (err) { 1698 mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); 1699 goto free; 1700 } 1701 } 1702 1703 kfree(in); 1704 return &mw->ibmw; 1705 1706 free: 1707 kfree(mw); 1708 kfree(in); 1709 return ERR_PTR(err); 1710 } 1711 1712 int mlx5_ib_dealloc_mw(struct ib_mw *mw) 1713 { 1714 struct mlx5_ib_mw *mmw = to_mmw(mw); 1715 int err; 1716 1717 err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev, 1718 &mmw->mmkey); 1719 if (!err) 1720 kfree(mmw); 1721 return err; 1722 } 1723 1724 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1725 struct ib_mr_status *mr_status) 1726 { 1727 struct mlx5_ib_mr *mmr = to_mmr(ibmr); 1728 int ret = 0; 1729 1730 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { 1731 pr_err("Invalid status check mask\n"); 1732 ret = -EINVAL; 1733 goto done; 1734 } 1735 1736 mr_status->fail_status = 0; 1737 if (check_mask & IB_MR_CHECK_SIG_STATUS) { 1738 if (!mmr->sig) { 1739 ret = -EINVAL; 1740 pr_err("signature status check requested on a non-signature enabled MR\n"); 1741 goto done; 1742 } 1743 1744 mmr->sig->sig_status_checked = true; 1745 if (!mmr->sig->sig_err_exists) 1746 goto done; 1747 1748 if (ibmr->lkey == mmr->sig->err_item.key) 1749 memcpy(&mr_status->sig_err, &mmr->sig->err_item, 1750 sizeof(mr_status->sig_err)); 1751 else { 1752 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; 1753 mr_status->sig_err.sig_err_offset = 0; 1754 mr_status->sig_err.key = mmr->sig->err_item.key; 1755 } 1756 1757 mmr->sig->sig_err_exists = false; 1758 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; 1759 } 1760 1761 done: 1762 return ret; 1763 } 1764 1765 static int 1766 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, 1767 struct scatterlist *sgl, 1768 unsigned short sg_nents, 1769 unsigned int *sg_offset_p) 1770 { 1771 struct scatterlist *sg = sgl; 1772 struct mlx5_klm *klms = mr->descs; 1773 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; 1774 u32 lkey = mr->ibmr.pd->local_dma_lkey; 1775 int i; 1776 1777 mr->ibmr.iova = sg_dma_address(sg) + sg_offset; 1778 mr->ibmr.length = 0; 1779 mr->ndescs = sg_nents; 1780 1781 for_each_sg(sgl, sg, sg_nents, i) { 1782 if (unlikely(i > mr->max_descs)) 1783 break; 1784 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); 1785 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); 1786 klms[i].key = cpu_to_be32(lkey); 1787 mr->ibmr.length += sg_dma_len(sg) - sg_offset; 1788 1789 sg_offset = 0; 1790 } 1791 1792 if (sg_offset_p) 1793 *sg_offset_p = sg_offset; 1794 1795 return i; 1796 } 1797 1798 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) 1799 { 1800 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1801 __be64 *descs; 1802 1803 if (unlikely(mr->ndescs == mr->max_descs)) 1804 return -ENOMEM; 1805 1806 descs = mr->descs; 1807 descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); 1808 1809 return 0; 1810 } 1811 1812 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1813 unsigned int *sg_offset) 1814 { 1815 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1816 int n; 1817 1818 mr->ndescs = 0; 1819 1820 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, 1821 mr->desc_size * mr->max_descs, 1822 DMA_TO_DEVICE); 1823 1824 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 1825 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset); 1826 else 1827 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, 1828 mlx5_set_page); 1829 1830 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, 1831 mr->desc_size * mr->max_descs, 1832 DMA_TO_DEVICE); 1833 1834 return n; 1835 } 1836