1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 49 #define mlx5_ib_dbg(dev, format, arg...) \ 50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_err(dev, format, arg...) \ 54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define mlx5_ib_warn(dev, format, arg...) \ 58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 59 __LINE__, current->pid, ##arg) 60 61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 62 sizeof(((type *)0)->fld) <= (sz)) 63 #define MLX5_IB_DEFAULT_UIDX 0xffffff 64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 65 66 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 67 68 enum { 69 MLX5_IB_MMAP_CMD_SHIFT = 8, 70 MLX5_IB_MMAP_CMD_MASK = 0xff, 71 }; 72 73 enum mlx5_ib_mmap_cmd { 74 MLX5_IB_MMAP_REGULAR_PAGE = 0, 75 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 76 MLX5_IB_MMAP_WC_PAGE = 2, 77 MLX5_IB_MMAP_NC_PAGE = 3, 78 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 79 MLX5_IB_MMAP_CORE_CLOCK = 5, 80 }; 81 82 enum { 83 MLX5_RES_SCAT_DATA32_CQE = 0x1, 84 MLX5_RES_SCAT_DATA64_CQE = 0x2, 85 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 86 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 87 }; 88 89 enum mlx5_ib_latency_class { 90 MLX5_IB_LATENCY_CLASS_LOW, 91 MLX5_IB_LATENCY_CLASS_MEDIUM, 92 MLX5_IB_LATENCY_CLASS_HIGH, 93 MLX5_IB_LATENCY_CLASS_FAST_PATH 94 }; 95 96 enum mlx5_ib_mad_ifc_flags { 97 MLX5_MAD_IFC_IGNORE_MKEY = 1, 98 MLX5_MAD_IFC_IGNORE_BKEY = 2, 99 MLX5_MAD_IFC_NET_VIEW = 4, 100 }; 101 102 enum { 103 MLX5_CROSS_CHANNEL_UUAR = 0, 104 }; 105 106 enum { 107 MLX5_CQE_VERSION_V0, 108 MLX5_CQE_VERSION_V1, 109 }; 110 111 struct mlx5_ib_vma_private_data { 112 struct list_head list; 113 struct vm_area_struct *vma; 114 }; 115 116 struct mlx5_ib_ucontext { 117 struct ib_ucontext ibucontext; 118 struct list_head db_page_list; 119 120 /* protect doorbell record alloc/free 121 */ 122 struct mutex db_page_mutex; 123 struct mlx5_uuar_info uuari; 124 u8 cqe_version; 125 /* Transport Domain number */ 126 u32 tdn; 127 struct list_head vma_private_list; 128 129 unsigned long upd_xlt_page; 130 /* protect ODP/KSM */ 131 struct mutex upd_xlt_page_mutex; 132 }; 133 134 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 135 { 136 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 137 } 138 139 struct mlx5_ib_pd { 140 struct ib_pd ibpd; 141 u32 pdn; 142 }; 143 144 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 145 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 146 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 147 #error "Invalid number of bypass priorities" 148 #endif 149 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 150 151 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 152 #define MLX5_IB_NUM_SNIFFER_FTS 2 153 struct mlx5_ib_flow_prio { 154 struct mlx5_flow_table *flow_table; 155 unsigned int refcount; 156 }; 157 158 struct mlx5_ib_flow_handler { 159 struct list_head list; 160 struct ib_flow ibflow; 161 struct mlx5_ib_flow_prio *prio; 162 struct mlx5_flow_handle *rule; 163 }; 164 165 struct mlx5_ib_flow_db { 166 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 167 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 168 struct mlx5_flow_table *lag_demux_ft; 169 /* Protect flow steering bypass flow tables 170 * when add/del flow rules. 171 * only single add/removal of flow steering rule could be done 172 * simultaneously. 173 */ 174 struct mutex lock; 175 }; 176 177 /* Use macros here so that don't have to duplicate 178 * enum ib_send_flags and enum ib_qp_type for low-level driver 179 */ 180 181 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 182 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 183 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 184 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 185 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 186 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 187 188 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 189 /* 190 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 191 * creates the actual hardware QP. 192 */ 193 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 194 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 195 196 #define MLX5_IB_UMR_OCTOWORD 16 197 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 198 199 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 200 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 201 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 202 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 203 #define MLX5_IB_UPD_XLT_PD BIT(4) 204 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 205 206 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 207 * 208 * These flags are intended for internal use by the mlx5_ib driver, and they 209 * rely on the range reserved for that use in the ib_qp_create_flags enum. 210 */ 211 212 /* Create a UD QP whose source QP number is 1 */ 213 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 214 { 215 return IB_QP_CREATE_RESERVED_START; 216 } 217 218 struct wr_list { 219 u16 opcode; 220 u16 next; 221 }; 222 223 struct mlx5_ib_wq { 224 u64 *wrid; 225 u32 *wr_data; 226 struct wr_list *w_list; 227 unsigned *wqe_head; 228 u16 unsig_count; 229 230 /* serialize post to the work queue 231 */ 232 spinlock_t lock; 233 int wqe_cnt; 234 int max_post; 235 int max_gs; 236 int offset; 237 int wqe_shift; 238 unsigned head; 239 unsigned tail; 240 u16 cur_post; 241 u16 last_poll; 242 void *qend; 243 }; 244 245 struct mlx5_ib_rwq { 246 struct ib_wq ibwq; 247 struct mlx5_core_qp core_qp; 248 u32 rq_num_pas; 249 u32 log_rq_stride; 250 u32 log_rq_size; 251 u32 rq_page_offset; 252 u32 log_page_size; 253 struct ib_umem *umem; 254 size_t buf_size; 255 unsigned int page_shift; 256 int create_type; 257 struct mlx5_db db; 258 u32 user_index; 259 u32 wqe_count; 260 u32 wqe_shift; 261 int wq_sig; 262 }; 263 264 enum { 265 MLX5_QP_USER, 266 MLX5_QP_KERNEL, 267 MLX5_QP_EMPTY 268 }; 269 270 enum { 271 MLX5_WQ_USER, 272 MLX5_WQ_KERNEL 273 }; 274 275 struct mlx5_ib_rwq_ind_table { 276 struct ib_rwq_ind_table ib_rwq_ind_tbl; 277 u32 rqtn; 278 }; 279 280 struct mlx5_ib_ubuffer { 281 struct ib_umem *umem; 282 int buf_size; 283 u64 buf_addr; 284 }; 285 286 struct mlx5_ib_qp_base { 287 struct mlx5_ib_qp *container_mibqp; 288 struct mlx5_core_qp mqp; 289 struct mlx5_ib_ubuffer ubuffer; 290 }; 291 292 struct mlx5_ib_qp_trans { 293 struct mlx5_ib_qp_base base; 294 u16 xrcdn; 295 u8 alt_port; 296 u8 atomic_rd_en; 297 u8 resp_depth; 298 }; 299 300 struct mlx5_ib_rss_qp { 301 u32 tirn; 302 }; 303 304 struct mlx5_ib_rq { 305 struct mlx5_ib_qp_base base; 306 struct mlx5_ib_wq *rq; 307 struct mlx5_ib_ubuffer ubuffer; 308 struct mlx5_db *doorbell; 309 u32 tirn; 310 u8 state; 311 }; 312 313 struct mlx5_ib_sq { 314 struct mlx5_ib_qp_base base; 315 struct mlx5_ib_wq *sq; 316 struct mlx5_ib_ubuffer ubuffer; 317 struct mlx5_db *doorbell; 318 u32 tisn; 319 u8 state; 320 }; 321 322 struct mlx5_ib_raw_packet_qp { 323 struct mlx5_ib_sq sq; 324 struct mlx5_ib_rq rq; 325 }; 326 327 struct mlx5_ib_qp { 328 struct ib_qp ibqp; 329 union { 330 struct mlx5_ib_qp_trans trans_qp; 331 struct mlx5_ib_raw_packet_qp raw_packet_qp; 332 struct mlx5_ib_rss_qp rss_qp; 333 }; 334 struct mlx5_buf buf; 335 336 struct mlx5_db db; 337 struct mlx5_ib_wq rq; 338 339 u8 sq_signal_bits; 340 u8 fm_cache; 341 struct mlx5_ib_wq sq; 342 343 /* serialize qp state modifications 344 */ 345 struct mutex mutex; 346 u32 flags; 347 u8 port; 348 u8 state; 349 int wq_sig; 350 int scat_cqe; 351 int max_inline_data; 352 struct mlx5_bf *bf; 353 int has_rq; 354 355 /* only for user space QPs. For kernel 356 * we have it from the bf object 357 */ 358 int uuarn; 359 360 int create_type; 361 362 /* Store signature errors */ 363 bool signature_en; 364 365 struct list_head qps_list; 366 struct list_head cq_recv_list; 367 struct list_head cq_send_list; 368 u32 rate_limit; 369 }; 370 371 struct mlx5_ib_cq_buf { 372 struct mlx5_buf buf; 373 struct ib_umem *umem; 374 int cqe_size; 375 int nent; 376 }; 377 378 enum mlx5_ib_qp_flags { 379 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 380 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 381 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 382 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 383 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 384 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 385 /* QP uses 1 as its source QP number */ 386 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 387 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 388 MLX5_IB_QP_RSS = 1 << 8, 389 }; 390 391 struct mlx5_umr_wr { 392 struct ib_send_wr wr; 393 u64 virt_addr; 394 u64 offset; 395 struct ib_pd *pd; 396 unsigned int page_shift; 397 unsigned int xlt_size; 398 u64 length; 399 int access_flags; 400 u32 mkey; 401 }; 402 403 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 404 { 405 return container_of(wr, struct mlx5_umr_wr, wr); 406 } 407 408 struct mlx5_shared_mr_info { 409 int mr_id; 410 struct ib_umem *umem; 411 }; 412 413 struct mlx5_ib_cq { 414 struct ib_cq ibcq; 415 struct mlx5_core_cq mcq; 416 struct mlx5_ib_cq_buf buf; 417 struct mlx5_db db; 418 419 /* serialize access to the CQ 420 */ 421 spinlock_t lock; 422 423 /* protect resize cq 424 */ 425 struct mutex resize_mutex; 426 struct mlx5_ib_cq_buf *resize_buf; 427 struct ib_umem *resize_umem; 428 int cqe_size; 429 struct list_head list_send_qp; 430 struct list_head list_recv_qp; 431 u32 create_flags; 432 struct list_head wc_list; 433 enum ib_cq_notify_flags notify_flags; 434 struct work_struct notify_work; 435 }; 436 437 struct mlx5_ib_wc { 438 struct ib_wc wc; 439 struct list_head list; 440 }; 441 442 struct mlx5_ib_srq { 443 struct ib_srq ibsrq; 444 struct mlx5_core_srq msrq; 445 struct mlx5_buf buf; 446 struct mlx5_db db; 447 u64 *wrid; 448 /* protect SRQ hanlding 449 */ 450 spinlock_t lock; 451 int head; 452 int tail; 453 u16 wqe_ctr; 454 struct ib_umem *umem; 455 /* serialize arming a SRQ 456 */ 457 struct mutex mutex; 458 int wq_sig; 459 }; 460 461 struct mlx5_ib_xrcd { 462 struct ib_xrcd ibxrcd; 463 u32 xrcdn; 464 }; 465 466 enum mlx5_ib_mtt_access_flags { 467 MLX5_IB_MTT_READ = (1 << 0), 468 MLX5_IB_MTT_WRITE = (1 << 1), 469 }; 470 471 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 472 473 struct mlx5_ib_mr { 474 struct ib_mr ibmr; 475 void *descs; 476 dma_addr_t desc_map; 477 int ndescs; 478 int max_descs; 479 int desc_size; 480 int access_mode; 481 struct mlx5_core_mkey mmkey; 482 struct ib_umem *umem; 483 struct mlx5_shared_mr_info *smr_info; 484 struct list_head list; 485 int order; 486 int umred; 487 int npages; 488 struct mlx5_ib_dev *dev; 489 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 490 struct mlx5_core_sig_ctx *sig; 491 int live; 492 void *descs_alloc; 493 int access_flags; /* Needed for rereg MR */ 494 }; 495 496 struct mlx5_ib_mw { 497 struct ib_mw ibmw; 498 struct mlx5_core_mkey mmkey; 499 }; 500 501 struct mlx5_ib_umr_context { 502 struct ib_cqe cqe; 503 enum ib_wc_status status; 504 struct completion done; 505 }; 506 507 struct umr_common { 508 struct ib_pd *pd; 509 struct ib_cq *cq; 510 struct ib_qp *qp; 511 /* control access to UMR QP 512 */ 513 struct semaphore sem; 514 }; 515 516 enum { 517 MLX5_FMR_INVALID, 518 MLX5_FMR_VALID, 519 MLX5_FMR_BUSY, 520 }; 521 522 struct mlx5_cache_ent { 523 struct list_head head; 524 /* sync access to the cahce entry 525 */ 526 spinlock_t lock; 527 528 529 struct dentry *dir; 530 char name[4]; 531 u32 order; 532 u32 size; 533 u32 cur; 534 u32 miss; 535 u32 limit; 536 537 struct dentry *fsize; 538 struct dentry *fcur; 539 struct dentry *fmiss; 540 struct dentry *flimit; 541 542 struct mlx5_ib_dev *dev; 543 struct work_struct work; 544 struct delayed_work dwork; 545 int pending; 546 }; 547 548 struct mlx5_mr_cache { 549 struct workqueue_struct *wq; 550 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 551 int stopped; 552 struct dentry *root; 553 unsigned long last_add; 554 }; 555 556 struct mlx5_ib_gsi_qp; 557 558 struct mlx5_ib_port_resources { 559 struct mlx5_ib_resources *devr; 560 struct mlx5_ib_gsi_qp *gsi; 561 struct work_struct pkey_change_work; 562 }; 563 564 struct mlx5_ib_resources { 565 struct ib_cq *c0; 566 struct ib_xrcd *x0; 567 struct ib_xrcd *x1; 568 struct ib_pd *p0; 569 struct ib_srq *s0; 570 struct ib_srq *s1; 571 struct mlx5_ib_port_resources ports[2]; 572 /* Protects changes to the port resources */ 573 struct mutex mutex; 574 }; 575 576 struct mlx5_ib_port { 577 u16 q_cnt_id; 578 }; 579 580 struct mlx5_roce { 581 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 582 * netdev pointer 583 */ 584 rwlock_t netdev_lock; 585 struct net_device *netdev; 586 struct notifier_block nb; 587 atomic_t next_port; 588 }; 589 590 struct mlx5_ib_dev { 591 struct ib_device ib_dev; 592 struct mlx5_core_dev *mdev; 593 struct mlx5_roce roce; 594 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 595 int num_ports; 596 /* serialize update of capability mask 597 */ 598 struct mutex cap_mask_mutex; 599 bool ib_active; 600 struct umr_common umrc; 601 /* sync used page count stats 602 */ 603 struct mlx5_ib_resources devr; 604 struct mlx5_mr_cache cache; 605 struct timer_list delay_timer; 606 /* Prevents soft lock on massive reg MRs */ 607 struct mutex slow_path_mutex; 608 int fill_delay; 609 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 610 struct ib_odp_caps odp_caps; 611 u64 odp_max_size; 612 /* 613 * Sleepable RCU that prevents destruction of MRs while they are still 614 * being used by a page fault handler. 615 */ 616 struct srcu_struct mr_srcu; 617 #endif 618 struct mlx5_ib_flow_db flow_db; 619 /* protect resources needed as part of reset flow */ 620 spinlock_t reset_flow_resource_lock; 621 struct list_head qp_list; 622 /* Array with num_ports elements */ 623 struct mlx5_ib_port *port; 624 }; 625 626 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 627 { 628 return container_of(mcq, struct mlx5_ib_cq, mcq); 629 } 630 631 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 632 { 633 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 634 } 635 636 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 637 { 638 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 639 } 640 641 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 642 { 643 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 644 } 645 646 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 647 { 648 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 649 } 650 651 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 652 { 653 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 654 } 655 656 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 657 { 658 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 659 } 660 661 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 662 { 663 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 664 } 665 666 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 667 { 668 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 669 } 670 671 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 672 { 673 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 674 } 675 676 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 677 { 678 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 679 } 680 681 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 682 { 683 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 684 } 685 686 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 687 { 688 return container_of(msrq, struct mlx5_ib_srq, msrq); 689 } 690 691 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 692 { 693 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 694 } 695 696 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 697 { 698 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 699 } 700 701 struct mlx5_ib_ah { 702 struct ib_ah ibah; 703 struct mlx5_av av; 704 }; 705 706 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 707 { 708 return container_of(ibah, struct mlx5_ib_ah, ibah); 709 } 710 711 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 712 struct mlx5_db *db); 713 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 714 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 715 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 716 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 717 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 718 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 719 const void *in_mad, void *response_mad); 720 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr, 721 struct ib_udata *udata); 722 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 723 int mlx5_ib_destroy_ah(struct ib_ah *ah); 724 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 725 struct ib_srq_init_attr *init_attr, 726 struct ib_udata *udata); 727 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 728 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 729 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 730 int mlx5_ib_destroy_srq(struct ib_srq *srq); 731 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 732 struct ib_recv_wr **bad_wr); 733 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 734 struct ib_qp_init_attr *init_attr, 735 struct ib_udata *udata); 736 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 737 int attr_mask, struct ib_udata *udata); 738 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 739 struct ib_qp_init_attr *qp_init_attr); 740 int mlx5_ib_destroy_qp(struct ib_qp *qp); 741 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 742 struct ib_send_wr **bad_wr); 743 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 744 struct ib_recv_wr **bad_wr); 745 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 746 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 747 void *buffer, u32 length, 748 struct mlx5_ib_qp_base *base); 749 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 750 const struct ib_cq_init_attr *attr, 751 struct ib_ucontext *context, 752 struct ib_udata *udata); 753 int mlx5_ib_destroy_cq(struct ib_cq *cq); 754 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 755 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 756 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 757 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 758 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 759 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 760 u64 virt_addr, int access_flags, 761 struct ib_udata *udata); 762 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 763 struct ib_udata *udata); 764 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 765 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 766 int page_shift, int flags); 767 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 768 u64 length, u64 virt_addr, int access_flags, 769 struct ib_pd *pd, struct ib_udata *udata); 770 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 771 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 772 enum ib_mr_type mr_type, 773 u32 max_num_sg); 774 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 775 unsigned int *sg_offset); 776 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 777 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 778 const struct ib_mad_hdr *in, size_t in_mad_size, 779 struct ib_mad_hdr *out, size_t *out_mad_size, 780 u16 *out_mad_pkey_index); 781 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 782 struct ib_ucontext *context, 783 struct ib_udata *udata); 784 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 785 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 786 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 787 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 788 struct ib_smp *out_mad); 789 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 790 __be64 *sys_image_guid); 791 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 792 u16 *max_pkeys); 793 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 794 u32 *vendor_id); 795 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 796 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 797 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 798 u16 *pkey); 799 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 800 union ib_gid *gid); 801 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 802 struct ib_port_attr *props); 803 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 804 struct ib_port_attr *props); 805 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 806 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 807 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 808 unsigned long max_page_shift, 809 int *count, int *shift, 810 int *ncont, int *order); 811 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 812 int page_shift, size_t offset, size_t num_pages, 813 __be64 *pas, int access_flags); 814 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 815 int page_shift, __be64 *pas, int access_flags); 816 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 817 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 818 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 819 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 820 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 821 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 822 struct ib_mr_status *mr_status); 823 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 824 struct ib_wq_init_attr *init_attr, 825 struct ib_udata *udata); 826 int mlx5_ib_destroy_wq(struct ib_wq *wq); 827 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 828 u32 wq_attr_mask, struct ib_udata *udata); 829 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 830 struct ib_rwq_ind_table_init_attr *init_attr, 831 struct ib_udata *udata); 832 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 833 834 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 835 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 836 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, 837 struct mlx5_pagefault *pfault); 838 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 839 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 840 int __init mlx5_ib_odp_init(void); 841 void mlx5_ib_odp_cleanup(void); 842 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 843 unsigned long end); 844 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 845 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 846 { 847 return; 848 } 849 850 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 851 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 852 static inline int mlx5_ib_odp_init(void) { return 0; } 853 static inline void mlx5_ib_odp_cleanup(void) {} 854 855 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 856 857 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 858 u8 port, struct ifla_vf_info *info); 859 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 860 u8 port, int state); 861 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 862 u8 port, struct ifla_vf_stats *stats); 863 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 864 u64 guid, int type); 865 866 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 867 int index); 868 869 /* GSI QP helper functions */ 870 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 871 struct ib_qp_init_attr *init_attr); 872 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 873 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 874 int attr_mask); 875 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 876 int qp_attr_mask, 877 struct ib_qp_init_attr *qp_init_attr); 878 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 879 struct ib_send_wr **bad_wr); 880 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 881 struct ib_recv_wr **bad_wr); 882 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 883 884 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 885 886 static inline void init_query_mad(struct ib_smp *mad) 887 { 888 mad->base_version = 1; 889 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 890 mad->class_version = 1; 891 mad->method = IB_MGMT_METHOD_GET; 892 } 893 894 static inline u8 convert_access(int acc) 895 { 896 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 897 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 898 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 899 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 900 MLX5_PERM_LOCAL_READ; 901 } 902 903 static inline int is_qp1(enum ib_qp_type qp_type) 904 { 905 return qp_type == MLX5_IB_QPT_HW_GSI; 906 } 907 908 #define MLX5_MAX_UMR_SHIFT 16 909 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 910 911 static inline u32 check_cq_create_flags(u32 flags) 912 { 913 /* 914 * It returns non-zero value for unsupported CQ 915 * create flags, otherwise it returns zero. 916 */ 917 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 918 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 919 } 920 921 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 922 u32 *user_index) 923 { 924 if (cqe_version) { 925 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 926 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 927 return -EINVAL; 928 *user_index = cmd_uidx; 929 } else { 930 *user_index = MLX5_IB_DEFAULT_UIDX; 931 } 932 933 return 0; 934 } 935 936 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 937 struct mlx5_ib_create_qp *ucmd, 938 int inlen, 939 u32 *user_index) 940 { 941 u8 cqe_version = ucontext->cqe_version; 942 943 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 944 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 945 return 0; 946 947 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 948 !!cqe_version)) 949 return -EINVAL; 950 951 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 952 } 953 954 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 955 struct mlx5_ib_create_srq *ucmd, 956 int inlen, 957 u32 *user_index) 958 { 959 u8 cqe_version = ucontext->cqe_version; 960 961 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 962 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 963 return 0; 964 965 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 966 !!cqe_version)) 967 return -EINVAL; 968 969 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 970 } 971 #endif /* MLX5_IB_H */ 972