1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 49 #define mlx5_ib_dbg(dev, format, arg...) \ 50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_err(dev, format, arg...) \ 54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define mlx5_ib_warn(dev, format, arg...) \ 58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 59 __LINE__, current->pid, ##arg) 60 61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 62 sizeof(((type *)0)->fld) <= (sz)) 63 #define MLX5_IB_DEFAULT_UIDX 0xffffff 64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 65 66 enum { 67 MLX5_IB_MMAP_CMD_SHIFT = 8, 68 MLX5_IB_MMAP_CMD_MASK = 0xff, 69 }; 70 71 enum mlx5_ib_mmap_cmd { 72 MLX5_IB_MMAP_REGULAR_PAGE = 0, 73 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 74 MLX5_IB_MMAP_WC_PAGE = 2, 75 MLX5_IB_MMAP_NC_PAGE = 3, 76 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 77 MLX5_IB_MMAP_CORE_CLOCK = 5, 78 }; 79 80 enum { 81 MLX5_RES_SCAT_DATA32_CQE = 0x1, 82 MLX5_RES_SCAT_DATA64_CQE = 0x2, 83 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 84 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 85 }; 86 87 enum mlx5_ib_latency_class { 88 MLX5_IB_LATENCY_CLASS_LOW, 89 MLX5_IB_LATENCY_CLASS_MEDIUM, 90 MLX5_IB_LATENCY_CLASS_HIGH, 91 MLX5_IB_LATENCY_CLASS_FAST_PATH 92 }; 93 94 enum mlx5_ib_mad_ifc_flags { 95 MLX5_MAD_IFC_IGNORE_MKEY = 1, 96 MLX5_MAD_IFC_IGNORE_BKEY = 2, 97 MLX5_MAD_IFC_NET_VIEW = 4, 98 }; 99 100 enum { 101 MLX5_CROSS_CHANNEL_UUAR = 0, 102 }; 103 104 enum { 105 MLX5_CQE_VERSION_V0, 106 MLX5_CQE_VERSION_V1, 107 }; 108 109 struct mlx5_ib_vma_private_data { 110 struct list_head list; 111 struct vm_area_struct *vma; 112 }; 113 114 struct mlx5_ib_ucontext { 115 struct ib_ucontext ibucontext; 116 struct list_head db_page_list; 117 118 /* protect doorbell record alloc/free 119 */ 120 struct mutex db_page_mutex; 121 struct mlx5_uuar_info uuari; 122 u8 cqe_version; 123 /* Transport Domain number */ 124 u32 tdn; 125 struct list_head vma_private_list; 126 }; 127 128 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 129 { 130 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 131 } 132 133 struct mlx5_ib_pd { 134 struct ib_pd ibpd; 135 u32 pdn; 136 }; 137 138 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 139 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 140 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 141 #error "Invalid number of bypass priorities" 142 #endif 143 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 144 145 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 146 #define MLX5_IB_NUM_SNIFFER_FTS 2 147 struct mlx5_ib_flow_prio { 148 struct mlx5_flow_table *flow_table; 149 unsigned int refcount; 150 }; 151 152 struct mlx5_ib_flow_handler { 153 struct list_head list; 154 struct ib_flow ibflow; 155 struct mlx5_ib_flow_prio *prio; 156 struct mlx5_flow_rule *rule; 157 }; 158 159 struct mlx5_ib_flow_db { 160 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 161 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 162 struct mlx5_flow_table *lag_demux_ft; 163 /* Protect flow steering bypass flow tables 164 * when add/del flow rules. 165 * only single add/removal of flow steering rule could be done 166 * simultaneously. 167 */ 168 struct mutex lock; 169 }; 170 171 /* Use macros here so that don't have to duplicate 172 * enum ib_send_flags and enum ib_qp_type for low-level driver 173 */ 174 175 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 176 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 177 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 178 179 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3) 180 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4) 181 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END 182 183 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 184 /* 185 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 186 * creates the actual hardware QP. 187 */ 188 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 189 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 190 191 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 192 * 193 * These flags are intended for internal use by the mlx5_ib driver, and they 194 * rely on the range reserved for that use in the ib_qp_create_flags enum. 195 */ 196 197 /* Create a UD QP whose source QP number is 1 */ 198 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 199 { 200 return IB_QP_CREATE_RESERVED_START; 201 } 202 203 struct wr_list { 204 u16 opcode; 205 u16 next; 206 }; 207 208 struct mlx5_ib_wq { 209 u64 *wrid; 210 u32 *wr_data; 211 struct wr_list *w_list; 212 unsigned *wqe_head; 213 u16 unsig_count; 214 215 /* serialize post to the work queue 216 */ 217 spinlock_t lock; 218 int wqe_cnt; 219 int max_post; 220 int max_gs; 221 int offset; 222 int wqe_shift; 223 unsigned head; 224 unsigned tail; 225 u16 cur_post; 226 u16 last_poll; 227 void *qend; 228 }; 229 230 struct mlx5_ib_rwq { 231 struct ib_wq ibwq; 232 struct mlx5_core_qp core_qp; 233 u32 rq_num_pas; 234 u32 log_rq_stride; 235 u32 log_rq_size; 236 u32 rq_page_offset; 237 u32 log_page_size; 238 struct ib_umem *umem; 239 size_t buf_size; 240 unsigned int page_shift; 241 int create_type; 242 struct mlx5_db db; 243 u32 user_index; 244 u32 wqe_count; 245 u32 wqe_shift; 246 int wq_sig; 247 }; 248 249 enum { 250 MLX5_QP_USER, 251 MLX5_QP_KERNEL, 252 MLX5_QP_EMPTY 253 }; 254 255 enum { 256 MLX5_WQ_USER, 257 MLX5_WQ_KERNEL 258 }; 259 260 struct mlx5_ib_rwq_ind_table { 261 struct ib_rwq_ind_table ib_rwq_ind_tbl; 262 u32 rqtn; 263 }; 264 265 /* 266 * Connect-IB can trigger up to four concurrent pagefaults 267 * per-QP. 268 */ 269 enum mlx5_ib_pagefault_context { 270 MLX5_IB_PAGEFAULT_RESPONDER_READ, 271 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 272 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 273 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 274 MLX5_IB_PAGEFAULT_CONTEXTS 275 }; 276 277 static inline enum mlx5_ib_pagefault_context 278 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 279 { 280 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 281 } 282 283 struct mlx5_ib_pfault { 284 struct work_struct work; 285 struct mlx5_pagefault mpfault; 286 }; 287 288 struct mlx5_ib_ubuffer { 289 struct ib_umem *umem; 290 int buf_size; 291 u64 buf_addr; 292 }; 293 294 struct mlx5_ib_qp_base { 295 struct mlx5_ib_qp *container_mibqp; 296 struct mlx5_core_qp mqp; 297 struct mlx5_ib_ubuffer ubuffer; 298 }; 299 300 struct mlx5_ib_qp_trans { 301 struct mlx5_ib_qp_base base; 302 u16 xrcdn; 303 u8 alt_port; 304 u8 atomic_rd_en; 305 u8 resp_depth; 306 }; 307 308 struct mlx5_ib_rss_qp { 309 u32 tirn; 310 }; 311 312 struct mlx5_ib_rq { 313 struct mlx5_ib_qp_base base; 314 struct mlx5_ib_wq *rq; 315 struct mlx5_ib_ubuffer ubuffer; 316 struct mlx5_db *doorbell; 317 u32 tirn; 318 u8 state; 319 }; 320 321 struct mlx5_ib_sq { 322 struct mlx5_ib_qp_base base; 323 struct mlx5_ib_wq *sq; 324 struct mlx5_ib_ubuffer ubuffer; 325 struct mlx5_db *doorbell; 326 u32 tisn; 327 u8 state; 328 }; 329 330 struct mlx5_ib_raw_packet_qp { 331 struct mlx5_ib_sq sq; 332 struct mlx5_ib_rq rq; 333 }; 334 335 struct mlx5_ib_qp { 336 struct ib_qp ibqp; 337 union { 338 struct mlx5_ib_qp_trans trans_qp; 339 struct mlx5_ib_raw_packet_qp raw_packet_qp; 340 struct mlx5_ib_rss_qp rss_qp; 341 }; 342 struct mlx5_buf buf; 343 344 struct mlx5_db db; 345 struct mlx5_ib_wq rq; 346 347 u8 sq_signal_bits; 348 u8 fm_cache; 349 struct mlx5_ib_wq sq; 350 351 /* serialize qp state modifications 352 */ 353 struct mutex mutex; 354 u32 flags; 355 u8 port; 356 u8 state; 357 int wq_sig; 358 int scat_cqe; 359 int max_inline_data; 360 struct mlx5_bf *bf; 361 int has_rq; 362 363 /* only for user space QPs. For kernel 364 * we have it from the bf object 365 */ 366 int uuarn; 367 368 int create_type; 369 370 /* Store signature errors */ 371 bool signature_en; 372 373 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 374 /* 375 * A flag that is true for QP's that are in a state that doesn't 376 * allow page faults, and shouldn't schedule any more faults. 377 */ 378 int disable_page_faults; 379 /* 380 * The disable_page_faults_lock protects a QP's disable_page_faults 381 * field, allowing for a thread to atomically check whether the QP 382 * allows page faults, and if so schedule a page fault. 383 */ 384 spinlock_t disable_page_faults_lock; 385 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 386 #endif 387 struct list_head qps_list; 388 struct list_head cq_recv_list; 389 struct list_head cq_send_list; 390 }; 391 392 struct mlx5_ib_cq_buf { 393 struct mlx5_buf buf; 394 struct ib_umem *umem; 395 int cqe_size; 396 int nent; 397 }; 398 399 enum mlx5_ib_qp_flags { 400 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 401 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 402 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 403 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 404 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 405 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 406 /* QP uses 1 as its source QP number */ 407 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 408 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 409 MLX5_IB_QP_RSS = 1 << 8, 410 }; 411 412 struct mlx5_umr_wr { 413 struct ib_send_wr wr; 414 union { 415 u64 virt_addr; 416 u64 offset; 417 } target; 418 struct ib_pd *pd; 419 unsigned int page_shift; 420 unsigned int npages; 421 u32 length; 422 int access_flags; 423 u32 mkey; 424 }; 425 426 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 427 { 428 return container_of(wr, struct mlx5_umr_wr, wr); 429 } 430 431 struct mlx5_shared_mr_info { 432 int mr_id; 433 struct ib_umem *umem; 434 }; 435 436 struct mlx5_ib_cq { 437 struct ib_cq ibcq; 438 struct mlx5_core_cq mcq; 439 struct mlx5_ib_cq_buf buf; 440 struct mlx5_db db; 441 442 /* serialize access to the CQ 443 */ 444 spinlock_t lock; 445 446 /* protect resize cq 447 */ 448 struct mutex resize_mutex; 449 struct mlx5_ib_cq_buf *resize_buf; 450 struct ib_umem *resize_umem; 451 int cqe_size; 452 struct list_head list_send_qp; 453 struct list_head list_recv_qp; 454 u32 create_flags; 455 struct list_head wc_list; 456 enum ib_cq_notify_flags notify_flags; 457 struct work_struct notify_work; 458 }; 459 460 struct mlx5_ib_wc { 461 struct ib_wc wc; 462 struct list_head list; 463 }; 464 465 struct mlx5_ib_srq { 466 struct ib_srq ibsrq; 467 struct mlx5_core_srq msrq; 468 struct mlx5_buf buf; 469 struct mlx5_db db; 470 u64 *wrid; 471 /* protect SRQ hanlding 472 */ 473 spinlock_t lock; 474 int head; 475 int tail; 476 u16 wqe_ctr; 477 struct ib_umem *umem; 478 /* serialize arming a SRQ 479 */ 480 struct mutex mutex; 481 int wq_sig; 482 }; 483 484 struct mlx5_ib_xrcd { 485 struct ib_xrcd ibxrcd; 486 u32 xrcdn; 487 }; 488 489 enum mlx5_ib_mtt_access_flags { 490 MLX5_IB_MTT_READ = (1 << 0), 491 MLX5_IB_MTT_WRITE = (1 << 1), 492 }; 493 494 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 495 496 struct mlx5_ib_mr { 497 struct ib_mr ibmr; 498 void *descs; 499 dma_addr_t desc_map; 500 int ndescs; 501 int max_descs; 502 int desc_size; 503 int access_mode; 504 struct mlx5_core_mkey mmkey; 505 struct ib_umem *umem; 506 struct mlx5_shared_mr_info *smr_info; 507 struct list_head list; 508 int order; 509 int umred; 510 int npages; 511 struct mlx5_ib_dev *dev; 512 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 513 struct mlx5_core_sig_ctx *sig; 514 int live; 515 void *descs_alloc; 516 int access_flags; /* Needed for rereg MR */ 517 }; 518 519 struct mlx5_ib_mw { 520 struct ib_mw ibmw; 521 struct mlx5_core_mkey mmkey; 522 }; 523 524 struct mlx5_ib_umr_context { 525 struct ib_cqe cqe; 526 enum ib_wc_status status; 527 struct completion done; 528 }; 529 530 struct umr_common { 531 struct ib_pd *pd; 532 struct ib_cq *cq; 533 struct ib_qp *qp; 534 /* control access to UMR QP 535 */ 536 struct semaphore sem; 537 }; 538 539 enum { 540 MLX5_FMR_INVALID, 541 MLX5_FMR_VALID, 542 MLX5_FMR_BUSY, 543 }; 544 545 struct mlx5_cache_ent { 546 struct list_head head; 547 /* sync access to the cahce entry 548 */ 549 spinlock_t lock; 550 551 552 struct dentry *dir; 553 char name[4]; 554 u32 order; 555 u32 size; 556 u32 cur; 557 u32 miss; 558 u32 limit; 559 560 struct dentry *fsize; 561 struct dentry *fcur; 562 struct dentry *fmiss; 563 struct dentry *flimit; 564 565 struct mlx5_ib_dev *dev; 566 struct work_struct work; 567 struct delayed_work dwork; 568 int pending; 569 }; 570 571 struct mlx5_mr_cache { 572 struct workqueue_struct *wq; 573 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 574 int stopped; 575 struct dentry *root; 576 unsigned long last_add; 577 }; 578 579 struct mlx5_ib_gsi_qp; 580 581 struct mlx5_ib_port_resources { 582 struct mlx5_ib_resources *devr; 583 struct mlx5_ib_gsi_qp *gsi; 584 struct work_struct pkey_change_work; 585 }; 586 587 struct mlx5_ib_resources { 588 struct ib_cq *c0; 589 struct ib_xrcd *x0; 590 struct ib_xrcd *x1; 591 struct ib_pd *p0; 592 struct ib_srq *s0; 593 struct ib_srq *s1; 594 struct mlx5_ib_port_resources ports[2]; 595 /* Protects changes to the port resources */ 596 struct mutex mutex; 597 }; 598 599 struct mlx5_ib_port { 600 u16 q_cnt_id; 601 }; 602 603 struct mlx5_roce { 604 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 605 * netdev pointer 606 */ 607 rwlock_t netdev_lock; 608 struct net_device *netdev; 609 struct notifier_block nb; 610 atomic_t next_port; 611 }; 612 613 struct mlx5_ib_dev { 614 struct ib_device ib_dev; 615 struct mlx5_core_dev *mdev; 616 struct mlx5_roce roce; 617 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 618 int num_ports; 619 /* serialize update of capability mask 620 */ 621 struct mutex cap_mask_mutex; 622 bool ib_active; 623 struct umr_common umrc; 624 /* sync used page count stats 625 */ 626 struct mlx5_ib_resources devr; 627 struct mlx5_mr_cache cache; 628 struct timer_list delay_timer; 629 int fill_delay; 630 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 631 struct ib_odp_caps odp_caps; 632 /* 633 * Sleepable RCU that prevents destruction of MRs while they are still 634 * being used by a page fault handler. 635 */ 636 struct srcu_struct mr_srcu; 637 #endif 638 struct mlx5_ib_flow_db flow_db; 639 /* protect resources needed as part of reset flow */ 640 spinlock_t reset_flow_resource_lock; 641 struct list_head qp_list; 642 /* Array with num_ports elements */ 643 struct mlx5_ib_port *port; 644 }; 645 646 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 647 { 648 return container_of(mcq, struct mlx5_ib_cq, mcq); 649 } 650 651 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 652 { 653 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 654 } 655 656 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 657 { 658 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 659 } 660 661 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 662 { 663 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 664 } 665 666 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 667 { 668 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 669 } 670 671 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 672 { 673 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 674 } 675 676 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 677 { 678 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 679 } 680 681 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 682 { 683 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 684 } 685 686 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 687 { 688 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 689 } 690 691 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 692 { 693 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 694 } 695 696 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 697 { 698 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 699 } 700 701 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 702 { 703 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 704 } 705 706 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 707 { 708 return container_of(msrq, struct mlx5_ib_srq, msrq); 709 } 710 711 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 712 { 713 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 714 } 715 716 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 717 { 718 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 719 } 720 721 struct mlx5_ib_ah { 722 struct ib_ah ibah; 723 struct mlx5_av av; 724 }; 725 726 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 727 { 728 return container_of(ibah, struct mlx5_ib_ah, ibah); 729 } 730 731 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 732 struct mlx5_db *db); 733 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 734 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 735 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 736 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 737 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 738 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 739 const void *in_mad, void *response_mad); 740 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 741 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 742 int mlx5_ib_destroy_ah(struct ib_ah *ah); 743 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 744 struct ib_srq_init_attr *init_attr, 745 struct ib_udata *udata); 746 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 747 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 748 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 749 int mlx5_ib_destroy_srq(struct ib_srq *srq); 750 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 751 struct ib_recv_wr **bad_wr); 752 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 753 struct ib_qp_init_attr *init_attr, 754 struct ib_udata *udata); 755 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 756 int attr_mask, struct ib_udata *udata); 757 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 758 struct ib_qp_init_attr *qp_init_attr); 759 int mlx5_ib_destroy_qp(struct ib_qp *qp); 760 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 761 struct ib_send_wr **bad_wr); 762 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 763 struct ib_recv_wr **bad_wr); 764 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 765 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 766 void *buffer, u32 length, 767 struct mlx5_ib_qp_base *base); 768 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 769 const struct ib_cq_init_attr *attr, 770 struct ib_ucontext *context, 771 struct ib_udata *udata); 772 int mlx5_ib_destroy_cq(struct ib_cq *cq); 773 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 774 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 775 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 776 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 777 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 778 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 779 u64 virt_addr, int access_flags, 780 struct ib_udata *udata); 781 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 782 struct ib_udata *udata); 783 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 784 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 785 int npages, int zap); 786 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 787 u64 length, u64 virt_addr, int access_flags, 788 struct ib_pd *pd, struct ib_udata *udata); 789 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 790 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 791 enum ib_mr_type mr_type, 792 u32 max_num_sg); 793 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 794 unsigned int *sg_offset); 795 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 796 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 797 const struct ib_mad_hdr *in, size_t in_mad_size, 798 struct ib_mad_hdr *out, size_t *out_mad_size, 799 u16 *out_mad_pkey_index); 800 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 801 struct ib_ucontext *context, 802 struct ib_udata *udata); 803 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 804 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 805 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 806 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 807 struct ib_smp *out_mad); 808 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 809 __be64 *sys_image_guid); 810 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 811 u16 *max_pkeys); 812 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 813 u32 *vendor_id); 814 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 815 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 816 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 817 u16 *pkey); 818 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 819 union ib_gid *gid); 820 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 821 struct ib_port_attr *props); 822 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 823 struct ib_port_attr *props); 824 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 825 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 826 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 827 int *ncont, int *order); 828 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 829 int page_shift, size_t offset, size_t num_pages, 830 __be64 *pas, int access_flags); 831 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 832 int page_shift, __be64 *pas, int access_flags); 833 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 834 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 835 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 836 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 837 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 838 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 839 struct ib_mr_status *mr_status); 840 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 841 struct ib_wq_init_attr *init_attr, 842 struct ib_udata *udata); 843 int mlx5_ib_destroy_wq(struct ib_wq *wq); 844 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 845 u32 wq_attr_mask, struct ib_udata *udata); 846 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 847 struct ib_rwq_ind_table_init_attr *init_attr, 848 struct ib_udata *udata); 849 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 850 851 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 852 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 853 854 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 855 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 856 struct mlx5_ib_pfault *pfault); 857 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 858 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 859 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 860 int __init mlx5_ib_odp_init(void); 861 void mlx5_ib_odp_cleanup(void); 862 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 863 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 864 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 865 unsigned long end); 866 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 867 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 868 { 869 return; 870 } 871 872 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 873 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 874 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 875 static inline int mlx5_ib_odp_init(void) { return 0; } 876 static inline void mlx5_ib_odp_cleanup(void) {} 877 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 878 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 879 880 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 881 882 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 883 u8 port, struct ifla_vf_info *info); 884 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 885 u8 port, int state); 886 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 887 u8 port, struct ifla_vf_stats *stats); 888 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 889 u64 guid, int type); 890 891 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 892 int index); 893 894 /* GSI QP helper functions */ 895 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 896 struct ib_qp_init_attr *init_attr); 897 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 898 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 899 int attr_mask); 900 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 901 int qp_attr_mask, 902 struct ib_qp_init_attr *qp_init_attr); 903 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 904 struct ib_send_wr **bad_wr); 905 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 906 struct ib_recv_wr **bad_wr); 907 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 908 909 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 910 911 static inline void init_query_mad(struct ib_smp *mad) 912 { 913 mad->base_version = 1; 914 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 915 mad->class_version = 1; 916 mad->method = IB_MGMT_METHOD_GET; 917 } 918 919 static inline u8 convert_access(int acc) 920 { 921 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 922 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 923 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 924 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 925 MLX5_PERM_LOCAL_READ; 926 } 927 928 static inline int is_qp1(enum ib_qp_type qp_type) 929 { 930 return qp_type == MLX5_IB_QPT_HW_GSI; 931 } 932 933 #define MLX5_MAX_UMR_SHIFT 16 934 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 935 936 static inline u32 check_cq_create_flags(u32 flags) 937 { 938 /* 939 * It returns non-zero value for unsupported CQ 940 * create flags, otherwise it returns zero. 941 */ 942 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 943 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 944 } 945 946 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 947 u32 *user_index) 948 { 949 if (cqe_version) { 950 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 951 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 952 return -EINVAL; 953 *user_index = cmd_uidx; 954 } else { 955 *user_index = MLX5_IB_DEFAULT_UIDX; 956 } 957 958 return 0; 959 } 960 961 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 962 struct mlx5_ib_create_qp *ucmd, 963 int inlen, 964 u32 *user_index) 965 { 966 u8 cqe_version = ucontext->cqe_version; 967 968 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 969 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 970 return 0; 971 972 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 973 !!cqe_version)) 974 return -EINVAL; 975 976 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 977 } 978 979 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 980 struct mlx5_ib_create_srq *ucmd, 981 int inlen, 982 u32 *user_index) 983 { 984 u8 cqe_version = ucontext->cqe_version; 985 986 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 987 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 988 return 0; 989 990 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 991 !!cqe_version)) 992 return -EINVAL; 993 994 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 995 } 996 #endif /* MLX5_IB_H */ 997