1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 29 #define mlx5_ib_dbg(_dev, format, arg...) \ 30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 31 __LINE__, current->pid, ##arg) 32 33 #define mlx5_ib_err(_dev, format, arg...) \ 34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 35 __LINE__, current->pid, ##arg) 36 37 #define mlx5_ib_warn(_dev, format, arg...) \ 38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 39 __LINE__, current->pid, ##arg) 40 41 #define mlx5_ib_log(lvl, _dev, format, arg...) \ 42 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \ 43 __func__, __LINE__, current->pid, ##arg) 44 45 #define MLX5_IB_DEFAULT_UIDX 0xffffff 46 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 47 48 static __always_inline unsigned long 49 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 50 unsigned int pgsz_shift) 51 { 52 unsigned int largest_pg_shift = 53 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 54 BITS_PER_LONG - 1); 55 56 /* 57 * Despite a command allowing it, the device does not support lower than 58 * 4k page size. 59 */ 60 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 61 return GENMASK(largest_pg_shift, pgsz_shift); 62 } 63 64 /* 65 * For mkc users, instead of a page_offset the command has a start_iova which 66 * specifies both the page_offset and the on-the-wire IOVA 67 */ 68 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \ 69 ib_umem_find_best_pgsz(umem, \ 70 __mlx5_log_page_size_to_bitmap( \ 71 __mlx5_bit_sz(typ, log_pgsz_fld), \ 72 pgsz_shift), \ 73 iova) 74 75 static __always_inline unsigned long 76 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 77 unsigned int offset_shift) 78 { 79 unsigned int largest_offset_shift = 80 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 81 BITS_PER_LONG - 1); 82 83 return GENMASK(largest_offset_shift, offset_shift); 84 } 85 86 /* 87 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 88 * page_offset_quantized * (page_size/scale) = page_offset 89 * Which restricts allowed page sizes to ones that satisify the above. 90 */ 91 unsigned long __mlx5_umem_find_best_quantized_pgoff( 92 struct ib_umem *umem, unsigned long pgsz_bitmap, 93 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 94 unsigned int *page_offset_quantized); 95 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 96 pgsz_shift, page_offset_fld, \ 97 scale, page_offset_quantized) \ 98 __mlx5_umem_find_best_quantized_pgoff( \ 99 umem, \ 100 __mlx5_log_page_size_to_bitmap( \ 101 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 102 __mlx5_bit_sz(typ, page_offset_fld), \ 103 GENMASK(31, order_base_2(scale)), scale, \ 104 page_offset_quantized) 105 106 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 107 pgsz_shift, page_offset_fld, \ 108 scale, page_offset_quantized) \ 109 __mlx5_umem_find_best_quantized_pgoff( \ 110 umem, \ 111 __mlx5_log_page_size_to_bitmap( \ 112 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 113 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 114 page_offset_quantized) 115 116 enum { 117 MLX5_IB_MMAP_OFFSET_START = 9, 118 MLX5_IB_MMAP_OFFSET_END = 255, 119 }; 120 121 enum { 122 MLX5_IB_MMAP_CMD_SHIFT = 8, 123 MLX5_IB_MMAP_CMD_MASK = 0xff, 124 }; 125 126 enum { 127 MLX5_RES_SCAT_DATA32_CQE = 0x1, 128 MLX5_RES_SCAT_DATA64_CQE = 0x2, 129 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 130 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 131 }; 132 133 enum mlx5_ib_mad_ifc_flags { 134 MLX5_MAD_IFC_IGNORE_MKEY = 1, 135 MLX5_MAD_IFC_IGNORE_BKEY = 2, 136 MLX5_MAD_IFC_NET_VIEW = 4, 137 }; 138 139 enum { 140 MLX5_CROSS_CHANNEL_BFREG = 0, 141 }; 142 143 enum { 144 MLX5_CQE_VERSION_V0, 145 MLX5_CQE_VERSION_V1, 146 }; 147 148 enum { 149 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 150 MLX5_TM_MAX_SGE = 1, 151 }; 152 153 enum { 154 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 155 MLX5_IB_INVALID_BFREG = BIT(31), 156 }; 157 158 enum { 159 MLX5_MAX_MEMIC_PAGES = 0x100, 160 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 161 }; 162 163 enum { 164 MLX5_MEMIC_BASE_ALIGN = 6, 165 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 166 }; 167 168 enum mlx5_ib_mmap_type { 169 MLX5_IB_MMAP_TYPE_MEMIC = 1, 170 MLX5_IB_MMAP_TYPE_VAR = 2, 171 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 172 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 173 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 174 }; 175 176 struct mlx5_bfreg_info { 177 u32 *sys_pages; 178 int num_low_latency_bfregs; 179 unsigned int *count; 180 181 /* 182 * protect bfreg allocation data structs 183 */ 184 struct mutex lock; 185 u32 ver; 186 u8 lib_uar_4k : 1; 187 u8 lib_uar_dyn : 1; 188 u32 num_sys_pages; 189 u32 num_static_sys_pages; 190 u32 total_num_bfregs; 191 u32 num_dyn_bfregs; 192 }; 193 194 struct mlx5_ib_ucontext { 195 struct ib_ucontext ibucontext; 196 struct list_head db_page_list; 197 198 /* protect doorbell record alloc/free 199 */ 200 struct mutex db_page_mutex; 201 struct mlx5_bfreg_info bfregi; 202 u8 cqe_version; 203 /* Transport Domain number */ 204 u32 tdn; 205 206 u64 lib_caps; 207 u16 devx_uid; 208 /* For RoCE LAG TX affinity */ 209 atomic_t tx_port_affinity; 210 }; 211 212 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 213 { 214 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 215 } 216 217 struct mlx5_ib_pd { 218 struct ib_pd ibpd; 219 u32 pdn; 220 u16 uid; 221 }; 222 223 enum { 224 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 225 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 226 MLX5_IB_FLOW_ACTION_DECAP, 227 }; 228 229 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 230 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 231 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 232 #error "Invalid number of bypass priorities" 233 #endif 234 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 235 236 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 237 #define MLX5_IB_NUM_SNIFFER_FTS 2 238 #define MLX5_IB_NUM_EGRESS_FTS 1 239 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 240 struct mlx5_ib_flow_prio { 241 struct mlx5_flow_table *flow_table; 242 unsigned int refcount; 243 }; 244 245 struct mlx5_ib_flow_handler { 246 struct list_head list; 247 struct ib_flow ibflow; 248 struct mlx5_ib_flow_prio *prio; 249 struct mlx5_flow_handle *rule; 250 struct ib_counters *ibcounters; 251 struct mlx5_ib_dev *dev; 252 struct mlx5_ib_flow_matcher *flow_matcher; 253 }; 254 255 struct mlx5_ib_flow_matcher { 256 struct mlx5_ib_match_params matcher_mask; 257 int mask_len; 258 enum mlx5_ib_flow_type flow_type; 259 enum mlx5_flow_namespace_type ns_type; 260 u16 priority; 261 struct mlx5_core_dev *mdev; 262 atomic_t usecnt; 263 u8 match_criteria_enable; 264 }; 265 266 struct mlx5_ib_steering_anchor { 267 struct mlx5_ib_flow_prio *ft_prio; 268 struct mlx5_ib_dev *dev; 269 atomic_t usecnt; 270 }; 271 272 struct mlx5_ib_pp { 273 u16 index; 274 struct mlx5_core_dev *mdev; 275 }; 276 277 enum mlx5_ib_optional_counter_type { 278 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 279 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 280 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 281 282 MLX5_IB_OPCOUNTER_MAX, 283 }; 284 285 struct mlx5_ib_flow_db { 286 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 287 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 288 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 289 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 290 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 291 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 292 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 293 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 294 struct mlx5_flow_table *lag_demux_ft; 295 /* Protect flow steering bypass flow tables 296 * when add/del flow rules. 297 * only single add/removal of flow steering rule could be done 298 * simultaneously. 299 */ 300 struct mutex lock; 301 }; 302 303 /* Use macros here so that don't have to duplicate 304 * enum ib_qp_type for low-level driver 305 */ 306 307 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 308 /* 309 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 310 * creates the actual hardware QP. 311 */ 312 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 313 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 314 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 315 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 316 317 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 318 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 319 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 320 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 321 #define MLX5_IB_UPD_XLT_PD BIT(4) 322 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 323 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 324 325 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 326 * 327 * These flags are intended for internal use by the mlx5_ib driver, and they 328 * rely on the range reserved for that use in the ib_qp_create_flags enum. 329 */ 330 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 331 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 332 333 struct wr_list { 334 u16 opcode; 335 u16 next; 336 }; 337 338 enum mlx5_ib_rq_flags { 339 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 340 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 341 }; 342 343 struct mlx5_ib_wq { 344 struct mlx5_frag_buf_ctrl fbc; 345 u64 *wrid; 346 u32 *wr_data; 347 struct wr_list *w_list; 348 unsigned *wqe_head; 349 u16 unsig_count; 350 351 /* serialize post to the work queue 352 */ 353 spinlock_t lock; 354 int wqe_cnt; 355 int max_post; 356 int max_gs; 357 int offset; 358 int wqe_shift; 359 unsigned head; 360 unsigned tail; 361 u16 cur_post; 362 u16 last_poll; 363 void *cur_edge; 364 }; 365 366 enum mlx5_ib_wq_flags { 367 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 368 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 369 }; 370 371 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 372 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 373 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 374 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 375 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 376 377 struct mlx5_ib_rwq { 378 struct ib_wq ibwq; 379 struct mlx5_core_qp core_qp; 380 u32 rq_num_pas; 381 u32 log_rq_stride; 382 u32 log_rq_size; 383 u32 rq_page_offset; 384 u32 log_page_size; 385 u32 log_num_strides; 386 u32 two_byte_shift_en; 387 u32 single_stride_log_num_of_bytes; 388 struct ib_umem *umem; 389 size_t buf_size; 390 unsigned int page_shift; 391 struct mlx5_db db; 392 u32 user_index; 393 u32 wqe_count; 394 u32 wqe_shift; 395 int wq_sig; 396 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 397 }; 398 399 struct mlx5_ib_rwq_ind_table { 400 struct ib_rwq_ind_table ib_rwq_ind_tbl; 401 u32 rqtn; 402 u16 uid; 403 }; 404 405 struct mlx5_ib_ubuffer { 406 struct ib_umem *umem; 407 int buf_size; 408 u64 buf_addr; 409 }; 410 411 struct mlx5_ib_qp_base { 412 struct mlx5_ib_qp *container_mibqp; 413 struct mlx5_core_qp mqp; 414 struct mlx5_ib_ubuffer ubuffer; 415 }; 416 417 struct mlx5_ib_qp_trans { 418 struct mlx5_ib_qp_base base; 419 u16 xrcdn; 420 u32 alt_port; 421 u8 atomic_rd_en; 422 u8 resp_depth; 423 }; 424 425 struct mlx5_ib_rss_qp { 426 u32 tirn; 427 }; 428 429 struct mlx5_ib_rq { 430 struct mlx5_ib_qp_base base; 431 struct mlx5_ib_wq *rq; 432 struct mlx5_ib_ubuffer ubuffer; 433 struct mlx5_db *doorbell; 434 u32 tirn; 435 u8 state; 436 u32 flags; 437 }; 438 439 struct mlx5_ib_sq { 440 struct mlx5_ib_qp_base base; 441 struct mlx5_ib_wq *sq; 442 struct mlx5_ib_ubuffer ubuffer; 443 struct mlx5_db *doorbell; 444 struct mlx5_flow_handle *flow_rule; 445 u32 tisn; 446 u8 state; 447 }; 448 449 struct mlx5_ib_raw_packet_qp { 450 struct mlx5_ib_sq sq; 451 struct mlx5_ib_rq rq; 452 }; 453 454 struct mlx5_bf { 455 int buf_size; 456 unsigned long offset; 457 struct mlx5_sq_bfreg *bfreg; 458 }; 459 460 struct mlx5_ib_dct { 461 struct mlx5_core_dct mdct; 462 u32 *in; 463 }; 464 465 struct mlx5_ib_gsi_qp { 466 struct ib_qp *rx_qp; 467 u32 port_num; 468 struct ib_qp_cap cap; 469 struct ib_cq *cq; 470 struct mlx5_ib_gsi_wr *outstanding_wrs; 471 u32 outstanding_pi, outstanding_ci; 472 int num_qps; 473 /* Protects access to the tx_qps. Post send operations synchronize 474 * with tx_qp creation in setup_qp(). Also protects the 475 * outstanding_wrs array and indices. 476 */ 477 spinlock_t lock; 478 struct ib_qp **tx_qps; 479 }; 480 481 struct mlx5_ib_qp { 482 struct ib_qp ibqp; 483 union { 484 struct mlx5_ib_qp_trans trans_qp; 485 struct mlx5_ib_raw_packet_qp raw_packet_qp; 486 struct mlx5_ib_rss_qp rss_qp; 487 struct mlx5_ib_dct dct; 488 struct mlx5_ib_gsi_qp gsi; 489 }; 490 struct mlx5_frag_buf buf; 491 492 struct mlx5_db db; 493 struct mlx5_ib_wq rq; 494 495 u8 sq_signal_bits; 496 u8 next_fence; 497 struct mlx5_ib_wq sq; 498 499 /* serialize qp state modifications 500 */ 501 struct mutex mutex; 502 /* cached variant of create_flags from struct ib_qp_init_attr */ 503 u32 flags; 504 u32 port; 505 u8 state; 506 int max_inline_data; 507 struct mlx5_bf bf; 508 u8 has_rq:1; 509 u8 is_rss:1; 510 511 /* only for user space QPs. For kernel 512 * we have it from the bf object 513 */ 514 int bfregn; 515 516 struct list_head qps_list; 517 struct list_head cq_recv_list; 518 struct list_head cq_send_list; 519 struct mlx5_rate_limit rl; 520 u32 underlay_qpn; 521 u32 flags_en; 522 /* 523 * IB/core doesn't store low-level QP types, so 524 * store both MLX and IBTA types in the field below. 525 */ 526 enum ib_qp_type type; 527 /* A flag to indicate if there's a new counter is configured 528 * but not take effective 529 */ 530 u32 counter_pending; 531 u16 gsi_lag_port; 532 }; 533 534 struct mlx5_ib_cq_buf { 535 struct mlx5_frag_buf_ctrl fbc; 536 struct mlx5_frag_buf frag_buf; 537 struct ib_umem *umem; 538 int cqe_size; 539 int nent; 540 }; 541 542 enum mlx5_ib_cq_pr_flags { 543 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 544 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 545 }; 546 547 struct mlx5_ib_cq { 548 struct ib_cq ibcq; 549 struct mlx5_core_cq mcq; 550 struct mlx5_ib_cq_buf buf; 551 struct mlx5_db db; 552 553 /* serialize access to the CQ 554 */ 555 spinlock_t lock; 556 557 /* protect resize cq 558 */ 559 struct mutex resize_mutex; 560 struct mlx5_ib_cq_buf *resize_buf; 561 struct ib_umem *resize_umem; 562 int cqe_size; 563 struct list_head list_send_qp; 564 struct list_head list_recv_qp; 565 u32 create_flags; 566 struct list_head wc_list; 567 enum ib_cq_notify_flags notify_flags; 568 struct work_struct notify_work; 569 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 570 }; 571 572 struct mlx5_ib_wc { 573 struct ib_wc wc; 574 struct list_head list; 575 }; 576 577 struct mlx5_ib_srq { 578 struct ib_srq ibsrq; 579 struct mlx5_core_srq msrq; 580 struct mlx5_frag_buf buf; 581 struct mlx5_db db; 582 struct mlx5_frag_buf_ctrl fbc; 583 u64 *wrid; 584 /* protect SRQ hanlding 585 */ 586 spinlock_t lock; 587 int head; 588 int tail; 589 u16 wqe_ctr; 590 struct ib_umem *umem; 591 /* serialize arming a SRQ 592 */ 593 struct mutex mutex; 594 int wq_sig; 595 }; 596 597 struct mlx5_ib_xrcd { 598 struct ib_xrcd ibxrcd; 599 u32 xrcdn; 600 }; 601 602 enum mlx5_ib_mtt_access_flags { 603 MLX5_IB_MTT_READ = (1 << 0), 604 MLX5_IB_MTT_WRITE = (1 << 1), 605 }; 606 607 struct mlx5_user_mmap_entry { 608 struct rdma_user_mmap_entry rdma_entry; 609 u8 mmap_flag; 610 u64 address; 611 u32 page_idx; 612 }; 613 614 enum mlx5_mkey_type { 615 MLX5_MKEY_MR = 1, 616 MLX5_MKEY_MW, 617 MLX5_MKEY_INDIRECT_DEVX, 618 }; 619 620 struct mlx5_ib_mkey { 621 u32 key; 622 enum mlx5_mkey_type type; 623 unsigned int ndescs; 624 struct wait_queue_head wait; 625 refcount_t usecount; 626 struct mlx5_cache_ent *cache_ent; 627 }; 628 629 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 630 631 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 632 IB_ACCESS_REMOTE_WRITE |\ 633 IB_ACCESS_REMOTE_READ |\ 634 IB_ACCESS_REMOTE_ATOMIC |\ 635 IB_ZERO_BASED) 636 637 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 638 IB_ACCESS_REMOTE_WRITE |\ 639 IB_ACCESS_REMOTE_READ |\ 640 IB_ZERO_BASED) 641 642 #define mlx5_update_odp_stats(mr, counter_name, value) \ 643 atomic64_add(value, &((mr)->odp_stats.counter_name)) 644 645 struct mlx5_ib_mr { 646 struct ib_mr ibmr; 647 struct mlx5_ib_mkey mmkey; 648 649 struct ib_umem *umem; 650 651 union { 652 /* Used only by kernel MRs (umem == NULL) */ 653 struct { 654 void *descs; 655 void *descs_alloc; 656 dma_addr_t desc_map; 657 int max_descs; 658 int desc_size; 659 int access_mode; 660 661 /* For Kernel IB_MR_TYPE_INTEGRITY */ 662 struct mlx5_core_sig_ctx *sig; 663 struct mlx5_ib_mr *pi_mr; 664 struct mlx5_ib_mr *klm_mr; 665 struct mlx5_ib_mr *mtt_mr; 666 u64 data_iova; 667 u64 pi_iova; 668 int meta_ndescs; 669 int meta_length; 670 int data_length; 671 }; 672 673 /* Used only by User MRs (umem != NULL) */ 674 struct { 675 unsigned int page_shift; 676 /* Current access_flags */ 677 int access_flags; 678 679 /* For User ODP */ 680 struct mlx5_ib_mr *parent; 681 struct xarray implicit_children; 682 union { 683 struct work_struct work; 684 } odp_destroy; 685 struct ib_odp_counters odp_stats; 686 bool is_odp_implicit; 687 }; 688 }; 689 }; 690 691 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 692 { 693 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 694 mr->umem->is_odp; 695 } 696 697 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 698 { 699 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 700 mr->umem->is_dmabuf; 701 } 702 703 struct mlx5_ib_mw { 704 struct ib_mw ibmw; 705 struct mlx5_ib_mkey mmkey; 706 }; 707 708 struct mlx5_ib_umr_context { 709 struct ib_cqe cqe; 710 enum ib_wc_status status; 711 struct completion done; 712 }; 713 714 enum { 715 MLX5_UMR_STATE_UNINIT, 716 MLX5_UMR_STATE_ACTIVE, 717 MLX5_UMR_STATE_RECOVER, 718 MLX5_UMR_STATE_ERR, 719 }; 720 721 struct umr_common { 722 struct ib_pd *pd; 723 struct ib_cq *cq; 724 struct ib_qp *qp; 725 /* Protects from UMR QP overflow 726 */ 727 struct semaphore sem; 728 /* Protects from using UMR while the UMR is not active 729 */ 730 struct mutex lock; 731 unsigned int state; 732 }; 733 734 struct mlx5_cache_ent { 735 struct xarray mkeys; 736 unsigned long stored; 737 unsigned long reserved; 738 739 char name[4]; 740 u32 order; 741 u32 access_mode; 742 u32 page; 743 unsigned int ndescs; 744 745 u8 disabled:1; 746 u8 fill_to_high_water:1; 747 748 /* 749 * - limit is the low water mark for stored mkeys, 2* limit is the 750 * upper water mark. 751 */ 752 u32 in_use; 753 u32 limit; 754 755 /* Statistics */ 756 u32 miss; 757 758 struct mlx5_ib_dev *dev; 759 struct delayed_work dwork; 760 }; 761 762 struct mlx5r_async_create_mkey { 763 union { 764 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)]; 765 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 766 }; 767 struct mlx5_async_work cb_work; 768 struct mlx5_cache_ent *ent; 769 u32 mkey; 770 }; 771 772 struct mlx5_mkey_cache { 773 struct workqueue_struct *wq; 774 struct mlx5_cache_ent ent[MAX_MKEY_CACHE_ENTRIES]; 775 struct dentry *root; 776 unsigned long last_add; 777 }; 778 779 struct mlx5_ib_port_resources { 780 struct mlx5_ib_gsi_qp *gsi; 781 struct work_struct pkey_change_work; 782 }; 783 784 struct mlx5_ib_resources { 785 struct ib_cq *c0; 786 u32 xrcdn0; 787 u32 xrcdn1; 788 struct ib_pd *p0; 789 struct ib_srq *s0; 790 struct ib_srq *s1; 791 struct mlx5_ib_port_resources ports[2]; 792 }; 793 794 #define MAX_OPFC_RULES 2 795 796 struct mlx5_ib_op_fc { 797 struct mlx5_fc *fc; 798 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 799 }; 800 801 struct mlx5_ib_counters { 802 struct rdma_stat_desc *descs; 803 size_t *offsets; 804 u32 num_q_counters; 805 u32 num_cong_counters; 806 u32 num_ext_ppcnt_counters; 807 u32 num_op_counters; 808 u16 set_id; 809 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 810 }; 811 812 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 813 struct mlx5_ib_op_fc *opfc, 814 enum mlx5_ib_optional_counter_type type); 815 816 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 817 struct mlx5_ib_op_fc *opfc, 818 enum mlx5_ib_optional_counter_type type); 819 820 struct mlx5_ib_multiport_info; 821 822 struct mlx5_ib_multiport { 823 struct mlx5_ib_multiport_info *mpi; 824 /* To be held when accessing the multiport info */ 825 spinlock_t mpi_lock; 826 }; 827 828 struct mlx5_roce { 829 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 830 * netdev pointer 831 */ 832 rwlock_t netdev_lock; 833 struct net_device *netdev; 834 struct notifier_block nb; 835 atomic_t tx_port_affinity; 836 enum ib_port_state last_port_state; 837 struct mlx5_ib_dev *dev; 838 u32 native_port_num; 839 }; 840 841 struct mlx5_ib_port { 842 struct mlx5_ib_counters cnts; 843 struct mlx5_ib_multiport mp; 844 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 845 struct mlx5_roce roce; 846 struct mlx5_eswitch_rep *rep; 847 }; 848 849 struct mlx5_ib_dbg_param { 850 int offset; 851 struct mlx5_ib_dev *dev; 852 struct dentry *dentry; 853 u32 port_num; 854 }; 855 856 enum mlx5_ib_dbg_cc_types { 857 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 858 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 859 MLX5_IB_DBG_CC_RP_TIME_RESET, 860 MLX5_IB_DBG_CC_RP_BYTE_RESET, 861 MLX5_IB_DBG_CC_RP_THRESHOLD, 862 MLX5_IB_DBG_CC_RP_AI_RATE, 863 MLX5_IB_DBG_CC_RP_MAX_RATE, 864 MLX5_IB_DBG_CC_RP_HAI_RATE, 865 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 866 MLX5_IB_DBG_CC_RP_MIN_RATE, 867 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 868 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 869 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 870 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 871 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 872 MLX5_IB_DBG_CC_RP_GD, 873 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 874 MLX5_IB_DBG_CC_NP_CNP_DSCP, 875 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 876 MLX5_IB_DBG_CC_NP_CNP_PRIO, 877 MLX5_IB_DBG_CC_MAX, 878 }; 879 880 struct mlx5_ib_dbg_cc_params { 881 struct dentry *root; 882 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 883 }; 884 885 enum { 886 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 887 }; 888 889 struct mlx5_ib_delay_drop { 890 struct mlx5_ib_dev *dev; 891 struct work_struct delay_drop_work; 892 /* serialize setting of delay drop */ 893 struct mutex lock; 894 u32 timeout; 895 bool activate; 896 atomic_t events_cnt; 897 atomic_t rqs_cnt; 898 struct dentry *dir_debugfs; 899 }; 900 901 enum mlx5_ib_stages { 902 MLX5_IB_STAGE_INIT, 903 MLX5_IB_STAGE_FS, 904 MLX5_IB_STAGE_CAPS, 905 MLX5_IB_STAGE_NON_DEFAULT_CB, 906 MLX5_IB_STAGE_ROCE, 907 MLX5_IB_STAGE_QP, 908 MLX5_IB_STAGE_SRQ, 909 MLX5_IB_STAGE_DEVICE_RESOURCES, 910 MLX5_IB_STAGE_DEVICE_NOTIFIER, 911 MLX5_IB_STAGE_ODP, 912 MLX5_IB_STAGE_COUNTERS, 913 MLX5_IB_STAGE_CONG_DEBUGFS, 914 MLX5_IB_STAGE_UAR, 915 MLX5_IB_STAGE_BFREG, 916 MLX5_IB_STAGE_PRE_IB_REG_UMR, 917 MLX5_IB_STAGE_WHITELIST_UID, 918 MLX5_IB_STAGE_IB_REG, 919 MLX5_IB_STAGE_POST_IB_REG_UMR, 920 MLX5_IB_STAGE_DELAY_DROP, 921 MLX5_IB_STAGE_RESTRACK, 922 MLX5_IB_STAGE_MAX, 923 }; 924 925 struct mlx5_ib_stage { 926 int (*init)(struct mlx5_ib_dev *dev); 927 void (*cleanup)(struct mlx5_ib_dev *dev); 928 }; 929 930 #define STAGE_CREATE(_stage, _init, _cleanup) \ 931 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 932 933 struct mlx5_ib_profile { 934 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 935 }; 936 937 struct mlx5_ib_multiport_info { 938 struct list_head list; 939 struct mlx5_ib_dev *ibdev; 940 struct mlx5_core_dev *mdev; 941 struct notifier_block mdev_events; 942 struct completion unref_comp; 943 u64 sys_image_guid; 944 u32 mdev_refcnt; 945 bool is_master; 946 bool unaffiliate; 947 }; 948 949 struct mlx5_ib_flow_action { 950 struct ib_flow_action ib_action; 951 union { 952 struct { 953 u64 ib_flags; 954 struct mlx5_accel_esp_xfrm *ctx; 955 } esp_aes_gcm; 956 struct { 957 struct mlx5_ib_dev *dev; 958 u32 sub_type; 959 union { 960 struct mlx5_modify_hdr *modify_hdr; 961 struct mlx5_pkt_reformat *pkt_reformat; 962 }; 963 } flow_action_raw; 964 }; 965 }; 966 967 struct mlx5_dm { 968 struct mlx5_core_dev *dev; 969 /* This lock is used to protect the access to the shared 970 * allocation map when concurrent requests by different 971 * processes are handled. 972 */ 973 spinlock_t lock; 974 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 975 }; 976 977 struct mlx5_read_counters_attr { 978 struct mlx5_fc *hw_cntrs_hndl; 979 u64 *out; 980 u32 flags; 981 }; 982 983 enum mlx5_ib_counters_type { 984 MLX5_IB_COUNTERS_FLOW, 985 }; 986 987 struct mlx5_ib_mcounters { 988 struct ib_counters ibcntrs; 989 enum mlx5_ib_counters_type type; 990 /* number of counters supported for this counters type */ 991 u32 counters_num; 992 struct mlx5_fc *hw_cntrs_hndl; 993 /* read function for this counters type */ 994 int (*read_counters)(struct ib_device *ibdev, 995 struct mlx5_read_counters_attr *read_attr); 996 /* max index set as part of create_flow */ 997 u32 cntrs_max_index; 998 /* number of counters data entries (<description,index> pair) */ 999 u32 ncounters; 1000 /* counters data array for descriptions and indexes */ 1001 struct mlx5_ib_flow_counters_desc *counters_data; 1002 /* protects access to mcounters internal data */ 1003 struct mutex mcntrs_mutex; 1004 }; 1005 1006 static inline struct mlx5_ib_mcounters * 1007 to_mcounters(struct ib_counters *ibcntrs) 1008 { 1009 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1010 } 1011 1012 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1013 bool is_egress, 1014 struct mlx5_flow_act *action); 1015 struct mlx5_ib_lb_state { 1016 /* protect the user_td */ 1017 struct mutex mutex; 1018 u32 user_td; 1019 int qps; 1020 bool enabled; 1021 }; 1022 1023 struct mlx5_ib_pf_eq { 1024 struct notifier_block irq_nb; 1025 struct mlx5_ib_dev *dev; 1026 struct mlx5_eq *core; 1027 struct work_struct work; 1028 spinlock_t lock; /* Pagefaults spinlock */ 1029 struct workqueue_struct *wq; 1030 mempool_t *pool; 1031 }; 1032 1033 struct mlx5_devx_event_table { 1034 struct mlx5_nb devx_nb; 1035 /* serialize updating the event_xa */ 1036 struct mutex event_xa_lock; 1037 struct xarray event_xa; 1038 }; 1039 1040 struct mlx5_var_table { 1041 /* serialize updating the bitmap */ 1042 struct mutex bitmap_lock; 1043 unsigned long *bitmap; 1044 u64 hw_start_addr; 1045 u32 stride_size; 1046 u64 num_var_hw_entries; 1047 }; 1048 1049 struct mlx5_port_caps { 1050 bool has_smi; 1051 u8 ext_port_cap; 1052 }; 1053 1054 struct mlx5_ib_dev { 1055 struct ib_device ib_dev; 1056 struct mlx5_core_dev *mdev; 1057 struct notifier_block mdev_events; 1058 int num_ports; 1059 /* serialize update of capability mask 1060 */ 1061 struct mutex cap_mask_mutex; 1062 u8 ib_active:1; 1063 u8 is_rep:1; 1064 u8 lag_active:1; 1065 u8 wc_support:1; 1066 u8 fill_delay; 1067 struct umr_common umrc; 1068 /* sync used page count stats 1069 */ 1070 struct mlx5_ib_resources devr; 1071 1072 atomic_t mkey_var; 1073 struct mlx5_mkey_cache cache; 1074 struct timer_list delay_timer; 1075 /* Prevents soft lock on massive reg MRs */ 1076 struct mutex slow_path_mutex; 1077 struct ib_odp_caps odp_caps; 1078 u64 odp_max_size; 1079 struct mutex odp_eq_mutex; 1080 struct mlx5_ib_pf_eq odp_pf_eq; 1081 1082 struct xarray odp_mkeys; 1083 1084 u32 null_mkey; 1085 struct mlx5_ib_flow_db *flow_db; 1086 /* protect resources needed as part of reset flow */ 1087 spinlock_t reset_flow_resource_lock; 1088 struct list_head qp_list; 1089 /* Array with num_ports elements */ 1090 struct mlx5_ib_port *port; 1091 struct mlx5_sq_bfreg bfreg; 1092 struct mlx5_sq_bfreg wc_bfreg; 1093 struct mlx5_sq_bfreg fp_bfreg; 1094 struct mlx5_ib_delay_drop delay_drop; 1095 const struct mlx5_ib_profile *profile; 1096 1097 struct mlx5_ib_lb_state lb; 1098 u8 umr_fence; 1099 struct list_head ib_dev_list; 1100 u64 sys_image_guid; 1101 struct mlx5_dm dm; 1102 u16 devx_whitelist_uid; 1103 struct mlx5_srq_table srq_table; 1104 struct mlx5_qp_table qp_table; 1105 struct mlx5_async_ctx async_ctx; 1106 struct mlx5_devx_event_table devx_event_table; 1107 struct mlx5_var_table var_table; 1108 1109 struct xarray sig_mrs; 1110 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1111 u16 pkey_table_len; 1112 u8 lag_ports; 1113 }; 1114 1115 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1116 { 1117 return container_of(mcq, struct mlx5_ib_cq, mcq); 1118 } 1119 1120 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1121 { 1122 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1123 } 1124 1125 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1126 { 1127 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1128 } 1129 1130 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1131 { 1132 return to_mdev(mr->ibmr.device); 1133 } 1134 1135 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1136 { 1137 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1138 udata, struct mlx5_ib_ucontext, ibucontext); 1139 1140 return to_mdev(context->ibucontext.device); 1141 } 1142 1143 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1144 { 1145 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1146 } 1147 1148 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1149 { 1150 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1151 } 1152 1153 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1154 { 1155 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1156 } 1157 1158 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1159 { 1160 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1161 } 1162 1163 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1164 { 1165 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1166 } 1167 1168 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1169 { 1170 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1171 } 1172 1173 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1174 { 1175 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1176 } 1177 1178 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1179 { 1180 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1181 } 1182 1183 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1184 { 1185 return container_of(msrq, struct mlx5_ib_srq, msrq); 1186 } 1187 1188 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1189 { 1190 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1191 } 1192 1193 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1194 { 1195 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1196 } 1197 1198 static inline struct mlx5_ib_flow_action * 1199 to_mflow_act(struct ib_flow_action *ibact) 1200 { 1201 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1202 } 1203 1204 static inline struct mlx5_user_mmap_entry * 1205 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1206 { 1207 return container_of(rdma_entry, 1208 struct mlx5_user_mmap_entry, rdma_entry); 1209 } 1210 1211 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1212 struct mlx5_db *db); 1213 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1214 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1215 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1216 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1217 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1218 struct ib_udata *udata); 1219 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1220 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1221 { 1222 return 0; 1223 } 1224 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1225 struct ib_udata *udata); 1226 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1227 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1228 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1229 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1230 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1231 const struct ib_recv_wr **bad_wr); 1232 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1233 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1234 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1235 struct ib_udata *udata); 1236 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1237 int attr_mask, struct ib_udata *udata); 1238 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1239 struct ib_qp_init_attr *qp_init_attr); 1240 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1241 void mlx5_ib_drain_sq(struct ib_qp *qp); 1242 void mlx5_ib_drain_rq(struct ib_qp *qp); 1243 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1244 size_t buflen, size_t *bc); 1245 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1246 size_t buflen, size_t *bc); 1247 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1248 size_t buflen, size_t *bc); 1249 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1250 struct ib_udata *udata); 1251 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1252 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1253 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1254 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1255 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1256 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1257 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1258 u64 virt_addr, int access_flags, 1259 struct ib_udata *udata); 1260 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1261 u64 length, u64 virt_addr, 1262 int fd, int access_flags, 1263 struct ib_udata *udata); 1264 int mlx5_ib_advise_mr(struct ib_pd *pd, 1265 enum ib_uverbs_advise_mr_advice advice, 1266 u32 flags, 1267 struct ib_sge *sg_list, 1268 u32 num_sge, 1269 struct uverbs_attr_bundle *attrs); 1270 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1271 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1272 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1273 int access_flags); 1274 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1275 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1276 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1277 u64 length, u64 virt_addr, int access_flags, 1278 struct ib_pd *pd, struct ib_udata *udata); 1279 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1280 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1281 u32 max_num_sg); 1282 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1283 u32 max_num_sg, 1284 u32 max_num_meta_sg); 1285 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1286 unsigned int *sg_offset); 1287 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1288 int data_sg_nents, unsigned int *data_sg_offset, 1289 struct scatterlist *meta_sg, int meta_sg_nents, 1290 unsigned int *meta_sg_offset); 1291 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1292 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1293 const struct ib_mad *in, struct ib_mad *out, 1294 size_t *out_mad_size, u16 *out_mad_pkey_index); 1295 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1296 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1297 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1298 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1299 __be64 *sys_image_guid); 1300 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1301 u16 *max_pkeys); 1302 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1303 u32 *vendor_id); 1304 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1305 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1306 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1307 u16 *pkey); 1308 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1309 union ib_gid *gid); 1310 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1311 struct ib_port_attr *props); 1312 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1313 struct ib_port_attr *props); 1314 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1315 u64 access_flags); 1316 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1317 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1318 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev); 1319 int mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev); 1320 1321 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1322 struct mlx5_cache_ent *ent, 1323 int access_flags); 1324 1325 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1326 struct ib_mr_status *mr_status); 1327 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1328 struct ib_wq_init_attr *init_attr, 1329 struct ib_udata *udata); 1330 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1331 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1332 u32 wq_attr_mask, struct ib_udata *udata); 1333 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1334 struct ib_rwq_ind_table_init_attr *init_attr, 1335 struct ib_udata *udata); 1336 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1337 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1338 struct ib_dm_mr_attr *attr, 1339 struct uverbs_attr_bundle *attrs); 1340 1341 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1342 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1343 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1344 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1345 int __init mlx5_ib_odp_init(void); 1346 void mlx5_ib_odp_cleanup(void); 1347 void mlx5_odp_init_mkey_cache_entry(struct mlx5_cache_ent *ent); 1348 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1349 struct mlx5_ib_mr *mr, int flags); 1350 1351 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1352 enum ib_uverbs_advise_mr_advice advice, 1353 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1354 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1355 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1356 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1357 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1358 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1359 struct mlx5_ib_pf_eq *eq) 1360 { 1361 return 0; 1362 } 1363 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1364 static inline int mlx5_ib_odp_init(void) { return 0; } 1365 static inline void mlx5_ib_odp_cleanup(void) {} 1366 static inline void mlx5_odp_init_mkey_cache_entry(struct mlx5_cache_ent *ent) {} 1367 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1368 struct mlx5_ib_mr *mr, int flags) {} 1369 1370 static inline int 1371 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1372 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1373 struct ib_sge *sg_list, u32 num_sge) 1374 { 1375 return -EOPNOTSUPP; 1376 } 1377 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1378 { 1379 return -EOPNOTSUPP; 1380 } 1381 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1382 { 1383 return -EOPNOTSUPP; 1384 } 1385 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1386 1387 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1388 1389 /* Needed for rep profile */ 1390 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1391 const struct mlx5_ib_profile *profile, 1392 int stage); 1393 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1394 const struct mlx5_ib_profile *profile); 1395 1396 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1397 u32 port, struct ifla_vf_info *info); 1398 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1399 u32 port, int state); 1400 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1401 u32 port, struct ifla_vf_stats *stats); 1402 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1403 struct ifla_vf_guid *node_guid, 1404 struct ifla_vf_guid *port_guid); 1405 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1406 u64 guid, int type); 1407 1408 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1409 const struct ib_gid_attr *attr); 1410 1411 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1412 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1413 1414 /* GSI QP helper functions */ 1415 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1416 struct ib_qp_init_attr *attr); 1417 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1418 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1419 int attr_mask); 1420 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1421 int qp_attr_mask, 1422 struct ib_qp_init_attr *qp_init_attr); 1423 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1424 const struct ib_send_wr **bad_wr); 1425 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1426 const struct ib_recv_wr **bad_wr); 1427 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1428 1429 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1430 1431 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1432 int bfregn); 1433 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1434 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1435 u32 ib_port_num, 1436 u32 *native_port_num); 1437 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1438 u32 port_num); 1439 1440 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1441 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1442 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1443 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1444 1445 static inline int is_qp1(enum ib_qp_type qp_type) 1446 { 1447 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1448 } 1449 1450 static inline u32 check_cq_create_flags(u32 flags) 1451 { 1452 /* 1453 * It returns non-zero value for unsupported CQ 1454 * create flags, otherwise it returns zero. 1455 */ 1456 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1457 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1458 } 1459 1460 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1461 u32 *user_index) 1462 { 1463 if (cqe_version) { 1464 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1465 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1466 return -EINVAL; 1467 *user_index = cmd_uidx; 1468 } else { 1469 *user_index = MLX5_IB_DEFAULT_UIDX; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1476 struct mlx5_ib_create_qp *ucmd, 1477 int inlen, 1478 u32 *user_index) 1479 { 1480 u8 cqe_version = ucontext->cqe_version; 1481 1482 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1483 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1484 return 0; 1485 1486 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1487 return -EINVAL; 1488 1489 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1490 } 1491 1492 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1493 struct mlx5_ib_create_srq *ucmd, 1494 int inlen, 1495 u32 *user_index) 1496 { 1497 u8 cqe_version = ucontext->cqe_version; 1498 1499 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1500 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1501 return 0; 1502 1503 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1504 return -EINVAL; 1505 1506 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1507 } 1508 1509 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1510 { 1511 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1512 MLX5_UARS_IN_PAGE : 1; 1513 } 1514 1515 extern void *xlt_emergency_page; 1516 1517 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1518 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1519 bool dyn_bfreg); 1520 1521 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1522 struct mlx5_ib_mkey *mmkey) 1523 { 1524 refcount_set(&mmkey->usecount, 1); 1525 1526 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1527 mmkey, GFP_KERNEL)); 1528 } 1529 1530 /* deref an mkey that can participate in ODP flow */ 1531 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1532 { 1533 if (refcount_dec_and_test(&mmkey->usecount)) 1534 wake_up(&mmkey->wait); 1535 } 1536 1537 /* deref an mkey that can participate in ODP flow and wait for relese */ 1538 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1539 { 1540 mlx5r_deref_odp_mkey(mmkey); 1541 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1542 } 1543 1544 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1545 1546 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1547 { 1548 /* 1549 * If the driver is in hash mode and the port_select_flow_table_bypass cap 1550 * is supported, it means that the driver no longer needs to assign the port 1551 * affinity by default. If a user wants to set the port affinity explicitly, 1552 * the user has a dedicated API to do that, so there is no need to assign 1553 * the port affinity by default. 1554 */ 1555 if (dev->lag_active && 1556 mlx5_lag_mode_is_hash(dev->mdev) && 1557 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass)) 1558 return 0; 1559 1560 return dev->lag_active || 1561 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1562 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1563 } 1564 1565 static inline bool rt_supported(int ts_cap) 1566 { 1567 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1568 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1569 } 1570 1571 /* 1572 * PCI Peer to Peer is a trainwreck. If no switch is present then things 1573 * sometimes work, depending on the pci_distance_p2p logic for excluding broken 1574 * root complexes. However if a switch is present in the path, then things get 1575 * really ugly depending on how the switch is setup. This table assumes that the 1576 * root complex is strict and is validating that all req/reps are matches 1577 * perfectly - so any scenario where it sees only half the transaction is a 1578 * failure. 1579 * 1580 * CR/RR/DT ATS RO P2P 1581 * 00X X X OK 1582 * 010 X X fails (request is routed to root but root never sees comp) 1583 * 011 0 X fails (request is routed to root but root never sees comp) 1584 * 011 1 X OK 1585 * 10X X 1 OK 1586 * 101 X 0 fails (completion is routed to root but root didn't see req) 1587 * 110 X 0 SLOW 1588 * 111 0 0 SLOW 1589 * 111 1 0 fails (completion is routed to root but root didn't see req) 1590 * 111 1 1 OK 1591 * 1592 * Unfortunately we cannot reliably know if a switch is present or what the 1593 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that 1594 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. 1595 * 1596 * For now assume if the umem is a dma_buf then it is P2P. 1597 */ 1598 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, 1599 struct ib_umem *umem, int access_flags) 1600 { 1601 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) 1602 return false; 1603 return access_flags & IB_ACCESS_RELAXED_ORDERING; 1604 } 1605 1606 #endif /* MLX5_IB_H */ 1607