1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 #include <rdma/uverbs_ioctl.h> 49 50 #define mlx5_ib_dbg(dev, format, arg...) \ 51 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 52 __LINE__, current->pid, ##arg) 53 54 #define mlx5_ib_err(dev, format, arg...) \ 55 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 56 __LINE__, current->pid, ##arg) 57 58 #define mlx5_ib_warn(dev, format, arg...) \ 59 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 60 __LINE__, current->pid, ##arg) 61 62 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 63 sizeof(((type *)0)->fld) <= (sz)) 64 #define MLX5_IB_DEFAULT_UIDX 0xffffff 65 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 66 67 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 68 69 enum { 70 MLX5_IB_MMAP_CMD_SHIFT = 8, 71 MLX5_IB_MMAP_CMD_MASK = 0xff, 72 }; 73 74 enum { 75 MLX5_RES_SCAT_DATA32_CQE = 0x1, 76 MLX5_RES_SCAT_DATA64_CQE = 0x2, 77 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 78 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 79 }; 80 81 enum mlx5_ib_latency_class { 82 MLX5_IB_LATENCY_CLASS_LOW, 83 MLX5_IB_LATENCY_CLASS_MEDIUM, 84 MLX5_IB_LATENCY_CLASS_HIGH, 85 }; 86 87 enum mlx5_ib_mad_ifc_flags { 88 MLX5_MAD_IFC_IGNORE_MKEY = 1, 89 MLX5_MAD_IFC_IGNORE_BKEY = 2, 90 MLX5_MAD_IFC_NET_VIEW = 4, 91 }; 92 93 enum { 94 MLX5_CROSS_CHANNEL_BFREG = 0, 95 }; 96 97 enum { 98 MLX5_CQE_VERSION_V0, 99 MLX5_CQE_VERSION_V1, 100 }; 101 102 enum { 103 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 104 MLX5_TM_MAX_SGE = 1, 105 }; 106 107 enum { 108 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 109 MLX5_IB_INVALID_BFREG = BIT(31), 110 }; 111 112 enum { 113 MLX5_MAX_MEMIC_PAGES = 0x100, 114 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 115 }; 116 117 enum { 118 MLX5_MEMIC_BASE_ALIGN = 6, 119 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 120 }; 121 122 struct mlx5_ib_vma_private_data { 123 struct list_head list; 124 struct vm_area_struct *vma; 125 /* protect vma_private_list add/del */ 126 struct mutex *vma_private_list_mutex; 127 }; 128 129 struct mlx5_ib_ucontext { 130 struct ib_ucontext ibucontext; 131 struct list_head db_page_list; 132 133 /* protect doorbell record alloc/free 134 */ 135 struct mutex db_page_mutex; 136 struct mlx5_bfreg_info bfregi; 137 u8 cqe_version; 138 /* Transport Domain number */ 139 u32 tdn; 140 struct list_head vma_private_list; 141 /* protect vma_private_list add/del */ 142 struct mutex vma_private_list_mutex; 143 144 u64 lib_caps; 145 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES); 146 }; 147 148 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 149 { 150 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 151 } 152 153 struct mlx5_ib_pd { 154 struct ib_pd ibpd; 155 u32 pdn; 156 }; 157 158 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 159 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 160 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 161 #error "Invalid number of bypass priorities" 162 #endif 163 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 164 165 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 166 #define MLX5_IB_NUM_SNIFFER_FTS 2 167 #define MLX5_IB_NUM_EGRESS_FTS 1 168 struct mlx5_ib_flow_prio { 169 struct mlx5_flow_table *flow_table; 170 unsigned int refcount; 171 }; 172 173 struct mlx5_ib_flow_handler { 174 struct list_head list; 175 struct ib_flow ibflow; 176 struct mlx5_ib_flow_prio *prio; 177 struct mlx5_flow_handle *rule; 178 struct ib_counters *ibcounters; 179 }; 180 181 struct mlx5_ib_flow_db { 182 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 183 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 184 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 185 struct mlx5_flow_table *lag_demux_ft; 186 /* Protect flow steering bypass flow tables 187 * when add/del flow rules. 188 * only single add/removal of flow steering rule could be done 189 * simultaneously. 190 */ 191 struct mutex lock; 192 }; 193 194 /* Use macros here so that don't have to duplicate 195 * enum ib_send_flags and enum ib_qp_type for low-level driver 196 */ 197 198 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 199 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 200 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 201 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 202 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 203 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 204 205 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 206 /* 207 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 208 * creates the actual hardware QP. 209 */ 210 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 211 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 212 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 213 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 214 215 #define MLX5_IB_UMR_OCTOWORD 16 216 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 217 218 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 219 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 220 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 221 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 222 #define MLX5_IB_UPD_XLT_PD BIT(4) 223 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 224 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 225 226 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 227 * 228 * These flags are intended for internal use by the mlx5_ib driver, and they 229 * rely on the range reserved for that use in the ib_qp_create_flags enum. 230 */ 231 232 /* Create a UD QP whose source QP number is 1 */ 233 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 234 { 235 return IB_QP_CREATE_RESERVED_START; 236 } 237 238 struct wr_list { 239 u16 opcode; 240 u16 next; 241 }; 242 243 enum mlx5_ib_rq_flags { 244 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 245 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 246 }; 247 248 struct mlx5_ib_wq { 249 u64 *wrid; 250 u32 *wr_data; 251 struct wr_list *w_list; 252 unsigned *wqe_head; 253 u16 unsig_count; 254 255 /* serialize post to the work queue 256 */ 257 spinlock_t lock; 258 int wqe_cnt; 259 int max_post; 260 int max_gs; 261 int offset; 262 int wqe_shift; 263 unsigned head; 264 unsigned tail; 265 u16 cur_post; 266 u16 last_poll; 267 void *qend; 268 }; 269 270 enum mlx5_ib_wq_flags { 271 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 272 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 273 }; 274 275 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 276 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 277 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 278 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 279 280 struct mlx5_ib_rwq { 281 struct ib_wq ibwq; 282 struct mlx5_core_qp core_qp; 283 u32 rq_num_pas; 284 u32 log_rq_stride; 285 u32 log_rq_size; 286 u32 rq_page_offset; 287 u32 log_page_size; 288 u32 log_num_strides; 289 u32 two_byte_shift_en; 290 u32 single_stride_log_num_of_bytes; 291 struct ib_umem *umem; 292 size_t buf_size; 293 unsigned int page_shift; 294 int create_type; 295 struct mlx5_db db; 296 u32 user_index; 297 u32 wqe_count; 298 u32 wqe_shift; 299 int wq_sig; 300 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 301 }; 302 303 enum { 304 MLX5_QP_USER, 305 MLX5_QP_KERNEL, 306 MLX5_QP_EMPTY 307 }; 308 309 enum { 310 MLX5_WQ_USER, 311 MLX5_WQ_KERNEL 312 }; 313 314 struct mlx5_ib_rwq_ind_table { 315 struct ib_rwq_ind_table ib_rwq_ind_tbl; 316 u32 rqtn; 317 }; 318 319 struct mlx5_ib_ubuffer { 320 struct ib_umem *umem; 321 int buf_size; 322 u64 buf_addr; 323 }; 324 325 struct mlx5_ib_qp_base { 326 struct mlx5_ib_qp *container_mibqp; 327 struct mlx5_core_qp mqp; 328 struct mlx5_ib_ubuffer ubuffer; 329 }; 330 331 struct mlx5_ib_qp_trans { 332 struct mlx5_ib_qp_base base; 333 u16 xrcdn; 334 u8 alt_port; 335 u8 atomic_rd_en; 336 u8 resp_depth; 337 }; 338 339 struct mlx5_ib_rss_qp { 340 u32 tirn; 341 }; 342 343 struct mlx5_ib_rq { 344 struct mlx5_ib_qp_base base; 345 struct mlx5_ib_wq *rq; 346 struct mlx5_ib_ubuffer ubuffer; 347 struct mlx5_db *doorbell; 348 u32 tirn; 349 u8 state; 350 u32 flags; 351 }; 352 353 struct mlx5_ib_sq { 354 struct mlx5_ib_qp_base base; 355 struct mlx5_ib_wq *sq; 356 struct mlx5_ib_ubuffer ubuffer; 357 struct mlx5_db *doorbell; 358 struct mlx5_flow_handle *flow_rule; 359 u32 tisn; 360 u8 state; 361 }; 362 363 struct mlx5_ib_raw_packet_qp { 364 struct mlx5_ib_sq sq; 365 struct mlx5_ib_rq rq; 366 }; 367 368 struct mlx5_bf { 369 int buf_size; 370 unsigned long offset; 371 struct mlx5_sq_bfreg *bfreg; 372 }; 373 374 struct mlx5_ib_dct { 375 struct mlx5_core_dct mdct; 376 u32 *in; 377 }; 378 379 struct mlx5_ib_qp { 380 struct ib_qp ibqp; 381 union { 382 struct mlx5_ib_qp_trans trans_qp; 383 struct mlx5_ib_raw_packet_qp raw_packet_qp; 384 struct mlx5_ib_rss_qp rss_qp; 385 struct mlx5_ib_dct dct; 386 }; 387 struct mlx5_frag_buf buf; 388 389 struct mlx5_db db; 390 struct mlx5_ib_wq rq; 391 392 u8 sq_signal_bits; 393 u8 next_fence; 394 struct mlx5_ib_wq sq; 395 396 /* serialize qp state modifications 397 */ 398 struct mutex mutex; 399 u32 flags; 400 u8 port; 401 u8 state; 402 int wq_sig; 403 int scat_cqe; 404 int max_inline_data; 405 struct mlx5_bf bf; 406 int has_rq; 407 408 /* only for user space QPs. For kernel 409 * we have it from the bf object 410 */ 411 int bfregn; 412 413 int create_type; 414 415 /* Store signature errors */ 416 bool signature_en; 417 418 struct list_head qps_list; 419 struct list_head cq_recv_list; 420 struct list_head cq_send_list; 421 struct mlx5_rate_limit rl; 422 u32 underlay_qpn; 423 bool tunnel_offload_en; 424 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 425 enum ib_qp_type qp_sub_type; 426 }; 427 428 struct mlx5_ib_cq_buf { 429 struct mlx5_frag_buf_ctrl fbc; 430 struct ib_umem *umem; 431 int cqe_size; 432 int nent; 433 }; 434 435 enum mlx5_ib_qp_flags { 436 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 437 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 438 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 439 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 440 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 441 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 442 /* QP uses 1 as its source QP number */ 443 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 444 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 445 MLX5_IB_QP_RSS = 1 << 8, 446 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 447 MLX5_IB_QP_UNDERLAY = 1 << 10, 448 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 449 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 450 }; 451 452 struct mlx5_umr_wr { 453 struct ib_send_wr wr; 454 u64 virt_addr; 455 u64 offset; 456 struct ib_pd *pd; 457 unsigned int page_shift; 458 unsigned int xlt_size; 459 u64 length; 460 int access_flags; 461 u32 mkey; 462 }; 463 464 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 465 { 466 return container_of(wr, struct mlx5_umr_wr, wr); 467 } 468 469 struct mlx5_shared_mr_info { 470 int mr_id; 471 struct ib_umem *umem; 472 }; 473 474 enum mlx5_ib_cq_pr_flags { 475 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 476 }; 477 478 struct mlx5_ib_cq { 479 struct ib_cq ibcq; 480 struct mlx5_core_cq mcq; 481 struct mlx5_ib_cq_buf buf; 482 struct mlx5_db db; 483 484 /* serialize access to the CQ 485 */ 486 spinlock_t lock; 487 488 /* protect resize cq 489 */ 490 struct mutex resize_mutex; 491 struct mlx5_ib_cq_buf *resize_buf; 492 struct ib_umem *resize_umem; 493 int cqe_size; 494 struct list_head list_send_qp; 495 struct list_head list_recv_qp; 496 u32 create_flags; 497 struct list_head wc_list; 498 enum ib_cq_notify_flags notify_flags; 499 struct work_struct notify_work; 500 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 501 }; 502 503 struct mlx5_ib_wc { 504 struct ib_wc wc; 505 struct list_head list; 506 }; 507 508 struct mlx5_ib_srq { 509 struct ib_srq ibsrq; 510 struct mlx5_core_srq msrq; 511 struct mlx5_frag_buf buf; 512 struct mlx5_db db; 513 u64 *wrid; 514 /* protect SRQ hanlding 515 */ 516 spinlock_t lock; 517 int head; 518 int tail; 519 u16 wqe_ctr; 520 struct ib_umem *umem; 521 /* serialize arming a SRQ 522 */ 523 struct mutex mutex; 524 int wq_sig; 525 }; 526 527 struct mlx5_ib_xrcd { 528 struct ib_xrcd ibxrcd; 529 u32 xrcdn; 530 }; 531 532 enum mlx5_ib_mtt_access_flags { 533 MLX5_IB_MTT_READ = (1 << 0), 534 MLX5_IB_MTT_WRITE = (1 << 1), 535 }; 536 537 struct mlx5_ib_dm { 538 struct ib_dm ibdm; 539 phys_addr_t dev_addr; 540 }; 541 542 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 543 544 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 545 IB_ACCESS_REMOTE_WRITE |\ 546 IB_ACCESS_REMOTE_READ |\ 547 IB_ACCESS_REMOTE_ATOMIC |\ 548 IB_ZERO_BASED) 549 550 struct mlx5_ib_mr { 551 struct ib_mr ibmr; 552 void *descs; 553 dma_addr_t desc_map; 554 int ndescs; 555 int max_descs; 556 int desc_size; 557 int access_mode; 558 struct mlx5_core_mkey mmkey; 559 struct ib_umem *umem; 560 struct mlx5_shared_mr_info *smr_info; 561 struct list_head list; 562 int order; 563 bool allocated_from_cache; 564 int npages; 565 struct mlx5_ib_dev *dev; 566 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 567 struct mlx5_core_sig_ctx *sig; 568 int live; 569 void *descs_alloc; 570 int access_flags; /* Needed for rereg MR */ 571 572 struct mlx5_ib_mr *parent; 573 atomic_t num_leaf_free; 574 wait_queue_head_t q_leaf_free; 575 }; 576 577 struct mlx5_ib_mw { 578 struct ib_mw ibmw; 579 struct mlx5_core_mkey mmkey; 580 int ndescs; 581 }; 582 583 struct mlx5_ib_umr_context { 584 struct ib_cqe cqe; 585 enum ib_wc_status status; 586 struct completion done; 587 }; 588 589 struct umr_common { 590 struct ib_pd *pd; 591 struct ib_cq *cq; 592 struct ib_qp *qp; 593 /* control access to UMR QP 594 */ 595 struct semaphore sem; 596 }; 597 598 enum { 599 MLX5_FMR_INVALID, 600 MLX5_FMR_VALID, 601 MLX5_FMR_BUSY, 602 }; 603 604 struct mlx5_cache_ent { 605 struct list_head head; 606 /* sync access to the cahce entry 607 */ 608 spinlock_t lock; 609 610 611 struct dentry *dir; 612 char name[4]; 613 u32 order; 614 u32 xlt; 615 u32 access_mode; 616 u32 page; 617 618 u32 size; 619 u32 cur; 620 u32 miss; 621 u32 limit; 622 623 struct dentry *fsize; 624 struct dentry *fcur; 625 struct dentry *fmiss; 626 struct dentry *flimit; 627 628 struct mlx5_ib_dev *dev; 629 struct work_struct work; 630 struct delayed_work dwork; 631 int pending; 632 struct completion compl; 633 }; 634 635 struct mlx5_mr_cache { 636 struct workqueue_struct *wq; 637 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 638 int stopped; 639 struct dentry *root; 640 unsigned long last_add; 641 }; 642 643 struct mlx5_ib_gsi_qp; 644 645 struct mlx5_ib_port_resources { 646 struct mlx5_ib_resources *devr; 647 struct mlx5_ib_gsi_qp *gsi; 648 struct work_struct pkey_change_work; 649 }; 650 651 struct mlx5_ib_resources { 652 struct ib_cq *c0; 653 struct ib_xrcd *x0; 654 struct ib_xrcd *x1; 655 struct ib_pd *p0; 656 struct ib_srq *s0; 657 struct ib_srq *s1; 658 struct mlx5_ib_port_resources ports[2]; 659 /* Protects changes to the port resources */ 660 struct mutex mutex; 661 }; 662 663 struct mlx5_ib_counters { 664 const char **names; 665 size_t *offsets; 666 u32 num_q_counters; 667 u32 num_cong_counters; 668 u16 set_id; 669 bool set_id_valid; 670 }; 671 672 struct mlx5_ib_multiport_info; 673 674 struct mlx5_ib_multiport { 675 struct mlx5_ib_multiport_info *mpi; 676 /* To be held when accessing the multiport info */ 677 spinlock_t mpi_lock; 678 }; 679 680 struct mlx5_ib_port { 681 struct mlx5_ib_counters cnts; 682 struct mlx5_ib_multiport mp; 683 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 684 }; 685 686 struct mlx5_roce { 687 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 688 * netdev pointer 689 */ 690 rwlock_t netdev_lock; 691 struct net_device *netdev; 692 struct notifier_block nb; 693 atomic_t next_port; 694 enum ib_port_state last_port_state; 695 struct mlx5_ib_dev *dev; 696 u8 native_port_num; 697 }; 698 699 struct mlx5_ib_dbg_param { 700 int offset; 701 struct mlx5_ib_dev *dev; 702 struct dentry *dentry; 703 u8 port_num; 704 }; 705 706 enum mlx5_ib_dbg_cc_types { 707 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 708 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 709 MLX5_IB_DBG_CC_RP_TIME_RESET, 710 MLX5_IB_DBG_CC_RP_BYTE_RESET, 711 MLX5_IB_DBG_CC_RP_THRESHOLD, 712 MLX5_IB_DBG_CC_RP_AI_RATE, 713 MLX5_IB_DBG_CC_RP_HAI_RATE, 714 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 715 MLX5_IB_DBG_CC_RP_MIN_RATE, 716 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 717 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 718 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 719 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 720 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 721 MLX5_IB_DBG_CC_RP_GD, 722 MLX5_IB_DBG_CC_NP_CNP_DSCP, 723 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 724 MLX5_IB_DBG_CC_NP_CNP_PRIO, 725 MLX5_IB_DBG_CC_MAX, 726 }; 727 728 struct mlx5_ib_dbg_cc_params { 729 struct dentry *root; 730 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 731 }; 732 733 enum { 734 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 735 }; 736 737 struct mlx5_ib_dbg_delay_drop { 738 struct dentry *dir_debugfs; 739 struct dentry *rqs_cnt_debugfs; 740 struct dentry *events_cnt_debugfs; 741 struct dentry *timeout_debugfs; 742 }; 743 744 struct mlx5_ib_delay_drop { 745 struct mlx5_ib_dev *dev; 746 struct work_struct delay_drop_work; 747 /* serialize setting of delay drop */ 748 struct mutex lock; 749 u32 timeout; 750 bool activate; 751 atomic_t events_cnt; 752 atomic_t rqs_cnt; 753 struct mlx5_ib_dbg_delay_drop *dbg; 754 }; 755 756 enum mlx5_ib_stages { 757 MLX5_IB_STAGE_INIT, 758 MLX5_IB_STAGE_FLOW_DB, 759 MLX5_IB_STAGE_CAPS, 760 MLX5_IB_STAGE_NON_DEFAULT_CB, 761 MLX5_IB_STAGE_ROCE, 762 MLX5_IB_STAGE_DEVICE_RESOURCES, 763 MLX5_IB_STAGE_ODP, 764 MLX5_IB_STAGE_COUNTERS, 765 MLX5_IB_STAGE_CONG_DEBUGFS, 766 MLX5_IB_STAGE_UAR, 767 MLX5_IB_STAGE_BFREG, 768 MLX5_IB_STAGE_PRE_IB_REG_UMR, 769 MLX5_IB_STAGE_SPECS, 770 MLX5_IB_STAGE_IB_REG, 771 MLX5_IB_STAGE_POST_IB_REG_UMR, 772 MLX5_IB_STAGE_DELAY_DROP, 773 MLX5_IB_STAGE_CLASS_ATTR, 774 MLX5_IB_STAGE_REP_REG, 775 MLX5_IB_STAGE_MAX, 776 }; 777 778 struct mlx5_ib_stage { 779 int (*init)(struct mlx5_ib_dev *dev); 780 void (*cleanup)(struct mlx5_ib_dev *dev); 781 }; 782 783 #define STAGE_CREATE(_stage, _init, _cleanup) \ 784 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 785 786 struct mlx5_ib_profile { 787 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 788 }; 789 790 struct mlx5_ib_multiport_info { 791 struct list_head list; 792 struct mlx5_ib_dev *ibdev; 793 struct mlx5_core_dev *mdev; 794 struct completion unref_comp; 795 u64 sys_image_guid; 796 u32 mdev_refcnt; 797 bool is_master; 798 bool unaffiliate; 799 }; 800 801 struct mlx5_ib_flow_action { 802 struct ib_flow_action ib_action; 803 union { 804 struct { 805 u64 ib_flags; 806 struct mlx5_accel_esp_xfrm *ctx; 807 } esp_aes_gcm; 808 }; 809 }; 810 811 struct mlx5_memic { 812 struct mlx5_core_dev *dev; 813 spinlock_t memic_lock; 814 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 815 }; 816 817 struct mlx5_read_counters_attr { 818 struct mlx5_fc *hw_cntrs_hndl; 819 u64 *out; 820 u32 flags; 821 }; 822 823 enum mlx5_ib_counters_type { 824 MLX5_IB_COUNTERS_FLOW, 825 }; 826 827 struct mlx5_ib_mcounters { 828 struct ib_counters ibcntrs; 829 enum mlx5_ib_counters_type type; 830 /* number of counters supported for this counters type */ 831 u32 counters_num; 832 struct mlx5_fc *hw_cntrs_hndl; 833 /* read function for this counters type */ 834 int (*read_counters)(struct ib_device *ibdev, 835 struct mlx5_read_counters_attr *read_attr); 836 /* max index set as part of create_flow */ 837 u32 cntrs_max_index; 838 /* number of counters data entries (<description,index> pair) */ 839 u32 ncounters; 840 /* counters data array for descriptions and indexes */ 841 struct mlx5_ib_flow_counters_desc *counters_data; 842 /* protects access to mcounters internal data */ 843 struct mutex mcntrs_mutex; 844 }; 845 846 static inline struct mlx5_ib_mcounters * 847 to_mcounters(struct ib_counters *ibcntrs) 848 { 849 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 850 } 851 852 struct mlx5_ib_dev { 853 struct ib_device ib_dev; 854 struct mlx5_core_dev *mdev; 855 struct mlx5_roce roce[MLX5_MAX_PORTS]; 856 int num_ports; 857 /* serialize update of capability mask 858 */ 859 struct mutex cap_mask_mutex; 860 bool ib_active; 861 struct umr_common umrc; 862 /* sync used page count stats 863 */ 864 struct mlx5_ib_resources devr; 865 struct mlx5_mr_cache cache; 866 struct timer_list delay_timer; 867 /* Prevents soft lock on massive reg MRs */ 868 struct mutex slow_path_mutex; 869 int fill_delay; 870 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 871 struct ib_odp_caps odp_caps; 872 u64 odp_max_size; 873 /* 874 * Sleepable RCU that prevents destruction of MRs while they are still 875 * being used by a page fault handler. 876 */ 877 struct srcu_struct mr_srcu; 878 u32 null_mkey; 879 #endif 880 struct mlx5_ib_flow_db *flow_db; 881 /* protect resources needed as part of reset flow */ 882 spinlock_t reset_flow_resource_lock; 883 struct list_head qp_list; 884 /* Array with num_ports elements */ 885 struct mlx5_ib_port *port; 886 struct mlx5_sq_bfreg bfreg; 887 struct mlx5_sq_bfreg fp_bfreg; 888 struct mlx5_ib_delay_drop delay_drop; 889 const struct mlx5_ib_profile *profile; 890 struct mlx5_eswitch_rep *rep; 891 892 /* protect the user_td */ 893 struct mutex lb_mutex; 894 u32 user_td; 895 u8 umr_fence; 896 struct list_head ib_dev_list; 897 u64 sys_image_guid; 898 struct mlx5_memic memic; 899 }; 900 901 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 902 { 903 return container_of(mcq, struct mlx5_ib_cq, mcq); 904 } 905 906 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 907 { 908 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 909 } 910 911 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 912 { 913 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 914 } 915 916 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 917 { 918 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 919 } 920 921 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 922 { 923 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 924 } 925 926 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 927 { 928 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 929 } 930 931 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 932 { 933 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 934 } 935 936 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 937 { 938 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 939 } 940 941 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 942 { 943 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 944 } 945 946 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 947 { 948 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 949 } 950 951 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 952 { 953 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 954 } 955 956 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 957 { 958 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 959 } 960 961 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 962 { 963 return container_of(msrq, struct mlx5_ib_srq, msrq); 964 } 965 966 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 967 { 968 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 969 } 970 971 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 972 { 973 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 974 } 975 976 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 977 { 978 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 979 } 980 981 static inline struct mlx5_ib_flow_action * 982 to_mflow_act(struct ib_flow_action *ibact) 983 { 984 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 985 } 986 987 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 988 struct mlx5_db *db); 989 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 990 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 991 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 992 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 993 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 994 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 995 const void *in_mad, void *response_mad); 996 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 997 struct ib_udata *udata); 998 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 999 int mlx5_ib_destroy_ah(struct ib_ah *ah); 1000 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 1001 struct ib_srq_init_attr *init_attr, 1002 struct ib_udata *udata); 1003 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1004 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1005 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1006 int mlx5_ib_destroy_srq(struct ib_srq *srq); 1007 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 1008 struct ib_recv_wr **bad_wr); 1009 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1010 struct ib_qp_init_attr *init_attr, 1011 struct ib_udata *udata); 1012 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1013 int attr_mask, struct ib_udata *udata); 1014 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1015 struct ib_qp_init_attr *qp_init_attr); 1016 int mlx5_ib_destroy_qp(struct ib_qp *qp); 1017 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 1018 struct ib_send_wr **bad_wr); 1019 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 1020 struct ib_recv_wr **bad_wr); 1021 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 1022 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 1023 void *buffer, u32 length, 1024 struct mlx5_ib_qp_base *base); 1025 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 1026 const struct ib_cq_init_attr *attr, 1027 struct ib_ucontext *context, 1028 struct ib_udata *udata); 1029 int mlx5_ib_destroy_cq(struct ib_cq *cq); 1030 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1031 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1032 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1033 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1034 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1035 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1036 u64 virt_addr, int access_flags, 1037 struct ib_udata *udata); 1038 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1039 struct ib_udata *udata); 1040 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1041 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1042 int page_shift, int flags); 1043 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1044 int access_flags); 1045 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1046 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1047 u64 length, u64 virt_addr, int access_flags, 1048 struct ib_pd *pd, struct ib_udata *udata); 1049 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 1050 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 1051 enum ib_mr_type mr_type, 1052 u32 max_num_sg); 1053 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1054 unsigned int *sg_offset); 1055 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1056 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1057 const struct ib_mad_hdr *in, size_t in_mad_size, 1058 struct ib_mad_hdr *out, size_t *out_mad_size, 1059 u16 *out_mad_pkey_index); 1060 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1061 struct ib_ucontext *context, 1062 struct ib_udata *udata); 1063 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 1064 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1065 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1066 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1067 struct ib_smp *out_mad); 1068 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1069 __be64 *sys_image_guid); 1070 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1071 u16 *max_pkeys); 1072 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1073 u32 *vendor_id); 1074 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1075 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1076 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1077 u16 *pkey); 1078 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1079 union ib_gid *gid); 1080 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1081 struct ib_port_attr *props); 1082 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1083 struct ib_port_attr *props); 1084 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1085 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1086 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1087 unsigned long max_page_shift, 1088 int *count, int *shift, 1089 int *ncont, int *order); 1090 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1091 int page_shift, size_t offset, size_t num_pages, 1092 __be64 *pas, int access_flags); 1093 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1094 int page_shift, __be64 *pas, int access_flags); 1095 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1096 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 1097 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1098 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1099 1100 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1101 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1102 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1103 struct ib_mr_status *mr_status); 1104 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1105 struct ib_wq_init_attr *init_attr, 1106 struct ib_udata *udata); 1107 int mlx5_ib_destroy_wq(struct ib_wq *wq); 1108 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1109 u32 wq_attr_mask, struct ib_udata *udata); 1110 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1111 struct ib_rwq_ind_table_init_attr *init_attr, 1112 struct ib_udata *udata); 1113 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1114 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); 1115 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1116 struct ib_ucontext *context, 1117 struct ib_dm_alloc_attr *attr, 1118 struct uverbs_attr_bundle *attrs); 1119 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm); 1120 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1121 struct ib_dm_mr_attr *attr, 1122 struct uverbs_attr_bundle *attrs); 1123 1124 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1125 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1126 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, 1127 struct mlx5_pagefault *pfault); 1128 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1129 int __init mlx5_ib_odp_init(void); 1130 void mlx5_ib_odp_cleanup(void); 1131 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 1132 unsigned long end); 1133 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1134 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1135 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1136 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1137 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1138 { 1139 return; 1140 } 1141 1142 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1143 static inline int mlx5_ib_odp_init(void) { return 0; } 1144 static inline void mlx5_ib_odp_cleanup(void) {} 1145 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1146 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1147 size_t nentries, struct mlx5_ib_mr *mr, 1148 int flags) {} 1149 1150 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1151 1152 /* Needed for rep profile */ 1153 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev); 1154 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev); 1155 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev); 1156 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev); 1157 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev); 1158 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev); 1159 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev); 1160 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev); 1161 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev); 1162 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev); 1163 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev); 1164 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev); 1165 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev); 1166 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev); 1167 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev); 1168 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev); 1169 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev); 1170 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev); 1171 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1172 const struct mlx5_ib_profile *profile, 1173 int stage); 1174 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1175 const struct mlx5_ib_profile *profile); 1176 1177 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1178 u8 port, struct ifla_vf_info *info); 1179 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1180 u8 port, int state); 1181 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1182 u8 port, struct ifla_vf_stats *stats); 1183 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1184 u64 guid, int type); 1185 1186 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 1187 int index); 1188 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 1189 int index, enum ib_gid_type *gid_type); 1190 1191 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1192 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1193 1194 /* GSI QP helper functions */ 1195 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1196 struct ib_qp_init_attr *init_attr); 1197 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1198 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1199 int attr_mask); 1200 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1201 int qp_attr_mask, 1202 struct ib_qp_init_attr *qp_init_attr); 1203 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 1204 struct ib_send_wr **bad_wr); 1205 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 1206 struct ib_recv_wr **bad_wr); 1207 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1208 1209 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1210 1211 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1212 int bfregn); 1213 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1214 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1215 u8 ib_port_num, 1216 u8 *native_port_num); 1217 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1218 u8 port_num); 1219 1220 static inline void init_query_mad(struct ib_smp *mad) 1221 { 1222 mad->base_version = 1; 1223 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1224 mad->class_version = 1; 1225 mad->method = IB_MGMT_METHOD_GET; 1226 } 1227 1228 static inline u8 convert_access(int acc) 1229 { 1230 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1231 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1232 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1233 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1234 MLX5_PERM_LOCAL_READ; 1235 } 1236 1237 static inline int is_qp1(enum ib_qp_type qp_type) 1238 { 1239 return qp_type == MLX5_IB_QPT_HW_GSI; 1240 } 1241 1242 #define MLX5_MAX_UMR_SHIFT 16 1243 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1244 1245 static inline u32 check_cq_create_flags(u32 flags) 1246 { 1247 /* 1248 * It returns non-zero value for unsupported CQ 1249 * create flags, otherwise it returns zero. 1250 */ 1251 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1252 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1253 } 1254 1255 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1256 u32 *user_index) 1257 { 1258 if (cqe_version) { 1259 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1260 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1261 return -EINVAL; 1262 *user_index = cmd_uidx; 1263 } else { 1264 *user_index = MLX5_IB_DEFAULT_UIDX; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1271 struct mlx5_ib_create_qp *ucmd, 1272 int inlen, 1273 u32 *user_index) 1274 { 1275 u8 cqe_version = ucontext->cqe_version; 1276 1277 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1278 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1279 return 0; 1280 1281 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1282 !!cqe_version)) 1283 return -EINVAL; 1284 1285 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1286 } 1287 1288 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1289 struct mlx5_ib_create_srq *ucmd, 1290 int inlen, 1291 u32 *user_index) 1292 { 1293 u8 cqe_version = ucontext->cqe_version; 1294 1295 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1296 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1297 return 0; 1298 1299 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1300 !!cqe_version)) 1301 return -EINVAL; 1302 1303 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1304 } 1305 1306 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1307 { 1308 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1309 MLX5_UARS_IN_PAGE : 1; 1310 } 1311 1312 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1313 struct mlx5_bfreg_info *bfregi) 1314 { 1315 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1316 } 1317 1318 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1319 void mlx5_ib_put_xlt_emergency_page(void); 1320 1321 #endif /* MLX5_IB_H */ 1322