1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 29 #define mlx5_ib_dbg(_dev, format, arg...) \ 30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 31 __LINE__, current->pid, ##arg) 32 33 #define mlx5_ib_err(_dev, format, arg...) \ 34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 35 __LINE__, current->pid, ##arg) 36 37 #define mlx5_ib_warn(_dev, format, arg...) \ 38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 39 __LINE__, current->pid, ##arg) 40 41 #define mlx5_ib_log(lvl, _dev, format, arg...) \ 42 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \ 43 __func__, __LINE__, current->pid, ##arg) 44 45 #define MLX5_IB_DEFAULT_UIDX 0xffffff 46 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 47 48 static __always_inline unsigned long 49 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 50 unsigned int pgsz_shift) 51 { 52 unsigned int largest_pg_shift = 53 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 54 BITS_PER_LONG - 1); 55 56 /* 57 * Despite a command allowing it, the device does not support lower than 58 * 4k page size. 59 */ 60 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 61 return GENMASK(largest_pg_shift, pgsz_shift); 62 } 63 64 /* 65 * For mkc users, instead of a page_offset the command has a start_iova which 66 * specifies both the page_offset and the on-the-wire IOVA 67 */ 68 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \ 69 ib_umem_find_best_pgsz(umem, \ 70 __mlx5_log_page_size_to_bitmap( \ 71 __mlx5_bit_sz(typ, log_pgsz_fld), \ 72 pgsz_shift), \ 73 iova) 74 75 static __always_inline unsigned long 76 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 77 unsigned int offset_shift) 78 { 79 unsigned int largest_offset_shift = 80 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 81 BITS_PER_LONG - 1); 82 83 return GENMASK(largest_offset_shift, offset_shift); 84 } 85 86 /* 87 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 88 * page_offset_quantized * (page_size/scale) = page_offset 89 * Which restricts allowed page sizes to ones that satisify the above. 90 */ 91 unsigned long __mlx5_umem_find_best_quantized_pgoff( 92 struct ib_umem *umem, unsigned long pgsz_bitmap, 93 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 94 unsigned int *page_offset_quantized); 95 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 96 pgsz_shift, page_offset_fld, \ 97 scale, page_offset_quantized) \ 98 __mlx5_umem_find_best_quantized_pgoff( \ 99 umem, \ 100 __mlx5_log_page_size_to_bitmap( \ 101 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 102 __mlx5_bit_sz(typ, page_offset_fld), \ 103 GENMASK(31, order_base_2(scale)), scale, \ 104 page_offset_quantized) 105 106 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 107 pgsz_shift, page_offset_fld, \ 108 scale, page_offset_quantized) \ 109 __mlx5_umem_find_best_quantized_pgoff( \ 110 umem, \ 111 __mlx5_log_page_size_to_bitmap( \ 112 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 113 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 114 page_offset_quantized) 115 116 enum { 117 MLX5_IB_MMAP_OFFSET_START = 9, 118 MLX5_IB_MMAP_OFFSET_END = 255, 119 }; 120 121 enum { 122 MLX5_IB_MMAP_CMD_SHIFT = 8, 123 MLX5_IB_MMAP_CMD_MASK = 0xff, 124 }; 125 126 enum { 127 MLX5_RES_SCAT_DATA32_CQE = 0x1, 128 MLX5_RES_SCAT_DATA64_CQE = 0x2, 129 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 130 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 131 }; 132 133 enum mlx5_ib_mad_ifc_flags { 134 MLX5_MAD_IFC_IGNORE_MKEY = 1, 135 MLX5_MAD_IFC_IGNORE_BKEY = 2, 136 MLX5_MAD_IFC_NET_VIEW = 4, 137 }; 138 139 enum { 140 MLX5_CROSS_CHANNEL_BFREG = 0, 141 }; 142 143 enum { 144 MLX5_CQE_VERSION_V0, 145 MLX5_CQE_VERSION_V1, 146 }; 147 148 enum { 149 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 150 MLX5_TM_MAX_SGE = 1, 151 }; 152 153 enum { 154 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 155 MLX5_IB_INVALID_BFREG = BIT(31), 156 }; 157 158 enum { 159 MLX5_MAX_MEMIC_PAGES = 0x100, 160 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 161 }; 162 163 enum { 164 MLX5_MEMIC_BASE_ALIGN = 6, 165 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 166 }; 167 168 enum mlx5_ib_mmap_type { 169 MLX5_IB_MMAP_TYPE_MEMIC = 1, 170 MLX5_IB_MMAP_TYPE_VAR = 2, 171 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 172 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 173 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 174 }; 175 176 struct mlx5_bfreg_info { 177 u32 *sys_pages; 178 int num_low_latency_bfregs; 179 unsigned int *count; 180 181 /* 182 * protect bfreg allocation data structs 183 */ 184 struct mutex lock; 185 u32 ver; 186 u8 lib_uar_4k : 1; 187 u8 lib_uar_dyn : 1; 188 u32 num_sys_pages; 189 u32 num_static_sys_pages; 190 u32 total_num_bfregs; 191 u32 num_dyn_bfregs; 192 }; 193 194 struct mlx5_ib_ucontext { 195 struct ib_ucontext ibucontext; 196 struct list_head db_page_list; 197 198 /* protect doorbell record alloc/free 199 */ 200 struct mutex db_page_mutex; 201 struct mlx5_bfreg_info bfregi; 202 u8 cqe_version; 203 /* Transport Domain number */ 204 u32 tdn; 205 206 u64 lib_caps; 207 u16 devx_uid; 208 /* For RoCE LAG TX affinity */ 209 atomic_t tx_port_affinity; 210 }; 211 212 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 213 { 214 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 215 } 216 217 struct mlx5_ib_pd { 218 struct ib_pd ibpd; 219 u32 pdn; 220 u16 uid; 221 }; 222 223 enum { 224 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 225 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 226 MLX5_IB_FLOW_ACTION_DECAP, 227 }; 228 229 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 230 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 231 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 232 #error "Invalid number of bypass priorities" 233 #endif 234 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 235 236 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 237 #define MLX5_IB_NUM_SNIFFER_FTS 2 238 #define MLX5_IB_NUM_EGRESS_FTS 1 239 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 240 241 struct mlx5_ib_anchor { 242 struct mlx5_flow_table *ft; 243 struct mlx5_flow_group *fg_goto_table; 244 struct mlx5_flow_group *fg_drop; 245 struct mlx5_flow_handle *rule_goto_table; 246 struct mlx5_flow_handle *rule_drop; 247 unsigned int rule_goto_table_ref; 248 }; 249 250 struct mlx5_ib_flow_prio { 251 struct mlx5_flow_table *flow_table; 252 struct mlx5_ib_anchor anchor; 253 unsigned int refcount; 254 }; 255 256 struct mlx5_ib_flow_handler { 257 struct list_head list; 258 struct ib_flow ibflow; 259 struct mlx5_ib_flow_prio *prio; 260 struct mlx5_flow_handle *rule; 261 struct ib_counters *ibcounters; 262 struct mlx5_ib_dev *dev; 263 struct mlx5_ib_flow_matcher *flow_matcher; 264 }; 265 266 struct mlx5_ib_flow_matcher { 267 struct mlx5_ib_match_params matcher_mask; 268 int mask_len; 269 enum mlx5_ib_flow_type flow_type; 270 enum mlx5_flow_namespace_type ns_type; 271 u16 priority; 272 struct mlx5_core_dev *mdev; 273 atomic_t usecnt; 274 u8 match_criteria_enable; 275 }; 276 277 struct mlx5_ib_steering_anchor { 278 struct mlx5_ib_flow_prio *ft_prio; 279 struct mlx5_ib_dev *dev; 280 atomic_t usecnt; 281 }; 282 283 struct mlx5_ib_pp { 284 u16 index; 285 struct mlx5_core_dev *mdev; 286 }; 287 288 enum mlx5_ib_optional_counter_type { 289 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 290 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 291 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 292 293 MLX5_IB_OPCOUNTER_MAX, 294 }; 295 296 struct mlx5_ib_flow_db { 297 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 298 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 299 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 300 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 301 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 302 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 303 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 304 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 305 struct mlx5_flow_table *lag_demux_ft; 306 /* Protect flow steering bypass flow tables 307 * when add/del flow rules. 308 * only single add/removal of flow steering rule could be done 309 * simultaneously. 310 */ 311 struct mutex lock; 312 }; 313 314 /* Use macros here so that don't have to duplicate 315 * enum ib_qp_type for low-level driver 316 */ 317 318 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 319 /* 320 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 321 * creates the actual hardware QP. 322 */ 323 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 324 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 325 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 326 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 327 328 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 329 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 330 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 331 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 332 #define MLX5_IB_UPD_XLT_PD BIT(4) 333 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 334 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 335 336 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 337 * 338 * These flags are intended for internal use by the mlx5_ib driver, and they 339 * rely on the range reserved for that use in the ib_qp_create_flags enum. 340 */ 341 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 342 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 343 344 struct wr_list { 345 u16 opcode; 346 u16 next; 347 }; 348 349 enum mlx5_ib_rq_flags { 350 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 351 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 352 }; 353 354 struct mlx5_ib_wq { 355 struct mlx5_frag_buf_ctrl fbc; 356 u64 *wrid; 357 u32 *wr_data; 358 struct wr_list *w_list; 359 unsigned *wqe_head; 360 u16 unsig_count; 361 362 /* serialize post to the work queue 363 */ 364 spinlock_t lock; 365 int wqe_cnt; 366 int max_post; 367 int max_gs; 368 int offset; 369 int wqe_shift; 370 unsigned head; 371 unsigned tail; 372 u16 cur_post; 373 u16 last_poll; 374 void *cur_edge; 375 }; 376 377 enum mlx5_ib_wq_flags { 378 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 379 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 380 }; 381 382 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 383 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 384 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 385 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 386 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 387 388 struct mlx5_ib_rwq { 389 struct ib_wq ibwq; 390 struct mlx5_core_qp core_qp; 391 u32 rq_num_pas; 392 u32 log_rq_stride; 393 u32 log_rq_size; 394 u32 rq_page_offset; 395 u32 log_page_size; 396 u32 log_num_strides; 397 u32 two_byte_shift_en; 398 u32 single_stride_log_num_of_bytes; 399 struct ib_umem *umem; 400 size_t buf_size; 401 unsigned int page_shift; 402 struct mlx5_db db; 403 u32 user_index; 404 u32 wqe_count; 405 u32 wqe_shift; 406 int wq_sig; 407 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 408 }; 409 410 struct mlx5_ib_rwq_ind_table { 411 struct ib_rwq_ind_table ib_rwq_ind_tbl; 412 u32 rqtn; 413 u16 uid; 414 }; 415 416 struct mlx5_ib_ubuffer { 417 struct ib_umem *umem; 418 int buf_size; 419 u64 buf_addr; 420 }; 421 422 struct mlx5_ib_qp_base { 423 struct mlx5_ib_qp *container_mibqp; 424 struct mlx5_core_qp mqp; 425 struct mlx5_ib_ubuffer ubuffer; 426 }; 427 428 struct mlx5_ib_qp_trans { 429 struct mlx5_ib_qp_base base; 430 u16 xrcdn; 431 u32 alt_port; 432 u8 atomic_rd_en; 433 u8 resp_depth; 434 }; 435 436 struct mlx5_ib_rss_qp { 437 u32 tirn; 438 }; 439 440 struct mlx5_ib_rq { 441 struct mlx5_ib_qp_base base; 442 struct mlx5_ib_wq *rq; 443 struct mlx5_ib_ubuffer ubuffer; 444 struct mlx5_db *doorbell; 445 u32 tirn; 446 u8 state; 447 u32 flags; 448 }; 449 450 struct mlx5_ib_sq { 451 struct mlx5_ib_qp_base base; 452 struct mlx5_ib_wq *sq; 453 struct mlx5_ib_ubuffer ubuffer; 454 struct mlx5_db *doorbell; 455 struct mlx5_flow_handle *flow_rule; 456 u32 tisn; 457 u8 state; 458 }; 459 460 struct mlx5_ib_raw_packet_qp { 461 struct mlx5_ib_sq sq; 462 struct mlx5_ib_rq rq; 463 }; 464 465 struct mlx5_bf { 466 int buf_size; 467 unsigned long offset; 468 struct mlx5_sq_bfreg *bfreg; 469 }; 470 471 struct mlx5_ib_dct { 472 struct mlx5_core_dct mdct; 473 u32 *in; 474 }; 475 476 struct mlx5_ib_gsi_qp { 477 struct ib_qp *rx_qp; 478 u32 port_num; 479 struct ib_qp_cap cap; 480 struct ib_cq *cq; 481 struct mlx5_ib_gsi_wr *outstanding_wrs; 482 u32 outstanding_pi, outstanding_ci; 483 int num_qps; 484 /* Protects access to the tx_qps. Post send operations synchronize 485 * with tx_qp creation in setup_qp(). Also protects the 486 * outstanding_wrs array and indices. 487 */ 488 spinlock_t lock; 489 struct ib_qp **tx_qps; 490 }; 491 492 struct mlx5_ib_qp { 493 struct ib_qp ibqp; 494 union { 495 struct mlx5_ib_qp_trans trans_qp; 496 struct mlx5_ib_raw_packet_qp raw_packet_qp; 497 struct mlx5_ib_rss_qp rss_qp; 498 struct mlx5_ib_dct dct; 499 struct mlx5_ib_gsi_qp gsi; 500 }; 501 struct mlx5_frag_buf buf; 502 503 struct mlx5_db db; 504 struct mlx5_ib_wq rq; 505 506 u8 sq_signal_bits; 507 u8 next_fence; 508 struct mlx5_ib_wq sq; 509 510 /* serialize qp state modifications 511 */ 512 struct mutex mutex; 513 /* cached variant of create_flags from struct ib_qp_init_attr */ 514 u32 flags; 515 u32 port; 516 u8 state; 517 int max_inline_data; 518 struct mlx5_bf bf; 519 u8 has_rq:1; 520 u8 is_rss:1; 521 522 /* only for user space QPs. For kernel 523 * we have it from the bf object 524 */ 525 int bfregn; 526 527 struct list_head qps_list; 528 struct list_head cq_recv_list; 529 struct list_head cq_send_list; 530 struct mlx5_rate_limit rl; 531 u32 underlay_qpn; 532 u32 flags_en; 533 /* 534 * IB/core doesn't store low-level QP types, so 535 * store both MLX and IBTA types in the field below. 536 */ 537 enum ib_qp_type type; 538 /* A flag to indicate if there's a new counter is configured 539 * but not take effective 540 */ 541 u32 counter_pending; 542 u16 gsi_lag_port; 543 }; 544 545 struct mlx5_ib_cq_buf { 546 struct mlx5_frag_buf_ctrl fbc; 547 struct mlx5_frag_buf frag_buf; 548 struct ib_umem *umem; 549 int cqe_size; 550 int nent; 551 }; 552 553 enum mlx5_ib_cq_pr_flags { 554 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 555 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 556 }; 557 558 struct mlx5_ib_cq { 559 struct ib_cq ibcq; 560 struct mlx5_core_cq mcq; 561 struct mlx5_ib_cq_buf buf; 562 struct mlx5_db db; 563 564 /* serialize access to the CQ 565 */ 566 spinlock_t lock; 567 568 /* protect resize cq 569 */ 570 struct mutex resize_mutex; 571 struct mlx5_ib_cq_buf *resize_buf; 572 struct ib_umem *resize_umem; 573 int cqe_size; 574 struct list_head list_send_qp; 575 struct list_head list_recv_qp; 576 u32 create_flags; 577 struct list_head wc_list; 578 enum ib_cq_notify_flags notify_flags; 579 struct work_struct notify_work; 580 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 581 }; 582 583 struct mlx5_ib_wc { 584 struct ib_wc wc; 585 struct list_head list; 586 }; 587 588 struct mlx5_ib_srq { 589 struct ib_srq ibsrq; 590 struct mlx5_core_srq msrq; 591 struct mlx5_frag_buf buf; 592 struct mlx5_db db; 593 struct mlx5_frag_buf_ctrl fbc; 594 u64 *wrid; 595 /* protect SRQ hanlding 596 */ 597 spinlock_t lock; 598 int head; 599 int tail; 600 u16 wqe_ctr; 601 struct ib_umem *umem; 602 /* serialize arming a SRQ 603 */ 604 struct mutex mutex; 605 int wq_sig; 606 }; 607 608 struct mlx5_ib_xrcd { 609 struct ib_xrcd ibxrcd; 610 u32 xrcdn; 611 }; 612 613 enum mlx5_ib_mtt_access_flags { 614 MLX5_IB_MTT_READ = (1 << 0), 615 MLX5_IB_MTT_WRITE = (1 << 1), 616 }; 617 618 struct mlx5_user_mmap_entry { 619 struct rdma_user_mmap_entry rdma_entry; 620 u8 mmap_flag; 621 u64 address; 622 u32 page_idx; 623 }; 624 625 enum mlx5_mkey_type { 626 MLX5_MKEY_MR = 1, 627 MLX5_MKEY_MW, 628 MLX5_MKEY_INDIRECT_DEVX, 629 }; 630 631 struct mlx5r_cache_rb_key { 632 u8 ats:1; 633 unsigned int access_mode; 634 unsigned int access_flags; 635 unsigned int ndescs; 636 }; 637 638 struct mlx5_ib_mkey { 639 u32 key; 640 enum mlx5_mkey_type type; 641 unsigned int ndescs; 642 struct wait_queue_head wait; 643 refcount_t usecount; 644 /* User Mkey must hold either a rb_key or a cache_ent. */ 645 struct mlx5r_cache_rb_key rb_key; 646 struct mlx5_cache_ent *cache_ent; 647 }; 648 649 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 650 651 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 652 IB_ACCESS_REMOTE_WRITE |\ 653 IB_ACCESS_REMOTE_READ |\ 654 IB_ACCESS_REMOTE_ATOMIC |\ 655 IB_ZERO_BASED) 656 657 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 658 IB_ACCESS_REMOTE_WRITE |\ 659 IB_ACCESS_REMOTE_READ |\ 660 IB_ZERO_BASED) 661 662 #define mlx5_update_odp_stats(mr, counter_name, value) \ 663 atomic64_add(value, &((mr)->odp_stats.counter_name)) 664 665 struct mlx5_ib_mr { 666 struct ib_mr ibmr; 667 struct mlx5_ib_mkey mmkey; 668 669 struct ib_umem *umem; 670 671 union { 672 /* Used only by kernel MRs (umem == NULL) */ 673 struct { 674 void *descs; 675 void *descs_alloc; 676 dma_addr_t desc_map; 677 int max_descs; 678 int desc_size; 679 int access_mode; 680 681 /* For Kernel IB_MR_TYPE_INTEGRITY */ 682 struct mlx5_core_sig_ctx *sig; 683 struct mlx5_ib_mr *pi_mr; 684 struct mlx5_ib_mr *klm_mr; 685 struct mlx5_ib_mr *mtt_mr; 686 u64 data_iova; 687 u64 pi_iova; 688 int meta_ndescs; 689 int meta_length; 690 int data_length; 691 }; 692 693 /* Used only by User MRs (umem != NULL) */ 694 struct { 695 unsigned int page_shift; 696 /* Current access_flags */ 697 int access_flags; 698 699 /* For User ODP */ 700 struct mlx5_ib_mr *parent; 701 struct xarray implicit_children; 702 union { 703 struct work_struct work; 704 } odp_destroy; 705 struct ib_odp_counters odp_stats; 706 bool is_odp_implicit; 707 }; 708 }; 709 }; 710 711 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 712 { 713 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 714 mr->umem->is_odp; 715 } 716 717 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 718 { 719 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 720 mr->umem->is_dmabuf; 721 } 722 723 struct mlx5_ib_mw { 724 struct ib_mw ibmw; 725 struct mlx5_ib_mkey mmkey; 726 }; 727 728 struct mlx5_ib_umr_context { 729 struct ib_cqe cqe; 730 enum ib_wc_status status; 731 struct completion done; 732 }; 733 734 enum { 735 MLX5_UMR_STATE_UNINIT, 736 MLX5_UMR_STATE_ACTIVE, 737 MLX5_UMR_STATE_RECOVER, 738 MLX5_UMR_STATE_ERR, 739 }; 740 741 struct umr_common { 742 struct ib_pd *pd; 743 struct ib_cq *cq; 744 struct ib_qp *qp; 745 /* Protects from UMR QP overflow 746 */ 747 struct semaphore sem; 748 /* Protects from using UMR while the UMR is not active 749 */ 750 struct mutex lock; 751 unsigned int state; 752 }; 753 754 struct mlx5_cache_ent { 755 struct xarray mkeys; 756 unsigned long stored; 757 unsigned long reserved; 758 759 char name[4]; 760 761 struct rb_node node; 762 struct mlx5r_cache_rb_key rb_key; 763 764 u8 is_tmp:1; 765 u8 disabled:1; 766 u8 fill_to_high_water:1; 767 768 /* 769 * - limit is the low water mark for stored mkeys, 2* limit is the 770 * upper water mark. 771 */ 772 u32 in_use; 773 u32 limit; 774 775 /* Statistics */ 776 u32 miss; 777 778 struct mlx5_ib_dev *dev; 779 struct delayed_work dwork; 780 }; 781 782 struct mlx5r_async_create_mkey { 783 union { 784 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)]; 785 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 786 }; 787 struct mlx5_async_work cb_work; 788 struct mlx5_cache_ent *ent; 789 u32 mkey; 790 }; 791 792 struct mlx5_mkey_cache { 793 struct workqueue_struct *wq; 794 struct rb_root rb_root; 795 struct mutex rb_lock; 796 struct dentry *fs_root; 797 unsigned long last_add; 798 struct delayed_work remove_ent_dwork; 799 }; 800 801 struct mlx5_ib_port_resources { 802 struct mlx5_ib_gsi_qp *gsi; 803 struct work_struct pkey_change_work; 804 }; 805 806 struct mlx5_ib_resources { 807 struct ib_cq *c0; 808 u32 xrcdn0; 809 u32 xrcdn1; 810 struct ib_pd *p0; 811 struct ib_srq *s0; 812 struct ib_srq *s1; 813 struct mlx5_ib_port_resources ports[2]; 814 }; 815 816 #define MAX_OPFC_RULES 2 817 818 struct mlx5_ib_op_fc { 819 struct mlx5_fc *fc; 820 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 821 }; 822 823 struct mlx5_ib_counters { 824 struct rdma_stat_desc *descs; 825 size_t *offsets; 826 u32 num_q_counters; 827 u32 num_cong_counters; 828 u32 num_ext_ppcnt_counters; 829 u32 num_op_counters; 830 u16 set_id; 831 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 832 }; 833 834 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 835 struct mlx5_ib_op_fc *opfc, 836 enum mlx5_ib_optional_counter_type type); 837 838 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 839 struct mlx5_ib_op_fc *opfc, 840 enum mlx5_ib_optional_counter_type type); 841 842 struct mlx5_ib_multiport_info; 843 844 struct mlx5_ib_multiport { 845 struct mlx5_ib_multiport_info *mpi; 846 /* To be held when accessing the multiport info */ 847 spinlock_t mpi_lock; 848 }; 849 850 struct mlx5_roce { 851 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 852 * netdev pointer 853 */ 854 rwlock_t netdev_lock; 855 struct net_device *netdev; 856 struct notifier_block nb; 857 struct netdev_net_notifier nn; 858 struct notifier_block mdev_nb; 859 struct net_device *tracking_netdev; 860 atomic_t tx_port_affinity; 861 enum ib_port_state last_port_state; 862 struct mlx5_ib_dev *dev; 863 u32 native_port_num; 864 }; 865 866 struct mlx5_ib_port { 867 struct mlx5_ib_counters cnts; 868 struct mlx5_ib_multiport mp; 869 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 870 struct mlx5_roce roce; 871 struct mlx5_eswitch_rep *rep; 872 }; 873 874 struct mlx5_ib_dbg_param { 875 int offset; 876 struct mlx5_ib_dev *dev; 877 struct dentry *dentry; 878 u32 port_num; 879 }; 880 881 enum mlx5_ib_dbg_cc_types { 882 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 883 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 884 MLX5_IB_DBG_CC_RP_TIME_RESET, 885 MLX5_IB_DBG_CC_RP_BYTE_RESET, 886 MLX5_IB_DBG_CC_RP_THRESHOLD, 887 MLX5_IB_DBG_CC_RP_AI_RATE, 888 MLX5_IB_DBG_CC_RP_MAX_RATE, 889 MLX5_IB_DBG_CC_RP_HAI_RATE, 890 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 891 MLX5_IB_DBG_CC_RP_MIN_RATE, 892 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 893 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 894 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 895 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 896 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 897 MLX5_IB_DBG_CC_RP_GD, 898 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 899 MLX5_IB_DBG_CC_NP_CNP_DSCP, 900 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 901 MLX5_IB_DBG_CC_NP_CNP_PRIO, 902 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID, 903 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP, 904 MLX5_IB_DBG_CC_MAX, 905 }; 906 907 struct mlx5_ib_dbg_cc_params { 908 struct dentry *root; 909 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 910 }; 911 912 enum { 913 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 914 }; 915 916 struct mlx5_ib_delay_drop { 917 struct mlx5_ib_dev *dev; 918 struct work_struct delay_drop_work; 919 /* serialize setting of delay drop */ 920 struct mutex lock; 921 u32 timeout; 922 bool activate; 923 atomic_t events_cnt; 924 atomic_t rqs_cnt; 925 struct dentry *dir_debugfs; 926 }; 927 928 enum mlx5_ib_stages { 929 MLX5_IB_STAGE_INIT, 930 MLX5_IB_STAGE_FS, 931 MLX5_IB_STAGE_CAPS, 932 MLX5_IB_STAGE_NON_DEFAULT_CB, 933 MLX5_IB_STAGE_ROCE, 934 MLX5_IB_STAGE_QP, 935 MLX5_IB_STAGE_SRQ, 936 MLX5_IB_STAGE_DEVICE_RESOURCES, 937 MLX5_IB_STAGE_DEVICE_NOTIFIER, 938 MLX5_IB_STAGE_ODP, 939 MLX5_IB_STAGE_COUNTERS, 940 MLX5_IB_STAGE_CONG_DEBUGFS, 941 MLX5_IB_STAGE_UAR, 942 MLX5_IB_STAGE_BFREG, 943 MLX5_IB_STAGE_PRE_IB_REG_UMR, 944 MLX5_IB_STAGE_WHITELIST_UID, 945 MLX5_IB_STAGE_IB_REG, 946 MLX5_IB_STAGE_POST_IB_REG_UMR, 947 MLX5_IB_STAGE_DELAY_DROP, 948 MLX5_IB_STAGE_RESTRACK, 949 MLX5_IB_STAGE_MAX, 950 }; 951 952 struct mlx5_ib_stage { 953 int (*init)(struct mlx5_ib_dev *dev); 954 void (*cleanup)(struct mlx5_ib_dev *dev); 955 }; 956 957 #define STAGE_CREATE(_stage, _init, _cleanup) \ 958 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 959 960 struct mlx5_ib_profile { 961 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 962 }; 963 964 struct mlx5_ib_multiport_info { 965 struct list_head list; 966 struct mlx5_ib_dev *ibdev; 967 struct mlx5_core_dev *mdev; 968 struct notifier_block mdev_events; 969 struct completion unref_comp; 970 u64 sys_image_guid; 971 u32 mdev_refcnt; 972 bool is_master; 973 bool unaffiliate; 974 }; 975 976 struct mlx5_ib_flow_action { 977 struct ib_flow_action ib_action; 978 union { 979 struct { 980 u64 ib_flags; 981 struct mlx5_accel_esp_xfrm *ctx; 982 } esp_aes_gcm; 983 struct { 984 struct mlx5_ib_dev *dev; 985 u32 sub_type; 986 union { 987 struct mlx5_modify_hdr *modify_hdr; 988 struct mlx5_pkt_reformat *pkt_reformat; 989 }; 990 } flow_action_raw; 991 }; 992 }; 993 994 struct mlx5_dm { 995 struct mlx5_core_dev *dev; 996 /* This lock is used to protect the access to the shared 997 * allocation map when concurrent requests by different 998 * processes are handled. 999 */ 1000 spinlock_t lock; 1001 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 1002 }; 1003 1004 struct mlx5_read_counters_attr { 1005 struct mlx5_fc *hw_cntrs_hndl; 1006 u64 *out; 1007 u32 flags; 1008 }; 1009 1010 enum mlx5_ib_counters_type { 1011 MLX5_IB_COUNTERS_FLOW, 1012 }; 1013 1014 struct mlx5_ib_mcounters { 1015 struct ib_counters ibcntrs; 1016 enum mlx5_ib_counters_type type; 1017 /* number of counters supported for this counters type */ 1018 u32 counters_num; 1019 struct mlx5_fc *hw_cntrs_hndl; 1020 /* read function for this counters type */ 1021 int (*read_counters)(struct ib_device *ibdev, 1022 struct mlx5_read_counters_attr *read_attr); 1023 /* max index set as part of create_flow */ 1024 u32 cntrs_max_index; 1025 /* number of counters data entries (<description,index> pair) */ 1026 u32 ncounters; 1027 /* counters data array for descriptions and indexes */ 1028 struct mlx5_ib_flow_counters_desc *counters_data; 1029 /* protects access to mcounters internal data */ 1030 struct mutex mcntrs_mutex; 1031 }; 1032 1033 static inline struct mlx5_ib_mcounters * 1034 to_mcounters(struct ib_counters *ibcntrs) 1035 { 1036 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1037 } 1038 1039 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1040 bool is_egress, 1041 struct mlx5_flow_act *action); 1042 struct mlx5_ib_lb_state { 1043 /* protect the user_td */ 1044 struct mutex mutex; 1045 u32 user_td; 1046 int qps; 1047 bool enabled; 1048 }; 1049 1050 struct mlx5_ib_pf_eq { 1051 struct notifier_block irq_nb; 1052 struct mlx5_ib_dev *dev; 1053 struct mlx5_eq *core; 1054 struct work_struct work; 1055 spinlock_t lock; /* Pagefaults spinlock */ 1056 struct workqueue_struct *wq; 1057 mempool_t *pool; 1058 }; 1059 1060 struct mlx5_devx_event_table { 1061 struct mlx5_nb devx_nb; 1062 /* serialize updating the event_xa */ 1063 struct mutex event_xa_lock; 1064 struct xarray event_xa; 1065 }; 1066 1067 struct mlx5_var_table { 1068 /* serialize updating the bitmap */ 1069 struct mutex bitmap_lock; 1070 unsigned long *bitmap; 1071 u64 hw_start_addr; 1072 u32 stride_size; 1073 u64 num_var_hw_entries; 1074 }; 1075 1076 struct mlx5_port_caps { 1077 bool has_smi; 1078 u8 ext_port_cap; 1079 }; 1080 1081 1082 struct mlx5_special_mkeys { 1083 u32 dump_fill_mkey; 1084 __be32 null_mkey; 1085 __be32 terminate_scatter_list_mkey; 1086 }; 1087 1088 struct mlx5_ib_dev { 1089 struct ib_device ib_dev; 1090 struct mlx5_core_dev *mdev; 1091 struct notifier_block mdev_events; 1092 int num_ports; 1093 /* serialize update of capability mask 1094 */ 1095 struct mutex cap_mask_mutex; 1096 u8 ib_active:1; 1097 u8 is_rep:1; 1098 u8 lag_active:1; 1099 u8 wc_support:1; 1100 u8 fill_delay; 1101 struct umr_common umrc; 1102 /* sync used page count stats 1103 */ 1104 struct mlx5_ib_resources devr; 1105 1106 atomic_t mkey_var; 1107 struct mlx5_mkey_cache cache; 1108 struct timer_list delay_timer; 1109 /* Prevents soft lock on massive reg MRs */ 1110 struct mutex slow_path_mutex; 1111 struct ib_odp_caps odp_caps; 1112 u64 odp_max_size; 1113 struct mutex odp_eq_mutex; 1114 struct mlx5_ib_pf_eq odp_pf_eq; 1115 1116 struct xarray odp_mkeys; 1117 1118 struct mlx5_ib_flow_db *flow_db; 1119 /* protect resources needed as part of reset flow */ 1120 spinlock_t reset_flow_resource_lock; 1121 struct list_head qp_list; 1122 /* Array with num_ports elements */ 1123 struct mlx5_ib_port *port; 1124 struct mlx5_sq_bfreg bfreg; 1125 struct mlx5_sq_bfreg wc_bfreg; 1126 struct mlx5_sq_bfreg fp_bfreg; 1127 struct mlx5_ib_delay_drop delay_drop; 1128 const struct mlx5_ib_profile *profile; 1129 1130 struct mlx5_ib_lb_state lb; 1131 u8 umr_fence; 1132 struct list_head ib_dev_list; 1133 u64 sys_image_guid; 1134 struct mlx5_dm dm; 1135 u16 devx_whitelist_uid; 1136 struct mlx5_srq_table srq_table; 1137 struct mlx5_qp_table qp_table; 1138 struct mlx5_async_ctx async_ctx; 1139 struct mlx5_devx_event_table devx_event_table; 1140 struct mlx5_var_table var_table; 1141 1142 struct xarray sig_mrs; 1143 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1144 u16 pkey_table_len; 1145 u8 lag_ports; 1146 struct mlx5_special_mkeys mkeys; 1147 }; 1148 1149 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1150 { 1151 return container_of(mcq, struct mlx5_ib_cq, mcq); 1152 } 1153 1154 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1155 { 1156 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1157 } 1158 1159 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1160 { 1161 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1162 } 1163 1164 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1165 { 1166 return to_mdev(mr->ibmr.device); 1167 } 1168 1169 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1170 { 1171 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1172 udata, struct mlx5_ib_ucontext, ibucontext); 1173 1174 return to_mdev(context->ibucontext.device); 1175 } 1176 1177 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1178 { 1179 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1180 } 1181 1182 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1183 { 1184 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1185 } 1186 1187 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1188 { 1189 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1190 } 1191 1192 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1193 { 1194 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1195 } 1196 1197 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1198 { 1199 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1200 } 1201 1202 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1203 { 1204 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1205 } 1206 1207 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1208 { 1209 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1210 } 1211 1212 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1213 { 1214 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1215 } 1216 1217 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1218 { 1219 return container_of(msrq, struct mlx5_ib_srq, msrq); 1220 } 1221 1222 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1223 { 1224 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1225 } 1226 1227 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1228 { 1229 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1230 } 1231 1232 static inline struct mlx5_ib_flow_action * 1233 to_mflow_act(struct ib_flow_action *ibact) 1234 { 1235 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1236 } 1237 1238 static inline struct mlx5_user_mmap_entry * 1239 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1240 { 1241 return container_of(rdma_entry, 1242 struct mlx5_user_mmap_entry, rdma_entry); 1243 } 1244 1245 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1246 struct mlx5_db *db); 1247 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1248 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1249 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1250 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1251 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1252 struct ib_udata *udata); 1253 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1254 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1255 { 1256 return 0; 1257 } 1258 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1259 struct ib_udata *udata); 1260 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1261 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1262 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1263 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1264 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1265 const struct ib_recv_wr **bad_wr); 1266 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1267 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1268 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1269 struct ib_udata *udata); 1270 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1271 int attr_mask, struct ib_udata *udata); 1272 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1273 struct ib_qp_init_attr *qp_init_attr); 1274 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1275 void mlx5_ib_drain_sq(struct ib_qp *qp); 1276 void mlx5_ib_drain_rq(struct ib_qp *qp); 1277 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1278 size_t buflen, size_t *bc); 1279 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1280 size_t buflen, size_t *bc); 1281 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1282 size_t buflen, size_t *bc); 1283 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1284 struct ib_udata *udata); 1285 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1286 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1287 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1288 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1289 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1290 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1291 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1292 u64 virt_addr, int access_flags, 1293 struct ib_udata *udata); 1294 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1295 u64 length, u64 virt_addr, 1296 int fd, int access_flags, 1297 struct ib_udata *udata); 1298 int mlx5_ib_advise_mr(struct ib_pd *pd, 1299 enum ib_uverbs_advise_mr_advice advice, 1300 u32 flags, 1301 struct ib_sge *sg_list, 1302 u32 num_sge, 1303 struct uverbs_attr_bundle *attrs); 1304 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1305 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1306 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1307 int access_flags); 1308 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1309 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1310 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1311 u64 length, u64 virt_addr, int access_flags, 1312 struct ib_pd *pd, struct ib_udata *udata); 1313 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1314 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1315 u32 max_num_sg); 1316 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1317 u32 max_num_sg, 1318 u32 max_num_meta_sg); 1319 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1320 unsigned int *sg_offset); 1321 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1322 int data_sg_nents, unsigned int *data_sg_offset, 1323 struct scatterlist *meta_sg, int meta_sg_nents, 1324 unsigned int *meta_sg_offset); 1325 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1326 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1327 const struct ib_mad *in, struct ib_mad *out, 1328 size_t *out_mad_size, u16 *out_mad_pkey_index); 1329 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1330 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1331 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1332 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1333 __be64 *sys_image_guid); 1334 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1335 u16 *max_pkeys); 1336 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1337 u32 *vendor_id); 1338 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1339 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1340 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1341 u16 *pkey); 1342 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1343 union ib_gid *gid); 1344 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1345 struct ib_port_attr *props); 1346 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1347 struct ib_port_attr *props); 1348 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1349 u64 access_flags); 1350 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1351 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1352 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev); 1353 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev); 1354 struct mlx5_cache_ent * 1355 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev, 1356 struct mlx5r_cache_rb_key rb_key, 1357 bool persistent_entry); 1358 1359 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1360 int access_flags, int access_mode, 1361 int ndescs); 1362 1363 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1364 struct ib_mr_status *mr_status); 1365 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1366 struct ib_wq_init_attr *init_attr, 1367 struct ib_udata *udata); 1368 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1369 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1370 u32 wq_attr_mask, struct ib_udata *udata); 1371 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1372 struct ib_rwq_ind_table_init_attr *init_attr, 1373 struct ib_udata *udata); 1374 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1375 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1376 struct ib_dm_mr_attr *attr, 1377 struct uverbs_attr_bundle *attrs); 1378 1379 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1380 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1381 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1382 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1383 int __init mlx5_ib_odp_init(void); 1384 void mlx5_ib_odp_cleanup(void); 1385 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev); 1386 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1387 struct mlx5_ib_mr *mr, int flags); 1388 1389 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1390 enum ib_uverbs_advise_mr_advice advice, 1391 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1392 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1393 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1394 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1395 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1396 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1397 struct mlx5_ib_pf_eq *eq) 1398 { 1399 return 0; 1400 } 1401 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1402 static inline int mlx5_ib_odp_init(void) { return 0; } 1403 static inline void mlx5_ib_odp_cleanup(void) {} 1404 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev) 1405 { 1406 return 0; 1407 } 1408 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1409 struct mlx5_ib_mr *mr, int flags) {} 1410 1411 static inline int 1412 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1413 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1414 struct ib_sge *sg_list, u32 num_sge) 1415 { 1416 return -EOPNOTSUPP; 1417 } 1418 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1419 { 1420 return -EOPNOTSUPP; 1421 } 1422 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1423 { 1424 return -EOPNOTSUPP; 1425 } 1426 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1427 1428 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1429 1430 /* Needed for rep profile */ 1431 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1432 const struct mlx5_ib_profile *profile, 1433 int stage); 1434 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1435 const struct mlx5_ib_profile *profile); 1436 1437 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1438 u32 port, struct ifla_vf_info *info); 1439 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1440 u32 port, int state); 1441 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1442 u32 port, struct ifla_vf_stats *stats); 1443 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1444 struct ifla_vf_guid *node_guid, 1445 struct ifla_vf_guid *port_guid); 1446 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1447 u64 guid, int type); 1448 1449 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1450 const struct ib_gid_attr *attr); 1451 1452 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1453 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1454 1455 /* GSI QP helper functions */ 1456 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1457 struct ib_qp_init_attr *attr); 1458 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1459 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1460 int attr_mask); 1461 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1462 int qp_attr_mask, 1463 struct ib_qp_init_attr *qp_init_attr); 1464 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1465 const struct ib_send_wr **bad_wr); 1466 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1467 const struct ib_recv_wr **bad_wr); 1468 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1469 1470 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1471 1472 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1473 int bfregn); 1474 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1475 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1476 u32 ib_port_num, 1477 u32 *native_port_num); 1478 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1479 u32 port_num); 1480 1481 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1482 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1483 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1484 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1485 1486 static inline int is_qp1(enum ib_qp_type qp_type) 1487 { 1488 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1489 } 1490 1491 static inline u32 check_cq_create_flags(u32 flags) 1492 { 1493 /* 1494 * It returns non-zero value for unsupported CQ 1495 * create flags, otherwise it returns zero. 1496 */ 1497 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1498 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1499 } 1500 1501 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1502 u32 *user_index) 1503 { 1504 if (cqe_version) { 1505 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1506 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1507 return -EINVAL; 1508 *user_index = cmd_uidx; 1509 } else { 1510 *user_index = MLX5_IB_DEFAULT_UIDX; 1511 } 1512 1513 return 0; 1514 } 1515 1516 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1517 struct mlx5_ib_create_qp *ucmd, 1518 int inlen, 1519 u32 *user_index) 1520 { 1521 u8 cqe_version = ucontext->cqe_version; 1522 1523 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1524 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1525 return 0; 1526 1527 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1528 return -EINVAL; 1529 1530 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1531 } 1532 1533 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1534 struct mlx5_ib_create_srq *ucmd, 1535 int inlen, 1536 u32 *user_index) 1537 { 1538 u8 cqe_version = ucontext->cqe_version; 1539 1540 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1541 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1542 return 0; 1543 1544 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1545 return -EINVAL; 1546 1547 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1548 } 1549 1550 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1551 { 1552 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1553 MLX5_UARS_IN_PAGE : 1; 1554 } 1555 1556 extern void *xlt_emergency_page; 1557 1558 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1559 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1560 bool dyn_bfreg); 1561 1562 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1563 struct mlx5_ib_mkey *mmkey) 1564 { 1565 refcount_set(&mmkey->usecount, 1); 1566 1567 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1568 mmkey, GFP_KERNEL)); 1569 } 1570 1571 /* deref an mkey that can participate in ODP flow */ 1572 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1573 { 1574 if (refcount_dec_and_test(&mmkey->usecount)) 1575 wake_up(&mmkey->wait); 1576 } 1577 1578 /* deref an mkey that can participate in ODP flow and wait for relese */ 1579 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1580 { 1581 mlx5r_deref_odp_mkey(mmkey); 1582 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1583 } 1584 1585 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1586 1587 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1588 { 1589 /* 1590 * If the driver is in hash mode and the port_select_flow_table_bypass cap 1591 * is supported, it means that the driver no longer needs to assign the port 1592 * affinity by default. If a user wants to set the port affinity explicitly, 1593 * the user has a dedicated API to do that, so there is no need to assign 1594 * the port affinity by default. 1595 */ 1596 if (dev->lag_active && 1597 mlx5_lag_mode_is_hash(dev->mdev) && 1598 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass)) 1599 return 0; 1600 1601 if (mlx5_lag_is_lacp_owner(dev->mdev) && !dev->lag_active) 1602 return 0; 1603 1604 return dev->lag_active || 1605 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1606 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1607 } 1608 1609 static inline bool rt_supported(int ts_cap) 1610 { 1611 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1612 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1613 } 1614 1615 /* 1616 * PCI Peer to Peer is a trainwreck. If no switch is present then things 1617 * sometimes work, depending on the pci_distance_p2p logic for excluding broken 1618 * root complexes. However if a switch is present in the path, then things get 1619 * really ugly depending on how the switch is setup. This table assumes that the 1620 * root complex is strict and is validating that all req/reps are matches 1621 * perfectly - so any scenario where it sees only half the transaction is a 1622 * failure. 1623 * 1624 * CR/RR/DT ATS RO P2P 1625 * 00X X X OK 1626 * 010 X X fails (request is routed to root but root never sees comp) 1627 * 011 0 X fails (request is routed to root but root never sees comp) 1628 * 011 1 X OK 1629 * 10X X 1 OK 1630 * 101 X 0 fails (completion is routed to root but root didn't see req) 1631 * 110 X 0 SLOW 1632 * 111 0 0 SLOW 1633 * 111 1 0 fails (completion is routed to root but root didn't see req) 1634 * 111 1 1 OK 1635 * 1636 * Unfortunately we cannot reliably know if a switch is present or what the 1637 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that 1638 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. 1639 * 1640 * For now assume if the umem is a dma_buf then it is P2P. 1641 */ 1642 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, 1643 struct ib_umem *umem, int access_flags) 1644 { 1645 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) 1646 return false; 1647 return access_flags & IB_ACCESS_RELAXED_ORDERING; 1648 } 1649 1650 #endif /* MLX5_IB_H */ 1651