1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 46 #define mlx5_ib_dbg(dev, format, arg...) \ 47 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 48 __LINE__, current->pid, ##arg) 49 50 #define mlx5_ib_err(dev, format, arg...) \ 51 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 52 __LINE__, current->pid, ##arg) 53 54 #define mlx5_ib_warn(dev, format, arg...) \ 55 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 56 __LINE__, current->pid, ##arg) 57 58 enum { 59 MLX5_IB_MMAP_CMD_SHIFT = 8, 60 MLX5_IB_MMAP_CMD_MASK = 0xff, 61 }; 62 63 enum mlx5_ib_mmap_cmd { 64 MLX5_IB_MMAP_REGULAR_PAGE = 0, 65 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, /* always last */ 66 }; 67 68 enum { 69 MLX5_RES_SCAT_DATA32_CQE = 0x1, 70 MLX5_RES_SCAT_DATA64_CQE = 0x2, 71 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 72 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 73 }; 74 75 enum mlx5_ib_latency_class { 76 MLX5_IB_LATENCY_CLASS_LOW, 77 MLX5_IB_LATENCY_CLASS_MEDIUM, 78 MLX5_IB_LATENCY_CLASS_HIGH, 79 MLX5_IB_LATENCY_CLASS_FAST_PATH 80 }; 81 82 enum mlx5_ib_mad_ifc_flags { 83 MLX5_MAD_IFC_IGNORE_MKEY = 1, 84 MLX5_MAD_IFC_IGNORE_BKEY = 2, 85 MLX5_MAD_IFC_NET_VIEW = 4, 86 }; 87 88 struct mlx5_ib_ucontext { 89 struct ib_ucontext ibucontext; 90 struct list_head db_page_list; 91 92 /* protect doorbell record alloc/free 93 */ 94 struct mutex db_page_mutex; 95 struct mlx5_uuar_info uuari; 96 }; 97 98 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 99 { 100 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 101 } 102 103 struct mlx5_ib_pd { 104 struct ib_pd ibpd; 105 u32 pdn; 106 }; 107 108 /* Use macros here so that don't have to duplicate 109 * enum ib_send_flags and enum ib_qp_type for low-level driver 110 */ 111 112 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 113 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 114 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 115 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 116 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 117 118 struct wr_list { 119 u16 opcode; 120 u16 next; 121 }; 122 123 struct mlx5_ib_wq { 124 u64 *wrid; 125 u32 *wr_data; 126 struct wr_list *w_list; 127 unsigned *wqe_head; 128 u16 unsig_count; 129 130 /* serialize post to the work queue 131 */ 132 spinlock_t lock; 133 int wqe_cnt; 134 int max_post; 135 int max_gs; 136 int offset; 137 int wqe_shift; 138 unsigned head; 139 unsigned tail; 140 u16 cur_post; 141 u16 last_poll; 142 void *qend; 143 }; 144 145 enum { 146 MLX5_QP_USER, 147 MLX5_QP_KERNEL, 148 MLX5_QP_EMPTY 149 }; 150 151 /* 152 * Connect-IB can trigger up to four concurrent pagefaults 153 * per-QP. 154 */ 155 enum mlx5_ib_pagefault_context { 156 MLX5_IB_PAGEFAULT_RESPONDER_READ, 157 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 158 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 159 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 160 MLX5_IB_PAGEFAULT_CONTEXTS 161 }; 162 163 static inline enum mlx5_ib_pagefault_context 164 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 165 { 166 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 167 } 168 169 struct mlx5_ib_pfault { 170 struct work_struct work; 171 struct mlx5_pagefault mpfault; 172 }; 173 174 struct mlx5_ib_qp { 175 struct ib_qp ibqp; 176 struct mlx5_core_qp mqp; 177 struct mlx5_buf buf; 178 179 struct mlx5_db db; 180 struct mlx5_ib_wq rq; 181 182 u32 doorbell_qpn; 183 u8 sq_signal_bits; 184 u8 fm_cache; 185 int sq_max_wqes_per_wr; 186 int sq_spare_wqes; 187 struct mlx5_ib_wq sq; 188 189 struct ib_umem *umem; 190 int buf_size; 191 192 /* serialize qp state modifications 193 */ 194 struct mutex mutex; 195 u16 xrcdn; 196 u32 flags; 197 u8 port; 198 u8 alt_port; 199 u8 atomic_rd_en; 200 u8 resp_depth; 201 u8 state; 202 int mlx_type; 203 int wq_sig; 204 int scat_cqe; 205 int max_inline_data; 206 struct mlx5_bf *bf; 207 int has_rq; 208 209 /* only for user space QPs. For kernel 210 * we have it from the bf object 211 */ 212 int uuarn; 213 214 int create_type; 215 216 /* Store signature errors */ 217 bool signature_en; 218 219 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 220 /* 221 * A flag that is true for QP's that are in a state that doesn't 222 * allow page faults, and shouldn't schedule any more faults. 223 */ 224 int disable_page_faults; 225 /* 226 * The disable_page_faults_lock protects a QP's disable_page_faults 227 * field, allowing for a thread to atomically check whether the QP 228 * allows page faults, and if so schedule a page fault. 229 */ 230 spinlock_t disable_page_faults_lock; 231 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 232 #endif 233 }; 234 235 struct mlx5_ib_cq_buf { 236 struct mlx5_buf buf; 237 struct ib_umem *umem; 238 int cqe_size; 239 int nent; 240 }; 241 242 enum mlx5_ib_qp_flags { 243 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0, 244 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1, 245 }; 246 247 struct mlx5_umr_wr { 248 union { 249 u64 virt_addr; 250 u64 offset; 251 } target; 252 struct ib_pd *pd; 253 unsigned int page_shift; 254 unsigned int npages; 255 u32 length; 256 int access_flags; 257 u32 mkey; 258 }; 259 260 struct mlx5_shared_mr_info { 261 int mr_id; 262 struct ib_umem *umem; 263 }; 264 265 struct mlx5_ib_cq { 266 struct ib_cq ibcq; 267 struct mlx5_core_cq mcq; 268 struct mlx5_ib_cq_buf buf; 269 struct mlx5_db db; 270 271 /* serialize access to the CQ 272 */ 273 spinlock_t lock; 274 275 /* protect resize cq 276 */ 277 struct mutex resize_mutex; 278 struct mlx5_ib_cq_buf *resize_buf; 279 struct ib_umem *resize_umem; 280 int cqe_size; 281 }; 282 283 struct mlx5_ib_srq { 284 struct ib_srq ibsrq; 285 struct mlx5_core_srq msrq; 286 struct mlx5_buf buf; 287 struct mlx5_db db; 288 u64 *wrid; 289 /* protect SRQ hanlding 290 */ 291 spinlock_t lock; 292 int head; 293 int tail; 294 u16 wqe_ctr; 295 struct ib_umem *umem; 296 /* serialize arming a SRQ 297 */ 298 struct mutex mutex; 299 int wq_sig; 300 }; 301 302 struct mlx5_ib_xrcd { 303 struct ib_xrcd ibxrcd; 304 u32 xrcdn; 305 }; 306 307 enum mlx5_ib_mtt_access_flags { 308 MLX5_IB_MTT_READ = (1 << 0), 309 MLX5_IB_MTT_WRITE = (1 << 1), 310 }; 311 312 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 313 314 struct mlx5_ib_mr { 315 struct ib_mr ibmr; 316 struct mlx5_core_mr mmr; 317 struct ib_umem *umem; 318 struct mlx5_shared_mr_info *smr_info; 319 struct list_head list; 320 int order; 321 int umred; 322 int npages; 323 struct mlx5_ib_dev *dev; 324 struct mlx5_create_mkey_mbox_out out; 325 struct mlx5_core_sig_ctx *sig; 326 int live; 327 }; 328 329 struct mlx5_ib_fast_reg_page_list { 330 struct ib_fast_reg_page_list ibfrpl; 331 __be64 *mapped_page_list; 332 dma_addr_t map; 333 }; 334 335 struct mlx5_ib_umr_context { 336 enum ib_wc_status status; 337 struct completion done; 338 }; 339 340 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) 341 { 342 context->status = -1; 343 init_completion(&context->done); 344 } 345 346 struct umr_common { 347 struct ib_pd *pd; 348 struct ib_cq *cq; 349 struct ib_qp *qp; 350 /* control access to UMR QP 351 */ 352 struct semaphore sem; 353 }; 354 355 enum { 356 MLX5_FMR_INVALID, 357 MLX5_FMR_VALID, 358 MLX5_FMR_BUSY, 359 }; 360 361 struct mlx5_ib_fmr { 362 struct ib_fmr ibfmr; 363 struct mlx5_core_mr mr; 364 int access_flags; 365 int state; 366 /* protect fmr state 367 */ 368 spinlock_t lock; 369 u64 wrid; 370 struct ib_send_wr wr[2]; 371 u8 page_shift; 372 struct ib_fast_reg_page_list page_list; 373 }; 374 375 struct mlx5_cache_ent { 376 struct list_head head; 377 /* sync access to the cahce entry 378 */ 379 spinlock_t lock; 380 381 382 struct dentry *dir; 383 char name[4]; 384 u32 order; 385 u32 size; 386 u32 cur; 387 u32 miss; 388 u32 limit; 389 390 struct dentry *fsize; 391 struct dentry *fcur; 392 struct dentry *fmiss; 393 struct dentry *flimit; 394 395 struct mlx5_ib_dev *dev; 396 struct work_struct work; 397 struct delayed_work dwork; 398 int pending; 399 }; 400 401 struct mlx5_mr_cache { 402 struct workqueue_struct *wq; 403 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 404 int stopped; 405 struct dentry *root; 406 unsigned long last_add; 407 }; 408 409 struct mlx5_ib_resources { 410 struct ib_cq *c0; 411 struct ib_xrcd *x0; 412 struct ib_xrcd *x1; 413 struct ib_pd *p0; 414 struct ib_srq *s0; 415 struct ib_srq *s1; 416 }; 417 418 struct mlx5_ib_dev { 419 struct ib_device ib_dev; 420 struct mlx5_core_dev *mdev; 421 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 422 int num_ports; 423 /* serialize update of capability mask 424 */ 425 struct mutex cap_mask_mutex; 426 bool ib_active; 427 struct umr_common umrc; 428 /* sync used page count stats 429 */ 430 struct mlx5_ib_resources devr; 431 struct mlx5_mr_cache cache; 432 struct timer_list delay_timer; 433 int fill_delay; 434 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 435 struct ib_odp_caps odp_caps; 436 /* 437 * Sleepable RCU that prevents destruction of MRs while they are still 438 * being used by a page fault handler. 439 */ 440 struct srcu_struct mr_srcu; 441 #endif 442 }; 443 444 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 445 { 446 return container_of(mcq, struct mlx5_ib_cq, mcq); 447 } 448 449 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 450 { 451 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 452 } 453 454 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 455 { 456 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 457 } 458 459 static inline struct mlx5_ib_fmr *to_mfmr(struct ib_fmr *ibfmr) 460 { 461 return container_of(ibfmr, struct mlx5_ib_fmr, ibfmr); 462 } 463 464 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 465 { 466 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 467 } 468 469 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 470 { 471 return container_of(mqp, struct mlx5_ib_qp, mqp); 472 } 473 474 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr) 475 { 476 return container_of(mmr, struct mlx5_ib_mr, mmr); 477 } 478 479 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 480 { 481 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 482 } 483 484 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 485 { 486 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 487 } 488 489 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 490 { 491 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 492 } 493 494 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 495 { 496 return container_of(msrq, struct mlx5_ib_srq, msrq); 497 } 498 499 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 500 { 501 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 502 } 503 504 static inline struct mlx5_ib_fast_reg_page_list *to_mfrpl(struct ib_fast_reg_page_list *ibfrpl) 505 { 506 return container_of(ibfrpl, struct mlx5_ib_fast_reg_page_list, ibfrpl); 507 } 508 509 struct mlx5_ib_ah { 510 struct ib_ah ibah; 511 struct mlx5_av av; 512 }; 513 514 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 515 { 516 return container_of(ibah, struct mlx5_ib_ah, ibah); 517 } 518 519 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 520 struct mlx5_db *db); 521 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 522 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 523 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 524 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 525 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 526 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 527 const void *in_mad, void *response_mad); 528 struct ib_ah *create_ib_ah(struct ib_ah_attr *ah_attr, 529 struct mlx5_ib_ah *ah); 530 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 531 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 532 int mlx5_ib_destroy_ah(struct ib_ah *ah); 533 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 534 struct ib_srq_init_attr *init_attr, 535 struct ib_udata *udata); 536 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 537 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 538 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 539 int mlx5_ib_destroy_srq(struct ib_srq *srq); 540 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 541 struct ib_recv_wr **bad_wr); 542 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 543 struct ib_qp_init_attr *init_attr, 544 struct ib_udata *udata); 545 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 546 int attr_mask, struct ib_udata *udata); 547 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 548 struct ib_qp_init_attr *qp_init_attr); 549 int mlx5_ib_destroy_qp(struct ib_qp *qp); 550 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 551 struct ib_send_wr **bad_wr); 552 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 553 struct ib_recv_wr **bad_wr); 554 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 555 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 556 void *buffer, u32 length); 557 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 558 const struct ib_cq_init_attr *attr, 559 struct ib_ucontext *context, 560 struct ib_udata *udata); 561 int mlx5_ib_destroy_cq(struct ib_cq *cq); 562 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 563 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 564 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 565 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 566 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 567 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 568 u64 virt_addr, int access_flags, 569 struct ib_udata *udata); 570 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 571 int npages, int zap); 572 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 573 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 574 enum ib_mr_type mr_type, 575 u32 max_num_sg); 576 struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev, 577 int page_list_len); 578 void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list); 579 struct ib_fmr *mlx5_ib_fmr_alloc(struct ib_pd *pd, int acc, 580 struct ib_fmr_attr *fmr_attr); 581 int mlx5_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 582 int npages, u64 iova); 583 int mlx5_ib_unmap_fmr(struct list_head *fmr_list); 584 int mlx5_ib_fmr_dealloc(struct ib_fmr *ibfmr); 585 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 586 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 587 const struct ib_mad_hdr *in, size_t in_mad_size, 588 struct ib_mad_hdr *out, size_t *out_mad_size, 589 u16 *out_mad_pkey_index); 590 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 591 struct ib_ucontext *context, 592 struct ib_udata *udata); 593 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 594 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 595 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 596 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 597 struct ib_smp *out_mad); 598 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 599 __be64 *sys_image_guid); 600 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 601 u16 *max_pkeys); 602 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 603 u32 *vendor_id); 604 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 605 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 606 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 607 u16 *pkey); 608 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 609 union ib_gid *gid); 610 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 611 struct ib_port_attr *props); 612 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 613 struct ib_port_attr *props); 614 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 615 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 616 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 617 int *ncont, int *order); 618 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 619 int page_shift, size_t offset, size_t num_pages, 620 __be64 *pas, int access_flags); 621 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 622 int page_shift, __be64 *pas, int access_flags); 623 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 624 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 625 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 626 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 627 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 628 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context); 629 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 630 struct ib_mr_status *mr_status); 631 632 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 633 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 634 635 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 636 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 637 struct mlx5_ib_pfault *pfault); 638 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 639 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 640 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 641 int __init mlx5_ib_odp_init(void); 642 void mlx5_ib_odp_cleanup(void); 643 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 644 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 645 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 646 unsigned long end); 647 648 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 649 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 650 { 651 return; 652 } 653 654 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 655 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 656 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 657 static inline int mlx5_ib_odp_init(void) { return 0; } 658 static inline void mlx5_ib_odp_cleanup(void) {} 659 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 660 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 661 662 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 663 664 static inline void init_query_mad(struct ib_smp *mad) 665 { 666 mad->base_version = 1; 667 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 668 mad->class_version = 1; 669 mad->method = IB_MGMT_METHOD_GET; 670 } 671 672 static inline u8 convert_access(int acc) 673 { 674 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 675 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 676 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 677 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 678 MLX5_PERM_LOCAL_READ; 679 } 680 681 static inline int is_qp1(enum ib_qp_type qp_type) 682 { 683 return qp_type == IB_QPT_GSI; 684 } 685 686 #define MLX5_MAX_UMR_SHIFT 16 687 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 688 689 #endif /* MLX5_IB_H */ 690