1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 29 #define mlx5_ib_dbg(_dev, format, arg...) \ 30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 31 __LINE__, current->pid, ##arg) 32 33 #define mlx5_ib_err(_dev, format, arg...) \ 34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 35 __LINE__, current->pid, ##arg) 36 37 #define mlx5_ib_warn(_dev, format, arg...) \ 38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 39 __LINE__, current->pid, ##arg) 40 41 #define MLX5_IB_DEFAULT_UIDX 0xffffff 42 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 43 44 static __always_inline unsigned long 45 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 46 unsigned int pgsz_shift) 47 { 48 unsigned int largest_pg_shift = 49 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 50 BITS_PER_LONG - 1); 51 52 /* 53 * Despite a command allowing it, the device does not support lower than 54 * 4k page size. 55 */ 56 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 57 return GENMASK(largest_pg_shift, pgsz_shift); 58 } 59 60 /* 61 * For mkc users, instead of a page_offset the command has a start_iova which 62 * specifies both the page_offset and the on-the-wire IOVA 63 */ 64 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \ 65 ib_umem_find_best_pgsz(umem, \ 66 __mlx5_log_page_size_to_bitmap( \ 67 __mlx5_bit_sz(typ, log_pgsz_fld), \ 68 pgsz_shift), \ 69 iova) 70 71 static __always_inline unsigned long 72 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 73 unsigned int offset_shift) 74 { 75 unsigned int largest_offset_shift = 76 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 77 BITS_PER_LONG - 1); 78 79 return GENMASK(largest_offset_shift, offset_shift); 80 } 81 82 /* 83 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 84 * page_offset_quantized * (page_size/scale) = page_offset 85 * Which restricts allowed page sizes to ones that satisify the above. 86 */ 87 unsigned long __mlx5_umem_find_best_quantized_pgoff( 88 struct ib_umem *umem, unsigned long pgsz_bitmap, 89 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 90 unsigned int *page_offset_quantized); 91 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 92 pgsz_shift, page_offset_fld, \ 93 scale, page_offset_quantized) \ 94 __mlx5_umem_find_best_quantized_pgoff( \ 95 umem, \ 96 __mlx5_log_page_size_to_bitmap( \ 97 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 98 __mlx5_bit_sz(typ, page_offset_fld), \ 99 GENMASK(31, order_base_2(scale)), scale, \ 100 page_offset_quantized) 101 102 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 103 pgsz_shift, page_offset_fld, \ 104 scale, page_offset_quantized) \ 105 __mlx5_umem_find_best_quantized_pgoff( \ 106 umem, \ 107 __mlx5_log_page_size_to_bitmap( \ 108 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 109 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 110 page_offset_quantized) 111 112 enum { 113 MLX5_IB_MMAP_OFFSET_START = 9, 114 MLX5_IB_MMAP_OFFSET_END = 255, 115 }; 116 117 enum { 118 MLX5_IB_MMAP_CMD_SHIFT = 8, 119 MLX5_IB_MMAP_CMD_MASK = 0xff, 120 }; 121 122 enum { 123 MLX5_RES_SCAT_DATA32_CQE = 0x1, 124 MLX5_RES_SCAT_DATA64_CQE = 0x2, 125 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 126 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 127 }; 128 129 enum mlx5_ib_mad_ifc_flags { 130 MLX5_MAD_IFC_IGNORE_MKEY = 1, 131 MLX5_MAD_IFC_IGNORE_BKEY = 2, 132 MLX5_MAD_IFC_NET_VIEW = 4, 133 }; 134 135 enum { 136 MLX5_CROSS_CHANNEL_BFREG = 0, 137 }; 138 139 enum { 140 MLX5_CQE_VERSION_V0, 141 MLX5_CQE_VERSION_V1, 142 }; 143 144 enum { 145 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 146 MLX5_TM_MAX_SGE = 1, 147 }; 148 149 enum { 150 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 151 MLX5_IB_INVALID_BFREG = BIT(31), 152 }; 153 154 enum { 155 MLX5_MAX_MEMIC_PAGES = 0x100, 156 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 157 }; 158 159 enum { 160 MLX5_MEMIC_BASE_ALIGN = 6, 161 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 162 }; 163 164 enum mlx5_ib_mmap_type { 165 MLX5_IB_MMAP_TYPE_MEMIC = 1, 166 MLX5_IB_MMAP_TYPE_VAR = 2, 167 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 168 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 169 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 170 }; 171 172 struct mlx5_bfreg_info { 173 u32 *sys_pages; 174 int num_low_latency_bfregs; 175 unsigned int *count; 176 177 /* 178 * protect bfreg allocation data structs 179 */ 180 struct mutex lock; 181 u32 ver; 182 u8 lib_uar_4k : 1; 183 u8 lib_uar_dyn : 1; 184 u32 num_sys_pages; 185 u32 num_static_sys_pages; 186 u32 total_num_bfregs; 187 u32 num_dyn_bfregs; 188 }; 189 190 struct mlx5_ib_ucontext { 191 struct ib_ucontext ibucontext; 192 struct list_head db_page_list; 193 194 /* protect doorbell record alloc/free 195 */ 196 struct mutex db_page_mutex; 197 struct mlx5_bfreg_info bfregi; 198 u8 cqe_version; 199 /* Transport Domain number */ 200 u32 tdn; 201 202 u64 lib_caps; 203 u16 devx_uid; 204 /* For RoCE LAG TX affinity */ 205 atomic_t tx_port_affinity; 206 }; 207 208 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 209 { 210 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 211 } 212 213 struct mlx5_ib_pd { 214 struct ib_pd ibpd; 215 u32 pdn; 216 u16 uid; 217 }; 218 219 enum { 220 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 221 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 222 MLX5_IB_FLOW_ACTION_DECAP, 223 }; 224 225 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 226 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 227 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 228 #error "Invalid number of bypass priorities" 229 #endif 230 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 231 232 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 233 #define MLX5_IB_NUM_SNIFFER_FTS 2 234 #define MLX5_IB_NUM_EGRESS_FTS 1 235 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 236 struct mlx5_ib_flow_prio { 237 struct mlx5_flow_table *flow_table; 238 unsigned int refcount; 239 }; 240 241 struct mlx5_ib_flow_handler { 242 struct list_head list; 243 struct ib_flow ibflow; 244 struct mlx5_ib_flow_prio *prio; 245 struct mlx5_flow_handle *rule; 246 struct ib_counters *ibcounters; 247 struct mlx5_ib_dev *dev; 248 struct mlx5_ib_flow_matcher *flow_matcher; 249 }; 250 251 struct mlx5_ib_flow_matcher { 252 struct mlx5_ib_match_params matcher_mask; 253 int mask_len; 254 enum mlx5_ib_flow_type flow_type; 255 enum mlx5_flow_namespace_type ns_type; 256 u16 priority; 257 struct mlx5_core_dev *mdev; 258 atomic_t usecnt; 259 u8 match_criteria_enable; 260 }; 261 262 struct mlx5_ib_pp { 263 u16 index; 264 struct mlx5_core_dev *mdev; 265 }; 266 267 enum mlx5_ib_optional_counter_type { 268 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 269 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 270 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 271 272 MLX5_IB_OPCOUNTER_MAX, 273 }; 274 275 struct mlx5_ib_flow_db { 276 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 277 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 278 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 279 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 280 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 281 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 282 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 283 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 284 struct mlx5_flow_table *lag_demux_ft; 285 /* Protect flow steering bypass flow tables 286 * when add/del flow rules. 287 * only single add/removal of flow steering rule could be done 288 * simultaneously. 289 */ 290 struct mutex lock; 291 }; 292 293 /* Use macros here so that don't have to duplicate 294 * enum ib_send_flags and enum ib_qp_type for low-level driver 295 */ 296 297 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 298 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 299 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 300 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 301 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 302 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 303 304 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 305 /* 306 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 307 * creates the actual hardware QP. 308 */ 309 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 310 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 311 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 312 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 313 314 #define MLX5_IB_UMR_OCTOWORD 16 315 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 316 317 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 318 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 319 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 320 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 321 #define MLX5_IB_UPD_XLT_PD BIT(4) 322 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 323 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 324 325 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 326 * 327 * These flags are intended for internal use by the mlx5_ib driver, and they 328 * rely on the range reserved for that use in the ib_qp_create_flags enum. 329 */ 330 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 331 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 332 333 struct wr_list { 334 u16 opcode; 335 u16 next; 336 }; 337 338 enum mlx5_ib_rq_flags { 339 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 340 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 341 }; 342 343 struct mlx5_ib_wq { 344 struct mlx5_frag_buf_ctrl fbc; 345 u64 *wrid; 346 u32 *wr_data; 347 struct wr_list *w_list; 348 unsigned *wqe_head; 349 u16 unsig_count; 350 351 /* serialize post to the work queue 352 */ 353 spinlock_t lock; 354 int wqe_cnt; 355 int max_post; 356 int max_gs; 357 int offset; 358 int wqe_shift; 359 unsigned head; 360 unsigned tail; 361 u16 cur_post; 362 u16 last_poll; 363 void *cur_edge; 364 }; 365 366 enum mlx5_ib_wq_flags { 367 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 368 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 369 }; 370 371 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 372 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 373 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 374 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 375 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 376 377 struct mlx5_ib_rwq { 378 struct ib_wq ibwq; 379 struct mlx5_core_qp core_qp; 380 u32 rq_num_pas; 381 u32 log_rq_stride; 382 u32 log_rq_size; 383 u32 rq_page_offset; 384 u32 log_page_size; 385 u32 log_num_strides; 386 u32 two_byte_shift_en; 387 u32 single_stride_log_num_of_bytes; 388 struct ib_umem *umem; 389 size_t buf_size; 390 unsigned int page_shift; 391 struct mlx5_db db; 392 u32 user_index; 393 u32 wqe_count; 394 u32 wqe_shift; 395 int wq_sig; 396 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 397 }; 398 399 struct mlx5_ib_rwq_ind_table { 400 struct ib_rwq_ind_table ib_rwq_ind_tbl; 401 u32 rqtn; 402 u16 uid; 403 }; 404 405 struct mlx5_ib_ubuffer { 406 struct ib_umem *umem; 407 int buf_size; 408 u64 buf_addr; 409 }; 410 411 struct mlx5_ib_qp_base { 412 struct mlx5_ib_qp *container_mibqp; 413 struct mlx5_core_qp mqp; 414 struct mlx5_ib_ubuffer ubuffer; 415 }; 416 417 struct mlx5_ib_qp_trans { 418 struct mlx5_ib_qp_base base; 419 u16 xrcdn; 420 u32 alt_port; 421 u8 atomic_rd_en; 422 u8 resp_depth; 423 }; 424 425 struct mlx5_ib_rss_qp { 426 u32 tirn; 427 }; 428 429 struct mlx5_ib_rq { 430 struct mlx5_ib_qp_base base; 431 struct mlx5_ib_wq *rq; 432 struct mlx5_ib_ubuffer ubuffer; 433 struct mlx5_db *doorbell; 434 u32 tirn; 435 u8 state; 436 u32 flags; 437 }; 438 439 struct mlx5_ib_sq { 440 struct mlx5_ib_qp_base base; 441 struct mlx5_ib_wq *sq; 442 struct mlx5_ib_ubuffer ubuffer; 443 struct mlx5_db *doorbell; 444 struct mlx5_flow_handle *flow_rule; 445 u32 tisn; 446 u8 state; 447 }; 448 449 struct mlx5_ib_raw_packet_qp { 450 struct mlx5_ib_sq sq; 451 struct mlx5_ib_rq rq; 452 }; 453 454 struct mlx5_bf { 455 int buf_size; 456 unsigned long offset; 457 struct mlx5_sq_bfreg *bfreg; 458 }; 459 460 struct mlx5_ib_dct { 461 struct mlx5_core_dct mdct; 462 u32 *in; 463 }; 464 465 struct mlx5_ib_gsi_qp { 466 struct ib_qp *rx_qp; 467 u32 port_num; 468 struct ib_qp_cap cap; 469 struct ib_cq *cq; 470 struct mlx5_ib_gsi_wr *outstanding_wrs; 471 u32 outstanding_pi, outstanding_ci; 472 int num_qps; 473 /* Protects access to the tx_qps. Post send operations synchronize 474 * with tx_qp creation in setup_qp(). Also protects the 475 * outstanding_wrs array and indices. 476 */ 477 spinlock_t lock; 478 struct ib_qp **tx_qps; 479 }; 480 481 struct mlx5_ib_qp { 482 struct ib_qp ibqp; 483 union { 484 struct mlx5_ib_qp_trans trans_qp; 485 struct mlx5_ib_raw_packet_qp raw_packet_qp; 486 struct mlx5_ib_rss_qp rss_qp; 487 struct mlx5_ib_dct dct; 488 struct mlx5_ib_gsi_qp gsi; 489 }; 490 struct mlx5_frag_buf buf; 491 492 struct mlx5_db db; 493 struct mlx5_ib_wq rq; 494 495 u8 sq_signal_bits; 496 u8 next_fence; 497 struct mlx5_ib_wq sq; 498 499 /* serialize qp state modifications 500 */ 501 struct mutex mutex; 502 /* cached variant of create_flags from struct ib_qp_init_attr */ 503 u32 flags; 504 u32 port; 505 u8 state; 506 int max_inline_data; 507 struct mlx5_bf bf; 508 u8 has_rq:1; 509 u8 is_rss:1; 510 511 /* only for user space QPs. For kernel 512 * we have it from the bf object 513 */ 514 int bfregn; 515 516 struct list_head qps_list; 517 struct list_head cq_recv_list; 518 struct list_head cq_send_list; 519 struct mlx5_rate_limit rl; 520 u32 underlay_qpn; 521 u32 flags_en; 522 /* 523 * IB/core doesn't store low-level QP types, so 524 * store both MLX and IBTA types in the field below. 525 */ 526 enum ib_qp_type type; 527 /* A flag to indicate if there's a new counter is configured 528 * but not take effective 529 */ 530 u32 counter_pending; 531 u16 gsi_lag_port; 532 }; 533 534 struct mlx5_ib_cq_buf { 535 struct mlx5_frag_buf_ctrl fbc; 536 struct mlx5_frag_buf frag_buf; 537 struct ib_umem *umem; 538 int cqe_size; 539 int nent; 540 }; 541 542 struct mlx5_umr_wr { 543 struct ib_send_wr wr; 544 u64 virt_addr; 545 u64 offset; 546 struct ib_pd *pd; 547 unsigned int page_shift; 548 unsigned int xlt_size; 549 u64 length; 550 int access_flags; 551 u32 mkey; 552 u8 ignore_free_state:1; 553 }; 554 555 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 556 { 557 return container_of(wr, struct mlx5_umr_wr, wr); 558 } 559 560 enum mlx5_ib_cq_pr_flags { 561 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 562 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 563 }; 564 565 struct mlx5_ib_cq { 566 struct ib_cq ibcq; 567 struct mlx5_core_cq mcq; 568 struct mlx5_ib_cq_buf buf; 569 struct mlx5_db db; 570 571 /* serialize access to the CQ 572 */ 573 spinlock_t lock; 574 575 /* protect resize cq 576 */ 577 struct mutex resize_mutex; 578 struct mlx5_ib_cq_buf *resize_buf; 579 struct ib_umem *resize_umem; 580 int cqe_size; 581 struct list_head list_send_qp; 582 struct list_head list_recv_qp; 583 u32 create_flags; 584 struct list_head wc_list; 585 enum ib_cq_notify_flags notify_flags; 586 struct work_struct notify_work; 587 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 588 }; 589 590 struct mlx5_ib_wc { 591 struct ib_wc wc; 592 struct list_head list; 593 }; 594 595 struct mlx5_ib_srq { 596 struct ib_srq ibsrq; 597 struct mlx5_core_srq msrq; 598 struct mlx5_frag_buf buf; 599 struct mlx5_db db; 600 struct mlx5_frag_buf_ctrl fbc; 601 u64 *wrid; 602 /* protect SRQ hanlding 603 */ 604 spinlock_t lock; 605 int head; 606 int tail; 607 u16 wqe_ctr; 608 struct ib_umem *umem; 609 /* serialize arming a SRQ 610 */ 611 struct mutex mutex; 612 int wq_sig; 613 }; 614 615 struct mlx5_ib_xrcd { 616 struct ib_xrcd ibxrcd; 617 u32 xrcdn; 618 }; 619 620 enum mlx5_ib_mtt_access_flags { 621 MLX5_IB_MTT_READ = (1 << 0), 622 MLX5_IB_MTT_WRITE = (1 << 1), 623 }; 624 625 struct mlx5_user_mmap_entry { 626 struct rdma_user_mmap_entry rdma_entry; 627 u8 mmap_flag; 628 u64 address; 629 u32 page_idx; 630 }; 631 632 enum mlx5_mkey_type { 633 MLX5_MKEY_MR = 1, 634 MLX5_MKEY_MW, 635 MLX5_MKEY_INDIRECT_DEVX, 636 }; 637 638 struct mlx5_ib_mkey { 639 u32 key; 640 enum mlx5_mkey_type type; 641 unsigned int ndescs; 642 struct wait_queue_head wait; 643 refcount_t usecount; 644 }; 645 646 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 647 648 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 649 IB_ACCESS_REMOTE_WRITE |\ 650 IB_ACCESS_REMOTE_READ |\ 651 IB_ACCESS_REMOTE_ATOMIC |\ 652 IB_ZERO_BASED) 653 654 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 655 IB_ACCESS_REMOTE_WRITE |\ 656 IB_ACCESS_REMOTE_READ |\ 657 IB_ZERO_BASED) 658 659 #define mlx5_update_odp_stats(mr, counter_name, value) \ 660 atomic64_add(value, &((mr)->odp_stats.counter_name)) 661 662 struct mlx5_ib_mr { 663 struct ib_mr ibmr; 664 struct mlx5_ib_mkey mmkey; 665 666 /* User MR data */ 667 struct mlx5_cache_ent *cache_ent; 668 /* Everything after cache_ent is zero'd when MR allocated */ 669 struct ib_umem *umem; 670 671 union { 672 /* Used only while the MR is in the cache */ 673 struct { 674 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 675 struct mlx5_async_work cb_work; 676 /* Cache list element */ 677 struct list_head list; 678 }; 679 680 /* Used only by kernel MRs (umem == NULL) */ 681 struct { 682 void *descs; 683 void *descs_alloc; 684 dma_addr_t desc_map; 685 int max_descs; 686 int desc_size; 687 int access_mode; 688 689 /* For Kernel IB_MR_TYPE_INTEGRITY */ 690 struct mlx5_core_sig_ctx *sig; 691 struct mlx5_ib_mr *pi_mr; 692 struct mlx5_ib_mr *klm_mr; 693 struct mlx5_ib_mr *mtt_mr; 694 u64 data_iova; 695 u64 pi_iova; 696 int meta_ndescs; 697 int meta_length; 698 int data_length; 699 }; 700 701 /* Used only by User MRs (umem != NULL) */ 702 struct { 703 unsigned int page_shift; 704 /* Current access_flags */ 705 int access_flags; 706 707 /* For User ODP */ 708 struct mlx5_ib_mr *parent; 709 struct xarray implicit_children; 710 union { 711 struct work_struct work; 712 } odp_destroy; 713 struct ib_odp_counters odp_stats; 714 bool is_odp_implicit; 715 }; 716 }; 717 }; 718 719 /* Zero the fields in the mr that are variant depending on usage */ 720 static inline void mlx5_clear_mr(struct mlx5_ib_mr *mr) 721 { 722 memset_after(mr, 0, cache_ent); 723 } 724 725 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 726 { 727 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 728 mr->umem->is_odp; 729 } 730 731 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 732 { 733 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 734 mr->umem->is_dmabuf; 735 } 736 737 struct mlx5_ib_mw { 738 struct ib_mw ibmw; 739 struct mlx5_ib_mkey mmkey; 740 }; 741 742 struct mlx5_ib_umr_context { 743 struct ib_cqe cqe; 744 enum ib_wc_status status; 745 struct completion done; 746 }; 747 748 struct umr_common { 749 struct ib_pd *pd; 750 struct ib_cq *cq; 751 struct ib_qp *qp; 752 /* control access to UMR QP 753 */ 754 struct semaphore sem; 755 }; 756 757 struct mlx5_cache_ent { 758 struct list_head head; 759 /* sync access to the cahce entry 760 */ 761 spinlock_t lock; 762 763 764 char name[4]; 765 u32 order; 766 u32 xlt; 767 u32 access_mode; 768 u32 page; 769 770 u8 disabled:1; 771 u8 fill_to_high_water:1; 772 773 /* 774 * - available_mrs is the length of list head, ie the number of MRs 775 * available for immediate allocation. 776 * - total_mrs is available_mrs plus all in use MRs that could be 777 * returned to the cache. 778 * - limit is the low water mark for available_mrs, 2* limit is the 779 * upper water mark. 780 * - pending is the number of MRs currently being created 781 */ 782 u32 total_mrs; 783 u32 available_mrs; 784 u32 limit; 785 u32 pending; 786 787 /* Statistics */ 788 u32 miss; 789 790 struct mlx5_ib_dev *dev; 791 struct work_struct work; 792 struct delayed_work dwork; 793 }; 794 795 struct mlx5_mr_cache { 796 struct workqueue_struct *wq; 797 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 798 struct dentry *root; 799 unsigned long last_add; 800 }; 801 802 struct mlx5_ib_port_resources { 803 struct mlx5_ib_gsi_qp *gsi; 804 struct work_struct pkey_change_work; 805 }; 806 807 struct mlx5_ib_resources { 808 struct ib_cq *c0; 809 u32 xrcdn0; 810 u32 xrcdn1; 811 struct ib_pd *p0; 812 struct ib_srq *s0; 813 struct ib_srq *s1; 814 struct mlx5_ib_port_resources ports[2]; 815 }; 816 817 #define MAX_OPFC_RULES 2 818 819 struct mlx5_ib_op_fc { 820 struct mlx5_fc *fc; 821 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 822 }; 823 824 struct mlx5_ib_counters { 825 struct rdma_stat_desc *descs; 826 size_t *offsets; 827 u32 num_q_counters; 828 u32 num_cong_counters; 829 u32 num_ext_ppcnt_counters; 830 u32 num_op_counters; 831 u16 set_id; 832 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 833 }; 834 835 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 836 struct mlx5_ib_op_fc *opfc, 837 enum mlx5_ib_optional_counter_type type); 838 839 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 840 struct mlx5_ib_op_fc *opfc, 841 enum mlx5_ib_optional_counter_type type); 842 843 struct mlx5_ib_multiport_info; 844 845 struct mlx5_ib_multiport { 846 struct mlx5_ib_multiport_info *mpi; 847 /* To be held when accessing the multiport info */ 848 spinlock_t mpi_lock; 849 }; 850 851 struct mlx5_roce { 852 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 853 * netdev pointer 854 */ 855 rwlock_t netdev_lock; 856 struct net_device *netdev; 857 struct notifier_block nb; 858 atomic_t tx_port_affinity; 859 enum ib_port_state last_port_state; 860 struct mlx5_ib_dev *dev; 861 u32 native_port_num; 862 }; 863 864 struct mlx5_ib_port { 865 struct mlx5_ib_counters cnts; 866 struct mlx5_ib_multiport mp; 867 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 868 struct mlx5_roce roce; 869 struct mlx5_eswitch_rep *rep; 870 }; 871 872 struct mlx5_ib_dbg_param { 873 int offset; 874 struct mlx5_ib_dev *dev; 875 struct dentry *dentry; 876 u32 port_num; 877 }; 878 879 enum mlx5_ib_dbg_cc_types { 880 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 881 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 882 MLX5_IB_DBG_CC_RP_TIME_RESET, 883 MLX5_IB_DBG_CC_RP_BYTE_RESET, 884 MLX5_IB_DBG_CC_RP_THRESHOLD, 885 MLX5_IB_DBG_CC_RP_AI_RATE, 886 MLX5_IB_DBG_CC_RP_MAX_RATE, 887 MLX5_IB_DBG_CC_RP_HAI_RATE, 888 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 889 MLX5_IB_DBG_CC_RP_MIN_RATE, 890 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 891 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 892 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 893 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 894 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 895 MLX5_IB_DBG_CC_RP_GD, 896 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 897 MLX5_IB_DBG_CC_NP_CNP_DSCP, 898 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 899 MLX5_IB_DBG_CC_NP_CNP_PRIO, 900 MLX5_IB_DBG_CC_MAX, 901 }; 902 903 struct mlx5_ib_dbg_cc_params { 904 struct dentry *root; 905 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 906 }; 907 908 enum { 909 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 910 }; 911 912 struct mlx5_ib_delay_drop { 913 struct mlx5_ib_dev *dev; 914 struct work_struct delay_drop_work; 915 /* serialize setting of delay drop */ 916 struct mutex lock; 917 u32 timeout; 918 bool activate; 919 atomic_t events_cnt; 920 atomic_t rqs_cnt; 921 struct dentry *dir_debugfs; 922 }; 923 924 enum mlx5_ib_stages { 925 MLX5_IB_STAGE_INIT, 926 MLX5_IB_STAGE_FS, 927 MLX5_IB_STAGE_CAPS, 928 MLX5_IB_STAGE_NON_DEFAULT_CB, 929 MLX5_IB_STAGE_ROCE, 930 MLX5_IB_STAGE_QP, 931 MLX5_IB_STAGE_SRQ, 932 MLX5_IB_STAGE_DEVICE_RESOURCES, 933 MLX5_IB_STAGE_DEVICE_NOTIFIER, 934 MLX5_IB_STAGE_ODP, 935 MLX5_IB_STAGE_COUNTERS, 936 MLX5_IB_STAGE_CONG_DEBUGFS, 937 MLX5_IB_STAGE_UAR, 938 MLX5_IB_STAGE_BFREG, 939 MLX5_IB_STAGE_PRE_IB_REG_UMR, 940 MLX5_IB_STAGE_WHITELIST_UID, 941 MLX5_IB_STAGE_IB_REG, 942 MLX5_IB_STAGE_POST_IB_REG_UMR, 943 MLX5_IB_STAGE_DELAY_DROP, 944 MLX5_IB_STAGE_RESTRACK, 945 MLX5_IB_STAGE_MAX, 946 }; 947 948 struct mlx5_ib_stage { 949 int (*init)(struct mlx5_ib_dev *dev); 950 void (*cleanup)(struct mlx5_ib_dev *dev); 951 }; 952 953 #define STAGE_CREATE(_stage, _init, _cleanup) \ 954 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 955 956 struct mlx5_ib_profile { 957 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 958 }; 959 960 struct mlx5_ib_multiport_info { 961 struct list_head list; 962 struct mlx5_ib_dev *ibdev; 963 struct mlx5_core_dev *mdev; 964 struct notifier_block mdev_events; 965 struct completion unref_comp; 966 u64 sys_image_guid; 967 u32 mdev_refcnt; 968 bool is_master; 969 bool unaffiliate; 970 }; 971 972 struct mlx5_ib_flow_action { 973 struct ib_flow_action ib_action; 974 union { 975 struct { 976 u64 ib_flags; 977 struct mlx5_accel_esp_xfrm *ctx; 978 } esp_aes_gcm; 979 struct { 980 struct mlx5_ib_dev *dev; 981 u32 sub_type; 982 union { 983 struct mlx5_modify_hdr *modify_hdr; 984 struct mlx5_pkt_reformat *pkt_reformat; 985 }; 986 } flow_action_raw; 987 }; 988 }; 989 990 struct mlx5_dm { 991 struct mlx5_core_dev *dev; 992 /* This lock is used to protect the access to the shared 993 * allocation map when concurrent requests by different 994 * processes are handled. 995 */ 996 spinlock_t lock; 997 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 998 }; 999 1000 struct mlx5_read_counters_attr { 1001 struct mlx5_fc *hw_cntrs_hndl; 1002 u64 *out; 1003 u32 flags; 1004 }; 1005 1006 enum mlx5_ib_counters_type { 1007 MLX5_IB_COUNTERS_FLOW, 1008 }; 1009 1010 struct mlx5_ib_mcounters { 1011 struct ib_counters ibcntrs; 1012 enum mlx5_ib_counters_type type; 1013 /* number of counters supported for this counters type */ 1014 u32 counters_num; 1015 struct mlx5_fc *hw_cntrs_hndl; 1016 /* read function for this counters type */ 1017 int (*read_counters)(struct ib_device *ibdev, 1018 struct mlx5_read_counters_attr *read_attr); 1019 /* max index set as part of create_flow */ 1020 u32 cntrs_max_index; 1021 /* number of counters data entries (<description,index> pair) */ 1022 u32 ncounters; 1023 /* counters data array for descriptions and indexes */ 1024 struct mlx5_ib_flow_counters_desc *counters_data; 1025 /* protects access to mcounters internal data */ 1026 struct mutex mcntrs_mutex; 1027 }; 1028 1029 static inline struct mlx5_ib_mcounters * 1030 to_mcounters(struct ib_counters *ibcntrs) 1031 { 1032 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1033 } 1034 1035 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1036 bool is_egress, 1037 struct mlx5_flow_act *action); 1038 struct mlx5_ib_lb_state { 1039 /* protect the user_td */ 1040 struct mutex mutex; 1041 u32 user_td; 1042 int qps; 1043 bool enabled; 1044 }; 1045 1046 struct mlx5_ib_pf_eq { 1047 struct notifier_block irq_nb; 1048 struct mlx5_ib_dev *dev; 1049 struct mlx5_eq *core; 1050 struct work_struct work; 1051 spinlock_t lock; /* Pagefaults spinlock */ 1052 struct workqueue_struct *wq; 1053 mempool_t *pool; 1054 }; 1055 1056 struct mlx5_devx_event_table { 1057 struct mlx5_nb devx_nb; 1058 /* serialize updating the event_xa */ 1059 struct mutex event_xa_lock; 1060 struct xarray event_xa; 1061 }; 1062 1063 struct mlx5_var_table { 1064 /* serialize updating the bitmap */ 1065 struct mutex bitmap_lock; 1066 unsigned long *bitmap; 1067 u64 hw_start_addr; 1068 u32 stride_size; 1069 u64 num_var_hw_entries; 1070 }; 1071 1072 struct mlx5_port_caps { 1073 bool has_smi; 1074 u8 ext_port_cap; 1075 }; 1076 1077 struct mlx5_ib_dev { 1078 struct ib_device ib_dev; 1079 struct mlx5_core_dev *mdev; 1080 struct notifier_block mdev_events; 1081 int num_ports; 1082 /* serialize update of capability mask 1083 */ 1084 struct mutex cap_mask_mutex; 1085 u8 ib_active:1; 1086 u8 is_rep:1; 1087 u8 lag_active:1; 1088 u8 wc_support:1; 1089 u8 fill_delay; 1090 struct umr_common umrc; 1091 /* sync used page count stats 1092 */ 1093 struct mlx5_ib_resources devr; 1094 1095 atomic_t mkey_var; 1096 struct mlx5_mr_cache cache; 1097 struct timer_list delay_timer; 1098 /* Prevents soft lock on massive reg MRs */ 1099 struct mutex slow_path_mutex; 1100 struct ib_odp_caps odp_caps; 1101 u64 odp_max_size; 1102 struct mutex odp_eq_mutex; 1103 struct mlx5_ib_pf_eq odp_pf_eq; 1104 1105 struct xarray odp_mkeys; 1106 1107 u32 null_mkey; 1108 struct mlx5_ib_flow_db *flow_db; 1109 /* protect resources needed as part of reset flow */ 1110 spinlock_t reset_flow_resource_lock; 1111 struct list_head qp_list; 1112 /* Array with num_ports elements */ 1113 struct mlx5_ib_port *port; 1114 struct mlx5_sq_bfreg bfreg; 1115 struct mlx5_sq_bfreg wc_bfreg; 1116 struct mlx5_sq_bfreg fp_bfreg; 1117 struct mlx5_ib_delay_drop delay_drop; 1118 const struct mlx5_ib_profile *profile; 1119 1120 struct mlx5_ib_lb_state lb; 1121 u8 umr_fence; 1122 struct list_head ib_dev_list; 1123 u64 sys_image_guid; 1124 struct mlx5_dm dm; 1125 u16 devx_whitelist_uid; 1126 struct mlx5_srq_table srq_table; 1127 struct mlx5_qp_table qp_table; 1128 struct mlx5_async_ctx async_ctx; 1129 struct mlx5_devx_event_table devx_event_table; 1130 struct mlx5_var_table var_table; 1131 1132 struct xarray sig_mrs; 1133 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1134 u16 pkey_table_len; 1135 }; 1136 1137 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1138 { 1139 return container_of(mcq, struct mlx5_ib_cq, mcq); 1140 } 1141 1142 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1143 { 1144 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1145 } 1146 1147 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1148 { 1149 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1150 } 1151 1152 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1153 { 1154 return to_mdev(mr->ibmr.device); 1155 } 1156 1157 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1158 { 1159 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1160 udata, struct mlx5_ib_ucontext, ibucontext); 1161 1162 return to_mdev(context->ibucontext.device); 1163 } 1164 1165 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1166 { 1167 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1168 } 1169 1170 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1171 { 1172 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1173 } 1174 1175 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1176 { 1177 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1178 } 1179 1180 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1181 { 1182 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1183 } 1184 1185 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1186 { 1187 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1188 } 1189 1190 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1191 { 1192 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1193 } 1194 1195 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1196 { 1197 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1198 } 1199 1200 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1201 { 1202 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1203 } 1204 1205 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1206 { 1207 return container_of(msrq, struct mlx5_ib_srq, msrq); 1208 } 1209 1210 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1211 { 1212 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1213 } 1214 1215 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1216 { 1217 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1218 } 1219 1220 static inline struct mlx5_ib_flow_action * 1221 to_mflow_act(struct ib_flow_action *ibact) 1222 { 1223 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1224 } 1225 1226 static inline struct mlx5_user_mmap_entry * 1227 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1228 { 1229 return container_of(rdma_entry, 1230 struct mlx5_user_mmap_entry, rdma_entry); 1231 } 1232 1233 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1234 struct mlx5_db *db); 1235 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1236 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1237 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1238 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1239 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1240 struct ib_udata *udata); 1241 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1242 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1243 { 1244 return 0; 1245 } 1246 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1247 struct ib_udata *udata); 1248 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1249 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1250 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1251 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1252 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1253 const struct ib_recv_wr **bad_wr); 1254 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1255 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1256 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1257 struct ib_udata *udata); 1258 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1259 int attr_mask, struct ib_udata *udata); 1260 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1261 struct ib_qp_init_attr *qp_init_attr); 1262 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1263 void mlx5_ib_drain_sq(struct ib_qp *qp); 1264 void mlx5_ib_drain_rq(struct ib_qp *qp); 1265 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1266 size_t buflen, size_t *bc); 1267 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1268 size_t buflen, size_t *bc); 1269 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1270 size_t buflen, size_t *bc); 1271 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1272 struct ib_udata *udata); 1273 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1274 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1275 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1276 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1277 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1278 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1279 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1280 u64 virt_addr, int access_flags, 1281 struct ib_udata *udata); 1282 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1283 u64 length, u64 virt_addr, 1284 int fd, int access_flags, 1285 struct ib_udata *udata); 1286 int mlx5_ib_advise_mr(struct ib_pd *pd, 1287 enum ib_uverbs_advise_mr_advice advice, 1288 u32 flags, 1289 struct ib_sge *sg_list, 1290 u32 num_sge, 1291 struct uverbs_attr_bundle *attrs); 1292 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1293 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1294 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1295 int page_shift, int flags); 1296 int mlx5_ib_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags); 1297 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1298 int access_flags); 1299 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1300 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1301 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1302 u64 length, u64 virt_addr, int access_flags, 1303 struct ib_pd *pd, struct ib_udata *udata); 1304 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1305 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1306 u32 max_num_sg); 1307 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1308 u32 max_num_sg, 1309 u32 max_num_meta_sg); 1310 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1311 unsigned int *sg_offset); 1312 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1313 int data_sg_nents, unsigned int *data_sg_offset, 1314 struct scatterlist *meta_sg, int meta_sg_nents, 1315 unsigned int *meta_sg_offset); 1316 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1317 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1318 const struct ib_mad *in, struct ib_mad *out, 1319 size_t *out_mad_size, u16 *out_mad_pkey_index); 1320 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1321 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1322 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1323 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1324 __be64 *sys_image_guid); 1325 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1326 u16 *max_pkeys); 1327 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1328 u32 *vendor_id); 1329 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1330 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1331 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1332 u16 *pkey); 1333 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1334 union ib_gid *gid); 1335 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1336 struct ib_port_attr *props); 1337 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1338 struct ib_port_attr *props); 1339 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1340 u64 access_flags); 1341 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1342 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1343 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1344 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1345 1346 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1347 unsigned int entry, int access_flags); 1348 1349 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1350 struct ib_mr_status *mr_status); 1351 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1352 struct ib_wq_init_attr *init_attr, 1353 struct ib_udata *udata); 1354 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1355 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1356 u32 wq_attr_mask, struct ib_udata *udata); 1357 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1358 struct ib_rwq_ind_table_init_attr *init_attr, 1359 struct ib_udata *udata); 1360 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1361 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1362 struct ib_dm_mr_attr *attr, 1363 struct uverbs_attr_bundle *attrs); 1364 1365 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1366 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1367 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1368 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1369 int __init mlx5_ib_odp_init(void); 1370 void mlx5_ib_odp_cleanup(void); 1371 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1372 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1373 struct mlx5_ib_mr *mr, int flags); 1374 1375 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1376 enum ib_uverbs_advise_mr_advice advice, 1377 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1378 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1379 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1380 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1381 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1382 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1383 struct mlx5_ib_pf_eq *eq) 1384 { 1385 return 0; 1386 } 1387 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1388 static inline int mlx5_ib_odp_init(void) { return 0; } 1389 static inline void mlx5_ib_odp_cleanup(void) {} 1390 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1391 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1392 struct mlx5_ib_mr *mr, int flags) {} 1393 1394 static inline int 1395 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1396 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1397 struct ib_sge *sg_list, u32 num_sge) 1398 { 1399 return -EOPNOTSUPP; 1400 } 1401 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1402 { 1403 return -EOPNOTSUPP; 1404 } 1405 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1406 { 1407 return -EOPNOTSUPP; 1408 } 1409 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1410 1411 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1412 1413 /* Needed for rep profile */ 1414 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1415 const struct mlx5_ib_profile *profile, 1416 int stage); 1417 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1418 const struct mlx5_ib_profile *profile); 1419 1420 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1421 u32 port, struct ifla_vf_info *info); 1422 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1423 u32 port, int state); 1424 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1425 u32 port, struct ifla_vf_stats *stats); 1426 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1427 struct ifla_vf_guid *node_guid, 1428 struct ifla_vf_guid *port_guid); 1429 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1430 u64 guid, int type); 1431 1432 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1433 const struct ib_gid_attr *attr); 1434 1435 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1436 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1437 1438 /* GSI QP helper functions */ 1439 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1440 struct ib_qp_init_attr *attr); 1441 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1442 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1443 int attr_mask); 1444 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1445 int qp_attr_mask, 1446 struct ib_qp_init_attr *qp_init_attr); 1447 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1448 const struct ib_send_wr **bad_wr); 1449 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1450 const struct ib_recv_wr **bad_wr); 1451 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1452 1453 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1454 1455 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1456 int bfregn); 1457 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1458 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1459 u32 ib_port_num, 1460 u32 *native_port_num); 1461 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1462 u32 port_num); 1463 1464 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1465 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1466 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1467 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1468 1469 static inline int is_qp1(enum ib_qp_type qp_type) 1470 { 1471 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1472 } 1473 1474 #define MLX5_MAX_UMR_SHIFT 16 1475 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1476 1477 static inline u32 check_cq_create_flags(u32 flags) 1478 { 1479 /* 1480 * It returns non-zero value for unsupported CQ 1481 * create flags, otherwise it returns zero. 1482 */ 1483 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1484 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1485 } 1486 1487 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1488 u32 *user_index) 1489 { 1490 if (cqe_version) { 1491 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1492 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1493 return -EINVAL; 1494 *user_index = cmd_uidx; 1495 } else { 1496 *user_index = MLX5_IB_DEFAULT_UIDX; 1497 } 1498 1499 return 0; 1500 } 1501 1502 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1503 struct mlx5_ib_create_qp *ucmd, 1504 int inlen, 1505 u32 *user_index) 1506 { 1507 u8 cqe_version = ucontext->cqe_version; 1508 1509 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1510 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1511 return 0; 1512 1513 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1514 return -EINVAL; 1515 1516 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1517 } 1518 1519 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1520 struct mlx5_ib_create_srq *ucmd, 1521 int inlen, 1522 u32 *user_index) 1523 { 1524 u8 cqe_version = ucontext->cqe_version; 1525 1526 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1527 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1528 return 0; 1529 1530 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1531 return -EINVAL; 1532 1533 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1534 } 1535 1536 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1537 { 1538 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1539 MLX5_UARS_IN_PAGE : 1; 1540 } 1541 1542 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1543 struct mlx5_bfreg_info *bfregi) 1544 { 1545 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1546 } 1547 1548 extern void *xlt_emergency_page; 1549 1550 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1551 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1552 bool dyn_bfreg); 1553 1554 static inline bool mlx5_ib_can_load_pas_with_umr(struct mlx5_ib_dev *dev, 1555 size_t length) 1556 { 1557 /* 1558 * umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is 1559 * always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka 1560 * MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey 1561 * can never be enabled without this capability. Simplify this weird 1562 * quirky hardware by just saying it can't use PAS lists with UMR at 1563 * all. 1564 */ 1565 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1566 return false; 1567 1568 /* 1569 * length is the size of the MR in bytes when mlx5_ib_update_xlt() is 1570 * used. 1571 */ 1572 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && 1573 length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE) 1574 return false; 1575 return true; 1576 } 1577 1578 /* 1579 * true if an existing MR can be reconfigured to new access_flags using UMR. 1580 * Older HW cannot use UMR to update certain elements of the MKC. See 1581 * umr_check_mkey_mask(), get_umr_update_access_mask() and umr_check_mkey_mask() 1582 */ 1583 static inline bool mlx5_ib_can_reconfig_with_umr(struct mlx5_ib_dev *dev, 1584 unsigned int current_access_flags, 1585 unsigned int target_access_flags) 1586 { 1587 unsigned int diffs = current_access_flags ^ target_access_flags; 1588 1589 if ((diffs & IB_ACCESS_REMOTE_ATOMIC) && 1590 MLX5_CAP_GEN(dev->mdev, atomic) && 1591 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1592 return false; 1593 1594 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 1595 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && 1596 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 1597 return false; 1598 1599 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 1600 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) && 1601 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 1602 return false; 1603 1604 return true; 1605 } 1606 1607 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1608 struct mlx5_ib_mkey *mmkey) 1609 { 1610 refcount_set(&mmkey->usecount, 1); 1611 1612 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1613 mmkey, GFP_KERNEL)); 1614 } 1615 1616 /* deref an mkey that can participate in ODP flow */ 1617 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1618 { 1619 if (refcount_dec_and_test(&mmkey->usecount)) 1620 wake_up(&mmkey->wait); 1621 } 1622 1623 /* deref an mkey that can participate in ODP flow and wait for relese */ 1624 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1625 { 1626 mlx5r_deref_odp_mkey(mmkey); 1627 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1628 } 1629 1630 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1631 1632 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1633 { 1634 return dev->lag_active || 1635 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1636 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1637 } 1638 1639 static inline bool rt_supported(int ts_cap) 1640 { 1641 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1642 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1643 } 1644 #endif /* MLX5_IB_H */ 1645