1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 49 #define mlx5_ib_dbg(dev, format, arg...) \ 50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_err(dev, format, arg...) \ 54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define mlx5_ib_warn(dev, format, arg...) \ 58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 59 __LINE__, current->pid, ##arg) 60 61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 62 sizeof(((type *)0)->fld) <= (sz)) 63 #define MLX5_IB_DEFAULT_UIDX 0xffffff 64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 65 66 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 67 68 enum { 69 MLX5_IB_MMAP_CMD_SHIFT = 8, 70 MLX5_IB_MMAP_CMD_MASK = 0xff, 71 }; 72 73 enum mlx5_ib_mmap_cmd { 74 MLX5_IB_MMAP_REGULAR_PAGE = 0, 75 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 76 MLX5_IB_MMAP_WC_PAGE = 2, 77 MLX5_IB_MMAP_NC_PAGE = 3, 78 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 79 MLX5_IB_MMAP_CORE_CLOCK = 5, 80 }; 81 82 enum { 83 MLX5_RES_SCAT_DATA32_CQE = 0x1, 84 MLX5_RES_SCAT_DATA64_CQE = 0x2, 85 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 86 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 87 }; 88 89 enum mlx5_ib_latency_class { 90 MLX5_IB_LATENCY_CLASS_LOW, 91 MLX5_IB_LATENCY_CLASS_MEDIUM, 92 MLX5_IB_LATENCY_CLASS_HIGH, 93 MLX5_IB_LATENCY_CLASS_FAST_PATH 94 }; 95 96 enum mlx5_ib_mad_ifc_flags { 97 MLX5_MAD_IFC_IGNORE_MKEY = 1, 98 MLX5_MAD_IFC_IGNORE_BKEY = 2, 99 MLX5_MAD_IFC_NET_VIEW = 4, 100 }; 101 102 enum { 103 MLX5_CROSS_CHANNEL_UUAR = 0, 104 }; 105 106 enum { 107 MLX5_CQE_VERSION_V0, 108 MLX5_CQE_VERSION_V1, 109 }; 110 111 struct mlx5_ib_vma_private_data { 112 struct list_head list; 113 struct vm_area_struct *vma; 114 }; 115 116 struct mlx5_ib_ucontext { 117 struct ib_ucontext ibucontext; 118 struct list_head db_page_list; 119 120 /* protect doorbell record alloc/free 121 */ 122 struct mutex db_page_mutex; 123 struct mlx5_uuar_info uuari; 124 u8 cqe_version; 125 /* Transport Domain number */ 126 u32 tdn; 127 struct list_head vma_private_list; 128 }; 129 130 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 131 { 132 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 133 } 134 135 struct mlx5_ib_pd { 136 struct ib_pd ibpd; 137 u32 pdn; 138 }; 139 140 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 141 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 142 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 143 #error "Invalid number of bypass priorities" 144 #endif 145 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 146 147 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 148 #define MLX5_IB_NUM_SNIFFER_FTS 2 149 struct mlx5_ib_flow_prio { 150 struct mlx5_flow_table *flow_table; 151 unsigned int refcount; 152 }; 153 154 struct mlx5_ib_flow_handler { 155 struct list_head list; 156 struct ib_flow ibflow; 157 struct mlx5_ib_flow_prio *prio; 158 struct mlx5_flow_handle *rule; 159 }; 160 161 struct mlx5_ib_flow_db { 162 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 163 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 164 struct mlx5_flow_table *lag_demux_ft; 165 /* Protect flow steering bypass flow tables 166 * when add/del flow rules. 167 * only single add/removal of flow steering rule could be done 168 * simultaneously. 169 */ 170 struct mutex lock; 171 }; 172 173 /* Use macros here so that don't have to duplicate 174 * enum ib_send_flags and enum ib_qp_type for low-level driver 175 */ 176 177 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 178 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 179 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 180 181 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3) 182 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4) 183 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END 184 185 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 186 /* 187 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 188 * creates the actual hardware QP. 189 */ 190 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 191 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 192 193 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 194 * 195 * These flags are intended for internal use by the mlx5_ib driver, and they 196 * rely on the range reserved for that use in the ib_qp_create_flags enum. 197 */ 198 199 /* Create a UD QP whose source QP number is 1 */ 200 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 201 { 202 return IB_QP_CREATE_RESERVED_START; 203 } 204 205 struct wr_list { 206 u16 opcode; 207 u16 next; 208 }; 209 210 struct mlx5_ib_wq { 211 u64 *wrid; 212 u32 *wr_data; 213 struct wr_list *w_list; 214 unsigned *wqe_head; 215 u16 unsig_count; 216 217 /* serialize post to the work queue 218 */ 219 spinlock_t lock; 220 int wqe_cnt; 221 int max_post; 222 int max_gs; 223 int offset; 224 int wqe_shift; 225 unsigned head; 226 unsigned tail; 227 u16 cur_post; 228 u16 last_poll; 229 void *qend; 230 }; 231 232 struct mlx5_ib_rwq { 233 struct ib_wq ibwq; 234 struct mlx5_core_qp core_qp; 235 u32 rq_num_pas; 236 u32 log_rq_stride; 237 u32 log_rq_size; 238 u32 rq_page_offset; 239 u32 log_page_size; 240 struct ib_umem *umem; 241 size_t buf_size; 242 unsigned int page_shift; 243 int create_type; 244 struct mlx5_db db; 245 u32 user_index; 246 u32 wqe_count; 247 u32 wqe_shift; 248 int wq_sig; 249 }; 250 251 enum { 252 MLX5_QP_USER, 253 MLX5_QP_KERNEL, 254 MLX5_QP_EMPTY 255 }; 256 257 enum { 258 MLX5_WQ_USER, 259 MLX5_WQ_KERNEL 260 }; 261 262 struct mlx5_ib_rwq_ind_table { 263 struct ib_rwq_ind_table ib_rwq_ind_tbl; 264 u32 rqtn; 265 }; 266 267 /* 268 * Connect-IB can trigger up to four concurrent pagefaults 269 * per-QP. 270 */ 271 enum mlx5_ib_pagefault_context { 272 MLX5_IB_PAGEFAULT_RESPONDER_READ, 273 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 274 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 275 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 276 MLX5_IB_PAGEFAULT_CONTEXTS 277 }; 278 279 static inline enum mlx5_ib_pagefault_context 280 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 281 { 282 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 283 } 284 285 struct mlx5_ib_pfault { 286 struct work_struct work; 287 struct mlx5_pagefault mpfault; 288 }; 289 290 struct mlx5_ib_ubuffer { 291 struct ib_umem *umem; 292 int buf_size; 293 u64 buf_addr; 294 }; 295 296 struct mlx5_ib_qp_base { 297 struct mlx5_ib_qp *container_mibqp; 298 struct mlx5_core_qp mqp; 299 struct mlx5_ib_ubuffer ubuffer; 300 }; 301 302 struct mlx5_ib_qp_trans { 303 struct mlx5_ib_qp_base base; 304 u16 xrcdn; 305 u8 alt_port; 306 u8 atomic_rd_en; 307 u8 resp_depth; 308 }; 309 310 struct mlx5_ib_rss_qp { 311 u32 tirn; 312 }; 313 314 struct mlx5_ib_rq { 315 struct mlx5_ib_qp_base base; 316 struct mlx5_ib_wq *rq; 317 struct mlx5_ib_ubuffer ubuffer; 318 struct mlx5_db *doorbell; 319 u32 tirn; 320 u8 state; 321 }; 322 323 struct mlx5_ib_sq { 324 struct mlx5_ib_qp_base base; 325 struct mlx5_ib_wq *sq; 326 struct mlx5_ib_ubuffer ubuffer; 327 struct mlx5_db *doorbell; 328 u32 tisn; 329 u8 state; 330 }; 331 332 struct mlx5_ib_raw_packet_qp { 333 struct mlx5_ib_sq sq; 334 struct mlx5_ib_rq rq; 335 }; 336 337 struct mlx5_ib_qp { 338 struct ib_qp ibqp; 339 union { 340 struct mlx5_ib_qp_trans trans_qp; 341 struct mlx5_ib_raw_packet_qp raw_packet_qp; 342 struct mlx5_ib_rss_qp rss_qp; 343 }; 344 struct mlx5_buf buf; 345 346 struct mlx5_db db; 347 struct mlx5_ib_wq rq; 348 349 u8 sq_signal_bits; 350 u8 fm_cache; 351 struct mlx5_ib_wq sq; 352 353 /* serialize qp state modifications 354 */ 355 struct mutex mutex; 356 u32 flags; 357 u8 port; 358 u8 state; 359 int wq_sig; 360 int scat_cqe; 361 int max_inline_data; 362 struct mlx5_bf *bf; 363 int has_rq; 364 365 /* only for user space QPs. For kernel 366 * we have it from the bf object 367 */ 368 int uuarn; 369 370 int create_type; 371 372 /* Store signature errors */ 373 bool signature_en; 374 375 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 376 /* 377 * A flag that is true for QP's that are in a state that doesn't 378 * allow page faults, and shouldn't schedule any more faults. 379 */ 380 int disable_page_faults; 381 /* 382 * The disable_page_faults_lock protects a QP's disable_page_faults 383 * field, allowing for a thread to atomically check whether the QP 384 * allows page faults, and if so schedule a page fault. 385 */ 386 spinlock_t disable_page_faults_lock; 387 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 388 #endif 389 struct list_head qps_list; 390 struct list_head cq_recv_list; 391 struct list_head cq_send_list; 392 u32 rate_limit; 393 }; 394 395 struct mlx5_ib_cq_buf { 396 struct mlx5_buf buf; 397 struct ib_umem *umem; 398 int cqe_size; 399 int nent; 400 }; 401 402 enum mlx5_ib_qp_flags { 403 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 404 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 405 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 406 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 407 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 408 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 409 /* QP uses 1 as its source QP number */ 410 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 411 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 412 MLX5_IB_QP_RSS = 1 << 8, 413 }; 414 415 struct mlx5_umr_wr { 416 struct ib_send_wr wr; 417 union { 418 u64 virt_addr; 419 u64 offset; 420 } target; 421 struct ib_pd *pd; 422 unsigned int page_shift; 423 unsigned int npages; 424 u64 length; 425 int access_flags; 426 u32 mkey; 427 }; 428 429 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 430 { 431 return container_of(wr, struct mlx5_umr_wr, wr); 432 } 433 434 struct mlx5_shared_mr_info { 435 int mr_id; 436 struct ib_umem *umem; 437 }; 438 439 struct mlx5_ib_cq { 440 struct ib_cq ibcq; 441 struct mlx5_core_cq mcq; 442 struct mlx5_ib_cq_buf buf; 443 struct mlx5_db db; 444 445 /* serialize access to the CQ 446 */ 447 spinlock_t lock; 448 449 /* protect resize cq 450 */ 451 struct mutex resize_mutex; 452 struct mlx5_ib_cq_buf *resize_buf; 453 struct ib_umem *resize_umem; 454 int cqe_size; 455 struct list_head list_send_qp; 456 struct list_head list_recv_qp; 457 u32 create_flags; 458 struct list_head wc_list; 459 enum ib_cq_notify_flags notify_flags; 460 struct work_struct notify_work; 461 }; 462 463 struct mlx5_ib_wc { 464 struct ib_wc wc; 465 struct list_head list; 466 }; 467 468 struct mlx5_ib_srq { 469 struct ib_srq ibsrq; 470 struct mlx5_core_srq msrq; 471 struct mlx5_buf buf; 472 struct mlx5_db db; 473 u64 *wrid; 474 /* protect SRQ hanlding 475 */ 476 spinlock_t lock; 477 int head; 478 int tail; 479 u16 wqe_ctr; 480 struct ib_umem *umem; 481 /* serialize arming a SRQ 482 */ 483 struct mutex mutex; 484 int wq_sig; 485 }; 486 487 struct mlx5_ib_xrcd { 488 struct ib_xrcd ibxrcd; 489 u32 xrcdn; 490 }; 491 492 enum mlx5_ib_mtt_access_flags { 493 MLX5_IB_MTT_READ = (1 << 0), 494 MLX5_IB_MTT_WRITE = (1 << 1), 495 }; 496 497 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 498 499 struct mlx5_ib_mr { 500 struct ib_mr ibmr; 501 void *descs; 502 dma_addr_t desc_map; 503 int ndescs; 504 int max_descs; 505 int desc_size; 506 int access_mode; 507 struct mlx5_core_mkey mmkey; 508 struct ib_umem *umem; 509 struct mlx5_shared_mr_info *smr_info; 510 struct list_head list; 511 int order; 512 int umred; 513 int npages; 514 struct mlx5_ib_dev *dev; 515 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 516 struct mlx5_core_sig_ctx *sig; 517 int live; 518 void *descs_alloc; 519 int access_flags; /* Needed for rereg MR */ 520 }; 521 522 struct mlx5_ib_mw { 523 struct ib_mw ibmw; 524 struct mlx5_core_mkey mmkey; 525 }; 526 527 struct mlx5_ib_umr_context { 528 struct ib_cqe cqe; 529 enum ib_wc_status status; 530 struct completion done; 531 }; 532 533 struct umr_common { 534 struct ib_pd *pd; 535 struct ib_cq *cq; 536 struct ib_qp *qp; 537 /* control access to UMR QP 538 */ 539 struct semaphore sem; 540 }; 541 542 enum { 543 MLX5_FMR_INVALID, 544 MLX5_FMR_VALID, 545 MLX5_FMR_BUSY, 546 }; 547 548 struct mlx5_cache_ent { 549 struct list_head head; 550 /* sync access to the cahce entry 551 */ 552 spinlock_t lock; 553 554 555 struct dentry *dir; 556 char name[4]; 557 u32 order; 558 u32 size; 559 u32 cur; 560 u32 miss; 561 u32 limit; 562 563 struct dentry *fsize; 564 struct dentry *fcur; 565 struct dentry *fmiss; 566 struct dentry *flimit; 567 568 struct mlx5_ib_dev *dev; 569 struct work_struct work; 570 struct delayed_work dwork; 571 int pending; 572 }; 573 574 struct mlx5_mr_cache { 575 struct workqueue_struct *wq; 576 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 577 int stopped; 578 struct dentry *root; 579 unsigned long last_add; 580 }; 581 582 struct mlx5_ib_gsi_qp; 583 584 struct mlx5_ib_port_resources { 585 struct mlx5_ib_resources *devr; 586 struct mlx5_ib_gsi_qp *gsi; 587 struct work_struct pkey_change_work; 588 }; 589 590 struct mlx5_ib_resources { 591 struct ib_cq *c0; 592 struct ib_xrcd *x0; 593 struct ib_xrcd *x1; 594 struct ib_pd *p0; 595 struct ib_srq *s0; 596 struct ib_srq *s1; 597 struct mlx5_ib_port_resources ports[2]; 598 /* Protects changes to the port resources */ 599 struct mutex mutex; 600 }; 601 602 struct mlx5_ib_port { 603 u16 q_cnt_id; 604 }; 605 606 struct mlx5_roce { 607 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 608 * netdev pointer 609 */ 610 rwlock_t netdev_lock; 611 struct net_device *netdev; 612 struct notifier_block nb; 613 atomic_t next_port; 614 }; 615 616 struct mlx5_ib_dev { 617 struct ib_device ib_dev; 618 struct mlx5_core_dev *mdev; 619 struct mlx5_roce roce; 620 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 621 int num_ports; 622 /* serialize update of capability mask 623 */ 624 struct mutex cap_mask_mutex; 625 bool ib_active; 626 struct umr_common umrc; 627 /* sync used page count stats 628 */ 629 struct mlx5_ib_resources devr; 630 struct mlx5_mr_cache cache; 631 struct timer_list delay_timer; 632 /* Prevents soft lock on massive reg MRs */ 633 struct mutex slow_path_mutex; 634 int fill_delay; 635 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 636 struct ib_odp_caps odp_caps; 637 /* 638 * Sleepable RCU that prevents destruction of MRs while they are still 639 * being used by a page fault handler. 640 */ 641 struct srcu_struct mr_srcu; 642 #endif 643 struct mlx5_ib_flow_db flow_db; 644 /* protect resources needed as part of reset flow */ 645 spinlock_t reset_flow_resource_lock; 646 struct list_head qp_list; 647 /* Array with num_ports elements */ 648 struct mlx5_ib_port *port; 649 }; 650 651 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 652 { 653 return container_of(mcq, struct mlx5_ib_cq, mcq); 654 } 655 656 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 657 { 658 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 659 } 660 661 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 662 { 663 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 664 } 665 666 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 667 { 668 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 669 } 670 671 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 672 { 673 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 674 } 675 676 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 677 { 678 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 679 } 680 681 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 682 { 683 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 684 } 685 686 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 687 { 688 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 689 } 690 691 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 692 { 693 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 694 } 695 696 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 697 { 698 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 699 } 700 701 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 702 { 703 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 704 } 705 706 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 707 { 708 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 709 } 710 711 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 712 { 713 return container_of(msrq, struct mlx5_ib_srq, msrq); 714 } 715 716 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 717 { 718 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 719 } 720 721 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 722 { 723 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 724 } 725 726 struct mlx5_ib_ah { 727 struct ib_ah ibah; 728 struct mlx5_av av; 729 }; 730 731 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 732 { 733 return container_of(ibah, struct mlx5_ib_ah, ibah); 734 } 735 736 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 737 struct mlx5_db *db); 738 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 739 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 740 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 741 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 742 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 743 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 744 const void *in_mad, void *response_mad); 745 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr, 746 struct ib_udata *udata); 747 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 748 int mlx5_ib_destroy_ah(struct ib_ah *ah); 749 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 750 struct ib_srq_init_attr *init_attr, 751 struct ib_udata *udata); 752 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 753 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 754 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 755 int mlx5_ib_destroy_srq(struct ib_srq *srq); 756 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 757 struct ib_recv_wr **bad_wr); 758 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 759 struct ib_qp_init_attr *init_attr, 760 struct ib_udata *udata); 761 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 762 int attr_mask, struct ib_udata *udata); 763 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 764 struct ib_qp_init_attr *qp_init_attr); 765 int mlx5_ib_destroy_qp(struct ib_qp *qp); 766 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 767 struct ib_send_wr **bad_wr); 768 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 769 struct ib_recv_wr **bad_wr); 770 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 771 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 772 void *buffer, u32 length, 773 struct mlx5_ib_qp_base *base); 774 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 775 const struct ib_cq_init_attr *attr, 776 struct ib_ucontext *context, 777 struct ib_udata *udata); 778 int mlx5_ib_destroy_cq(struct ib_cq *cq); 779 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 780 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 781 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 782 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 783 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 784 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 785 u64 virt_addr, int access_flags, 786 struct ib_udata *udata); 787 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 788 struct ib_udata *udata); 789 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 790 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 791 int npages, int zap); 792 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 793 u64 length, u64 virt_addr, int access_flags, 794 struct ib_pd *pd, struct ib_udata *udata); 795 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 796 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 797 enum ib_mr_type mr_type, 798 u32 max_num_sg); 799 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 800 unsigned int *sg_offset); 801 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 802 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 803 const struct ib_mad_hdr *in, size_t in_mad_size, 804 struct ib_mad_hdr *out, size_t *out_mad_size, 805 u16 *out_mad_pkey_index); 806 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 807 struct ib_ucontext *context, 808 struct ib_udata *udata); 809 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 810 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 811 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 812 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 813 struct ib_smp *out_mad); 814 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 815 __be64 *sys_image_guid); 816 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 817 u16 *max_pkeys); 818 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 819 u32 *vendor_id); 820 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 821 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 822 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 823 u16 *pkey); 824 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 825 union ib_gid *gid); 826 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 827 struct ib_port_attr *props); 828 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 829 struct ib_port_attr *props); 830 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 831 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 832 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 833 unsigned long max_page_shift, 834 int *count, int *shift, 835 int *ncont, int *order); 836 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 837 int page_shift, size_t offset, size_t num_pages, 838 __be64 *pas, int access_flags); 839 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 840 int page_shift, __be64 *pas, int access_flags); 841 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 842 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 843 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 844 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 845 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 846 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 847 struct ib_mr_status *mr_status); 848 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 849 struct ib_wq_init_attr *init_attr, 850 struct ib_udata *udata); 851 int mlx5_ib_destroy_wq(struct ib_wq *wq); 852 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 853 u32 wq_attr_mask, struct ib_udata *udata); 854 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 855 struct ib_rwq_ind_table_init_attr *init_attr, 856 struct ib_udata *udata); 857 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 858 859 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 860 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 861 862 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 863 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 864 struct mlx5_ib_pfault *pfault); 865 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 866 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 867 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 868 int __init mlx5_ib_odp_init(void); 869 void mlx5_ib_odp_cleanup(void); 870 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 871 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 872 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 873 unsigned long end); 874 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 875 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 876 { 877 return; 878 } 879 880 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 881 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 882 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 883 static inline int mlx5_ib_odp_init(void) { return 0; } 884 static inline void mlx5_ib_odp_cleanup(void) {} 885 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 886 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 887 888 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 889 890 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 891 u8 port, struct ifla_vf_info *info); 892 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 893 u8 port, int state); 894 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 895 u8 port, struct ifla_vf_stats *stats); 896 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 897 u64 guid, int type); 898 899 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 900 int index); 901 902 /* GSI QP helper functions */ 903 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 904 struct ib_qp_init_attr *init_attr); 905 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 906 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 907 int attr_mask); 908 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 909 int qp_attr_mask, 910 struct ib_qp_init_attr *qp_init_attr); 911 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 912 struct ib_send_wr **bad_wr); 913 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 914 struct ib_recv_wr **bad_wr); 915 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 916 917 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 918 919 static inline void init_query_mad(struct ib_smp *mad) 920 { 921 mad->base_version = 1; 922 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 923 mad->class_version = 1; 924 mad->method = IB_MGMT_METHOD_GET; 925 } 926 927 static inline u8 convert_access(int acc) 928 { 929 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 930 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 931 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 932 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 933 MLX5_PERM_LOCAL_READ; 934 } 935 936 static inline int is_qp1(enum ib_qp_type qp_type) 937 { 938 return qp_type == MLX5_IB_QPT_HW_GSI; 939 } 940 941 #define MLX5_MAX_UMR_SHIFT 16 942 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 943 944 static inline u32 check_cq_create_flags(u32 flags) 945 { 946 /* 947 * It returns non-zero value for unsupported CQ 948 * create flags, otherwise it returns zero. 949 */ 950 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 951 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 952 } 953 954 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 955 u32 *user_index) 956 { 957 if (cqe_version) { 958 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 959 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 960 return -EINVAL; 961 *user_index = cmd_uidx; 962 } else { 963 *user_index = MLX5_IB_DEFAULT_UIDX; 964 } 965 966 return 0; 967 } 968 969 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 970 struct mlx5_ib_create_qp *ucmd, 971 int inlen, 972 u32 *user_index) 973 { 974 u8 cqe_version = ucontext->cqe_version; 975 976 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 977 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 978 return 0; 979 980 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 981 !!cqe_version)) 982 return -EINVAL; 983 984 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 985 } 986 987 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 988 struct mlx5_ib_create_srq *ucmd, 989 int inlen, 990 u32 *user_index) 991 { 992 u8 cqe_version = ucontext->cqe_version; 993 994 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 995 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 996 return 0; 997 998 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 999 !!cqe_version)) 1000 return -EINVAL; 1001 1002 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1003 } 1004 #endif /* MLX5_IB_H */ 1005