1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_umem.h> 40 #include <rdma/ib_smi.h> 41 #include <linux/mlx5/driver.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/fs.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/types.h> 46 #include <linux/mlx5/transobj.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/mlx5-abi.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/mlx5_user_ioctl_verbs.h> 52 53 #include "srq.h" 54 55 #define mlx5_ib_dbg(_dev, format, arg...) \ 56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 57 __LINE__, current->pid, ##arg) 58 59 #define mlx5_ib_err(_dev, format, arg...) \ 60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 61 __LINE__, current->pid, ##arg) 62 63 #define mlx5_ib_warn(_dev, format, arg...) \ 64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 65 __LINE__, current->pid, ##arg) 66 67 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 68 sizeof(((type *)0)->fld) <= (sz)) 69 #define MLX5_IB_DEFAULT_UIDX 0xffffff 70 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 71 72 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 73 74 enum { 75 MLX5_IB_MMAP_OFFSET_START = 9, 76 MLX5_IB_MMAP_OFFSET_END = 255, 77 }; 78 79 enum { 80 MLX5_IB_MMAP_CMD_SHIFT = 8, 81 MLX5_IB_MMAP_CMD_MASK = 0xff, 82 }; 83 84 enum { 85 MLX5_RES_SCAT_DATA32_CQE = 0x1, 86 MLX5_RES_SCAT_DATA64_CQE = 0x2, 87 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 88 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 89 }; 90 91 enum mlx5_ib_mad_ifc_flags { 92 MLX5_MAD_IFC_IGNORE_MKEY = 1, 93 MLX5_MAD_IFC_IGNORE_BKEY = 2, 94 MLX5_MAD_IFC_NET_VIEW = 4, 95 }; 96 97 enum { 98 MLX5_CROSS_CHANNEL_BFREG = 0, 99 }; 100 101 enum { 102 MLX5_CQE_VERSION_V0, 103 MLX5_CQE_VERSION_V1, 104 }; 105 106 enum { 107 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 108 MLX5_TM_MAX_SGE = 1, 109 }; 110 111 enum { 112 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 113 MLX5_IB_INVALID_BFREG = BIT(31), 114 }; 115 116 enum { 117 MLX5_MAX_MEMIC_PAGES = 0x100, 118 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 119 }; 120 121 enum { 122 MLX5_MEMIC_BASE_ALIGN = 6, 123 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 124 }; 125 126 enum mlx5_ib_mmap_type { 127 MLX5_IB_MMAP_TYPE_MEMIC = 1, 128 MLX5_IB_MMAP_TYPE_VAR = 2, 129 }; 130 131 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) \ 132 (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) 133 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) 134 135 struct mlx5_ib_ucontext { 136 struct ib_ucontext ibucontext; 137 struct list_head db_page_list; 138 139 /* protect doorbell record alloc/free 140 */ 141 struct mutex db_page_mutex; 142 struct mlx5_bfreg_info bfregi; 143 u8 cqe_version; 144 /* Transport Domain number */ 145 u32 tdn; 146 147 u64 lib_caps; 148 u16 devx_uid; 149 /* For RoCE LAG TX affinity */ 150 atomic_t tx_port_affinity; 151 }; 152 153 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 154 { 155 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 156 } 157 158 struct mlx5_ib_pd { 159 struct ib_pd ibpd; 160 u32 pdn; 161 u16 uid; 162 }; 163 164 enum { 165 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 166 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 167 MLX5_IB_FLOW_ACTION_DECAP, 168 }; 169 170 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 171 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 172 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 173 #error "Invalid number of bypass priorities" 174 #endif 175 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 176 177 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 178 #define MLX5_IB_NUM_SNIFFER_FTS 2 179 #define MLX5_IB_NUM_EGRESS_FTS 1 180 struct mlx5_ib_flow_prio { 181 struct mlx5_flow_table *flow_table; 182 unsigned int refcount; 183 }; 184 185 struct mlx5_ib_flow_handler { 186 struct list_head list; 187 struct ib_flow ibflow; 188 struct mlx5_ib_flow_prio *prio; 189 struct mlx5_flow_handle *rule; 190 struct ib_counters *ibcounters; 191 struct mlx5_ib_dev *dev; 192 struct mlx5_ib_flow_matcher *flow_matcher; 193 }; 194 195 struct mlx5_ib_flow_matcher { 196 struct mlx5_ib_match_params matcher_mask; 197 int mask_len; 198 enum mlx5_ib_flow_type flow_type; 199 enum mlx5_flow_namespace_type ns_type; 200 u16 priority; 201 struct mlx5_core_dev *mdev; 202 atomic_t usecnt; 203 u8 match_criteria_enable; 204 }; 205 206 struct mlx5_ib_flow_db { 207 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 208 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 209 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 210 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 211 struct mlx5_ib_flow_prio fdb; 212 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 213 struct mlx5_flow_table *lag_demux_ft; 214 /* Protect flow steering bypass flow tables 215 * when add/del flow rules. 216 * only single add/removal of flow steering rule could be done 217 * simultaneously. 218 */ 219 struct mutex lock; 220 }; 221 222 /* Use macros here so that don't have to duplicate 223 * enum ib_send_flags and enum ib_qp_type for low-level driver 224 */ 225 226 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 227 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 228 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 229 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 230 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 231 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 232 233 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 234 /* 235 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 236 * creates the actual hardware QP. 237 */ 238 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 239 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 240 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 241 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 242 243 #define MLX5_IB_UMR_OCTOWORD 16 244 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 245 246 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 247 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 248 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 249 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 250 #define MLX5_IB_UPD_XLT_PD BIT(4) 251 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 252 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 253 254 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 255 * 256 * These flags are intended for internal use by the mlx5_ib driver, and they 257 * rely on the range reserved for that use in the ib_qp_create_flags enum. 258 */ 259 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 260 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 261 262 struct wr_list { 263 u16 opcode; 264 u16 next; 265 }; 266 267 enum mlx5_ib_rq_flags { 268 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 269 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 270 }; 271 272 struct mlx5_ib_wq { 273 struct mlx5_frag_buf_ctrl fbc; 274 u64 *wrid; 275 u32 *wr_data; 276 struct wr_list *w_list; 277 unsigned *wqe_head; 278 u16 unsig_count; 279 280 /* serialize post to the work queue 281 */ 282 spinlock_t lock; 283 int wqe_cnt; 284 int max_post; 285 int max_gs; 286 int offset; 287 int wqe_shift; 288 unsigned head; 289 unsigned tail; 290 u16 cur_post; 291 void *cur_edge; 292 }; 293 294 enum mlx5_ib_wq_flags { 295 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 296 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 297 }; 298 299 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 300 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 301 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 302 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 303 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 304 305 struct mlx5_ib_rwq { 306 struct ib_wq ibwq; 307 struct mlx5_core_qp core_qp; 308 u32 rq_num_pas; 309 u32 log_rq_stride; 310 u32 log_rq_size; 311 u32 rq_page_offset; 312 u32 log_page_size; 313 u32 log_num_strides; 314 u32 two_byte_shift_en; 315 u32 single_stride_log_num_of_bytes; 316 struct ib_umem *umem; 317 size_t buf_size; 318 unsigned int page_shift; 319 int create_type; 320 struct mlx5_db db; 321 u32 user_index; 322 u32 wqe_count; 323 u32 wqe_shift; 324 int wq_sig; 325 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 326 }; 327 328 enum { 329 MLX5_QP_USER, 330 MLX5_QP_KERNEL, 331 MLX5_QP_EMPTY 332 }; 333 334 enum { 335 MLX5_WQ_USER, 336 MLX5_WQ_KERNEL 337 }; 338 339 struct mlx5_ib_rwq_ind_table { 340 struct ib_rwq_ind_table ib_rwq_ind_tbl; 341 u32 rqtn; 342 u16 uid; 343 }; 344 345 struct mlx5_ib_ubuffer { 346 struct ib_umem *umem; 347 int buf_size; 348 u64 buf_addr; 349 }; 350 351 struct mlx5_ib_qp_base { 352 struct mlx5_ib_qp *container_mibqp; 353 struct mlx5_core_qp mqp; 354 struct mlx5_ib_ubuffer ubuffer; 355 }; 356 357 struct mlx5_ib_qp_trans { 358 struct mlx5_ib_qp_base base; 359 u16 xrcdn; 360 u8 alt_port; 361 u8 atomic_rd_en; 362 u8 resp_depth; 363 }; 364 365 struct mlx5_ib_rss_qp { 366 u32 tirn; 367 }; 368 369 struct mlx5_ib_rq { 370 struct mlx5_ib_qp_base base; 371 struct mlx5_ib_wq *rq; 372 struct mlx5_ib_ubuffer ubuffer; 373 struct mlx5_db *doorbell; 374 u32 tirn; 375 u8 state; 376 u32 flags; 377 }; 378 379 struct mlx5_ib_sq { 380 struct mlx5_ib_qp_base base; 381 struct mlx5_ib_wq *sq; 382 struct mlx5_ib_ubuffer ubuffer; 383 struct mlx5_db *doorbell; 384 struct mlx5_flow_handle *flow_rule; 385 u32 tisn; 386 u8 state; 387 }; 388 389 struct mlx5_ib_raw_packet_qp { 390 struct mlx5_ib_sq sq; 391 struct mlx5_ib_rq rq; 392 }; 393 394 struct mlx5_bf { 395 int buf_size; 396 unsigned long offset; 397 struct mlx5_sq_bfreg *bfreg; 398 }; 399 400 struct mlx5_ib_dct { 401 struct mlx5_core_dct mdct; 402 u32 *in; 403 }; 404 405 struct mlx5_ib_qp { 406 struct ib_qp ibqp; 407 union { 408 struct mlx5_ib_qp_trans trans_qp; 409 struct mlx5_ib_raw_packet_qp raw_packet_qp; 410 struct mlx5_ib_rss_qp rss_qp; 411 struct mlx5_ib_dct dct; 412 }; 413 struct mlx5_frag_buf buf; 414 415 struct mlx5_db db; 416 struct mlx5_ib_wq rq; 417 418 u8 sq_signal_bits; 419 u8 next_fence; 420 struct mlx5_ib_wq sq; 421 422 /* serialize qp state modifications 423 */ 424 struct mutex mutex; 425 u32 flags; 426 u8 port; 427 u8 state; 428 int wq_sig; 429 int scat_cqe; 430 int max_inline_data; 431 struct mlx5_bf bf; 432 int has_rq; 433 434 /* only for user space QPs. For kernel 435 * we have it from the bf object 436 */ 437 int bfregn; 438 439 int create_type; 440 441 struct list_head qps_list; 442 struct list_head cq_recv_list; 443 struct list_head cq_send_list; 444 struct mlx5_rate_limit rl; 445 u32 underlay_qpn; 446 u32 flags_en; 447 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 448 enum ib_qp_type qp_sub_type; 449 /* A flag to indicate if there's a new counter is configured 450 * but not take effective 451 */ 452 u32 counter_pending; 453 }; 454 455 struct mlx5_ib_cq_buf { 456 struct mlx5_frag_buf_ctrl fbc; 457 struct mlx5_frag_buf frag_buf; 458 struct ib_umem *umem; 459 int cqe_size; 460 int nent; 461 }; 462 463 enum mlx5_ib_qp_flags { 464 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 465 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 466 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 467 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 468 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 469 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 470 /* QP uses 1 as its source QP number */ 471 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 472 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 473 MLX5_IB_QP_RSS = 1 << 8, 474 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 475 MLX5_IB_QP_UNDERLAY = 1 << 10, 476 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 477 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 478 MLX5_IB_QP_PACKET_BASED_CREDIT = 1 << 13, 479 }; 480 481 struct mlx5_umr_wr { 482 struct ib_send_wr wr; 483 u64 virt_addr; 484 u64 offset; 485 struct ib_pd *pd; 486 unsigned int page_shift; 487 unsigned int xlt_size; 488 u64 length; 489 int access_flags; 490 u32 mkey; 491 u8 ignore_free_state:1; 492 }; 493 494 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 495 { 496 return container_of(wr, struct mlx5_umr_wr, wr); 497 } 498 499 struct mlx5_shared_mr_info { 500 int mr_id; 501 struct ib_umem *umem; 502 }; 503 504 enum mlx5_ib_cq_pr_flags { 505 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 506 }; 507 508 struct mlx5_ib_cq { 509 struct ib_cq ibcq; 510 struct mlx5_core_cq mcq; 511 struct mlx5_ib_cq_buf buf; 512 struct mlx5_db db; 513 514 /* serialize access to the CQ 515 */ 516 spinlock_t lock; 517 518 /* protect resize cq 519 */ 520 struct mutex resize_mutex; 521 struct mlx5_ib_cq_buf *resize_buf; 522 struct ib_umem *resize_umem; 523 int cqe_size; 524 struct list_head list_send_qp; 525 struct list_head list_recv_qp; 526 u32 create_flags; 527 struct list_head wc_list; 528 enum ib_cq_notify_flags notify_flags; 529 struct work_struct notify_work; 530 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 531 }; 532 533 struct mlx5_ib_wc { 534 struct ib_wc wc; 535 struct list_head list; 536 }; 537 538 struct mlx5_ib_srq { 539 struct ib_srq ibsrq; 540 struct mlx5_core_srq msrq; 541 struct mlx5_frag_buf buf; 542 struct mlx5_db db; 543 struct mlx5_frag_buf_ctrl fbc; 544 u64 *wrid; 545 /* protect SRQ hanlding 546 */ 547 spinlock_t lock; 548 int head; 549 int tail; 550 u16 wqe_ctr; 551 struct ib_umem *umem; 552 /* serialize arming a SRQ 553 */ 554 struct mutex mutex; 555 int wq_sig; 556 }; 557 558 struct mlx5_ib_xrcd { 559 struct ib_xrcd ibxrcd; 560 u32 xrcdn; 561 }; 562 563 enum mlx5_ib_mtt_access_flags { 564 MLX5_IB_MTT_READ = (1 << 0), 565 MLX5_IB_MTT_WRITE = (1 << 1), 566 }; 567 568 struct mlx5_user_mmap_entry { 569 struct rdma_user_mmap_entry rdma_entry; 570 u8 mmap_flag; 571 u64 address; 572 u32 page_idx; 573 }; 574 575 struct mlx5_ib_dm { 576 struct ib_dm ibdm; 577 phys_addr_t dev_addr; 578 u32 type; 579 size_t size; 580 union { 581 struct { 582 u32 obj_id; 583 } icm_dm; 584 /* other dm types specific params should be added here */ 585 }; 586 struct mlx5_user_mmap_entry mentry; 587 }; 588 589 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 590 591 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 592 IB_ACCESS_REMOTE_WRITE |\ 593 IB_ACCESS_REMOTE_READ |\ 594 IB_ACCESS_REMOTE_ATOMIC |\ 595 IB_ZERO_BASED) 596 597 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 598 IB_ACCESS_REMOTE_WRITE |\ 599 IB_ACCESS_REMOTE_READ |\ 600 IB_ZERO_BASED) 601 602 #define mlx5_update_odp_stats(mr, counter_name, value) \ 603 atomic64_add(value, &((mr)->odp_stats.counter_name)) 604 605 struct mlx5_ib_mr { 606 struct ib_mr ibmr; 607 void *descs; 608 dma_addr_t desc_map; 609 int ndescs; 610 int data_length; 611 int meta_ndescs; 612 int meta_length; 613 int max_descs; 614 int desc_size; 615 int access_mode; 616 struct mlx5_core_mkey mmkey; 617 struct ib_umem *umem; 618 struct mlx5_shared_mr_info *smr_info; 619 struct list_head list; 620 int order; 621 bool allocated_from_cache; 622 int npages; 623 struct mlx5_ib_dev *dev; 624 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 625 struct mlx5_core_sig_ctx *sig; 626 void *descs_alloc; 627 int access_flags; /* Needed for rereg MR */ 628 629 struct mlx5_ib_mr *parent; 630 /* Needed for IB_MR_TYPE_INTEGRITY */ 631 struct mlx5_ib_mr *pi_mr; 632 struct mlx5_ib_mr *klm_mr; 633 struct mlx5_ib_mr *mtt_mr; 634 u64 data_iova; 635 u64 pi_iova; 636 637 /* For ODP and implicit */ 638 atomic_t num_deferred_work; 639 struct xarray implicit_children; 640 union { 641 struct rcu_head rcu; 642 struct list_head elm; 643 struct work_struct work; 644 } odp_destroy; 645 struct ib_odp_counters odp_stats; 646 bool is_odp_implicit; 647 648 struct mlx5_async_work cb_work; 649 }; 650 651 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 652 { 653 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 654 mr->umem->is_odp; 655 } 656 657 struct mlx5_ib_mw { 658 struct ib_mw ibmw; 659 struct mlx5_core_mkey mmkey; 660 int ndescs; 661 }; 662 663 struct mlx5_ib_devx_mr { 664 struct mlx5_core_mkey mmkey; 665 int ndescs; 666 }; 667 668 struct mlx5_ib_umr_context { 669 struct ib_cqe cqe; 670 enum ib_wc_status status; 671 struct completion done; 672 }; 673 674 struct umr_common { 675 struct ib_pd *pd; 676 struct ib_cq *cq; 677 struct ib_qp *qp; 678 /* control access to UMR QP 679 */ 680 struct semaphore sem; 681 }; 682 683 enum { 684 MLX5_FMR_INVALID, 685 MLX5_FMR_VALID, 686 MLX5_FMR_BUSY, 687 }; 688 689 struct mlx5_cache_ent { 690 struct list_head head; 691 /* sync access to the cahce entry 692 */ 693 spinlock_t lock; 694 695 696 char name[4]; 697 u32 order; 698 u32 xlt; 699 u32 access_mode; 700 u32 page; 701 702 u32 size; 703 u32 cur; 704 u32 miss; 705 u32 limit; 706 707 struct mlx5_ib_dev *dev; 708 struct work_struct work; 709 struct delayed_work dwork; 710 int pending; 711 struct completion compl; 712 }; 713 714 struct mlx5_mr_cache { 715 struct workqueue_struct *wq; 716 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 717 int stopped; 718 struct dentry *root; 719 unsigned long last_add; 720 }; 721 722 struct mlx5_ib_gsi_qp; 723 724 struct mlx5_ib_port_resources { 725 struct mlx5_ib_resources *devr; 726 struct mlx5_ib_gsi_qp *gsi; 727 struct work_struct pkey_change_work; 728 }; 729 730 struct mlx5_ib_resources { 731 struct ib_cq *c0; 732 struct ib_xrcd *x0; 733 struct ib_xrcd *x1; 734 struct ib_pd *p0; 735 struct ib_srq *s0; 736 struct ib_srq *s1; 737 struct mlx5_ib_port_resources ports[2]; 738 /* Protects changes to the port resources */ 739 struct mutex mutex; 740 }; 741 742 struct mlx5_ib_counters { 743 const char **names; 744 size_t *offsets; 745 u32 num_q_counters; 746 u32 num_cong_counters; 747 u32 num_ext_ppcnt_counters; 748 u16 set_id; 749 bool set_id_valid; 750 }; 751 752 struct mlx5_ib_multiport_info; 753 754 struct mlx5_ib_multiport { 755 struct mlx5_ib_multiport_info *mpi; 756 /* To be held when accessing the multiport info */ 757 spinlock_t mpi_lock; 758 }; 759 760 struct mlx5_roce { 761 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 762 * netdev pointer 763 */ 764 rwlock_t netdev_lock; 765 struct net_device *netdev; 766 struct notifier_block nb; 767 atomic_t tx_port_affinity; 768 enum ib_port_state last_port_state; 769 struct mlx5_ib_dev *dev; 770 u8 native_port_num; 771 }; 772 773 struct mlx5_ib_port { 774 struct mlx5_ib_counters cnts; 775 struct mlx5_ib_multiport mp; 776 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 777 struct mlx5_roce roce; 778 struct mlx5_eswitch_rep *rep; 779 }; 780 781 struct mlx5_ib_dbg_param { 782 int offset; 783 struct mlx5_ib_dev *dev; 784 struct dentry *dentry; 785 u8 port_num; 786 }; 787 788 enum mlx5_ib_dbg_cc_types { 789 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 790 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 791 MLX5_IB_DBG_CC_RP_TIME_RESET, 792 MLX5_IB_DBG_CC_RP_BYTE_RESET, 793 MLX5_IB_DBG_CC_RP_THRESHOLD, 794 MLX5_IB_DBG_CC_RP_AI_RATE, 795 MLX5_IB_DBG_CC_RP_HAI_RATE, 796 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 797 MLX5_IB_DBG_CC_RP_MIN_RATE, 798 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 799 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 800 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 801 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 802 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 803 MLX5_IB_DBG_CC_RP_GD, 804 MLX5_IB_DBG_CC_NP_CNP_DSCP, 805 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 806 MLX5_IB_DBG_CC_NP_CNP_PRIO, 807 MLX5_IB_DBG_CC_MAX, 808 }; 809 810 struct mlx5_ib_dbg_cc_params { 811 struct dentry *root; 812 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 813 }; 814 815 enum { 816 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 817 }; 818 819 struct mlx5_ib_delay_drop { 820 struct mlx5_ib_dev *dev; 821 struct work_struct delay_drop_work; 822 /* serialize setting of delay drop */ 823 struct mutex lock; 824 u32 timeout; 825 bool activate; 826 atomic_t events_cnt; 827 atomic_t rqs_cnt; 828 struct dentry *dir_debugfs; 829 }; 830 831 enum mlx5_ib_stages { 832 MLX5_IB_STAGE_INIT, 833 MLX5_IB_STAGE_FLOW_DB, 834 MLX5_IB_STAGE_CAPS, 835 MLX5_IB_STAGE_NON_DEFAULT_CB, 836 MLX5_IB_STAGE_ROCE, 837 MLX5_IB_STAGE_SRQ, 838 MLX5_IB_STAGE_DEVICE_RESOURCES, 839 MLX5_IB_STAGE_DEVICE_NOTIFIER, 840 MLX5_IB_STAGE_ODP, 841 MLX5_IB_STAGE_COUNTERS, 842 MLX5_IB_STAGE_CONG_DEBUGFS, 843 MLX5_IB_STAGE_UAR, 844 MLX5_IB_STAGE_BFREG, 845 MLX5_IB_STAGE_PRE_IB_REG_UMR, 846 MLX5_IB_STAGE_WHITELIST_UID, 847 MLX5_IB_STAGE_IB_REG, 848 MLX5_IB_STAGE_POST_IB_REG_UMR, 849 MLX5_IB_STAGE_DELAY_DROP, 850 MLX5_IB_STAGE_CLASS_ATTR, 851 MLX5_IB_STAGE_MAX, 852 }; 853 854 struct mlx5_ib_stage { 855 int (*init)(struct mlx5_ib_dev *dev); 856 void (*cleanup)(struct mlx5_ib_dev *dev); 857 }; 858 859 #define STAGE_CREATE(_stage, _init, _cleanup) \ 860 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 861 862 struct mlx5_ib_profile { 863 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 864 }; 865 866 struct mlx5_ib_multiport_info { 867 struct list_head list; 868 struct mlx5_ib_dev *ibdev; 869 struct mlx5_core_dev *mdev; 870 struct notifier_block mdev_events; 871 struct completion unref_comp; 872 u64 sys_image_guid; 873 u32 mdev_refcnt; 874 bool is_master; 875 bool unaffiliate; 876 }; 877 878 struct mlx5_ib_flow_action { 879 struct ib_flow_action ib_action; 880 union { 881 struct { 882 u64 ib_flags; 883 struct mlx5_accel_esp_xfrm *ctx; 884 } esp_aes_gcm; 885 struct { 886 struct mlx5_ib_dev *dev; 887 u32 sub_type; 888 union { 889 struct mlx5_modify_hdr *modify_hdr; 890 struct mlx5_pkt_reformat *pkt_reformat; 891 }; 892 } flow_action_raw; 893 }; 894 }; 895 896 struct mlx5_dm { 897 struct mlx5_core_dev *dev; 898 /* This lock is used to protect the access to the shared 899 * allocation map when concurrent requests by different 900 * processes are handled. 901 */ 902 spinlock_t lock; 903 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 904 }; 905 906 struct mlx5_read_counters_attr { 907 struct mlx5_fc *hw_cntrs_hndl; 908 u64 *out; 909 u32 flags; 910 }; 911 912 enum mlx5_ib_counters_type { 913 MLX5_IB_COUNTERS_FLOW, 914 }; 915 916 struct mlx5_ib_mcounters { 917 struct ib_counters ibcntrs; 918 enum mlx5_ib_counters_type type; 919 /* number of counters supported for this counters type */ 920 u32 counters_num; 921 struct mlx5_fc *hw_cntrs_hndl; 922 /* read function for this counters type */ 923 int (*read_counters)(struct ib_device *ibdev, 924 struct mlx5_read_counters_attr *read_attr); 925 /* max index set as part of create_flow */ 926 u32 cntrs_max_index; 927 /* number of counters data entries (<description,index> pair) */ 928 u32 ncounters; 929 /* counters data array for descriptions and indexes */ 930 struct mlx5_ib_flow_counters_desc *counters_data; 931 /* protects access to mcounters internal data */ 932 struct mutex mcntrs_mutex; 933 }; 934 935 static inline struct mlx5_ib_mcounters * 936 to_mcounters(struct ib_counters *ibcntrs) 937 { 938 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 939 } 940 941 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 942 bool is_egress, 943 struct mlx5_flow_act *action); 944 struct mlx5_ib_lb_state { 945 /* protect the user_td */ 946 struct mutex mutex; 947 u32 user_td; 948 int qps; 949 bool enabled; 950 }; 951 952 struct mlx5_ib_pf_eq { 953 struct notifier_block irq_nb; 954 struct mlx5_ib_dev *dev; 955 struct mlx5_eq *core; 956 struct work_struct work; 957 spinlock_t lock; /* Pagefaults spinlock */ 958 struct workqueue_struct *wq; 959 mempool_t *pool; 960 }; 961 962 struct mlx5_devx_event_table { 963 struct mlx5_nb devx_nb; 964 /* serialize updating the event_xa */ 965 struct mutex event_xa_lock; 966 struct xarray event_xa; 967 }; 968 969 struct mlx5_var_table { 970 /* serialize updating the bitmap */ 971 struct mutex bitmap_lock; 972 unsigned long *bitmap; 973 u64 hw_start_addr; 974 u32 stride_size; 975 u64 num_var_hw_entries; 976 }; 977 978 struct mlx5_ib_dev { 979 struct ib_device ib_dev; 980 struct mlx5_core_dev *mdev; 981 struct notifier_block mdev_events; 982 int num_ports; 983 /* serialize update of capability mask 984 */ 985 struct mutex cap_mask_mutex; 986 u8 ib_active:1; 987 u8 fill_delay:1; 988 u8 is_rep:1; 989 u8 lag_active:1; 990 u8 wc_support:1; 991 struct umr_common umrc; 992 /* sync used page count stats 993 */ 994 struct mlx5_ib_resources devr; 995 struct mlx5_mr_cache cache; 996 struct timer_list delay_timer; 997 /* Prevents soft lock on massive reg MRs */ 998 struct mutex slow_path_mutex; 999 struct ib_odp_caps odp_caps; 1000 u64 odp_max_size; 1001 struct mlx5_ib_pf_eq odp_pf_eq; 1002 1003 /* 1004 * Sleepable RCU that prevents destruction of MRs while they are still 1005 * being used by a page fault handler. 1006 */ 1007 struct srcu_struct odp_srcu; 1008 struct xarray odp_mkeys; 1009 1010 u32 null_mkey; 1011 struct mlx5_ib_flow_db *flow_db; 1012 /* protect resources needed as part of reset flow */ 1013 spinlock_t reset_flow_resource_lock; 1014 struct list_head qp_list; 1015 /* Array with num_ports elements */ 1016 struct mlx5_ib_port *port; 1017 struct mlx5_sq_bfreg bfreg; 1018 struct mlx5_sq_bfreg wc_bfreg; 1019 struct mlx5_sq_bfreg fp_bfreg; 1020 struct mlx5_ib_delay_drop delay_drop; 1021 const struct mlx5_ib_profile *profile; 1022 1023 struct mlx5_ib_lb_state lb; 1024 u8 umr_fence; 1025 struct list_head ib_dev_list; 1026 u64 sys_image_guid; 1027 struct mlx5_dm dm; 1028 u16 devx_whitelist_uid; 1029 struct mlx5_srq_table srq_table; 1030 struct mlx5_async_ctx async_ctx; 1031 struct mlx5_devx_event_table devx_event_table; 1032 struct mlx5_var_table var_table; 1033 1034 struct xarray sig_mrs; 1035 }; 1036 1037 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1038 { 1039 return container_of(mcq, struct mlx5_ib_cq, mcq); 1040 } 1041 1042 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1043 { 1044 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1045 } 1046 1047 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1048 { 1049 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1050 } 1051 1052 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1053 { 1054 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1055 udata, struct mlx5_ib_ucontext, ibucontext); 1056 1057 return to_mdev(context->ibucontext.device); 1058 } 1059 1060 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1061 { 1062 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1063 } 1064 1065 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1066 { 1067 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1068 } 1069 1070 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1071 { 1072 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1073 } 1074 1075 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 1076 { 1077 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 1078 } 1079 1080 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1081 { 1082 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1083 } 1084 1085 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1086 { 1087 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1088 } 1089 1090 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1091 { 1092 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1093 } 1094 1095 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1096 { 1097 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1098 } 1099 1100 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1101 { 1102 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1103 } 1104 1105 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1106 { 1107 return container_of(msrq, struct mlx5_ib_srq, msrq); 1108 } 1109 1110 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1111 { 1112 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1113 } 1114 1115 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1116 { 1117 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1118 } 1119 1120 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1121 { 1122 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1123 } 1124 1125 static inline struct mlx5_ib_flow_action * 1126 to_mflow_act(struct ib_flow_action *ibact) 1127 { 1128 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1129 } 1130 1131 static inline struct mlx5_user_mmap_entry * 1132 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1133 { 1134 return container_of(rdma_entry, 1135 struct mlx5_user_mmap_entry, rdma_entry); 1136 } 1137 1138 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, 1139 struct ib_udata *udata, unsigned long virt, 1140 struct mlx5_db *db); 1141 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1142 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1143 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1144 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1145 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags, 1146 struct ib_udata *udata); 1147 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1148 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags); 1149 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1150 struct ib_udata *udata); 1151 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1152 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1153 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1154 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1155 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1156 const struct ib_recv_wr **bad_wr); 1157 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1158 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1159 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1160 struct ib_qp_init_attr *init_attr, 1161 struct ib_udata *udata); 1162 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1163 int attr_mask, struct ib_udata *udata); 1164 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1165 struct ib_qp_init_attr *qp_init_attr); 1166 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1167 void mlx5_ib_drain_sq(struct ib_qp *qp); 1168 void mlx5_ib_drain_rq(struct ib_qp *qp); 1169 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1170 const struct ib_send_wr **bad_wr); 1171 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1172 const struct ib_recv_wr **bad_wr); 1173 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1174 size_t buflen, size_t *bc); 1175 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1176 size_t buflen, size_t *bc); 1177 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1178 size_t buflen, size_t *bc); 1179 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1180 struct ib_udata *udata); 1181 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1182 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1183 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1184 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1185 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1186 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1187 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1188 u64 virt_addr, int access_flags, 1189 struct ib_udata *udata); 1190 int mlx5_ib_advise_mr(struct ib_pd *pd, 1191 enum ib_uverbs_advise_mr_advice advice, 1192 u32 flags, 1193 struct ib_sge *sg_list, 1194 u32 num_sge, 1195 struct uverbs_attr_bundle *attrs); 1196 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1197 struct ib_udata *udata); 1198 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1199 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1200 int page_shift, int flags); 1201 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1202 struct ib_udata *udata, 1203 int access_flags); 1204 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1205 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr); 1206 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1207 u64 length, u64 virt_addr, int access_flags, 1208 struct ib_pd *pd, struct ib_udata *udata); 1209 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1210 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1211 u32 max_num_sg, struct ib_udata *udata); 1212 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1213 u32 max_num_sg, 1214 u32 max_num_meta_sg); 1215 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1216 unsigned int *sg_offset); 1217 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1218 int data_sg_nents, unsigned int *data_sg_offset, 1219 struct scatterlist *meta_sg, int meta_sg_nents, 1220 unsigned int *meta_sg_offset); 1221 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1222 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1223 const struct ib_mad *in, struct ib_mad *out, 1224 size_t *out_mad_size, u16 *out_mad_pkey_index); 1225 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1226 struct ib_udata *udata); 1227 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1228 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1229 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1230 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1231 struct ib_smp *out_mad); 1232 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1233 __be64 *sys_image_guid); 1234 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1235 u16 *max_pkeys); 1236 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1237 u32 *vendor_id); 1238 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1239 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1240 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1241 u16 *pkey); 1242 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1243 union ib_gid *gid); 1244 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1245 struct ib_port_attr *props); 1246 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1247 struct ib_port_attr *props); 1248 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1249 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1250 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1251 unsigned long max_page_shift, 1252 int *count, int *shift, 1253 int *ncont, int *order); 1254 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1255 int page_shift, size_t offset, size_t num_pages, 1256 __be64 *pas, int access_flags); 1257 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1258 int page_shift, __be64 *pas, int access_flags); 1259 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1260 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1261 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1262 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1263 1264 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1265 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1266 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr); 1267 1268 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1269 struct ib_mr_status *mr_status); 1270 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1271 struct ib_wq_init_attr *init_attr, 1272 struct ib_udata *udata); 1273 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1274 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1275 u32 wq_attr_mask, struct ib_udata *udata); 1276 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1277 struct ib_rwq_ind_table_init_attr *init_attr, 1278 struct ib_udata *udata); 1279 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1280 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1281 struct ib_ucontext *context, 1282 struct ib_dm_alloc_attr *attr, 1283 struct uverbs_attr_bundle *attrs); 1284 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs); 1285 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1286 struct ib_dm_mr_attr *attr, 1287 struct uverbs_attr_bundle *attrs); 1288 1289 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1290 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1291 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1292 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1293 int __init mlx5_ib_odp_init(void); 1294 void mlx5_ib_odp_cleanup(void); 1295 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1296 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1297 struct mlx5_ib_mr *mr, int flags); 1298 1299 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1300 enum ib_uverbs_advise_mr_advice advice, 1301 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1302 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1303 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1304 { 1305 return; 1306 } 1307 1308 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1309 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1310 static inline int mlx5_ib_odp_init(void) { return 0; } 1311 static inline void mlx5_ib_odp_cleanup(void) {} 1312 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1313 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1314 struct mlx5_ib_mr *mr, int flags) {} 1315 1316 static inline int 1317 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1318 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1319 struct ib_sge *sg_list, u32 num_sge) 1320 { 1321 return -EOPNOTSUPP; 1322 } 1323 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1324 1325 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1326 1327 /* Needed for rep profile */ 1328 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1329 const struct mlx5_ib_profile *profile, 1330 int stage); 1331 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1332 const struct mlx5_ib_profile *profile); 1333 1334 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1335 u8 port, struct ifla_vf_info *info); 1336 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1337 u8 port, int state); 1338 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1339 u8 port, struct ifla_vf_stats *stats); 1340 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port, 1341 struct ifla_vf_guid *node_guid, 1342 struct ifla_vf_guid *port_guid); 1343 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1344 u64 guid, int type); 1345 1346 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 1347 const struct ib_gid_attr *attr); 1348 1349 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1350 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1351 1352 /* GSI QP helper functions */ 1353 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1354 struct ib_qp_init_attr *init_attr); 1355 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1356 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1357 int attr_mask); 1358 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1359 int qp_attr_mask, 1360 struct ib_qp_init_attr *qp_init_attr); 1361 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1362 const struct ib_send_wr **bad_wr); 1363 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1364 const struct ib_recv_wr **bad_wr); 1365 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1366 1367 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1368 1369 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1370 int bfregn); 1371 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1372 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1373 u8 ib_port_num, 1374 u8 *native_port_num); 1375 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1376 u8 port_num); 1377 int mlx5_ib_fill_res_entry(struct sk_buff *msg, 1378 struct rdma_restrack_entry *res); 1379 int mlx5_ib_fill_stat_entry(struct sk_buff *msg, 1380 struct rdma_restrack_entry *res); 1381 1382 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1383 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1384 1385 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1386 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user); 1387 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); 1388 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev); 1389 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev); 1390 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1391 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1392 struct mlx5_flow_context *flow_context, 1393 struct mlx5_flow_act *flow_act, u32 counter_id, 1394 void *cmd_in, int inlen, int dest_id, int dest_type); 1395 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1396 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 offset, u32 *counter_id); 1397 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); 1398 #else 1399 static inline int 1400 mlx5_ib_devx_create(struct mlx5_ib_dev *dev, 1401 bool is_user) { return -EOPNOTSUPP; } 1402 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} 1403 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {} 1404 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {} 1405 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1406 int *dest_type) 1407 { 1408 return false; 1409 } 1410 static inline void 1411 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) 1412 { 1413 return; 1414 }; 1415 #endif 1416 static inline void init_query_mad(struct ib_smp *mad) 1417 { 1418 mad->base_version = 1; 1419 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1420 mad->class_version = 1; 1421 mad->method = IB_MGMT_METHOD_GET; 1422 } 1423 1424 static inline u8 convert_access(int acc) 1425 { 1426 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1427 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1428 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1429 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1430 MLX5_PERM_LOCAL_READ; 1431 } 1432 1433 static inline int is_qp1(enum ib_qp_type qp_type) 1434 { 1435 return qp_type == MLX5_IB_QPT_HW_GSI; 1436 } 1437 1438 #define MLX5_MAX_UMR_SHIFT 16 1439 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1440 1441 static inline u32 check_cq_create_flags(u32 flags) 1442 { 1443 /* 1444 * It returns non-zero value for unsupported CQ 1445 * create flags, otherwise it returns zero. 1446 */ 1447 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1448 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1449 } 1450 1451 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1452 u32 *user_index) 1453 { 1454 if (cqe_version) { 1455 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1456 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1457 return -EINVAL; 1458 *user_index = cmd_uidx; 1459 } else { 1460 *user_index = MLX5_IB_DEFAULT_UIDX; 1461 } 1462 1463 return 0; 1464 } 1465 1466 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1467 struct mlx5_ib_create_qp *ucmd, 1468 int inlen, 1469 u32 *user_index) 1470 { 1471 u8 cqe_version = ucontext->cqe_version; 1472 1473 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1474 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1475 return 0; 1476 1477 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1478 !!cqe_version)) 1479 return -EINVAL; 1480 1481 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1482 } 1483 1484 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1485 struct mlx5_ib_create_srq *ucmd, 1486 int inlen, 1487 u32 *user_index) 1488 { 1489 u8 cqe_version = ucontext->cqe_version; 1490 1491 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1492 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1493 return 0; 1494 1495 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1496 !!cqe_version)) 1497 return -EINVAL; 1498 1499 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1500 } 1501 1502 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1503 { 1504 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1505 MLX5_UARS_IN_PAGE : 1; 1506 } 1507 1508 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1509 struct mlx5_bfreg_info *bfregi) 1510 { 1511 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1512 } 1513 1514 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1515 void mlx5_ib_put_xlt_emergency_page(void); 1516 1517 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1518 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1519 bool dyn_bfreg); 1520 1521 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter); 1522 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num); 1523 1524 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev, 1525 bool do_modify_atomic, int access_flags) 1526 { 1527 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1528 return false; 1529 1530 if (do_modify_atomic && 1531 MLX5_CAP_GEN(dev->mdev, atomic) && 1532 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1533 return false; 1534 1535 if (access_flags & IB_ACCESS_RELAXED_ORDERING) 1536 return false; 1537 1538 return true; 1539 } 1540 1541 int mlx5_ib_enable_driver(struct ib_device *dev); 1542 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1543 #endif /* MLX5_IB_H */ 1544