1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 49 #define mlx5_ib_dbg(dev, format, arg...) \ 50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_err(dev, format, arg...) \ 54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define mlx5_ib_warn(dev, format, arg...) \ 58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 59 __LINE__, current->pid, ##arg) 60 61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 62 sizeof(((type *)0)->fld) <= (sz)) 63 #define MLX5_IB_DEFAULT_UIDX 0xffffff 64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 65 66 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 67 68 enum { 69 MLX5_IB_MMAP_CMD_SHIFT = 8, 70 MLX5_IB_MMAP_CMD_MASK = 0xff, 71 }; 72 73 enum { 74 MLX5_RES_SCAT_DATA32_CQE = 0x1, 75 MLX5_RES_SCAT_DATA64_CQE = 0x2, 76 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 77 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 78 }; 79 80 enum mlx5_ib_latency_class { 81 MLX5_IB_LATENCY_CLASS_LOW, 82 MLX5_IB_LATENCY_CLASS_MEDIUM, 83 MLX5_IB_LATENCY_CLASS_HIGH, 84 }; 85 86 enum mlx5_ib_mad_ifc_flags { 87 MLX5_MAD_IFC_IGNORE_MKEY = 1, 88 MLX5_MAD_IFC_IGNORE_BKEY = 2, 89 MLX5_MAD_IFC_NET_VIEW = 4, 90 }; 91 92 enum { 93 MLX5_CROSS_CHANNEL_BFREG = 0, 94 }; 95 96 enum { 97 MLX5_CQE_VERSION_V0, 98 MLX5_CQE_VERSION_V1, 99 }; 100 101 enum { 102 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 103 MLX5_TM_MAX_SGE = 1, 104 }; 105 106 enum { 107 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 108 MLX5_IB_INVALID_BFREG = BIT(31), 109 }; 110 111 struct mlx5_ib_vma_private_data { 112 struct list_head list; 113 struct vm_area_struct *vma; 114 /* protect vma_private_list add/del */ 115 struct mutex *vma_private_list_mutex; 116 }; 117 118 struct mlx5_ib_ucontext { 119 struct ib_ucontext ibucontext; 120 struct list_head db_page_list; 121 122 /* protect doorbell record alloc/free 123 */ 124 struct mutex db_page_mutex; 125 struct mlx5_bfreg_info bfregi; 126 u8 cqe_version; 127 /* Transport Domain number */ 128 u32 tdn; 129 struct list_head vma_private_list; 130 /* protect vma_private_list add/del */ 131 struct mutex vma_private_list_mutex; 132 133 unsigned long upd_xlt_page; 134 /* protect ODP/KSM */ 135 struct mutex upd_xlt_page_mutex; 136 u64 lib_caps; 137 }; 138 139 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 140 { 141 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 142 } 143 144 struct mlx5_ib_pd { 145 struct ib_pd ibpd; 146 u32 pdn; 147 }; 148 149 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 150 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 151 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 152 #error "Invalid number of bypass priorities" 153 #endif 154 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 155 156 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 157 #define MLX5_IB_NUM_SNIFFER_FTS 2 158 struct mlx5_ib_flow_prio { 159 struct mlx5_flow_table *flow_table; 160 unsigned int refcount; 161 }; 162 163 struct mlx5_ib_flow_handler { 164 struct list_head list; 165 struct ib_flow ibflow; 166 struct mlx5_ib_flow_prio *prio; 167 struct mlx5_flow_handle *rule; 168 }; 169 170 struct mlx5_ib_flow_db { 171 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 172 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 173 struct mlx5_flow_table *lag_demux_ft; 174 /* Protect flow steering bypass flow tables 175 * when add/del flow rules. 176 * only single add/removal of flow steering rule could be done 177 * simultaneously. 178 */ 179 struct mutex lock; 180 }; 181 182 /* Use macros here so that don't have to duplicate 183 * enum ib_send_flags and enum ib_qp_type for low-level driver 184 */ 185 186 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 187 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 188 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 189 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 190 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 191 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 192 193 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 194 /* 195 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 196 * creates the actual hardware QP. 197 */ 198 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 199 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 200 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 201 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 202 203 #define MLX5_IB_UMR_OCTOWORD 16 204 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 205 206 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 207 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 208 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 209 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 210 #define MLX5_IB_UPD_XLT_PD BIT(4) 211 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 212 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 213 214 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 215 * 216 * These flags are intended for internal use by the mlx5_ib driver, and they 217 * rely on the range reserved for that use in the ib_qp_create_flags enum. 218 */ 219 220 /* Create a UD QP whose source QP number is 1 */ 221 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 222 { 223 return IB_QP_CREATE_RESERVED_START; 224 } 225 226 struct wr_list { 227 u16 opcode; 228 u16 next; 229 }; 230 231 enum mlx5_ib_rq_flags { 232 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 233 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 234 }; 235 236 struct mlx5_ib_wq { 237 u64 *wrid; 238 u32 *wr_data; 239 struct wr_list *w_list; 240 unsigned *wqe_head; 241 u16 unsig_count; 242 243 /* serialize post to the work queue 244 */ 245 spinlock_t lock; 246 int wqe_cnt; 247 int max_post; 248 int max_gs; 249 int offset; 250 int wqe_shift; 251 unsigned head; 252 unsigned tail; 253 u16 cur_post; 254 u16 last_poll; 255 void *qend; 256 }; 257 258 enum mlx5_ib_wq_flags { 259 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 260 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 261 }; 262 263 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 264 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 265 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 266 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 267 268 struct mlx5_ib_rwq { 269 struct ib_wq ibwq; 270 struct mlx5_core_qp core_qp; 271 u32 rq_num_pas; 272 u32 log_rq_stride; 273 u32 log_rq_size; 274 u32 rq_page_offset; 275 u32 log_page_size; 276 u32 log_num_strides; 277 u32 two_byte_shift_en; 278 u32 single_stride_log_num_of_bytes; 279 struct ib_umem *umem; 280 size_t buf_size; 281 unsigned int page_shift; 282 int create_type; 283 struct mlx5_db db; 284 u32 user_index; 285 u32 wqe_count; 286 u32 wqe_shift; 287 int wq_sig; 288 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 289 }; 290 291 enum { 292 MLX5_QP_USER, 293 MLX5_QP_KERNEL, 294 MLX5_QP_EMPTY 295 }; 296 297 enum { 298 MLX5_WQ_USER, 299 MLX5_WQ_KERNEL 300 }; 301 302 struct mlx5_ib_rwq_ind_table { 303 struct ib_rwq_ind_table ib_rwq_ind_tbl; 304 u32 rqtn; 305 }; 306 307 struct mlx5_ib_ubuffer { 308 struct ib_umem *umem; 309 int buf_size; 310 u64 buf_addr; 311 }; 312 313 struct mlx5_ib_qp_base { 314 struct mlx5_ib_qp *container_mibqp; 315 struct mlx5_core_qp mqp; 316 struct mlx5_ib_ubuffer ubuffer; 317 }; 318 319 struct mlx5_ib_qp_trans { 320 struct mlx5_ib_qp_base base; 321 u16 xrcdn; 322 u8 alt_port; 323 u8 atomic_rd_en; 324 u8 resp_depth; 325 }; 326 327 struct mlx5_ib_rss_qp { 328 u32 tirn; 329 }; 330 331 struct mlx5_ib_rq { 332 struct mlx5_ib_qp_base base; 333 struct mlx5_ib_wq *rq; 334 struct mlx5_ib_ubuffer ubuffer; 335 struct mlx5_db *doorbell; 336 u32 tirn; 337 u8 state; 338 u32 flags; 339 }; 340 341 struct mlx5_ib_sq { 342 struct mlx5_ib_qp_base base; 343 struct mlx5_ib_wq *sq; 344 struct mlx5_ib_ubuffer ubuffer; 345 struct mlx5_db *doorbell; 346 u32 tisn; 347 u8 state; 348 }; 349 350 struct mlx5_ib_raw_packet_qp { 351 struct mlx5_ib_sq sq; 352 struct mlx5_ib_rq rq; 353 }; 354 355 struct mlx5_bf { 356 int buf_size; 357 unsigned long offset; 358 struct mlx5_sq_bfreg *bfreg; 359 }; 360 361 struct mlx5_ib_dct { 362 struct mlx5_core_dct mdct; 363 u32 *in; 364 }; 365 366 struct mlx5_ib_qp { 367 struct ib_qp ibqp; 368 union { 369 struct mlx5_ib_qp_trans trans_qp; 370 struct mlx5_ib_raw_packet_qp raw_packet_qp; 371 struct mlx5_ib_rss_qp rss_qp; 372 struct mlx5_ib_dct dct; 373 }; 374 struct mlx5_buf buf; 375 376 struct mlx5_db db; 377 struct mlx5_ib_wq rq; 378 379 u8 sq_signal_bits; 380 u8 next_fence; 381 struct mlx5_ib_wq sq; 382 383 /* serialize qp state modifications 384 */ 385 struct mutex mutex; 386 u32 flags; 387 u8 port; 388 u8 state; 389 int wq_sig; 390 int scat_cqe; 391 int max_inline_data; 392 struct mlx5_bf bf; 393 int has_rq; 394 395 /* only for user space QPs. For kernel 396 * we have it from the bf object 397 */ 398 int bfregn; 399 400 int create_type; 401 402 /* Store signature errors */ 403 bool signature_en; 404 405 struct list_head qps_list; 406 struct list_head cq_recv_list; 407 struct list_head cq_send_list; 408 u32 rate_limit; 409 u32 underlay_qpn; 410 bool tunnel_offload_en; 411 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 412 enum ib_qp_type qp_sub_type; 413 }; 414 415 struct mlx5_ib_cq_buf { 416 struct mlx5_buf buf; 417 struct ib_umem *umem; 418 int cqe_size; 419 int nent; 420 }; 421 422 enum mlx5_ib_qp_flags { 423 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 424 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 425 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 426 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 427 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 428 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 429 /* QP uses 1 as its source QP number */ 430 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 431 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 432 MLX5_IB_QP_RSS = 1 << 8, 433 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 434 MLX5_IB_QP_UNDERLAY = 1 << 10, 435 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 436 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 437 }; 438 439 struct mlx5_umr_wr { 440 struct ib_send_wr wr; 441 u64 virt_addr; 442 u64 offset; 443 struct ib_pd *pd; 444 unsigned int page_shift; 445 unsigned int xlt_size; 446 u64 length; 447 int access_flags; 448 u32 mkey; 449 }; 450 451 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 452 { 453 return container_of(wr, struct mlx5_umr_wr, wr); 454 } 455 456 struct mlx5_shared_mr_info { 457 int mr_id; 458 struct ib_umem *umem; 459 }; 460 461 enum mlx5_ib_cq_pr_flags { 462 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 463 }; 464 465 struct mlx5_ib_cq { 466 struct ib_cq ibcq; 467 struct mlx5_core_cq mcq; 468 struct mlx5_ib_cq_buf buf; 469 struct mlx5_db db; 470 471 /* serialize access to the CQ 472 */ 473 spinlock_t lock; 474 475 /* protect resize cq 476 */ 477 struct mutex resize_mutex; 478 struct mlx5_ib_cq_buf *resize_buf; 479 struct ib_umem *resize_umem; 480 int cqe_size; 481 struct list_head list_send_qp; 482 struct list_head list_recv_qp; 483 u32 create_flags; 484 struct list_head wc_list; 485 enum ib_cq_notify_flags notify_flags; 486 struct work_struct notify_work; 487 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 488 }; 489 490 struct mlx5_ib_wc { 491 struct ib_wc wc; 492 struct list_head list; 493 }; 494 495 struct mlx5_ib_srq { 496 struct ib_srq ibsrq; 497 struct mlx5_core_srq msrq; 498 struct mlx5_buf buf; 499 struct mlx5_db db; 500 u64 *wrid; 501 /* protect SRQ hanlding 502 */ 503 spinlock_t lock; 504 int head; 505 int tail; 506 u16 wqe_ctr; 507 struct ib_umem *umem; 508 /* serialize arming a SRQ 509 */ 510 struct mutex mutex; 511 int wq_sig; 512 }; 513 514 struct mlx5_ib_xrcd { 515 struct ib_xrcd ibxrcd; 516 u32 xrcdn; 517 }; 518 519 enum mlx5_ib_mtt_access_flags { 520 MLX5_IB_MTT_READ = (1 << 0), 521 MLX5_IB_MTT_WRITE = (1 << 1), 522 }; 523 524 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 525 526 struct mlx5_ib_mr { 527 struct ib_mr ibmr; 528 void *descs; 529 dma_addr_t desc_map; 530 int ndescs; 531 int max_descs; 532 int desc_size; 533 int access_mode; 534 struct mlx5_core_mkey mmkey; 535 struct ib_umem *umem; 536 struct mlx5_shared_mr_info *smr_info; 537 struct list_head list; 538 int order; 539 bool allocated_from_cache; 540 int npages; 541 struct mlx5_ib_dev *dev; 542 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 543 struct mlx5_core_sig_ctx *sig; 544 int live; 545 void *descs_alloc; 546 int access_flags; /* Needed for rereg MR */ 547 548 struct mlx5_ib_mr *parent; 549 atomic_t num_leaf_free; 550 wait_queue_head_t q_leaf_free; 551 }; 552 553 struct mlx5_ib_mw { 554 struct ib_mw ibmw; 555 struct mlx5_core_mkey mmkey; 556 int ndescs; 557 }; 558 559 struct mlx5_ib_umr_context { 560 struct ib_cqe cqe; 561 enum ib_wc_status status; 562 struct completion done; 563 }; 564 565 struct umr_common { 566 struct ib_pd *pd; 567 struct ib_cq *cq; 568 struct ib_qp *qp; 569 /* control access to UMR QP 570 */ 571 struct semaphore sem; 572 }; 573 574 enum { 575 MLX5_FMR_INVALID, 576 MLX5_FMR_VALID, 577 MLX5_FMR_BUSY, 578 }; 579 580 struct mlx5_cache_ent { 581 struct list_head head; 582 /* sync access to the cahce entry 583 */ 584 spinlock_t lock; 585 586 587 struct dentry *dir; 588 char name[4]; 589 u32 order; 590 u32 xlt; 591 u32 access_mode; 592 u32 page; 593 594 u32 size; 595 u32 cur; 596 u32 miss; 597 u32 limit; 598 599 struct dentry *fsize; 600 struct dentry *fcur; 601 struct dentry *fmiss; 602 struct dentry *flimit; 603 604 struct mlx5_ib_dev *dev; 605 struct work_struct work; 606 struct delayed_work dwork; 607 int pending; 608 struct completion compl; 609 }; 610 611 struct mlx5_mr_cache { 612 struct workqueue_struct *wq; 613 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 614 int stopped; 615 struct dentry *root; 616 unsigned long last_add; 617 }; 618 619 struct mlx5_ib_gsi_qp; 620 621 struct mlx5_ib_port_resources { 622 struct mlx5_ib_resources *devr; 623 struct mlx5_ib_gsi_qp *gsi; 624 struct work_struct pkey_change_work; 625 }; 626 627 struct mlx5_ib_resources { 628 struct ib_cq *c0; 629 struct ib_xrcd *x0; 630 struct ib_xrcd *x1; 631 struct ib_pd *p0; 632 struct ib_srq *s0; 633 struct ib_srq *s1; 634 struct mlx5_ib_port_resources ports[2]; 635 /* Protects changes to the port resources */ 636 struct mutex mutex; 637 }; 638 639 struct mlx5_ib_counters { 640 const char **names; 641 size_t *offsets; 642 u32 num_q_counters; 643 u32 num_cong_counters; 644 u16 set_id; 645 bool set_id_valid; 646 }; 647 648 struct mlx5_ib_multiport_info; 649 650 struct mlx5_ib_multiport { 651 struct mlx5_ib_multiport_info *mpi; 652 /* To be held when accessing the multiport info */ 653 spinlock_t mpi_lock; 654 }; 655 656 struct mlx5_ib_port { 657 struct mlx5_ib_counters cnts; 658 struct mlx5_ib_multiport mp; 659 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 660 }; 661 662 struct mlx5_roce { 663 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 664 * netdev pointer 665 */ 666 rwlock_t netdev_lock; 667 struct net_device *netdev; 668 struct notifier_block nb; 669 atomic_t next_port; 670 enum ib_port_state last_port_state; 671 struct mlx5_ib_dev *dev; 672 u8 native_port_num; 673 }; 674 675 struct mlx5_ib_dbg_param { 676 int offset; 677 struct mlx5_ib_dev *dev; 678 struct dentry *dentry; 679 u8 port_num; 680 }; 681 682 enum mlx5_ib_dbg_cc_types { 683 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 684 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 685 MLX5_IB_DBG_CC_RP_TIME_RESET, 686 MLX5_IB_DBG_CC_RP_BYTE_RESET, 687 MLX5_IB_DBG_CC_RP_THRESHOLD, 688 MLX5_IB_DBG_CC_RP_AI_RATE, 689 MLX5_IB_DBG_CC_RP_HAI_RATE, 690 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 691 MLX5_IB_DBG_CC_RP_MIN_RATE, 692 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 693 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 694 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 695 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 696 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 697 MLX5_IB_DBG_CC_RP_GD, 698 MLX5_IB_DBG_CC_NP_CNP_DSCP, 699 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 700 MLX5_IB_DBG_CC_NP_CNP_PRIO, 701 MLX5_IB_DBG_CC_MAX, 702 }; 703 704 struct mlx5_ib_dbg_cc_params { 705 struct dentry *root; 706 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 707 }; 708 709 enum { 710 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 711 }; 712 713 struct mlx5_ib_dbg_delay_drop { 714 struct dentry *dir_debugfs; 715 struct dentry *rqs_cnt_debugfs; 716 struct dentry *events_cnt_debugfs; 717 struct dentry *timeout_debugfs; 718 }; 719 720 struct mlx5_ib_delay_drop { 721 struct mlx5_ib_dev *dev; 722 struct work_struct delay_drop_work; 723 /* serialize setting of delay drop */ 724 struct mutex lock; 725 u32 timeout; 726 bool activate; 727 atomic_t events_cnt; 728 atomic_t rqs_cnt; 729 struct mlx5_ib_dbg_delay_drop *dbg; 730 }; 731 732 enum mlx5_ib_stages { 733 MLX5_IB_STAGE_INIT, 734 MLX5_IB_STAGE_CAPS, 735 MLX5_IB_STAGE_ROCE, 736 MLX5_IB_STAGE_DEVICE_RESOURCES, 737 MLX5_IB_STAGE_ODP, 738 MLX5_IB_STAGE_COUNTERS, 739 MLX5_IB_STAGE_CONG_DEBUGFS, 740 MLX5_IB_STAGE_UAR, 741 MLX5_IB_STAGE_BFREG, 742 MLX5_IB_STAGE_IB_REG, 743 MLX5_IB_STAGE_UMR_RESOURCES, 744 MLX5_IB_STAGE_DELAY_DROP, 745 MLX5_IB_STAGE_CLASS_ATTR, 746 MLX5_IB_STAGE_MAX, 747 }; 748 749 struct mlx5_ib_stage { 750 int (*init)(struct mlx5_ib_dev *dev); 751 void (*cleanup)(struct mlx5_ib_dev *dev); 752 }; 753 754 #define STAGE_CREATE(_stage, _init, _cleanup) \ 755 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 756 757 struct mlx5_ib_profile { 758 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 759 }; 760 761 struct mlx5_ib_multiport_info { 762 struct list_head list; 763 struct mlx5_ib_dev *ibdev; 764 struct mlx5_core_dev *mdev; 765 struct completion unref_comp; 766 u64 sys_image_guid; 767 u32 mdev_refcnt; 768 bool is_master; 769 bool unaffiliate; 770 }; 771 772 struct mlx5_ib_dev { 773 struct ib_device ib_dev; 774 struct mlx5_core_dev *mdev; 775 struct mlx5_roce roce[MLX5_MAX_PORTS]; 776 int num_ports; 777 /* serialize update of capability mask 778 */ 779 struct mutex cap_mask_mutex; 780 bool ib_active; 781 struct umr_common umrc; 782 /* sync used page count stats 783 */ 784 struct mlx5_ib_resources devr; 785 struct mlx5_mr_cache cache; 786 struct timer_list delay_timer; 787 /* Prevents soft lock on massive reg MRs */ 788 struct mutex slow_path_mutex; 789 int fill_delay; 790 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 791 struct ib_odp_caps odp_caps; 792 u64 odp_max_size; 793 /* 794 * Sleepable RCU that prevents destruction of MRs while they are still 795 * being used by a page fault handler. 796 */ 797 struct srcu_struct mr_srcu; 798 u32 null_mkey; 799 #endif 800 struct mlx5_ib_flow_db flow_db; 801 /* protect resources needed as part of reset flow */ 802 spinlock_t reset_flow_resource_lock; 803 struct list_head qp_list; 804 /* Array with num_ports elements */ 805 struct mlx5_ib_port *port; 806 struct mlx5_sq_bfreg bfreg; 807 struct mlx5_sq_bfreg fp_bfreg; 808 struct mlx5_ib_delay_drop delay_drop; 809 const struct mlx5_ib_profile *profile; 810 811 /* protect the user_td */ 812 struct mutex lb_mutex; 813 u32 user_td; 814 u8 umr_fence; 815 struct list_head ib_dev_list; 816 u64 sys_image_guid; 817 }; 818 819 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 820 { 821 return container_of(mcq, struct mlx5_ib_cq, mcq); 822 } 823 824 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 825 { 826 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 827 } 828 829 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 830 { 831 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 832 } 833 834 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 835 { 836 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 837 } 838 839 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 840 { 841 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 842 } 843 844 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 845 { 846 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 847 } 848 849 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 850 { 851 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 852 } 853 854 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 855 { 856 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 857 } 858 859 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 860 { 861 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 862 } 863 864 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 865 { 866 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 867 } 868 869 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 870 { 871 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 872 } 873 874 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 875 { 876 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 877 } 878 879 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 880 { 881 return container_of(msrq, struct mlx5_ib_srq, msrq); 882 } 883 884 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 885 { 886 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 887 } 888 889 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 890 { 891 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 892 } 893 894 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 895 struct mlx5_db *db); 896 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 897 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 898 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 899 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 900 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 901 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 902 const void *in_mad, void *response_mad); 903 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 904 struct ib_udata *udata); 905 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 906 int mlx5_ib_destroy_ah(struct ib_ah *ah); 907 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 908 struct ib_srq_init_attr *init_attr, 909 struct ib_udata *udata); 910 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 911 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 912 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 913 int mlx5_ib_destroy_srq(struct ib_srq *srq); 914 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 915 struct ib_recv_wr **bad_wr); 916 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 917 struct ib_qp_init_attr *init_attr, 918 struct ib_udata *udata); 919 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 920 int attr_mask, struct ib_udata *udata); 921 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 922 struct ib_qp_init_attr *qp_init_attr); 923 int mlx5_ib_destroy_qp(struct ib_qp *qp); 924 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 925 struct ib_send_wr **bad_wr); 926 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 927 struct ib_recv_wr **bad_wr); 928 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 929 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 930 void *buffer, u32 length, 931 struct mlx5_ib_qp_base *base); 932 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 933 const struct ib_cq_init_attr *attr, 934 struct ib_ucontext *context, 935 struct ib_udata *udata); 936 int mlx5_ib_destroy_cq(struct ib_cq *cq); 937 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 938 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 939 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 940 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 941 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 942 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 943 u64 virt_addr, int access_flags, 944 struct ib_udata *udata); 945 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 946 struct ib_udata *udata); 947 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 948 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 949 int page_shift, int flags); 950 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 951 int access_flags); 952 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 953 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 954 u64 length, u64 virt_addr, int access_flags, 955 struct ib_pd *pd, struct ib_udata *udata); 956 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 957 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 958 enum ib_mr_type mr_type, 959 u32 max_num_sg); 960 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 961 unsigned int *sg_offset); 962 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 963 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 964 const struct ib_mad_hdr *in, size_t in_mad_size, 965 struct ib_mad_hdr *out, size_t *out_mad_size, 966 u16 *out_mad_pkey_index); 967 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 968 struct ib_ucontext *context, 969 struct ib_udata *udata); 970 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 971 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 972 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 973 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 974 struct ib_smp *out_mad); 975 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 976 __be64 *sys_image_guid); 977 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 978 u16 *max_pkeys); 979 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 980 u32 *vendor_id); 981 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 982 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 983 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 984 u16 *pkey); 985 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 986 union ib_gid *gid); 987 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 988 struct ib_port_attr *props); 989 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 990 struct ib_port_attr *props); 991 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 992 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 993 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 994 unsigned long max_page_shift, 995 int *count, int *shift, 996 int *ncont, int *order); 997 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 998 int page_shift, size_t offset, size_t num_pages, 999 __be64 *pas, int access_flags); 1000 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1001 int page_shift, __be64 *pas, int access_flags); 1002 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1003 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 1004 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1005 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1006 1007 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1008 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1009 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1010 struct ib_mr_status *mr_status); 1011 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1012 struct ib_wq_init_attr *init_attr, 1013 struct ib_udata *udata); 1014 int mlx5_ib_destroy_wq(struct ib_wq *wq); 1015 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1016 u32 wq_attr_mask, struct ib_udata *udata); 1017 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1018 struct ib_rwq_ind_table_init_attr *init_attr, 1019 struct ib_udata *udata); 1020 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1021 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); 1022 1023 1024 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1025 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1026 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, 1027 struct mlx5_pagefault *pfault); 1028 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1029 int __init mlx5_ib_odp_init(void); 1030 void mlx5_ib_odp_cleanup(void); 1031 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 1032 unsigned long end); 1033 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1034 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1035 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1036 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1037 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1038 { 1039 return; 1040 } 1041 1042 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1043 static inline int mlx5_ib_odp_init(void) { return 0; } 1044 static inline void mlx5_ib_odp_cleanup(void) {} 1045 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1046 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1047 size_t nentries, struct mlx5_ib_mr *mr, 1048 int flags) {} 1049 1050 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1051 1052 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1053 u8 port, struct ifla_vf_info *info); 1054 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1055 u8 port, int state); 1056 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1057 u8 port, struct ifla_vf_stats *stats); 1058 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1059 u64 guid, int type); 1060 1061 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 1062 int index); 1063 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 1064 int index, enum ib_gid_type *gid_type); 1065 1066 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1067 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1068 1069 /* GSI QP helper functions */ 1070 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1071 struct ib_qp_init_attr *init_attr); 1072 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1073 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1074 int attr_mask); 1075 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1076 int qp_attr_mask, 1077 struct ib_qp_init_attr *qp_init_attr); 1078 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 1079 struct ib_send_wr **bad_wr); 1080 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 1081 struct ib_recv_wr **bad_wr); 1082 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1083 1084 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1085 1086 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1087 int bfregn); 1088 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1089 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1090 u8 ib_port_num, 1091 u8 *native_port_num); 1092 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1093 u8 port_num); 1094 1095 static inline void init_query_mad(struct ib_smp *mad) 1096 { 1097 mad->base_version = 1; 1098 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1099 mad->class_version = 1; 1100 mad->method = IB_MGMT_METHOD_GET; 1101 } 1102 1103 static inline u8 convert_access(int acc) 1104 { 1105 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1106 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1107 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1108 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1109 MLX5_PERM_LOCAL_READ; 1110 } 1111 1112 static inline int is_qp1(enum ib_qp_type qp_type) 1113 { 1114 return qp_type == MLX5_IB_QPT_HW_GSI; 1115 } 1116 1117 #define MLX5_MAX_UMR_SHIFT 16 1118 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1119 1120 static inline u32 check_cq_create_flags(u32 flags) 1121 { 1122 /* 1123 * It returns non-zero value for unsupported CQ 1124 * create flags, otherwise it returns zero. 1125 */ 1126 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1127 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1128 } 1129 1130 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1131 u32 *user_index) 1132 { 1133 if (cqe_version) { 1134 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1135 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1136 return -EINVAL; 1137 *user_index = cmd_uidx; 1138 } else { 1139 *user_index = MLX5_IB_DEFAULT_UIDX; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1146 struct mlx5_ib_create_qp *ucmd, 1147 int inlen, 1148 u32 *user_index) 1149 { 1150 u8 cqe_version = ucontext->cqe_version; 1151 1152 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1153 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1154 return 0; 1155 1156 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1157 !!cqe_version)) 1158 return -EINVAL; 1159 1160 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1161 } 1162 1163 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1164 struct mlx5_ib_create_srq *ucmd, 1165 int inlen, 1166 u32 *user_index) 1167 { 1168 u8 cqe_version = ucontext->cqe_version; 1169 1170 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1171 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1172 return 0; 1173 1174 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1175 !!cqe_version)) 1176 return -EINVAL; 1177 1178 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1179 } 1180 1181 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1182 { 1183 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1184 MLX5_UARS_IN_PAGE : 1; 1185 } 1186 1187 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1188 struct mlx5_bfreg_info *bfregi) 1189 { 1190 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1191 } 1192 1193 #endif /* MLX5_IB_H */ 1194