1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/fs.h> 43 #include <linux/mlx5/qp.h> 44 #include <linux/mlx5/srq.h> 45 #include <linux/mlx5/fs.h> 46 #include <linux/types.h> 47 #include <linux/mlx5/transobj.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/mlx5-abi.h> 50 #include <rdma/uverbs_ioctl.h> 51 #include <rdma/mlx5_user_ioctl_cmds.h> 52 53 #define mlx5_ib_dbg(_dev, format, arg...) \ 54 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define mlx5_ib_err(_dev, format, arg...) \ 58 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 59 __LINE__, current->pid, ##arg) 60 61 #define mlx5_ib_warn(_dev, format, arg...) \ 62 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 63 __LINE__, current->pid, ##arg) 64 65 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 66 sizeof(((type *)0)->fld) <= (sz)) 67 #define MLX5_IB_DEFAULT_UIDX 0xffffff 68 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 69 70 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 71 72 enum { 73 MLX5_IB_MMAP_CMD_SHIFT = 8, 74 MLX5_IB_MMAP_CMD_MASK = 0xff, 75 }; 76 77 enum { 78 MLX5_RES_SCAT_DATA32_CQE = 0x1, 79 MLX5_RES_SCAT_DATA64_CQE = 0x2, 80 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 81 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 82 }; 83 84 enum mlx5_ib_mad_ifc_flags { 85 MLX5_MAD_IFC_IGNORE_MKEY = 1, 86 MLX5_MAD_IFC_IGNORE_BKEY = 2, 87 MLX5_MAD_IFC_NET_VIEW = 4, 88 }; 89 90 enum { 91 MLX5_CROSS_CHANNEL_BFREG = 0, 92 }; 93 94 enum { 95 MLX5_CQE_VERSION_V0, 96 MLX5_CQE_VERSION_V1, 97 }; 98 99 enum { 100 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 101 MLX5_TM_MAX_SGE = 1, 102 }; 103 104 enum { 105 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 106 MLX5_IB_INVALID_BFREG = BIT(31), 107 }; 108 109 enum { 110 MLX5_MAX_MEMIC_PAGES = 0x100, 111 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 112 }; 113 114 enum { 115 MLX5_MEMIC_BASE_ALIGN = 6, 116 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 117 }; 118 119 struct mlx5_ib_ucontext { 120 struct ib_ucontext ibucontext; 121 struct list_head db_page_list; 122 123 /* protect doorbell record alloc/free 124 */ 125 struct mutex db_page_mutex; 126 struct mlx5_bfreg_info bfregi; 127 u8 cqe_version; 128 /* Transport Domain number */ 129 u32 tdn; 130 131 u64 lib_caps; 132 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES); 133 u16 devx_uid; 134 /* For RoCE LAG TX affinity */ 135 atomic_t tx_port_affinity; 136 }; 137 138 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 139 { 140 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 141 } 142 143 struct mlx5_ib_pd { 144 struct ib_pd ibpd; 145 u32 pdn; 146 u16 uid; 147 }; 148 149 enum { 150 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 151 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 152 MLX5_IB_FLOW_ACTION_DECAP, 153 }; 154 155 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 156 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 157 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 158 #error "Invalid number of bypass priorities" 159 #endif 160 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 161 162 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 163 #define MLX5_IB_NUM_SNIFFER_FTS 2 164 #define MLX5_IB_NUM_EGRESS_FTS 1 165 struct mlx5_ib_flow_prio { 166 struct mlx5_flow_table *flow_table; 167 unsigned int refcount; 168 }; 169 170 struct mlx5_ib_flow_handler { 171 struct list_head list; 172 struct ib_flow ibflow; 173 struct mlx5_ib_flow_prio *prio; 174 struct mlx5_flow_handle *rule; 175 struct ib_counters *ibcounters; 176 struct mlx5_ib_dev *dev; 177 struct mlx5_ib_flow_matcher *flow_matcher; 178 }; 179 180 struct mlx5_ib_flow_matcher { 181 struct mlx5_ib_match_params matcher_mask; 182 int mask_len; 183 enum mlx5_ib_flow_type flow_type; 184 enum mlx5_flow_namespace_type ns_type; 185 u16 priority; 186 struct mlx5_core_dev *mdev; 187 atomic_t usecnt; 188 u8 match_criteria_enable; 189 }; 190 191 struct mlx5_ib_flow_db { 192 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 193 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 194 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 195 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 196 struct mlx5_flow_table *lag_demux_ft; 197 /* Protect flow steering bypass flow tables 198 * when add/del flow rules. 199 * only single add/removal of flow steering rule could be done 200 * simultaneously. 201 */ 202 struct mutex lock; 203 }; 204 205 /* Use macros here so that don't have to duplicate 206 * enum ib_send_flags and enum ib_qp_type for low-level driver 207 */ 208 209 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 210 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 211 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 212 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 213 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 214 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 215 216 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 217 /* 218 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 219 * creates the actual hardware QP. 220 */ 221 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 222 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 223 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 224 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 225 226 #define MLX5_IB_UMR_OCTOWORD 16 227 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 228 229 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 230 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 231 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 232 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 233 #define MLX5_IB_UPD_XLT_PD BIT(4) 234 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 235 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 236 237 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 238 * 239 * These flags are intended for internal use by the mlx5_ib driver, and they 240 * rely on the range reserved for that use in the ib_qp_create_flags enum. 241 */ 242 243 /* Create a UD QP whose source QP number is 1 */ 244 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 245 { 246 return IB_QP_CREATE_RESERVED_START; 247 } 248 249 struct wr_list { 250 u16 opcode; 251 u16 next; 252 }; 253 254 enum mlx5_ib_rq_flags { 255 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 256 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 257 }; 258 259 struct mlx5_ib_wq { 260 u64 *wrid; 261 u32 *wr_data; 262 struct wr_list *w_list; 263 unsigned *wqe_head; 264 u16 unsig_count; 265 266 /* serialize post to the work queue 267 */ 268 spinlock_t lock; 269 int wqe_cnt; 270 int max_post; 271 int max_gs; 272 int offset; 273 int wqe_shift; 274 unsigned head; 275 unsigned tail; 276 u16 cur_post; 277 u16 last_poll; 278 void *qend; 279 }; 280 281 enum mlx5_ib_wq_flags { 282 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 283 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 284 }; 285 286 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 287 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 288 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 289 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 290 291 struct mlx5_ib_rwq { 292 struct ib_wq ibwq; 293 struct mlx5_core_qp core_qp; 294 u32 rq_num_pas; 295 u32 log_rq_stride; 296 u32 log_rq_size; 297 u32 rq_page_offset; 298 u32 log_page_size; 299 u32 log_num_strides; 300 u32 two_byte_shift_en; 301 u32 single_stride_log_num_of_bytes; 302 struct ib_umem *umem; 303 size_t buf_size; 304 unsigned int page_shift; 305 int create_type; 306 struct mlx5_db db; 307 u32 user_index; 308 u32 wqe_count; 309 u32 wqe_shift; 310 int wq_sig; 311 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 312 }; 313 314 enum { 315 MLX5_QP_USER, 316 MLX5_QP_KERNEL, 317 MLX5_QP_EMPTY 318 }; 319 320 enum { 321 MLX5_WQ_USER, 322 MLX5_WQ_KERNEL 323 }; 324 325 struct mlx5_ib_rwq_ind_table { 326 struct ib_rwq_ind_table ib_rwq_ind_tbl; 327 u32 rqtn; 328 u16 uid; 329 }; 330 331 struct mlx5_ib_ubuffer { 332 struct ib_umem *umem; 333 int buf_size; 334 u64 buf_addr; 335 }; 336 337 struct mlx5_ib_qp_base { 338 struct mlx5_ib_qp *container_mibqp; 339 struct mlx5_core_qp mqp; 340 struct mlx5_ib_ubuffer ubuffer; 341 }; 342 343 struct mlx5_ib_qp_trans { 344 struct mlx5_ib_qp_base base; 345 u16 xrcdn; 346 u8 alt_port; 347 u8 atomic_rd_en; 348 u8 resp_depth; 349 }; 350 351 struct mlx5_ib_rss_qp { 352 u32 tirn; 353 }; 354 355 struct mlx5_ib_rq { 356 struct mlx5_ib_qp_base base; 357 struct mlx5_ib_wq *rq; 358 struct mlx5_ib_ubuffer ubuffer; 359 struct mlx5_db *doorbell; 360 u32 tirn; 361 u8 state; 362 u32 flags; 363 }; 364 365 struct mlx5_ib_sq { 366 struct mlx5_ib_qp_base base; 367 struct mlx5_ib_wq *sq; 368 struct mlx5_ib_ubuffer ubuffer; 369 struct mlx5_db *doorbell; 370 struct mlx5_flow_handle *flow_rule; 371 u32 tisn; 372 u8 state; 373 }; 374 375 struct mlx5_ib_raw_packet_qp { 376 struct mlx5_ib_sq sq; 377 struct mlx5_ib_rq rq; 378 }; 379 380 struct mlx5_bf { 381 int buf_size; 382 unsigned long offset; 383 struct mlx5_sq_bfreg *bfreg; 384 }; 385 386 struct mlx5_ib_dct { 387 struct mlx5_core_dct mdct; 388 u32 *in; 389 }; 390 391 struct mlx5_ib_qp { 392 struct ib_qp ibqp; 393 union { 394 struct mlx5_ib_qp_trans trans_qp; 395 struct mlx5_ib_raw_packet_qp raw_packet_qp; 396 struct mlx5_ib_rss_qp rss_qp; 397 struct mlx5_ib_dct dct; 398 }; 399 struct mlx5_frag_buf buf; 400 401 struct mlx5_db db; 402 struct mlx5_ib_wq rq; 403 404 u8 sq_signal_bits; 405 u8 next_fence; 406 struct mlx5_ib_wq sq; 407 408 /* serialize qp state modifications 409 */ 410 struct mutex mutex; 411 u32 flags; 412 u8 port; 413 u8 state; 414 int wq_sig; 415 int scat_cqe; 416 int max_inline_data; 417 struct mlx5_bf bf; 418 int has_rq; 419 420 /* only for user space QPs. For kernel 421 * we have it from the bf object 422 */ 423 int bfregn; 424 425 int create_type; 426 427 /* Store signature errors */ 428 bool signature_en; 429 430 struct list_head qps_list; 431 struct list_head cq_recv_list; 432 struct list_head cq_send_list; 433 struct mlx5_rate_limit rl; 434 u32 underlay_qpn; 435 u32 flags_en; 436 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 437 enum ib_qp_type qp_sub_type; 438 }; 439 440 struct mlx5_ib_cq_buf { 441 struct mlx5_frag_buf_ctrl fbc; 442 struct mlx5_frag_buf frag_buf; 443 struct ib_umem *umem; 444 int cqe_size; 445 int nent; 446 }; 447 448 enum mlx5_ib_qp_flags { 449 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 450 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 451 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 452 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 453 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 454 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 455 /* QP uses 1 as its source QP number */ 456 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 457 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 458 MLX5_IB_QP_RSS = 1 << 8, 459 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 460 MLX5_IB_QP_UNDERLAY = 1 << 10, 461 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 462 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 463 }; 464 465 struct mlx5_umr_wr { 466 struct ib_send_wr wr; 467 u64 virt_addr; 468 u64 offset; 469 struct ib_pd *pd; 470 unsigned int page_shift; 471 unsigned int xlt_size; 472 u64 length; 473 int access_flags; 474 u32 mkey; 475 }; 476 477 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 478 { 479 return container_of(wr, struct mlx5_umr_wr, wr); 480 } 481 482 struct mlx5_shared_mr_info { 483 int mr_id; 484 struct ib_umem *umem; 485 }; 486 487 enum mlx5_ib_cq_pr_flags { 488 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 489 }; 490 491 struct mlx5_ib_cq { 492 struct ib_cq ibcq; 493 struct mlx5_core_cq mcq; 494 struct mlx5_ib_cq_buf buf; 495 struct mlx5_db db; 496 497 /* serialize access to the CQ 498 */ 499 spinlock_t lock; 500 501 /* protect resize cq 502 */ 503 struct mutex resize_mutex; 504 struct mlx5_ib_cq_buf *resize_buf; 505 struct ib_umem *resize_umem; 506 int cqe_size; 507 struct list_head list_send_qp; 508 struct list_head list_recv_qp; 509 u32 create_flags; 510 struct list_head wc_list; 511 enum ib_cq_notify_flags notify_flags; 512 struct work_struct notify_work; 513 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 514 }; 515 516 struct mlx5_ib_wc { 517 struct ib_wc wc; 518 struct list_head list; 519 }; 520 521 struct mlx5_ib_srq { 522 struct ib_srq ibsrq; 523 struct mlx5_core_srq msrq; 524 struct mlx5_frag_buf buf; 525 struct mlx5_db db; 526 u64 *wrid; 527 /* protect SRQ hanlding 528 */ 529 spinlock_t lock; 530 int head; 531 int tail; 532 u16 wqe_ctr; 533 struct ib_umem *umem; 534 /* serialize arming a SRQ 535 */ 536 struct mutex mutex; 537 int wq_sig; 538 }; 539 540 struct mlx5_ib_xrcd { 541 struct ib_xrcd ibxrcd; 542 u32 xrcdn; 543 u16 uid; 544 }; 545 546 enum mlx5_ib_mtt_access_flags { 547 MLX5_IB_MTT_READ = (1 << 0), 548 MLX5_IB_MTT_WRITE = (1 << 1), 549 }; 550 551 struct mlx5_ib_dm { 552 struct ib_dm ibdm; 553 phys_addr_t dev_addr; 554 }; 555 556 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 557 558 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 559 IB_ACCESS_REMOTE_WRITE |\ 560 IB_ACCESS_REMOTE_READ |\ 561 IB_ACCESS_REMOTE_ATOMIC |\ 562 IB_ZERO_BASED) 563 564 struct mlx5_ib_mr { 565 struct ib_mr ibmr; 566 void *descs; 567 dma_addr_t desc_map; 568 int ndescs; 569 int max_descs; 570 int desc_size; 571 int access_mode; 572 struct mlx5_core_mkey mmkey; 573 struct ib_umem *umem; 574 struct mlx5_shared_mr_info *smr_info; 575 struct list_head list; 576 int order; 577 bool allocated_from_cache; 578 int npages; 579 struct mlx5_ib_dev *dev; 580 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 581 struct mlx5_core_sig_ctx *sig; 582 int live; 583 void *descs_alloc; 584 int access_flags; /* Needed for rereg MR */ 585 586 struct mlx5_ib_mr *parent; 587 atomic_t num_leaf_free; 588 wait_queue_head_t q_leaf_free; 589 }; 590 591 struct mlx5_ib_mw { 592 struct ib_mw ibmw; 593 struct mlx5_core_mkey mmkey; 594 int ndescs; 595 }; 596 597 struct mlx5_ib_umr_context { 598 struct ib_cqe cqe; 599 enum ib_wc_status status; 600 struct completion done; 601 }; 602 603 struct umr_common { 604 struct ib_pd *pd; 605 struct ib_cq *cq; 606 struct ib_qp *qp; 607 /* control access to UMR QP 608 */ 609 struct semaphore sem; 610 }; 611 612 enum { 613 MLX5_FMR_INVALID, 614 MLX5_FMR_VALID, 615 MLX5_FMR_BUSY, 616 }; 617 618 struct mlx5_cache_ent { 619 struct list_head head; 620 /* sync access to the cahce entry 621 */ 622 spinlock_t lock; 623 624 625 struct dentry *dir; 626 char name[4]; 627 u32 order; 628 u32 xlt; 629 u32 access_mode; 630 u32 page; 631 632 u32 size; 633 u32 cur; 634 u32 miss; 635 u32 limit; 636 637 struct dentry *fsize; 638 struct dentry *fcur; 639 struct dentry *fmiss; 640 struct dentry *flimit; 641 642 struct mlx5_ib_dev *dev; 643 struct work_struct work; 644 struct delayed_work dwork; 645 int pending; 646 struct completion compl; 647 }; 648 649 struct mlx5_mr_cache { 650 struct workqueue_struct *wq; 651 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 652 int stopped; 653 struct dentry *root; 654 unsigned long last_add; 655 }; 656 657 struct mlx5_ib_gsi_qp; 658 659 struct mlx5_ib_port_resources { 660 struct mlx5_ib_resources *devr; 661 struct mlx5_ib_gsi_qp *gsi; 662 struct work_struct pkey_change_work; 663 }; 664 665 struct mlx5_ib_resources { 666 struct ib_cq *c0; 667 struct ib_xrcd *x0; 668 struct ib_xrcd *x1; 669 struct ib_pd *p0; 670 struct ib_srq *s0; 671 struct ib_srq *s1; 672 struct mlx5_ib_port_resources ports[2]; 673 /* Protects changes to the port resources */ 674 struct mutex mutex; 675 }; 676 677 struct mlx5_ib_counters { 678 const char **names; 679 size_t *offsets; 680 u32 num_q_counters; 681 u32 num_cong_counters; 682 u32 num_ext_ppcnt_counters; 683 u16 set_id; 684 bool set_id_valid; 685 }; 686 687 struct mlx5_ib_multiport_info; 688 689 struct mlx5_ib_multiport { 690 struct mlx5_ib_multiport_info *mpi; 691 /* To be held when accessing the multiport info */ 692 spinlock_t mpi_lock; 693 }; 694 695 struct mlx5_ib_port { 696 struct mlx5_ib_counters cnts; 697 struct mlx5_ib_multiport mp; 698 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 699 }; 700 701 struct mlx5_roce { 702 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 703 * netdev pointer 704 */ 705 rwlock_t netdev_lock; 706 struct net_device *netdev; 707 struct notifier_block nb; 708 atomic_t tx_port_affinity; 709 enum ib_port_state last_port_state; 710 struct mlx5_ib_dev *dev; 711 u8 native_port_num; 712 }; 713 714 struct mlx5_ib_dbg_param { 715 int offset; 716 struct mlx5_ib_dev *dev; 717 struct dentry *dentry; 718 u8 port_num; 719 }; 720 721 enum mlx5_ib_dbg_cc_types { 722 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 723 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 724 MLX5_IB_DBG_CC_RP_TIME_RESET, 725 MLX5_IB_DBG_CC_RP_BYTE_RESET, 726 MLX5_IB_DBG_CC_RP_THRESHOLD, 727 MLX5_IB_DBG_CC_RP_AI_RATE, 728 MLX5_IB_DBG_CC_RP_HAI_RATE, 729 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 730 MLX5_IB_DBG_CC_RP_MIN_RATE, 731 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 732 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 733 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 734 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 735 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 736 MLX5_IB_DBG_CC_RP_GD, 737 MLX5_IB_DBG_CC_NP_CNP_DSCP, 738 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 739 MLX5_IB_DBG_CC_NP_CNP_PRIO, 740 MLX5_IB_DBG_CC_MAX, 741 }; 742 743 struct mlx5_ib_dbg_cc_params { 744 struct dentry *root; 745 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 746 }; 747 748 enum { 749 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 750 }; 751 752 struct mlx5_ib_dbg_delay_drop { 753 struct dentry *dir_debugfs; 754 struct dentry *rqs_cnt_debugfs; 755 struct dentry *events_cnt_debugfs; 756 struct dentry *timeout_debugfs; 757 }; 758 759 struct mlx5_ib_delay_drop { 760 struct mlx5_ib_dev *dev; 761 struct work_struct delay_drop_work; 762 /* serialize setting of delay drop */ 763 struct mutex lock; 764 u32 timeout; 765 bool activate; 766 atomic_t events_cnt; 767 atomic_t rqs_cnt; 768 struct mlx5_ib_dbg_delay_drop *dbg; 769 }; 770 771 enum mlx5_ib_stages { 772 MLX5_IB_STAGE_INIT, 773 MLX5_IB_STAGE_FLOW_DB, 774 MLX5_IB_STAGE_CAPS, 775 MLX5_IB_STAGE_NON_DEFAULT_CB, 776 MLX5_IB_STAGE_ROCE, 777 MLX5_IB_STAGE_DEVICE_RESOURCES, 778 MLX5_IB_STAGE_ODP, 779 MLX5_IB_STAGE_COUNTERS, 780 MLX5_IB_STAGE_CONG_DEBUGFS, 781 MLX5_IB_STAGE_UAR, 782 MLX5_IB_STAGE_BFREG, 783 MLX5_IB_STAGE_PRE_IB_REG_UMR, 784 MLX5_IB_STAGE_SPECS, 785 MLX5_IB_STAGE_IB_REG, 786 MLX5_IB_STAGE_POST_IB_REG_UMR, 787 MLX5_IB_STAGE_DELAY_DROP, 788 MLX5_IB_STAGE_CLASS_ATTR, 789 MLX5_IB_STAGE_REP_REG, 790 MLX5_IB_STAGE_MAX, 791 }; 792 793 struct mlx5_ib_stage { 794 int (*init)(struct mlx5_ib_dev *dev); 795 void (*cleanup)(struct mlx5_ib_dev *dev); 796 }; 797 798 #define STAGE_CREATE(_stage, _init, _cleanup) \ 799 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 800 801 struct mlx5_ib_profile { 802 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 803 }; 804 805 struct mlx5_ib_multiport_info { 806 struct list_head list; 807 struct mlx5_ib_dev *ibdev; 808 struct mlx5_core_dev *mdev; 809 struct completion unref_comp; 810 u64 sys_image_guid; 811 u32 mdev_refcnt; 812 bool is_master; 813 bool unaffiliate; 814 }; 815 816 struct mlx5_ib_flow_action { 817 struct ib_flow_action ib_action; 818 union { 819 struct { 820 u64 ib_flags; 821 struct mlx5_accel_esp_xfrm *ctx; 822 } esp_aes_gcm; 823 struct { 824 struct mlx5_ib_dev *dev; 825 u32 sub_type; 826 u32 action_id; 827 } flow_action_raw; 828 }; 829 }; 830 831 struct mlx5_memic { 832 struct mlx5_core_dev *dev; 833 spinlock_t memic_lock; 834 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 835 }; 836 837 struct mlx5_read_counters_attr { 838 struct mlx5_fc *hw_cntrs_hndl; 839 u64 *out; 840 u32 flags; 841 }; 842 843 enum mlx5_ib_counters_type { 844 MLX5_IB_COUNTERS_FLOW, 845 }; 846 847 struct mlx5_ib_mcounters { 848 struct ib_counters ibcntrs; 849 enum mlx5_ib_counters_type type; 850 /* number of counters supported for this counters type */ 851 u32 counters_num; 852 struct mlx5_fc *hw_cntrs_hndl; 853 /* read function for this counters type */ 854 int (*read_counters)(struct ib_device *ibdev, 855 struct mlx5_read_counters_attr *read_attr); 856 /* max index set as part of create_flow */ 857 u32 cntrs_max_index; 858 /* number of counters data entries (<description,index> pair) */ 859 u32 ncounters; 860 /* counters data array for descriptions and indexes */ 861 struct mlx5_ib_flow_counters_desc *counters_data; 862 /* protects access to mcounters internal data */ 863 struct mutex mcntrs_mutex; 864 }; 865 866 static inline struct mlx5_ib_mcounters * 867 to_mcounters(struct ib_counters *ibcntrs) 868 { 869 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 870 } 871 872 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 873 bool is_egress, 874 struct mlx5_flow_act *action); 875 struct mlx5_ib_lb_state { 876 /* protect the user_td */ 877 struct mutex mutex; 878 u32 user_td; 879 int qps; 880 bool enabled; 881 }; 882 883 struct mlx5_ib_dev { 884 struct ib_device ib_dev; 885 const struct uverbs_object_tree_def *driver_trees[7]; 886 struct mlx5_core_dev *mdev; 887 struct mlx5_roce roce[MLX5_MAX_PORTS]; 888 int num_ports; 889 /* serialize update of capability mask 890 */ 891 struct mutex cap_mask_mutex; 892 bool ib_active; 893 struct umr_common umrc; 894 /* sync used page count stats 895 */ 896 struct mlx5_ib_resources devr; 897 struct mlx5_mr_cache cache; 898 struct timer_list delay_timer; 899 /* Prevents soft lock on massive reg MRs */ 900 struct mutex slow_path_mutex; 901 int fill_delay; 902 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 903 struct ib_odp_caps odp_caps; 904 u64 odp_max_size; 905 /* 906 * Sleepable RCU that prevents destruction of MRs while they are still 907 * being used by a page fault handler. 908 */ 909 struct srcu_struct mr_srcu; 910 u32 null_mkey; 911 #endif 912 struct mlx5_ib_flow_db *flow_db; 913 /* protect resources needed as part of reset flow */ 914 spinlock_t reset_flow_resource_lock; 915 struct list_head qp_list; 916 /* Array with num_ports elements */ 917 struct mlx5_ib_port *port; 918 struct mlx5_sq_bfreg bfreg; 919 struct mlx5_sq_bfreg fp_bfreg; 920 struct mlx5_ib_delay_drop delay_drop; 921 const struct mlx5_ib_profile *profile; 922 struct mlx5_eswitch_rep *rep; 923 924 struct mlx5_ib_lb_state lb; 925 u8 umr_fence; 926 struct list_head ib_dev_list; 927 u64 sys_image_guid; 928 struct mlx5_memic memic; 929 u16 devx_whitelist_uid; 930 }; 931 932 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 933 { 934 return container_of(mcq, struct mlx5_ib_cq, mcq); 935 } 936 937 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 938 { 939 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 940 } 941 942 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 943 { 944 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 945 } 946 947 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 948 { 949 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 950 } 951 952 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 953 { 954 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 955 } 956 957 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 958 { 959 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 960 } 961 962 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 963 { 964 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 965 } 966 967 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 968 { 969 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 970 } 971 972 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 973 { 974 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 975 } 976 977 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 978 { 979 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 980 } 981 982 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 983 { 984 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 985 } 986 987 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 988 { 989 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 990 } 991 992 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 993 { 994 return container_of(msrq, struct mlx5_ib_srq, msrq); 995 } 996 997 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 998 { 999 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1000 } 1001 1002 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1003 { 1004 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1005 } 1006 1007 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1008 { 1009 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1010 } 1011 1012 static inline struct mlx5_ib_flow_action * 1013 to_mflow_act(struct ib_flow_action *ibact) 1014 { 1015 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1016 } 1017 1018 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1019 struct mlx5_db *db); 1020 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1021 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1022 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1023 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1024 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 1025 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1026 const void *in_mad, void *response_mad); 1027 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 1028 struct ib_udata *udata); 1029 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1030 int mlx5_ib_destroy_ah(struct ib_ah *ah); 1031 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 1032 struct ib_srq_init_attr *init_attr, 1033 struct ib_udata *udata); 1034 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1035 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1036 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1037 int mlx5_ib_destroy_srq(struct ib_srq *srq); 1038 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1039 const struct ib_recv_wr **bad_wr); 1040 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1041 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1042 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1043 struct ib_qp_init_attr *init_attr, 1044 struct ib_udata *udata); 1045 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1046 int attr_mask, struct ib_udata *udata); 1047 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1048 struct ib_qp_init_attr *qp_init_attr); 1049 int mlx5_ib_destroy_qp(struct ib_qp *qp); 1050 void mlx5_ib_drain_sq(struct ib_qp *qp); 1051 void mlx5_ib_drain_rq(struct ib_qp *qp); 1052 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1053 const struct ib_send_wr **bad_wr); 1054 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1055 const struct ib_recv_wr **bad_wr); 1056 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 1057 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 1058 void *buffer, u32 length, 1059 struct mlx5_ib_qp_base *base); 1060 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 1061 const struct ib_cq_init_attr *attr, 1062 struct ib_ucontext *context, 1063 struct ib_udata *udata); 1064 int mlx5_ib_destroy_cq(struct ib_cq *cq); 1065 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1066 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1067 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1068 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1069 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1070 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1071 u64 virt_addr, int access_flags, 1072 struct ib_udata *udata); 1073 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1074 struct ib_udata *udata); 1075 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1076 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1077 int page_shift, int flags); 1078 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1079 int access_flags); 1080 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1081 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1082 u64 length, u64 virt_addr, int access_flags, 1083 struct ib_pd *pd, struct ib_udata *udata); 1084 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 1085 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 1086 enum ib_mr_type mr_type, 1087 u32 max_num_sg); 1088 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1089 unsigned int *sg_offset); 1090 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1091 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1092 const struct ib_mad_hdr *in, size_t in_mad_size, 1093 struct ib_mad_hdr *out, size_t *out_mad_size, 1094 u16 *out_mad_pkey_index); 1095 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1096 struct ib_ucontext *context, 1097 struct ib_udata *udata); 1098 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 1099 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1100 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1101 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1102 struct ib_smp *out_mad); 1103 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1104 __be64 *sys_image_guid); 1105 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1106 u16 *max_pkeys); 1107 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1108 u32 *vendor_id); 1109 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1110 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1111 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1112 u16 *pkey); 1113 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1114 union ib_gid *gid); 1115 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1116 struct ib_port_attr *props); 1117 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1118 struct ib_port_attr *props); 1119 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1120 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1121 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1122 unsigned long max_page_shift, 1123 int *count, int *shift, 1124 int *ncont, int *order); 1125 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1126 int page_shift, size_t offset, size_t num_pages, 1127 __be64 *pas, int access_flags); 1128 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1129 int page_shift, __be64 *pas, int access_flags); 1130 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1131 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1132 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1133 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1134 1135 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1136 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1137 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1138 struct ib_mr_status *mr_status); 1139 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1140 struct ib_wq_init_attr *init_attr, 1141 struct ib_udata *udata); 1142 int mlx5_ib_destroy_wq(struct ib_wq *wq); 1143 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1144 u32 wq_attr_mask, struct ib_udata *udata); 1145 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1146 struct ib_rwq_ind_table_init_attr *init_attr, 1147 struct ib_udata *udata); 1148 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1149 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); 1150 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1151 struct ib_ucontext *context, 1152 struct ib_dm_alloc_attr *attr, 1153 struct uverbs_attr_bundle *attrs); 1154 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm); 1155 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1156 struct ib_dm_mr_attr *attr, 1157 struct uverbs_attr_bundle *attrs); 1158 1159 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1160 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1161 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, 1162 struct mlx5_pagefault *pfault); 1163 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1164 int __init mlx5_ib_odp_init(void); 1165 void mlx5_ib_odp_cleanup(void); 1166 void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start, 1167 unsigned long end); 1168 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1169 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1170 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1171 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1172 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1173 { 1174 return; 1175 } 1176 1177 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1178 static inline int mlx5_ib_odp_init(void) { return 0; } 1179 static inline void mlx5_ib_odp_cleanup(void) {} 1180 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1181 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1182 size_t nentries, struct mlx5_ib_mr *mr, 1183 int flags) {} 1184 1185 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1186 1187 /* Needed for rep profile */ 1188 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev); 1189 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev); 1190 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev); 1191 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev); 1192 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev); 1193 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev); 1194 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev); 1195 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev); 1196 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev); 1197 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev); 1198 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev); 1199 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev); 1200 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev); 1201 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev); 1202 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev); 1203 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev); 1204 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev); 1205 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1206 const struct mlx5_ib_profile *profile, 1207 int stage); 1208 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1209 const struct mlx5_ib_profile *profile); 1210 1211 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1212 u8 port, struct ifla_vf_info *info); 1213 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1214 u8 port, int state); 1215 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1216 u8 port, struct ifla_vf_stats *stats); 1217 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1218 u64 guid, int type); 1219 1220 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 1221 const struct ib_gid_attr *attr); 1222 1223 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1224 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1225 1226 /* GSI QP helper functions */ 1227 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1228 struct ib_qp_init_attr *init_attr); 1229 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1230 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1231 int attr_mask); 1232 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1233 int qp_attr_mask, 1234 struct ib_qp_init_attr *qp_init_attr); 1235 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1236 const struct ib_send_wr **bad_wr); 1237 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1238 const struct ib_recv_wr **bad_wr); 1239 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1240 1241 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1242 1243 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1244 int bfregn); 1245 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1246 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1247 u8 ib_port_num, 1248 u8 *native_port_num); 1249 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1250 u8 port_num); 1251 1252 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1253 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev); 1254 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); 1255 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void); 1256 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1257 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1258 struct mlx5_flow_act *flow_act, void *cmd_in, int inlen, 1259 int dest_id, int dest_type); 1260 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1261 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root); 1262 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); 1263 #else 1264 static inline int 1265 mlx5_ib_devx_create(struct mlx5_ib_dev *dev) { return -EOPNOTSUPP; }; 1266 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} 1267 static inline const struct uverbs_object_tree_def * 1268 mlx5_ib_get_devx_tree(void) { return NULL; } 1269 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1270 int *dest_type) 1271 { 1272 return false; 1273 } 1274 static inline int 1275 mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root) 1276 { 1277 return 0; 1278 } 1279 static inline void 1280 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) 1281 { 1282 return; 1283 }; 1284 #endif 1285 static inline void init_query_mad(struct ib_smp *mad) 1286 { 1287 mad->base_version = 1; 1288 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1289 mad->class_version = 1; 1290 mad->method = IB_MGMT_METHOD_GET; 1291 } 1292 1293 static inline u8 convert_access(int acc) 1294 { 1295 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1296 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1297 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1298 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1299 MLX5_PERM_LOCAL_READ; 1300 } 1301 1302 static inline int is_qp1(enum ib_qp_type qp_type) 1303 { 1304 return qp_type == MLX5_IB_QPT_HW_GSI; 1305 } 1306 1307 #define MLX5_MAX_UMR_SHIFT 16 1308 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1309 1310 static inline u32 check_cq_create_flags(u32 flags) 1311 { 1312 /* 1313 * It returns non-zero value for unsupported CQ 1314 * create flags, otherwise it returns zero. 1315 */ 1316 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1317 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1318 } 1319 1320 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1321 u32 *user_index) 1322 { 1323 if (cqe_version) { 1324 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1325 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1326 return -EINVAL; 1327 *user_index = cmd_uidx; 1328 } else { 1329 *user_index = MLX5_IB_DEFAULT_UIDX; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1336 struct mlx5_ib_create_qp *ucmd, 1337 int inlen, 1338 u32 *user_index) 1339 { 1340 u8 cqe_version = ucontext->cqe_version; 1341 1342 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1343 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1344 return 0; 1345 1346 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1347 !!cqe_version)) 1348 return -EINVAL; 1349 1350 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1351 } 1352 1353 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1354 struct mlx5_ib_create_srq *ucmd, 1355 int inlen, 1356 u32 *user_index) 1357 { 1358 u8 cqe_version = ucontext->cqe_version; 1359 1360 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1361 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1362 return 0; 1363 1364 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1365 !!cqe_version)) 1366 return -EINVAL; 1367 1368 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1369 } 1370 1371 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1372 { 1373 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1374 MLX5_UARS_IN_PAGE : 1; 1375 } 1376 1377 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1378 struct mlx5_bfreg_info *bfregi) 1379 { 1380 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1381 } 1382 1383 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1384 void mlx5_ib_put_xlt_emergency_page(void); 1385 1386 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1387 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1388 bool dyn_bfreg); 1389 #endif /* MLX5_IB_H */ 1390