1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_umem.h> 40 #include <rdma/ib_smi.h> 41 #include <linux/mlx5/driver.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/fs.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/types.h> 46 #include <linux/mlx5/transobj.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/mlx5-abi.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/mlx5_user_ioctl_verbs.h> 52 53 #include "srq.h" 54 55 #define mlx5_ib_dbg(_dev, format, arg...) \ 56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 57 __LINE__, current->pid, ##arg) 58 59 #define mlx5_ib_err(_dev, format, arg...) \ 60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 61 __LINE__, current->pid, ##arg) 62 63 #define mlx5_ib_warn(_dev, format, arg...) \ 64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 65 __LINE__, current->pid, ##arg) 66 67 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 68 sizeof(((type *)0)->fld) <= (sz)) 69 #define MLX5_IB_DEFAULT_UIDX 0xffffff 70 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 71 72 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 73 74 enum { 75 MLX5_IB_MMAP_OFFSET_START = 9, 76 MLX5_IB_MMAP_OFFSET_END = 255, 77 }; 78 79 enum { 80 MLX5_IB_MMAP_CMD_SHIFT = 8, 81 MLX5_IB_MMAP_CMD_MASK = 0xff, 82 }; 83 84 enum { 85 MLX5_RES_SCAT_DATA32_CQE = 0x1, 86 MLX5_RES_SCAT_DATA64_CQE = 0x2, 87 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 88 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 89 }; 90 91 enum mlx5_ib_mad_ifc_flags { 92 MLX5_MAD_IFC_IGNORE_MKEY = 1, 93 MLX5_MAD_IFC_IGNORE_BKEY = 2, 94 MLX5_MAD_IFC_NET_VIEW = 4, 95 }; 96 97 enum { 98 MLX5_CROSS_CHANNEL_BFREG = 0, 99 }; 100 101 enum { 102 MLX5_CQE_VERSION_V0, 103 MLX5_CQE_VERSION_V1, 104 }; 105 106 enum { 107 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 108 MLX5_TM_MAX_SGE = 1, 109 }; 110 111 enum { 112 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 113 MLX5_IB_INVALID_BFREG = BIT(31), 114 }; 115 116 enum { 117 MLX5_MAX_MEMIC_PAGES = 0x100, 118 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 119 }; 120 121 enum { 122 MLX5_MEMIC_BASE_ALIGN = 6, 123 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 124 }; 125 126 enum mlx5_ib_mmap_type { 127 MLX5_IB_MMAP_TYPE_MEMIC = 1, 128 MLX5_IB_MMAP_TYPE_VAR = 2, 129 }; 130 131 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) \ 132 (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) 133 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) 134 135 struct mlx5_ib_ucontext { 136 struct ib_ucontext ibucontext; 137 struct list_head db_page_list; 138 139 /* protect doorbell record alloc/free 140 */ 141 struct mutex db_page_mutex; 142 struct mlx5_bfreg_info bfregi; 143 u8 cqe_version; 144 /* Transport Domain number */ 145 u32 tdn; 146 147 u64 lib_caps; 148 u16 devx_uid; 149 /* For RoCE LAG TX affinity */ 150 atomic_t tx_port_affinity; 151 }; 152 153 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 154 { 155 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 156 } 157 158 struct mlx5_ib_pd { 159 struct ib_pd ibpd; 160 u32 pdn; 161 u16 uid; 162 }; 163 164 enum { 165 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 166 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 167 MLX5_IB_FLOW_ACTION_DECAP, 168 }; 169 170 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 171 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 172 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 173 #error "Invalid number of bypass priorities" 174 #endif 175 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 176 177 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 178 #define MLX5_IB_NUM_SNIFFER_FTS 2 179 #define MLX5_IB_NUM_EGRESS_FTS 1 180 struct mlx5_ib_flow_prio { 181 struct mlx5_flow_table *flow_table; 182 unsigned int refcount; 183 }; 184 185 struct mlx5_ib_flow_handler { 186 struct list_head list; 187 struct ib_flow ibflow; 188 struct mlx5_ib_flow_prio *prio; 189 struct mlx5_flow_handle *rule; 190 struct ib_counters *ibcounters; 191 struct mlx5_ib_dev *dev; 192 struct mlx5_ib_flow_matcher *flow_matcher; 193 }; 194 195 struct mlx5_ib_flow_matcher { 196 struct mlx5_ib_match_params matcher_mask; 197 int mask_len; 198 enum mlx5_ib_flow_type flow_type; 199 enum mlx5_flow_namespace_type ns_type; 200 u16 priority; 201 struct mlx5_core_dev *mdev; 202 atomic_t usecnt; 203 u8 match_criteria_enable; 204 }; 205 206 struct mlx5_ib_flow_db { 207 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 208 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 209 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 210 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 211 struct mlx5_ib_flow_prio fdb; 212 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 213 struct mlx5_flow_table *lag_demux_ft; 214 /* Protect flow steering bypass flow tables 215 * when add/del flow rules. 216 * only single add/removal of flow steering rule could be done 217 * simultaneously. 218 */ 219 struct mutex lock; 220 }; 221 222 /* Use macros here so that don't have to duplicate 223 * enum ib_send_flags and enum ib_qp_type for low-level driver 224 */ 225 226 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 227 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 228 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 229 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 230 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 231 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 232 233 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 234 /* 235 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 236 * creates the actual hardware QP. 237 */ 238 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 239 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 240 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 241 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 242 243 #define MLX5_IB_UMR_OCTOWORD 16 244 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 245 246 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 247 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 248 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 249 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 250 #define MLX5_IB_UPD_XLT_PD BIT(4) 251 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 252 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 253 254 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 255 * 256 * These flags are intended for internal use by the mlx5_ib driver, and they 257 * rely on the range reserved for that use in the ib_qp_create_flags enum. 258 */ 259 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 260 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 261 262 struct wr_list { 263 u16 opcode; 264 u16 next; 265 }; 266 267 enum mlx5_ib_rq_flags { 268 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 269 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 270 }; 271 272 struct mlx5_ib_wq { 273 struct mlx5_frag_buf_ctrl fbc; 274 u64 *wrid; 275 u32 *wr_data; 276 struct wr_list *w_list; 277 unsigned *wqe_head; 278 u16 unsig_count; 279 280 /* serialize post to the work queue 281 */ 282 spinlock_t lock; 283 int wqe_cnt; 284 int max_post; 285 int max_gs; 286 int offset; 287 int wqe_shift; 288 unsigned head; 289 unsigned tail; 290 u16 cur_post; 291 u16 last_poll; 292 void *cur_edge; 293 }; 294 295 enum mlx5_ib_wq_flags { 296 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 297 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 298 }; 299 300 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 301 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 302 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 303 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 304 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 305 306 struct mlx5_ib_rwq { 307 struct ib_wq ibwq; 308 struct mlx5_core_qp core_qp; 309 u32 rq_num_pas; 310 u32 log_rq_stride; 311 u32 log_rq_size; 312 u32 rq_page_offset; 313 u32 log_page_size; 314 u32 log_num_strides; 315 u32 two_byte_shift_en; 316 u32 single_stride_log_num_of_bytes; 317 struct ib_umem *umem; 318 size_t buf_size; 319 unsigned int page_shift; 320 int create_type; 321 struct mlx5_db db; 322 u32 user_index; 323 u32 wqe_count; 324 u32 wqe_shift; 325 int wq_sig; 326 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 327 }; 328 329 enum { 330 MLX5_QP_USER, 331 MLX5_QP_KERNEL, 332 MLX5_QP_EMPTY 333 }; 334 335 enum { 336 MLX5_WQ_USER, 337 MLX5_WQ_KERNEL 338 }; 339 340 struct mlx5_ib_rwq_ind_table { 341 struct ib_rwq_ind_table ib_rwq_ind_tbl; 342 u32 rqtn; 343 u16 uid; 344 }; 345 346 struct mlx5_ib_ubuffer { 347 struct ib_umem *umem; 348 int buf_size; 349 u64 buf_addr; 350 }; 351 352 struct mlx5_ib_qp_base { 353 struct mlx5_ib_qp *container_mibqp; 354 struct mlx5_core_qp mqp; 355 struct mlx5_ib_ubuffer ubuffer; 356 }; 357 358 struct mlx5_ib_qp_trans { 359 struct mlx5_ib_qp_base base; 360 u16 xrcdn; 361 u8 alt_port; 362 u8 atomic_rd_en; 363 u8 resp_depth; 364 }; 365 366 struct mlx5_ib_rss_qp { 367 u32 tirn; 368 }; 369 370 struct mlx5_ib_rq { 371 struct mlx5_ib_qp_base base; 372 struct mlx5_ib_wq *rq; 373 struct mlx5_ib_ubuffer ubuffer; 374 struct mlx5_db *doorbell; 375 u32 tirn; 376 u8 state; 377 u32 flags; 378 }; 379 380 struct mlx5_ib_sq { 381 struct mlx5_ib_qp_base base; 382 struct mlx5_ib_wq *sq; 383 struct mlx5_ib_ubuffer ubuffer; 384 struct mlx5_db *doorbell; 385 struct mlx5_flow_handle *flow_rule; 386 u32 tisn; 387 u8 state; 388 }; 389 390 struct mlx5_ib_raw_packet_qp { 391 struct mlx5_ib_sq sq; 392 struct mlx5_ib_rq rq; 393 }; 394 395 struct mlx5_bf { 396 int buf_size; 397 unsigned long offset; 398 struct mlx5_sq_bfreg *bfreg; 399 }; 400 401 struct mlx5_ib_dct { 402 struct mlx5_core_dct mdct; 403 u32 *in; 404 }; 405 406 struct mlx5_ib_qp { 407 struct ib_qp ibqp; 408 union { 409 struct mlx5_ib_qp_trans trans_qp; 410 struct mlx5_ib_raw_packet_qp raw_packet_qp; 411 struct mlx5_ib_rss_qp rss_qp; 412 struct mlx5_ib_dct dct; 413 }; 414 struct mlx5_frag_buf buf; 415 416 struct mlx5_db db; 417 struct mlx5_ib_wq rq; 418 419 u8 sq_signal_bits; 420 u8 next_fence; 421 struct mlx5_ib_wq sq; 422 423 /* serialize qp state modifications 424 */ 425 struct mutex mutex; 426 u32 flags; 427 u8 port; 428 u8 state; 429 int wq_sig; 430 int scat_cqe; 431 int max_inline_data; 432 struct mlx5_bf bf; 433 int has_rq; 434 435 /* only for user space QPs. For kernel 436 * we have it from the bf object 437 */ 438 int bfregn; 439 440 int create_type; 441 442 struct list_head qps_list; 443 struct list_head cq_recv_list; 444 struct list_head cq_send_list; 445 struct mlx5_rate_limit rl; 446 u32 underlay_qpn; 447 u32 flags_en; 448 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 449 enum ib_qp_type qp_sub_type; 450 /* A flag to indicate if there's a new counter is configured 451 * but not take effective 452 */ 453 u32 counter_pending; 454 }; 455 456 struct mlx5_ib_cq_buf { 457 struct mlx5_frag_buf_ctrl fbc; 458 struct mlx5_frag_buf frag_buf; 459 struct ib_umem *umem; 460 int cqe_size; 461 int nent; 462 }; 463 464 enum mlx5_ib_qp_flags { 465 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 466 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 467 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 468 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 469 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 470 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 471 /* QP uses 1 as its source QP number */ 472 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 473 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 474 MLX5_IB_QP_RSS = 1 << 8, 475 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 476 MLX5_IB_QP_UNDERLAY = 1 << 10, 477 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 478 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 479 MLX5_IB_QP_PACKET_BASED_CREDIT = 1 << 13, 480 }; 481 482 struct mlx5_umr_wr { 483 struct ib_send_wr wr; 484 u64 virt_addr; 485 u64 offset; 486 struct ib_pd *pd; 487 unsigned int page_shift; 488 unsigned int xlt_size; 489 u64 length; 490 int access_flags; 491 u32 mkey; 492 u8 ignore_free_state:1; 493 }; 494 495 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 496 { 497 return container_of(wr, struct mlx5_umr_wr, wr); 498 } 499 500 struct mlx5_shared_mr_info { 501 int mr_id; 502 struct ib_umem *umem; 503 }; 504 505 enum mlx5_ib_cq_pr_flags { 506 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 507 }; 508 509 struct mlx5_ib_cq { 510 struct ib_cq ibcq; 511 struct mlx5_core_cq mcq; 512 struct mlx5_ib_cq_buf buf; 513 struct mlx5_db db; 514 515 /* serialize access to the CQ 516 */ 517 spinlock_t lock; 518 519 /* protect resize cq 520 */ 521 struct mutex resize_mutex; 522 struct mlx5_ib_cq_buf *resize_buf; 523 struct ib_umem *resize_umem; 524 int cqe_size; 525 struct list_head list_send_qp; 526 struct list_head list_recv_qp; 527 u32 create_flags; 528 struct list_head wc_list; 529 enum ib_cq_notify_flags notify_flags; 530 struct work_struct notify_work; 531 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 532 }; 533 534 struct mlx5_ib_wc { 535 struct ib_wc wc; 536 struct list_head list; 537 }; 538 539 struct mlx5_ib_srq { 540 struct ib_srq ibsrq; 541 struct mlx5_core_srq msrq; 542 struct mlx5_frag_buf buf; 543 struct mlx5_db db; 544 struct mlx5_frag_buf_ctrl fbc; 545 u64 *wrid; 546 /* protect SRQ hanlding 547 */ 548 spinlock_t lock; 549 int head; 550 int tail; 551 u16 wqe_ctr; 552 struct ib_umem *umem; 553 /* serialize arming a SRQ 554 */ 555 struct mutex mutex; 556 int wq_sig; 557 }; 558 559 struct mlx5_ib_xrcd { 560 struct ib_xrcd ibxrcd; 561 u32 xrcdn; 562 }; 563 564 enum mlx5_ib_mtt_access_flags { 565 MLX5_IB_MTT_READ = (1 << 0), 566 MLX5_IB_MTT_WRITE = (1 << 1), 567 }; 568 569 struct mlx5_user_mmap_entry { 570 struct rdma_user_mmap_entry rdma_entry; 571 u8 mmap_flag; 572 u64 address; 573 u32 page_idx; 574 }; 575 576 struct mlx5_ib_dm { 577 struct ib_dm ibdm; 578 phys_addr_t dev_addr; 579 u32 type; 580 size_t size; 581 union { 582 struct { 583 u32 obj_id; 584 } icm_dm; 585 /* other dm types specific params should be added here */ 586 }; 587 struct mlx5_user_mmap_entry mentry; 588 }; 589 590 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 591 592 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 593 IB_ACCESS_REMOTE_WRITE |\ 594 IB_ACCESS_REMOTE_READ |\ 595 IB_ACCESS_REMOTE_ATOMIC |\ 596 IB_ZERO_BASED) 597 598 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 599 IB_ACCESS_REMOTE_WRITE |\ 600 IB_ACCESS_REMOTE_READ |\ 601 IB_ZERO_BASED) 602 603 #define mlx5_update_odp_stats(mr, counter_name, value) \ 604 atomic64_add(value, &((mr)->odp_stats.counter_name)) 605 606 struct mlx5_ib_mr { 607 struct ib_mr ibmr; 608 void *descs; 609 dma_addr_t desc_map; 610 int ndescs; 611 int data_length; 612 int meta_ndescs; 613 int meta_length; 614 int max_descs; 615 int desc_size; 616 int access_mode; 617 struct mlx5_core_mkey mmkey; 618 struct ib_umem *umem; 619 struct mlx5_shared_mr_info *smr_info; 620 struct list_head list; 621 int order; 622 bool allocated_from_cache; 623 int npages; 624 struct mlx5_ib_dev *dev; 625 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 626 struct mlx5_core_sig_ctx *sig; 627 void *descs_alloc; 628 int access_flags; /* Needed for rereg MR */ 629 630 struct mlx5_ib_mr *parent; 631 /* Needed for IB_MR_TYPE_INTEGRITY */ 632 struct mlx5_ib_mr *pi_mr; 633 struct mlx5_ib_mr *klm_mr; 634 struct mlx5_ib_mr *mtt_mr; 635 u64 data_iova; 636 u64 pi_iova; 637 638 /* For ODP and implicit */ 639 atomic_t num_deferred_work; 640 wait_queue_head_t q_deferred_work; 641 struct xarray implicit_children; 642 union { 643 struct rcu_head rcu; 644 struct list_head elm; 645 struct work_struct work; 646 } odp_destroy; 647 struct ib_odp_counters odp_stats; 648 bool is_odp_implicit; 649 650 struct mlx5_async_work cb_work; 651 }; 652 653 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 654 { 655 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 656 mr->umem->is_odp; 657 } 658 659 struct mlx5_ib_mw { 660 struct ib_mw ibmw; 661 struct mlx5_core_mkey mmkey; 662 int ndescs; 663 }; 664 665 struct mlx5_ib_devx_mr { 666 struct mlx5_core_mkey mmkey; 667 int ndescs; 668 }; 669 670 struct mlx5_ib_umr_context { 671 struct ib_cqe cqe; 672 enum ib_wc_status status; 673 struct completion done; 674 }; 675 676 struct umr_common { 677 struct ib_pd *pd; 678 struct ib_cq *cq; 679 struct ib_qp *qp; 680 /* control access to UMR QP 681 */ 682 struct semaphore sem; 683 }; 684 685 enum { 686 MLX5_FMR_INVALID, 687 MLX5_FMR_VALID, 688 MLX5_FMR_BUSY, 689 }; 690 691 struct mlx5_cache_ent { 692 struct list_head head; 693 /* sync access to the cahce entry 694 */ 695 spinlock_t lock; 696 697 698 char name[4]; 699 u32 order; 700 u32 xlt; 701 u32 access_mode; 702 u32 page; 703 704 u32 size; 705 u32 cur; 706 u32 miss; 707 u32 limit; 708 709 struct mlx5_ib_dev *dev; 710 struct work_struct work; 711 struct delayed_work dwork; 712 int pending; 713 struct completion compl; 714 }; 715 716 struct mlx5_mr_cache { 717 struct workqueue_struct *wq; 718 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 719 int stopped; 720 struct dentry *root; 721 unsigned long last_add; 722 }; 723 724 struct mlx5_ib_gsi_qp; 725 726 struct mlx5_ib_port_resources { 727 struct mlx5_ib_resources *devr; 728 struct mlx5_ib_gsi_qp *gsi; 729 struct work_struct pkey_change_work; 730 }; 731 732 struct mlx5_ib_resources { 733 struct ib_cq *c0; 734 struct ib_xrcd *x0; 735 struct ib_xrcd *x1; 736 struct ib_pd *p0; 737 struct ib_srq *s0; 738 struct ib_srq *s1; 739 struct mlx5_ib_port_resources ports[2]; 740 /* Protects changes to the port resources */ 741 struct mutex mutex; 742 }; 743 744 struct mlx5_ib_counters { 745 const char **names; 746 size_t *offsets; 747 u32 num_q_counters; 748 u32 num_cong_counters; 749 u32 num_ext_ppcnt_counters; 750 u16 set_id; 751 bool set_id_valid; 752 }; 753 754 struct mlx5_ib_multiport_info; 755 756 struct mlx5_ib_multiport { 757 struct mlx5_ib_multiport_info *mpi; 758 /* To be held when accessing the multiport info */ 759 spinlock_t mpi_lock; 760 }; 761 762 struct mlx5_roce { 763 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 764 * netdev pointer 765 */ 766 rwlock_t netdev_lock; 767 struct net_device *netdev; 768 struct notifier_block nb; 769 atomic_t tx_port_affinity; 770 enum ib_port_state last_port_state; 771 struct mlx5_ib_dev *dev; 772 u8 native_port_num; 773 }; 774 775 struct mlx5_ib_port { 776 struct mlx5_ib_counters cnts; 777 struct mlx5_ib_multiport mp; 778 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 779 struct mlx5_roce roce; 780 struct mlx5_eswitch_rep *rep; 781 }; 782 783 struct mlx5_ib_dbg_param { 784 int offset; 785 struct mlx5_ib_dev *dev; 786 struct dentry *dentry; 787 u8 port_num; 788 }; 789 790 enum mlx5_ib_dbg_cc_types { 791 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 792 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 793 MLX5_IB_DBG_CC_RP_TIME_RESET, 794 MLX5_IB_DBG_CC_RP_BYTE_RESET, 795 MLX5_IB_DBG_CC_RP_THRESHOLD, 796 MLX5_IB_DBG_CC_RP_AI_RATE, 797 MLX5_IB_DBG_CC_RP_HAI_RATE, 798 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 799 MLX5_IB_DBG_CC_RP_MIN_RATE, 800 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 801 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 802 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 803 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 804 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 805 MLX5_IB_DBG_CC_RP_GD, 806 MLX5_IB_DBG_CC_NP_CNP_DSCP, 807 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 808 MLX5_IB_DBG_CC_NP_CNP_PRIO, 809 MLX5_IB_DBG_CC_MAX, 810 }; 811 812 struct mlx5_ib_dbg_cc_params { 813 struct dentry *root; 814 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 815 }; 816 817 enum { 818 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 819 }; 820 821 struct mlx5_ib_delay_drop { 822 struct mlx5_ib_dev *dev; 823 struct work_struct delay_drop_work; 824 /* serialize setting of delay drop */ 825 struct mutex lock; 826 u32 timeout; 827 bool activate; 828 atomic_t events_cnt; 829 atomic_t rqs_cnt; 830 struct dentry *dir_debugfs; 831 }; 832 833 enum mlx5_ib_stages { 834 MLX5_IB_STAGE_INIT, 835 MLX5_IB_STAGE_FLOW_DB, 836 MLX5_IB_STAGE_CAPS, 837 MLX5_IB_STAGE_NON_DEFAULT_CB, 838 MLX5_IB_STAGE_ROCE, 839 MLX5_IB_STAGE_SRQ, 840 MLX5_IB_STAGE_DEVICE_RESOURCES, 841 MLX5_IB_STAGE_DEVICE_NOTIFIER, 842 MLX5_IB_STAGE_ODP, 843 MLX5_IB_STAGE_COUNTERS, 844 MLX5_IB_STAGE_CONG_DEBUGFS, 845 MLX5_IB_STAGE_UAR, 846 MLX5_IB_STAGE_BFREG, 847 MLX5_IB_STAGE_PRE_IB_REG_UMR, 848 MLX5_IB_STAGE_WHITELIST_UID, 849 MLX5_IB_STAGE_IB_REG, 850 MLX5_IB_STAGE_POST_IB_REG_UMR, 851 MLX5_IB_STAGE_DELAY_DROP, 852 MLX5_IB_STAGE_CLASS_ATTR, 853 MLX5_IB_STAGE_MAX, 854 }; 855 856 struct mlx5_ib_stage { 857 int (*init)(struct mlx5_ib_dev *dev); 858 void (*cleanup)(struct mlx5_ib_dev *dev); 859 }; 860 861 #define STAGE_CREATE(_stage, _init, _cleanup) \ 862 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 863 864 struct mlx5_ib_profile { 865 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 866 }; 867 868 struct mlx5_ib_multiport_info { 869 struct list_head list; 870 struct mlx5_ib_dev *ibdev; 871 struct mlx5_core_dev *mdev; 872 struct notifier_block mdev_events; 873 struct completion unref_comp; 874 u64 sys_image_guid; 875 u32 mdev_refcnt; 876 bool is_master; 877 bool unaffiliate; 878 }; 879 880 struct mlx5_ib_flow_action { 881 struct ib_flow_action ib_action; 882 union { 883 struct { 884 u64 ib_flags; 885 struct mlx5_accel_esp_xfrm *ctx; 886 } esp_aes_gcm; 887 struct { 888 struct mlx5_ib_dev *dev; 889 u32 sub_type; 890 union { 891 struct mlx5_modify_hdr *modify_hdr; 892 struct mlx5_pkt_reformat *pkt_reformat; 893 }; 894 } flow_action_raw; 895 }; 896 }; 897 898 struct mlx5_dm { 899 struct mlx5_core_dev *dev; 900 /* This lock is used to protect the access to the shared 901 * allocation map when concurrent requests by different 902 * processes are handled. 903 */ 904 spinlock_t lock; 905 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 906 }; 907 908 struct mlx5_read_counters_attr { 909 struct mlx5_fc *hw_cntrs_hndl; 910 u64 *out; 911 u32 flags; 912 }; 913 914 enum mlx5_ib_counters_type { 915 MLX5_IB_COUNTERS_FLOW, 916 }; 917 918 struct mlx5_ib_mcounters { 919 struct ib_counters ibcntrs; 920 enum mlx5_ib_counters_type type; 921 /* number of counters supported for this counters type */ 922 u32 counters_num; 923 struct mlx5_fc *hw_cntrs_hndl; 924 /* read function for this counters type */ 925 int (*read_counters)(struct ib_device *ibdev, 926 struct mlx5_read_counters_attr *read_attr); 927 /* max index set as part of create_flow */ 928 u32 cntrs_max_index; 929 /* number of counters data entries (<description,index> pair) */ 930 u32 ncounters; 931 /* counters data array for descriptions and indexes */ 932 struct mlx5_ib_flow_counters_desc *counters_data; 933 /* protects access to mcounters internal data */ 934 struct mutex mcntrs_mutex; 935 }; 936 937 static inline struct mlx5_ib_mcounters * 938 to_mcounters(struct ib_counters *ibcntrs) 939 { 940 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 941 } 942 943 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 944 bool is_egress, 945 struct mlx5_flow_act *action); 946 struct mlx5_ib_lb_state { 947 /* protect the user_td */ 948 struct mutex mutex; 949 u32 user_td; 950 int qps; 951 bool enabled; 952 }; 953 954 struct mlx5_ib_pf_eq { 955 struct notifier_block irq_nb; 956 struct mlx5_ib_dev *dev; 957 struct mlx5_eq *core; 958 struct work_struct work; 959 spinlock_t lock; /* Pagefaults spinlock */ 960 struct workqueue_struct *wq; 961 mempool_t *pool; 962 }; 963 964 struct mlx5_devx_event_table { 965 struct mlx5_nb devx_nb; 966 /* serialize updating the event_xa */ 967 struct mutex event_xa_lock; 968 struct xarray event_xa; 969 }; 970 971 struct mlx5_var_table { 972 /* serialize updating the bitmap */ 973 struct mutex bitmap_lock; 974 unsigned long *bitmap; 975 u64 hw_start_addr; 976 u32 stride_size; 977 u64 num_var_hw_entries; 978 }; 979 980 struct mlx5_ib_dev { 981 struct ib_device ib_dev; 982 struct mlx5_core_dev *mdev; 983 struct notifier_block mdev_events; 984 int num_ports; 985 /* serialize update of capability mask 986 */ 987 struct mutex cap_mask_mutex; 988 u8 ib_active:1; 989 u8 fill_delay:1; 990 u8 is_rep:1; 991 u8 lag_active:1; 992 u8 wc_support:1; 993 struct umr_common umrc; 994 /* sync used page count stats 995 */ 996 struct mlx5_ib_resources devr; 997 struct mlx5_mr_cache cache; 998 struct timer_list delay_timer; 999 /* Prevents soft lock on massive reg MRs */ 1000 struct mutex slow_path_mutex; 1001 struct ib_odp_caps odp_caps; 1002 u64 odp_max_size; 1003 struct mlx5_ib_pf_eq odp_pf_eq; 1004 1005 /* 1006 * Sleepable RCU that prevents destruction of MRs while they are still 1007 * being used by a page fault handler. 1008 */ 1009 struct srcu_struct odp_srcu; 1010 struct xarray odp_mkeys; 1011 1012 u32 null_mkey; 1013 struct mlx5_ib_flow_db *flow_db; 1014 /* protect resources needed as part of reset flow */ 1015 spinlock_t reset_flow_resource_lock; 1016 struct list_head qp_list; 1017 /* Array with num_ports elements */ 1018 struct mlx5_ib_port *port; 1019 struct mlx5_sq_bfreg bfreg; 1020 struct mlx5_sq_bfreg wc_bfreg; 1021 struct mlx5_sq_bfreg fp_bfreg; 1022 struct mlx5_ib_delay_drop delay_drop; 1023 const struct mlx5_ib_profile *profile; 1024 1025 struct mlx5_ib_lb_state lb; 1026 u8 umr_fence; 1027 struct list_head ib_dev_list; 1028 u64 sys_image_guid; 1029 struct mlx5_dm dm; 1030 u16 devx_whitelist_uid; 1031 struct mlx5_srq_table srq_table; 1032 struct mlx5_async_ctx async_ctx; 1033 struct mlx5_devx_event_table devx_event_table; 1034 struct mlx5_var_table var_table; 1035 1036 struct xarray sig_mrs; 1037 }; 1038 1039 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1040 { 1041 return container_of(mcq, struct mlx5_ib_cq, mcq); 1042 } 1043 1044 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1045 { 1046 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1047 } 1048 1049 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1050 { 1051 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1052 } 1053 1054 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1055 { 1056 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1057 udata, struct mlx5_ib_ucontext, ibucontext); 1058 1059 return to_mdev(context->ibucontext.device); 1060 } 1061 1062 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1063 { 1064 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1065 } 1066 1067 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1068 { 1069 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1070 } 1071 1072 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1073 { 1074 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1075 } 1076 1077 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 1078 { 1079 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 1080 } 1081 1082 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1083 { 1084 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1085 } 1086 1087 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1088 { 1089 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1090 } 1091 1092 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1093 { 1094 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1095 } 1096 1097 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1098 { 1099 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1100 } 1101 1102 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1103 { 1104 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1105 } 1106 1107 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1108 { 1109 return container_of(msrq, struct mlx5_ib_srq, msrq); 1110 } 1111 1112 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1113 { 1114 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1115 } 1116 1117 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1118 { 1119 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1120 } 1121 1122 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1123 { 1124 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1125 } 1126 1127 static inline struct mlx5_ib_flow_action * 1128 to_mflow_act(struct ib_flow_action *ibact) 1129 { 1130 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1131 } 1132 1133 static inline struct mlx5_user_mmap_entry * 1134 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1135 { 1136 return container_of(rdma_entry, 1137 struct mlx5_user_mmap_entry, rdma_entry); 1138 } 1139 1140 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, 1141 struct ib_udata *udata, unsigned long virt, 1142 struct mlx5_db *db); 1143 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1144 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1145 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1146 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1147 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags, 1148 struct ib_udata *udata); 1149 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1150 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags); 1151 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1152 struct ib_udata *udata); 1153 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1154 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1155 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1156 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1157 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1158 const struct ib_recv_wr **bad_wr); 1159 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1160 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1161 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1162 struct ib_qp_init_attr *init_attr, 1163 struct ib_udata *udata); 1164 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1165 int attr_mask, struct ib_udata *udata); 1166 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1167 struct ib_qp_init_attr *qp_init_attr); 1168 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1169 void mlx5_ib_drain_sq(struct ib_qp *qp); 1170 void mlx5_ib_drain_rq(struct ib_qp *qp); 1171 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1172 const struct ib_send_wr **bad_wr); 1173 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1174 const struct ib_recv_wr **bad_wr); 1175 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1176 size_t buflen, size_t *bc); 1177 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1178 size_t buflen, size_t *bc); 1179 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1180 size_t buflen, size_t *bc); 1181 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1182 struct ib_udata *udata); 1183 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1184 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1185 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1186 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1187 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1188 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1189 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1190 u64 virt_addr, int access_flags, 1191 struct ib_udata *udata); 1192 int mlx5_ib_advise_mr(struct ib_pd *pd, 1193 enum ib_uverbs_advise_mr_advice advice, 1194 u32 flags, 1195 struct ib_sge *sg_list, 1196 u32 num_sge, 1197 struct uverbs_attr_bundle *attrs); 1198 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1199 struct ib_udata *udata); 1200 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1201 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1202 int page_shift, int flags); 1203 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1204 struct ib_udata *udata, 1205 int access_flags); 1206 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1207 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr); 1208 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1209 u64 length, u64 virt_addr, int access_flags, 1210 struct ib_pd *pd, struct ib_udata *udata); 1211 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1212 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1213 u32 max_num_sg, struct ib_udata *udata); 1214 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1215 u32 max_num_sg, 1216 u32 max_num_meta_sg); 1217 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1218 unsigned int *sg_offset); 1219 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1220 int data_sg_nents, unsigned int *data_sg_offset, 1221 struct scatterlist *meta_sg, int meta_sg_nents, 1222 unsigned int *meta_sg_offset); 1223 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1224 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1225 const struct ib_mad *in, struct ib_mad *out, 1226 size_t *out_mad_size, u16 *out_mad_pkey_index); 1227 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1228 struct ib_udata *udata); 1229 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1230 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1231 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1232 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1233 struct ib_smp *out_mad); 1234 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1235 __be64 *sys_image_guid); 1236 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1237 u16 *max_pkeys); 1238 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1239 u32 *vendor_id); 1240 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1241 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1242 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1243 u16 *pkey); 1244 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1245 union ib_gid *gid); 1246 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1247 struct ib_port_attr *props); 1248 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1249 struct ib_port_attr *props); 1250 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1251 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1252 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1253 unsigned long max_page_shift, 1254 int *count, int *shift, 1255 int *ncont, int *order); 1256 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1257 int page_shift, size_t offset, size_t num_pages, 1258 __be64 *pas, int access_flags); 1259 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1260 int page_shift, __be64 *pas, int access_flags); 1261 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1262 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1263 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1264 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1265 1266 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1267 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1268 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr); 1269 1270 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1271 struct ib_mr_status *mr_status); 1272 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1273 struct ib_wq_init_attr *init_attr, 1274 struct ib_udata *udata); 1275 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1276 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1277 u32 wq_attr_mask, struct ib_udata *udata); 1278 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1279 struct ib_rwq_ind_table_init_attr *init_attr, 1280 struct ib_udata *udata); 1281 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1282 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1283 struct ib_ucontext *context, 1284 struct ib_dm_alloc_attr *attr, 1285 struct uverbs_attr_bundle *attrs); 1286 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs); 1287 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1288 struct ib_dm_mr_attr *attr, 1289 struct uverbs_attr_bundle *attrs); 1290 1291 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1292 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1293 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1294 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1295 int __init mlx5_ib_odp_init(void); 1296 void mlx5_ib_odp_cleanup(void); 1297 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1298 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1299 struct mlx5_ib_mr *mr, int flags); 1300 1301 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1302 enum ib_uverbs_advise_mr_advice advice, 1303 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1304 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1305 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1306 { 1307 return; 1308 } 1309 1310 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1311 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1312 static inline int mlx5_ib_odp_init(void) { return 0; } 1313 static inline void mlx5_ib_odp_cleanup(void) {} 1314 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1315 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1316 struct mlx5_ib_mr *mr, int flags) {} 1317 1318 static inline int 1319 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1320 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1321 struct ib_sge *sg_list, u32 num_sge) 1322 { 1323 return -EOPNOTSUPP; 1324 } 1325 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1326 1327 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1328 1329 /* Needed for rep profile */ 1330 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1331 const struct mlx5_ib_profile *profile, 1332 int stage); 1333 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1334 const struct mlx5_ib_profile *profile); 1335 1336 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1337 u8 port, struct ifla_vf_info *info); 1338 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1339 u8 port, int state); 1340 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1341 u8 port, struct ifla_vf_stats *stats); 1342 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port, 1343 struct ifla_vf_guid *node_guid, 1344 struct ifla_vf_guid *port_guid); 1345 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1346 u64 guid, int type); 1347 1348 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 1349 const struct ib_gid_attr *attr); 1350 1351 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1352 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1353 1354 /* GSI QP helper functions */ 1355 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1356 struct ib_qp_init_attr *init_attr); 1357 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1358 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1359 int attr_mask); 1360 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1361 int qp_attr_mask, 1362 struct ib_qp_init_attr *qp_init_attr); 1363 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1364 const struct ib_send_wr **bad_wr); 1365 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1366 const struct ib_recv_wr **bad_wr); 1367 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1368 1369 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1370 1371 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1372 int bfregn); 1373 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1374 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1375 u8 ib_port_num, 1376 u8 *native_port_num); 1377 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1378 u8 port_num); 1379 int mlx5_ib_fill_res_entry(struct sk_buff *msg, 1380 struct rdma_restrack_entry *res); 1381 int mlx5_ib_fill_stat_entry(struct sk_buff *msg, 1382 struct rdma_restrack_entry *res); 1383 1384 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1385 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1386 1387 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1388 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user); 1389 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); 1390 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev); 1391 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev); 1392 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1393 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1394 struct mlx5_flow_context *flow_context, 1395 struct mlx5_flow_act *flow_act, u32 counter_id, 1396 void *cmd_in, int inlen, int dest_id, int dest_type); 1397 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1398 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 offset, u32 *counter_id); 1399 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); 1400 #else 1401 static inline int 1402 mlx5_ib_devx_create(struct mlx5_ib_dev *dev, 1403 bool is_user) { return -EOPNOTSUPP; } 1404 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} 1405 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {} 1406 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {} 1407 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1408 int *dest_type) 1409 { 1410 return false; 1411 } 1412 static inline void 1413 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) 1414 { 1415 return; 1416 }; 1417 #endif 1418 static inline void init_query_mad(struct ib_smp *mad) 1419 { 1420 mad->base_version = 1; 1421 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1422 mad->class_version = 1; 1423 mad->method = IB_MGMT_METHOD_GET; 1424 } 1425 1426 static inline u8 convert_access(int acc) 1427 { 1428 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1429 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1430 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1431 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1432 MLX5_PERM_LOCAL_READ; 1433 } 1434 1435 static inline int is_qp1(enum ib_qp_type qp_type) 1436 { 1437 return qp_type == MLX5_IB_QPT_HW_GSI; 1438 } 1439 1440 #define MLX5_MAX_UMR_SHIFT 16 1441 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1442 1443 static inline u32 check_cq_create_flags(u32 flags) 1444 { 1445 /* 1446 * It returns non-zero value for unsupported CQ 1447 * create flags, otherwise it returns zero. 1448 */ 1449 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1450 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1451 } 1452 1453 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1454 u32 *user_index) 1455 { 1456 if (cqe_version) { 1457 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1458 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1459 return -EINVAL; 1460 *user_index = cmd_uidx; 1461 } else { 1462 *user_index = MLX5_IB_DEFAULT_UIDX; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1469 struct mlx5_ib_create_qp *ucmd, 1470 int inlen, 1471 u32 *user_index) 1472 { 1473 u8 cqe_version = ucontext->cqe_version; 1474 1475 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1476 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1477 return 0; 1478 1479 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1480 !!cqe_version)) 1481 return -EINVAL; 1482 1483 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1484 } 1485 1486 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1487 struct mlx5_ib_create_srq *ucmd, 1488 int inlen, 1489 u32 *user_index) 1490 { 1491 u8 cqe_version = ucontext->cqe_version; 1492 1493 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1494 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1495 return 0; 1496 1497 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1498 !!cqe_version)) 1499 return -EINVAL; 1500 1501 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1502 } 1503 1504 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1505 { 1506 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1507 MLX5_UARS_IN_PAGE : 1; 1508 } 1509 1510 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1511 struct mlx5_bfreg_info *bfregi) 1512 { 1513 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1514 } 1515 1516 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1517 void mlx5_ib_put_xlt_emergency_page(void); 1518 1519 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1520 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1521 bool dyn_bfreg); 1522 1523 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter); 1524 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num); 1525 1526 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev, 1527 bool do_modify_atomic, int access_flags) 1528 { 1529 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1530 return false; 1531 1532 if (do_modify_atomic && 1533 MLX5_CAP_GEN(dev->mdev, atomic) && 1534 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1535 return false; 1536 1537 if (access_flags & IB_ACCESS_RELAXED_ORDERING) 1538 return false; 1539 1540 return true; 1541 } 1542 1543 int mlx5_ib_enable_driver(struct ib_device *dev); 1544 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1545 #endif /* MLX5_IB_H */ 1546